Release v1.5.2
diff --git a/.github/ISSUE_TEMPLATE/bug_report.md b/.github/ISSUE_TEMPLATE/bug_report.md
new file mode 100644
index 0000000..f76fec1
--- /dev/null
+++ b/.github/ISSUE_TEMPLATE/bug_report.md
@@ -0,0 +1,35 @@
+---
+name: Bug report
+about: Create a report to help us improve
+title: ''
+labels: ''
+assignees: ''
+
+---
+
+**Caution**
+The Issues are strictly limited for the reporting of problem encountered with the software provided in this project.
+For any other problem related to the STM32 product, the performance, the hardware characteristics and boards, the tools the environment in general, please post a topic in the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus)
+
+**Describe the set-up**
+ * The board (either ST RPN reference or your custom board)
+ * IDE or at least the compiler and its version
+
+**Describe the bug**
+A clear and concise description of what the bug is.
+
+**How To Reproduce**
+1. Indicate the global behavior of your application project
+
+2. The modules that you suspect to be the cause of the problem (Driver, BSP, MW ...)
+
+3. The use case that generates the problem
+
+4. How we can reproduce the problem
+
+
+**Additional context**
+If you have a first analysis or patch correction, thank you to share your proposal.
+
+**Screenshots**
+If applicable, add screenshots to help explain your problem.
diff --git a/.github/ISSUE_TEMPLATE/other-issue.md b/.github/ISSUE_TEMPLATE/other-issue.md
new file mode 100644
index 0000000..5164861
--- /dev/null
+++ b/.github/ISSUE_TEMPLATE/other-issue.md
@@ -0,0 +1,22 @@
+---
+name: 'Other Issue '
+about: Generic issue description
+title: ''
+labels: ''
+assignees: ''
+
+---
+
+**Caution**
+The Issues are strictly limited for the reporting of problem encountered with the software provided in this project.
+For any other problem related to the STM32 product, the performance, the hardware characteristics and boards, the tools the environment in general, please post a topic in the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus)
+
+**Describe the set-up**
+ * The board (either ST RPN reference or your custom board)
+ * IDE or at least the compiler and its version
+
+**Additional context**
+If you have a first analysis or a patch proposal, thank you to share your proposal.
+
+**Screenshots**
+If applicable, add screenshots to help explain your problem.
diff --git a/.github/PULL_REQUEST_TEMPLATE.md b/.github/PULL_REQUEST_TEMPLATE.md
new file mode 100644
index 0000000..721da06
--- /dev/null
+++ b/.github/PULL_REQUEST_TEMPLATE.md
@@ -0,0 +1,8 @@
+## IMPORTANT INFORMATION
+
+### Contributor License Agreement (CLA)
+* The Pull Request feature will be considered by STMicroelectronics only after a **Contributor License Agreement (CLA)** mechanism has been deployed.
+* We are currently working on the set-up of this procedure.
+
+
+
diff --git a/CODE_OF_CONDUCT.md b/CODE_OF_CONDUCT.md
new file mode 100644
index 0000000..0952b04
--- /dev/null
+++ b/CODE_OF_CONDUCT.md
@@ -0,0 +1,76 @@
+# Contributor Covenant Code of Conduct
+
+## Our Pledge
+
+In the interest of fostering an open and welcoming environment, we as
+contributors and maintainers pledge to making participation in our project and
+our community a harassment-free experience for everyone, regardless of age, body
+size, disability, ethnicity, sex characteristics, gender identity and expression,
+level of experience, education, socio-economic status, nationality, personal
+appearance, race, religion, or sexual identity and orientation.
+
+## Our Standards
+
+Examples of behavior that contributes to creating a positive environment
+include:
+
+* Using welcoming and inclusive language
+* Being respectful of differing viewpoints and experiences
+* Gracefully accepting constructive criticism
+* Focusing on what is best for the community
+* Showing empathy towards other community members
+
+Examples of unacceptable behavior by participants include:
+
+* The use of sexualized language or imagery and unwelcome sexual attention or
+ advances
+* Trolling, insulting/derogatory comments, and personal or political attacks
+* Public or private harassment
+* Publishing others' private information, such as a physical or electronic
+ address, without explicit permission
+* Other conduct which could reasonably be considered inappropriate in a
+ professional setting
+
+## Our Responsibilities
+
+Project maintainers are responsible for clarifying the standards of acceptable
+behavior and are expected to take appropriate and fair corrective action in
+response to any instances of unacceptable behavior.
+
+Project maintainers have the right and responsibility to remove, edit, or
+reject comments, commits, code, wiki edits, issues, and other contributions
+that are not aligned to this Code of Conduct, or to ban temporarily or
+permanently any contributor for other behaviors that they deem inappropriate,
+threatening, offensive, or harmful.
+
+## Scope
+
+This Code of Conduct applies both within project spaces and in public spaces
+when an individual is representing the project or its community. Examples of
+representing a project or community include using an official project e-mail
+address, posting via an official social media account, or acting as an appointed
+representative at an online or offline event. Representation of a project may be
+further defined and clarified by project maintainers.
+
+## Enforcement
+
+Instances of abusive, harassing, or otherwise unacceptable behavior may be
+reported by contacting the project team at https://www.st.com/content/st_com/en/contact-us.html. All
+complaints will be reviewed and investigated and will result in a response that
+is deemed necessary and appropriate to the circumstances. The project team is
+obligated to maintain confidentiality with regard to the reporter of an incident.
+Further details of specific enforcement policies may be posted separately.
+
+Project maintainers who do not follow or enforce the Code of Conduct in good
+faith may face temporary or permanent repercussions as determined by other
+members of the project's leadership.
+
+## Attribution
+
+This Code of Conduct is adapted from the [Contributor Covenant][homepage], version 1.4,
+available at https://www.contributor-covenant.org/version/1/4/code-of-conduct.html
+
+[homepage]: https://www.contributor-covenant.org
+
+For answers to common questions about this code of conduct, see
+https://www.contributor-covenant.org/faq
diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md
new file mode 100644
index 0000000..d227cd7
--- /dev/null
+++ b/CONTRIBUTING.md
@@ -0,0 +1,21 @@
+## Contributing guide
+This document serves as a checklist before contributing to this repository.
+It includes links to read up on if topics are unclear to you.
+
+This guide mainly focuses on the proper use of Git.
+
+### 1. Before opening an issue
+To report a bug/request please file an issue in the right repository
+(example for [stm32f3xx_hal_driver](https://github.com/STMicroelectronics/stm32f3xx_hal_driver/issues/new/choose)).
+But check the following boxes before posting an issue:
+
+- [ ] `Make sure you are using the latest commit (major releases are Tagged, but corrections are available as new commits).`
+- [ ] `Make sure your issue is a question/feedback/suggestions RELATED TO the software provided in this repo.` Otherwise, it should be discussed on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus).
+- [ ] `Make sure your issue is not already reported/fixed on GitHub or discussed on a previous Issue.` Please refer to this [dashboard](https://github.com/orgs/STMicroelectronics/projects/2) for the list of issues and pull-requests. Do not forget to browse into the **closed** issues.
+
+
+### 2. Posting the issue
+When you have checked the previous boxes. You will find two templates Issues (Bug Report or Other Issue) available in the **Issues** tab of the repo
+
+### 3. Pull Requests
+For the moment, the Pull Request feature is not deployed. STMicrolectronics is working on a Contributor License Agreement procedure
diff --git a/Inc/Legacy/stm32_hal_legacy.h b/Inc/Legacy/stm32_hal_legacy.h
new file mode 100644
index 0000000..20c6e32
--- /dev/null
+++ b/Inc/Legacy/stm32_hal_legacy.h
@@ -0,0 +1,3371 @@
+/**
+ ******************************************************************************
+ * @file stm32_hal_legacy.h
+ * @author MCD Application Team
+ * @brief This file contains aliases definition for the STM32Cube HAL constants
+ * macros and functions maintained for legacy purpose.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32_HAL_LEGACY
+#define STM32_HAL_LEGACY
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define AES_FLAG_RDERR CRYP_FLAG_RDERR
+#define AES_FLAG_WRERR CRYP_FLAG_WRERR
+#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
+#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
+#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define ADC_RESOLUTION12b ADC_RESOLUTION_12B
+#define ADC_RESOLUTION10b ADC_RESOLUTION_10B
+#define ADC_RESOLUTION8b ADC_RESOLUTION_8B
+#define ADC_RESOLUTION6b ADC_RESOLUTION_6B
+#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
+#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
+#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
+#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV
+#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
+#define REGULAR_GROUP ADC_REGULAR_GROUP
+#define INJECTED_GROUP ADC_INJECTED_GROUP
+#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
+#define AWD_EVENT ADC_AWD_EVENT
+#define AWD1_EVENT ADC_AWD1_EVENT
+#define AWD2_EVENT ADC_AWD2_EVENT
+#define AWD3_EVENT ADC_AWD3_EVENT
+#define OVR_EVENT ADC_OVR_EVENT
+#define JQOVF_EVENT ADC_JQOVF_EVENT
+#define ALL_CHANNELS ADC_ALL_CHANNELS
+#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS
+#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS
+#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
+#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
+#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
+#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
+#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
+#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
+#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
+#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
+#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
+#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
+#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
+#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
+#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
+#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
+#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
+#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
+#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
+#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
+#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5
+
+#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY
+#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY
+#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC
+#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC
+#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL
+#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL
+#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
+/**
+ * @}
+ */
+
+/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
+#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
+#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
+#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
+#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3
+#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4
+#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
+#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
+#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
+#if defined(STM32L0)
+#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */
+#endif
+#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
+#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32L0) || defined(STM32L4)
+#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
+
+#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1
+#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2
+#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3
+#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4
+#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5
+#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6
+
+#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT
+#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT
+#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT
+#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT
+#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1
+#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1
+#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1
+#if defined(STM32L0)
+/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */
+/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */
+/* to the second dedicated IO (only for COMP2). */
+#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2
+#else
+#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2
+#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3
+#endif
+#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4
+#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5
+
+#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW
+#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH
+
+/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */
+/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */
+#if defined(COMP_CSR_LOCK)
+#define COMP_FLAG_LOCK COMP_CSR_LOCK
+#elif defined(COMP_CSR_COMP1LOCK)
+#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK
+#elif defined(COMP_CSR_COMPxLOCK)
+#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK
+#endif
+
+#if defined(STM32L4)
+#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1
+#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1
+#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1
+#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2
+#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2
+#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2
+#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE
+#endif
+
+#if defined(STM32L0)
+#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED
+#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER
+#else
+#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED
+#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED
+#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER
+#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER
+#endif
+
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
+/**
+ * @}
+ */
+
+/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
+#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define DAC1_CHANNEL_1 DAC_CHANNEL_1
+#define DAC1_CHANNEL_2 DAC_CHANNEL_2
+#define DAC2_CHANNEL_1 DAC_CHANNEL_1
+#define DAC_WAVE_NONE 0x00000000U
+#define DAC_WAVE_NOISE DAC_CR_WAVE1_0
+#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1
+#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
+#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
+#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
+#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
+#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
+#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
+#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
+#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
+#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6
+#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
+#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
+#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
+#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
+#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
+#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
+#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6
+
+#define IS_HAL_REMAPDMA IS_DMA_REMAP
+#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
+#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
+
+#if defined(STM32L4)
+
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE
+#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT
+#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT
+#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT
+
+#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
+#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
+#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
+#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
+
+#endif /* STM32L4 */
+
+#if defined(STM32H7)
+
+#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
+#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
+
+#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
+#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
+
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
+#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
+
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0
+#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2
+#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
+#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT
+#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
+#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
+
+#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
+#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
+#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
+#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
+
+#endif /* STM32H7 */
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
+#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
+#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
+#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD
+#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS
+#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES
+#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES
+#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE
+#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE
+#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE
+#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE
+#define OBEX_PCROP OPTIONBYTE_PCROP
+#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG
+#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE
+#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE
+#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE
+#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD
+#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD
+#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE
+#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
+#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD
+#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
+#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
+#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
+#define PAGESIZE FLASH_PAGE_SIZE
+#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
+#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
+#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
+#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1
+#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
+#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
+#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
+#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
+#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
+#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
+#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
+#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA
+#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB
+#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE
+#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
+#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
+#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
+#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
+#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
+#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
+#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS
+#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP
+#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV
+#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR
+#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG
+#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION
+#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA
+#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE
+#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE
+#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS
+#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS
+#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST
+#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR
+#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
+#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
+#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
+#define OB_WDG_SW OB_IWDG_SW
+#define OB_WDG_HW OB_IWDG_HW
+#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET
+#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET
+#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET
+#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET
+#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR
+#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
+#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
+#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
+#if defined(STM32G0)
+#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE
+#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH
+#else
+#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE
+#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#if defined(STM32H7)
+#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE
+#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE
+#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET
+#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET
+#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
+#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
+#endif /* STM32H7 */
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
+#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
+#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
+#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
+/**
+ * @}
+ */
+
+
+/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
+ * @{
+ */
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7)
+#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
+#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
+#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4)
+#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
+#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
+#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
+#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
+#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
+/**
+ * @}
+ */
+
+/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define GET_GPIO_SOURCE GPIO_GET_INDEX
+#define GET_GPIO_INDEX GPIO_GET_INDEX
+
+#if defined(STM32F4)
+#define GPIO_AF12_SDMMC GPIO_AF12_SDIO
+#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO
+#endif
+
+#if defined(STM32F7)
+#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
+#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
+#endif
+
+#if defined(STM32L4)
+#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
+#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
+#endif
+
+#if defined(STM32H7)
+#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1
+#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1
+#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1
+#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2
+#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2
+#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2
+#endif
+
+#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
+#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
+#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
+
+#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4)
+#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
+#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
+#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
+#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
+#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 */
+
+#if defined(STM32L1)
+ #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
+ #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
+ #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
+ #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
+#endif /* STM32L1 */
+
+#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
+ #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
+ #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
+ #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
+#endif /* STM32F0 || STM32F3 || STM32F1 */
+
+#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
+/**
+ * @}
+ */
+
+/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
+
+#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER
+#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER
+#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD
+#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD
+#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
+#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
+#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
+#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE
+#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE
+#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE
+#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE
+#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE
+#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
+#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
+#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
+#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
+#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
+#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX
+#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
+#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define KR_KEY_RELOAD IWDG_KEY_RELOAD
+#define KR_KEY_ENABLE IWDG_KEY_ENABLE
+#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
+#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
+#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
+#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
+#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
+
+#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING
+#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
+#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING
+
+#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
+#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+
+/* The following 3 definition have also been present in a temporary version of lptim.h */
+/* They need to be renamed also to the right name, just in case */
+#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b
+#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b
+#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b
+#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b
+
+#define NAND_AddressTypedef NAND_AddressTypeDef
+
+#define __ARRAY_ADDRESS ARRAY_ADDRESS
+#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE
+#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE
+#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE
+#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define NOR_StatusTypedef HAL_NOR_StatusTypeDef
+#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS
+#define NOR_ONGOING HAL_NOR_STATUS_ONGOING
+#define NOR_ERROR HAL_NOR_STATUS_ERROR
+#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
+
+#define __NOR_WRITE NOR_WRITE
+#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT
+/**
+ * @}
+ */
+
+/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
+#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
+#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
+#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
+
+#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
+#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
+#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
+#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
+
+#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
+#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
+
+#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
+#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
+
+#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
+#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
+
+#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
+
+#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
+#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
+#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
+#if defined(STM32F7)
+ #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+/* Compact Flash-ATA registers description */
+#define CF_DATA ATA_DATA
+#define CF_SECTOR_COUNT ATA_SECTOR_COUNT
+#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
+#define CF_CYLINDER_LOW ATA_CYLINDER_LOW
+#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
+#define CF_CARD_HEAD ATA_CARD_HEAD
+#define CF_STATUS_CMD ATA_STATUS_CMD
+#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
+#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
+
+/* Compact Flash-ATA commands */
+#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
+#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
+#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
+#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
+
+#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
+#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS
+#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING
+#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR
+#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
+/**
+ * @}
+ */
+
+/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define FORMAT_BIN RTC_FORMAT_BIN
+#define FORMAT_BCD RTC_FORMAT_BCD
+
+#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
+#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
+#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
+
+#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
+#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
+#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
+#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
+
+#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
+#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
+
+#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
+#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1
+#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1
+
+#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
+#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
+#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
+#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
+
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
+
+#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
+#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
+
+#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
+#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
+#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE
+#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE
+#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE
+#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE
+#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
+#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
+#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
+#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE
+#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE
+#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
+#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE
+
+#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
+#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE
+
+#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
+#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
+#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
+
+#define TIM_DMABase_CR1 TIM_DMABASE_CR1
+#define TIM_DMABase_CR2 TIM_DMABASE_CR2
+#define TIM_DMABase_SMCR TIM_DMABASE_SMCR
+#define TIM_DMABase_DIER TIM_DMABASE_DIER
+#define TIM_DMABase_SR TIM_DMABASE_SR
+#define TIM_DMABase_EGR TIM_DMABASE_EGR
+#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
+#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
+#define TIM_DMABase_CCER TIM_DMABASE_CCER
+#define TIM_DMABase_CNT TIM_DMABASE_CNT
+#define TIM_DMABase_PSC TIM_DMABASE_PSC
+#define TIM_DMABase_ARR TIM_DMABASE_ARR
+#define TIM_DMABase_RCR TIM_DMABASE_RCR
+#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1
+#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2
+#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3
+#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4
+#define TIM_DMABase_BDTR TIM_DMABASE_BDTR
+#define TIM_DMABase_DCR TIM_DMABASE_DCR
+#define TIM_DMABase_DMAR TIM_DMABASE_DMAR
+#define TIM_DMABase_OR1 TIM_DMABASE_OR1
+#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
+#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5
+#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
+#define TIM_DMABase_OR2 TIM_DMABASE_OR2
+#define TIM_DMABase_OR3 TIM_DMABASE_OR3
+#define TIM_DMABase_OR TIM_DMABASE_OR
+
+#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
+#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
+#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2
+#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3
+#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4
+#define TIM_EventSource_COM TIM_EVENTSOURCE_COM
+#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
+#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK
+#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2
+
+#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER
+#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS
+#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS
+#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS
+#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS
+#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS
+#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS
+#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS
+#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS
+#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
+#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
+#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
+#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
+#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
+#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
+#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
+#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
+#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
+
+#if defined(STM32L0)
+#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO
+#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO
+#endif
+
+#if defined(STM32F3)
+#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING
+#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
+/**
+ * @}
+ */
+
+/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
+#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
+#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
+#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
+
+#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
+#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
+
+#define __DIV_SAMPLING16 UART_DIV_SAMPLING16
+#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
+#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
+#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
+
+#define __DIV_SAMPLING8 UART_DIV_SAMPLING8
+#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
+#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
+#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
+
+#define __DIV_LPUART UART_DIV_LPUART
+
+#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
+#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE
+#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE
+
+#define USARTNACK_ENABLED USART_NACK_ENABLE
+#define USARTNACK_DISABLED USART_NACK_DISABLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define CFR_BASE WWDG_CFR_BASE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define CAN_FilterFIFO0 CAN_FILTER_FIFO0
+#define CAN_FilterFIFO1 CAN_FILTER_FIFO1
+#define CAN_IT_RQCP0 CAN_IT_TME
+#define CAN_IT_RQCP1 CAN_IT_TME
+#define CAN_IT_RQCP2 CAN_IT_TME
+#define INAK_TIMEOUT CAN_TIMEOUT_VALUE
+#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
+#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U)
+#define CAN_TXSTATUS_OK ((uint8_t)0x01U)
+#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U)
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define VLAN_TAG ETH_VLAN_TAG
+#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
+#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
+#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
+#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
+#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
+#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
+#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
+
+#define ETH_MMCCR 0x00000100U
+#define ETH_MMCRIR 0x00000104U
+#define ETH_MMCTIR 0x00000108U
+#define ETH_MMCRIMR 0x0000010CU
+#define ETH_MMCTIMR 0x00000110U
+#define ETH_MMCTGFSCCR 0x0000014CU
+#define ETH_MMCTGFMSCCR 0x00000150U
+#define ETH_MMCTGFCR 0x00000168U
+#define ETH_MMCRFCECR 0x00000194U
+#define ETH_MMCRFAECR 0x00000198U
+#define ETH_MMCRGUFCR 0x000001C4U
+
+#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
+#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
+#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
+#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
+#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
+#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
+#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
+#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */
+#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */
+#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */
+#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
+#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */
+#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
+#if defined(STM32F1)
+#else
+#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */
+#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */
+#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */
+#endif
+#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */
+#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */
+#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */
+#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */
+#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */
+#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */
+#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR
+#define DCMI_IT_OVF DCMI_IT_OVR
+#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI
+#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI
+
+#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop
+#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop
+#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop
+
+/**
+ * @}
+ */
+
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
+ || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888
+#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888
+#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565
+#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555
+#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444
+
+#define CM_ARGB8888 DMA2D_INPUT_ARGB8888
+#define CM_RGB888 DMA2D_INPUT_RGB888
+#define CM_RGB565 DMA2D_INPUT_RGB565
+#define CM_ARGB1555 DMA2D_INPUT_ARGB1555
+#define CM_ARGB4444 DMA2D_INPUT_ARGB4444
+#define CM_L8 DMA2D_INPUT_L8
+#define CM_AL44 DMA2D_INPUT_AL44
+#define CM_AL88 DMA2D_INPUT_AL88
+#define CM_L4 DMA2D_INPUT_L4
+#define CM_A8 DMA2D_INPUT_A8
+#define CM_A4 DMA2D_INPUT_A4
+/**
+ * @}
+ */
+#endif /* STM32L4 || STM32F7*/
+
+/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
+/**
+ * @}
+ */
+
+/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef
+#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef
+#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
+#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
+#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
+#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
+
+/*HASH Algorithm Selection*/
+
+#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
+#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
+#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
+#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
+
+#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
+#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
+
+#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
+#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
+#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
+#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
+#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
+#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
+#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
+#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
+#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
+#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
+#if defined(STM32L0)
+#else
+#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
+#endif
+#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
+#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
+/**
+ * @}
+ */
+
+/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
+#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
+#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
+#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
+#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
+#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
+#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
+
+ /**
+ * @}
+ */
+
+/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
+#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
+#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
+#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
+
+#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
+ /**
+ * @}
+ */
+
+/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
+ * @{
+ */
+#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
+#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
+#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
+#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
+#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
+#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
+#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
+#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
+#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
+#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
+#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
+#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
+#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
+#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
+#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
+#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
+
+#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
+#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
+#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
+#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
+#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
+#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING
+#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING
+
+#define CR_OFFSET_BB PWR_CR_OFFSET_BB
+#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
+#define PMODE_BIT_NUMBER VOS_BIT_NUMBER
+#define CR_PMODE_BB CR_VOS_BB
+
+#define DBP_BitNumber DBP_BIT_NUMBER
+#define PVDE_BitNumber PVDE_BIT_NUMBER
+#define PMODE_BitNumber PMODE_BIT_NUMBER
+#define EWUP_BitNumber EWUP_BIT_NUMBER
+#define FPDS_BitNumber FPDS_BIT_NUMBER
+#define ODEN_BitNumber ODEN_BIT_NUMBER
+#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER
+#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER
+#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER
+#define BRE_BitNumber BRE_BIT_NUMBER
+
+#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
+
+ /**
+ * @}
+ */
+
+/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
+#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
+#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
+#define HAL_TIM_DMAError TIM_DMAError
+#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
+#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
+/**
+ * @}
+ */
+
+/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
+/**
+ * @}
+ */
+
+/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
+#define HAL_LTDC_Relaod HAL_LTDC_Reload
+#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig
+#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros ------------------------------------------------------------*/
+
+/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define AES_IT_CC CRYP_IT_CC
+#define AES_IT_ERR CRYP_IT_ERR
+#define AES_FLAG_CCF CRYP_FLAG_CCF
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE
+#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH
+#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
+#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
+#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
+#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
+#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC
+#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI
+#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
+#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
+#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
+#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
+#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
+#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE
+
+#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
+#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
+#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
+#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
+#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __ADC_ENABLE __HAL_ADC_ENABLE
+#define __ADC_DISABLE __HAL_ADC_DISABLE
+#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS
+#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS
+#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE
+#define __ADC_IS_ENABLED ADC_IS_ENABLE
+#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR
+#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR
+#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING
+#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE
+
+#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
+#define __HAL_ADC_JSQR_RK ADC_JSQR_RK
+#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT
+#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR
+#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
+#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE
+#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS
+#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS
+#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM
+#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT
+#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS
+#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN
+#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ
+#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
+#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET
+#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL
+#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL
+#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET
+#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET
+#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD
+
+#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION
+#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
+#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
+#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER
+#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI
+#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
+#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
+#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER
+#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER
+#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE
+
+#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT
+#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT
+#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL
+#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
+#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET
+#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE
+#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
+#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER
+
+#define __HAL_ADC_SQR1 ADC_SQR1
+#define __HAL_ADC_SMPR1 ADC_SMPR1
+#define __HAL_ADC_SMPR2 ADC_SMPR2
+#define __HAL_ADC_SQR3_RK ADC_SQR3_RK
+#define __HAL_ADC_SQR2_RK ADC_SQR2_RK
+#define __HAL_ADC_SQR1_RK ADC_SQR1_RK
+#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS
+#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
+#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
+#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
+#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
+#define __HAL_ADC_JSQR ADC_JSQR
+
+#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
+#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
+#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF
+#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT
+#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS
+#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN
+#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR
+#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
+#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
+#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
+#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
+#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
+#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
+#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
+#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
+#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
+#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
+#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
+#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
+#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
+#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
+#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
+#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
+#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
+#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
+#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
+
+#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
+#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
+#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
+#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
+#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
+#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
+#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
+#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
+#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
+#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
+#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
+#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
+#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
+#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
+
+
+#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
+#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
+#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
+#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
+#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
+#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
+#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
+#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
+#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
+#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
+#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
+#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
+#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
+#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
+#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
+#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
+#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
+#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
+#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
+#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
+#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
+#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
+#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
+#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#if defined(STM32F3)
+#define COMP_START __HAL_COMP_ENABLE
+#define COMP_STOP __HAL_COMP_DISABLE
+#define COMP_LOCK __HAL_COMP_LOCK
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP6_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F302xE) || defined(STM32F302xC)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP6_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP7_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP7_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP7_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F373xC) ||defined(STM32F378xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP2_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
+# endif
+#else
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP2_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
+#endif
+
+#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
+
+#if defined(STM32L0) || defined(STM32L4)
+/* Note: On these STM32 families, the only argument of this macro */
+/* is COMP_FLAG_LOCK. */
+/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */
+/* argument. */
+#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__))
+#endif
+/**
+ * @}
+ */
+
+#if defined(STM32L0) || defined(STM32L4)
+/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
+#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
+/**
+ * @}
+ */
+#endif
+
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
+ ((WAVE) == DAC_WAVE_NOISE)|| \
+ ((WAVE) == DAC_WAVE_TRIANGLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define IS_WRPAREA IS_OB_WRPAREA
+#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
+#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
+#define IS_TYPEERASE IS_FLASH_TYPEERASE
+#define IS_NBSECTORS IS_FLASH_NBSECTORS
+#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
+#define __HAL_I2C_GENERATE_START I2C_GENERATE_START
+#if defined(STM32F1)
+#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE
+#else
+#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
+#endif /* STM32F1 */
+#define __HAL_I2C_RISE_TIME I2C_RISE_TIME
+#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
+#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
+#define __HAL_I2C_SPEED I2C_SPEED
+#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE
+#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ
+#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS
+#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
+#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ
+#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB
+#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB
+#define __HAL_I2C_FREQRANGE I2C_FREQRANGE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
+#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __IRDA_DISABLE __HAL_IRDA_DISABLE
+#define __IRDA_ENABLE __HAL_IRDA_ENABLE
+
+#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
+#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
+#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
+#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
+
+#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
+
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS
+#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT
+#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
+#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD
+#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX
+#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX
+#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX
+#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX
+#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L
+#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H
+#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM
+#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES
+#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX
+#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT
+#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION
+#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
+#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
+#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE
+#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
+#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
+#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
+#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine
+#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
+#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
+#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
+#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
+#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
+#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
+#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2
+#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
+#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
+
+#if defined (STM32F4)
+#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()
+#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()
+#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
+#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
+#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
+#else
+#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG
+#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
+#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
+#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
+#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
+#endif /* STM32F4 */
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
+ * @{
+ */
+
+#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI
+#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
+
+#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
+#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
+
+#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
+#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
+#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
+#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
+#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
+#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
+#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
+#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
+#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
+#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
+#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
+#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
+#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
+#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
+#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
+#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
+#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
+#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
+#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
+#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
+#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
+#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
+#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
+#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
+#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
+#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
+#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
+#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
+#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
+#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
+#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
+#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
+#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
+#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
+#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
+#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
+#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
+#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
+#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
+#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
+#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
+#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
+#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
+#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
+#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
+#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
+#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
+#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
+#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
+#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
+#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
+#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
+#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
+#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
+#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
+#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
+#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
+#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
+#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
+#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
+#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
+#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
+#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
+#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
+#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
+#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
+#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
+#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
+#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE
+#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE
+#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET
+#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET
+#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE
+#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE
+#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
+#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
+#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
+#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
+#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
+#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
+#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
+#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
+#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
+#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
+#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
+#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
+#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
+#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
+#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
+#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
+#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
+#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
+#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE
+#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE
+#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET
+#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET
+#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
+#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
+#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
+#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
+#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
+#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
+#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
+#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
+#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
+#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
+#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
+#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
+#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
+#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
+#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
+#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
+#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
+#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
+#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
+#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
+#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
+#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
+#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
+#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
+#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
+#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
+#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
+#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
+#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
+#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
+#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
+#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
+#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
+#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
+#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
+#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
+#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET
+#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET
+#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
+#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
+#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
+#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
+#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
+#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
+#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
+#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
+#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
+#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
+#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
+#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
+#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
+#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
+#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
+#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
+#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
+#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
+#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
+#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
+#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
+#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
+#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
+#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
+#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
+#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
+#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
+#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
+#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
+#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
+#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
+#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
+#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
+#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
+#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
+#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
+#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
+#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
+#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
+#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
+#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
+#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
+#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
+#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
+#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
+#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
+#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
+#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
+#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
+#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
+#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
+#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
+#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
+#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
+#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
+#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
+#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
+#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
+#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
+#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
+#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
+#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
+#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
+#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
+#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
+#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
+#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
+#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
+#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
+#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
+#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
+#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
+#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
+#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
+#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
+#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
+#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
+#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
+#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
+#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
+#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
+#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
+#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
+#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
+#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
+#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
+#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
+#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
+#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
+#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
+#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
+#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
+#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
+#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
+#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
+#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
+#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
+#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
+#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
+#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
+#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
+#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
+#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
+#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
+#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
+#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
+#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
+#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
+#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
+#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
+#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
+#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
+#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
+#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
+#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
+#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
+#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
+#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
+#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
+#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
+#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
+#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
+#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
+#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
+
+#if defined(STM32WB)
+#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE
+#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE
+#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET
+#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET
+#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED
+#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED
+#define QSPI_IRQHandler QUADSPI_IRQHandler
+#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */
+
+#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
+#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
+#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
+#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
+#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
+#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
+#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
+#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
+#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
+#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
+#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
+#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
+#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
+#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
+#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
+#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
+#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
+#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
+#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
+#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
+#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
+#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
+#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
+#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
+#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
+#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
+#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
+#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
+#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
+#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
+#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
+#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
+#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
+#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
+#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
+#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
+#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
+#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
+#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
+#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
+#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
+#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
+#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
+#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
+#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
+#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
+#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
+#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
+#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
+#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
+#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
+#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
+#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
+#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
+#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
+#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
+#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
+#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
+#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
+#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
+#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
+#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
+#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
+#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
+#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
+#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
+#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
+#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
+#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
+#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
+#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
+#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
+#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
+#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
+#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
+#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
+#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
+#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
+#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
+#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
+#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
+#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
+#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
+#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
+#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
+#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
+#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
+#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
+#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
+#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
+#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
+#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
+#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
+#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
+#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
+#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
+#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
+#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
+#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
+#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
+#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
+#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
+#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
+#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
+#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
+#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
+#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
+#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
+#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
+#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
+#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
+#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
+#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
+#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
+#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
+#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
+#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
+#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
+#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
+#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
+#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
+#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
+#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
+#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
+#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
+#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
+#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
+#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
+#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
+#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
+#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
+#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
+#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
+#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
+#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
+#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
+#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
+#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
+#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
+#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
+#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
+#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
+#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
+#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
+#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
+#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
+#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
+#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
+#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
+#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
+#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
+#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
+#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
+#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
+#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
+#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
+#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
+#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
+#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
+#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
+#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
+#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
+#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
+#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
+#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
+#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
+#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
+#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
+#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
+#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
+#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
+#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
+#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
+#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
+#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
+#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
+#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
+#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
+#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
+#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
+#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
+#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
+#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
+#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
+#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
+#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
+#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
+#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
+#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
+#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
+#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
+#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
+#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
+#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
+#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
+#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
+#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
+#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
+#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
+#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
+#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
+#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
+#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
+#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
+#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
+#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
+#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
+#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
+#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
+#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
+#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
+#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE
+#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE
+#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
+#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
+#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
+#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
+#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
+#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
+#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
+#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
+#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
+#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
+#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
+#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
+#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET
+#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
+#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
+#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE
+#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE
+#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET
+#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET
+#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
+#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
+#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
+#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
+#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
+#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
+#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
+#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
+#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
+#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
+
+#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
+#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
+#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
+#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
+#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
+#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
+#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
+#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
+#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
+#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
+#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
+#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
+#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
+#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
+#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
+#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
+#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
+#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
+#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
+#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
+#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
+#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
+#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
+#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
+#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
+#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
+#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
+#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
+#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
+#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
+#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
+#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
+#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
+#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
+#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
+#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
+#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
+#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
+#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
+#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
+#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
+#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
+#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
+#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
+#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
+#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
+#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
+#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
+#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
+#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
+#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
+#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
+#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
+#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
+#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
+#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
+#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
+#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
+#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
+#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
+#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
+#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
+#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
+#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
+#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
+#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
+#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
+#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
+#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
+#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
+#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
+#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
+#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
+#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
+#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
+#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
+#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
+#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
+#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
+#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
+#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
+#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
+#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
+#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
+#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
+#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
+#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
+#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
+#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
+#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
+#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
+#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
+#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
+#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
+#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
+#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
+#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
+#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
+#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
+#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
+#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
+#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
+#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
+#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
+#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
+#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
+#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
+#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
+#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
+#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
+#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
+#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
+#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
+#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
+#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
+#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
+#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
+#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
+#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
+#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
+#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
+#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
+#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
+#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
+#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
+#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
+#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
+#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
+#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
+#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
+#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
+#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
+#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
+#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
+#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
+#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
+#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
+#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
+#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
+
+/* alias define maintained for legacy */
+#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
+#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
+
+#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
+#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
+#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
+#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
+#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
+#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
+#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
+#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE
+#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE
+#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE
+#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE
+#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE
+#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE
+#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE
+#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE
+#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE
+#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE
+#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE
+#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE
+#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE
+
+#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
+#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
+#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
+#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
+#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
+#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
+#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
+#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET
+#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET
+#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET
+#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET
+#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET
+#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET
+#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET
+#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET
+#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET
+#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET
+#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET
+#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET
+#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET
+
+#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED
+#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED
+#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
+#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
+#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED
+#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED
+#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED
+#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED
+#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED
+#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED
+#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED
+#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED
+#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED
+#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED
+#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED
+#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED
+#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED
+#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED
+#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED
+#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED
+#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED
+#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED
+#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED
+#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED
+#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED
+#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED
+#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED
+#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED
+#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED
+#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED
+#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED
+#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED
+#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED
+#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED
+#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED
+#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED
+#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED
+#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED
+#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED
+#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED
+#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED
+#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED
+#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED
+#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED
+#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED
+#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED
+#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED
+#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED
+#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED
+#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED
+#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED
+#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED
+#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED
+#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED
+#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED
+#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED
+#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED
+#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED
+#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED
+#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED
+#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED
+#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED
+#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED
+#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED
+#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED
+#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED
+#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED
+#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED
+#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED
+#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED
+#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED
+#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED
+#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED
+#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED
+#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED
+#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED
+#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED
+#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED
+#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED
+#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED
+#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED
+#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED
+#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED
+#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED
+#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED
+#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED
+#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED
+#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED
+#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED
+#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED
+#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED
+#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED
+#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED
+#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED
+#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED
+#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED
+#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED
+#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED
+#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED
+#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED
+#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED
+#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED
+#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED
+#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED
+#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED
+#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED
+#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED
+#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED
+#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED
+#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED
+#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED
+#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED
+#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED
+#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED
+#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
+#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
+
+#if defined(STM32F4)
+#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
+#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
+#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
+#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
+#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED
+#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED
+#define Sdmmc1ClockSelection SdioClockSelection
+#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO
+#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48
+#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK
+#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG
+#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE
+#endif
+
+#if defined(STM32F7) || defined(STM32L4)
+#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET
+#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
+#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE
+#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED
+#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED
+#define SdioClockSelection Sdmmc1ClockSelection
+#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1
+#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG
+#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
+#endif
+
+#if defined(STM32F7)
+#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48
+#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
+#endif
+
+#if defined(STM32H7)
+#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET()
+#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
+
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET()
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()
+#endif
+
+#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
+#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
+
+#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
+
+#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
+#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
+#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK
+#define IS_RCC_HCLK_DIV IS_RCC_PCLK
+#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK
+
+#define RCC_IT_HSI14 RCC_IT_HSI14RDY
+
+#define RCC_IT_CSSLSE RCC_IT_LSECSS
+#define RCC_IT_CSSHSE RCC_IT_CSS
+
+#define RCC_PLLMUL_3 RCC_PLL_MUL3
+#define RCC_PLLMUL_4 RCC_PLL_MUL4
+#define RCC_PLLMUL_6 RCC_PLL_MUL6
+#define RCC_PLLMUL_8 RCC_PLL_MUL8
+#define RCC_PLLMUL_12 RCC_PLL_MUL12
+#define RCC_PLLMUL_16 RCC_PLL_MUL16
+#define RCC_PLLMUL_24 RCC_PLL_MUL24
+#define RCC_PLLMUL_32 RCC_PLL_MUL32
+#define RCC_PLLMUL_48 RCC_PLL_MUL48
+
+#define RCC_PLLDIV_2 RCC_PLL_DIV2
+#define RCC_PLLDIV_3 RCC_PLL_DIV3
+#define RCC_PLLDIV_4 RCC_PLL_DIV4
+
+#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
+#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
+#define RCC_MCO_NODIV RCC_MCODIV_1
+#define RCC_MCO_DIV1 RCC_MCODIV_1
+#define RCC_MCO_DIV2 RCC_MCODIV_2
+#define RCC_MCO_DIV4 RCC_MCODIV_4
+#define RCC_MCO_DIV8 RCC_MCODIV_8
+#define RCC_MCO_DIV16 RCC_MCODIV_16
+#define RCC_MCO_DIV32 RCC_MCODIV_32
+#define RCC_MCO_DIV64 RCC_MCODIV_64
+#define RCC_MCO_DIV128 RCC_MCODIV_128
+#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK
+#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI
+#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE
+#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK
+#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI
+#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14
+#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48
+#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE
+#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK
+#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
+#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
+
+#if defined(STM32L4)
+#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
+#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4)
+#else
+#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
+#endif
+
+#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
+#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
+#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI
+#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL
+#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL
+#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5
+#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2
+#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3
+
+#define HSION_BitNumber RCC_HSION_BIT_NUMBER
+#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER
+#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER
+#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER
+#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER
+#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
+#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER
+#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
+#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER
+#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
+#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
+#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
+#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER
+#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
+#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER
+#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER
+#define LSION_BitNumber RCC_LSION_BIT_NUMBER
+#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER
+#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER
+#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER
+#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER
+#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
+#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
+#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER
+#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER
+#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
+#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
+#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
+#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
+#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS
+#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE
+#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE
+
+#define CR_HSION_BB RCC_CR_HSION_BB
+#define CR_CSSON_BB RCC_CR_CSSON_BB
+#define CR_PLLON_BB RCC_CR_PLLON_BB
+#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
+#define CR_MSION_BB RCC_CR_MSION_BB
+#define CSR_LSION_BB RCC_CSR_LSION_BB
+#define CSR_LSEON_BB RCC_CSR_LSEON_BB
+#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB
+#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB
+#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB
+#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
+#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
+#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
+#define CR_HSEON_BB RCC_CR_HSEON_BB
+#define CSR_RMVF_BB RCC_CSR_RMVF_BB
+#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
+#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
+
+#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
+#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
+#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
+#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
+#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE
+
+#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT
+
+#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN
+#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF
+
+#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48
+#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ
+#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP
+#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ
+#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE
+#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48
+
+#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE
+#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE
+#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED
+#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED
+#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET
+#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET
+#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
+#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
+#define DfsdmClockSelection Dfsdm1ClockSelection
+#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
+#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
+#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
+#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
+#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
+#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
+#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
+
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2
+#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
+#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32WL)
+#else
+#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
+#endif
+#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
+#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
+
+#if defined (STM32F1)
+#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
+
+#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()
+
+#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()
+
+#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()
+
+#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
+#else
+#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
+#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
+#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
+#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
+#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
+#endif /* STM32F1 */
+
+#define IS_ALARM IS_RTC_ALARM
+#define IS_ALARM_MASK IS_RTC_ALARM_MASK
+#define IS_TAMPER IS_RTC_TAMPER
+#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
+#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
+#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
+#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
+#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
+#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE
+#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ
+#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
+#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER
+#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK
+#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER
+
+#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
+#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
+#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
+
+#if defined(STM32F4) || defined(STM32F2)
+#define SD_SDMMC_DISABLED SD_SDIO_DISABLED
+#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
+#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
+#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION
+#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND
+#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT
+#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED
+#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE
+#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE
+#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE
+#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
+#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT
+#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT
+#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG
+#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG
+#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT
+#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT
+#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS
+#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT
+#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND
+/* alias CMSIS */
+#define SDMMC1_IRQn SDIO_IRQn
+#define SDMMC1_IRQHandler SDIO_IRQHandler
+#endif
+
+#if defined(STM32F7) || defined(STM32L4)
+#define SD_SDIO_DISABLED SD_SDMMC_DISABLED
+#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY
+#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED
+#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION
+#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND
+#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT
+#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED
+#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE
+#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE
+#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE
+#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE
+#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT
+#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT
+#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG
+#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
+#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
+#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
+#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
+#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
+#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
+/* alias CMSIS for compatibilities */
+#define SDIO_IRQn SDMMC1_IRQn
+#define SDIO_IRQHandler SDMMC1_IRQHandler
+#endif
+
+#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2)
+#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef
+#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef
+#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef
+#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
+#endif
+
+#if defined(STM32H7)
+#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
+#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
+#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
+#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback
+#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback
+#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback
+#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback
+#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback
+#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT
+#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT
+#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE
+#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE
+#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE
+#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
+
+#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
+#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
+
+#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1
+#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2
+#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START
+#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH
+#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR
+#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE
+#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE
+#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_SPI_1LINE_TX SPI_1LINE_TX
+#define __HAL_SPI_1LINE_RX SPI_1LINE_RX
+#define __HAL_SPI_RESET_CRC SPI_RESET_CRC
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
+#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
+#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
+#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION
+
+#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
+
+#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
+#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT
+#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT
+#define __USART_ENABLE __HAL_USART_ENABLE
+#define __USART_DISABLE __HAL_USART_DISABLE
+
+#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
+#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE
+
+#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
+#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
+#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
+#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE
+
+#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
+#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
+#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
+#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE
+
+#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+
+#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
+
+#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
+
+#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup
+#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup
+
+#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
+#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE
+#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
+
+#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
+#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
+
+#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
+
+#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
+#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
+#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
+#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER
+#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD
+#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD
+#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
+#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
+#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER
+#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
+#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
+#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
+
+#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
+/**
+ * @}
+ */
+
+/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
+#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
+#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
+#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
+
+#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
+#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
+#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_LTDC_LAYER LTDC_LAYER
+#if defined(STM32F7)
+#else
+#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE
+#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE
+#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
+#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
+#define SAI_STREOMODE SAI_STEREOMODE
+#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
+#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
+#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
+#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
+#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
+#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
+#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
+#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1
+#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#if defined(STM32H7)
+#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow
+#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT
+#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32_HAL_LEGACY */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Inc/Legacy/stm32f3xx_hal_can_legacy.h b/Inc/Legacy/stm32f3xx_hal_can_legacy.h
new file mode 100644
index 0000000..bcc92b9
--- /dev/null
+++ b/Inc/Legacy/stm32f3xx_hal_can_legacy.h
@@ -0,0 +1,819 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_can.h
+ * @author MCD Application Team
+ * @brief Header file of CAN HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_CAN_H
+#define __STM32F3xx_CAN_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F302x8) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CAN
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CAN_Exported_Types CAN Exported Types
+ * @{
+ */
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */
+ HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */
+ HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_RX0 = 0x22U, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_RX1 = 0x32U, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_TX_RX0 = 0x42U, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_TX_RX1 = 0x52U, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_RX0_RX1 = 0x62U, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_TX_RX0_RX1 = 0x72U, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< CAN in Timeout state */
+ HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */
+
+}HAL_CAN_StateTypeDef;
+
+/**
+ * @brief CAN init structure definition
+ */
+typedef struct
+{
+ uint32_t Prescaler; /*!< Specifies the length of a time quantum.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */
+
+ uint32_t Mode; /*!< Specifies the CAN operating mode.
+ This parameter can be a value of @ref CAN_operating_mode */
+
+ uint32_t SJW; /*!< Specifies the maximum number of time quanta
+ the CAN hardware is allowed to lengthen or
+ shorten a bit to perform resynchronization.
+ This parameter can be a value of @ref CAN_synchronisation_jump_width */
+
+ uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1.
+ This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
+
+ uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
+ This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
+
+ uint32_t TTCM; /*!< Enable or disable the time triggered communication mode.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t ABOM; /*!< Enable or disable the automatic bus-off management.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t RFLM; /*!< Enable or disable the Receive FIFO Locked mode.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority.
+ This parameter can be set to ENABLE or DISABLE. */
+}CAN_InitTypeDef;
+
+/**
+ * @brief CAN filter configuration structure definition
+ */
+typedef struct
+{
+ uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
+ configuration, first one for a 16-bit configuration).
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
+ uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
+ configuration, second one for a 16-bit configuration).
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
+ uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
+ according to the mode (MSBs for a 32-bit configuration,
+ first one for a 16-bit configuration).
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
+ uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
+ according to the mode (LSBs for a 32-bit configuration,
+ second one for a 16-bit configuration).
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
+ uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter.
+ This parameter can be a value of @ref CAN_filter_FIFO */
+
+ uint32_t FilterNumber; /*!< Specifies the filter which will be initialized.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 27. */
+
+ uint32_t FilterMode; /*!< Specifies the filter mode to be initialized.
+ This parameter can be a value of @ref CAN_filter_mode */
+
+ uint32_t FilterScale; /*!< Specifies the filter scale.
+ This parameter can be a value of @ref CAN_filter_scale */
+
+ uint32_t FilterActivation; /*!< Enable or disable the filter.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t BankNumber; /*!< Select the start slave bank filter
+ F3 devices don't support CAN2 interface (Slave). Therefore this parameter
+ is meaningless but it has been kept for compatibility accross STM32 families */
+
+}CAN_FilterConfTypeDef;
+
+/**
+ * @brief CAN Tx message structure definition
+ */
+typedef struct
+{
+ uint32_t StdId; /*!< Specifies the standard identifier.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
+
+ uint32_t ExtId; /*!< Specifies the extended identifier.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
+
+ uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
+ This parameter can be a value of @ref CAN_identifier_type */
+
+ uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
+ This parameter can be a value of @ref CAN_remote_transmission_request */
+
+ uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
+
+ uint8_t Data[8]; /*!< Contains the data to be transmitted.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
+
+}CanTxMsgTypeDef;
+
+/**
+ * @brief CAN Rx message structure definition
+ */
+typedef struct
+{
+ uint32_t StdId; /*!< Specifies the standard identifier.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
+
+ uint32_t ExtId; /*!< Specifies the extended identifier.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
+
+ uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received.
+ This parameter can be a value of @ref CAN_identifier_type */
+
+ uint32_t RTR; /*!< Specifies the type of frame for the received message.
+ This parameter can be a value of @ref CAN_remote_transmission_request */
+
+ uint32_t DLC; /*!< Specifies the length of the frame that will be received.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
+
+ uint8_t Data[8]; /*!< Contains the data to be received.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
+
+ uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
+
+ uint32_t FIFONumber; /*!< Specifies the receive FIFO number.
+ This parameter can be CAN_FIFO0 or CAN_FIFO1 */
+
+}CanRxMsgTypeDef;
+
+/**
+ * @brief CAN handle Structure definition
+ */
+typedef struct
+{
+ CAN_TypeDef *Instance; /*!< Register base address */
+
+ CAN_InitTypeDef Init; /*!< CAN required parameters */
+
+ CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */
+
+ CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure for RX FIFO0 msg */
+
+ CanRxMsgTypeDef* pRx1Msg; /*!< Pointer to reception structure for RX FIFO1 msg */
+
+ HAL_LockTypeDef Lock; /*!< CAN locking object */
+
+ __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
+
+ __IO uint32_t ErrorCode; /*!< CAN Error code
+ This parameter can be a value of @ref CAN_Error_Code */
+
+}CAN_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CAN_Exported_Constants CAN Exported Constants
+ * @{
+ */
+
+/** @defgroup CAN_Error_Code CAN Error Code
+ * @{
+ */
+#define HAL_CAN_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_CAN_ERROR_EWG (0x00000001U) /*!< EWG error */
+#define HAL_CAN_ERROR_EPV (0x00000002U) /*!< EPV error */
+#define HAL_CAN_ERROR_BOF (0x00000004U) /*!< BOF error */
+#define HAL_CAN_ERROR_STF (0x00000008U) /*!< Stuff error */
+#define HAL_CAN_ERROR_FOR (0x00000010U) /*!< Form error */
+#define HAL_CAN_ERROR_ACK (0x00000020U) /*!< Acknowledgment error */
+#define HAL_CAN_ERROR_BR (0x00000040U) /*!< Bit recessive */
+#define HAL_CAN_ERROR_BD (0x00000080U) /*!< LEC dominant */
+#define HAL_CAN_ERROR_CRC (0x00000100U) /*!< LEC transfer error */
+#define HAL_CAN_ERROR_FOV0 (0x00000200U) /*!< FIFO0 overrun error */
+#define HAL_CAN_ERROR_FOV1 (0x00000400U) /*!< FIFO1 overrun error */
+#define HAL_CAN_ERROR_TXFAIL (0x00000800U) /*!< Transmit failure */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_InitStatus CAN InitStatus
+ * @{
+ */
+#define CAN_INITSTATUS_FAILED (0x00000000U) /*!< CAN initialization failed */
+#define CAN_INITSTATUS_SUCCESS (0x00000001U) /*!< CAN initialization OK */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_operating_mode CAN Operating Mode
+ * @{
+ */
+#define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */
+#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
+#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
+#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
+/**
+ * @}
+ */
+
+
+/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width
+ * @{
+ */
+#define CAN_SJW_1TQ (0x00000000U) /*!< 1 time quantum */
+#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */
+#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */
+#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1
+ * @{
+ */
+#define CAN_BS1_1TQ (0x00000000U) /*!< 1 time quantum */
+#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */
+#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */
+#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */
+#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */
+#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */
+#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */
+#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */
+#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */
+#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */
+#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */
+#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */
+#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */
+#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */
+#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */
+#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2
+ * @{
+ */
+#define CAN_BS2_1TQ (0x00000000U) /*!< 1 time quantum */
+#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */
+#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */
+#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */
+#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */
+#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */
+#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */
+#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_mode CAN Filter Mode
+ * @{
+ */
+#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00U) /*!< Identifier mask mode */
+#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01U) /*!< Identifier list mode */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_scale CAN Filter Scale
+ * @{
+ */
+#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00U) /*!< Two 16-bit filters */
+#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01U) /*!< One 32-bit filter */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_FIFO CAN Filter FIFO
+ * @{
+ */
+#define CAN_FILTER_FIFO0 ((uint8_t)0x00U) /*!< Filter FIFO 0 assignment for filter x */
+#define CAN_FILTER_FIFO1 ((uint8_t)0x01U) /*!< Filter FIFO 1 assignment for filter x */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_identifier_type CAN Identifier Type
+ * @{
+ */
+#define CAN_ID_STD (0x00000000U) /*!< Standard Id */
+#define CAN_ID_EXT (0x00000004U) /*!< Extended Id */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
+ * @{
+ */
+#define CAN_RTR_DATA (0x00000000U) /*!< Data frame */
+#define CAN_RTR_REMOTE (0x00000002U) /*!< Remote frame */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number
+ * @{
+ */
+#define CAN_FIFO0 ((uint8_t)0x00U) /*!< CAN FIFO 0 used to receive */
+#define CAN_FIFO1 ((uint8_t)0x01U) /*!< CAN FIFO 1 used to receive */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_flags CAN Flags
+ * @{
+ */
+/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
+ and CAN_ClearFlag() functions. */
+/* If the flag is 0x1XXXXXXX, it means that it can only be used with
+ CAN_GetFlagStatus() function. */
+
+/* Transmit Flags */
+#define CAN_FLAG_RQCP0 (0x00000500U) /*!< Request MailBox0 flag */
+#define CAN_FLAG_RQCP1 (0x00000508U) /*!< Request MailBox1 flag */
+#define CAN_FLAG_RQCP2 (0x00000510U) /*!< Request MailBox2 flag */
+#define CAN_FLAG_TXOK0 (0x00000501U) /*!< Transmission OK MailBox0 flag */
+#define CAN_FLAG_TXOK1 (0x00000509U) /*!< Transmission OK MailBox1 flag */
+#define CAN_FLAG_TXOK2 (0x00000511U) /*!< Transmission OK MailBox2 flag */
+#define CAN_FLAG_TME0 (0x0000051AU) /*!< Transmit mailbox 0 empty flag */
+#define CAN_FLAG_TME1 (0x0000051BU) /*!< Transmit mailbox 0 empty flag */
+#define CAN_FLAG_TME2 (0x0000051CU) /*!< Transmit mailbox 0 empty flag */
+
+/* Receive Flags */
+#define CAN_FLAG_FF0 (0x00000203U) /*!< FIFO 0 Full flag */
+#define CAN_FLAG_FOV0 (0x00000204U) /*!< FIFO 0 Overrun flag */
+
+#define CAN_FLAG_FF1 (0x00000403U) /*!< FIFO 1 Full flag */
+#define CAN_FLAG_FOV1 (0x00000404U) /*!< FIFO 1 Overrun flag */
+
+/* Operating Mode Flags */
+#define CAN_FLAG_INAK (0x00000100U) /*!< Initialization acknowledge flag */
+#define CAN_FLAG_SLAK (0x00000101U) /*!< Sleep acknowledge flag */
+#define CAN_FLAG_ERRI (0x00000102U) /*!< Error flag */
+#define CAN_FLAG_WKU (0x00000103U) /*!< Wake up flag */
+#define CAN_FLAG_SLAKI (0x00000104U) /*!< Sleep acknowledge flag */
+/* @note When SLAK interrupt is disabled (SLKIE=0U), no polling on SLAKI is possible.
+ In this case the SLAK bit can be polled.*/
+
+/* Error Flags */
+#define CAN_FLAG_EWG (0x00000300U) /*!< Error warning flag */
+#define CAN_FLAG_EPV (0x00000301U) /*!< Error passive flag */
+#define CAN_FLAG_BOF (0x00000302U) /*!< Bus-Off flag */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup CAN_interrupts CAN Interrupts
+ * @{
+ */
+#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */
+
+/* Receive Interrupts */
+#define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */
+#define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */
+#define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */
+#define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */
+#define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */
+#define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */
+
+/* Operating Mode Interrupts */
+#define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */
+#define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */
+
+/* Error Interrupts */
+#define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */
+#define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */
+#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */
+#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
+#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Mailboxes CAN Mailboxes
+* @{
+*/
+/* Mailboxes definition */
+#define CAN_TXMAILBOX_0 ((uint8_t)0x00U)
+#define CAN_TXMAILBOX_1 ((uint8_t)0x01U)
+#define CAN_TXMAILBOX_2 ((uint8_t)0x02U)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup CAN_Exported_Macros CAN Exported Macros
+ * @{
+ */
+
+/** @brief Reset CAN handle state
+ * @param __HANDLE__ CAN handle.
+ * @retval None
+ */
+#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
+
+/**
+ * @brief Enable the specified CAN interrupts.
+ * @param __HANDLE__ CAN handle.
+ * @param __INTERRUPT__ CAN Interrupt
+ * @retval None
+ */
+#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the specified CAN interrupts.
+ * @param __HANDLE__ CAN handle.
+ * @param __INTERRUPT__ CAN Interrupt
+ * @retval None
+ */
+#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
+
+/**
+ * @brief Return the number of pending received messages.
+ * @param __HANDLE__ CAN handle.
+ * @param __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+ * @retval The number of pending message.
+ */
+#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
+((uint8_t)((__HANDLE__)->Instance->RF0R&0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&0x03U)))
+
+/** @brief Check whether the specified CAN flag is set or not.
+ * @param __HANDLE__ specifies the CAN Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg CAN_TSR_RQCP0: Request MailBox0 Flag
+ * @arg CAN_TSR_RQCP1: Request MailBox1 Flag
+ * @arg CAN_TSR_RQCP2: Request MailBox2 Flag
+ * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
+ * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
+ * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
+ * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
+ * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
+ * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
+ * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
+ * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
+ * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
+ * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
+ * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
+ * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
+ * @arg CAN_FLAG_WKU: Wake up Flag
+ * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
+ * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
+ * @arg CAN_FLAG_EWG: Error Warning Flag
+ * @arg CAN_FLAG_EPV: Error Passive Flag
+ * @arg CAN_FLAG_BOF: Bus-Off Flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
+((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))))
+
+/** @brief Clear the specified CAN pending flag.
+ * @param __HANDLE__ specifies the CAN Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg CAN_TSR_RQCP0: Request MailBox0 Flag
+ * @arg CAN_TSR_RQCP1: Request MailBox1 Flag
+ * @arg CAN_TSR_RQCP2: Request MailBox2 Flag
+ * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
+ * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
+ * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
+ * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
+ * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
+ * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
+ * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
+ * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
+ * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
+ * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
+ * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
+ * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
+ * @arg CAN_FLAG_WKU: Wake up Flag
+ * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
+ * @arg CAN_FLAG_EWG: Error Warning Flag
+ * @arg CAN_FLAG_EPV: Error Passive Flag
+ * @arg CAN_FLAG_BOF: Bus-Off Flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)
+
+
+/** @brief Check if the specified CAN interrupt source is enabled or disabled.
+ * @param __HANDLE__ specifies the CAN Handle.
+ * @param __INTERRUPT__ specifies the CAN interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
+ * @arg CAN_IT_FMP0: FIFO0 message pending interrupt enablev
+ * @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/**
+ * @brief Check the transmission status of a CAN Frame.
+ * @param __HANDLE__ CAN handle.
+ * @param __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission.
+ * @retval The new status of transmission (TRUE or FALSE).
+ */
+#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
+(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TME0)) :\
+ ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TME1)) :\
+ ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TME2)))
+
+ /**
+ * @brief Release the specified receive FIFO.
+ * @param __HANDLE__ CAN handle.
+ * @param __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+ * @retval None
+ */
+#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
+((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1))
+
+/**
+ * @brief Cancel a transmit request.
+ * @param __HANDLE__ specifies the CAN Handle.
+ * @param __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission.
+ * @retval None
+ */
+#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
+(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ0) :\
+ ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ1) :\
+ ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ2))
+
+/**
+ * @brief Enable or disables the DBG Freeze for CAN.
+ * @param __HANDLE__ specifies the CAN Handle.
+ * @param __NEWSTATE__ new state of the CAN peripheral.
+ * This parameter can be: ENABLE (CAN reception/transmission is frozen
+ * during debug. Reception FIFOs can still be accessed/controlled normally)
+ * or DISABLE (CAN is working during debug).
+ * @retval None
+ */
+#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
+((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CAN_Exported_Functions CAN Exported Functions
+ * @{
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
+HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
+HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
+void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
+void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group2 Input and Output operation functions
+ * @brief I/O operation functions
+ * @{
+ */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
+HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
+void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
+void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
+void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
+void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
+ * @brief CAN Peripheral State functions
+ * @{
+ */
+/* Peripheral State and Error functions ***************************************/
+uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
+HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup CAN_Private_Types CAN Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup CAN_Private_Variables CAN Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup CAN_Private_Constants CAN Private Constants
+ * @{
+ */
+#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04U) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
+#define CAN_FLAG_MASK (0x000000FFU)
+/**
+ * @}
+ */
+
+/* Private Macros -----------------------------------------------------------*/
+/** @defgroup CAN_Private_Macros CAN Private Macros
+ * @{
+ */
+
+#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
+ ((MODE) == CAN_MODE_LOOPBACK)|| \
+ ((MODE) == CAN_MODE_SILENT) || \
+ ((MODE) == CAN_MODE_SILENT_LOOPBACK))
+
+#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
+ ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
+
+#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
+
+#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
+
+#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))
+
+#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27U)
+
+#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
+ ((MODE) == CAN_FILTERMODE_IDLIST))
+
+#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
+ ((SCALE) == CAN_FILTERSCALE_32BIT))
+
+#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
+ ((FIFO) == CAN_FILTER_FIFO1))
+
+#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U)
+
+#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02U))
+#define IS_CAN_STDID(STDID) ((STDID) <= (0x7FFU))
+#define IS_CAN_EXTID(EXTID) ((EXTID) <= (0x1FFFFFFFU))
+#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08U))
+
+#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
+ ((IDTYPE) == CAN_ID_EXT))
+
+#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
+
+#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
+
+#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\
+ ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\
+ ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\
+ ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
+ ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
+ ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
+ ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
+
+#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\
+ ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\
+ ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\
+ ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
+ ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
+ ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
+
+/**
+ * @}
+ */
+/* End of private macros -----------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F302x8 || */
+ /* STM32F373xC || STM32F378xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_CAN_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32_assert_template.h b/Inc/stm32_assert_template.h
new file mode 100644
index 0000000..d71e0c3
--- /dev/null
+++ b/Inc/stm32_assert_template.h
@@ -0,0 +1,73 @@
+/**
+ ******************************************************************************
+ * @file stm32_assert.h
+ * @author MCD Application Team
+ * @brief STM32 assert template file.
+ * This file should be copied to the application folder and renamed
+ * to stm32_assert.h.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_ASSERT_H
+#define __STM32_ASSERT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Includes ------------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval None
+ */
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((char *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+ void assert_failed(char* file, uint32_t line);
+#else
+ #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32_ASSERT_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_hal.h b/Inc/stm32f3xx_hal.h
new file mode 100644
index 0000000..fb2215d
--- /dev/null
+++ b/Inc/stm32f3xx_hal.h
@@ -0,0 +1,961 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal.h
+ * @author MCD Application Team
+ * @brief This file contains all the functions prototypes for the HAL
+ * module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_H
+#define __STM32F3xx_HAL_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_conf.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup HAL
+ * @{
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup HAL_Private_Macros
+ * @{
+ */
+#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
+ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
+ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
+ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
+/**
+ * @}
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup HAL_Exported_Constants HAL Exported Constants
+ * @{
+ */
+
+/** @defgroup HAL_TICK_FREQ Tick Frequency
+ * @{
+ */
+typedef enum
+{
+ HAL_TICK_FREQ_10HZ = 100U,
+ HAL_TICK_FREQ_100HZ = 10U,
+ HAL_TICK_FREQ_1KHZ = 1U,
+ HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
+} HAL_TickFreqTypeDef;
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/** @defgroup HAL_Exported_Constants HAL Exported Constants
+ * @{
+ */
+/** @defgroup SYSCFG_BitAddress_AliasRegion SYSCFG registers bit address in the alias region
+ * @brief SYSCFG registers bit address in the alias region
+ * @{
+ */
+/* ------------ SYSCFG registers bit address in the alias region -------------*/
+#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)
+/* --- CFGR2 Register ---*/
+/* Alias word address of BYP_ADDR_PAR bit */
+#define CFGR2_OFFSET (SYSCFG_OFFSET + 0x18U)
+#define BYPADDRPAR_BitNumber 0x04U
+#define CFGR2_BYPADDRPAR_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32U) + (BYPADDRPAR_BitNumber * 4U))
+/**
+ * @}
+ */
+
+#if defined(SYSCFG_CFGR1_DMA_RMP)
+/** @defgroup HAL_DMA_Remapping HAL DMA Remapping
+ * Elements values convention: 0xXXYYYYYY
+ * - YYYYYY : Position in the register
+ * - XX : Register index
+ * - 00: CFGR1 register in SYSCFG
+ * - 01: CFGR3 register in SYSCFG (not available on STM32F373xC/STM32F378xx devices)
+ * @{
+ */
+#define HAL_REMAPDMA_ADC24_DMA2_CH34 (0x00000100U) /*!< ADC24 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices)
+ 1: Remap (ADC24 DMA requests mapped on DMA2 channels 3 and 4) */
+#define HAL_REMAPDMA_TIM16_DMA1_CH6 (0x00000800U) /*!< TIM16 DMA request remap
+ 1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA1 channel 6) */
+#define HAL_REMAPDMA_TIM17_DMA1_CH7 (0x00001000U) /*!< TIM17 DMA request remap
+ 1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA1 channel 7) */
+#define HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3 (0x00002000U) /*!< TIM6 and DAC channel1 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices)
+ 1: Remap (TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3) */
+#define HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4 (0x00004000U) /*!< TIM7 and DAC channel2 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices)
+ 1: Remap (TIM7_UP and DAC_CH2 DMA requests mapped on DMA1 channel 4) */
+#define HAL_REMAPDMA_DAC2_CH1_DMA1_CH5 (0x00008000U) /*!< DAC2 channel1 DMA remap (STM32F303x4/6/8 devices only)
+ 1: Remap (DAC2_CH1 DMA requests mapped on DMA1 channel 5) */
+#define HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5 (0x00008000U) /*!< DAC2 channel1 DMA remap (STM32F303x4/6/8 devices only)
+ 1: Remap (DAC2_CH1 DMA requests mapped on DMA1 channel 5) */
+#if defined(SYSCFG_CFGR3_DMA_RMP)
+#if !defined(HAL_REMAP_CFGR3_MASK)
+#define HAL_REMAP_CFGR3_MASK (0x01000000U)
+#endif
+
+#define HAL_REMAPDMA_SPI1_RX_DMA1_CH2 (0x01000003U) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only)
+ 11: Map on DMA1 channel 2 */
+#define HAL_REMAPDMA_SPI1_RX_DMA1_CH4 (0x01000001U) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only)
+ 01: Map on DMA1 channel 4 */
+#define HAL_REMAPDMA_SPI1_RX_DMA1_CH6 (0x01000002U) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only)
+ 10: Map on DMA1 channel 6 */
+#define HAL_REMAPDMA_SPI1_TX_DMA1_CH3 (0x0100000CU) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only)
+ 11: Map on DMA1 channel 3 */
+#define HAL_REMAPDMA_SPI1_TX_DMA1_CH5 (0x01000004U) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only)
+ 01: Map on DMA1 channel 5 */
+#define HAL_REMAPDMA_SPI1_TX_DMA1_CH7 (0x01000008U) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only)
+ 10: Map on DMA1 channel 7 */
+#define HAL_REMAPDMA_I2C1_RX_DMA1_CH7 (0x01000030U) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only)
+ 11: Map on DMA1 channel 7 */
+#define HAL_REMAPDMA_I2C1_RX_DMA1_CH3 (0x01000010U) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only)
+ 01: Map on DMA1 channel 3 */
+#define HAL_REMAPDMA_I2C1_RX_DMA1_CH5 (0x01000020U) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only)
+ 10: Map on DMA1 channel 5 */
+#define HAL_REMAPDMA_I2C1_TX_DMA1_CH6 (0x010000C0U) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only)
+ 11: Map on DMA1 channel 6 */
+#define HAL_REMAPDMA_I2C1_TX_DMA1_CH2 (0x01000040U) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only)
+ 01: Map on DMA1 channel 2 */
+#define HAL_REMAPDMA_I2C1_TX_DMA1_CH4 (0x01000080U) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only)
+ 10: Map on DMA1 channel 4 */
+#define HAL_REMAPDMA_ADC2_DMA1_CH2 (0x01000100U) /*!< ADC2 DMA remap
+ x0: No remap (ADC2 on DMA2)
+ 10: Map on DMA1 channel 2 */
+#define HAL_REMAPDMA_ADC2_DMA1_CH4 (0x01000300U) /*!< ADC2 DMA remap
+ 11: Map on DMA1 channel 4 */
+#endif /* SYSCFG_CFGR3_DMA_RMP */
+
+#if defined(SYSCFG_CFGR3_DMA_RMP)
+#define IS_DMA_REMAP(RMP) ((((RMP) & HAL_REMAPDMA_ADC24_DMA2_CH34) == HAL_REMAPDMA_ADC24_DMA2_CH34) || \
+ (((RMP) & HAL_REMAPDMA_TIM16_DMA1_CH6) == HAL_REMAPDMA_TIM16_DMA1_CH6) || \
+ (((RMP) & HAL_REMAPDMA_TIM17_DMA1_CH7) == HAL_REMAPDMA_TIM17_DMA1_CH7) || \
+ (((RMP) & HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) == HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) || \
+ (((RMP) & HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) == HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) || \
+ (((RMP) & HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) || \
+ (((RMP) & HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) || \
+ (((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH2) == HAL_REMAPDMA_SPI1_RX_DMA1_CH2) || \
+ (((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH4) == HAL_REMAPDMA_SPI1_RX_DMA1_CH4) || \
+ (((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH6) == HAL_REMAPDMA_SPI1_RX_DMA1_CH6) || \
+ (((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH3) == HAL_REMAPDMA_SPI1_TX_DMA1_CH3) || \
+ (((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH5) == HAL_REMAPDMA_SPI1_TX_DMA1_CH5) || \
+ (((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH7) == HAL_REMAPDMA_SPI1_TX_DMA1_CH7) || \
+ (((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH7) == HAL_REMAPDMA_I2C1_RX_DMA1_CH7) || \
+ (((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH3) == HAL_REMAPDMA_I2C1_RX_DMA1_CH3) || \
+ (((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH5) == HAL_REMAPDMA_I2C1_RX_DMA1_CH5) || \
+ (((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH6) == HAL_REMAPDMA_I2C1_TX_DMA1_CH6) || \
+ (((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH2) == HAL_REMAPDMA_I2C1_TX_DMA1_CH2) || \
+ (((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH4) == HAL_REMAPDMA_I2C1_TX_DMA1_CH4) || \
+ (((RMP) & HAL_REMAPDMA_ADC2_DMA1_CH2) == HAL_REMAPDMA_ADC2_DMA1_CH2) || \
+ (((RMP) & HAL_REMAPDMA_ADC2_DMA1_CH4) == HAL_REMAPDMA_ADC2_DMA1_CH4))
+#else
+#define IS_DMA_REMAP(RMP) ((((RMP) & HAL_REMAPDMA_ADC24_DMA2_CH34) == HAL_REMAPDMA_ADC24_DMA2_CH34) || \
+ (((RMP) & HAL_REMAPDMA_TIM16_DMA1_CH6) == HAL_REMAPDMA_TIM16_DMA1_CH6) || \
+ (((RMP) & HAL_REMAPDMA_TIM17_DMA1_CH7) == HAL_REMAPDMA_TIM17_DMA1_CH7) || \
+ (((RMP) & HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) == HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) || \
+ (((RMP) & HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) == HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) || \
+ (((RMP) & HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) || \
+ (((RMP) & HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5))
+#endif /* SYSCFG_CFGR3_DMA_RMP && SYSCFG_CFGR1_DMA_RMP*/
+/**
+ * @}
+ */
+#endif /* SYSCFG_CFGR1_DMA_RMP */
+
+/** @defgroup HAL_Trigger_Remapping HAL Trigger Remapping
+ * Elements values convention: 0xXXYYYYYY
+ * - YYYYYY : Position in the register
+ * - XX : Register index
+ * - 00: CFGR1 register in SYSCFG
+ * - 01: CFGR3 register in SYSCFG
+ * @{
+ */
+#define HAL_REMAPTRIGGER_DAC1_TRIG (0x00000080U) /*!< DAC trigger remap (when TSEL = 001 on STM32F303xB/C and STM32F358xx devices)
+ 0: No remap (DAC trigger is TIM8_TRGO)
+ 1: Remap (DAC trigger is TIM3_TRGO) */
+#define HAL_REMAPTRIGGER_TIM1_ITR3 (0x00000040U) /*!< TIM1 ITR3 trigger remap
+ 0: No remap
+ 1: Remap (TIM1_TRG3 = TIM17_OC) */
+#if defined(SYSCFG_CFGR3_TRIGGER_RMP)
+#if !defined(HAL_REMAP_CFGR3_MASK)
+#define HAL_REMAP_CFGR3_MASK (0x01000000U)
+#endif
+#define HAL_REMAPTRIGGER_DAC1_TRIG3 (0x01010000U) /*!< DAC1_CH1 / DAC1_CH2 Trigger remap
+ 0: Remap (DAC trigger is TIM15_TRGO)
+ 1: Remap (DAC trigger is HRTIM1_DAC1_TRIG1) */
+#define HAL_REMAPTRIGGER_DAC1_TRIG5 (0x01020000U) /*!< DAC1_CH1 / DAC1_CH2 Trigger remap
+ 0: No remap
+ 1: Remap (DAC trigger is HRTIM1_DAC1_TRIG2) */
+#define IS_HAL_REMAPTRIGGER(RMP) ((((RMP) & HAL_REMAPTRIGGER_DAC1) == HAL_REMAPTRIGGER_DAC1) || \
+ (((RMP) & HAL_REMAPTRIGGER_TIM1_ITR3) == HAL_REMAPTRIGGER_TIM1_ITR3) || \
+ (((RMP) & HAL_REMAPTRIGGER_DAC1_TRIG3) == HAL_REMAPTRIGGER_DAC1_TRIG3) || \
+ (((RMP) & HAL_REMAPTRIGGER_DAC1_TRIG5) == HAL_REMAPTRIGGER_DAC1_TRIG5))
+#else
+#define IS_HAL_REMAPTRIGGER(RMP) ((((RMP) & HAL_REMAPTRIGGER_DAC1) == HAL_REMAPTRIGGER_DAC1) || \
+ (((RMP) & HAL_REMAPTRIGGER_TIM1_ITR3) == HAL_REMAPTRIGGER_TIM1_ITR3))
+#endif /* SYSCFG_CFGR3_TRIGGER_RMP */
+/**
+ * @}
+ */
+
+#if defined (STM32F302xE)
+/** @defgroup HAL_ADC_Trigger_Remapping HAL ADC Trigger Remapping
+ * @{
+ */
+#define HAL_REMAPADCTRIGGER_ADC12_EXT2 SYSCFG_CFGR4_ADC12_EXT2_RMP /*!< Input trigger of ADC12 regular channel EXT2
+ 0: No remap (TIM1_CC3)
+ 1: Remap (TIM20_TRGO) */
+#define HAL_REMAPADCTRIGGER_ADC12_EXT3 SYSCFG_CFGR4_ADC12_EXT3_RMP /*!< Input trigger of ADC12 regular channel EXT3
+ 0: No remap (TIM2_CC2)
+ 1: Remap (TIM20_TRGO2) */
+#define HAL_REMAPADCTRIGGER_ADC12_EXT5 SYSCFG_CFGR4_ADC12_EXT5_RMP /*!< Input trigger of ADC12 regular channel EXT5
+ 0: No remap (TIM4_CC4)
+ 1: Remap (TIM20_CC1) */
+#define HAL_REMAPADCTRIGGER_ADC12_EXT13 SYSCFG_CFGR4_ADC12_EXT13_RMP /*!< Input trigger of ADC12 regular channel EXT13
+ 0: No remap (TIM6_TRGO)
+ 1: Remap (TIM20_CC2) */
+#define HAL_REMAPADCTRIGGER_ADC12_EXT15 SYSCFG_CFGR4_ADC12_EXT15_RMP /*!< Input trigger of ADC12 regular channel EXT15
+ 0: No remap (TIM3_CC4)
+ 1: Remap (TIM20_CC3) */
+#define HAL_REMAPADCTRIGGER_ADC12_JEXT3 SYSCFG_CFGR4_ADC12_JEXT3_RMP /*!< Input trigger of ADC12 injected channel JEXT3
+ 0: No remap (TIM2_CC1)
+ 1: Remap (TIM20_TRGO) */
+#define HAL_REMAPADCTRIGGER_ADC12_JEXT6 SYSCFG_CFGR4_ADC12_JEXT6_RMP /*!< Input trigger of ADC12 injected channel JEXT6
+ 0: No remap (EXTI line 15)
+ 1: Remap (TIM20_TRGO2) */
+#define HAL_REMAPADCTRIGGER_ADC12_JEXT13 SYSCFG_CFGR4_ADC12_JEXT13_RMP /*!< Input trigger of ADC12 injected channel JEXT13
+ 0: No remap (TIM3_CC1)
+ 1: Remap (TIM20_CC4) */
+
+#define IS_HAL_REMAPADCTRIGGER(RMP) ((((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT2) == HAL_REMAPADCTRIGGER_ADC12_EXT2) || \
+ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT3) == HAL_REMAPADCTRIGGER_ADC12_EXT3) || \
+ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT5) == HAL_REMAPADCTRIGGER_ADC12_EXT5) || \
+ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT13) == HAL_REMAPADCTRIGGER_ADC12_EXT13) || \
+ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT15) == HAL_REMAPADCTRIGGER_ADC12_EXT15) || \
+ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT3) == HAL_REMAPADCTRIGGER_ADC12_JEXT3) || \
+ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT6) == HAL_REMAPADCTRIGGER_ADC12_JEXT6) || \
+ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT13) == HAL_REMAPADCTRIGGER_ADC12_JEXT13))
+/**
+ * @}
+ */
+#endif /* STM32F302xE */
+
+#if defined (STM32F303xE) || defined (STM32F398xx)
+/** @defgroup HAL_ADC_Trigger_Remapping HAL ADC Trigger Remapping
+ * @{
+ */
+#define HAL_REMAPADCTRIGGER_ADC12_EXT2 SYSCFG_CFGR4_ADC12_EXT2_RMP /*!< Input trigger of ADC12 regular channel EXT2
+ 0: No remap (TIM1_CC3)
+ 1: Remap (TIM20_TRGO) */
+#define HAL_REMAPADCTRIGGER_ADC12_EXT3 SYSCFG_CFGR4_ADC12_EXT3_RMP /*!< Input trigger of ADC12 regular channel EXT3
+ 0: No remap (TIM2_CC2)
+ 1: Remap (TIM20_TRGO2) */
+#define HAL_REMAPADCTRIGGER_ADC12_EXT5 SYSCFG_CFGR4_ADC12_EXT5_RMP /*!< Input trigger of ADC12 regular channel EXT5
+ 0: No remap (TIM4_CC4)
+ 1: Remap (TIM20_CC1) */
+#define HAL_REMAPADCTRIGGER_ADC12_EXT13 SYSCFG_CFGR4_ADC12_EXT13_RMP /*!< Input trigger of ADC12 regular channel EXT13
+ 0: No remap (TIM6_TRGO)
+ 1: Remap (TIM20_CC2) */
+#define HAL_REMAPADCTRIGGER_ADC12_EXT15 SYSCFG_CFGR4_ADC12_EXT15_RMP /*!< Input trigger of ADC12 regular channel EXT15
+ 0: No remap (TIM3_CC4)
+ 1: Remap (TIM20_CC3) */
+#define HAL_REMAPADCTRIGGER_ADC12_JEXT3 SYSCFG_CFGR4_ADC12_JEXT3_RMP /*!< Input trigger of ADC12 injected channel JEXT3
+ 0: No remap (TIM2_CC1)
+ 1: Remap (TIM20_TRGO) */
+#define HAL_REMAPADCTRIGGER_ADC12_JEXT6 SYSCFG_CFGR4_ADC12_JEXT6_RMP /*!< Input trigger of ADC12 injected channel JEXT6
+ 0: No remap (EXTI line 15)
+ 1: Remap (TIM20_TRGO2) */
+#define HAL_REMAPADCTRIGGER_ADC12_JEXT13 SYSCFG_CFGR4_ADC12_JEXT13_RMP /*!< Input trigger of ADC12 injected channel JEXT13
+ 0: No remap (TIM3_CC1)
+ 1: Remap (TIM20_CC4) */
+#define HAL_REMAPADCTRIGGER_ADC34_EXT5 SYSCFG_CFGR4_ADC34_EXT5_RMP /*!< Input trigger of ADC34 regular channel EXT5
+ 0: No remap (EXTI line 2)
+ 1: Remap (TIM20_TRGO) */
+#define HAL_REMAPADCTRIGGER_ADC34_EXT6 SYSCFG_CFGR4_ADC34_EXT6_RMP /*!< Input trigger of ADC34 regular channel EXT6
+ 0: No remap (TIM4_CC1)
+ 1: Remap (TIM20_TRGO2) */
+#define HAL_REMAPADCTRIGGER_ADC34_EXT15 SYSCFG_CFGR4_ADC34_EXT15_RMP /*!< Input trigger of ADC34 regular channel EXT15
+ 0: No remap (TIM2_CC1)
+ 1: Remap (TIM20_CC1) */
+#define HAL_REMAPADCTRIGGER_ADC34_JEXT5 SYSCFG_CFGR4_ADC34_JEXT5_RMP /*!< Input trigger of ADC34 injected channel JEXT5
+ 0: No remap (TIM4_CC3)
+ 1: Remap (TIM20_TRGO) */
+#define HAL_REMAPADCTRIGGER_ADC34_JEXT11 SYSCFG_CFGR4_ADC34_JEXT11_RMP /*!< Input trigger of ADC34 injected channel JEXT11
+ 0: No remap (TIM1_CC3)
+ 1: Remap (TIM20_TRGO2) */
+#define HAL_REMAPADCTRIGGER_ADC34_JEXT14 SYSCFG_CFGR4_ADC34_JEXT14_RMP /*!< Input trigger of ADC34 injected channel JEXT14
+ 0: No remap (TIM7_TRGO)
+ 1: Remap (TIM20_CC2) */
+
+#define IS_HAL_REMAPADCTRIGGER(RMP) ((((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT2) == HAL_REMAPADCTRIGGER_ADC12_EXT2) || \
+ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT3) == HAL_REMAPADCTRIGGER_ADC12_EXT3) || \
+ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT5) == HAL_REMAPADCTRIGGER_ADC12_EXT5) || \
+ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT13) == HAL_REMAPADCTRIGGER_ADC12_EXT13) || \
+ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT15) == HAL_REMAPADCTRIGGER_ADC12_EXT15) || \
+ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT3) == HAL_REMAPADCTRIGGER_ADC12_JEXT3) || \
+ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT6) == HAL_REMAPADCTRIGGER_ADC12_JEXT6) || \
+ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT13) == HAL_REMAPADCTRIGGER_ADC12_JEXT13) || \
+ (((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT5) == HAL_REMAPADCTRIGGER_ADC34_EXT5) || \
+ (((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT6) == HAL_REMAPADCTRIGGER_ADC34_EXT6) || \
+ (((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT15) == HAL_REMAPADCTRIGGER_ADC34_EXT15) || \
+ (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT5) == HAL_REMAPADCTRIGGER_ADC34_JEXT5) || \
+ (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT11) == HAL_REMAPADCTRIGGER_ADC34_JEXT11) || \
+ (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT14) == HAL_REMAPADCTRIGGER_ADC34_JEXT14))
+/**
+ * @}
+ */
+#endif /* STM32F303xE || STM32F398xx */
+
+/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
+ * @{
+ */
+
+/** @brief Fast-mode Plus driving capability on a specific GPIO
+ */
+#if defined(SYSCFG_CFGR1_I2C_PB6_FMP)
+#define SYSCFG_FASTMODEPLUS_PB6 ((uint32_t)SYSCFG_CFGR1_I2C_PB6_FMP) /*!< Enable Fast-mode Plus on PB6 */
+#endif /* SYSCFG_CFGR1_I2C_PB6_FMP */
+
+#if defined(SYSCFG_CFGR1_I2C_PB7_FMP)
+#define SYSCFG_FASTMODEPLUS_PB7 ((uint32_t)SYSCFG_CFGR1_I2C_PB7_FMP) /*!< Enable Fast-mode Plus on PB7 */
+#endif /* SYSCFG_CFGR1_I2C_PB7_FMP */
+
+#if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
+#define SYSCFG_FASTMODEPLUS_PB8 ((uint32_t)SYSCFG_CFGR1_I2C_PB8_FMP) /*!< Enable Fast-mode Plus on PB8 */
+#endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
+
+#if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
+#define SYSCFG_FASTMODEPLUS_PB9 ((uint32_t)SYSCFG_CFGR1_I2C_PB9_FMP) /*!< Enable Fast-mode Plus on PB9 */
+#endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
+/**
+ * @}
+ */
+
+#if defined(SYSCFG_RCR_PAGE0)
+/* CCM-SRAM defined */
+/** @defgroup HAL_Page_Write_Protection HAL CCM RAM page write protection
+ * @{
+ */
+#define HAL_SYSCFG_WP_PAGE0 (SYSCFG_RCR_PAGE0) /*!< ICODE SRAM Write protection page 0 */
+#define HAL_SYSCFG_WP_PAGE1 (SYSCFG_RCR_PAGE1) /*!< ICODE SRAM Write protection page 1 */
+#define HAL_SYSCFG_WP_PAGE2 (SYSCFG_RCR_PAGE2) /*!< ICODE SRAM Write protection page 2 */
+#define HAL_SYSCFG_WP_PAGE3 (SYSCFG_RCR_PAGE3) /*!< ICODE SRAM Write protection page 3 */
+#if defined(SYSCFG_RCR_PAGE4)
+/* More than 4KB CCM-SRAM defined */
+#define HAL_SYSCFG_WP_PAGE4 (SYSCFG_RCR_PAGE4) /*!< ICODE SRAM Write protection page 4 */
+#define HAL_SYSCFG_WP_PAGE5 (SYSCFG_RCR_PAGE5) /*!< ICODE SRAM Write protection page 5 */
+#define HAL_SYSCFG_WP_PAGE6 (SYSCFG_RCR_PAGE6) /*!< ICODE SRAM Write protection page 6 */
+#define HAL_SYSCFG_WP_PAGE7 (SYSCFG_RCR_PAGE7) /*!< ICODE SRAM Write protection page 7 */
+#endif /* SYSCFG_RCR_PAGE4 */
+#if defined(SYSCFG_RCR_PAGE8)
+#define HAL_SYSCFG_WP_PAGE8 (SYSCFG_RCR_PAGE8) /*!< ICODE SRAM Write protection page 8 */
+#define HAL_SYSCFG_WP_PAGE9 (SYSCFG_RCR_PAGE9) /*!< ICODE SRAM Write protection page 9 */
+#define HAL_SYSCFG_WP_PAGE10 (SYSCFG_RCR_PAGE10) /*!< ICODE SRAM Write protection page 10 */
+#define HAL_SYSCFG_WP_PAGE11 (SYSCFG_RCR_PAGE11) /*!< ICODE SRAM Write protection page 11 */
+#define HAL_SYSCFG_WP_PAGE12 (SYSCFG_RCR_PAGE12) /*!< ICODE SRAM Write protection page 12 */
+#define HAL_SYSCFG_WP_PAGE13 (SYSCFG_RCR_PAGE13) /*!< ICODE SRAM Write protection page 13 */
+#define HAL_SYSCFG_WP_PAGE14 (SYSCFG_RCR_PAGE14) /*!< ICODE SRAM Write protection page 14 */
+#define HAL_SYSCFG_WP_PAGE15 (SYSCFG_RCR_PAGE15) /*!< ICODE SRAM Write protection page 15 */
+#endif /* SYSCFG_RCR_PAGE8 */
+
+#if defined(SYSCFG_RCR_PAGE8)
+#define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFU))
+#elif defined(SYSCFG_RCR_PAGE4)
+#define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0x00FFU))
+#else
+#define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0x000FU))
+#endif /* SYSCFG_RCR_PAGE8 */
+/**
+ * @}
+ */
+#endif /* SYSCFG_RCR_PAGE0 */
+
+/** @defgroup HAL_SYSCFG_Interrupts HAL SYSCFG Interrupts
+ * @{
+ */
+#define HAL_SYSCFG_IT_FPU_IOC (SYSCFG_CFGR1_FPU_IE_0) /*!< Floating Point Unit Invalid operation Interrupt */
+#define HAL_SYSCFG_IT_FPU_DZC (SYSCFG_CFGR1_FPU_IE_1) /*!< Floating Point Unit Divide-by-zero Interrupt */
+#define HAL_SYSCFG_IT_FPU_UFC (SYSCFG_CFGR1_FPU_IE_2) /*!< Floating Point Unit Underflow Interrupt */
+#define HAL_SYSCFG_IT_FPU_OFC (SYSCFG_CFGR1_FPU_IE_3) /*!< Floating Point Unit Overflow Interrupt */
+#define HAL_SYSCFG_IT_FPU_IDC (SYSCFG_CFGR1_FPU_IE_4) /*!< Floating Point Unit Input denormal Interrupt */
+#define HAL_SYSCFG_IT_FPU_IXC (SYSCFG_CFGR1_FPU_IE_5) /*!< Floating Point Unit Inexact Interrupt */
+
+#define IS_HAL_SYSCFG_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_0) == SYSCFG_CFGR1_FPU_IE_0) || \
+ (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_1) == SYSCFG_CFGR1_FPU_IE_1) || \
+ (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_2) == SYSCFG_CFGR1_FPU_IE_2) || \
+ (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_3) == SYSCFG_CFGR1_FPU_IE_3) || \
+ (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_4) == SYSCFG_CFGR1_FPU_IE_4) || \
+ (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_5) == SYSCFG_CFGR1_FPU_IE_5))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup HAL_Exported_Macros HAL Exported Macros
+ * @{
+ */
+
+/** @defgroup Debug_MCU_APB1_Freeze Freeze/Unfreeze APB1 Peripherals in Debug mode
+ * @{
+ */
+#if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
+#endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */
+
+#if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
+#endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */
+
+#if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM4() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))
+#endif /* DBGMCU_APB1_FZ_DBG_TIM4_STOP */
+
+#if defined(DBGMCU_APB1_FZ_DBG_TIM5_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM5() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))
+#endif /* DBGMCU_APB1_FZ_DBG_TIM5_STOP */
+
+#if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
+#endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */
+
+#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
+#endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */
+
+#if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM12() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))
+#endif /* DBGMCU_APB1_FZ_DBG_TIM12_STOP */
+
+#if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM13() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))
+#endif /* DBGMCU_APB1_FZ_DBG_TIM13_STOP */
+
+#if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
+#endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */
+
+#if defined(DBGMCU_APB1_FZ_DBG_TIM18_STOP)
+#define __HAL_FREEZE_TIM18_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM18_STOP))
+#define __HAL_UNFREEZE_TIM18_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM18_STOP))
+#endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */
+
+#if defined(DBGMCU_APB1_FZ_DBG_RTC_STOP)
+#define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
+#define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
+#endif /* DBGMCU_APB1_FZ_DBG_RTC_STOP */
+
+#if defined(DBGMCU_APB1_FZ_DBG_WWDG_STOP)
+#define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
+#define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
+#endif /* DBGMCU_APB1_FZ_DBG_WWDG_STOP */
+
+#if defined(DBGMCU_APB1_FZ_DBG_IWDG_STOP)
+#define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
+#define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
+#endif /* DBGMCU_APB1_FZ_DBG_IWDG_STOP */
+
+#if defined(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
+#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
+#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
+#endif /* DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT */
+
+#if defined(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
+#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
+#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
+#endif /* DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT */
+
+#if defined(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)
+#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
+#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
+#endif /* DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT */
+
+#if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP)
+#define __HAL_FREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN_STOP))
+#define __HAL_UNFREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN_STOP))
+#endif /* DBGMCU_APB1_FZ_DBG_CAN_STOP */
+/**
+ * @}
+ */
+
+/** @defgroup Debug_MCU_APB2_Freeze Freeze/Unfreeze APB2 Peripherals in Debug mode
+ * @{
+ */
+#if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
+#endif /* DBGMCU_APB2_FZ_DBG_TIM1_STOP */
+
+#if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM8() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))
+#endif /* DBGMCU_APB2_FZ_DBG_TIM8_STOP */
+
+#if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM15() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM15_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM15() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM15_STOP))
+#endif /* DBGMCU_APB2_FZ_DBG_TIM15_STOP */
+
+#if defined(DBGMCU_APB2_FZ_DBG_TIM16_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM16() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM16_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM16() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM16_STOP))
+#endif /* DBGMCU_APB2_FZ_DBG_TIM16_STOP */
+
+#if defined(DBGMCU_APB2_FZ_DBG_TIM17_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM17() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM17_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM17() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM17_STOP))
+#endif /* DBGMCU_APB2_FZ_DBG_TIM17_STOP */
+
+#if defined(DBGMCU_APB2_FZ_DBG_TIM19_STOP)
+#define __HAL_FREEZE_TIM19_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM19_STOP))
+#define __HAL_UNFREEZE_TIM19_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM19_STOP))
+#endif /* DBGMCU_APB2_FZ_DBG_TIM19_STOP */
+
+#if defined(DBGMCU_APB2_FZ_DBG_TIM20_STOP)
+#define __HAL_FREEZE_TIM20_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM20_STOP))
+#define __HAL_UNFREEZE_TIM20_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM20_STOP))
+#endif /* DBGMCU_APB2_FZ_DBG_TIM20_STOP */
+
+#if defined(DBGMCU_APB2_FZ_DBG_HRTIM1_STOP)
+#define __HAL_FREEZE_HRTIM1_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_HRTIM1_STOP))
+#define __HAL_UNFREEZE_HRTIM1_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_HRTIM1_STOP))
+#endif /* DBGMCU_APB2_FZ_DBG_HRTIM1_STOP */
+/**
+ * @}
+ */
+
+/** @defgroup Memory_Mapping_Selection Memory Mapping Selection
+ * @{
+ */
+#if defined(SYSCFG_CFGR1_MEM_MODE)
+/** @brief Main Flash memory mapped at 0x00000000
+ */
+#define __HAL_SYSCFG_REMAPMEMORY_FLASH() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE))
+#endif /* SYSCFG_CFGR1_MEM_MODE */
+
+#if defined(SYSCFG_CFGR1_MEM_MODE_0)
+/** @brief System Flash memory mapped at 0x00000000
+ */
+#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
+ SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE_0; \
+ }while(0U)
+#endif /* SYSCFG_CFGR1_MEM_MODE_0 */
+
+#if defined(SYSCFG_CFGR1_MEM_MODE_0) && defined(SYSCFG_CFGR1_MEM_MODE_1)
+/** @brief Embedded SRAM mapped at 0x00000000
+ */
+#define __HAL_SYSCFG_REMAPMEMORY_SRAM() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
+ SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1); \
+ }while(0U)
+#endif /* SYSCFG_CFGR1_MEM_MODE_0 && SYSCFG_CFGR1_MEM_MODE_1 */
+
+#if defined(SYSCFG_CFGR1_MEM_MODE_2)
+#define __HAL_SYSCFG_FMC_BANK() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
+ SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_2); \
+ }while(0U)
+#endif /* SYSCFG_CFGR1_MEM_MODE_2 */
+/**
+ * @}
+ */
+
+/** @defgroup Encoder_Mode Encoder Mode
+ * @{
+ */
+#if defined(SYSCFG_CFGR1_ENCODER_MODE)
+/** @brief No Encoder mode
+ */
+#define __HAL_REMAPENCODER_NONE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE))
+#endif /* SYSCFG_CFGR1_ENCODER_MODE */
+
+#if defined(SYSCFG_CFGR1_ENCODER_MODE_0)
+/** @brief Encoder mode : TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
+ */
+#define __HAL_REMAPENCODER_TIM2() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \
+ SYSCFG->CFGR1 |= SYSCFG_CFGR1_ENCODER_MODE_0; \
+ }while(0U)
+#endif /* SYSCFG_CFGR1_ENCODER_MODE_0 */
+
+#if defined(SYSCFG_CFGR1_ENCODER_MODE_1)
+/** @brief Encoder mode : TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
+ */
+#define __HAL_REMAPENCODER_TIM3() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \
+ SYSCFG->CFGR1 |= SYSCFG_CFGR1_ENCODER_MODE_1; \
+ }while(0U)
+#endif /* SYSCFG_CFGR1_ENCODER_MODE_1 */
+
+#if defined(SYSCFG_CFGR1_ENCODER_MODE_0) && defined(SYSCFG_CFGR1_ENCODER_MODE_1)
+/** @brief Encoder mode : TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 (STM32F303xB/C and STM32F358xx devices)
+ */
+#define __HAL_REMAPENCODER_TIM4() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \
+ SYSCFG->CFGR1 |= (SYSCFG_CFGR1_ENCODER_MODE_0 | SYSCFG_CFGR1_ENCODER_MODE_1); \
+ }while(0U)
+#endif /* SYSCFG_CFGR1_ENCODER_MODE_0 && SYSCFG_CFGR1_ENCODER_MODE_1 */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Remap_Enable DMA Remap Enable
+ * @{
+ */
+#if defined(SYSCFG_CFGR3_DMA_RMP) && defined(SYSCFG_CFGR1_DMA_RMP)
+/** @brief DMA remapping enable/disable macros
+ * @param __DMA_REMAP__ This parameter can be a value of @ref HAL_DMA_Remapping
+ */
+#define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
+ (((__DMA_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
+ (SYSCFG->CFGR3 |= ((__DMA_REMAP__) & ~HAL_REMAP_CFGR3_MASK)) : \
+ (SYSCFG->CFGR1 |= (__DMA_REMAP__))); \
+ }while(0U)
+#define __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
+ (((__DMA_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
+ (SYSCFG->CFGR3 &= (~(__DMA_REMAP__) | HAL_REMAP_CFGR3_MASK)) : \
+ (SYSCFG->CFGR1 &= ~(__DMA_REMAP__))); \
+ }while(0U)
+#elif defined(SYSCFG_CFGR1_DMA_RMP)
+/** @brief DMA remapping enable/disable macros
+ * @param __DMA_REMAP__ This parameter can be a value of @ref HAL_DMA_Remapping
+ */
+#define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
+ SYSCFG->CFGR1 |= (__DMA_REMAP__); \
+ }while(0U)
+#define __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
+ SYSCFG->CFGR1 &= ~(__DMA_REMAP__); \
+ }while(0U)
+#endif /* SYSCFG_CFGR3_DMA_RMP || SYSCFG_CFGR1_DMA_RMP */
+/**
+ * @}
+ */
+
+/** @defgroup FastModePlus_GPIO Fast-mode Plus on GPIO
+ * @{
+ */
+/** @brief Fast-mode Plus driving capability enable/disable macros
+ * @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO values.
+ * That you can find above these macros.
+ */
+#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
+ SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
+ }while(0U)
+
+#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
+ CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
+ }while(0U)
+/**
+ * @}
+ */
+
+/** @defgroup Floating_Point_Unit_Interrupts_Enable Floating Point Unit Interrupts Enable
+ * @{
+ */
+/** @brief SYSCFG interrupt enable/disable macros
+ * @param __INTERRUPT__ This parameter can be a value of @ref HAL_SYSCFG_Interrupts
+ */
+#define __HAL_SYSCFG_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_HAL_SYSCFG_INTERRUPT((__INTERRUPT__))); \
+ SYSCFG->CFGR1 |= (__INTERRUPT__); \
+ }while(0U)
+
+#define __HAL_SYSCFG_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_HAL_SYSCFG_INTERRUPT((__INTERRUPT__))); \
+ SYSCFG->CFGR1 &= ~(__INTERRUPT__); \
+ }while(0U)
+/**
+ * @}
+ */
+
+#if defined(SYSCFG_CFGR1_USB_IT_RMP)
+/** @defgroup USB_Interrupt_Remap USB Interrupt Remap
+ * @{
+ */
+/** @brief USB interrupt remapping enable/disable macros
+ */
+#define __HAL_REMAPINTERRUPT_USB_ENABLE() (SYSCFG->CFGR1 |= (SYSCFG_CFGR1_USB_IT_RMP))
+#define __HAL_REMAPINTERRUPT_USB_DISABLE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_USB_IT_RMP))
+/**
+ * @}
+ */
+#endif /* SYSCFG_CFGR1_USB_IT_RMP */
+
+#if defined(SYSCFG_CFGR1_VBAT)
+/** @defgroup VBAT_Monitoring_Enable VBAT Monitoring Enable
+ * @{
+ */
+/** @brief SYSCFG interrupt enable/disable macros
+ */
+#define __HAL_SYSCFG_VBAT_MONITORING_ENABLE() (SYSCFG->CFGR1 |= (SYSCFG_CFGR1_VBAT))
+#define __HAL_SYSCFG_VBAT_MONITORING_DISABLE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_VBAT))
+/**
+ * @}
+ */
+#endif /* SYSCFG_CFGR1_VBAT */
+
+#if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
+/** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable
+ * @{
+ */
+/** @brief SYSCFG Break Lockup lock
+ * Enables and locks the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/15/16/17 Break input
+ * @note The selected configuration is locked and can be unlocked by system reset
+ */
+#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \
+ SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \
+ }while(0U)
+/**
+ * @}
+ */
+#endif /* SYSCFG_CFGR2_LOCKUP_LOCK */
+
+#if defined(SYSCFG_CFGR2_PVD_LOCK)
+/** @defgroup PVD_Lock_Enable PVD Lock
+ * @{
+ */
+/** @brief SYSCFG Break PVD lock
+ * Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register
+ * @note The selected configuration is locked and can be unlocked by system reset
+ */
+#define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \
+ SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \
+ }while(0U)
+/**
+ * @}
+ */
+#endif /* SYSCFG_CFGR2_PVD_LOCK */
+
+#if defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
+/** @defgroup SRAM_Parity_Lock SRAM Parity Lock
+ * @{
+ */
+/** @brief SYSCFG Break SRAM PARITY lock
+ * Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17
+ * @note The selected configuration is locked and can be unlocked by system reset
+ */
+#define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_SRAM_PARITY_LOCK); \
+ SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PARITY_LOCK; \
+ }while(0U)
+/**
+ * @}
+ */
+#endif /* SYSCFG_CFGR2_SRAM_PARITY_LOCK */
+
+/** @defgroup Trigger_Remapping_Enable Trigger Remapping Enable
+ * @{
+ */
+#if defined(SYSCFG_CFGR3_TRIGGER_RMP)
+/** @brief Trigger remapping enable/disable macros
+ * @param __TRIGGER_REMAP__ This parameter can be a value of @ref HAL_Trigger_Remapping
+ */
+#define __HAL_REMAPTRIGGER_ENABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
+ (((__TRIGGER_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
+ (SYSCFG->CFGR3 |= ((__TRIGGER_REMAP__) & ~HAL_REMAP_CFGR3_MASK)) : \
+ (SYSCFG->CFGR1 |= (__TRIGGER_REMAP__))); \
+ }while(0U)
+#define __HAL_REMAPTRIGGER_DISABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
+ (((__TRIGGER_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
+ (SYSCFG->CFGR3 &= (~(__TRIGGER_REMAP__) | HAL_REMAP_CFGR3_MASK)) : \
+ (SYSCFG->CFGR1 &= ~(__TRIGGER_REMAP__))); \
+ }while(0U)
+#else
+/** @brief Trigger remapping enable/disable macros
+ * @param __TRIGGER_REMAP__ This parameter can be a value of @ref HAL_Trigger_Remapping
+ */
+#define __HAL_REMAPTRIGGER_ENABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
+ (SYSCFG->CFGR1 |= (__TRIGGER_REMAP__)); \
+ }while(0U)
+#define __HAL_REMAPTRIGGER_DISABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
+ (SYSCFG->CFGR1 &= ~(__TRIGGER_REMAP__)); \
+ }while(0U)
+#endif /* SYSCFG_CFGR3_TRIGGER_RMP */
+/**
+ * @}
+ */
+
+#if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx)
+/** @defgroup ADC_Trigger_Remapping_Enable ADC Trigger Remapping Enable
+ * @{
+ */
+/** @brief ADC trigger remapping enable/disable macros
+ * @param __ADCTRIGGER_REMAP__ This parameter can be a value of @ref HAL_ADC_Trigger_Remapping
+ */
+#define __HAL_REMAPADCTRIGGER_ENABLE(__ADCTRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPADCTRIGGER((__ADCTRIGGER_REMAP__))); \
+ (SYSCFG->CFGR4 |= (__ADCTRIGGER_REMAP__)); \
+ }while(0U)
+#define __HAL_REMAPADCTRIGGER_DISABLE(__ADCTRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPADCTRIGGER((__ADCTRIGGER_REMAP__))); \
+ (SYSCFG->CFGR4 &= ~(__ADCTRIGGER_REMAP__)); \
+ }while(0U)
+/**
+ * @}
+ */
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+
+#if defined(SYSCFG_CFGR2_BYP_ADDR_PAR)
+/** @defgroup RAM_Parity_Check_Disable RAM Parity Check Disable
+ * @{
+ */
+/**
+ * @brief Parity check on RAM disable macro
+ * @note Disabling the parity check on RAM locks the configuration bit.
+ * To re-enable the parity check on RAM perform a system reset.
+ */
+#define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (*(__IO uint32_t *) CFGR2_BYPADDRPAR_BB = 0x00000001U)
+/**
+ * @}
+ */
+#endif /* SYSCFG_CFGR2_BYP_ADDR_PAR */
+
+#if defined(SYSCFG_RCR_PAGE0)
+/** @defgroup CCM_RAM_Page_Write_Protection_Enable CCM RAM page write protection enable
+ * @{
+ */
+/** @brief CCM RAM page write protection enable macro
+ * @param __PAGE_WP__ This parameter can be a value of @ref HAL_Page_Write_Protection
+ * @note write protection can only be disabled by a system reset
+ */
+#define __HAL_SYSCFG_SRAM_WRP_ENABLE(__PAGE_WP__) do {assert_param(IS_HAL_SYSCFG_WP_PAGE((__PAGE_WP__))); \
+ SYSCFG->RCR |= (__PAGE_WP__); \
+ }while(0U)
+/**
+ * @}
+ */
+#endif /* SYSCFG_RCR_PAGE0 */
+
+/**
+ * @}
+ */
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup HAL_Private_Macros HAL Private Macros
+ * @{
+ */
+#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \
+ ((FREQ) == HAL_TICK_FREQ_100HZ) || \
+ ((FREQ) == HAL_TICK_FREQ_1KHZ))
+/**
+ * @}
+ */
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup HAL_Exported_Functions HAL Exported Functions
+ * @{
+ */
+
+/** @addtogroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
+ * @brief Initialization and de-initialization functions
+ * @{
+ */
+/* Initialization and de-initialization functions ******************************/
+HAL_StatusTypeDef HAL_Init(void);
+HAL_StatusTypeDef HAL_DeInit(void);
+void HAL_MspInit(void);
+void HAL_MspDeInit(void);
+HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
+/**
+ * @}
+ */
+
+/* Exported variables ---------------------------------------------------------*/
+/** @addtogroup HAL_Exported_Variables
+ * @{
+ */
+extern __IO uint32_t uwTick;
+extern uint32_t uwTickPrio;
+extern HAL_TickFreqTypeDef uwTickFreq;
+/**
+ * @}
+ */
+
+/** @addtogroup HAL_Exported_Functions_Group2 HAL Control functions
+ * @brief HAL Control functions
+ * @{
+ */
+/* Peripheral Control functions ************************************************/
+void HAL_IncTick(void);
+void HAL_Delay(uint32_t Delay);
+void HAL_SuspendTick(void);
+void HAL_ResumeTick(void);
+uint32_t HAL_GetTick(void);
+uint32_t HAL_GetTickPrio(void);
+HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
+HAL_TickFreqTypeDef HAL_GetTickFreq(void);
+uint32_t HAL_GetHalVersion(void);
+uint32_t HAL_GetREVID(void);
+uint32_t HAL_GetDEVID(void);
+uint32_t HAL_GetUIDw0(void);
+uint32_t HAL_GetUIDw1(void);
+uint32_t HAL_GetUIDw2(void);
+void HAL_DBGMCU_EnableDBGSleepMode(void);
+void HAL_DBGMCU_DisableDBGSleepMode(void);
+void HAL_DBGMCU_EnableDBGStopMode(void);
+void HAL_DBGMCU_DisableDBGStopMode(void);
+void HAL_DBGMCU_EnableDBGStandbyMode(void);
+void HAL_DBGMCU_DisableDBGStandbyMode(void);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_hal_adc.h b/Inc/stm32f3xx_hal_adc.h
new file mode 100644
index 0000000..16eca9a
--- /dev/null
+++ b/Inc/stm32f3xx_hal_adc.h
@@ -0,0 +1,241 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_adc.h
+ * @author MCD Application Team
+ * @brief Header file containing functions prototypes of ADC HAL library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_ADC_H
+#define __STM32F3xx_ADC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/* Include ADC HAL Extended module */
+/* (include on top of file since ADC structures are defined in extended file) */
+#include "stm32f3xx_hal_adc_ex.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup ADC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup ADC_Exported_Types ADC Exported Types
+ * @{
+ */
+/**
+ * @brief HAL ADC state machine: ADC states definition (bitfields)
+ * @note ADC state machine is managed by bitfields, state must be compared
+ * with bit by bit.
+ * For example:
+ * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) "
+ * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) "
+ */
+/* States of ADC global scope */
+#define HAL_ADC_STATE_RESET (0x00000000U) /*!< ADC not yet initialized or disabled */
+#define HAL_ADC_STATE_READY (0x00000001U) /*!< ADC peripheral ready for use */
+#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002U) /*!< ADC is busy to internal process (initialization, calibration) */
+#define HAL_ADC_STATE_TIMEOUT (0x00000004U) /*!< TimeOut occurrence */
+
+/* States of ADC errors */
+#define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010U) /*!< Internal error occurrence */
+#define HAL_ADC_STATE_ERROR_CONFIG (0x00000020U) /*!< Configuration error occurrence */
+#define HAL_ADC_STATE_ERROR_DMA (0x00000040U) /*!< DMA error occurrence */
+
+/* States of ADC group regular */
+#define HAL_ADC_STATE_REG_BUSY (0x00000100U) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
+ external trigger, low power auto power-on, multimode ADC master control) */
+#define HAL_ADC_STATE_REG_EOC (0x00000200U) /*!< Conversion data available on group regular */
+#define HAL_ADC_STATE_REG_OVR (0x00000400U) /*!< Overrun occurrence */
+#define HAL_ADC_STATE_REG_EOSMP (0x00000800U) /*!< End Of Sampling flag raised */
+
+/* States of ADC group injected */
+#define HAL_ADC_STATE_INJ_BUSY (0x00001000U) /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
+ external trigger, low power auto power-on, multimode ADC master control) */
+#define HAL_ADC_STATE_INJ_EOC (0x00002000U) /*!< Conversion data available on group injected */
+#define HAL_ADC_STATE_INJ_JQOVF (0x00004000U) /*!< Injected queue overflow occurrence */
+
+/* States of ADC analog watchdogs */
+#define HAL_ADC_STATE_AWD1 (0x00010000U) /*!< Out-of-window occurrence of analog watchdog 1 */
+#define HAL_ADC_STATE_AWD2 (0x00020000U) /*!< Out-of-window occurrence of analog watchdog 2 */
+#define HAL_ADC_STATE_AWD3 (0x00040000U) /*!< Out-of-window occurrence of analog watchdog 3 */
+
+/* States of ADC multi-mode */
+#define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000U) /*!< ADC in multimode slave state, controlled by another ADC master ( */
+
+
+/**
+ * @brief ADC handle Structure definition
+ */
+typedef struct __ADC_HandleTypeDef
+{
+ ADC_TypeDef *Instance; /*!< Register base address */
+
+ ADC_InitTypeDef Init; /*!< ADC required parameters */
+
+ DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
+
+ HAL_LockTypeDef Lock; /*!< ADC locking object */
+
+ __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */
+
+ __IO uint32_t ErrorCode; /*!< ADC Error code */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+ ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up structure */
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+}ADC_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Macro ADC Exported Macros
+ * @{
+ */
+/** @brief Reset ADC handle state
+ * @param __HANDLE__ ADC handle
+ * @retval None
+ */
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
+
+/**
+ * @}
+ */
+
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADC_Exported_Functions ADC Exported Functions
+ * @{
+ */
+
+/** @addtogroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+/* Initialization and de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
+void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
+void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Exported_Functions_Group2 Input and Output operation functions
+ * @{
+ */
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
+HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
+
+/* Non-blocking mode: Interruption */
+HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
+
+/* Non-blocking mode: DMA */
+HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
+HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
+
+/* ADC retrieve conversion value intended to be used with polling or interruption */
+uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
+
+/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
+void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
+void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
+void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
+void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
+void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
+HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
+ * @brief ADC Peripheral State functions
+ * @{
+ */
+/* Peripheral State functions *************************************************/
+uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
+uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F3xx_ADC_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_hal_adc_ex.h b/Inc/stm32f3xx_hal_adc_ex.h
new file mode 100644
index 0000000..1d26d6d
--- /dev/null
+++ b/Inc/stm32f3xx_hal_adc_ex.h
@@ -0,0 +1,3988 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_adc_ex.h
+ * @author MCD Application Team
+ * @brief Header file containing functions prototypes of ADC HAL library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_ADC_EX_H
+#define __STM32F3xx_ADC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup ADCEx ADCEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup ADCEx_Exported_Types ADCEx Exported Types
+ * @{
+ */
+struct __ADC_HandleTypeDef;
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Structure definition of ADC initialization and regular group
+ * @note Parameters of this structure are shared within 2 scopes:
+ * - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, DataAlign,
+ * ScanConvMode, EOCSelection, LowPowerAutoWait.
+ * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv, DMAContinuousRequests, Overrun.
+ * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
+ * ADC state can be either:
+ * - For all parameters: ADC disabled
+ * - For all parameters except 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on regular group.
+ * - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on regular and injected groups.
+ * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
+ * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fullfills the ADC state condition) on the fly).
+ */
+typedef struct
+{
+ uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from AHB clock or asynchronous clock derived from ADC dedicated PLL 72MHz) and clock prescaler.
+ The clock is common for all the ADCs.
+ This parameter can be a value of @ref ADCEx_ClockPrescaler
+ Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits,
+ AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits.
+ Note: In case of usage of the ADC dedicated PLL clock, this clock must be preliminarily enabled and prescaler set at RCC top level.
+ Note: This parameter can be modified only if all ADCs of the common ADC group are disabled (for products with several ADCs) */
+ uint32_t Resolution; /*!< Configures the ADC resolution.
+ This parameter can be a value of @ref ADCEx_Resolution */
+ uint32_t DataAlign; /*!< Specifies ADC data alignment to right (for resolution 12 bits: MSB on register bit 11 and LSB on register bit 0U) (default setting)
+ or to left (for resolution 12 bits, if offset disabled: MSB on register bit 15 and LSB on register bit 4U, if offset enabled: MSB on register bit 14 and LSB on register bit 3U).
+ See reference manual for alignments with other resolutions.
+ This parameter can be a value of @ref ADCEx_Data_align */
+ uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
+ This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
+ If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1U).
+ Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1U).
+ If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
+ Scan direction is upward: from rank1 to rank 'n'.
+ This parameter can be a value of @ref ADCEx_Scan_mode */
+ uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
+ This parameter can be a value of @ref ADCEx_EOCSelection. */
+ uint32_t LowPowerAutoWait; /*!< Selects the dynamic low power Auto Delay: ADC conversions are performed only when necessary.
+ New conversion starts only when the previous conversion (for regular group) or previous sequence (for injected group) has been treated by user software.
+ This feature automatically adapts the speed of ADC to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications.
+ This parameter can be set to ENABLE or DISABLE.
+ Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they have to clear immediately the EOC flag to free the IRQ vector sequencer.
+ Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed
+ and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion (in case of usage of injected group, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */
+ uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
+ after the selected trigger occurred (software start or external trigger).
+ This parameter can be set to ENABLE or DISABLE. */
+ uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
+ To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 16.
+ Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */
+ uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
+ Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
+ Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
+ This parameter can be set to ENABLE or DISABLE. */
+ uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided.
+ If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
+ uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
+ If set to ADC_SOFTWARE_START, external triggers are disabled.
+ This parameter can be a value of @ref ADCEx_External_trigger_source_Regular
+ Caution: For devices with several ADCs, external trigger source is common to ADC common group (for example: ADC1&ADC2, ADC3&ADC4, if available) */
+ uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group.
+ If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
+ This parameter can be a value of @ref ADCEx_External_trigger_edge_Regular */
+ uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
+ or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
+ Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
+ This parameter can be set to ENABLE or DISABLE.
+ Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */
+ uint32_t Overrun; /*!< Select the behaviour in case of overrun: data overwritten (default) or preserved.
+ This parameter is for regular group only.
+ This parameter can be a value of @ref ADCEx_Overrun
+ Note: Case of overrun set to data preserved and usage with end on conversion interruption (HAL_Start_IT()): ADC IRQ handler has to clear end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved into function HAL_ADC_ConvCpltCallback() (called before end of conversion flags clear).
+ Note: Error reporting in function of conversion mode:
+ - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data overwritten, user can willingly not read the conversion data each time, this is not considered as an erroneous case.
+ - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register, any data missed would be abnormal). */
+}ADC_InitTypeDef;
+
+/**
+ * @brief Structure definition of ADC channel for regular group
+ * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
+ * ADC state can be either:
+ * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff')
+ * - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular group.
+ * - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular and injected groups.
+ * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
+ * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
+ */
+typedef struct
+{
+ uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
+ This parameter can be a value of @ref ADCEx_channels
+ Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
+ uint32_t Rank; /*!< Specifies the rank in the regular group sequencer.
+ This parameter can be a value of @ref ADCEx_regular_rank
+ Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
+ uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
+ Unit: ADC clock cycles
+ Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
+ This parameter can be a value of @ref ADCEx_sampling_times
+ Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
+ If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
+ Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
+ sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
+ Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 2.2us min). */
+ uint32_t SingleDiff; /*!< Selection of single-ended or differential input.
+ In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
+ Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
+ This parameter must be a value of @ref ADCEx_SingleDifferential
+ Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
+ If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
+ Note: Channels 1 to 14 are available in differential mode. Channels 15U, 16U, 17U, 18 can be used only in single-ended mode.
+ Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
+ Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
+ If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly) */
+ uint32_t OffsetNumber; /*!< Selects the offset number
+ This parameter can be a value of @ref ADCEx_OffsetNumber
+ Caution: Only one channel is allowed per channel. If another channel was on this offset number, the offset will be changed to the new channel */
+ uint32_t Offset; /*!< Defines the offset to be subtracted from the raw converted data when convert channels.
+ Offset value must be a positive number.
+ Depending of ADC resolution selected (12U, 10U, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFFU, 0x3FFU, 0xFF or 0x3F respectively.
+ Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */
+}ADC_ChannelConfTypeDef;
+
+/**
+ * @brief Structure definition of ADC injected group and ADC channel for injected group
+ * @note Parameters of this structure are shared within 2 scopes:
+ * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset
+ * - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
+ * AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConvEdge, ExternalTrigInjecConv.
+ * @note The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
+ * ADC state can be either:
+ * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff')
+ * - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext': ADC enabled without conversion on going on injected group.
+ * - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups.
+ * - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going on regular and injected groups.
+ * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
+ * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
+ */
+typedef struct
+{
+ uint32_t InjectedChannel; /*!< Configure the ADC injected channel
+ This parameter can be a value of @ref ADCEx_channels
+ Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
+ uint32_t InjectedRank; /*!< The rank in the regular group sequencer
+ This parameter must be a value of @ref ADCEx_injected_rank
+ Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
+ uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
+ Unit: ADC clock cycles
+ Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
+ This parameter can be a value of @ref ADCEx_sampling_times
+ Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
+ If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
+ Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
+ sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
+ Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 2.2us min). */
+ uint32_t InjectedSingleDiff; /*!< Selection of single-ended or differential input.
+ In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
+ Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
+ This parameter must be a value of @ref ADCEx_SingleDifferential
+ Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
+ If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
+ Note: Channels 1 to 14 are available in differential mode. Channels 15U, 16U, 17U, 18 can be used only in single-ended mode.
+ Note: When configuring a channel 'i' in differential mode, the channel 'i-1' is not usable separately.
+ Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
+ If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly) */
+ uint32_t InjectedOffsetNumber; /*!< Selects the offset number
+ This parameter can be a value of @ref ADCEx_OffsetNumber
+ Caution: Only one channel is allowed per offset number. If another channel was on this offset number, the offset will be changed to the new channel. */
+ uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data.
+ Offset value must be a positive number.
+ Depending of ADC resolution selected (12U, 10U, 8 or 6 bits),
+ this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFFU, 0x3FFU, 0xFF or 0x3F respectively. */
+ uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
+ To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 4.
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration of other channels previously set. */
+ uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
+ Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
+ Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
+ This parameter can be set to ENABLE or DISABLE.
+ Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
+ Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration of other channels previously set. */
+ uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
+ This parameter can be set to ENABLE or DISABLE.
+ Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
+ Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)
+ Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
+ To maintain JAUTO always enabled, DMA must be configured in circular mode.
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration of other channels previously set. */
+ uint32_t QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled.
+ This parameter can be set to ENABLE or DISABLE.
+ If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a
+ new injected context is set when queue is full, error is triggered by interruption and through function 'HAL_ADCEx_InjectedQueueOverflowCallback'.
+ Caution: This feature request that the sequence is fully configured before injected conversion start.
+ Therefore, configure channels with HAL_ADCEx_InjectedConfigChannel() as many times as value of 'InjectedNbrOfConversion' parameter.
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration of other channels previously set.
+ Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */
+ uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group.
+ If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled.
+ This parameter can be a value of @ref ADCEx_External_trigger_source_Injected
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration of other channels previously set. */
+ uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group.
+ This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected.
+ If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration of other channels previously set. */
+}ADC_InjectionConfTypeDef;
+
+/**
+ * @brief ADC Injection Configuration
+ */
+typedef struct
+{
+ uint32_t ContextQueue; /*!< Injected channel configuration context: build-up over each
+ HAL_ADCEx_InjectedConfigChannel() call to finally initialize
+ JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */
+
+ uint32_t ChannelCount; /*!< Number of channels in the injected sequence */
+}ADC_InjectionConfigTypeDef;
+
+/**
+ * @brief Structure definition of ADC analog watchdog
+ * @note The setting of these parameters with function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.
+ * ADC state can be either: ADC disabled or ADC enabled without conversion on going on regular and injected groups.
+ */
+typedef struct
+{
+ uint32_t WatchdogNumber; /*!< Selects which ADC analog watchdog to apply to the selected channel.
+ For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode')
+ For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel)
+ This parameter can be a value of @ref ADCEx_analog_watchdog_number. */
+ uint32_t WatchdogMode; /*!< For Analog Watchdog 1: Configures the ADC analog watchdog mode: single channel/overall group of channels, regular/injected group.
+ For Analog Watchdog 2 and 3: There is no configuration for overall group of channels as AWD1. Set value 'ADC_ANALOGWATCHDOG_NONE' to reset channels group programmed with parameter 'Channel', set any other value to not use this parameter.
+ This parameter can be a value of @ref ADCEx_analog_watchdog_mode. */
+ uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog.
+ For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel. Only 1 channel can be monitored.
+ For Analog Watchdog 2 and 3: Several channels can be monitored (successive calls of HAL_ADC_AnalogWDGConfig() must be done, one for each channel.
+ Channels group reset can be done by setting WatchdogMode to 'ADC_ANALOGWATCHDOG_NONE').
+ This parameter can be a value of @ref ADCEx_channels. */
+ uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
+ This parameter can be set to ENABLE or DISABLE */
+ uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
+ Depending of ADC resolution selected (12U, 10U, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFFU, 0x3FFU, 0xFF or 0x3F respectively.
+ Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
+ the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. */
+ uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
+ Depending of ADC resolution selected (12U, 10U, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFFU, 0x3FFU, 0xFF or 0x3F respectively.
+ Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
+ the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. */
+}ADC_AnalogWDGConfTypeDef;
+
+/**
+ * @brief Structure definition of ADC multimode
+ * @note The setting of these parameters with function HAL_ADCEx_MultiModeConfigChannel() is conditioned to ADCs state (both ADCs of the common group).
+ * ADC state can be either:
+ * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'DMAAccessMode')
+ * - For parameter 'DMAAccessMode': ADC enabled without conversion on going on regular group.
+ * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
+ * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
+ */
+typedef struct
+{
+ uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode.
+ This parameter can be a value of @ref ADCEx_Common_mode */
+ uint32_t DMAAccessMode; /*!< Configures the DMA mode for multi ADC mode:
+ selection whether 2 DMA channels (each ADC use its own DMA channel) or 1 DMA channel (one DMA channel for both ADC, DMA of ADC master)
+ This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multimode
+ Caution: Limitations with multimode DMA access enabled (1 DMA channel used): In case of dual mode in high speed (more than 5Msps) or high activity of DMA by other peripherals, there is a risk of DMA overrun.
+ Therefore, it is recommended to disable multimode DMA access: each ADC uses its own DMA channel.
+ Refer to device errata sheet for more details. */
+ uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
+ This parameter can be a value of @ref ADCEx_delay_between_2_sampling_phases
+ Delay range depends on selected resolution: from 1 to 12 clock cycles for 12 bits, from 1 to 10 clock cycles for 10 bits
+ from 1 to 8 clock cycles for 8 bits, from 1 to 6 clock cycles for 6 bits */
+}ADC_MultiModeTypeDef;
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Structure definition of ADC and regular group initialization
+ * @note Parameters of this structure are shared within 2 scopes:
+ * - Scope entire ADC (affects regular and injected groups): DataAlign, ScanConvMode.
+ * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
+ * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
+ * ADC can be either disabled or enabled without conversion on going on regular group.
+ */
+typedef struct
+{
+ uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0U) (default setting)
+ or to left (if regular group: MSB on register bit 15 and LSB on register bit 4U, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3U).
+ This parameter can be a value of @ref ADCEx_Data_align */
+ uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
+ This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
+ If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1U).
+ Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1U).
+ If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
+ Scan direction is upward: from rank1 to rank 'n'.
+ This parameter can be a value of @ref ADCEx_Scan_mode
+ Note: For regular group, this parameter should be enabled in conversion either by polling (HAL_ADC_Start with Discontinuous mode and NbrOfDiscConversion=1U)
+ or by DMA (HAL_ADC_Start_DMA), but not by interruption (HAL_ADC_Start_IT): in scan mode, interruption is triggered only on the
+ the last conversion of the sequence. All previous conversions would be overwritten by the last one.
+ Injected group used with scan mode has not this constraint: each rank has its own result register, no data is overwritten. */
+ uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
+ after the selected trigger occurred (software start or external trigger).
+ This parameter can be set to ENABLE or DISABLE. */
+ uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
+ To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
+ uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
+ Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
+ Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
+ This parameter can be set to ENABLE or DISABLE. */
+ uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided.
+ If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
+ uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
+ If set to ADC_SOFTWARE_START, external triggers are disabled.
+ If set to external trigger source, triggering is on event rising edge.
+ This parameter can be a value of @ref ADCEx_External_trigger_source_Regular */
+}ADC_InitTypeDef;
+
+/**
+ * @brief Structure definition of ADC channel for regular group
+ * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
+ * ADC can be either disabled or enabled without conversion on going on regular group.
+ */
+typedef struct
+{
+ uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
+ This parameter can be a value of @ref ADCEx_channels
+ Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
+ uint32_t Rank; /*!< Specifies the rank in the regular group sequencer
+ This parameter can be a value of @ref ADCEx_regular_rank
+ Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
+ uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
+ Unit: ADC clock cycles
+ Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits).
+ This parameter can be a value of @ref ADCEx_sampling_times
+ Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
+ If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
+ Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
+ sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
+ Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 5us to 17.1us min). */
+}ADC_ChannelConfTypeDef;
+
+/**
+ * @brief ADC Configuration injected Channel structure definition
+ * @note Parameters of this structure are shared within 2 scopes:
+ * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset
+ * - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
+ * AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv.
+ * @note The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
+ * ADC state can be either:
+ * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'ExternalTrigInjecConv')
+ * - For all except parameters 'ExternalTrigInjecConv': ADC enabled without conversion on going on injected group.
+ */
+typedef struct
+{
+ uint32_t InjectedChannel; /*!< Selection of ADC channel to configure
+ This parameter can be a value of @ref ADCEx_channels
+ Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
+ uint32_t InjectedRank; /*!< Rank in the injected group sequencer
+ This parameter must be a value of @ref ADCEx_injected_rank
+ Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
+ uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
+ Unit: ADC clock cycles
+ Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits).
+ This parameter can be a value of @ref ADCEx_sampling_times
+ Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
+ If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
+ Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
+ sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
+ Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 5us to 17.1us min). */
+ uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only).
+ Offset value must be a positive number.
+ Depending of ADC resolution selected (12U, 10U, 8 or 6 bits),
+ this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFFU, 0x3FFU, 0xFF or 0x3F respectively. */
+ uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
+ To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 4.
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration of other channels previously set. */
+ uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
+ Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
+ Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
+ This parameter can be set to ENABLE or DISABLE.
+ Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration of other channels previously set. */
+ uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
+ This parameter can be set to ENABLE or DISABLE.
+ Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
+ Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)
+ Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
+ To maintain JAUTO always enabled, DMA must be configured in circular mode.
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration of other channels previously set. */
+ uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group.
+ If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled.
+ If set to external trigger source, triggering is on event rising edge.
+ This parameter can be a value of @ref ADCEx_External_trigger_source_Injected
+ Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
+ If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly)
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration of other channels previously set. */
+}ADC_InjectionConfTypeDef;
+
+/**
+ * @brief ADC Configuration analog watchdog definition
+ * @note The setting of these parameters with function is conditioned to ADC state.
+ * ADC state can be either disabled or enabled without conversion on going on regular and injected groups.
+ */
+typedef struct
+{
+ uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group.
+ This parameter can be a value of @ref ADCEx_analog_watchdog_mode. */
+ uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog.
+ This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode)
+ This parameter can be a value of @ref ADCEx_channels. */
+ uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
+ This parameter can be set to ENABLE or DISABLE */
+ uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
+ This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
+ uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
+ This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
+ uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0U */
+}ADC_AnalogWDGConfTypeDef;
+#endif /* STM32F373xC || STM32F378xx */
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADCEx_Exported_Constants ADCEx Exported Constants
+ * @{
+ */
+
+/** @defgroup ADCEx_Error_Code ADC Extended Error Code
+ * @{
+ */
+#define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */
+#define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC IP internal error: if problem of clocking,
+ enable/disable, erroneous state */
+#define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */
+#define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */
+#define HAL_ADC_ERROR_JQOVF (0x08U) /*!< Injected context queue overflow error */
+/**
+ * @}
+ */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/** @defgroup ADCEx_ClockPrescaler ADC Extended Clock Prescaler
+ * @{
+ */
+#define ADC_CLOCK_ASYNC_DIV1 (0x00000000U) /*!< ADC asynchronous clock derived from ADC dedicated PLL */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define ADC_CLOCK_SYNC_PCLK_DIV1 ((uint32_t)ADC12_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock without prescaler */
+#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC12_CCR_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 2U */
+#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC12_CCR_CKMODE) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 4U */
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define ADC_CLOCK_SYNC_PCLK_DIV1 ((uint32_t)ADC1_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock without prescaler */
+#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC1_CCR_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 2U */
+#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC1_CCR_CKMODE) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 4U */
+#endif /* STM32F301x8 || STM32F318xx || STM32F302x8 */
+
+#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) || \
+ ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV1) || \
+ ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
+ ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) )
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_Resolution ADC Extended Resolution
+ * @{
+ */
+#define ADC_RESOLUTION_12B (0x00000000U) /*!< ADC 12-bit resolution */
+#define ADC_RESOLUTION_10B ((uint32_t)ADC_CFGR_RES_0) /*!< ADC 10-bit resolution */
+#define ADC_RESOLUTION_8B ((uint32_t)ADC_CFGR_RES_1) /*!< ADC 8-bit resolution */
+#define ADC_RESOLUTION_6B ((uint32_t)ADC_CFGR_RES) /*!< ADC 6-bit resolution */
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_Data_align ADC Extended Data Alignment
+ * @{
+ */
+#define ADC_DATAALIGN_RIGHT (0x00000000U)
+#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CFGR_ALIGN)
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_Scan_mode ADC Extended Scan Mode
+ * @{
+ */
+#define ADC_SCAN_DISABLE (0x00000000U)
+#define ADC_SCAN_ENABLE (0x00000001U)
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_External_trigger_edge_Regular ADC Extended External trigger enable and polarity selection for regular group
+ * @{
+ */
+#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000U)
+#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR_EXTEN_0)
+#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR_EXTEN_1)
+#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR_EXTEN)
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_External_trigger_source_Regular ADC Extended External trigger selection for regular group
+ * @{
+ */
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+/*!< List of external triggers with generic trigger name, independently of */
+/* ADC target (caution: applies to other ADCs sharing the same common group), */
+/* sorted by trigger name: */
+
+/*!< External triggers of regular group for ADC1&ADC2 only */
+#define ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_2_EXTERNALTRIG_T1_CC1
+#define ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_2_EXTERNALTRIG_T1_CC2
+#define ADC_EXTERNALTRIGCONV_T2_CC2 ADC1_2_EXTERNALTRIG_T2_CC2
+#define ADC_EXTERNALTRIGCONV_T3_CC4 ADC1_2_EXTERNALTRIG_T3_CC4
+#define ADC_EXTERNALTRIGCONV_T4_CC4 ADC1_2_EXTERNALTRIG_T4_CC4
+#define ADC_EXTERNALTRIGCONV_T6_TRGO ADC1_2_EXTERNALTRIG_T6_TRGO
+#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11
+
+/*!< External triggers of regular group for ADC3&ADC4 only */
+#define ADC_EXTERNALTRIGCONV_T2_CC1 ADC3_4_EXTERNALTRIG_T2_CC1
+#define ADC_EXTERNALTRIGCONV_T2_CC3 ADC3_4_EXTERNALTRIG_T2_CC3
+#define ADC_EXTERNALTRIGCONV_T3_CC1 ADC3_4_EXTERNALTRIG_T3_CC1
+#define ADC_EXTERNALTRIGCONV_T4_CC1 ADC3_4_EXTERNALTRIG_T4_CC1
+#define ADC_EXTERNALTRIGCONV_T7_TRGO ADC3_4_EXTERNALTRIG_T7_TRGO
+#define ADC_EXTERNALTRIGCONV_T8_CC1 ADC3_4_EXTERNALTRIG_T8_CC1
+#define ADC_EXTERNALTRIGCONV_EXT_IT2 ADC3_4_EXTERNALTRIG_EXT_IT2
+
+/*!< External triggers of regular group for ADC1&ADC2, ADC3&ADC4 */
+/* Note: Triggers affected to group ADC1_2 by default, redirected to group */
+/* ADC3_4 by driver when needed. */
+#define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_2_EXTERNALTRIG_T1_CC3
+#define ADC_EXTERNALTRIGCONV_T1_TRGO ADC1_2_EXTERNALTRIG_T1_TRGO
+#define ADC_EXTERNALTRIGCONV_T1_TRGO2 ADC1_2_EXTERNALTRIG_T1_TRGO2
+#define ADC_EXTERNALTRIGCONV_T2_TRGO ADC1_2_EXTERNALTRIG_T2_TRGO
+#define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO
+#define ADC_EXTERNALTRIGCONV_T4_TRGO ADC1_2_EXTERNALTRIG_T4_TRGO
+#define ADC_EXTERNALTRIGCONV_T8_TRGO ADC1_2_EXTERNALTRIG_T8_TRGO
+#define ADC_EXTERNALTRIGCONV_T8_TRGO2 ADC1_2_EXTERNALTRIG_T8_TRGO2
+#define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_2_EXTERNALTRIG_T15_TRGO
+
+#define ADC_SOFTWARE_START (0x00000001U)
+
+#if defined(STM32F303xE) || defined(STM32F398xx)
+/* ADC external triggers specific to device STM303xE: mask to differentiate */
+/* standard triggers from specific timer 20U, needed for reallocation of */
+/* triggers common to ADC1&2U/ADC3&4 and to avoid mixing with standard */
+/* triggers without remap. */
+#define ADC_EXTERNALTRIGCONV_T20_MASK 0x1000
+
+/*!< List of external triggers specific to device STM303xE: using Timer20 */
+/* with ADC trigger input remap. */
+/* To remap ADC trigger from other timers/ExtLine to timer20: use macro */
+/* " __HAL_REMAPADCTRIGGER_ENABLE(...) " with parameters described below: */
+
+/*!< External triggers of regular group for ADC1&ADC2 only, specific to */
+/* device STM303xE: : using Timer20 with ADC trigger input remap */
+#define ADC_EXTERNALTRIGCONV_T20_CC2 ADC_EXTERNALTRIGCONV_T6_TRGO /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT13U) */
+#define ADC_EXTERNALTRIGCONV_T20_CC3 ADC_EXTERNALTRIGCONV_T3_CC4 /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT15U) */
+
+/*!< External triggers of regular group for ADC3&ADC4 only, specific to */
+/* device STM303xE: : using Timer20 with ADC trigger input remap */
+/* None */
+
+/*!< External triggers of regular group for ADC1&ADC2, ADC3&ADC4, specific to */
+/* device STM303xE: : using Timer20 with ADC trigger input remap */
+/* Note: Triggers affected to group ADC1_2 by default, redirected to group */
+/* ADC3_4 by driver when needed. */
+#define ADC_EXTERNALTRIGCONV_T20_CC1 (ADC_EXTERNALTRIGCONV_T4_CC4 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT5) */
+ /*!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_EXT15U) */
+#define ADC_EXTERNALTRIGCONV_T20_TRGO (ADC_EXTERNALTRIGCONV_T1_CC3 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT2) */
+ /*!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_EXT5) */
+#define ADC_EXTERNALTRIGCONV_T20_TRGO2 (ADC_EXTERNALTRIGCONV_T2_CC2 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT3) */
+ /*!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_EXT6) */
+#endif /* STM32F303xE || STM32F398xx */
+
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC)
+/*!< List of external triggers with generic trigger name, independently of */
+/* ADC target (caution: applies to other ADCs sharing the same common group), */
+/* sorted by trigger name: */
+
+/*!< External triggers of regular group for ADC1&ADC2 */
+#define ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_2_EXTERNALTRIG_T1_CC1
+#define ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_2_EXTERNALTRIG_T1_CC2
+#define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_2_EXTERNALTRIG_T1_CC3
+#define ADC_EXTERNALTRIGCONV_T1_TRGO ADC1_2_EXTERNALTRIG_T1_TRGO
+#define ADC_EXTERNALTRIGCONV_T1_TRGO2 ADC1_2_EXTERNALTRIG_T1_TRGO2
+#define ADC_EXTERNALTRIGCONV_T2_CC2 ADC1_2_EXTERNALTRIG_T2_CC2
+#define ADC_EXTERNALTRIGCONV_T2_TRGO ADC1_2_EXTERNALTRIG_T2_TRGO
+#define ADC_EXTERNALTRIGCONV_T3_CC4 ADC1_2_EXTERNALTRIG_T3_CC4
+#define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO
+#define ADC_EXTERNALTRIGCONV_T4_CC4 ADC1_2_EXTERNALTRIG_T4_CC4
+#define ADC_EXTERNALTRIGCONV_T4_TRGO ADC1_2_EXTERNALTRIG_T4_TRGO
+#define ADC_EXTERNALTRIGCONV_T6_TRGO ADC1_2_EXTERNALTRIG_T6_TRGO
+#define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_2_EXTERNALTRIG_T15_TRGO
+#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11
+#define ADC_SOFTWARE_START (0x00000001U)
+
+#if defined(STM32F302xE)
+/* ADC external triggers specific to device STM302xE: mask to differentiate */
+/* standard triggers from specific timer 20U, needed for reallocation of */
+/* triggers common to ADC1&2 and to avoind mixing with standard */
+/* triggers without remap. */
+#define ADC_EXTERNALTRIGCONV_T20_MASK 0x1000
+
+/*!< List of external triggers specific to device STM302xE: using Timer20 */
+/* with ADC trigger input remap. */
+/* To remap ADC trigger from other timers/ExtLine to timer20: use macro */
+/* " __HAL_REMAPADCTRIGGER_ENABLE(...) " with parameters described below: */
+
+/*!< External triggers of regular group for ADC1&ADC2 only, specific to */
+/* device STM302xE: : using Timer20 with ADC trigger input remap */
+#define ADC_EXTERNALTRIGCONV_T20_CC2 ADC_EXTERNALTRIGCONV_T6_TRGO /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT13U) */
+#define ADC_EXTERNALTRIGCONV_T20_CC3 ADC_EXTERNALTRIGCONV_T3_CC4 /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT15U) */
+#endif /* STM32F302xE */
+
+#endif /* STM32F302xE || */
+ /* STM32F302xC */
+
+#if defined(STM32F303x8) || defined(STM32F328xx)
+/*!< List of external triggers with generic trigger name, independently of */
+/* ADC target (caution: applies to other ADCs sharing the same common group), */
+/* sorted by trigger name: */
+
+/*!< External triggers of regular group for ADC1&ADC2 */
+#define ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_2_EXTERNALTRIG_T1_CC1
+#define ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_2_EXTERNALTRIG_T1_CC2
+#define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_2_EXTERNALTRIG_T1_CC3
+#define ADC_EXTERNALTRIGCONV_T1_TRGO ADC1_2_EXTERNALTRIG_T1_TRGO
+#define ADC_EXTERNALTRIGCONV_T1_TRGO2 ADC1_2_EXTERNALTRIG_T1_TRGO2
+#define ADC_EXTERNALTRIGCONV_T2_CC2 ADC1_2_EXTERNALTRIG_T2_CC2
+#define ADC_EXTERNALTRIGCONV_T2_TRGO ADC1_2_EXTERNALTRIG_T2_TRGO
+#define ADC_EXTERNALTRIGCONV_T3_CC4 ADC1_2_EXTERNALTRIG_T3_CC4
+#define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO
+#define ADC_EXTERNALTRIGCONV_T4_CC4 ADC1_2_EXTERNALTRIG_T4_CC4
+#define ADC_EXTERNALTRIGCONV_T4_TRGO ADC1_2_EXTERNALTRIG_T4_TRGO
+#define ADC_EXTERNALTRIGCONV_T8_TRGO ADC1_2_EXTERNALTRIG_T8_TRGO
+#define ADC_EXTERNALTRIGCONV_T8_TRGO2 ADC1_2_EXTERNALTRIG_T8_TRGO2
+#define ADC_EXTERNALTRIGCONV_T6_TRGO ADC1_2_EXTERNALTRIG_T6_TRGO
+#define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_2_EXTERNALTRIG_T15_TRGO
+#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11
+#define ADC_SOFTWARE_START (0x00000001U)
+
+#endif /* STM32F303x8 || STM32F328xx */
+
+#if defined(STM32F334x8)
+/*!< List of external triggers with generic trigger name, independently of */
+/* ADC target (caution: applies to other ADCs sharing the same common group), */
+/* sorted by trigger name: */
+
+/*!< External triggers of regular group for ADC1&ADC2 */
+#define ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_2_EXTERNALTRIG_T1_CC1
+#define ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_2_EXTERNALTRIG_T1_CC2
+#define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_2_EXTERNALTRIG_T1_CC3
+#define ADC_EXTERNALTRIGCONV_T1_TRGO ADC1_2_EXTERNALTRIG_T1_TRGO
+#define ADC_EXTERNALTRIGCONV_T1_TRGO2 ADC1_2_EXTERNALTRIG_T1_TRGO2
+#define ADC_EXTERNALTRIGCONV_T2_CC2 ADC1_2_EXTERNALTRIG_T2_CC2
+#define ADC_EXTERNALTRIGCONV_T2_TRGO ADC1_2_EXTERNALTRIG_T2_TRGO
+#define ADC_EXTERNALTRIGCONV_T3_CC4 ADC1_2_EXTERNALTRIG_T3_CC4
+#define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO
+#define ADC_EXTERNALTRIGCONV_T6_TRGO ADC1_2_EXTERNALTRIG_T6_TRGO
+#define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_2_EXTERNALTRIG_T15_TRGO
+#define ADC_EXTERNALTRIGCONVHRTIM_TRG1 ADC1_2_EXTERNALTRIG_HRTIM_TRG1
+#define ADC_EXTERNALTRIGCONVHRTIM_TRG3 ADC1_2_EXTERNALTRIG_HRTIM_TRG3
+#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11
+#define ADC_SOFTWARE_START (0x00000001U)
+#endif /* STM32F334x8 */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/* List of external triggers with generic trigger name, sorted by trigger */
+/* name: */
+
+/* External triggers of regular group for ADC1 */
+#define ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_EXTERNALTRIG_T1_CC1
+#define ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_EXTERNALTRIG_T1_CC2
+#define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_EXTERNALTRIG_T1_CC3
+#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_EXTERNALTRIG_EXT_IT11
+#define ADC_EXTERNALTRIGCONV_T1_TRGO ADC1_EXTERNALTRIG_T1_TRGO
+#define ADC_EXTERNALTRIGCONV_T1_TRGO2 ADC1_EXTERNALTRIG_T1_TRGO2
+#define ADC_EXTERNALTRIGCONV_T2_TRGO ADC1_EXTERNALTRIG_T2_TRGO
+#define ADC_EXTERNALTRIGCONV_T6_TRGO ADC1_EXTERNALTRIG_T6_TRGO
+#define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_EXTERNALTRIG_T15_TRGO
+#define ADC_SOFTWARE_START (0x00000001U)
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_EOCSelection ADC Extended End of Regular Sequence/Conversion
+ * @{
+ */
+#define ADC_EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC)
+#define ADC_EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS)
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_Overrun ADC Extended overrun
+ * @{
+ */
+#define ADC_OVR_DATA_OVERWRITTEN (0x00000000U) /*!< Default setting, to be used for compatibility with other STM32 devices */
+#define ADC_OVR_DATA_PRESERVED (0x00000001U)
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_channels ADC Extended Channels
+ * @{
+ */
+/* Note: Depending on devices, some channels may not be available on package */
+/* pins. Refer to device datasheet for channels availability. */
+#define ADC_CHANNEL_1 ((uint32_t)(ADC_SQR3_SQ10_0))
+#define ADC_CHANNEL_2 ((uint32_t)(ADC_SQR3_SQ10_1))
+#define ADC_CHANNEL_3 ((uint32_t)(ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))
+#define ADC_CHANNEL_4 ((uint32_t)(ADC_SQR3_SQ10_2))
+#define ADC_CHANNEL_5 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_0))
+#define ADC_CHANNEL_6 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1))
+#define ADC_CHANNEL_7 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))
+#define ADC_CHANNEL_8 ((uint32_t)(ADC_SQR3_SQ10_3))
+#define ADC_CHANNEL_9 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_0))
+#define ADC_CHANNEL_10 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_1))
+#define ADC_CHANNEL_11 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))
+#define ADC_CHANNEL_12 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2))
+#define ADC_CHANNEL_13 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_0))
+#define ADC_CHANNEL_14 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1))
+#define ADC_CHANNEL_15 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))
+#define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ10_4))
+#define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_0))
+#define ADC_CHANNEL_18 ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_1))
+
+/* Note: Vopamp1, TempSensor and Vbat internal channels available on ADC1 only */
+#define ADC_CHANNEL_VOPAMP1 ADC_CHANNEL_15
+#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16
+#define ADC_CHANNEL_VBAT ADC_CHANNEL_17
+
+/* Note: Vopamp2/3U/4 internal channels available on ADC2/3U/4 respectively */
+#define ADC_CHANNEL_VOPAMP2 ADC_CHANNEL_17
+#define ADC_CHANNEL_VOPAMP3 ADC_CHANNEL_17
+#define ADC_CHANNEL_VOPAMP4 ADC_CHANNEL_17
+
+/* Note: VrefInt internal channels available on all ADCs, but only */
+/* one ADC is allowed to be connected to VrefInt at the same time. */
+#define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_18)
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_sampling_times ADC Extended Sampling Times
+ * @{
+ */
+#define ADC_SAMPLETIME_1CYCLE_5 (0x00000000U) /*!< Sampling time 1.5 ADC clock cycle */
+#define ADC_SAMPLETIME_2CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_0) /*!< Sampling time 2.5 ADC clock cycles */
+#define ADC_SAMPLETIME_4CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_1) /*!< Sampling time 4.5 ADC clock cycles */
+#define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0)) /*!< Sampling time 7.5 ADC clock cycles */
+#define ADC_SAMPLETIME_19CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_2) /*!< Sampling time 19.5 ADC clock cycles */
+#define ADC_SAMPLETIME_61CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0)) /*!< Sampling time 61.5 ADC clock cycles */
+#define ADC_SAMPLETIME_181CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1)) /*!< Sampling time 181.5 ADC clock cycles */
+#define ADC_SAMPLETIME_601CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10) /*!< Sampling time 601.5 ADC clock cycles */
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_SingleDifferential ADC Extended Single-ended/Differential input mode
+ * @{
+ */
+#define ADC_SINGLE_ENDED (0x00000000U)
+#define ADC_DIFFERENTIAL_ENDED (0x00000001U)
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_OffsetNumber ADC Extended Offset Number
+ * @{
+ */
+#define ADC_OFFSET_NONE (0x00U)
+#define ADC_OFFSET_1 (0x01U)
+#define ADC_OFFSET_2 (0x02U)
+#define ADC_OFFSET_3 (0x03U)
+#define ADC_OFFSET_4 (0x04U)
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_regular_rank ADC Extended rank into regular group
+ * @{
+ */
+#define ADC_REGULAR_RANK_1 (0x00000001U)
+#define ADC_REGULAR_RANK_2 (0x00000002U)
+#define ADC_REGULAR_RANK_3 (0x00000003U)
+#define ADC_REGULAR_RANK_4 (0x00000004U)
+#define ADC_REGULAR_RANK_5 (0x00000005U)
+#define ADC_REGULAR_RANK_6 (0x00000006U)
+#define ADC_REGULAR_RANK_7 (0x00000007U)
+#define ADC_REGULAR_RANK_8 (0x00000008U)
+#define ADC_REGULAR_RANK_9 (0x00000009U)
+#define ADC_REGULAR_RANK_10 (0x0000000AU)
+#define ADC_REGULAR_RANK_11 (0x0000000BU)
+#define ADC_REGULAR_RANK_12 (0x0000000CU)
+#define ADC_REGULAR_RANK_13 (0x0000000DU)
+#define ADC_REGULAR_RANK_14 (0x0000000EU)
+#define ADC_REGULAR_RANK_15 (0x0000000FU)
+#define ADC_REGULAR_RANK_16 (0x00000010U)
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_injected_rank ADC Extended Injected Channel Rank
+ * @{
+ */
+#define ADC_INJECTED_RANK_1 (0x00000001U)
+#define ADC_INJECTED_RANK_2 (0x00000002U)
+#define ADC_INJECTED_RANK_3 (0x00000003U)
+#define ADC_INJECTED_RANK_4 (0x00000004U)
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_External_trigger_edge_Injected External Trigger Edge of Injected Group
+ * @{
+ */
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000U)
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_JSQR_JEXTEN_0)
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING ((uint32_t)ADC_JSQR_JEXTEN_1)
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING ((uint32_t)ADC_JSQR_JEXTEN)
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_External_trigger_source_Injected External Trigger Source of Injected Group
+ * @{
+ */
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+/* List of external triggers with generic trigger name, independently of ADC */
+/* target (caution: applies to other ADCs sharing the same common group), */
+/* sorted by trigger name: */
+
+/* External triggers of injected group for ADC1&ADC2 only */
+#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC1_2_EXTERNALTRIGINJEC_T2_CC1
+#define ADC_EXTERNALTRIGINJECCONV_T3_CC1 ADC1_2_EXTERNALTRIGINJEC_T3_CC1
+#define ADC_EXTERNALTRIGINJECCONV_T3_CC3 ADC1_2_EXTERNALTRIGINJEC_T3_CC3
+#define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4
+#define ADC_EXTERNALTRIGINJECCONV_T6_TRGO ADC1_2_EXTERNALTRIGINJEC_T6_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
+
+/* External triggers of injected group for ADC3&ADC4 only */
+#define ADC_EXTERNALTRIGINJECCONV_T1_CC3 ADC3_4_EXTERNALTRIGINJEC_T1_CC3
+#define ADC_EXTERNALTRIGINJECCONV_T4_CC3 ADC3_4_EXTERNALTRIGINJEC_T4_CC3
+#define ADC_EXTERNALTRIGINJECCONV_T4_CC4 ADC3_4_EXTERNALTRIGINJEC_T4_CC4
+#define ADC_EXTERNALTRIGINJECCONV_T7_TRGO ADC3_4_EXTERNALTRIGINJEC_T7_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T8_CC2 ADC3_4_EXTERNALTRIGINJEC_T8_CC2
+
+/* External triggers of injected group for ADC1&ADC2, ADC3&ADC4 */
+/* Note: Triggers affected to group ADC1_2 by default, redirected to group */
+/* ADC3_4 by driver when needed. */
+#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_2_EXTERNALTRIGINJEC_T1_CC4
+#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_2_EXTERNALTRIGINJEC_T1_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2 ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2
+#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC1_2_EXTERNALTRIGINJEC_T2_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T3_TRGO ADC1_2_EXTERNALTRIGINJEC_T3_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_T8_CC4
+#define ADC_EXTERNALTRIGINJECCONV_T8_TRGO ADC1_2_EXTERNALTRIGINJEC_T8_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T8_TRGO2 ADC1_2_EXTERNALTRIGINJEC_T8_TRGO2
+#define ADC_EXTERNALTRIGINJECCONV_T15_TRGO ADC1_2_EXTERNALTRIGINJEC_T15_TRGO
+
+#define ADC_INJECTED_SOFTWARE_START (0x00000001U)
+
+#if defined(STM32F303xE) || defined(STM32F398xx)
+/*!< List of external triggers specific to device STM303xE: using Timer20 */
+/* with ADC trigger input remap. */
+/* To remap ADC trigger from other timers/ExtLine to timer20: use macro */
+/* " __HAL_REMAPADCTRIGGER_ENABLE(...) " with parameters described below: */
+
+/*!< External triggers of injected group for ADC1&ADC2 only, specific to */
+/* device STM303xE: : using Timer20 with ADC trigger input remap */
+#define ADC_EXTERNALTRIGINJECCONV_T20_CC4 ADC_EXTERNALTRIGINJECCONV_T3_CC1 /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT13U) */
+
+/*!< External triggers of injected group for ADC3&ADC4 only, specific to */
+/* device STM303xE: : using Timer20 with ADC trigger input remap */
+#define ADC_EXTERNALTRIGINJECCONV_T20_CC2 ADC_EXTERNALTRIGINJECCONV_T7_TRGO /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_JEXT14U) */
+
+/*!< External triggers of regular group for ADC1&ADC2, ADC3&ADC4, specific to */
+/* device STM303xE: : using Timer20 with ADC trigger input remap */
+/* Note: Triggers affected to group ADC1_2 by default, redirected to group */
+/* ADC3_4 by driver when needed. */
+#define ADC_EXTERNALTRIGINJECCONV_T20_TRGO (ADC_EXTERNALTRIGINJECCONV_T2_CC1 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT3) */
+ /*!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_JEXT5) */
+#define ADC_EXTERNALTRIGINJECCONV_T20_TRGO2 (ADC_EXTERNALTRIGINJECCONV_EXT_IT15 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT6) */
+ /*!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_JEXT11U) */
+#endif /* STM32F303xE || STM32F398xx */
+
+#if defined(STM32F303xC) || defined(STM32F358xx)
+#define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
+ \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T7_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \
+ \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO2) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \
+ \
+ ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) )
+#endif /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)
+#define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
+ \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T7_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \
+ \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO2) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \
+ \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_CC2) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_TRGO2) || \
+ \
+ ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) )
+#endif /* STM32F303xE || STM32F398xx */
+
+#endif /* STM32F303xC || STM32F303xE || STM32F398xx || STM32F358xx */
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC)
+/*!< List of external triggers with generic trigger name, independently of */
+/* ADC target (caution: applies to other ADCs sharing the same common group), */
+/* sorted by trigger name: */
+
+/* External triggers of injected group for ADC1&ADC2 */
+#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_2_EXTERNALTRIGINJEC_T1_CC4
+#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_2_EXTERNALTRIGINJEC_T1_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2 ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2
+#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC1_2_EXTERNALTRIGINJEC_T2_CC1
+#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC1_2_EXTERNALTRIGINJEC_T2_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T3_CC1 ADC1_2_EXTERNALTRIGINJEC_T3_CC1
+#define ADC_EXTERNALTRIGINJECCONV_T3_CC3 ADC1_2_EXTERNALTRIGINJEC_T3_CC3
+#define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4
+#define ADC_EXTERNALTRIGINJECCONV_T3_TRGO ADC1_2_EXTERNALTRIGINJEC_T3_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T6_TRGO ADC1_2_EXTERNALTRIGINJEC_T6_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T15_TRGO ADC1_2_EXTERNALTRIGINJEC_T15_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
+
+#define ADC_INJECTED_SOFTWARE_START (0x00000001U)
+
+#if defined(STM32F302xE)
+/*!< List of external triggers specific to device STM302xE: using Timer20 */
+/* with ADC trigger input remap. */
+/* To remap ADC trigger from other timers/ExtLine to timer20: use macro */
+/* " __HAL_REMAPADCTRIGGER_ENABLE(...) " with parameters described below: */
+
+/*!< External triggers of injected group for ADC1&ADC2 only, specific to */
+/* device STM302xE: : using Timer20 with ADC trigger input remap */
+#define ADC_EXTERNALTRIGINJECCONV_T20_CC4 ADC_EXTERNALTRIGINJECCONV_T3_CC1 /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT13U) */
+#define ADC_EXTERNALTRIGINJECCONV_T20_TRGO (ADC_EXTERNALTRIGINJECCONV_T2_CC1 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT3) */
+#define ADC_EXTERNALTRIGINJECCONV_T20_TRGO2 (ADC_EXTERNALTRIGINJECCONV_EXT_IT15 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT6) */
+#endif /* STM32F302xE */
+
+#endif /* STM32F302xE || */
+ /* STM32F302xC */
+
+#if defined(STM32F303x8) || defined(STM32F328xx)
+/*!< List of external triggers with generic trigger name, independently of */
+/* ADC target (caution: applies to other ADCs sharing the same common group), */
+/* sorted by trigger name: */
+
+/* External triggers of injected group for ADC1&ADC2 */
+#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_2_EXTERNALTRIGINJEC_T1_CC4
+#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_2_EXTERNALTRIGINJEC_T1_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2 ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2
+#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC1_2_EXTERNALTRIGINJEC_T2_CC1
+#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC1_2_EXTERNALTRIGINJEC_T2_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T3_CC1 ADC1_2_EXTERNALTRIGINJEC_T3_CC1
+#define ADC_EXTERNALTRIGINJECCONV_T3_CC3 ADC1_2_EXTERNALTRIGINJEC_T3_CC3
+#define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4
+#define ADC_EXTERNALTRIGINJECCONV_T3_TRGO ADC1_2_EXTERNALTRIGINJEC_T3_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T6_TRGO ADC1_2_EXTERNALTRIGINJEC_T6_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_T8_CC4
+#define ADC_EXTERNALTRIGINJECCONV_T8_TRGO ADC1_2_EXTERNALTRIGINJEC_T8_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T8_TRGO2 ADC1_2_EXTERNALTRIGINJEC_T8_TRGO2
+#define ADC_EXTERNALTRIGINJECCONV_T15_TRGO ADC1_2_EXTERNALTRIGINJEC_T15_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
+
+#define ADC_INJECTED_SOFTWARE_START (0x00000001U)
+#endif /* STM32F303x8 || STM32F328xx */
+
+#if defined(STM32F334x8)
+/*!< List of external triggers with generic trigger name, independently of */
+/* ADC target (caution: applies to other ADCs sharing the same common group), */
+/* sorted by trigger name: */
+
+/* External triggers of injected group for ADC1&ADC2 */
+#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_2_EXTERNALTRIGINJEC_T1_CC4
+#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_2_EXTERNALTRIGINJEC_T1_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2 ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2
+#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC1_2_EXTERNALTRIGINJEC_T2_CC1
+#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC1_2_EXTERNALTRIGINJEC_T2_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T3_CC1 ADC1_2_EXTERNALTRIGINJEC_T3_CC1
+#define ADC_EXTERNALTRIGINJECCONV_T3_CC3 ADC1_2_EXTERNALTRIGINJEC_T3_CC3
+#define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4
+#define ADC_EXTERNALTRIGINJECCONV_T3_TRGO ADC1_2_EXTERNALTRIGINJEC_T3_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T6_TRGO ADC1_2_EXTERNALTRIGINJEC_T6_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T15_TRGO ADC1_2_EXTERNALTRIGINJEC_T15_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_HRTIM_TRG2 ADC1_2_EXTERNALTRIGINJEC_HRTIM_TRG2
+#define ADC_EXTERNALTRIGINJECCONV_HRTIM_TRG4 ADC1_2_EXTERNALTRIGINJEC_HRTIM_TRG4
+#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
+
+#define ADC_INJECTED_SOFTWARE_START (0x00000001U)
+#endif /* STM32F334x8 */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/* List of external triggers with generic trigger name, sorted by trigger */
+/* name: */
+
+/* External triggers of injected group for ADC1 */
+#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_EXTERNALTRIGINJEC_T1_CC4
+#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_EXTERNALTRIGINJEC_T1_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2 ADC1_EXTERNALTRIGINJEC_T1_TRGO2
+#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC1_EXTERNALTRIGINJEC_T2_CC1
+#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC1_EXTERNALTRIGINJEC_T2_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T6_TRGO ADC1_EXTERNALTRIGINJEC_T6_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T15_TRGO ADC1_EXTERNALTRIGINJEC_T15_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_EXTERNALTRIGINJEC_EXT_IT15
+
+#define ADC_INJECTED_SOFTWARE_START (0x00000001U)
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+/**
+ * @}
+ */
+
+
+/** @defgroup ADCEx_Common_mode ADC Extended Dual ADC Mode
+ * @{
+ */
+#define ADC_MODE_INDEPENDENT ((uint32_t)(0x00000000U))
+#define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC12_CCR_MULTI_0))
+#define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)(ADC12_CCR_MULTI_1))
+#define ADC_DUALMODE_REGINTERL_INJECSIMULT ((uint32_t)(ADC12_CCR_MULTI_1 | ADC12_CCR_MULTI_0))
+#define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC12_CCR_MULTI_2 | ADC12_CCR_MULTI_0))
+#define ADC_DUALMODE_REGSIMULT ((uint32_t)(ADC12_CCR_MULTI_2 | ADC12_CCR_MULTI_1))
+#define ADC_DUALMODE_INTERL ((uint32_t)(ADC12_CCR_MULTI_2 | ADC12_CCR_MULTI_1 | ADC12_CCR_MULTI_0))
+#define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC12_CCR_MULTI_3 | ADC12_CCR_MULTI_0))
+/**
+ * @}
+ */
+
+
+/** @defgroup ADCEx_Direct_memory_access_mode_for_multimode ADC Extended DMA Mode for Dual ADC Mode
+ * @{
+ */
+#define ADC_DMAACCESSMODE_DISABLED (0x00000000U) /*!< DMA multimode disabled: each ADC will use its own DMA channel */
+#define ADC_DMAACCESSMODE_12_10_BITS ((uint32_t)ADC12_CCR_MDMA_1) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 12 and 10 bits resolution */
+#define ADC_DMAACCESSMODE_8_6_BITS ((uint32_t)ADC12_CCR_MDMA) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 8 and 6 bits resolution */
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_delay_between_2_sampling_phases ADC Extended Delay Between 2 Sampling Phases
+ * @{
+ */
+#define ADC_TWOSAMPLINGDELAY_1CYCLE ((uint32_t)(0x00000000U))
+#define ADC_TWOSAMPLINGDELAY_2CYCLES ((uint32_t)(ADC12_CCR_DELAY_0))
+#define ADC_TWOSAMPLINGDELAY_3CYCLES ((uint32_t)(ADC12_CCR_DELAY_1))
+#define ADC_TWOSAMPLINGDELAY_4CYCLES ((uint32_t)(ADC12_CCR_DELAY_1 | ADC12_CCR_DELAY_0))
+#define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)(ADC12_CCR_DELAY_2))
+#define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)(ADC12_CCR_DELAY_2 | ADC12_CCR_DELAY_0))
+#define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)(ADC12_CCR_DELAY_2 | ADC12_CCR_DELAY_1))
+#define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC12_CCR_DELAY_2 | ADC12_CCR_DELAY_1 | ADC12_CCR_DELAY_0))
+#define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)(ADC12_CCR_DELAY_3))
+#define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC12_CCR_DELAY_3 | ADC12_CCR_DELAY_0))
+#define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC12_CCR_DELAY_3 | ADC12_CCR_DELAY_1))
+#define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC12_CCR_DELAY_3 | ADC12_CCR_DELAY_1 | ADC12_CCR_DELAY_0))
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_analog_watchdog_number ADC Extended Analog Watchdog Selection
+ * @{
+ */
+#define ADC_ANALOGWATCHDOG_1 (0x00000001U)
+#define ADC_ANALOGWATCHDOG_2 (0x00000002U)
+#define ADC_ANALOGWATCHDOG_3 (0x00000003U)
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_analog_watchdog_mode ADC Extended Analog Watchdog Mode
+ * @{
+ */
+#define ADC_ANALOGWATCHDOG_NONE ( 0x00000000U)
+#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN))
+#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN))
+#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN))
+#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CFGR_AWD1EN)
+#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CFGR_JAWD1EN)
+#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_conversion_group ADC Conversion Group
+ * @{
+ */
+#define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS))
+#define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC | ADC_FLAG_JEOS))
+#define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_JEOC | ADC_FLAG_JEOS))
+
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_Event_type ADC Extended Event Type
+ * @{
+ */
+#define ADC_AWD1_EVENT ((uint32_t)ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices) */
+#define ADC_AWD2_EVENT ((uint32_t)ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 families) */
+#define ADC_AWD3_EVENT ((uint32_t)ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families) */
+#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) /*!< ADC overrun event */
+#define ADC_JQOVF_EVENT ((uint32_t)ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */
+
+#define ADC_AWD_EVENT ADC_AWD1_EVENT /* ADC Analog watchdog 1 event: Alternate naming for compatibility with other STM32 devices having only 1 analog watchdog */
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_interrupts_definition ADC Extended Interrupts Definition
+ * @{
+ */
+#define ADC_IT_RDY ADC_IER_RDY /*!< ADC Ready (ADRDY) interrupt source */
+#define ADC_IT_EOSMP ADC_IER_EOSMP /*!< ADC End of Sampling interrupt source */
+#define ADC_IT_EOC ADC_IER_EOC /*!< ADC End of Regular Conversion interrupt source */
+#define ADC_IT_EOS ADC_IER_EOS /*!< ADC End of Regular sequence of Conversions interrupt source */
+#define ADC_IT_OVR ADC_IER_OVR /*!< ADC overrun interrupt source */
+#define ADC_IT_JEOC ADC_IER_JEOC /*!< ADC End of Injected Conversion interrupt source */
+#define ADC_IT_JEOS ADC_IER_JEOS /*!< ADC End of Injected sequence of Conversions interrupt source */
+#define ADC_IT_AWD1 ADC_IER_AWD1 /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog, present on all STM32 devices) */
+#define ADC_IT_AWD2 ADC_IER_AWD2 /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog, present only on STM32F3 devices) */
+#define ADC_IT_AWD3 ADC_IER_AWD3 /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog, present only on STM32F3 devices) */
+#define ADC_IT_JQOVF ADC_IER_JQOVF /*!< ADC Injected Context Queue Overflow interrupt source */
+
+#define ADC_IT_AWD ADC_IT_AWD1 /* ADC Analog watchdog 1 interrupt source: Alternate naming for compatibility with other STM32 devices having only 1 analog watchdog */
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_flags_definition ADC Extended Flags Definition
+ * @{
+ */
+#define ADC_FLAG_RDY ADC_ISR_ADRD /*!< ADC Ready (ADRDY) flag */
+#define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */
+#define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */
+#define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */
+#define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */
+#define ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC End of Injected Conversion flag */
+#define ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC End of Injected sequence of Conversions flag */
+#define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog, present on all STM32 devices) */
+#define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog, present only on STM32F3 devices) */
+#define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog, present only on STM32F3 devices) */
+#define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */
+
+#define ADC_FLAG_AWD ADC_FLAG_AWD1 /* ADC Analog watchdog 1 flag: Alternate naming for compatibility with other STM32 devices having only 1 analog watchdog */
+/**
+ * @}
+ */
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/** @defgroup ADCEx_Data_align ADC Extended Data Alignment
+ * @{
+ */
+#define ADC_DATAALIGN_RIGHT (0x00000000U)
+#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_Scan_mode ADC Extended Scan Mode
+ * @{
+ */
+#define ADC_SCAN_DISABLE (0x00000000U)
+#define ADC_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN)
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_External_trigger_edge_Regular ADC Extended External trigger enable for regular group
+ * @{
+ */
+#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000U)
+#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTTRIG)
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_External_trigger_source_Regular ADC Extended External trigger selection for regular group
+ * @{
+ */
+/* List of external triggers with generic trigger name, sorted by trigger */
+/* name: */
+
+/* External triggers of regular group for ADC1 */
+#define ADC_EXTERNALTRIGCONV_T2_CC2 ADC_EXTERNALTRIG_T2_CC2
+#define ADC_EXTERNALTRIGCONV_T3_TRGO ADC_EXTERNALTRIG_T3_TRGO
+#define ADC_EXTERNALTRIGCONV_T4_CC4 ADC_EXTERNALTRIG_T4_CC4
+#define ADC_EXTERNALTRIGCONV_T19_TRGO ADC_EXTERNALTRIG_T19_TRGO
+#define ADC_EXTERNALTRIGCONV_T19_CC3 ADC_EXTERNALTRIG_T19_CC3
+#define ADC_EXTERNALTRIGCONV_T19_CC4 ADC_EXTERNALTRIG_T19_CC4
+#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC_EXTERNALTRIG_EXT_IT11
+#define ADC_SOFTWARE_START ADC_SWSTART
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_channels ADC Extended Channels
+ * @{
+ */
+/* Note: Depending on devices, some channels may not be available on package */
+/* pins. Refer to device datasheet for channels availability. */
+#define ADC_CHANNEL_0 (0x00000000U)
+#define ADC_CHANNEL_1 ((uint32_t)(ADC_SQR3_SQ1_0))
+#define ADC_CHANNEL_2 ((uint32_t)(ADC_SQR3_SQ1_1))
+#define ADC_CHANNEL_3 ((uint32_t)(ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
+#define ADC_CHANNEL_4 ((uint32_t)(ADC_SQR3_SQ1_2))
+#define ADC_CHANNEL_5 ((uint32_t)(ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0))
+#define ADC_CHANNEL_6 ((uint32_t)(ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1))
+#define ADC_CHANNEL_7 ((uint32_t)(ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
+#define ADC_CHANNEL_8 ((uint32_t)(ADC_SQR3_SQ1_3))
+#define ADC_CHANNEL_9 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_0))
+#define ADC_CHANNEL_10 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1))
+#define ADC_CHANNEL_11 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
+#define ADC_CHANNEL_12 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2))
+#define ADC_CHANNEL_13 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0))
+#define ADC_CHANNEL_14 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1))
+#define ADC_CHANNEL_15 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
+#define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ1_4))
+#define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ1_4 | ADC_SQR3_SQ1_0))
+#define ADC_CHANNEL_18 ((uint32_t)(ADC_SQR3_SQ1_4 | ADC_SQR3_SQ1_1))
+
+#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16
+#define ADC_CHANNEL_VREFINT ADC_CHANNEL_17
+#define ADC_CHANNEL_VBAT ADC_CHANNEL_18
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_sampling_times ADC Extended Sampling Times
+ * @{
+ */
+#define ADC_SAMPLETIME_1CYCLE_5 (0x00000000U) /*!< Sampling time 1.5 ADC clock cycle */
+#define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t) ADC_SMPR2_SMP0_0) /*!< Sampling time 7.5 ADC clock cycles */
+#define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t) ADC_SMPR2_SMP0_1) /*!< Sampling time 13.5 ADC clock cycles */
+#define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 28.5 ADC clock cycles */
+#define ADC_SAMPLETIME_41CYCLES_5 ((uint32_t) ADC_SMPR2_SMP0_2) /*!< Sampling time 41.5 ADC clock cycles */
+#define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 55.5 ADC clock cycles */
+#define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1)) /*!< Sampling time 71.5 ADC clock cycles */
+#define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t) ADC_SMPR2_SMP0) /*!< Sampling time 239.5 ADC clock cycles */
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_regular_rank ADC Extended rank into regular group
+ * @{
+ */
+#define ADC_REGULAR_RANK_1 (0x00000001U)
+#define ADC_REGULAR_RANK_2 (0x00000002U)
+#define ADC_REGULAR_RANK_3 (0x00000003U)
+#define ADC_REGULAR_RANK_4 (0x00000004U)
+#define ADC_REGULAR_RANK_5 (0x00000005U)
+#define ADC_REGULAR_RANK_6 (0x00000006U)
+#define ADC_REGULAR_RANK_7 (0x00000007U)
+#define ADC_REGULAR_RANK_8 (0x00000008U)
+#define ADC_REGULAR_RANK_9 (0x00000009U)
+#define ADC_REGULAR_RANK_10 (0x0000000AU)
+#define ADC_REGULAR_RANK_11 (0x0000000BU)
+#define ADC_REGULAR_RANK_12 (0x0000000CU)
+#define ADC_REGULAR_RANK_13 (0x0000000DU)
+#define ADC_REGULAR_RANK_14 (0x0000000EU)
+#define ADC_REGULAR_RANK_15 (0x0000000FU)
+#define ADC_REGULAR_RANK_16 (0x00000010U)
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_injected_rank ADC Extended Injected Channel Rank
+ * @{
+ */
+#define ADC_INJECTED_RANK_1 (0x00000001U)
+#define ADC_INJECTED_RANK_2 (0x00000002U)
+#define ADC_INJECTED_RANK_3 (0x00000003U)
+#define ADC_INJECTED_RANK_4 (0x00000004U)
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_External_trigger_edge_Injected External Trigger Edge of Injected Group
+ * @{
+ */
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000U)
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_CR2_JEXTTRIG)
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_External_trigger_source_Injected External Trigger Source of Injected Group
+ * @{
+ */
+/* External triggers for injected groups of ADC1 */
+#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC_EXTERNALTRIGINJEC_T2_CC1
+#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC_EXTERNALTRIGINJEC_T2_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC_EXTERNALTRIGINJEC_T3_CC4
+#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC_EXTERNALTRIGINJEC_T4_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T19_CC1 ADC_EXTERNALTRIGINJEC_T19_CC1
+#define ADC_EXTERNALTRIGINJECCONV_T19_CC2 ADC_EXTERNALTRIGINJEC_T19_CC2
+#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC_EXTERNALTRIGINJEC_EXT_IT15
+#define ADC_INJECTED_SOFTWARE_START ADC_JSWSTART
+/**
+ * @}
+ */
+
+
+/** @defgroup ADCEx_analog_watchdog_mode ADC Extended analog watchdog mode
+ * @{
+ */
+#define ADC_ANALOGWATCHDOG_NONE (0x00000000U)
+#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
+#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
+#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
+#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CR1_AWDEN)
+#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CR1_JAWDEN)
+#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_conversion_group ADC Conversion Group
+ * @{
+ */
+#define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC))
+#define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC))
+#define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_JEOC))
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_Event_type ADC Extended Event Type
+ * @{
+ */
+#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /*!< ADC Analog watchdog event */
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_interrupts_definition ADC Extended Interrupts Definition
+ * @{
+ */
+#define ADC_IT_EOC ADC_CR1_EOCIE /*!< ADC End of Regular Conversion interrupt source */
+#define ADC_IT_JEOC ADC_CR1_JEOCIE /*!< ADC End of Injected Conversion interrupt source */
+#define ADC_IT_AWD ADC_CR1_AWDIE /*!< ADC Analog watchdog interrupt source */
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_flags_definition ADC Extended Flags Definition
+ * @{
+ */
+#define ADC_FLAG_AWD ADC_SR_AWD /*!< ADC Analog watchdog flag */
+#define ADC_FLAG_EOC ADC_SR_EOC /*!< ADC End of Regular conversion flag */
+#define ADC_FLAG_JEOC ADC_SR_JEOC /*!< ADC End of Injected conversion flag */
+#define ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC Injected group start flag */
+#define ADC_FLAG_STRT ADC_SR_STRT /*!< ADC Regular group start flag */
+
+/**
+ * @}
+ */
+#endif /* STM32F373xC || STM32F378xx */
+
+/**
+ * @}
+ */
+
+
+
+/* Private constants ---------------------------------------------------------*/
+
+/** @addtogroup ADCEx_Private_Constants ADCEx Private Constants
+ * @{
+ */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+
+
+/** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Regular ADC Extended Internal HAL driver trigger selection for regular group
+ * @{
+ */
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+/* List of external triggers for common groups ADC1&ADC2 and/or ADC3&ADC4: */
+/* (used internally by HAL driver. To not use into HAL structure parameters) */
+
+/* External triggers of regular group for ADC1 & ADC2 */
+#define ADC1_2_EXTERNALTRIG_T1_CC1 (0x00000000U)
+#define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0)
+#define ADC1_2_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1)
+#define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)ADC_CFGR_EXTSEL_2)
+#define ADC1_2_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
+#define ADC1_2_EXTERNALTRIG_T8_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_T8_TRGO2 ((uint32_t) ADC_CFGR_EXTSEL_3)
+#define ADC1_2_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1))
+#define ADC1_2_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2))
+#define ADC1_2_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
+#define ADC1_2_EXTERNALTRIG_T3_CC4 ((uint32_t)ADC_CFGR_EXTSEL)
+
+/* External triggers of regular group for ADC3 & ADC4 */
+#define ADC3_4_EXTERNALTRIG_T3_CC1 (0x00000000U)
+#define ADC3_4_EXTERNALTRIG_T2_CC3 ((uint32_t)ADC_CFGR_EXTSEL_0)
+#define ADC3_4_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1)
+#define ADC3_4_EXTERNALTRIG_T8_CC1 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
+#define ADC3_4_EXTERNALTRIG_T8_TRGO ((uint32_t)ADC_CFGR_EXTSEL_2)
+#define ADC3_4_EXTERNALTRIG_EXT_IT2 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
+#define ADC3_4_EXTERNALTRIG_T4_CC1 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
+#define ADC3_4_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
+#define ADC3_4_EXTERNALTRIG_T8_TRGO2 ((uint32_t)ADC_CFGR_EXTSEL_3)
+#define ADC3_4_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0))
+#define ADC3_4_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1))
+#define ADC3_4_EXTERNALTRIG_T3_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
+#define ADC3_4_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2))
+#define ADC3_4_EXTERNALTRIG_T7_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
+#define ADC3_4_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
+#define ADC3_4_EXTERNALTRIG_T2_CC1 ((uint32_t)ADC_CFGR_EXTSEL)
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC)
+/* List of external triggers of common group ADC1&ADC2: */
+/* (used internally by HAL driver. To not use into HAL structure parameters) */
+#define ADC1_2_EXTERNALTRIG_T1_CC1 (0x00000000U)
+#define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0)
+#define ADC1_2_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1)
+#define ADC1_2_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1))
+#define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_T3_CC4 ((uint32_t)ADC_CFGR_EXTSEL)
+#define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)ADC_CFGR_EXTSEL_2)
+#define ADC1_2_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2))
+#define ADC1_2_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
+#define ADC1_2_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
+#endif /* STM32F302xE || */
+ /* STM32F302xC */
+
+#if defined(STM32F303x8) || defined(STM32F328xx)
+/* List of external triggers of common group ADC1&ADC2: */
+/* (used internally by HAL driver. To not use into HAL structure parameters) */
+#define ADC1_2_EXTERNALTRIG_T1_CC1 (0x00000000U)
+#define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0)
+#define ADC1_2_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1)
+#define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)ADC_CFGR_EXTSEL_2)
+#define ADC1_2_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
+#define ADC1_2_EXTERNALTRIG_T8_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_T8_TRGO2 ((uint32_t) ADC_CFGR_EXTSEL_3)
+#define ADC1_2_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1))
+#define ADC1_2_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2))
+#define ADC1_2_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
+#define ADC1_2_EXTERNALTRIG_T3_CC4 ((uint32_t)ADC_CFGR_EXTSEL)
+#endif /* STM32F303x8 || STM32F328xx */
+
+#if defined(STM32F334x8)
+/* List of external triggers of common group ADC1&ADC2: */
+/* (used internally by HAL driver. To not use into HAL structure parameters) */
+#define ADC1_2_EXTERNALTRIG_T1_CC1 (0x00000000U)
+#define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0)
+#define ADC1_2_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1)
+#define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)ADC_CFGR_EXTSEL_2)
+#define ADC1_2_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
+#define ADC1_2_EXTERNALTRIG_HRTIM_TRG1 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_HRTIM_TRG3 ((uint32_t) ADC_CFGR_EXTSEL_3)
+#define ADC1_2_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1))
+#define ADC1_2_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
+#define ADC1_2_EXTERNALTRIG_T3_CC4 ((uint32_t)ADC_CFGR_EXTSEL)
+#endif /* STM32F334x8 */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/* List of external triggers of regular group for ADC1: */
+/* (used internally by HAL driver. To not use into HAL structure parameters) */
+#define ADC1_EXTERNALTRIG_T1_CC1 (0x00000000U)
+#define ADC1_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0)
+#define ADC1_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1)
+#define ADC1_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
+#define ADC1_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0))
+#define ADC1_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1))
+#define ADC1_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
+#define ADC1_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
+#define ADC1_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
+#define ADC_SOFTWARE_START (0x00000001U)
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+/**
+ * @}
+ */
+
+
+/** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Injected ADC Extended Internal HAL driver trigger selection for injected group
+ * @{
+ */
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+/* List of external triggers sorted of groups ADC1&ADC2 and/or ADC3&ADC4: */
+/* (used internally by HAL driver. To not use into HAL structure parameters) */
+
+/* External triggers for injected groups of ADC1 & ADC2 */
+#define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO (0x00000000U)
+#define ADC1_2_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0)
+#define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1)
+#define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
+#define ADC1_2_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2)
+#define ADC1_2_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
+#define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
+#define ADC1_2_EXTERNALTRIGINJEC_T8_CC4 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
+#define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3)
+#define ADC1_2_EXTERNALTRIGINJEC_T8_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0))
+#define ADC1_2_EXTERNALTRIGINJEC_T8_TRGO2 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1))
+#define ADC1_2_EXTERNALTRIGINJEC_T3_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
+#define ADC1_2_EXTERNALTRIGINJEC_T3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2))
+#define ADC1_2_EXTERNALTRIGINJEC_T3_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
+#define ADC1_2_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
+#define ADC1_2_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL)
+
+/* External triggers for injected groups of ADC3 & ADC4 */
+/* Note: External triggers JEXT2 and JEXT5 are the same (TIM4_CC3 event). */
+/* JEXT2 is the main trigger, JEXT5 could be redirected to another */
+/* in future devices. */
+/* However, this channel is implemented with a SW offset of 0x10000 for */
+/* differentiation between similar triggers of common groups ADC1&ADC2, */
+/* ADC3&ADC4 (Differentiation processed into macro */
+/* ADC_JSQR_JEXTSEL_SET) */
+#define ADC3_4_EXTERNALTRIGINJEC_T1_TRGO (0x00000000U)
+#define ADC3_4_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0)
+#define ADC3_4_EXTERNALTRIGINJEC_T4_CC3 ((uint32_t)ADC_JSQR_JEXTSEL_1 | 0x10000U)
+#define ADC3_4_EXTERNALTRIGINJEC_T8_CC2 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
+#define ADC3_4_EXTERNALTRIGINJEC_T8_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2)
+
+#if defined(STM32F303xE) || defined(STM32F398xx)
+#define ADC3_4_EXTERNALTRIGINJEC_T20_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
+#endif /* STM32F303xE || STM32F398xx */
+
+#define ADC3_4_EXTERNALTRIGINJEC_T4_CC4 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
+#define ADC3_4_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
+#define ADC3_4_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3)
+#define ADC3_4_EXTERNALTRIGINJEC_T8_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0))
+#define ADC3_4_EXTERNALTRIGINJEC_T8_TRGO2 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1))
+#define ADC3_4_EXTERNALTRIGINJEC_T1_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
+#define ADC3_4_EXTERNALTRIGINJEC_T3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2))
+#define ADC3_4_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
+#define ADC3_4_EXTERNALTRIGINJEC_T7_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
+#define ADC3_4_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL)
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC)
+/* List of external triggers of group ADC1&ADC2: */
+/* (used internally by HAL driver. To not use into HAL structure parameters) */
+#define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO (0x00000000U)
+#define ADC1_2_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0)
+#define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1)
+#define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
+#define ADC1_2_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2)
+#define ADC1_2_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
+#define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
+#define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3)
+#define ADC1_2_EXTERNALTRIGINJEC_T3_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
+#define ADC1_2_EXTERNALTRIGINJEC_T3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2))
+#define ADC1_2_EXTERNALTRIGINJEC_T3_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
+#define ADC1_2_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
+#define ADC1_2_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL)
+#endif /* STM32F302xE || */
+ /* STM32F302xC */
+
+#if defined(STM32F303x8) || defined(STM32F328xx)
+/* List of external triggers of group ADC1&ADC2: */
+/* (used internally by HAL driver. To not use into HAL structure parameters) */
+#define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO (0x00000000U)
+#define ADC1_2_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0)
+#define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1)
+#define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
+#define ADC1_2_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2)
+#define ADC1_2_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
+#define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
+#define ADC1_2_EXTERNALTRIGINJEC_T8_CC4 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
+#define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3)
+#define ADC1_2_EXTERNALTRIGINJEC_T8_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0))
+#define ADC1_2_EXTERNALTRIGINJEC_T8_TRGO2 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1))
+#define ADC1_2_EXTERNALTRIGINJEC_T3_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
+#define ADC1_2_EXTERNALTRIGINJEC_T3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2))
+#define ADC1_2_EXTERNALTRIGINJEC_T3_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
+#define ADC1_2_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
+#define ADC1_2_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL)
+#endif /* STM32F303x8 || STM32F328xx */
+
+#if defined(STM32F334x8)
+/* List of external triggers of group ADC1&ADC2: */
+/* (used internally by HAL driver. To not use into HAL structure parameters) */
+#define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO (0x00000000U)
+#define ADC1_2_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0)
+#define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1)
+#define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
+#define ADC1_2_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2)
+#define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
+#define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3)
+#define ADC1_2_EXTERNALTRIGINJEC_HRTIM_TRG2 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0))
+#define ADC1_2_EXTERNALTRIGINJEC_HRTIM_TRG4 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1))
+#define ADC1_2_EXTERNALTRIGINJEC_T3_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
+#define ADC1_2_EXTERNALTRIGINJEC_T3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2))
+#define ADC1_2_EXTERNALTRIGINJEC_T3_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
+#define ADC1_2_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
+#define ADC1_2_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL)
+#endif /* STM32F334x8 */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/* List of external triggers of injected group for ADC1: */
+/* (used internally by HAL driver. To not use into HAL structure parameters) */
+#define ADC1_EXTERNALTRIGINJEC_T1_TRGO (0x00000000U)
+#define ADC1_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0)
+#define ADC1_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1)
+#define ADC1_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
+#define ADC1_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
+#define ADC1_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3)
+#define ADC1_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
+#define ADC1_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL)
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+/**
+ * @}
+ */
+
+#define ADC_FLAG_ALL (ADC_FLAG_RDY | ADC_FLAG_EOSMP | ADC_FLAG_EOC | ADC_FLAG_EOS | \
+ ADC_FLAG_JEOC | ADC_FLAG_JEOS | ADC_FLAG_OVR | ADC_FLAG_AWD1 | \
+ ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | ADC_FLAG_JQOVF)
+
+/* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */
+#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_JEOC | ADC_FLAG_JEOS | \
+ ADC_FLAG_OVR | ADC_FLAG_AWD1 | ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | \
+ ADC_FLAG_JQOVF)
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+
+/** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Regular ADC Extended Internal HAL driver trigger selection for regular group
+ * @{
+ */
+/* List of external triggers of regular group for ADC1: */
+/* (used internally by HAL driver. To not use into HAL structure parameters) */
+
+/* External triggers of regular group for ADC1 */
+#define ADC_EXTERNALTRIG_T19_TRGO (0x00000000U)
+#define ADC_EXTERNALTRIG_T19_CC3 ((uint32_t)ADC_CR2_EXTSEL_0)
+#define ADC_EXTERNALTRIG_T19_CC4 ((uint32_t)ADC_CR2_EXTSEL_1)
+#define ADC_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
+#define ADC_EXTERNALTRIG_T3_TRGO ((uint32_t)ADC_CR2_EXTSEL_2)
+#define ADC_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
+#define ADC_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
+#define ADC_SWSTART ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Injected ADC Extended Internal HAL driver trigger selection for injected group
+ * @{
+ */
+/* List of external triggers of injected group for ADC1: */
+/* (used internally by HAL driver. To not use into HAL structure parameters) */
+
+/* External triggers of injected group for ADC1 */
+#define ADC_EXTERNALTRIGINJEC_T19_CC1 ( 0x00000000U)
+#define ADC_EXTERNALTRIGINJEC_T19_CC2 ((uint32_t) ADC_CR2_JEXTSEL_0)
+#define ADC_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t) ADC_CR2_JEXTSEL_1)
+#define ADC_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
+#define ADC_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t) ADC_CR2_JEXTSEL_2)
+#define ADC_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
+#define ADC_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
+#define ADC_JSWSTART ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_sampling_times_all_channels ADC Extended Sampling Times All Channels
+ * @{
+ */
+#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \
+ (ADC_SMPR2_SMP9_2 | ADC_SMPR2_SMP8_2 | ADC_SMPR2_SMP7_2 | ADC_SMPR2_SMP6_2 | \
+ ADC_SMPR2_SMP5_2 | ADC_SMPR2_SMP4_2 | ADC_SMPR2_SMP3_2 | ADC_SMPR2_SMP2_2 | \
+ ADC_SMPR2_SMP1_2 | ADC_SMPR2_SMP0_2)
+#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \
+ (ADC_SMPR1_SMP17_2 | ADC_SMPR1_SMP16_2 | ADC_SMPR1_SMP15_2 | ADC_SMPR1_SMP14_2 | \
+ ADC_SMPR1_SMP13_2 | ADC_SMPR1_SMP12_2 | ADC_SMPR1_SMP11_2 | ADC_SMPR1_SMP10_2 )
+
+#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \
+ (ADC_SMPR2_SMP9_1 | ADC_SMPR2_SMP8_1 | ADC_SMPR2_SMP7_1 | ADC_SMPR2_SMP6_1 | \
+ ADC_SMPR2_SMP5_1 | ADC_SMPR2_SMP4_1 | ADC_SMPR2_SMP3_1 | ADC_SMPR2_SMP2_1 | \
+ ADC_SMPR2_SMP1_1 | ADC_SMPR2_SMP0_1)
+#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \
+ (ADC_SMPR1_SMP17_1 | ADC_SMPR1_SMP16_1 | ADC_SMPR1_SMP15_1 | ADC_SMPR1_SMP14_1 | \
+ ADC_SMPR1_SMP13_1 | ADC_SMPR1_SMP12_1 | ADC_SMPR1_SMP11_1 | ADC_SMPR1_SMP10_1 )
+
+#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 \
+ (ADC_SMPR2_SMP9_0 | ADC_SMPR2_SMP8_0 | ADC_SMPR2_SMP7_0 | ADC_SMPR2_SMP6_0 | \
+ ADC_SMPR2_SMP5_0 | ADC_SMPR2_SMP4_0 | ADC_SMPR2_SMP3_0 | ADC_SMPR2_SMP2_0 | \
+ ADC_SMPR2_SMP1_0 | ADC_SMPR2_SMP0_0)
+#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \
+ (ADC_SMPR1_SMP17_0 | ADC_SMPR1_SMP16_0 | ADC_SMPR1_SMP15_0 | ADC_SMPR1_SMP14_0 | \
+ ADC_SMPR1_SMP13_0 | ADC_SMPR1_SMP12_0 | ADC_SMPR1_SMP11_0 | ADC_SMPR1_SMP10_0 )
+
+#define ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS (0x00000000U)
+#define ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
+#define ADC_SAMPLETIME_13CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
+#define ADC_SAMPLETIME_28CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
+#define ADC_SAMPLETIME_41CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2)
+#define ADC_SAMPLETIME_55CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
+#define ADC_SAMPLETIME_71CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
+#define ADC_SAMPLETIME_239CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
+
+#define ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS (0x00000000U)
+#define ADC_SAMPLETIME_7CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
+#define ADC_SAMPLETIME_13CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
+#define ADC_SAMPLETIME_28CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
+#define ADC_SAMPLETIME_41CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2)
+#define ADC_SAMPLETIME_55CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
+#define ADC_SAMPLETIME_71CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
+#define ADC_SAMPLETIME_239CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
+
+/* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */
+#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_JEOC | ADC_FLAG_AWD )
+/**
+ * @}
+ */
+
+#endif /* STM32F373xC || STM32F378xx */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup ADCEx_Exported_Macros ADCEx Exported Macros
+ * @{
+ */
+/* Macro for internal HAL driver usage, and possibly can be used into code of */
+/* final user. */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+
+/**
+ * @brief Enable the ADC peripheral
+ * @param __HANDLE__ ADC handle
+ * @note ADC enable requires a delay for ADC stabilization time
+ * (refer to device datasheet, parameter tSTAB)
+ * @note On STM32F3 devices, some hardware constraints must be strictly
+ * respected before using this macro:
+ * - ADC internal voltage regulator must be preliminarily enabled.
+ * This is performed by function HAL_ADC_Init().
+ * - ADC state requirements: ADC must be disabled, no conversion on
+ * going, no calibration on going.
+ * These checks are performed by functions HAL_ADC_start_xxx().
+ * @retval None
+ */
+#define __HAL_ADC_ENABLE(__HANDLE__) \
+ (SET_BIT((__HANDLE__)->Instance->CR, ADC_CR_ADEN))
+
+/**
+ * @brief Disable the ADC peripheral
+ * @param __HANDLE__ ADC handle
+ * @note On STM32F3 devices, some hardware constraints must be strictly
+ * respected before using this macro:
+ * - ADC state requirements: ADC must be enabled, no conversion on
+ * going.
+ * These checks are performed by functions HAL_ADC_start_xxx().
+ * @retval None
+ */
+#define __HAL_ADC_DISABLE(__HANDLE__) \
+ do{ \
+ SET_BIT((__HANDLE__)->Instance->CR, ADC_CR_ADDIS); \
+ __HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); \
+ } while(0U)
+
+/**
+ * @brief Enable the ADC end of conversion interrupt.
+ * @param __HANDLE__ ADC handle
+ * @param __INTERRUPT__ ADC Interrupt
+ * This parameter can be any combination of the following values:
+ * @arg ADC_IT_RDY: ADC Ready (ADRDY) interrupt source
+ * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source
+ * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
+ * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source
+ * @arg ADC_IT_OVR: ADC overrun interrupt source
+ * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
+ * @arg ADC_IT_JEOS: ADC End of Injected sequence of Conversions interrupt source
+ * @arg ADC_IT_AWD1: ADC Analog watchdog 1 interrupt source (main analog watchdog, present on all STM32 devices)
+ * @arg ADC_IT_AWD2: ADC Analog watchdog 2 interrupt source (additional analog watchdog, present only on STM32F3 devices)
+ * @arg ADC_IT_AWD3: ADC Analog watchdog 3 interrupt source (additional analog watchdog, present only on STM32F3 devices)
+ * @arg ADC_IT_JQOVF: ADC Injected Context Queue Overflow interrupt source
+ * @retval None
+ */
+#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
+ (SET_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__)))
+
+/**
+ * @brief Disable the ADC end of conversion interrupt.
+ * @param __HANDLE__ ADC handle
+ * @param __INTERRUPT__ ADC Interrupt
+ * This parameter can be any combination of the following values:
+ * @arg ADC_IT_RDY: ADC Ready (ADRDY) interrupt source
+ * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source
+ * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
+ * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source
+ * @arg ADC_IT_OVR: ADC overrun interrupt source
+ * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
+ * @arg ADC_IT_JEOS: ADC End of Injected sequence of Conversions interrupt source
+ * @arg ADC_IT_AWD1: ADC Analog watchdog 1 interrupt source (main analog watchdog, present on all STM32 devices)
+ * @arg ADC_IT_AWD2: ADC Analog watchdog 2 interrupt source (additional analog watchdog, present only on STM32F3 devices)
+ * @arg ADC_IT_AWD3: ADC Analog watchdog 3 interrupt source (additional analog watchdog, present only on STM32F3 devices)
+ * @arg ADC_IT_JQOVF: ADC Injected Context Queue Overflow interrupt source
+ * @retval None
+ */
+#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
+ (CLEAR_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__)))
+
+/** @brief Checks if the specified ADC interrupt source is enabled or disabled.
+ * @param __HANDLE__ ADC handle
+ * @param __INTERRUPT__ ADC interrupt source to check
+ * This parameter can be any combination of the following values:
+ * @arg ADC_IT_RDY: ADC Ready (ADRDY) interrupt source
+ * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source
+ * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
+ * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source
+ * @arg ADC_IT_OVR: ADC overrun interrupt source
+ * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
+ * @arg ADC_IT_JEOS: ADC End of Injected sequence of Conversions interrupt source
+ * @arg ADC_IT_AWD1: ADC Analog watchdog 1 interrupt source (main analog watchdog, present on all STM32 devices)
+ * @arg ADC_IT_AWD2: ADC Analog watchdog 2 interrupt source (additional analog watchdog, present only on STM32F3 devices)
+ * @arg ADC_IT_AWD3: ADC Analog watchdog 3 interrupt source (additional analog watchdog, present only on STM32F3 devices)
+ * @arg ADC_IT_JQOVF: ADC Injected Context Queue Overflow interrupt source
+ * @retval State of interruption (SET or RESET)
+ */
+#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+ * @brief Get the selected ADC's flag status.
+ * @param __HANDLE__ ADC handle
+ * @param __FLAG__ ADC flag
+ * This parameter can be any combination of the following values:
+ * @arg ADC_FLAG_RDY: ADC Ready (ADRDY) flag
+ * @arg ADC_FLAG_EOSMP: ADC End of Sampling flag
+ * @arg ADC_FLAG_EOC: ADC End of Regular Conversion flag
+ * @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag
+ * @arg ADC_FLAG_OVR: ADC overrun flag
+ * @arg ADC_FLAG_JEOC: ADC End of Injected Conversion flag
+ * @arg ADC_FLAG_JEOS: ADC End of Injected sequence of Conversions flag
+ * @arg ADC_FLAG_AWD1: ADC Analog watchdog 1 flag (main analog watchdog, present on all STM32 devices)
+ * @arg ADC_FLAG_AWD2: ADC Analog watchdog 2 flag (additional analog watchdog, present only on STM32F3 devices)
+ * @arg ADC_FLAG_AWD3: ADC Analog watchdog 3 flag (additional analog watchdog, present only on STM32F3 devices)
+ * @arg ADC_FLAG_JQOVF: ADC Injected Context Queue Overflow flag
+ * @retval None
+ */
+#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
+ ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Clear the ADC's pending flags
+ * @param __HANDLE__ ADC handle
+ * @param __FLAG__ ADC flag
+ * This parameter can be any combination of the following values:
+ * @arg ADC_FLAG_RDY: ADC Ready (ADRDY) flag
+ * @arg ADC_FLAG_EOSMP: ADC End of Sampling flag
+ * @arg ADC_FLAG_EOC: ADC End of Regular Conversion flag
+ * @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag
+ * @arg ADC_FLAG_OVR: ADC overrun flag
+ * @arg ADC_FLAG_JEOC: ADC End of Injected Conversion flag
+ * @arg ADC_FLAG_JEOS: ADC End of Injected sequence of Conversions flag
+ * @arg ADC_FLAG_AWD1: ADC Analog watchdog 1 flag (main analog watchdog, present on all STM32 devices)
+ * @arg ADC_FLAG_AWD2: ADC Analog watchdog 2 flag (additional analog watchdog, present only on STM32F3 devices)
+ * @arg ADC_FLAG_AWD3: ADC Analog watchdog 3 flag (additional analog watchdog, present only on STM32F3 devices)
+ * @arg ADC_FLAG_JQOVF: ADC Injected Context Queue Overflow flag
+ * @retval None
+ */
+/* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of */
+/* register ISR). */
+#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+ (WRITE_REG((__HANDLE__)->Instance->ISR, (__FLAG__)))
+
+/** @brief Reset ADC handle state
+ * @param __HANDLE__ ADC handle
+ * @retval None
+ */
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
+ ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+
+/**
+ * @brief Enable the ADC peripheral
+ * @note ADC enable requires a delay for ADC stabilization time
+ * (refer to device datasheet, parameter tSTAB)
+ * @note On STM32F37x devices, if ADC is already enabled this macro trigs
+ * a conversion SW start on regular group.
+ * @param __HANDLE__ ADC handle
+ * @retval None
+ */
+#define __HAL_ADC_ENABLE(__HANDLE__) \
+ (SET_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
+
+/**
+ * @brief Disable the ADC peripheral
+ * @param __HANDLE__ ADC handle
+ * @retval None
+ */
+#define __HAL_ADC_DISABLE(__HANDLE__) \
+ (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
+
+/** @brief Enable the ADC end of conversion interrupt.
+ * @param __HANDLE__ ADC handle
+ * @param __INTERRUPT__ ADC Interrupt
+ * This parameter can be any combination of the following values:
+ * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
+ * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
+ * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
+ * @retval None
+ */
+#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
+ (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
+
+/** @brief Disable the ADC end of conversion interrupt.
+ * @param __HANDLE__ ADC handle
+ * @param __INTERRUPT__ ADC Interrupt
+ * This parameter can be any combination of the following values:
+ * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
+ * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
+ * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
+ * @retval None
+ */
+#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
+ (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
+
+/** @brief Checks if the specified ADC interrupt source is enabled or disabled.
+ * @param __HANDLE__ ADC handle
+ * @param __INTERRUPT__ ADC interrupt source to check
+ * This parameter can be any combination of the following values:
+ * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
+ * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
+ * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
+ * @retval State of interruption (SET or RESET)
+ */
+#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/** @brief Get the selected ADC's flag status.
+ * @param __HANDLE__ ADC handle
+ * @param __FLAG__ ADC flag
+ * This parameter can be any combination of the following values:
+ * @arg ADC_FLAG_STRT: ADC Regular group start flag
+ * @arg ADC_FLAG_JSTRT: ADC Injected group start flag
+ * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
+ * @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
+ * @arg ADC_FLAG_AWD: ADC Analog watchdog flag
+ * @retval None
+ */
+#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
+ ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the ADC's pending flags
+ * @param __HANDLE__ ADC handle
+ * @param __FLAG__ ADC flag
+ * This parameter can be any combination of the following values:
+ * @arg ADC_FLAG_STRT: ADC Regular group start flag
+ * @arg ADC_FLAG_JSTRT: ADC Injected group start flag
+ * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
+ * @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
+ * @arg ADC_FLAG_AWD: ADC Analog watchdog flag
+ * @retval None
+ */
+#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+ (WRITE_REG((__HANDLE__)->Instance->SR, ~(__FLAG__)))
+
+/** @brief Reset ADC handle state
+ * @param __HANDLE__ ADC handle
+ * @retval None
+ */
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
+ ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
+#endif /* STM32F373xC || STM32F378xx */
+
+/**
+ * @}
+ */
+
+/* Private macro ------------------------------------------------------------*/
+
+/** @addtogroup ADCEx_Private_Macro ADCEx Private Macros
+ * @{
+ */
+/* Macro reserved for internal HAL driver usage, not intended to be used in */
+/* code of final user. */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+
+/**
+ * @brief Verification of hardware constraints before ADC can be enabled
+ * @param __HANDLE__ ADC handle
+ * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled)
+ */
+#define ADC_ENABLING_CONDITIONS(__HANDLE__) \
+ (( HAL_IS_BIT_CLR((__HANDLE__)->Instance->CR , \
+ (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | \
+ ADC_CR_JADSTART |ADC_CR_ADSTART | ADC_CR_ADDIS | \
+ ADC_CR_ADEN ) ) \
+ ) ? SET : RESET)
+
+/**
+ * @brief Verification of ADC state: enabled or disabled
+ * @param __HANDLE__ ADC handle
+ * @retval SET (ADC enabled) or RESET (ADC disabled)
+ */
+#define ADC_IS_ENABLE(__HANDLE__) \
+ (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
+ ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \
+ ) ? SET : RESET)
+
+/**
+ * @brief Test if conversion trigger of regular group is software start
+ * or external trigger.
+ * @param __HANDLE__ ADC handle
+ * @retval SET (software start) or RESET (external trigger)
+ */
+#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
+ (((__HANDLE__)->Instance->CFGR & ADC_CFGR_EXTEN) == RESET)
+
+/**
+ * @brief Test if conversion trigger of injected group is software start
+ * or external trigger.
+ * @param __HANDLE__ ADC handle
+ * @retval SET (software start) or RESET (external trigger)
+ */
+#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
+ (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == RESET)
+
+/**
+ * @brief Check if no conversion on going on regular and/or injected groups
+ * @param __HANDLE__ ADC handle
+ * @retval SET (conversion is on going) or RESET (no conversion is on going)
+ */
+#define ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__) \
+ (( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART | ADC_CR_JADSTART)) == RESET \
+ ) ? RESET : SET)
+
+/**
+ * @brief Check if no conversion on going on regular group
+ * @param __HANDLE__ ADC handle
+ * @retval SET (conversion is on going) or RESET (no conversion is on going)
+ */
+#define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \
+ (( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET \
+ ) ? RESET : SET)
+
+/**
+ * @brief Check if no conversion on going on injected group
+ * @param __HANDLE__ ADC handle
+ * @retval SET (conversion is on going) or RESET (no conversion is on going)
+ */
+#define ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__) \
+ (( (((__HANDLE__)->Instance->CR) & ADC_CR_JADSTART) == RESET \
+ ) ? RESET : SET)
+
+/**
+ * @brief Returns resolution bits in CFGR1 register: RES[1:0].
+ * Returned value is among parameters to @ref ADCEx_Resolution.
+ * @param __HANDLE__ ADC handle
+ * @retval None
+ */
+#define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)
+
+/**
+ * @brief Simultaneously clears and sets specific bits of the handle State
+ * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
+ * the first parameter is the ADC handle State, the second parameter is the
+ * bit field to clear, the third and last parameter is the bit field to set.
+ * @retval None
+ */
+#define ADC_STATE_CLR_SET MODIFY_REG
+
+/**
+ * @brief Clear ADC error code (set it to error code: "no error")
+ * @param __HANDLE__ ADC handle
+ * @retval None
+ */
+#define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
+
+/**
+ * @brief Set the ADC's sample time for Channels numbers between 0 and 9.
+ * @param _SAMPLETIME_ Sample time parameter.
+ * @param _CHANNELNB_ Channel number.
+ * @retval None
+ */
+#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * (_CHANNELNB_)))
+
+/**
+ * @brief Set the ADC's sample time for Channels numbers between 10 and 18.
+ * @param _SAMPLETIME_ Sample time parameter.
+ * @param _CHANNELNB_ Channel number.
+ * @retval None
+ */
+#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * ((_CHANNELNB_) - 10U)))
+
+/**
+ * @brief Set the selected regular Channel rank for rank between 1 and 4.
+ * @param _CHANNELNB_ Channel number.
+ * @param _RANKNB_ Rank number.
+ * @retval None
+ */
+#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6U * (_RANKNB_)))
+
+/**
+ * @brief Set the selected regular Channel rank for rank between 5 and 9.
+ * @param _CHANNELNB_ Channel number.
+ * @param _RANKNB_ Rank number.
+ * @retval None
+ */
+#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6U * ((_RANKNB_) - 5U)))
+
+/**
+ * @brief Set the selected regular Channel rank for rank between 10 and 14.
+ * @param _CHANNELNB_ Channel number.
+ * @param _RANKNB_ Rank number.
+ * @retval None
+ */
+#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6U * ((_RANKNB_) - 10U)))
+
+/**
+ * @brief Set the selected regular Channel rank for rank between 15 and 16.
+ * @param _CHANNELNB_ Channel number.
+ * @param _RANKNB_ Rank number.
+ * @retval None
+ */
+#define ADC_SQR4_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6U * ((_RANKNB_) - 15U)))
+
+/**
+ * @brief Set the selected injected Channel rank.
+ * @param _CHANNELNB_ Channel number.
+ * @param _RANKNB_ Rank number.
+ * @retval None
+ */
+#define ADC_JSQR_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6U * (_RANKNB_) +2U))
+
+
+/**
+ * @brief Set the Analog Watchdog 1 channel.
+ * @param _CHANNEL_ channel to be monitored by Analog Watchdog 1.
+ * @retval None
+ */
+#define ADC_CFGR_AWD1CH_SHIFT(_CHANNEL_) ((_CHANNEL_) << 26U)
+
+/**
+ * @brief Configure the channel number into Analog Watchdog 2 or 3.
+ * @param _CHANNEL_ ADC Channel
+ * @retval None
+ */
+#define ADC_CFGR_AWD23CR(_CHANNEL_) (1U << (_CHANNEL_))
+
+/**
+ * @brief Enable automatic conversion of injected group
+ * @param _INJECT_AUTO_CONVERSION_ Injected automatic conversion.
+ * @retval None
+ */
+#define ADC_CFGR_INJECT_AUTO_CONVERSION(_INJECT_AUTO_CONVERSION_) ((_INJECT_AUTO_CONVERSION_) << 25U)
+
+/**
+ * @brief Enable ADC injected context queue
+ * @param _INJECT_CONTEXT_QUEUE_MODE_ Injected context queue mode.
+ * @retval None
+ */
+#define ADC_CFGR_INJECT_CONTEXT_QUEUE(_INJECT_CONTEXT_QUEUE_MODE_) ((_INJECT_CONTEXT_QUEUE_MODE_) << 21U)
+
+/**
+ * @brief Enable ADC discontinuous conversion mode for injected group
+ * @param _INJECT_DISCONTINUOUS_MODE_ Injected discontinuous mode.
+ * @retval None
+ */
+#define ADC_CFGR_INJECT_DISCCONTINUOUS(_INJECT_DISCONTINUOUS_MODE_) ((_INJECT_DISCONTINUOUS_MODE_) << 20U)
+
+/**
+ * @brief Enable ADC discontinuous conversion mode for regular group
+ * @param _REG_DISCONTINUOUS_MODE_ Regular discontinuous mode.
+ * @retval None
+ */
+#define ADC_CFGR_REG_DISCCONTINUOUS(_REG_DISCONTINUOUS_MODE_) ((_REG_DISCONTINUOUS_MODE_) << 16U)
+
+/**
+ * @brief Configures the number of discontinuous conversions for regular group.
+ * @param _NBR_DISCONTINUOUS_CONV_ Number of discontinuous conversions.
+ * @retval None
+ */
+#define ADC_CFGR_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_) - 1U) << 17U)
+
+/**
+ * @brief Enable the ADC auto delay mode.
+ * @param _AUTOWAIT_ Auto delay bit enable or disable.
+ * @retval None
+ */
+#define ADC_CFGR_AUTOWAIT(_AUTOWAIT_) ((_AUTOWAIT_) << 14U)
+
+/**
+ * @brief Enable ADC continuous conversion mode.
+ * @param _CONTINUOUS_MODE_ Continuous mode.
+ * @retval None
+ */
+#define ADC_CFGR_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 13U)
+
+/**
+ * @brief Enable ADC overrun mode.
+ * @param _OVERRUN_MODE_ Overrun mode.
+ * @retval Overrun bit setting to be programmed into CFGR register
+ */
+/* Note: Bit ADC_CFGR_OVRMOD not used directly in constant */
+/* "ADC_OVR_DATA_OVERWRITTEN" to have this case defined to 0x00U, to set it */
+/* as the default case to be compliant with other STM32 devices. */
+#define ADC_CFGR_OVERRUN(_OVERRUN_MODE_) \
+ ( ( (_OVERRUN_MODE_) != (ADC_OVR_DATA_PRESERVED) \
+ )? (ADC_CFGR_OVRMOD) : (0x00000000U) \
+ )
+
+/**
+ * @brief Enable the ADC DMA continuous request.
+ * @param _DMACONTREQ_MODE_ DMA continuous request mode.
+ * @retval None
+ */
+#define ADC_CFGR_DMACONTREQ(_DMACONTREQ_MODE_) ((_DMACONTREQ_MODE_) << 1U)
+
+/**
+ * @brief For devices with 3 ADCs or more: Defines the external trigger source
+ * for regular group according to ADC into common group ADC1&ADC2 or
+ * ADC3&ADC4 (some triggers with same source have different value to
+ * be programmed into ADC EXTSEL bits of CFGR register).
+ * Note: No risk of trigger bits value of common group ADC1&ADC2
+ * misleading to another trigger at same bits value, because the 3
+ * exceptions below are circular and do not point to any other trigger
+ * with direct treatment.
+ * For devices with 2 ADCs or less: this macro makes no change.
+ * @param __HANDLE__ ADC handle
+ * @param __EXT_TRIG_CONV__ External trigger selected for regular group.
+ * @retval External trigger to be programmed into EXTSEL bits of CFGR register
+ */
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+
+#if defined(STM32F303xC) || defined(STM32F358xx)
+#define ADC_CFGR_EXTSEL_SET(__HANDLE__, __EXT_TRIG_CONV__) \
+ (( ((((__HANDLE__)->Instance) == ADC3) || (((__HANDLE__)->Instance) == ADC4)) \
+ )? \
+ ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T2_TRGO \
+ )? \
+ (ADC3_4_EXTERNALTRIG_T2_TRGO) \
+ : \
+ ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T3_TRGO \
+ )? \
+ (ADC3_4_EXTERNALTRIG_T3_TRGO) \
+ : \
+ ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T8_TRGO \
+ )? \
+ (ADC3_4_EXTERNALTRIG_T8_TRGO) \
+ : \
+ (__EXT_TRIG_CONV__) \
+ ) \
+ ) \
+ ) \
+ : \
+ (__EXT_TRIG_CONV__) \
+ )
+#endif /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)
+/* Note: Macro including external triggers specific to device STM303xE: using */
+/* Timer20 with ADC trigger input remap. */
+#define ADC_CFGR_EXTSEL_SET(__HANDLE__, __EXT_TRIG_CONV__) \
+ (( ((((__HANDLE__)->Instance) == ADC3) || (((__HANDLE__)->Instance) == ADC4)) \
+ )? \
+ ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T2_TRGO \
+ )? \
+ (ADC3_4_EXTERNALTRIG_T2_TRGO) \
+ : \
+ ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T3_TRGO \
+ )? \
+ (ADC3_4_EXTERNALTRIG_T3_TRGO) \
+ : \
+ ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T8_TRGO \
+ )? \
+ (ADC3_4_EXTERNALTRIG_T8_TRGO) \
+ : \
+ ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T20_CC1 \
+ )? \
+ (ADC3_4_EXTERNALTRIG_T2_CC1) \
+ : \
+ ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T20_TRGO \
+ )? \
+ (ADC3_4_EXTERNALTRIG_EXT_IT2) \
+ : \
+ ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T20_TRGO2 \
+ )? \
+ (ADC3_4_EXTERNALTRIG_T4_CC1) \
+ : \
+ (__EXT_TRIG_CONV__) \
+ ) \
+ ) \
+ ) \
+ ) \
+ ) \
+ ) \
+ : \
+ (__EXT_TRIG_CONV__ & (~ADC_EXTERNALTRIGCONV_T20_MASK)) \
+ )
+#endif /* STM32F303xE || STM32F398xx */
+#else
+#define ADC_CFGR_EXTSEL_SET(__HANDLE__, __EXT_TRIG_CONV__) \
+ (__EXT_TRIG_CONV__)
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+/**
+ * @brief For devices with 3 ADCs or more: Defines the external trigger source
+ * for injected group according to ADC into common group ADC1&ADC2 or
+ * ADC3&ADC4 (some triggers with same source have different value to
+ * be programmed into ADC JEXTSEL bits of JSQR register).
+ * Note: No risk of trigger bits value of common group ADC1&ADC2
+ * misleading to another trigger at same bits value, because the 3
+ * exceptions below are circular and do not point to any other trigger
+ * with direct treatment, except trigger
+ * ADC_EXTERNALTRIGINJECCONV_T4_CC3 differentiated with SW offset.
+ * For devices with 2 ADCs or less: this macro makes no change.
+ * @param __HANDLE__ ADC handle
+ * @param __EXT_TRIG_INJECTCONV__ External trigger selected for injected group
+ * @retval External trigger to be programmed into JEXTSEL bits of JSQR register
+ */
+#if defined(STM32F303xC) || defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F358xx)
+#if defined(STM32F303xC) || defined(STM32F358xx)
+#define ADC_JSQR_JEXTSEL_SET(__HANDLE__, __EXT_TRIG_INJECTCONV__) \
+ (( ((((__HANDLE__)->Instance) == ADC3) || (((__HANDLE__)->Instance) == ADC4)) \
+ )? \
+ ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO \
+ )? \
+ (ADC3_4_EXTERNALTRIGINJEC_T2_TRGO) \
+ : \
+ ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO \
+ )? \
+ (ADC3_4_EXTERNALTRIGINJEC_T4_TRGO) \
+ : \
+ ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4 \
+ )? \
+ (ADC3_4_EXTERNALTRIGINJEC_T8_CC4) \
+ : \
+ ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T4_CC3 \
+ )? \
+ (ADC3_4_EXTERNALTRIGINJEC_T4_CC3) \
+ : \
+ (__EXT_TRIG_INJECTCONV__) \
+ ) \
+ ) \
+ ) \
+ ) \
+ : \
+ (__EXT_TRIG_INJECTCONV__) \
+ )
+#endif /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)
+/* Note: Macro including external triggers specific to device STM303xE: using */
+/* Timer20 with ADC trigger input remap. */
+#define ADC_JSQR_JEXTSEL_SET(__HANDLE__, __EXT_TRIG_INJECTCONV__) \
+ (( ((((__HANDLE__)->Instance) == ADC3) || (((__HANDLE__)->Instance) == ADC4)) \
+ )? \
+ ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO \
+ )? \
+ (ADC3_4_EXTERNALTRIGINJEC_T2_TRGO) \
+ : \
+ ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO \
+ )? \
+ (ADC3_4_EXTERNALTRIGINJEC_T4_TRGO) \
+ : \
+ ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4 \
+ )? \
+ (ADC3_4_EXTERNALTRIGINJEC_T8_CC4) \
+ : \
+ ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T4_CC3 \
+ )? \
+ (ADC3_4_EXTERNALTRIGINJEC_T4_CC3) \
+ : \
+ ( ( (__EXT_TRIG_INJECTCONV__) \
+ == ADC_EXTERNALTRIGINJECCONV_T20_TRGO \
+ )? \
+ (ADC3_4_EXTERNALTRIGINJEC_T20_TRGO) \
+ : \
+ ( ( (__EXT_TRIG_INJECTCONV__) \
+ == ADC_EXTERNALTRIGINJECCONV_T20_TRGO2 \
+ )? \
+ (ADC3_4_EXTERNALTRIGINJEC_T1_CC3) \
+ : \
+ (__EXT_TRIG_INJECTCONV__) \
+ ) \
+ ) \
+ ) \
+ ) \
+ ) \
+ ) \
+ : \
+ (__EXT_TRIG_INJECTCONV__ & (~ADC_EXTERNALTRIGCONV_T20_MASK)) \
+ )
+#endif /* STM32F303xE || STM32F398xx */
+#else
+#define ADC_JSQR_JEXTSEL_SET(__HANDLE__, __EXT_TRIG_INJECTCONV__) \
+ (__EXT_TRIG_INJECTCONV__)
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+/**
+ * @brief Configure the channel number into offset OFRx register
+ * @param _CHANNEL_ ADC Channel
+ * @retval None
+ */
+#define ADC_OFR_CHANNEL(_CHANNEL_) ((_CHANNEL_) << 26U)
+
+/**
+ * @brief Configure the channel number into differential mode selection register
+ * @param _CHANNEL_ ADC Channel
+ * @retval None
+ */
+#define ADC_DIFSEL_CHANNEL(_CHANNEL_) (1U << (_CHANNEL_))
+
+/**
+ * @brief Calibration factor in differential mode to be set into calibration register
+ * @param _Calibration_Factor_ Calibration factor value
+ * @retval None
+ */
+#define ADC_CALFACT_DIFF_SET(_Calibration_Factor_) ((_Calibration_Factor_) << 16U)
+
+/**
+ * @brief Calibration factor in differential mode to be retrieved from calibration register
+ * @param _Calibration_Factor_ Calibration factor value
+ * @retval None
+ */
+#define ADC_CALFACT_DIFF_GET(_Calibration_Factor_) ((_Calibration_Factor_) >> 16U)
+
+/**
+ * @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3.
+ * @param _Threshold_ Threshold value
+ * @retval None
+ */
+#define ADC_TRX_HIGHTHRESHOLD(_Threshold_) ((_Threshold_) << 16U)
+
+/**
+ * @brief Enable the ADC DMA continuous request for ADC multimode.
+ * @param _DMAContReq_MODE_ DMA continuous request mode.
+ * @retval None
+ */
+#define ADC_CCR_MULTI_DMACONTREQ(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 13U)
+
+/**
+ * @brief Verification of hardware constraints before ADC can be disabled
+ * @param __HANDLE__ ADC handle
+ * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled)
+ */
+#define ADC_DISABLING_CONDITIONS(__HANDLE__) \
+ (( ( ((__HANDLE__)->Instance->CR) & \
+ (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN \
+ ) ? SET : RESET)
+
+
+/**
+ * @brief Shift the offset in function of the selected ADC resolution.
+ * Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0
+ * If resolution 12 bits, no shift.
+ * If resolution 10 bits, shift of 2 ranks on the left.
+ * If resolution 8 bits, shift of 4 ranks on the left.
+ * If resolution 6 bits, shift of 6 ranks on the left.
+ * therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2))
+ * @param __HANDLE__ ADC handle
+ * @param _Offset_ Value to be shifted
+ * @retval None
+ */
+#define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, _Offset_) \
+ ((_Offset_) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3U)*2U))
+
+/**
+ * @brief Shift the AWD1 threshold in function of the selected ADC resolution.
+ * Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0.
+ * If resolution 12 bits, no shift.
+ * If resolution 10 bits, shift of 2 ranks on the left.
+ * If resolution 8 bits, shift of 4 ranks on the left.
+ * If resolution 6 bits, shift of 6 ranks on the left.
+ * therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2))
+ * @param __HANDLE__ ADC handle
+ * @param _Threshold_ Value to be shifted
+ * @retval None
+ */
+#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \
+ ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3U)*2U))
+
+/**
+ * @brief Shift the AWD2 and AWD3 threshold in function of the selected ADC resolution.
+ * Thresholds have to be left-aligned on bit 7.
+ * If resolution 12 bits, shift of 4 ranks on the right (the 4 LSB are discarded)
+ * If resolution 10 bits, shift of 2 ranks on the right (the 2 LSB are discarded)
+ * If resolution 8 bits, no shift.
+ * If resolution 6 bits, shift of 2 ranks on the left (the 2 LSB are set to 0)
+ * @param __HANDLE__ ADC handle
+ * @param _Threshold_ Value to be shifted
+ * @retval None
+ */
+#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \
+ ( ((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) ? \
+ ((_Threshold_) >> (4U- ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3U)*2U))) : \
+ (_Threshold_) << 2U )
+
+/**
+ * @brief Defines if the selected ADC is within ADC common register ADC1_2 or ADC3_4
+ * if available (ADC2, ADC3, ADC4 availability depends on STM32 product)
+ * @param __HANDLE__ ADC handle
+ * @retval Common control register ADC1_2 or ADC3_4
+ */
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+#define ADC_MASTER_INSTANCE(__HANDLE__) \
+ ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \
+ )? (ADC1) : (ADC3) \
+ )
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define ADC_MASTER_INSTANCE(__HANDLE__) \
+ (ADC1)
+#endif /* STM32F302xE || */
+ /* STM32F302xC || */
+ /* STM32F303x8 || STM32F328xx || STM32F334x8 */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define ADC_MASTER_INSTANCE(__HANDLE__) \
+ (ADC1)
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+/**
+ * @brief Defines if the selected ADC is within ADC common register ADC1_2 or ADC3_4
+ * if available (ADC2, ADC3, ADC4 availability depends on STM32 product)
+ * @param __HANDLE__ ADC handle
+ * @retval Common control register ADC1_2 or ADC3_4
+ */
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+#define ADC_COMMON_REGISTER(__HANDLE__) \
+ ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \
+ )? (ADC1_2_COMMON) : (ADC3_4_COMMON) \
+ )
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define ADC_COMMON_REGISTER(__HANDLE__) \
+ (ADC1_2_COMMON)
+#endif /* STM32F302xE || */
+ /* STM32F302xC || */
+ /* STM32F303x8 || STM32F328xx || STM32F334x8 */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define ADC_COMMON_REGISTER(__HANDLE__) \
+ (ADC1_COMMON)
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+/**
+ * @brief Selection of ADC common register CCR bits MULTI[4:0]corresponding to the selected ADC (applicable for devices with several ADCs)
+ * @param __HANDLE__ ADC handle
+ * @retval None
+ */
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+#define ADC_COMMON_CCR_MULTI(__HANDLE__) \
+ ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \
+ )? \
+ (ADC1_2_COMMON->CCR & ADC12_CCR_MULTI) \
+ : \
+ (ADC3_4_COMMON->CCR & ADC34_CCR_MULTI) \
+ )
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define ADC_COMMON_CCR_MULTI(__HANDLE__) \
+ (ADC1_2_COMMON->CCR & ADC12_CCR_MULTI)
+#endif /* STM32F302xE || */
+ /* STM32F302xC || */
+ /* STM32F303x8 || STM32F328xx || STM32F334x8 */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define ADC_COMMON_CCR_MULTI(__HANDLE__) \
+ (RESET)
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+/**
+ * @brief Verification of condition for ADC start conversion: ADC must be in non-multimode, or multimode with handle of ADC master (applicable for devices with several ADCs)
+ * @param __HANDLE__ ADC handle
+ * @retval None
+ */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \
+ ((ADC_COMMON_CCR_MULTI(__HANDLE__) == ADC_MODE_INDEPENDENT) || \
+ (IS_ADC_MULTIMODE_MASTER_INSTANCE((__HANDLE__)->Instance)) )
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \
+ (!RESET)
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+/**
+ * @brief Verification of condition for ADC group regular start conversion: ADC must be in non-multimode or multimode on group injected only, or multimode with handle of ADC master (applicable for devices with several ADCs)
+ * @param __HANDLE__ ADC handle.
+ * @retval None
+ */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(__HANDLE__) \
+ ((ADC_COMMON_CCR_MULTI(__HANDLE__) == ADC_MODE_INDEPENDENT) || \
+ (ADC_COMMON_CCR_MULTI(__HANDLE__) == ADC_DUALMODE_INJECSIMULT) || \
+ (ADC_COMMON_CCR_MULTI(__HANDLE__) == ADC_DUALMODE_ALTERTRIG) || \
+ (IS_ADC_MULTIMODE_MASTER_INSTANCE((__HANDLE__)->Instance)) )
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(__HANDLE__) \
+ (!RESET)
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+/**
+ * @brief Verification of condition for ADC group injected start conversion: ADC must be in non-multimode or multimode on group regular only, or multimode with handle of ADC master (applicable for devices with several ADCs)
+ * @param __HANDLE__ ADC handle.
+ * @retval None
+ */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define ADC_NONMULTIMODE_INJ_OR_MULTIMODEMASTER(__HANDLE__) \
+ ((ADC_COMMON_CCR_MULTI(__HANDLE__) == ADC_MODE_INDEPENDENT) || \
+ (ADC_COMMON_CCR_MULTI(__HANDLE__) == ADC_DUALMODE_REGSIMULT) || \
+ (ADC_COMMON_CCR_MULTI(__HANDLE__) == ADC_DUALMODE_INTERL) || \
+ (IS_ADC_MULTIMODE_MASTER_INSTANCE((__HANDLE__)->Instance)) )
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define ADC_NONMULTIMODE_INJ_OR_MULTIMODEMASTER(__HANDLE__) \
+ (!RESET)
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+/**
+ * @brief Check ADC multimode setting: In case of multimode, check whether ADC master of the selected ADC has feature auto-injection enabled (applicable for devices with several ADCs)
+ * @param __HANDLE__ ADC handle
+ * @retval None
+ */
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+#define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) \
+ (( (((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2) \
+ )? \
+ (ADC1->CFGR & ADC_CFGR_JAUTO) \
+ : \
+ (ADC3->CFGR & ADC_CFGR_JAUTO) \
+ )
+#elif defined(STM32F302xE) || \
+ defined(STM32F302xC) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) \
+ (( (((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2) \
+ )? \
+ (ADC1->CFGR & ADC_CFGR_JAUTO) \
+ : \
+ (RESET) \
+ )
+#else
+#define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) \
+ (RESET)
+#endif
+
+/**
+ * @brief Set handle of the other ADC sharing the same common register ADC1_2 or ADC3_4
+ * if available (ADC2, ADC3, ADC4 availability depends on STM32 product)
+ * @param __HANDLE__ ADC handle
+ * @param __HANDLE_OTHER_ADC__ other ADC handle
+ * @retval None
+ */
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+#define ADC_COMMON_ADC_OTHER(__HANDLE__, __HANDLE_OTHER_ADC__) \
+ ( ( ((__HANDLE__)->Instance == ADC1) \
+ )? \
+ ((__HANDLE_OTHER_ADC__)->Instance = ADC2) \
+ : \
+ ( ( ((__HANDLE__)->Instance == ADC2) \
+ )? \
+ ((__HANDLE_OTHER_ADC__)->Instance = ADC1) \
+ : \
+ ( ( ((__HANDLE__)->Instance == ADC3) \
+ )? \
+ ((__HANDLE_OTHER_ADC__)->Instance = ADC4) \
+ : \
+ ( ( ((__HANDLE__)->Instance == ADC4) \
+ )? \
+ ((__HANDLE_OTHER_ADC__)->Instance = ADC3) \
+ : \
+ ((__HANDLE_OTHER_ADC__)->Instance = NULL) \
+ ) \
+ ) \
+ ) \
+ )
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define ADC_COMMON_ADC_OTHER(__HANDLE__, __HANDLE_OTHER_ADC__) \
+ ( ( ((__HANDLE__)->Instance == ADC1) \
+ )? \
+ ((__HANDLE_OTHER_ADC__)->Instance = ADC2) \
+ : \
+ ((__HANDLE_OTHER_ADC__)->Instance = ADC1) \
+ )
+#endif /* STM32F302xE || */
+ /* STM32F302xC || */
+ /* STM32F303x8 || STM32F328xx || STM32F334x8 */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define ADC_COMMON_ADC_OTHER(__HANDLE__, __HANDLE_OTHER_ADC__) \
+ ((__HANDLE_OTHER_ADC__)->Instance = NULL)
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+/**
+ * @brief Set handle of the ADC slave associated to the ADC master
+ * if available (ADC2, ADC3, ADC4 availability depends on STM32 product)
+ * @param __HANDLE_MASTER__ ADC master handle
+ * @param __HANDLE_SLAVE__ ADC slave handle
+ * @retval None
+ */
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \
+ ( ( ((__HANDLE_MASTER__)->Instance == ADC1) \
+ )? \
+ ((__HANDLE_SLAVE__)->Instance = ADC2) \
+ : \
+ ( ( ((__HANDLE_MASTER__)->Instance == ADC3) \
+ )? \
+ ((__HANDLE_SLAVE__)->Instance = ADC4) \
+ : \
+ ((__HANDLE_SLAVE__)->Instance = NULL) \
+ ) \
+ )
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \
+ ( ( ((__HANDLE_MASTER__)->Instance == ADC1) \
+ )? \
+ ((__HANDLE_SLAVE__)->Instance = ADC2) \
+ : \
+ ( NULL ) \
+ )
+#endif /* STM32F302xE || */
+ /* STM32F302xC || */
+ /* STM32F303x8 || STM32F328xx || STM32F334x8 */
+
+
+#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \
+ ((RESOLUTION) == ADC_RESOLUTION_10B) || \
+ ((RESOLUTION) == ADC_RESOLUTION_8B) || \
+ ((RESOLUTION) == ADC_RESOLUTION_6B) )
+
+#define IS_ADC_RESOLUTION_8_6_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_8B) || \
+ ((RESOLUTION) == ADC_RESOLUTION_6B) )
+
+
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
+ ((ALIGN) == ADC_DATAALIGN_LEFT) )
+
+#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \
+ ((SCAN_MODE) == ADC_SCAN_ENABLE) )
+
+#define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || \
+ ((EOC_SELECTION) == ADC_EOC_SEQ_CONV) )
+
+#define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) || \
+ ((OVR) == ADC_OVR_DATA_OVERWRITTEN) )
+
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_1) || \
+ ((CHANNEL) == ADC_CHANNEL_2) || \
+ ((CHANNEL) == ADC_CHANNEL_3) || \
+ ((CHANNEL) == ADC_CHANNEL_4) || \
+ ((CHANNEL) == ADC_CHANNEL_5) || \
+ ((CHANNEL) == ADC_CHANNEL_6) || \
+ ((CHANNEL) == ADC_CHANNEL_7) || \
+ ((CHANNEL) == ADC_CHANNEL_8) || \
+ ((CHANNEL) == ADC_CHANNEL_9) || \
+ ((CHANNEL) == ADC_CHANNEL_10) || \
+ ((CHANNEL) == ADC_CHANNEL_11) || \
+ ((CHANNEL) == ADC_CHANNEL_12) || \
+ ((CHANNEL) == ADC_CHANNEL_13) || \
+ ((CHANNEL) == ADC_CHANNEL_14) || \
+ ((CHANNEL) == ADC_CHANNEL_15) || \
+ ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \
+ ((CHANNEL) == ADC_CHANNEL_VBAT) || \
+ ((CHANNEL) == ADC_CHANNEL_VREFINT) || \
+ ((CHANNEL) == ADC_CHANNEL_VOPAMP1) || \
+ ((CHANNEL) == ADC_CHANNEL_VOPAMP2) || \
+ ((CHANNEL) == ADC_CHANNEL_VOPAMP3) || \
+ ((CHANNEL) == ADC_CHANNEL_VOPAMP4) )
+
+#define IS_ADC_DIFF_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_1) || \
+ ((CHANNEL) == ADC_CHANNEL_2) || \
+ ((CHANNEL) == ADC_CHANNEL_3) || \
+ ((CHANNEL) == ADC_CHANNEL_4) || \
+ ((CHANNEL) == ADC_CHANNEL_5) || \
+ ((CHANNEL) == ADC_CHANNEL_6) || \
+ ((CHANNEL) == ADC_CHANNEL_7) || \
+ ((CHANNEL) == ADC_CHANNEL_8) || \
+ ((CHANNEL) == ADC_CHANNEL_9) || \
+ ((CHANNEL) == ADC_CHANNEL_10) || \
+ ((CHANNEL) == ADC_CHANNEL_11) || \
+ ((CHANNEL) == ADC_CHANNEL_12) || \
+ ((CHANNEL) == ADC_CHANNEL_13) || \
+ ((CHANNEL) == ADC_CHANNEL_14) )
+
+#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \
+ ((TIME) == ADC_SAMPLETIME_2CYCLES_5) || \
+ ((TIME) == ADC_SAMPLETIME_4CYCLES_5) || \
+ ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \
+ ((TIME) == ADC_SAMPLETIME_19CYCLES_5) || \
+ ((TIME) == ADC_SAMPLETIME_61CYCLES_5) || \
+ ((TIME) == ADC_SAMPLETIME_181CYCLES_5) || \
+ ((TIME) == ADC_SAMPLETIME_601CYCLES_5) )
+
+#define IS_ADC_SINGLE_DIFFERENTIAL(SING_DIFF) (((SING_DIFF) == ADC_SINGLE_ENDED) || \
+ ((SING_DIFF) == ADC_DIFFERENTIAL_ENDED) )
+
+#define IS_ADC_OFFSET_NUMBER(OFFSET_NUMBER) (((OFFSET_NUMBER) == ADC_OFFSET_NONE) || \
+ ((OFFSET_NUMBER) == ADC_OFFSET_1) || \
+ ((OFFSET_NUMBER) == ADC_OFFSET_2) || \
+ ((OFFSET_NUMBER) == ADC_OFFSET_3) || \
+ ((OFFSET_NUMBER) == ADC_OFFSET_4) )
+
+#define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_10) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_11) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_12) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_13) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_14) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_15) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_16) )
+
+#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
+ ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
+ ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
+ ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) )
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+
+#if defined(STM32F303xC) || defined(STM32F358xx)
+#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC4) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
+ \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T7_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT2) || \
+ \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \
+ \
+ ((REGTRIG) == ADC_SOFTWARE_START) )
+#endif /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)
+#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC4) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
+ \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T7_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT2) || \
+ \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \
+ \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_CC3) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_TRGO2) || \
+ \
+ ((REGTRIG) == ADC_SOFTWARE_START) )
+#endif /* STM32F303xE || STM32F398xx */
+
+#endif /* STM32F303xC || STM32F303xE || STM32F398xx || STM32F358xx */
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC)
+
+#if defined(STM32F302xE)
+#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC4) || \
+ \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_CC3) || \
+ \
+ ((REGTRIG) == ADC_SOFTWARE_START) )
+#endif /* STM32F302xE */
+
+#if defined(STM32F302xC)
+#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC4) || \
+ \
+ ((REGTRIG) == ADC_SOFTWARE_START) )
+#endif /* STM32F302xC */
+
+#endif /* STM32F302xE || */
+ /* STM32F302xC */
+
+#if defined(STM32F303x8) || defined(STM32F328xx)
+#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC4) || \
+ \
+ ((REGTRIG) == ADC_SOFTWARE_START) )
+#endif /* STM32F303x8 || STM32F328xx */
+
+#if defined(STM32F334x8)
+#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONVHRTIM_TRG1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONVHRTIM_TRG3) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC4) || \
+ \
+ ((REGTRIG) == ADC_SOFTWARE_START) )
+#endif /* STM32F334x8 */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \
+ ((REGTRIG) == ADC_SOFTWARE_START) )
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \
+ ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \
+ ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \
+ ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) )
+
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+
+#if defined(STM32F303xC) || defined(STM32F358xx)
+#define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
+ \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T7_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \
+ \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO2) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \
+ \
+ ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) )
+#endif /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)
+#define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
+ \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T7_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \
+ \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO2) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \
+ \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_CC2) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_TRGO2) || \
+ \
+ ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) )
+#endif /* STM32F303xE || STM32F398xx */
+
+#endif /* STM32F303xC || STM32F303xE || STM32F398xx || STM32F358xx */
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC)
+
+#if defined(STM32F302xE)
+#define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_TRGO2) || \
+ ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) )
+#endif /* STM32F302xE */
+
+#if defined(STM32F302xC)
+#define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
+ ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) )
+#endif /* STM32F302xC */
+
+#endif /* STM32F302xE || */
+ /* STM32F302xC */
+
+#if defined(STM32F303x8) || defined(STM32F328xx)
+#define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO2) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \
+ ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) )
+#endif /* STM32F303x8 || STM32F328xx */
+
+#if defined(STM32F334x8)
+#define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_HRTIM_TRG2) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_HRTIM_TRG4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \
+ ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) )
+#endif /* STM32F334x8 */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \
+ ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) )
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || \
+ ((CHANNEL) == ADC_INJECTED_RANK_2) || \
+ ((CHANNEL) == ADC_INJECTED_RANK_3) || \
+ ((CHANNEL) == ADC_INJECTED_RANK_4) )
+
+#define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT) || \
+ ((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
+ ((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \
+ ((MODE) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \
+ ((MODE) == ADC_DUALMODE_INJECSIMULT) || \
+ ((MODE) == ADC_DUALMODE_REGSIMULT) || \
+ ((MODE) == ADC_DUALMODE_INTERL) || \
+ ((MODE) == ADC_DUALMODE_ALTERTRIG) )
+
+#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAACCESSMODE_DISABLED) || \
+ ((MODE) == ADC_DMAACCESSMODE_12_10_BITS) || \
+ ((MODE) == ADC_DMAACCESSMODE_8_6_BITS) )
+
+#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_1CYCLE) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_2CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_3CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_4CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_12CYCLES) )
+
+#define IS_ADC_ANALOG_WATCHDOG_NUMBER(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_1) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_2) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_3) )
+
+#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
+
+#define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP) || \
+ ((CONVERSION) == ADC_INJECTED_GROUP) || \
+ ((CONVERSION) == ADC_REGULAR_INJECTED_GROUP) )
+
+#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \
+ ((EVENT) == ADC_AWD2_EVENT) || \
+ ((EVENT) == ADC_AWD3_EVENT) || \
+ ((EVENT) == ADC_OVR_EVENT) || \
+ ((EVENT) == ADC_JQOVF_EVENT) )
+
+/** @defgroup ADCEx_range_verification ADC Extended Range Verification
+ * in function of ADC resolution selected (12, 10, 8 or 6 bits)
+ * @{
+ */
+#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \
+ ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= (0x0FFFU))) || \
+ (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= (0x03FFU))) || \
+ (((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= (0x00FFU))) || \
+ (((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= (0x003FU))) )
+/**
+ * @}
+ */
+
+/** @defgroup ADC_injected_nb_conv_verification ADC Injected Conversion Number Verification
+ * @{
+ */
+#define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (4U)))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_regular_nb_conv_verification ADC Regular Conversion Number Verification
+ * @{
+ */
+#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (16U)))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_regular_discontinuous_mode_number_verification ADC Regular Discontinuous Mode NumberVerification
+ * @{
+ */
+#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1U)) && ((NUMBER) <= (8U)))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_calibration_factor_length_verification ADC Calibration Factor Length Verification
+ * @{
+ */
+/**
+ * @brief Calibration factor length verification (7 bits maximum)
+ * @param _Calibration_Factor_ Calibration factor value
+ * @retval None
+ */
+#define IS_ADC_CALFACT(_Calibration_Factor_) ((_Calibration_Factor_) <= (0x7FU))
+/**
+ * @}
+ */
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+
+/**
+ * @brief Verification of ADC state: enabled or disabled
+ * @param __HANDLE__ ADC handle
+ * @retval SET (ADC enabled) or RESET (ADC disabled)
+ */
+#define ADC_IS_ENABLE(__HANDLE__) \
+ ((( ((__HANDLE__)->Instance->CR2 & ADC_CR2_ADON) == ADC_CR2_ADON ) \
+ ) ? SET : RESET)
+
+/**
+ * @brief Test if conversion trigger of regular group is software start
+ * or external trigger.
+ * @param __HANDLE__ ADC handle
+ * @retval SET (software start) or RESET (external trigger)
+ */
+#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
+ (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTSEL) == ADC_SOFTWARE_START)
+
+/**
+ * @brief Test if conversion trigger of injected group is software start
+ * or external trigger.
+ * @param __HANDLE__ ADC handle
+ * @retval SET (software start) or RESET (external trigger)
+ */
+#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
+ (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTSEL) == ADC_INJECTED_SOFTWARE_START)
+
+/**
+ * @brief Simultaneously clears and sets specific bits of the handle State
+ * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
+ * the first parameter is the ADC handle State, the second parameter is the
+ * bit field to clear, the third and last parameter is the bit field to set.
+ * @retval None
+ */
+#define ADC_STATE_CLR_SET MODIFY_REG
+
+/**
+ * @brief Clear ADC error code (set it to error code: "no error")
+ * @param __HANDLE__ ADC handle
+ * @retval None
+ */
+#define ADC_CLEAR_ERRORCODE(__HANDLE__) \
+ ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
+
+/**
+ * @brief Set ADC number of conversions into regular channel sequence length.
+ * @param _NbrOfConversion_ Regular channel sequence length
+ * @retval None
+ */
+#define ADC_SQR1_L_SHIFT(_NbrOfConversion_) \
+ (((_NbrOfConversion_) - (uint8_t)1U) << 20U)
+
+/**
+ * @brief Set the ADC's sample time for channel numbers between 10 and 18.
+ * @param _SAMPLETIME_ Sample time parameter.
+ * @param _CHANNELNB_ Channel number.
+ * @retval None
+ */
+#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) \
+ ((_SAMPLETIME_) << (3U * ((_CHANNELNB_) - 10U)))
+
+/**
+ * @brief Set the ADC's sample time for channel numbers between 0 and 9.
+ * @param _SAMPLETIME_ Sample time parameter.
+ * @param _CHANNELNB_ Channel number.
+ * @retval None
+ */
+#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) \
+ ((_SAMPLETIME_) << (3U * (_CHANNELNB_)))
+
+/**
+ * @brief Set the selected regular channel rank for rank between 1 and 6.
+ * @param _CHANNELNB_ Channel number.
+ * @param _RANKNB_ Rank number.
+ * @retval None
+ */
+#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) \
+ ((_CHANNELNB_) << (5U * ((_RANKNB_) - 1U)))
+
+/**
+ * @brief Set the selected regular channel rank for rank between 7 and 12.
+ * @param _CHANNELNB_ Channel number.
+ * @param _RANKNB_ Rank number.
+ * @retval None
+ */
+#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) \
+ ((_CHANNELNB_) << (5U * ((_RANKNB_) - 7U)))
+
+/**
+ * @brief Set the selected regular channel rank for rank between 13 and 16.
+ * @param _CHANNELNB_ Channel number.
+ * @param _RANKNB_ Rank number.
+ * @retval None
+ */
+#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) \
+ ((_CHANNELNB_) << (5U * ((_RANKNB_) - 13U)))
+
+/**
+ * @brief Set the injected sequence length.
+ * @param _JSQR_JL_ Sequence length.
+ * @retval None
+ */
+#define ADC_JSQR_JL_SHIFT(_JSQR_JL_) \
+ (((_JSQR_JL_) -1U) << 20U)
+
+/**
+ * @brief Set the selected injected channel rank
+ * Note: on STM32F37x devices, channel rank position in JSQR register
+ * is depending on total number of ranks selected into
+ * injected sequencer (ranks sequence starting from 4-JL)
+ * @param _CHANNELNB_ Channel number.
+ * @param _RANKNB_ Rank number.
+ * @param _JSQR_JL_ Sequence length.
+ * @retval None
+ */
+#define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) \
+ ((_CHANNELNB_) << (5U * ((4U - ((_JSQR_JL_) - (_RANKNB_))) - 1U)))
+
+/**
+ * @brief Enable ADC continuous conversion mode.
+ * @param _CONTINUOUS_MODE_ Continuous mode.
+ * @retval None
+ */
+#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) \
+ ((_CONTINUOUS_MODE_) << 1U)
+
+/**
+ * @brief Configures the number of discontinuous conversions for the regular group channels.
+ * @param _NBR_DISCONTINUOUS_CONV_ Number of discontinuous conversions.
+ * @retval None
+ */
+#define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) \
+ (((_NBR_DISCONTINUOUS_CONV_) - 1U) << 13U)
+
+/**
+ * @brief Enable ADC scan mode to convert multiple ranks with sequencer.
+ * @param _SCAN_MODE_ Scan conversion mode.
+ * @retval None
+ */
+/* Note: Scan mode is compared to ENABLE for legacy purpose, this parameter */
+/* is equivalent to ADC_SCAN_ENABLE. */
+#define ADC_CR1_SCAN_SET(_SCAN_MODE_) \
+ (( ((_SCAN_MODE_) == ADC_SCAN_ENABLE) || ((_SCAN_MODE_) == ENABLE) \
+ )? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE) \
+ )
+
+/**
+ * @brief Calibration factor in differential mode to be set into calibration register
+ * @param _Calibration_Factor_ Calibration factor value
+ * @retval None
+ */
+#define ADC_CALFACT_DIFF_SET(_Calibration_Factor_) \
+ ((_Calibration_Factor_) << 16U)
+
+/**
+ * @brief Calibration factor in differential mode to be retrieved from calibration register
+ * @param _Calibration_Factor_ Calibration factor value
+ * @retval None
+ */
+#define ADC_CALFACT_DIFF_GET(_Calibration_Factor_) \
+ ((_Calibration_Factor_) >> 16U)
+
+
+/**
+ * @brief Get the maximum ADC conversion cycles on all channels.
+ * Returns the selected sampling time + conversion time (12.5 ADC clock cycles)
+ * Approximation of sampling time within 4 ranges, returns the highest value:
+ * below 7.5 cycles {1.5 cycle; 7.5 cycles},
+ * between 13.5 cycles and 28.5 cycles {13.5 cycles; 28.5 cycles}
+ * between 41.5 cycles and 71.5 cycles {41.5 cycles; 55.5 cycles; 71.5cycles}
+ * equal to 239.5 cycles
+ * Unit: ADC clock cycles
+ * @param __HANDLE__ ADC handle
+ * @retval ADC conversion cycles on all channels
+ */
+#define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \
+ (( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && \
+ (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) ) ? \
+ \
+ (( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \
+ (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET) ) ? \
+ ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5) \
+ : \
+ ((((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \
+ (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET)) || \
+ ((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET) && \
+ (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET))) ? \
+ ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5) \
+ )
+
+/**
+ * @brief Get the total ADC clock prescaler (APB2 prescaler x ADC prescaler)
+ * from system clock configuration register.
+ * Approximation within 3 ranges, returns the higher value:
+ * total prescaler minimum: 2 (ADC presc 2, APB2 presc 0)
+ * total prescaler 32 (ADC presc 0 and APB2 presc all, or
+ * ADC presc {4, 6, 8} and APB2 presc {0, 2, 4})
+ * total prescaler maximum: 128 (ADC presc {4, 6, 8} and APB2 presc {8, 16})
+ * Unit: none (prescaler factor)
+ * @retval ADC and APB2 prescaler factor
+ */
+#define ADC_CLOCK_PRESCALER_RANGE() \
+ (( (RCC->CFGR & (RCC_CFGR_ADCPRE_1 | RCC_CFGR_ADCPRE_0)) == RESET) ? \
+ (( (RCC->CFGR & RCC_CFGR_PPRE2_2) == RESET) ? 2 : 32U ) \
+ : \
+ (( (RCC->CFGR & RCC_CFGR_PPRE2_1) == RESET) ? 32 : 128U ) \
+ )
+
+/**
+ * @brief Get the ADC clock prescaler from system clock configuration register.
+ * @retval None
+ */
+#define ADC_GET_CLOCK_PRESCALER() (((RCC->CFGR & RCC_CFGR_ADCPRE) >> 14U) +1U)
+
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
+ ((ALIGN) == ADC_DATAALIGN_LEFT) )
+
+#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \
+ ((SCAN_MODE) == ADC_SCAN_ENABLE) )
+
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \
+ ((CHANNEL) == ADC_CHANNEL_1) || \
+ ((CHANNEL) == ADC_CHANNEL_2) || \
+ ((CHANNEL) == ADC_CHANNEL_3) || \
+ ((CHANNEL) == ADC_CHANNEL_4) || \
+ ((CHANNEL) == ADC_CHANNEL_5) || \
+ ((CHANNEL) == ADC_CHANNEL_6) || \
+ ((CHANNEL) == ADC_CHANNEL_7) || \
+ ((CHANNEL) == ADC_CHANNEL_8) || \
+ ((CHANNEL) == ADC_CHANNEL_9) || \
+ ((CHANNEL) == ADC_CHANNEL_10) || \
+ ((CHANNEL) == ADC_CHANNEL_11) || \
+ ((CHANNEL) == ADC_CHANNEL_12) || \
+ ((CHANNEL) == ADC_CHANNEL_13) || \
+ ((CHANNEL) == ADC_CHANNEL_14) || \
+ ((CHANNEL) == ADC_CHANNEL_15) || \
+ ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \
+ ((CHANNEL) == ADC_CHANNEL_VREFINT) || \
+ ((CHANNEL) == ADC_CHANNEL_VBAT) )
+
+#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \
+ ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \
+ ((TIME) == ADC_SAMPLETIME_13CYCLES_5) || \
+ ((TIME) == ADC_SAMPLETIME_28CYCLES_5) || \
+ ((TIME) == ADC_SAMPLETIME_41CYCLES_5) || \
+ ((TIME) == ADC_SAMPLETIME_55CYCLES_5) || \
+ ((TIME) == ADC_SAMPLETIME_71CYCLES_5) || \
+ ((TIME) == ADC_SAMPLETIME_239CYCLES_5) )
+
+#define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_10) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_11) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_12) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_13) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_14) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_15) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_16) )
+
+#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
+ ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) )
+
+#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T19_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T19_CC3) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T19_CC4) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
+ ((REGTRIG) == ADC_SOFTWARE_START) )
+
+#define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \
+ ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) )
+
+#define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T19_CC1) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T19_CC2) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
+ ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) )
+
+#define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || \
+ ((CHANNEL) == ADC_INJECTED_RANK_2) || \
+ ((CHANNEL) == ADC_INJECTED_RANK_3) || \
+ ((CHANNEL) == ADC_INJECTED_RANK_4) )
+
+#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
+
+#define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP) || \
+ ((CONVERSION) == ADC_INJECTED_GROUP) || \
+ ((CONVERSION) == ADC_REGULAR_INJECTED_GROUP) )
+
+#define IS_ADC_EVENT_TYPE(EVENT) ((EVENT) == ADC_AWD_EVENT)
+
+/** @defgroup ADCEx_range_verification ADC Extended Range Verification
+ * For a unique ADC resolution: 12 bits
+ * @{
+ */
+#define IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= (0x0FFFU))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_injected_nb_conv_verification ADC Injected Conversion Number Verification
+ * @{
+ */
+#define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (4U)))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_regular_nb_conv_verification ADC Regular Conversion Number Verification
+ * @{
+ */
+#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (16U)))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_regular_discontinuous_mode_number_verification ADC Regular Discontinuous Mode NumberVerification
+ * @{
+ */
+#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1U)) && ((NUMBER) <= (8U)))
+/**
+ * @}
+ */
+
+#endif /* STM32F373xC || STM32F378xx */
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADCEx_Exported_Functions ADCEx Exported Functions
+ * @{
+ */
+
+/* Initialization/de-initialization functions *********************************/
+
+/** @addtogroup ADCEx_Exported_Functions_Group2 ADCEx Input and Output operation functions
+ * @{
+ */
+/* I/O operation functions ****************************************************/
+
+/* ADC calibration */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(struct __ADC_HandleTypeDef* hadc, uint32_t SingleDiff);
+uint32_t HAL_ADCEx_Calibration_GetValue(struct __ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
+HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(struct __ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor);
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(struct __ADC_HandleTypeDef* hadc);
+#endif /* STM32F373xC || STM32F378xx */
+
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart(struct __ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop(struct __ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(struct __ADC_HandleTypeDef* hadc, uint32_t Timeout);
+
+/* Non-blocking mode: Interruption */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(struct __ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(struct __ADC_HandleTypeDef* hadc);
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/* ADC multimode */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(struct __ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(struct __ADC_HandleTypeDef *hadc);
+uint32_t HAL_ADCEx_MultiModeGetValue(struct __ADC_HandleTypeDef *hadc);
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+/* ADC group regular stop conversion without impacting group injected */
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_ADCEx_RegularStop(struct __ADC_HandleTypeDef* hadc);
+/* Non-blocking mode: Interruption */
+HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(struct __ADC_HandleTypeDef* hadc);
+/* Non-blocking mode: DMA */
+HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(struct __ADC_HandleTypeDef* hadc);
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/* ADC multimode */
+HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(struct __ADC_HandleTypeDef *hadc);
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+/* ADC retrieve conversion value intended to be used with polling or interruption */
+uint32_t HAL_ADCEx_InjectedGetValue(struct __ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
+
+/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
+void HAL_ADCEx_InjectedConvCpltCallback(struct __ADC_HandleTypeDef* hadc);
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+void HAL_ADCEx_InjectedQueueOverflowCallback(struct __ADC_HandleTypeDef* hadc);
+void HAL_ADCEx_LevelOutOfWindow2Callback(struct __ADC_HandleTypeDef* hadc);
+void HAL_ADCEx_LevelOutOfWindow3Callback(struct __ADC_HandleTypeDef* hadc);
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+/**
+ * @}
+ */
+
+/** @addtogroup ADCEx_Exported_Functions_Group3 ADCEx Peripheral Control functions
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(struct __ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(struct __ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode);
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F3xx_ADC_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_hal_can.h b/Inc/stm32f3xx_hal_can.h
new file mode 100644
index 0000000..b6630f8
--- /dev/null
+++ b/Inc/stm32f3xx_hal_can.h
@@ -0,0 +1,792 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_can.h
+ * @author MCD Application Team
+ * @brief Header file of CAN HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F3xx_HAL_CAN_H
+#define STM32F3xx_HAL_CAN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+#if defined (CAN)
+/** @addtogroup CAN
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CAN_Exported_Types CAN Exported Types
+ * @{
+ */
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */
+ HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */
+ HAL_CAN_STATE_LISTENING = 0x02U, /*!< CAN receive process is ongoing */
+ HAL_CAN_STATE_SLEEP_PENDING = 0x03U, /*!< CAN sleep request is pending */
+ HAL_CAN_STATE_SLEEP_ACTIVE = 0x04U, /*!< CAN sleep mode is active */
+ HAL_CAN_STATE_ERROR = 0x05U /*!< CAN error state */
+
+} HAL_CAN_StateTypeDef;
+
+/**
+ * @brief CAN init structure definition
+ */
+typedef struct
+{
+ uint32_t Prescaler; /*!< Specifies the length of a time quantum.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */
+
+ uint32_t Mode; /*!< Specifies the CAN operating mode.
+ This parameter can be a value of @ref CAN_operating_mode */
+
+ uint32_t SyncJumpWidth; /*!< Specifies the maximum number of time quanta the CAN hardware
+ is allowed to lengthen or shorten a bit to perform resynchronization.
+ This parameter can be a value of @ref CAN_synchronisation_jump_width */
+
+ uint32_t TimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1.
+ This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
+
+ uint32_t TimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2.
+ This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
+
+ FunctionalState TimeTriggeredMode; /*!< Enable or disable the time triggered communication mode.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ FunctionalState AutoBusOff; /*!< Enable or disable the automatic bus-off management.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ FunctionalState AutoWakeUp; /*!< Enable or disable the automatic wake-up mode.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ FunctionalState AutoRetransmission; /*!< Enable or disable the non-automatic retransmission mode.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ FunctionalState ReceiveFifoLocked; /*!< Enable or disable the Receive FIFO Locked mode.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ FunctionalState TransmitFifoPriority;/*!< Enable or disable the transmit FIFO priority.
+ This parameter can be set to ENABLE or DISABLE. */
+
+} CAN_InitTypeDef;
+
+/**
+ * @brief CAN filter configuration structure definition
+ */
+typedef struct
+{
+ uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
+ configuration, first one for a 16-bit configuration).
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
+ uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
+ configuration, second one for a 16-bit configuration).
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
+ uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
+ according to the mode (MSBs for a 32-bit configuration,
+ first one for a 16-bit configuration).
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
+ uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
+ according to the mode (LSBs for a 32-bit configuration,
+ second one for a 16-bit configuration).
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
+ uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter.
+ This parameter can be a value of @ref CAN_filter_FIFO */
+
+ uint32_t FilterBank; /*!< Specifies the filter bank which will be initialized.
+ This parameter mus be a number between Min_Data = 0 and Max_Data = 13. */
+
+ uint32_t FilterMode; /*!< Specifies the filter mode to be initialized.
+ This parameter can be a value of @ref CAN_filter_mode */
+
+ uint32_t FilterScale; /*!< Specifies the filter scale.
+ This parameter can be a value of @ref CAN_filter_scale */
+
+ uint32_t FilterActivation; /*!< Enable or disable the filter.
+ This parameter can be a value of @ref CAN_filter_activation */
+
+ uint32_t SlaveStartFilterBank; /*!< Select the start filter bank for the slave CAN instance.
+ STM32F3xx devices don't support slave CAN instance (dual CAN). Therefore
+ this parameter is meaningless but it has been kept for compatibility accross
+ STM32 families. */
+
+} CAN_FilterTypeDef;
+
+/**
+ * @brief CAN Tx message header structure definition
+ */
+typedef struct
+{
+ uint32_t StdId; /*!< Specifies the standard identifier.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
+
+ uint32_t ExtId; /*!< Specifies the extended identifier.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
+
+ uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
+ This parameter can be a value of @ref CAN_identifier_type */
+
+ uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
+ This parameter can be a value of @ref CAN_remote_transmission_request */
+
+ uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
+
+ FunctionalState TransmitGlobalTime; /*!< Specifies whether the timestamp counter value captured on start
+ of frame transmission, is sent in DATA6 and DATA7 replacing pData[6] and pData[7].
+ @note: Time Triggered Communication Mode must be enabled.
+ @note: DLC must be programmed as 8 bytes, in order these 2 bytes are sent.
+ This parameter can be set to ENABLE or DISABLE. */
+
+} CAN_TxHeaderTypeDef;
+
+/**
+ * @brief CAN Rx message header structure definition
+ */
+typedef struct
+{
+ uint32_t StdId; /*!< Specifies the standard identifier.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
+
+ uint32_t ExtId; /*!< Specifies the extended identifier.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
+
+ uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
+ This parameter can be a value of @ref CAN_identifier_type */
+
+ uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
+ This parameter can be a value of @ref CAN_remote_transmission_request */
+
+ uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
+
+ uint32_t Timestamp; /*!< Specifies the timestamp counter value captured on start of frame reception.
+ @note: Time Triggered Communication Mode must be enabled.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0xFFFF. */
+
+ uint32_t FilterMatchIndex; /*!< Specifies the index of matching acceptance filter element.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
+
+} CAN_RxHeaderTypeDef;
+
+/**
+ * @brief CAN handle Structure definition
+ */
+typedef struct __CAN_HandleTypeDef
+{
+ CAN_TypeDef *Instance; /*!< Register base address */
+
+ CAN_InitTypeDef Init; /*!< CAN required parameters */
+
+ __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
+
+ __IO uint32_t ErrorCode; /*!< CAN Error code.
+ This parameter can be a value of @ref CAN_Error_Code */
+
+} CAN_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CAN_Exported_Constants CAN Exported Constants
+ * @{
+ */
+
+/** @defgroup CAN_Error_Code CAN Error Code
+ * @{
+ */
+#define HAL_CAN_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_CAN_ERROR_EWG (0x00000001U) /*!< Protocol Error Warning */
+#define HAL_CAN_ERROR_EPV (0x00000002U) /*!< Error Passive */
+#define HAL_CAN_ERROR_BOF (0x00000004U) /*!< Bus-off error */
+#define HAL_CAN_ERROR_STF (0x00000008U) /*!< Stuff error */
+#define HAL_CAN_ERROR_FOR (0x00000010U) /*!< Form error */
+#define HAL_CAN_ERROR_ACK (0x00000020U) /*!< Acknowledgment error */
+#define HAL_CAN_ERROR_BR (0x00000040U) /*!< Bit recessive error */
+#define HAL_CAN_ERROR_BD (0x00000080U) /*!< Bit dominant error */
+#define HAL_CAN_ERROR_CRC (0x00000100U) /*!< CRC error */
+#define HAL_CAN_ERROR_RX_FOV0 (0x00000200U) /*!< Rx FIFO0 overrun error */
+#define HAL_CAN_ERROR_RX_FOV1 (0x00000400U) /*!< Rx FIFO1 overrun error */
+#define HAL_CAN_ERROR_TX_ALST0 (0x00000800U) /*!< TxMailbox 0 transmit failure due to arbitration lost */
+#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 1 transmit failure due to tranmit error */
+#define HAL_CAN_ERROR_TX_ALST1 (0x00002000U) /*!< TxMailbox 0 transmit failure due to arbitration lost */
+#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to tranmit error */
+#define HAL_CAN_ERROR_TX_ALST2 (0x00008000U) /*!< TxMailbox 0 transmit failure due to arbitration lost */
+#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 1 transmit failure due to tranmit error */
+#define HAL_CAN_ERROR_TIMEOUT (0x00020000U) /*!< Timeout error */
+#define HAL_CAN_ERROR_NOT_INITIALIZED (0x00040000U) /*!< Peripheral not initialized */
+#define HAL_CAN_ERROR_NOT_READY (0x00080000U) /*!< Peripheral not ready */
+#define HAL_CAN_ERROR_NOT_STARTED (0x00100000U) /*!< Peripheral not started */
+#define HAL_CAN_ERROR_PARAM (0x00200000U) /*!< Parameter error */
+
+#define HAL_CAN_ERROR_INTERNAL (0x00800000U) /*!< Internal error */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_InitStatus CAN InitStatus
+ * @{
+ */
+#define CAN_INITSTATUS_FAILED (0x00000000U) /*!< CAN initialization failed */
+#define CAN_INITSTATUS_SUCCESS (0x00000001U) /*!< CAN initialization OK */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_operating_mode CAN Operating Mode
+ * @{
+ */
+#define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */
+#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
+#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
+#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
+/**
+ * @}
+ */
+
+
+/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width
+ * @{
+ */
+#define CAN_SJW_1TQ (0x00000000U) /*!< 1 time quantum */
+#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */
+#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */
+#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1
+ * @{
+ */
+#define CAN_BS1_1TQ (0x00000000U) /*!< 1 time quantum */
+#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */
+#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */
+#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */
+#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */
+#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */
+#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */
+#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */
+#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */
+#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */
+#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */
+#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */
+#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */
+#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */
+#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */
+#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2
+ * @{
+ */
+#define CAN_BS2_1TQ (0x00000000U) /*!< 1 time quantum */
+#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */
+#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */
+#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */
+#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */
+#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */
+#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */
+#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_mode CAN Filter Mode
+ * @{
+ */
+#define CAN_FILTERMODE_IDMASK (0x00000000U) /*!< Identifier mask mode */
+#define CAN_FILTERMODE_IDLIST (0x00000001U) /*!< Identifier list mode */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_scale CAN Filter Scale
+ * @{
+ */
+#define CAN_FILTERSCALE_16BIT (0x00000000U) /*!< Two 16-bit filters */
+#define CAN_FILTERSCALE_32BIT (0x00000001U) /*!< One 32-bit filter */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_activation CAN Filter Activation
+ * @{
+ */
+#define CAN_FILTER_DISABLE (0x00000000U) /*!< Disable filter */
+#define CAN_FILTER_ENABLE (0x00000001U) /*!< Enable filter */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_FIFO CAN Filter FIFO
+ * @{
+ */
+#define CAN_FILTER_FIFO0 (0x00000000U) /*!< Filter FIFO 0 assignment for filter x */
+#define CAN_FILTER_FIFO1 (0x00000001U) /*!< Filter FIFO 1 assignment for filter x */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_identifier_type CAN Identifier Type
+ * @{
+ */
+#define CAN_ID_STD (0x00000000U) /*!< Standard Id */
+#define CAN_ID_EXT (0x00000004U) /*!< Extended Id */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
+ * @{
+ */
+#define CAN_RTR_DATA (0x00000000U) /*!< Data frame */
+#define CAN_RTR_REMOTE (0x00000002U) /*!< Remote frame */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_receive_FIFO_number CAN Receive FIFO Number
+ * @{
+ */
+#define CAN_RX_FIFO0 (0x00000000U) /*!< CAN receive FIFO 0 */
+#define CAN_RX_FIFO1 (0x00000001U) /*!< CAN receive FIFO 1 */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Tx_Mailboxes CAN Tx Mailboxes
+ * @{
+ */
+#define CAN_TX_MAILBOX0 (0x00000001U) /*!< Tx Mailbox 0 */
+#define CAN_TX_MAILBOX1 (0x00000002U) /*!< Tx Mailbox 1 */
+#define CAN_TX_MAILBOX2 (0x00000004U) /*!< Tx Mailbox 2 */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_flags CAN Flags
+ * @{
+ */
+/* Transmit Flags */
+#define CAN_FLAG_RQCP0 (0x00000500U) /*!< Request complete MailBox 0 flag */
+#define CAN_FLAG_TXOK0 (0x00000501U) /*!< Transmission OK MailBox 0 flag */
+#define CAN_FLAG_ALST0 (0x00000502U) /*!< Arbitration Lost MailBox 0 flag */
+#define CAN_FLAG_TERR0 (0x00000503U) /*!< Transmission error MailBox 0 flag */
+#define CAN_FLAG_RQCP1 (0x00000508U) /*!< Request complete MailBox1 flag */
+#define CAN_FLAG_TXOK1 (0x00000509U) /*!< Transmission OK MailBox 1 flag */
+#define CAN_FLAG_ALST1 (0x0000050AU) /*!< Arbitration Lost MailBox 1 flag */
+#define CAN_FLAG_TERR1 (0x0000050BU) /*!< Transmission error MailBox 1 flag */
+#define CAN_FLAG_RQCP2 (0x00000510U) /*!< Request complete MailBox2 flag */
+#define CAN_FLAG_TXOK2 (0x00000511U) /*!< Transmission OK MailBox 2 flag */
+#define CAN_FLAG_ALST2 (0x00000512U) /*!< Arbitration Lost MailBox 2 flag */
+#define CAN_FLAG_TERR2 (0x00000513U) /*!< Transmission error MailBox 2 flag */
+#define CAN_FLAG_TME0 (0x0000051AU) /*!< Transmit mailbox 0 empty flag */
+#define CAN_FLAG_TME1 (0x0000051BU) /*!< Transmit mailbox 1 empty flag */
+#define CAN_FLAG_TME2 (0x0000051CU) /*!< Transmit mailbox 2 empty flag */
+#define CAN_FLAG_LOW0 (0x0000051DU) /*!< Lowest priority mailbox 0 flag */
+#define CAN_FLAG_LOW1 (0x0000051EU) /*!< Lowest priority mailbox 1 flag */
+#define CAN_FLAG_LOW2 (0x0000051FU) /*!< Lowest priority mailbox 2 flag */
+
+/* Receive Flags */
+#define CAN_FLAG_FF0 (0x00000203U) /*!< RX FIFO 0 Full flag */
+#define CAN_FLAG_FOV0 (0x00000204U) /*!< RX FIFO 0 Overrun flag */
+#define CAN_FLAG_FF1 (0x00000403U) /*!< RX FIFO 1 Full flag */
+#define CAN_FLAG_FOV1 (0x00000404U) /*!< RX FIFO 1 Overrun flag */
+
+/* Operating Mode Flags */
+#define CAN_FLAG_INAK (0x00000100U) /*!< Initialization acknowledge flag */
+#define CAN_FLAG_SLAK (0x00000101U) /*!< Sleep acknowledge flag */
+#define CAN_FLAG_ERRI (0x00000102U) /*!< Error flag */
+#define CAN_FLAG_WKU (0x00000103U) /*!< Wake up interrupt flag */
+#define CAN_FLAG_SLAKI (0x00000104U) /*!< Sleep acknowledge interrupt flag */
+
+/* Error Flags */
+#define CAN_FLAG_EWG (0x00000300U) /*!< Error warning flag */
+#define CAN_FLAG_EPV (0x00000301U) /*!< Error passive flag */
+#define CAN_FLAG_BOF (0x00000302U) /*!< Bus-Off flag */
+/**
+ * @}
+ */
+
+
+/** @defgroup CAN_Interrupts CAN Interrupts
+ * @{
+ */
+/* Transmit Interrupt */
+#define CAN_IT_TX_MAILBOX_EMPTY ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */
+
+/* Receive Interrupts */
+#define CAN_IT_RX_FIFO0_MSG_PENDING ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */
+#define CAN_IT_RX_FIFO0_FULL ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */
+#define CAN_IT_RX_FIFO0_OVERRUN ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */
+#define CAN_IT_RX_FIFO1_MSG_PENDING ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */
+#define CAN_IT_RX_FIFO1_FULL ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */
+#define CAN_IT_RX_FIFO1_OVERRUN ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */
+
+/* Operating Mode Interrupts */
+#define CAN_IT_WAKEUP ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */
+#define CAN_IT_SLEEP_ACK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */
+
+/* Error Interrupts */
+#define CAN_IT_ERROR_WARNING ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */
+#define CAN_IT_ERROR_PASSIVE ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */
+#define CAN_IT_BUSOFF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */
+#define CAN_IT_LAST_ERROR_CODE ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
+#define CAN_IT_ERROR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup CAN_Exported_Macros CAN Exported Macros
+ * @{
+ */
+
+/** @brief Reset CAN handle state
+ * @param __HANDLE__ CAN handle.
+ * @retval None
+ */
+#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
+
+/**
+ * @brief Enable the specified CAN interrupts.
+ * @param __HANDLE__ CAN handle.
+ * @param __INTERRUPT__ CAN Interrupt sources to enable.
+ * This parameter can be any combination of @arg CAN_Interrupts
+ * @retval None
+ */
+#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the specified CAN interrupts.
+ * @param __HANDLE__ CAN handle.
+ * @param __INTERRUPT__ CAN Interrupt sources to disable.
+ * This parameter can be any combination of @arg CAN_Interrupts
+ * @retval None
+ */
+#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
+
+/** @brief Check if the specified CAN interrupt source is enabled or disabled.
+ * @param __HANDLE__ specifies the CAN Handle.
+ * @param __INTERRUPT__ specifies the CAN interrupt source to check.
+ * This parameter can be a value of @arg CAN_Interrupts
+ * @retval The state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) & (__INTERRUPT__))
+
+/** @brief Check whether the specified CAN flag is set or not.
+ * @param __HANDLE__ specifies the CAN Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of @arg CAN_flags
+ * @retval The state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
+ ((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 3U)? ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)
+
+/** @brief Clear the specified CAN pending flag.
+ * @param __HANDLE__ specifies the CAN Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg CAN_FLAG_RQCP0: Request complete MailBox 0 Flag
+ * @arg CAN_FLAG_TXOK0: Transmission OK MailBox 0 Flag
+ * @arg CAN_FLAG_ALST0: Arbitration Lost MailBox 0 Flag
+ * @arg CAN_FLAG_TERR0: Transmission error MailBox 0 Flag
+ * @arg CAN_FLAG_RQCP1: Request complete MailBox 1 Flag
+ * @arg CAN_FLAG_TXOK1: Transmission OK MailBox 1 Flag
+ * @arg CAN_FLAG_ALST1: Arbitration Lost MailBox 1 Flag
+ * @arg CAN_FLAG_TERR1: Transmission error MailBox 1 Flag
+ * @arg CAN_FLAG_RQCP2: Request complete MailBox 2 Flag
+ * @arg CAN_FLAG_TXOK2: Transmission OK MailBox 2 Flag
+ * @arg CAN_FLAG_ALST2: Arbitration Lost MailBox 2 Flag
+ * @arg CAN_FLAG_TERR2: Transmission error MailBox 2 Flag
+ * @arg CAN_FLAG_FF0: RX FIFO 0 Full Flag
+ * @arg CAN_FLAG_FOV0: RX FIFO 0 Overrun Flag
+ * @arg CAN_FLAG_FF1: RX FIFO 1 Full Flag
+ * @arg CAN_FLAG_FOV1: RX FIFO 1 Overrun Flag
+ * @arg CAN_FLAG_WKUI: Wake up Interrupt Flag
+ * @arg CAN_FLAG_SLAKI: Sleep acknowledge Interrupt Flag
+ * @retval None
+ */
+#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+ ((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CAN_Exported_Functions CAN Exported Functions
+ * @{
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan);
+void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan);
+void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan);
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group2 Configuration functions
+ * @brief Configuration functions
+ * @{
+ */
+
+/* Configuration functions ****************************************************/
+HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig);
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group3 Control functions
+ * @brief Control functions
+ * @{
+ */
+
+/* Control functions **********************************************************/
+HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
+uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox);
+HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes);
+uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan);
+uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes);
+uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox);
+HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]);
+uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo);
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group4 Interrupts management
+ * @brief Interrupts management
+ * @{
+ */
+/* Interrupts management ******************************************************/
+HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs);
+HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs);
+void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan);
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group5 Callback functions
+ * @brief Callback functions
+ * @{
+ */
+/* Callbacks functions ********************************************************/
+
+void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group6 Peripheral State and Error functions
+ * @brief CAN Peripheral State functions
+ * @{
+ */
+/* Peripheral State and Error functions ***************************************/
+HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan);
+uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup CAN_Private_Types CAN Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup CAN_Private_Variables CAN Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup CAN_Private_Constants CAN Private Constants
+ * @{
+ */
+#define CAN_FLAG_MASK (0x000000FFU)
+/**
+ * @}
+ */
+
+/* Private Macros -----------------------------------------------------------*/
+/** @defgroup CAN_Private_Macros CAN Private Macros
+ * @{
+ */
+
+#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
+ ((MODE) == CAN_MODE_LOOPBACK)|| \
+ ((MODE) == CAN_MODE_SILENT) || \
+ ((MODE) == CAN_MODE_SILENT_LOOPBACK))
+#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ) || \
+ ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
+#define IS_CAN_BS1(BS1) (((BS1) == CAN_BS1_1TQ) || ((BS1) == CAN_BS1_2TQ) || \
+ ((BS1) == CAN_BS1_3TQ) || ((BS1) == CAN_BS1_4TQ) || \
+ ((BS1) == CAN_BS1_5TQ) || ((BS1) == CAN_BS1_6TQ) || \
+ ((BS1) == CAN_BS1_7TQ) || ((BS1) == CAN_BS1_8TQ) || \
+ ((BS1) == CAN_BS1_9TQ) || ((BS1) == CAN_BS1_10TQ)|| \
+ ((BS1) == CAN_BS1_11TQ)|| ((BS1) == CAN_BS1_12TQ)|| \
+ ((BS1) == CAN_BS1_13TQ)|| ((BS1) == CAN_BS1_14TQ)|| \
+ ((BS1) == CAN_BS1_15TQ)|| ((BS1) == CAN_BS1_16TQ))
+#define IS_CAN_BS2(BS2) (((BS2) == CAN_BS2_1TQ) || ((BS2) == CAN_BS2_2TQ) || \
+ ((BS2) == CAN_BS2_3TQ) || ((BS2) == CAN_BS2_4TQ) || \
+ ((BS2) == CAN_BS2_5TQ) || ((BS2) == CAN_BS2_6TQ) || \
+ ((BS2) == CAN_BS2_7TQ) || ((BS2) == CAN_BS2_8TQ))
+#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))
+#define IS_CAN_FILTER_ID_HALFWORD(HALFWORD) ((HALFWORD) <= 0xFFFFU)
+#define IS_CAN_FILTER_BANK_DUAL(BANK) ((BANK) <= 27U)
+#define IS_CAN_FILTER_BANK_SINGLE(BANK) ((BANK) <= 13U)
+#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
+ ((MODE) == CAN_FILTERMODE_IDLIST))
+#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
+ ((SCALE) == CAN_FILTERSCALE_32BIT))
+#define IS_CAN_FILTER_ACTIVATION(ACTIVATION) (((ACTIVATION) == CAN_FILTER_DISABLE) || \
+ ((ACTIVATION) == CAN_FILTER_ENABLE))
+#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
+ ((FIFO) == CAN_FILTER_FIFO1))
+#define IS_CAN_TX_MAILBOX(TRANSMITMAILBOX) (((TRANSMITMAILBOX) == CAN_TX_MAILBOX0 ) || \
+ ((TRANSMITMAILBOX) == CAN_TX_MAILBOX1 ) || \
+ ((TRANSMITMAILBOX) == CAN_TX_MAILBOX2 ))
+#define IS_CAN_TX_MAILBOX_LIST(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= (CAN_TX_MAILBOX0 | CAN_TX_MAILBOX1 | CAN_TX_MAILBOX2))
+#define IS_CAN_STDID(STDID) ((STDID) <= 0x7FFU)
+#define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU)
+#define IS_CAN_DLC(DLC) ((DLC) <= 8U)
+#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
+ ((IDTYPE) == CAN_ID_EXT))
+#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
+#define IS_CAN_RX_FIFO(FIFO) (((FIFO) == CAN_RX_FIFO0) || ((FIFO) == CAN_RX_FIFO1))
+#define IS_CAN_IT(IT) ((IT) <= (CAN_IT_TX_MAILBOX_EMPTY | CAN_IT_RX_FIFO0_MSG_PENDING | \
+ CAN_IT_RX_FIFO0_FULL | CAN_IT_RX_FIFO0_OVERRUN | \
+ CAN_IT_RX_FIFO1_MSG_PENDING | CAN_IT_RX_FIFO1_FULL | \
+ CAN_IT_RX_FIFO1_OVERRUN | CAN_IT_WAKEUP | \
+ CAN_IT_SLEEP_ACK | CAN_IT_ERROR_WARNING | \
+ CAN_IT_ERROR_PASSIVE | CAN_IT_BUSOFF | \
+ CAN_IT_LAST_ERROR_CODE | CAN_IT_ERROR))
+
+/**
+ * @}
+ */
+/* End of private macros -----------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+
+#endif /* CAN */
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32F3xx_HAL_CAN_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_hal_cec.h b/Inc/stm32f3xx_hal_cec.h
new file mode 100644
index 0000000..0d39481
--- /dev/null
+++ b/Inc/stm32f3xx_hal_cec.h
@@ -0,0 +1,749 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_cec.h
+ * @author MCD Application Team
+ * @brief Header file of CEC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_CEC_H
+#define __STM32F3xx_HAL_CEC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CEC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CEC_Exported_Types CEC Exported Types
+ * @{
+ */
+
+/**
+ * @brief CEC Init Structure definition
+ */
+typedef struct
+{
+ uint32_t SignalFreeTime; /*!< Set SFT field, specifies the Signal Free Time.
+ It can be one of @ref CEC_Signal_Free_Time
+ and belongs to the set {0U,...,7} where
+ 0x0 is the default configuration
+ else means 0.5U + (SignalFreeTime - 1U) nominal data bit periods */
+
+ uint32_t Tolerance; /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms,
+ it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE
+ or CEC_EXTENDED_TOLERANCE */
+
+ uint32_t BRERxStop; /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception.
+ CEC_NO_RX_STOP_ON_BRE: reception is not stopped.
+ CEC_RX_STOP_ON_BRE: reception is stopped. */
+
+ uint32_t BREErrorBitGen; /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the
+ CEC line upon Bit Rising Error detection.
+ CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation.
+ CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set. */
+
+ uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the
+ CEC line upon Long Bit Period Error detection.
+ CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation.
+ CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */
+
+ uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line
+ upon an error detected on a broadcast message.
+
+ It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values:
+
+ 1U) CEC_BROADCASTERROR_ERRORBIT_GENERATION.
+ a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE
+ and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.
+ b) LBPE detection: error-bit generation on the CEC line
+ if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.
+
+ 2U) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION.
+ no error-bit generation in case neither a) nor b) are satisfied. Additionally,
+ there is no error-bit generation in case of Short Bit Period Error detection in
+ a broadcast message while LSTN bit is set. */
+
+ uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts.
+ CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software.
+ CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end of message transmission/reception. */
+
+ uint32_t ListenMode; /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values:
+
+ CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its
+ own address (OAR). Messages addressed to different destination are ignored.
+ Broadcast messages are always received.
+
+ CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own
+ address (OAR) with positive acknowledge. Messages addressed to different destination
+ are received, but without interfering with the CEC bus: no acknowledge sent. */
+
+ uint16_t OwnAddress; /*!< Own addresses configuration
+ This parameter can be a value of @ref CEC_OWN_ADDRESS */
+
+ uint8_t *RxBuffer; /*!< CEC Rx buffer pointeur */
+
+
+}CEC_InitTypeDef;
+
+/**
+ * @brief HAL CEC State structures definition
+ * @note HAL CEC State value is a combination of 2 different substates: gState and RxState.
+ * - gState contains CEC state information related to global Handle management
+ * and also information related to Tx operations.
+ * gState value coding follow below described bitmap :
+ * b7 (not used)
+ * x : Should be set to 0
+ * b6 Error information
+ * 0 : No Error
+ * 1 : Error
+ * b5 IP initilisation status
+ * 0 : Reset (IP not initialized)
+ * 1 : Init done (IP initialized. HAL CEC Init function already called)
+ * b4-b3 (not used)
+ * xx : Should be set to 00
+ * b2 Intrinsic process state
+ * 0 : Ready
+ * 1 : Busy (IP busy with some configuration or internal operations)
+ * b1 (not used)
+ * x : Should be set to 0
+ * b0 Tx state
+ * 0 : Ready (no Tx operation ongoing)
+ * 1 : Busy (Tx operation ongoing)
+ * - RxState contains information related to Rx operations.
+ * RxState value coding follow below described bitmap :
+ * b7-b6 (not used)
+ * xx : Should be set to 00
+ * b5 IP initilisation status
+ * 0 : Reset (IP not initialized)
+ * 1 : Init done (IP initialized)
+ * b4-b2 (not used)
+ * xxx : Should be set to 000
+ * b1 Rx state
+ * 0 : Ready (no Rx operation ongoing)
+ * 1 : Busy (Rx operation ongoing)
+ * b0 (not used)
+ * x : Should be set to 0.
+ */
+typedef enum
+{
+ HAL_CEC_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
+ Value is allowed for gState and RxState */
+ HAL_CEC_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
+ Value is allowed for gState and RxState */
+ HAL_CEC_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
+ Value is allowed for gState only */
+ HAL_CEC_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
+ Value is allowed for RxState only */
+ HAL_CEC_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
+ Value is allowed for gState only */
+ HAL_CEC_STATE_BUSY_RX_TX = 0x23U, /*!< an internal process is ongoing
+ Value is allowed for gState only */
+HAL_CEC_STATE_ERROR = 0x60U /*!< Error Value is allowed for gState only */
+}HAL_CEC_StateTypeDef;
+
+/**
+ * @brief CEC handle Structure definition
+ */
+typedef struct
+{
+ CEC_TypeDef *Instance; /*!< CEC registers base address */
+
+ CEC_InitTypeDef Init; /*!< CEC communication parameters */
+
+ uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */
+
+ uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */
+
+ uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */
+
+ HAL_LockTypeDef Lock; /*!< Locking object */
+
+ HAL_CEC_StateTypeDef gState; /*!< CEC state information related to global Handle management
+ and also related to Tx operations.
+ This parameter can be a value of @ref HAL_CEC_StateTypeDef */
+
+ HAL_CEC_StateTypeDef RxState; /*!< CEC state information related to Rx operations.
+ This parameter can be a value of @ref HAL_CEC_StateTypeDef */
+
+ uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register
+ in case error is reported */
+}CEC_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CEC_Exported_Constants CEC Exported Constants
+ * @{
+ */
+
+/** @defgroup CEC_Error_Code CEC Error Code
+ * @{
+ */
+#define HAL_CEC_ERROR_NONE (0x00000000U) /*!< no error */
+#define HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR /*!< CEC Rx-Overrun */
+#define HAL_CEC_ERROR_BRE CEC_ISR_BRE /*!< CEC Rx Bit Rising Error */
+#define HAL_CEC_ERROR_SBPE CEC_ISR_SBPE /*!< CEC Rx Short Bit period Error */
+#define HAL_CEC_ERROR_LBPE CEC_ISR_LBPE /*!< CEC Rx Long Bit period Error */
+#define HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE /*!< CEC Rx Missing Acknowledge */
+#define HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST /*!< CEC Arbitration Lost */
+#define HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR /*!< CEC Tx-Buffer Underrun */
+#define HAL_CEC_ERROR_TXERR CEC_ISR_TXERR /*!< CEC Tx-Error */
+#define HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE /*!< CEC Tx Missing Acknowledge */
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Signal_Free_Time CEC Signal Free Time setting parameter
+ * @{
+ */
+#define CEC_DEFAULT_SFT (0x00000000U)
+#define CEC_0_5_BITPERIOD_SFT (0x00000001U)
+#define CEC_1_5_BITPERIOD_SFT (0x00000002U)
+#define CEC_2_5_BITPERIOD_SFT (0x00000003U)
+#define CEC_3_5_BITPERIOD_SFT (0x00000004U)
+#define CEC_4_5_BITPERIOD_SFT (0x00000005U)
+#define CEC_5_5_BITPERIOD_SFT (0x00000006U)
+#define CEC_6_5_BITPERIOD_SFT (0x00000007U)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Tolerance CEC Receiver Tolerance
+ * @{
+ */
+#define CEC_STANDARD_TOLERANCE (0x00000000U)
+#define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_BRERxStop CEC Reception Stop on Error
+ * @{
+ */
+#define CEC_NO_RX_STOP_ON_BRE (0x00000000U)
+#define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_BREErrorBitGen CEC Error Bit Generation if Bit Rise Error reported
+ * @{
+ */
+#define CEC_BRE_ERRORBIT_NO_GENERATION (0x00000000U)
+#define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_LBPEErrorBitGen CEC Error Bit Generation if Long Bit Period Error reported
+ * @{
+ */
+#define CEC_LBPE_ERRORBIT_NO_GENERATION (0x00000000U)
+#define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_BroadCastMsgErrorBitGen CEC Error Bit Generation on Broadcast message
+ * @{
+ */
+#define CEC_BROADCASTERROR_ERRORBIT_GENERATION (0x00000000U)
+#define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_SFT_Option CEC Signal Free Time start option
+ * @{
+ */
+#define CEC_SFT_START_ON_TXSOM (0x00000000U)
+#define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Listening_Mode CEC Listening mode option
+ * @{
+ */
+#define CEC_REDUCED_LISTENING_MODE (0x00000000U)
+#define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_OAR_Position CEC Device Own Address position in CEC CFGR register
+ * @{
+ */
+#define CEC_CFGR_OAR_LSB_POS (16U)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Initiator_Position CEC Initiator logical address position in message header
+ * @{
+ */
+#define CEC_INITIATOR_LSB_POS (4U)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_OWN_ADDRESS CEC Own Address
+ * @{
+ */
+#define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */
+#define CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0U */
+#define CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1U */
+#define CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2U */
+#define CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3U */
+#define CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4U */
+#define CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5U */
+#define CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6U */
+#define CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7U */
+#define CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9U */
+#define CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U) /* Logical Address 10U */
+#define CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U) /* Logical Address 11U */
+#define CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U) /* Logical Address 12U */
+#define CEC_OWN_ADDRESS_12 ((uint16_t) 0x1000U) /* Logical Address 13U */
+#define CEC_OWN_ADDRESS_13 ((uint16_t) 0x2000U) /* Logical Address 14U */
+#define CEC_OWN_ADDRESS_14 ((uint16_t) 0x4000U) /* Logical Address 15U */
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Interrupts_Definitions CEC Interrupts definition
+ * @{
+ */
+#define CEC_IT_TXACKE CEC_IER_TXACKEIE
+#define CEC_IT_TXERR CEC_IER_TXERRIE
+#define CEC_IT_TXUDR CEC_IER_TXUDRIE
+#define CEC_IT_TXEND CEC_IER_TXENDIE
+#define CEC_IT_TXBR CEC_IER_TXBRIE
+#define CEC_IT_ARBLST CEC_IER_ARBLSTIE
+#define CEC_IT_RXACKE CEC_IER_RXACKEIE
+#define CEC_IT_LBPE CEC_IER_LBPEIE
+#define CEC_IT_SBPE CEC_IER_SBPEIE
+#define CEC_IT_BRE CEC_IER_BREIE
+#define CEC_IT_RXOVR CEC_IER_RXOVRIE
+#define CEC_IT_RXEND CEC_IER_RXENDIE
+#define CEC_IT_RXBR CEC_IER_RXBRIE
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Flags_Definitions CEC Flags definition
+ * @{
+ */
+#define CEC_FLAG_TXACKE CEC_ISR_TXACKE
+#define CEC_FLAG_TXERR CEC_ISR_TXERR
+#define CEC_FLAG_TXUDR CEC_ISR_TXUDR
+#define CEC_FLAG_TXEND CEC_ISR_TXEND
+#define CEC_FLAG_TXBR CEC_ISR_TXBR
+#define CEC_FLAG_ARBLST CEC_ISR_ARBLST
+#define CEC_FLAG_RXACKE CEC_ISR_RXACKE
+#define CEC_FLAG_LBPE CEC_ISR_LBPE
+#define CEC_FLAG_SBPE CEC_ISR_SBPE
+#define CEC_FLAG_BRE CEC_ISR_BRE
+#define CEC_FLAG_RXOVR CEC_ISR_RXOVR
+#define CEC_FLAG_RXEND CEC_ISR_RXEND
+#define CEC_FLAG_RXBR CEC_ISR_RXBR
+/**
+ * @}
+ */
+
+/** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags
+ * @{
+ */
+#define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
+ CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag
+ * @{
+ */
+#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag
+ * @{
+ */
+#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup CEC_Exported_Macros CEC Exported Macros
+ * @{
+ */
+
+/** @brief Reset CEC handle gstate & RxState
+ * @param __HANDLE__ CEC handle.
+ * @retval None
+ */
+#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->gState = HAL_CEC_STATE_RESET; \
+ (__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \
+ } while(0U)
+
+/** @brief Checks whether or not the specified CEC interrupt flag is set.
+ * @param __HANDLE__ specifies the CEC Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
+ * @arg CEC_FLAG_TXERR: Tx Error.
+ * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
+ * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
+ * @arg CEC_FLAG_TXBR: Tx-Byte Request.
+ * @arg CEC_FLAG_ARBLST: Arbitration Lost
+ * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
+ * @arg CEC_FLAG_LBPE: Rx Long period Error
+ * @arg CEC_FLAG_SBPE: Rx Short period Error
+ * @arg CEC_FLAG_BRE: Rx Bit Rising Error
+ * @arg CEC_FLAG_RXOVR: Rx Overrun.
+ * @arg CEC_FLAG_RXEND: End Of Reception.
+ * @arg CEC_FLAG_RXBR: Rx-Byte Received.
+ * @retval ITStatus
+ */
+#define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
+
+/** @brief Clears the interrupt or status flag when raised (write at 1U)
+ * @param __HANDLE__ specifies the CEC Handle.
+ * @param __FLAG__ specifies the interrupt/status flag to clear.
+ * This parameter can be one of the following values:
+ * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
+ * @arg CEC_FLAG_TXERR: Tx Error.
+ * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
+ * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
+ * @arg CEC_FLAG_TXBR: Tx-Byte Request.
+ * @arg CEC_FLAG_ARBLST: Arbitration Lost
+ * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
+ * @arg CEC_FLAG_LBPE: Rx Long period Error
+ * @arg CEC_FLAG_SBPE: Rx Short period Error
+ * @arg CEC_FLAG_BRE: Rx Bit Rising Error
+ * @arg CEC_FLAG_RXOVR: Rx Overrun.
+ * @arg CEC_FLAG_RXEND: End Of Reception.
+ * @arg CEC_FLAG_RXBR: Rx-Byte Received.
+ * @retval none
+ */
+#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__))
+
+/** @brief Enables the specified CEC interrupt.
+ * @param __HANDLE__ specifies the CEC Handle.
+ * @param __INTERRUPT__ specifies the CEC interrupt to enable.
+ * This parameter can be one of the following values:
+ * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
+ * @arg CEC_IT_TXERR: Tx Error IT Enable
+ * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
+ * @arg CEC_IT_TXEND: End of transmission IT Enable
+ * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
+ * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
+ * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
+ * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
+ * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
+ * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
+ * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
+ * @arg CEC_IT_RXEND: End Of Reception IT Enable
+ * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
+ * @retval none
+ */
+#define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
+
+/** @brief Disables the specified CEC interrupt.
+ * @param __HANDLE__ specifies the CEC Handle.
+ * @param __INTERRUPT__ specifies the CEC interrupt to disable.
+ * This parameter can be one of the following values:
+ * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
+ * @arg CEC_IT_TXERR: Tx Error IT Enable
+ * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
+ * @arg CEC_IT_TXEND: End of transmission IT Enable
+ * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
+ * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
+ * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
+ * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
+ * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
+ * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
+ * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
+ * @arg CEC_IT_RXEND: End Of Reception IT Enable
+ * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
+ * @retval none
+ */
+#define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
+
+/** @brief Checks whether or not the specified CEC interrupt is enabled.
+ * @param __HANDLE__ specifies the CEC Handle.
+ * @param __INTERRUPT__ specifies the CEC interrupt to check.
+ * This parameter can be one of the following values:
+ * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
+ * @arg CEC_IT_TXERR: Tx Error IT Enable
+ * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
+ * @arg CEC_IT_TXEND: End of transmission IT Enable
+ * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
+ * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
+ * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
+ * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
+ * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
+ * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
+ * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
+ * @arg CEC_IT_RXEND: End Of Reception IT Enable
+ * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
+ * @retval FlagStatus
+ */
+#define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
+
+/** @brief Enables the CEC device
+ * @param __HANDLE__ specifies the CEC Handle.
+ * @retval none
+ */
+#define __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN)
+
+/** @brief Disables the CEC device
+ * @param __HANDLE__ specifies the CEC Handle.
+ * @retval none
+ */
+#define __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN)
+
+/** @brief Set Transmission Start flag
+ * @param __HANDLE__ specifies the CEC Handle.
+ * @retval none
+ */
+#define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM)
+
+/** @brief Set Transmission End flag
+ * @param __HANDLE__ specifies the CEC Handle.
+ * @retval none
+ * If the CEC message consists of only one byte, TXEOM must be set before of TXSOM.
+ */
+#define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM)
+
+/** @brief Get Transmission Start flag
+ * @param __HANDLE__ specifies the CEC Handle.
+ * @retval FlagStatus
+ */
+#define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
+
+/** @brief Get Transmission End flag
+ * @param __HANDLE__ specifies the CEC Handle.
+ * @retval FlagStatus
+ */
+#define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
+
+/** @brief Clear OAR register
+ * @param __HANDLE__ specifies the CEC Handle.
+ * @retval none
+ */
+#define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
+
+/** @brief Set OAR register (without resetting previously set address in case of multi-address mode)
+ * To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand
+ * @param __HANDLE__ specifies the CEC Handle.
+ * @param __ADDRESS__ Own Address value (CEC logical address is identified by bit position)
+ * @retval none
+ */
+#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CEC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup CEC_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
+HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
+HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress);
+void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
+void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
+/**
+ * @}
+ */
+
+/** @addtogroup CEC_Exported_Functions_Group2
+ * @{
+ */
+/* I/O operation functions ***************************************************/
+HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);
+uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec);
+void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer);
+void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
+void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
+void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize);
+void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
+/**
+ * @}
+ */
+
+/** @addtogroup CEC_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral State functions ************************************************/
+HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);
+uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup CEC_Private_Types CEC Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup CEC_Private_Variables CEC Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup CEC_Private_Constants CEC Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CEC_Private_Macros CEC Private Macros
+ * @{
+ */
+
+#define IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT)
+
+#define IS_CEC_TOLERANCE(__RXTOL__) (((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \
+ ((__RXTOL__) == CEC_EXTENDED_TOLERANCE))
+
+#define IS_CEC_BRERXSTOP(__BRERXSTOP__) (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \
+ ((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE))
+
+#define IS_CEC_BREERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \
+ ((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION))
+
+#define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \
+ ((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION))
+
+#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
+ ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))
+
+#define IS_CEC_SFTOP(__SFTOP__) (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \
+ ((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END))
+
+#define IS_CEC_LISTENING_MODE(__MODE__) (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \
+ ((__MODE__) == CEC_FULL_LISTENING_MODE))
+
+/** @brief Check CEC message size.
+ * The message size is the payload size: without counting the header,
+ * it varies from 0 byte (ping operation, one header only, no payload) to
+ * 15 bytes (1 opcode and up to 14 operands following the header).
+ * @param __SIZE__ CEC message size.
+ * @retval Test result (TRUE or FALSE).
+ */
+#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U)
+
+/** @brief Check CEC device Own Address Register (OAR) setting.
+ * OAR address is written in a 15-bit field within CEC_CFGR register.
+ * @param __ADDRESS__ CEC own address.
+ * @retval Test result (TRUE or FALSE).
+ */
+#define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFFU)
+
+/** @brief Check CEC initiator or destination logical address setting.
+ * Initiator and destination addresses are coded over 4 bits.
+ * @param __ADDRESS__ CEC initiator or logical address.
+ * @retval Test result (TRUE or FALSE).
+ */
+#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0FU)
+/**
+ * @}
+ */
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup CEC_Private_Functions CEC Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(STM32F373xC) || defined(STM32F378xx) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_CEC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Inc/stm32f3xx_hal_comp.h b/Inc/stm32f3xx_hal_comp.h
new file mode 100644
index 0000000..f1e6b4e
--- /dev/null
+++ b/Inc/stm32f3xx_hal_comp.h
@@ -0,0 +1,292 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_comp.h
+ * @author MCD Application Team
+ * @brief Header file of COMP HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_COMP_H
+#define __STM32F3xx_HAL_COMP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup COMP
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup COMP_Exported_Types COMP Exported Types
+ * @{
+ */
+/**
+ * @brief COMP Init structure definition
+ */
+typedef struct
+{
+
+ uint32_t InvertingInput; /*!< Selects the inverting input of the comparator.
+ This parameter can be a value of @ref COMPEx_InvertingInput */
+
+ uint32_t NonInvertingInput; /*!< Selects the non inverting input of the comparator.
+ This parameter can be a value of @ref COMPEx_NonInvertingInput
+ Note: Only available on STM32F302xB/xC, STM32F303xB/xC and STM32F358xx devices */
+
+ uint32_t Output; /*!< Selects the output redirection of the comparator.
+ This parameter can be a value of @ref COMPEx_Output */
+
+ uint32_t OutputPol; /*!< Selects the output polarity of the comparator.
+ This parameter can be a value of @ref COMP_OutputPolarity */
+
+ uint32_t Hysteresis; /*!< Selects the hysteresis voltage of the comparator.
+ This parameter can be a value of @ref COMPEx_Hysteresis
+ Note: Only available on STM32F302xB/xC, STM32F303xB/xC, STM32F373xB/xC, STM32F358xx and STM32F378xx devices */
+
+ uint32_t BlankingSrce; /*!< Selects the output blanking source of the comparator.
+ This parameter can be a value of @ref COMPEx_BlankingSrce
+ Note: Not available on STM32F373xB/C and STM32F378xx devices */
+
+ uint32_t Mode; /*!< Selects the operating consumption mode of the comparator
+ to adjust the speed/consumption.
+ This parameter can be a value of @ref COMPEx_Mode
+ Note: Not available on STM32F301x6/x8, STM32F302x6/x8, STM32F334x6/x8, STM32F318xx and STM32F328xx devices */
+
+ uint32_t WindowMode; /*!< Selects the window mode of the comparator X (X=2U, 4 or 6 if available).
+ This parameter can be a value of @ref COMPEx_WindowMode */
+
+ uint32_t TriggerMode; /*!< Selects the trigger mode of the comparator (interrupt mode).
+ This parameter can be a value of @ref COMP_TriggerMode */
+
+} COMP_InitTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_COMP_STATE_RESET = 0x00U, /*!< COMP not yet initialized or disabled */
+ HAL_COMP_STATE_READY = 0x01U, /*!< COMP initialized and ready for use */
+ HAL_COMP_STATE_READY_LOCKED = 0x11U, /*!< COMP initialized but the configuration is locked */
+ HAL_COMP_STATE_BUSY = 0x02U, /*!< COMP is running */
+ HAL_COMP_STATE_BUSY_LOCKED = 0x12 /*!< COMP is running and the configuration is locked */
+} HAL_COMP_StateTypeDef;
+
+/**
+ * @brief COMP Handle Structure definition
+ */
+typedef struct
+{
+ COMP_TypeDef *Instance; /*!< Register base address */
+ COMP_InitTypeDef Init; /*!< COMP required parameters */
+ HAL_LockTypeDef Lock; /*!< Locking object */
+ __IO HAL_COMP_StateTypeDef State; /*!< COMP communication state */
+} COMP_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup COMP_Exported_Constants COMP Exported Constants
+ * @{
+ */
+
+/** @defgroup COMP_OutputPolarity COMP Output Polarity
+ * @{
+ */
+#define COMP_OUTPUTPOL_NONINVERTED (0x00000000U) /*!< COMP output on GPIO isn't inverted */
+#define COMP_OUTPUTPOL_INVERTED COMP_CSR_COMPxPOL /*!< COMP output on GPIO is inverted */
+/**
+ * @}
+ */
+
+/** @defgroup COMP_OutputLevel COMP Output Level
+ * @{
+ */
+/* When output polarity is not inverted, comparator output is low when
+ the non-inverting input is at a lower voltage than the inverting input*/
+#define COMP_OUTPUTLEVEL_LOW (0x00000000U)
+/* When output polarity is not inverted, comparator output is high when
+ the non-inverting input is at a higher voltage than the inverting input */
+#define COMP_OUTPUTLEVEL_HIGH COMP_CSR_COMPxOUT
+/**
+ * @}
+ */
+
+/** @defgroup COMP_TriggerMode COMP Trigger Mode
+ * @{
+ */
+#define COMP_TRIGGERMODE_NONE (0x00000000U) /*!< No External Interrupt trigger detection */
+#define COMP_TRIGGERMODE_IT_RISING (0x00000001U) /*!< External Interrupt Mode with Rising edge trigger detection */
+#define COMP_TRIGGERMODE_IT_FALLING (0x00000002U) /*!< External Interrupt Mode with Falling edge trigger detection */
+#define COMP_TRIGGERMODE_IT_RISING_FALLING (0x00000003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+#define COMP_TRIGGERMODE_EVENT_RISING (0x00000010U) /*!< Event Mode with Rising edge trigger detection */
+#define COMP_TRIGGERMODE_EVENT_FALLING (0x00000020U) /*!< Event Mode with Falling edge trigger detection */
+#define COMP_TRIGGERMODE_EVENT_RISING_FALLING (0x00000030U) /*!< Event Mode with Rising/Falling edge trigger detection */
+/**
+ * @}
+ */
+
+/** @defgroup COMP_State_Lock COMP State Lock
+ * @{
+ */
+#define COMP_STATE_BIT_LOCK (0x00000010U) /* Lock bit in COMP handle state */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup COMP_Exported_Macros COMP Exported Macros
+ * @{
+ */
+
+/** @brief Reset COMP handle state.
+ * @param __HANDLE__ COMP handle.
+ * @retval None
+ */
+#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
+/**
+ * @}
+ */
+
+/* Include COMP HAL Extended module */
+#include "stm32f3xx_hal_comp_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup COMP_Exported_Functions
+ * @{
+ */
+/** @addtogroup COMP_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp);
+HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp);
+void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp);
+void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp);
+/**
+ * @}
+ */
+
+/* IO operation functions *****************************************************/
+/** @addtogroup COMP_Exported_Functions_Group2
+ * @{
+ */
+HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp);
+HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp);
+HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp);
+HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp);
+void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp);
+/* Callback in Interrupt mode */
+void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp);
+/**
+ * @}
+ */
+
+/* Peripheral Control functions ************************************************/
+/** @addtogroup COMP_Exported_Functions_Group3
+ * @{
+ */
+HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp);
+uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp);
+/**
+ * @}
+ */
+
+/* Peripheral State functions **************************************************/
+/** @addtogroup COMP_Exported_Functions_Group4
+ * @{
+ */
+HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup COMP_Private_Macros COMP Private Macros
+ * @{
+ */
+
+/** @defgroup COMP_IS_COMP_Definitions COMP Private macros to check input parameters
+ * @{
+ */
+
+#define IS_COMP_OUTPUTPOL(__POL__) (((__POL__) == COMP_OUTPUTPOL_NONINVERTED) || \
+ ((__POL__) == COMP_OUTPUTPOL_INVERTED))
+
+#define IS_COMP_TRIGGERMODE(__MODE__) (((__MODE__) == COMP_TRIGGERMODE_NONE) || \
+ ((__MODE__) == COMP_TRIGGERMODE_IT_RISING) || \
+ ((__MODE__) == COMP_TRIGGERMODE_IT_FALLING) || \
+ ((__MODE__) == COMP_TRIGGERMODE_IT_RISING_FALLING) || \
+ ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING) || \
+ ((__MODE__) == COMP_TRIGGERMODE_EVENT_FALLING) || \
+ ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING_FALLING))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_COMP_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_hal_comp_ex.h b/Inc/stm32f3xx_hal_comp_ex.h
new file mode 100644
index 0000000..c98de2d
--- /dev/null
+++ b/Inc/stm32f3xx_hal_comp_ex.h
@@ -0,0 +1,2796 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_comp_ex.h
+ * @author MCD Application Team
+ * @brief Header file of COMP HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_COMP_EX_H
+#define __STM32F3xx_HAL_COMP_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup COMPEx COMPEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup COMPEx_Exported_Constants COMP Extended Exported Constants
+ * @{
+ */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+/** @defgroup COMPEx_InvertingInput COMP Extended InvertingInput (STM32F302xE/STM32F303xE/STM32F398xx/STM32F302xC/STM32F303xC/STM32F358xx Product devices)
+ * @{
+ */
+#define COMP_INVERTINGINPUT_1_4VREFINT (0x00000000U) /*!< 1U/4 VREFINT connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_1_2VREFINT COMP_CSR_COMPxINSEL_0 /*!< 1U/2 VREFINT connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_3_4VREFINT COMP_CSR_COMPxINSEL_1 /*!< 3U/4 VREFINT connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_VREFINT (COMP_CSR_COMPxINSEL_1|COMP_CSR_COMPxINSEL_0) /*!< VREFINT connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_CSR_COMPxINSEL_2 /*!< DAC1_CH1_OUT (PA4) connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_DAC1_CH2 (COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_0) /*!< DAC1_CH2_OUT (PA5) connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_IO1 (COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_1) /*!< IO1 (PA0 for COMP1, PA2 for COMP2, PD15 for COMP3,
+ PE8 for COMP4, PD13 for COMP5, PD10 for COMP6,
+ PC0 for COMP7) connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_IO2 COMP_CSR_COMPxINSEL /*!< IO2 (PB12 for COMP3, PB2 for COMP4, PB10 for COMP5,
+ PB15 for COMP6) connected to comparator inverting input */
+/* Aliases for compatibility */
+#define COMP_INVERTINGINPUT_DAC1 COMP_INVERTINGINPUT_DAC1_CH1
+#define COMP_INVERTINGINPUT_DAC2 COMP_INVERTINGINPUT_DAC1_CH2
+/**
+ * @}
+ */
+#elif defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/** @defgroup COMPEx_InvertingInput COMP Extended InvertingInput (STM32F301x8/STM32F302x8/STM32F318xx Product devices)
+ * @{
+ */
+#define COMP_INVERTINGINPUT_1_4VREFINT (0x00000000U) /*!< 1U/4 VREFINT connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_1_2VREFINT COMP_CSR_COMPxINSEL_0 /*!< 1U/2 VREFINT connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_3_4VREFINT COMP_CSR_COMPxINSEL_1 /*!< 3U/4 VREFINT connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_VREFINT (COMP_CSR_COMPxINSEL_1|COMP_CSR_COMPxINSEL_0) /*!< VREFINT connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_CSR_COMPxINSEL_2 /*!< DAC1_CH1_OUT (PA4) connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_IO1 (COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_1) /*!< IO1 (PA2 for COMP2),
+ connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_IO2 COMP_CSR_COMPxINSEL /*!< IO2 (PB2 for COMP4, PB15 for COMP6)
+ connected to comparator inverting input */
+/* Aliases for compatibility */
+#define COMP_INVERTINGINPUT_DAC1 COMP_INVERTINGINPUT_DAC1_CH1
+/**
+ * @}
+ */
+#elif defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+/** @defgroup COMPEx_InvertingInput COMP Extended InvertingInput (STM32F303x8/STM32F334x8/STM32F328xx Product devices)
+ * @{
+ */
+/* Note: On these STM32 devices, there is only 1 comparator inverting input */
+/* connected to a GPIO. */
+/* It must be chosen among the 2 literals COMP_INVERTINGINPUT_IOx */
+/* depending on comparator instance COMPx. */
+#define COMP_INVERTINGINPUT_1_4VREFINT (0x00000000U) /*!< 1U/4 VREFINT connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_1_2VREFINT COMP_CSR_COMPxINSEL_0 /*!< 1U/2 VREFINT connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_3_4VREFINT COMP_CSR_COMPxINSEL_1 /*!< 3U/4 VREFINT connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_VREFINT (COMP_CSR_COMPxINSEL_1|COMP_CSR_COMPxINSEL_0) /*!< VREFINT connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_CSR_COMPxINSEL_2 /*!< DAC1_CH1_OUT (PA4) connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_DAC1_CH2 (COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_0) /*!< DAC1_CH2_OUT (PA5) connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_IO1 (COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_1) /*!< IO1 (PA2 for COMP2),
+ connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_IO2 COMP_CSR_COMPxINSEL /*!< IO2 (PB2 for COMP4, PB15 for COMP6)
+ connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_DAC2_CH1 COMP_CSR_COMPxINSEL_3 /*!< DAC2_CH1_OUT connected to comparator inverting input */
+
+/* Aliases for compatibility */
+#define COMP_INVERTINGINPUT_DAC1 COMP_INVERTINGINPUT_DAC1_CH1
+#define COMP_INVERTINGINPUT_DAC2 COMP_INVERTINGINPUT_DAC1_CH2
+/**
+ * @}
+ */
+#elif defined(STM32F373xC) || defined(STM32F378xx)
+/** @defgroup COMPEx_InvertingInput COMP Extended InvertingInput (STM32F373xC/STM32F378xx Product devices)
+ * @{
+ */
+#define COMP_INVERTINGINPUT_1_4VREFINT (0x00000000U) /*!< 1U/4 VREFINT connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_1_2VREFINT ((uint32_t)COMP_CSR_COMPxINSEL_0) /*!< 1U/2 VREFINT connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_3_4VREFINT ((uint32_t)COMP_CSR_COMPxINSEL_1) /*!< 3U/4 VREFINT connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_VREFINT ((uint32_t)(COMP_CSR_COMPxINSEL_1|COMP_CSR_COMPxINSEL_0)) /*!< VREFINT connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_DAC1_CH1 ((uint32_t)COMP_CSR_COMPxINSEL_2) /*!< DAC1_CH1_OUT (PA4) connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_DAC1_CH2 ((uint32_t)(COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_0)) /*!< DAC1_CH2_OUT (PA5) connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_IO1 ((uint32_t)(COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_1)) /*!< IO1 (PA0 for COMP1, PA2 for COMP2) connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_DAC2_CH1 ((uint32_t)COMP_CSR_COMPxINSEL) /*!< DAC2_CH1_OUT connected to comparator inverting input */
+
+/* Aliases for compatibility */
+#define COMP_INVERTINGINPUT_DAC1 COMP_INVERTINGINPUT_DAC1_CH1
+#define COMP_INVERTINGINPUT_DAC2 COMP_INVERTINGINPUT_DAC1_CH2
+/**
+ * @}
+ */
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+/** @defgroup COMPEx_NonInvertingInput COMP Extended NonInvertingInput (STM32F302xC/STM32F303xC/STM32F358xx Product devices)
+ * @{
+ */
+#define COMP_NONINVERTINGINPUT_IO1 (0x00000000U) /*!< IO1 (PA1 for COMP1, PA7 for COMP2, PB14 for COMP3,
+ PB0 for COMP4, PD12 for COMP5, PD11 for COMP6,
+ PA0 for COMP7) connected to comparator non inverting input */
+#define COMP_NONINVERTINGINPUT_IO2 COMP_CSR_COMPxNONINSEL /*!< IO2 (PA3 for COMP2, PD14 for COMP3, PE7 for COMP4, PB13 for COMP5,
+ PB11 for COMP6, PC1 for COMP7) connected to comparator non inverting input */
+#define COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED COMP1_CSR_COMP1SW1 /*!< DAC ouput connected to comparator COMP1 non inverting input */
+/**
+ * @}
+ */
+#elif defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/** @defgroup COMPEx_NonInvertingInput COMP Extended NonInvertingInput (STM32F301x8/STM32F302x8/STM32F318xx Product devices)
+ * @{
+ */
+#define COMP_NONINVERTINGINPUT_IO1 (0x00000000U) /*!< IO1 (PA7 for COMP2, PB0 for COMP4, PB11 for COMP6)
+ connected to comparator non inverting input */
+#define COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED COMP2_CSR_COMP2INPDAC /*!< DAC ouput connected to comparator COMP2 non inverting input */
+/**
+ * @}
+ */
+#elif defined(STM32F373xC) || defined(STM32F378xx)
+/** @defgroup COMPEx_NonInvertingInput COMP Extended NonInvertingInput (STM32F373xC/STM32F378xx Product devices)
+ * @{
+ */
+#define COMP_NONINVERTINGINPUT_IO1 (0x00000000U) /*!< IO1 (PA1 for COMP1, PA3 for COMP2)
+ connected to comparator non inverting input */
+#define COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED COMP_CSR_COMP1SW1 /*!< DAC ouput connected to comparator COMP1 non inverting input */
+/**
+ * @}
+ */
+#elif defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+/** @defgroup COMPEx_NonInvertingInput COMP Extended NonInvertingInput (STM32F302xE/STM32F303xE/STM32F398xx Product devices)
+ * @{
+ */
+#define COMP_NONINVERTINGINPUT_IO1 (0x00000000U) /*!< IO1 (PA1 for COMP1, PA7 for COMP2, PB14 for COMP3,
+ PB0 for COMP4, PD12 for COMP5, PD11 for COMP6,
+ PA0 for COMP7) connected to comparator non inverting input */
+#define COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED COMP1_CSR_COMP1SW1 /*!< DAC ouput connected to comparator COMP1 non inverting input */
+/**
+ * @}
+ */
+#else
+/** @defgroup COMPEx_NonInvertingInput COMP Extended NonInvertingInput (Other Product devices)
+ * @{
+ */
+#define COMP_NONINVERTINGINPUT_IO1 (0x00000000U) /*!< IO1 (PA7 for COMP2, PB0 for COMP4, PB11 for COMP6)
+ connected to comparator non inverting input */
+/**
+ * @}
+ */
+#endif /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/** @defgroup COMPEx_Output COMP Extended Output (STM32F301x8/STM32F302x8/STM32F318xx Product devices)
+ * Elements value convention on 16 LSB: 00XXXX0000YYYYYYb
+ * - YYYYYY : Applicable comparator instance number (bitmap format: 000010 for COMP2, 100000 for COMP6)
+ * - XXXX : COMPxOUTSEL value
+ * @{
+ */
+/* Output Redirection values common to all comparators COMP2, COMP4 and COMP6 */
+#define COMP_OUTPUT_NONE (0x0000002AU) /*!< COMP2, COMP4 or COMP6 output isn't connected to other peripherals */
+#define COMP_OUTPUT_TIM1BKIN (0x0000042AU) /*!< COMP2, COMP4 or COMP6 output connected to TIM1 Break Input (BKIN) */
+#define COMP_OUTPUT_TIM1BKIN2_BRK2 (0x0000082AU) /*!< COMP2, COMP4 or COMP6 output connected to TIM1 Break Input 2 (BRK2) */
+#define COMP_OUTPUT_TIM1BKIN2 (0x0000142AU) /*!< COMP2, COMP4 or COMP6 output connected to TIM1 Break Input 2 (BKIN2) */
+/* Output Redirection specific to COMP2 */
+#define COMP_OUTPUT_TIM1OCREFCLR (0x00001802U) /*!< COMP2 output connected to TIM1 OCREF Clear */
+#define COMP_OUTPUT_TIM1IC1 (0x00001C02U) /*!< COMP2 output connected to TIM1 Input Capture 1U */
+#define COMP_OUTPUT_TIM2IC4 (0x00002002U) /*!< COMP2 output connected to TIM2 Input Capture 4U */
+#define COMP_OUTPUT_TIM2OCREFCLR (0x00002402U) /*!< COMP2 output connected to TIM2 OCREF Clear */
+/* Output Redirection specific to COMP4 */
+#define COMP_OUTPUT_TIM15IC2 (0x00002008U) /*!< COMP4 output connected to TIM15 Input Capture 2U */
+#define COMP_OUTPUT_TIM15OCREFCLR (0x00002808U) /*!< COMP4 output connected to TIM15 OCREF Clear */
+/* Output Redirection specific to COMP6 */
+#define COMP_OUTPUT_TIM2IC2 (0x00001820U) /*!< COMP6 output connected to TIM2 Input Capture 2U */
+#define COMP_OUTPUT_COMP6_TIM2OCREFCLR (0x00002020U) /*!< COMP6 output connected to TIM2 OCREF Clear */
+#define COMP_OUTPUT_TIM16OCREFCLR (0x00002420U) /*!< COMP6 output connected to TIM16 OCREF Clear */
+#define COMP_OUTPUT_TIM16IC1 (0x00002820U) /*!< COMP6 output connected to TIM16 Input Capture 1U */
+/**
+ * @}
+ */
+#elif defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+/** @defgroup COMPEx_Output COMP Extended Output (STM32F303x8/STM32F334x8/STM32F328xx Product devices)
+ * Elements value convention on 16 LSB: 00XXXX0000YYYYYYb
+ * - YYYYYY : Applicable comparator instance number (bitmap format: 000010 for COMP2, 100000 for COMP6)
+ * - XXXX : COMPxOUTSEL value
+ * @{
+ */
+/* Output Redirection values common to all comparators COMP2, COMP4 and COMP6 */
+#define COMP_OUTPUT_NONE (0x0000002AU) /*!< COMP2, COMP4 or COMP6 output isn't connected to other peripherals */
+#define COMP_OUTPUT_TIM1BKIN (0x0000042AU) /*!< COMP2, COMP4 or COMP6 output connected to TIM1 Break Input (BKIN) */
+#define COMP_OUTPUT_TIM1BKIN2 (0x0000082AU) /*!< COMP2, COMP4 or COMP6 output connected to TIM1 Break Input 2 (BKIN2) */
+/* Output Redirection common to COMP2 and COMP4 */
+#define COMP_OUTPUT_TIM3OCREFCLR (0x00002C0AU) /*!< COMP2 or COMP4 output connected to TIM3 OCREF Clear */
+/* Output Redirection specific to COMP2 */
+#define COMP_OUTPUT_TIM1OCREFCLR (0x00001802U) /*!< COMP2 output connected to TIM1 OCREF Clear */
+#define COMP_OUTPUT_TIM1IC1 (0x00001C02U) /*!< COMP2 output connected to TIM1 Input Capture 1U */
+#define COMP_OUTPUT_TIM2IC4 (0x00002002U) /*!< COMP2 output connected to TIM2 Input Capture 4U */
+#define COMP_OUTPUT_TIM2OCREFCLR (0x00002402U) /*!< COMP2 output connected to TIM2 OCREF Clear */
+#define COMP_OUTPUT_TIM3IC1 (0x00002802U) /*!< COMP2 output connected to TIM3 Input Capture 1U */
+/* Output Redirection specific to COMP4 */
+#define COMP_OUTPUT_TIM3IC3 (0x00001808U) /*!< COMP4 output connected to TIM3 Input Capture 3U */
+#define COMP_OUTPUT_TIM15IC2 (0x00002008U) /*!< COMP4 output connected to TIM15 Input Capture 2U */
+#define COMP_OUTPUT_TIM15OCREFCLR (0x00002808U) /*!< COMP4 output connected to TIM15 OCREF Clear */
+/* Output Redirection specific to COMP6 */
+#define COMP_OUTPUT_TIM2IC2 (0x00001820U) /*!< COMP6 output connected to TIM2 Input Capture 2U */
+#define COMP_OUTPUT_COMP6_TIM2OCREFCLR (0x00002020U) /*!< COMP6 output connected to TIM2 OCREF Clear */
+#define COMP_OUTPUT_TIM16OCREFCLR (0x00002420U) /*!< COMP6 output connected to TIM16 OCREF Clear */
+#define COMP_OUTPUT_TIM16IC1 (0x00002820U) /*!< COMP6 output connected to TIM16 Input Capture 1U */
+/**
+ * @}
+ */
+#elif defined(STM32F302xC) || defined(STM32F302xE)
+/** @defgroup COMPEx_Output COMP Extended Output (STM32F302xC/STM32F302xE Product devices)
+ * Elements value convention on 16 LSB: 00XXXX0000YYYYYYb
+ * - YYYYYY : Applicable comparator instance number (bitmap format: 000001 for COMP1, 100000 for COMP6)
+ * - XXXX : COMPxOUTSEL value
+ * @{
+ */
+/* Output Redirection values common to all comparators COMP1, COMP2, COMP4, COMP6 */
+#define COMP_OUTPUT_NONE (0x0000002BU) /*!< COMP1, COMP2, COMP4 or COMP6 output isn't connected to other peripherals */
+#define COMP_OUTPUT_TIM1BKIN (0x0000042BU) /*!< COMP1, COMP2, COMP4 or COMP6 output connected to TIM1 Break Input (BKIN) */
+#define COMP_OUTPUT_TIM1BKIN2_BRK2 (0x0000082BU) /*!< COMP1, COMP2, COMP4 or COMP6 output connected to TIM1 Break Input 2 (BRK2) */
+#define COMP_OUTPUT_TIM1BKIN2 (0x0000142BU) /*!< COMP1, COMP2, COMP4 or COMP6 output connected to TIM1 Break Input 2 (BKIN2) */
+/* Output Redirection common to COMP1 and COMP2 */
+#define COMP_OUTPUT_TIM1OCREFCLR (0x00001803U) /*!< COMP1 or COMP2 output connected to TIM1 OCREF Clear */
+#define COMP_OUTPUT_TIM1IC1 (0x00001C03U) /*!< COMP1 or COMP2 output connected to TIM1 Input Capture 1U */
+#define COMP_OUTPUT_TIM2IC4 (0x00002003U) /*!< COMP1 or COMP2 output connected to TIM2 Input Capture 4U */
+#define COMP_OUTPUT_TIM2OCREFCLR (0x00002403U) /*!< COMP1 or COMP2 output connected to TIM2 OCREF Clear */
+#define COMP_OUTPUT_TIM3IC1 (0x00002803U) /*!< COMP1 or COMP2 output connected to TIM3 Input Capture 1U */
+/* Output Redirection common to COMP1,COMP2 and COMP4 */
+#define COMP_OUTPUT_TIM3OCREFCLR (0x00002C0BU) /*!< COMP1, COMP2 or COMP4 output connected to TIM3 OCREF Clear */
+/* Output Redirection specific to COMP4 */
+#define COMP_OUTPUT_TIM3IC3 (0x00001808U) /*!< COMP4 output connected to TIM3 Input Capture 3U */
+#define COMP_OUTPUT_TIM15IC2 (0x00002008U) /*!< COMP4 output connected to TIM15 Input Capture 2U */
+#define COMP_OUTPUT_TIM4IC2 (0x00002408U) /*!< COMP4 output connected to TIM4 Input Capture 2U */
+#define COMP_OUTPUT_TIM15OCREFCLR (0x00002808U) /*!< COMP4 output connected to TIM15 OCREF Clear */
+/* Output Redirection specific to COMP6 */
+#define COMP_OUTPUT_TIM2IC2 (0x00001820U) /*!< COMP6 output connected to TIM2 Input Capture 2U */
+#define COMP_OUTPUT_COMP6_TIM2OCREFCLR (0x00002020U) /*!< COMP6 output connected to TIM2 OCREF Clear */
+#define COMP_OUTPUT_TIM16OCREFCLR (0x00002420U) /*!< COMP6 output connected to TIM16 OCREF Clear */
+#define COMP_OUTPUT_TIM16IC1 (0x00002820U) /*!< COMP6 output connected to TIM16 Input Capture 1U */
+#define COMP_OUTPUT_TIM4IC4 (0x00002C20U) /*!< COMP6 output connected to TIM4 Input Capture 4U */
+/**
+ * @}
+ */
+#elif defined(STM32F303xC) || defined(STM32F358xx)
+/** @defgroup COMPEx_Output COMP Extended Output (STM32F303xC/STM32F358xx Product devices)
+ * Elements value convention on 16 LSB: 00XXXX000YYYYYYYb
+ * - YYYYYYY : Applicable comparator instance number (bitmap format: 0000001 for COMP1, 1000000 for COMP7)
+ * - XXXX : COMPxOUTSEL value
+ * @{
+ */
+/* Output Redirection values common to all comparators COMP1...COMP7 */
+#define COMP_OUTPUT_NONE (0x0000007FU) /*!< COMP1, COMP2... or COMP7 output isn't connected to other peripherals */
+#define COMP_OUTPUT_TIM1BKIN (0x0000047FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input (BKIN) */
+#define COMP_OUTPUT_TIM1BKIN2 (0x0000087FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input 2 (BKIN2) */
+#define COMP_OUTPUT_TIM8BKIN (0x00000C7FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM8 Break Input (BKIN) */
+#define COMP_OUTPUT_TIM8BKIN2 (0x0000107FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM8 Break Input 2 (BKIN2) */
+#define COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2 (0x0000147FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input 2 and TIM8 Break Input 2U */
+/* Output Redirection common to COMP1, COMP2, COMP3 and COMP7 */
+#define COMP_OUTPUT_TIM1OCREFCLR (0x00001847U) /*!< COMP1, COMP2, COMP3 or COMP7 output connected to TIM1 OCREF Clear */
+/* Output Redirection common to COMP1, COMP2 and COMP3 */
+#define COMP_OUTPUT_TIM2OCREFCLR (0x00002407U) /*!< COMP1, COMP2 or COMP3 output connected to TIM2 OCREF Clear */
+/* Output Redirection common to COMP1, COMP2, COMP4 and COMP5 */
+#define COMP_OUTPUT_TIM3OCREFCLR (0x00002C1BU) /*!< COMP1, COMP2, COMP4 or COMP5 output connected to TIM3 OCREF Clear */
+/* Output Redirection common to COMP4, COMP5, COMP6 and COMP7 */
+#define COMP_OUTPUT_TIM8OCREFCLR (0x00001C78U) /*!< COMP4, COMP5, COMP6 or COMP7 output connected to TIM8 OCREF Clear */
+/* Output Redirection common to COMP1 and COMP2 */
+#define COMP_OUTPUT_TIM1IC1 (0x00001C03U) /*!< COMP1 or COMP2 output connected to TIM1 Input Capture 1U */
+#define COMP_OUTPUT_TIM2IC4 (0x00002003U) /*!< COMP1 or COMP2 output connected to TIM2 Input Capture 4U */
+#define COMP_OUTPUT_TIM3IC1 (0x00002803U) /*!< COMP1 or COMP2 output connected to TIM3 Input Capture 1U */
+/* Output Redirection specific to COMP3 */
+#define COMP_OUTPUT_TIM4IC1 (0x00001C04U) /*!< COMP3 output connected to TIM4 Input Capture 1U */
+#define COMP_OUTPUT_TIM3IC2 (0x00002004U) /*!< COMP3 output connected to TIM3 Input Capture 2U */
+#define COMP_OUTPUT_TIM15IC1 (0x00002804U) /*!< COMP3 output connected to TIM15 Input Capture 1U */
+#define COMP_OUTPUT_TIM15BKIN (0x00002C04U) /*!< COMP3 output connected to TIM15 Break Input (BKIN) */
+/* Output Redirection specific to COMP4 */
+#define COMP_OUTPUT_TIM3IC3 (0x00001808U) /*!< COMP4 output connected to TIM3 Input Capture 3U */
+#define COMP_OUTPUT_TIM15IC2 (0x00002008U) /*!< COMP4 output connected to TIM15 Input Capture 2U */
+#define COMP_OUTPUT_TIM4IC2 (0x00002408U) /*!< COMP4 output connected to TIM4 Input Capture 2U */
+#define COMP_OUTPUT_TIM15OCREFCLR (0x00002808U) /*!< COMP4 output connected to TIM15 OCREF Clear */
+/* Output Redirection specific to COMP5 */
+#define COMP_OUTPUT_TIM2IC1 (0x00001810U) /*!< COMP5 output connected to TIM2 Input Capture 1U */
+#define COMP_OUTPUT_TIM17IC1 (0x00002010U) /*!< COMP5 output connected to TIM17 Input Capture 1U */
+#define COMP_OUTPUT_TIM4IC3 (0x00002410U) /*!< COMP5 output connected to TIM4 Input Capture 3U */
+#define COMP_OUTPUT_TIM16BKIN (0x00002810U) /*!< COMP5 output connected to TIM16 Break Input (BKIN) */
+/* Output Redirection specific to COMP6 */
+#define COMP_OUTPUT_TIM2IC2 (0x00001820U) /*!< COMP6 output connected to TIM2 Input Capture 2U */
+#define COMP_OUTPUT_COMP6_TIM2OCREFCLR (0x00002020U) /*!< COMP6 output connected to TIM2 OCREF Clear */
+#define COMP_OUTPUT_TIM16OCREFCLR (0x00002420U) /*!< COMP6 output connected to TIM16 OCREF Clear */
+#define COMP_OUTPUT_TIM16IC1 (0x00002820U) /*!< COMP6 output connected to TIM16 Input Capture 1U */
+#define COMP_OUTPUT_TIM4IC4 (0x00002C20U) /*!< COMP6 output connected to TIM4 Input Capture 4U */
+/* Output Redirection specific to COMP7 */
+#define COMP_OUTPUT_TIM2IC3 (0x00002040U) /*!< COMP7 output connected to TIM2 Input Capture 3U */
+#define COMP_OUTPUT_TIM1IC2 (0x00002440U) /*!< COMP7 output connected to TIM1 Input Capture 2U */
+#define COMP_OUTPUT_TIM17OCREFCLR (0x00002840U) /*!< COMP7 output connected to TIM17 OCREF Clear */
+#define COMP_OUTPUT_TIM17BKIN (0x00002C40U) /*!< COMP7 output connected to TIM17 Break Input (BKIN) */
+/**
+ * @}
+ */
+#elif defined(STM32F303xE) || defined(STM32F398xx)
+/** @defgroup COMPEx_Output COMP Extended Output (STM32F303xE/STM32F398xx Product devices)
+ * Elements value convention on 16 LSB: 00XXXX000YYYYYYYb
+ * - YYYYYYY : Applicable comparator instance number (bitmap format: 0000001 for COMP1, 1000000 for COMP7)
+ * - XXXX : COMPxOUTSEL value
+ * @{
+ */
+/* Output Redirection values common to all comparators COMP1...COMP7 */
+#define COMP_OUTPUT_NONE (0x0000007FU) /*!< COMP1, COMP2... or COMP7 output isn't connected to other peripherals */
+#define COMP_OUTPUT_TIM1BKIN (0x0000047FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input (BKIN) */
+#define COMP_OUTPUT_TIM1BKIN2 (0x0000087FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input 2 (BKIN2) */
+#define COMP_OUTPUT_TIM8BKIN (0x00000C7FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM8 Break Input (BKIN) */
+#define COMP_OUTPUT_TIM8BKIN2 (0x0000107FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM8 Break Input 2 (BKIN2) */
+#define COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2 (0x0000147FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input 2 and TIM8 Break Input 2U */
+#define COMP_OUTPUT_TIM20BKIN (0x0000307FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM20 Break Input (BKIN) */
+#define COMP_OUTPUT_TIM20BKIN2 (0x0000347FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM20 Break Input 2 (BKIN2) */
+#define COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2_TIM20BKIN2 (0x0000387FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input 2U, TIM8 Break Input 2 and TIM20 Break Input 2 */
+/* Output Redirection common to COMP1, COMP2, COMP3 and COMP7 */
+#define COMP_OUTPUT_TIM1OCREFCLR (0x00001847U) /*!< COMP1, COMP2, COMP3 or COMP7 output connected to TIM1 OCREF Clear */
+/* Output Redirection common to COMP1, COMP2 and COMP3 */
+#define COMP_OUTPUT_TIM2OCREFCLR (0x00002407U) /*!< COMP1, COMP2 or COMP3 output connected to TIM2 OCREF Clear */
+/* Output Redirection common to COMP1, COMP2, COMP4 and COMP5 */
+#define COMP_OUTPUT_TIM3OCREFCLR (0x00002C1BU) /*!< COMP1, COMP2, COMP4 or COMP5 output connected to TIM3 OCREF Clear */
+/* Output Redirection common to COMP4, COMP5, COMP6 and COMP7 */
+#define COMP_OUTPUT_TIM8OCREFCLR (0x00001C78U) /*!< COMP4, COMP5, COMP6 or COMP7 output connected to TIM8 OCREF Clear */
+/* Output Redirection common to COMP1 and COMP2 */
+#define COMP_OUTPUT_TIM1IC1 (0x00001C03U) /*!< COMP1 or COMP2 output connected to TIM1 Input Capture 1U */
+#define COMP_OUTPUT_TIM2IC4 (0x00002003U) /*!< COMP1 or COMP2 output connected to TIM2 Input Capture 4U */
+#define COMP_OUTPUT_TIM3IC1 (0x00002803U) /*!< COMP1 or COMP2 output connected to TIM3 Input Capture 1U */
+/* Output Redirection specific to COMP2 */
+#define COMP_OUTPUT_TIM20OCREFCLR (0x00003C04U) /*!< COMP2 output connected to TIM20 OCREF Clear */
+/* Output Redirection specific to COMP3 */
+#define COMP_OUTPUT_TIM4IC1 (0x00001C04U) /*!< COMP3 output connected to TIM4 Input Capture 1U */
+#define COMP_OUTPUT_TIM3IC2 (0x00002004U) /*!< COMP3 output connected to TIM3 Input Capture 2U */
+#define COMP_OUTPUT_TIM15IC1 (0x00002804U) /*!< COMP3 output connected to TIM15 Input Capture 1U */
+#define COMP_OUTPUT_TIM15BKIN (0x00002C04U) /*!< COMP3 output connected to TIM15 Break Input (BKIN) */
+/* Output Redirection specific to COMP4 */
+#define COMP_OUTPUT_TIM3IC3 (0x00001808U) /*!< COMP4 output connected to TIM3 Input Capture 3U */
+#define COMP_OUTPUT_TIM15IC2 (0x00002008U) /*!< COMP4 output connected to TIM15 Input Capture 2U */
+#define COMP_OUTPUT_TIM4IC2 (0x00002408U) /*!< COMP4 output connected to TIM4 Input Capture 2U */
+#define COMP_OUTPUT_TIM15OCREFCLR (0x00002808U) /*!< COMP4 output connected to TIM15 OCREF Clear */
+/* Output Redirection specific to COMP5 */
+#define COMP_OUTPUT_TIM2IC1 (0x00001810U) /*!< COMP5 output connected to TIM2 Input Capture 1U */
+#define COMP_OUTPUT_TIM17IC1 (0x00002010U) /*!< COMP5 output connected to TIM17 Input Capture 1U */
+#define COMP_OUTPUT_TIM4IC3 (0x00002410U) /*!< COMP5 output connected to TIM4 Input Capture 3U */
+#define COMP_OUTPUT_TIM16BKIN (0x00002810U) /*!< COMP5 output connected to TIM16 Break Input (BKIN) */
+/* Output Redirection specific to COMP6 */
+#define COMP_OUTPUT_TIM2IC2 (0x00001820U) /*!< COMP6 output connected to TIM2 Input Capture 2U */
+#define COMP_OUTPUT_COMP6_TIM2OCREFCLR (0x00002020U) /*!< COMP6 output connected to TIM2 OCREF Clear */
+#define COMP_OUTPUT_TIM16OCREFCLR (0x00002420U) /*!< COMP6 output connected to TIM16 OCREF Clear */
+#define COMP_OUTPUT_TIM16IC1 (0x00002820U) /*!< COMP6 output connected to TIM16 Input Capture 1U */
+#define COMP_OUTPUT_TIM4IC4 (0x00002C20U) /*!< COMP6 output connected to TIM4 Input Capture 4U */
+/* Output Redirection specific to COMP7 */
+#define COMP_OUTPUT_TIM2IC3 (0x00002040U) /*!< COMP7 output connected to TIM2 Input Capture 3U */
+#define COMP_OUTPUT_TIM1IC2 (0x00002440U) /*!< COMP7 output connected to TIM1 Input Capture 2U */
+#define COMP_OUTPUT_TIM17OCREFCLR (0x00002840U) /*!< COMP7 output connected to TIM17 OCREF Clear */
+#define COMP_OUTPUT_TIM17BKIN (0x00002C40U) /*!< COMP7 output connected to TIM17 Break Input (BKIN) */
+/**
+ * @}
+ */
+#elif defined(STM32F373xC) || defined(STM32F378xx)
+/** @defgroup COMPEx_Output COMP Extended Output (STM32F373xC/STM32F378xx Product devices)
+ * Elements value convention: 00000XXX000000YYb
+ * - YY : Applicable comparator instance number (bitmap format: 01 for COMP1, 10 for COMP2)
+ * - XXX : COMPxOUTSEL value
+ * @{
+ */
+/* Output Redirection values common to all comparators COMP1 and COMP2 */
+#define COMP_OUTPUT_NONE (0x0003U) /*!< COMP1 or COMP2 output isn't connected to other peripherals */
+#define COMP_OUTPUT_TIM2IC4 (0x0403U) /*!< COMP1 or COMP2 output connected to TIM2 Input Capture 4U */
+#define COMP_OUTPUT_TIM2OCREFCLR (0x0503U) /*!< COMP1 or COMP2 output connected to TIM2 OCREF Clear */
+/* Output Redirection specific to COMP1 */
+#define COMP_OUTPUT_TIM15BKIN (0x0101U) /*!< COMP1 output connected to TIM15 Break Input */
+#define COMP_OUTPUT_COMP1_TIM3IC1 (0x0201U) /*!< COMP1 output connected to TIM3 Input Capture 1U */
+#define COMP_OUTPUT_COMP1_TIM3OCREFCLR (0x0301U) /*!< COMP1 output connected to TIM3 OCREF Clear */
+#define COMP_OUTPUT_TIM5IC4 (0x0601U) /*!< COMP1 output connected to TIM5 Input Capture 4U */
+#define COMP_OUTPUT_TIM5OCREFCLR (0x0701U) /*!< COMP1 output connected to TIM5 OCREF Clear */
+/* Output Redirection specific to COMP2 */
+#define COMP_OUTPUT_TIM16BKIN (0x0102U) /*!< COMP2 output connected to TIM16 Break Input */
+#define COMP_OUTPUT_TIM4IC1 (0x0202U) /*!< COMP2 output connected to TIM4 Input Capture 1U */
+#define COMP_OUTPUT_TIM4OCREFCLR (0x0302U) /*!< COMP2 output connected to TIM4 OCREF Clear */
+#define COMP_OUTPUT_COMP2_TIM3IC1 (0x0602U) /*!< COMP2 output connected to TIM3 Input Capture 1U */
+#define COMP_OUTPUT_COMP2_TIM3OCREFCLR (0x0702U) /*!< COMP2 output connected to TIM3 OCREF Clear */
+/**
+ * @}
+ */
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+/** @defgroup COMPEx_WindowMode COMP Extended WindowMode (STM32F302xC/STM32F303xC/STM32F358xx Product devices)
+ * @{
+ */
+#define COMP_WINDOWMODE_DISABLE (0x00000000U) /*!< Window mode disabled */
+#define COMP_WINDOWMODE_ENABLE COMP_CSR_COMPxWNDWEN /*!< Window mode enabled: non inverting input of comparator X (x=2U,4,6U)
+ is connected to the non inverting input of comparator X-1U */
+/**
+ * @}
+ */
+#elif defined(STM32F373xC) || defined(STM32F378xx)
+/** @defgroup COMPEx_WindowMode COMP Extended WindowMode (STM32F373xC/STM32F378xx Product devices)
+ * @{
+ */
+#define COMP_WINDOWMODE_DISABLE (0x00000000U) /*!< Window mode disabled */
+#define COMP_WINDOWMODE_ENABLE ((uint32_t)COMP_CSR_COMPxWNDWEN) /*!< Window mode enabled: non inverting input of comparator 2
+ is connected to the non inverting input of comparator 1 (PA1) */
+/**
+ * @}
+ */
+#else
+/** @defgroup COMPEx_WindowMode COMP Extended WindowMode (Other Product devices)
+ * @{
+ */
+#define COMP_WINDOWMODE_DISABLE (0x00000000U) /*!< Window mode disabled (not available) */
+/**
+ * @}
+ */
+#endif /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+/** @defgroup COMPEx_Mode COMP Extended Mode
+ * @{
+ */
+#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+
+/* Please refer to the electrical characteristics in the device datasheet for
+ the power consumption values */
+#define COMP_MODE_HIGHSPEED (0x00000000U) /*!< High Speed */
+#define COMP_MODE_MEDIUMSPEED COMP_CSR_COMPxMODE_0 /*!< Medium Speed */
+#define COMP_MODE_LOWPOWER COMP_CSR_COMPxMODE_1 /*!< Low power mode */
+#define COMP_MODE_ULTRALOWPOWER COMP_CSR_COMPxMODE /*!< Ultra-low power mode */
+
+#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F373xC || STM32F378xx */
+/**
+ * @}
+ */
+
+/** @defgroup COMPEx_Hysteresis COMP Extended Hysteresis
+ * @{
+ */
+#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+
+#define COMP_HYSTERESIS_NONE (0x00000000U) /*!< No hysteresis */
+#define COMP_HYSTERESIS_LOW COMP_CSR_COMPxHYST_0 /*!< Hysteresis level low */
+#define COMP_HYSTERESIS_MEDIUM COMP_CSR_COMPxHYST_1 /*!< Hysteresis level medium */
+#define COMP_HYSTERESIS_HIGH COMP_CSR_COMPxHYST /*!< Hysteresis level high */
+
+#else
+
+#define COMP_HYSTERESIS_NONE (0x00000000U) /*!< No hysteresis */
+
+#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F373xC || STM32F378xx */
+/**
+ * @}
+ */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+/** @defgroup COMPEx_BlankingSrce COMP Extended Blanking Source (STM32F301x8/STM32F302x8/STM32F303x8/STM32F334x8/STM32F318xx/STM32F328xx Product devices)
+ * @{
+ */
+/* No blanking source can be selected for all comparators */
+#define COMP_BLANKINGSRCE_NONE (0x00000000U) /*!< No blanking source */
+/* Blanking source for COMP2 */
+#define COMP_BLANKINGSRCE_TIM1OC5 COMP_CSR_COMPxBLANKING_0 /*!< TIM1 OC5 selected as blanking source for COMP2 */
+#define COMP_BLANKINGSRCE_TIM2OC3 COMP_CSR_COMPxBLANKING_1 /*!< TIM2 OC3 selected as blanking source for COMP2 */
+#define COMP_BLANKINGSRCE_TIM3OC3 (COMP_CSR_COMPxBLANKING_0|COMP_CSR_COMPxBLANKING_1) /*!< TIM3 OC3 selected as blanking source for COMP2 */
+/* Blanking source for COMP4 */
+#define COMP_BLANKINGSRCE_TIM3OC4 COMP_CSR_COMPxBLANKING_0 /*!< TIM3 OC4 selected as blanking source for COMP4 */
+#define COMP_BLANKINGSRCE_TIM15OC1 (COMP_CSR_COMPxBLANKING_0|COMP_CSR_COMPxBLANKING_1) /*!< TIM15 OC1 selected as blanking source for COMP4 */
+/* Blanking source for COMP6 */
+#define COMP_BLANKINGSRCE_TIM2OC4 (COMP_CSR_COMPxBLANKING_0|COMP_CSR_COMPxBLANKING_1) /*!< TIM2 OC4 selected as blanking source for COMP6 */
+#define COMP_BLANKINGSRCE_TIM15OC2 COMP_CSR_COMPxBLANKING_2 /*!< TIM15 OC2 selected as blanking source for COMP6 */
+/**
+ * @}
+ */
+
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F302xE) ||\
+ defined(STM32F302xC)
+/** @defgroup COMPEx_BlankingSrce COMP Extended Blanking Source (STM32F302xE/STM32F302xC Product devices)
+ * @{
+ */
+/* No blanking source can be selected for all comparators */
+#define COMP_BLANKINGSRCE_NONE (0x00000000U) /*!< No blanking source */
+/* Blanking source common for COMP1 and COMP2 */
+#define COMP_BLANKINGSRCE_TIM1OC5 COMP_CSR_COMPxBLANKING_0 /*!< TIM1 OC5 selected as blanking source for COMP1 and COMP2 */
+/* Blanking source common for COMP1 and COMP2 */
+#define COMP_BLANKINGSRCE_TIM2OC3 COMP_CSR_COMPxBLANKING_1 /*!< TIM2 OC3 selected as blanking source for COMP1 and COMP2 */
+/* Blanking source common for COMP1 and COMP2 */
+#define COMP_BLANKINGSRCE_TIM3OC3 (COMP_CSR_COMPxBLANKING_0|COMP_CSR_COMPxBLANKING_1) /*!< TIM3 OC3 selected as blanking source for COMP1 and COMP2 */
+/* Blanking source for COMP4 */
+#define COMP_BLANKINGSRCE_TIM3OC4 COMP_CSR_COMPxBLANKING_0 /*!< TIM3 OC4 selected as blanking source for COMP4 */
+#define COMP_BLANKINGSRCE_TIM15OC1 (COMP_CSR_COMPxBLANKING_0|COMP_CSR_COMPxBLANKING_1) /*!< TIM15 OC1 selected as blanking source for COMP4 */
+/* Blanking source for COMP6 */
+#define COMP_BLANKINGSRCE_TIM2OC4 (COMP_CSR_COMPxBLANKING_0|COMP_CSR_COMPxBLANKING_1) /*!< TIM2 OC4 selected as blanking source for COMP6 */
+#define COMP_BLANKINGSRCE_TIM15OC2 COMP_CSR_COMPxBLANKING_2 /*!< TIM15 OC2 selected as blanking source for COMP6 */
+/**
+ * @}
+ */
+
+#endif /* STM32F302xE || */
+ /* STM32F302xC */
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+/** @defgroup COMPEx_BlankingSrce COMP Extended Blanking Source (STM32F303xE/STM32F398xx/STM32F303xC/STM32F358xx Product devices)
+ * @{
+ */
+/* No blanking source can be selected for all comparators */
+#define COMP_BLANKINGSRCE_NONE (0x00000000U) /*!< No blanking source */
+/* Blanking source common for COMP1, COMP2, COMP3 and COMP7 */
+#define COMP_BLANKINGSRCE_TIM1OC5 COMP_CSR_COMPxBLANKING_0 /*!< TIM1 OC5 selected as blanking source for COMP1, COMP2, COMP3 and COMP7 */
+/* Blanking source common for COMP1 and COMP2 */
+#define COMP_BLANKINGSRCE_TIM2OC3 COMP_CSR_COMPxBLANKING_1 /*!< TIM2 OC5 selected as blanking source for COMP1 and COMP2 */
+/* Blanking source common for COMP1, COMP2 and COMP5 */
+#define COMP_BLANKINGSRCE_TIM3OC3 (COMP_CSR_COMPxBLANKING_0|COMP_CSR_COMPxBLANKING_1) /*!< TIM2 OC3 selected as blanking source for COMP1, COMP2 and COMP5 */
+/* Blanking source common for COMP3 and COMP6 */
+#define COMP_BLANKINGSRCE_TIM2OC4 (COMP_CSR_COMPxBLANKING_0|COMP_CSR_COMPxBLANKING_1) /*!< TIM2 OC4 selected as blanking source for COMP3 and COMP6 */
+/* Blanking source common for COMP4, COMP5, COMP6 and COMP7 */
+#define COMP_BLANKINGSRCE_TIM8OC5 COMP_CSR_COMPxBLANKING_1 /*!< TIM8 OC5 selected as blanking source for COMP4, COMP5, COMP6 and COMP7 */
+/* Blanking source for COMP4 */
+#define COMP_BLANKINGSRCE_TIM3OC4 COMP_CSR_COMPxBLANKING_0 /*!< TIM3 OC4 selected as blanking source for COMP4 */
+#define COMP_BLANKINGSRCE_TIM15OC1 (COMP_CSR_COMPxBLANKING_0|COMP_CSR_COMPxBLANKING_1) /*!< TIM15 OC1 selected as blanking source for COMP4 */
+/* Blanking source common for COMP6 and COMP7 */
+#define COMP_BLANKINGSRCE_TIM15OC2 COMP_CSR_COMPxBLANKING_2 /*!< TIM15 OC2 selected as blanking source for COMP6 and COMP7 */
+/**
+ * @}
+ */
+
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/** @defgroup COMPEx_BlankingSrce COMP Extended Blanking Source (STM32F373xC/STM32F378xx Product devices)
+ * @{
+ */
+/* No blanking source can be selected for all comparators */
+#define COMP_BLANKINGSRCE_NONE (0x00000000U) /*!< No blanking source */
+/**
+ * @}
+ */
+
+#endif /* STM32F373xC || STM32F378xx */
+
+/** @defgroup COMP_Flag COMP Flag
+ * @{
+ */
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK /*!< Lock flag */
+#else
+#define COMP_FLAG_LOCK COMP_CSR_LOCK /*!< Lock flag */
+#endif /* STM32F373xC || STM32F378xx */
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup COMPEx_Exported_Macros COMP Extended Exported Macros
+ * @{
+ */
+#if defined(STM32F373xC) || defined(STM32F378xx)
+
+/**
+ * @brief Enable the specified comparator.
+ * @param __HANDLE__ COMP handle.
+ * @retval None
+ */
+#define __HAL_COMP_ENABLE(__HANDLE__) \
+ do { \
+ uint32_t regshift = COMP_CSR_COMP1_SHIFT; \
+ \
+ if((__HANDLE__)->Instance == COMP2) \
+ { \
+ regshift = COMP_CSR_COMP2_SHIFT; \
+ } \
+ SET_BIT(COMP->CSR, (uint32_t)COMP_CSR_COMPxEN << regshift); \
+ } while(0U)
+
+/**
+ * @brief Disable the specified comparator.
+ * @param __HANDLE__ COMP handle.
+ * @retval None
+ */
+#define __HAL_COMP_DISABLE(__HANDLE__) \
+ do { \
+ uint32_t regshift = COMP_CSR_COMP1_SHIFT; \
+ \
+ if((__HANDLE__)->Instance == COMP2) \
+ { \
+ regshift = COMP_CSR_COMP2_SHIFT; \
+ } \
+ CLEAR_BIT(COMP->CSR, (uint32_t)COMP_CSR_COMPxEN << regshift); \
+ } while(0U)
+
+/**
+ * @brief Lock a comparator instance
+ * @param __HANDLE__ COMP handle
+ * @retval None.
+ */
+#define __HAL_COMP_LOCK(__HANDLE__) \
+ do { \
+ uint32_t regshift = COMP_CSR_COMP1_SHIFT; \
+ \
+ if((__HANDLE__)->Instance == COMP2) \
+ { \
+ regshift = COMP_CSR_COMP2_SHIFT; \
+ } \
+ SET_BIT(COMP->CSR, (uint32_t)COMP_CSR_COMPxLOCK << regshift); \
+ } while(0U)
+
+/** @brief Check whether the specified COMP flag is set or not.
+ * @param __HANDLE__ COMP Handle.
+ * @param __FLAG__ flag to check.
+ * This parameter can be one of the following values:
+ * @arg @ref COMP_FLAG_LOCK lock flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) \
+ (((__HANDLE__)->Instance == COMP1) ? (((__HANDLE__)->Instance->CSR & (__FLAG__)) == (__FLAG__)) \
+ (((__HANDLE__)->Instance->CSR & (uint32_t)((__FLAG__) << COMP_CSR_COMP2_SHIFT) == (__FLAG__))))
+
+#else
+
+/**
+ * @brief Enable the specified comparator.
+ * @param __HANDLE__ COMP handle.
+ * @retval None
+ */
+#define __HAL_COMP_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_COMPxEN)
+
+/**
+ * @brief Disable the specified comparator.
+ * @param __HANDLE__ COMP handle.
+ * @retval None
+ */
+#define __HAL_COMP_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_COMPxEN)
+
+/**
+ * @brief Lock a comparator instance
+ * @param __HANDLE__ COMP handle
+ * @retval None.
+ */
+#define __HAL_COMP_LOCK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_COMPxLOCK)
+
+/** @brief Check whether the specified COMP flag is set or not.
+ * @param __HANDLE__ COMP Handle.
+ * @param __FLAG__ flag to check.
+ * This parameter can be one of the following values:
+ * @arg @ref COMP_FLAG_LOCK lock flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->CSR & (__FLAG__)) == (__FLAG__))
+
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+
+/**
+ * @brief Enable the COMP1 EXTI line rising edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP1)
+
+/**
+ * @brief Disable the COMP1 EXTI line rising edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP1)
+
+/**
+ * @brief Enable the COMP1 EXTI line falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP1)
+
+/**
+ * @brief Disable the COMP1 EXTI line falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP1)
+
+/**
+ * @brief Enable the COMP1 EXTI line rising & falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
+ __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE(); \
+ __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE(); \
+ } while(0U)
+
+/**
+ * @brief Disable the COMP1 EXTI line rising & falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
+ __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE(); \
+ } while(0U)
+
+/**
+ * @brief Enable the COMP1 EXTI line in interrupt mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP1)
+
+/**
+ * @brief Disable the COMP1 EXTI line in interrupt mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP1)
+
+/**
+ * @brief Generate a software interrupt on the COMP1 EXTI line.
+ * @retval None
+ */
+#define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, COMP_EXTI_LINE_COMP1)
+
+/**
+ * @brief Enable the COMP1 EXTI line in event mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP1)
+
+/**
+ * @brief Disable the COMP1 EXTI line in event mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP1)
+
+/**
+ * @brief Check whether the COMP1 EXTI line flag is set or not.
+ * @retval RESET or SET
+ */
+#define __HAL_COMP_COMP1_EXTI_GET_FLAG() READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP1)
+
+/**
+ * @brief Clear the COMP1 EXTI flag.
+ * @retval None
+ */
+#define __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP1)
+
+#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F373xC || STM32F378xx */
+
+/**
+ * @brief Enable the COMP2 EXTI line rising edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP2)
+
+/**
+ * @brief Disable the COMP2 EXTI line rising edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP2)
+
+/**
+ * @brief Enable the COMP2 EXTI line falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP2)
+
+/**
+ * @brief Disable the COMP2 EXTI line falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP2)
+
+/**
+ * @brief Enable the COMP2 EXTI line rising & falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
+ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE(); \
+ __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE(); \
+ } while(0U)
+
+/**
+ * @brief Disable the COMP2 EXTI line rising & falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
+ __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE(); \
+ } while(0U)
+
+/**
+ * @brief Enable the COMP2 EXTI line in interrupt mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP2)
+
+/**
+ * @brief Disable the COMP2 EXTI line in interrupt mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP2)
+
+/**
+ * @brief Generate a software interrupt on the COMP2 EXTI line.
+ * @retval None
+ */
+#define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, COMP_EXTI_LINE_COMP2)
+
+/**
+ * @brief Enable the COMP2 EXTI line in event mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP2)
+
+/**
+ * @brief Disable the COMP2 EXTI line in event mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP2)
+
+/**
+ * @brief Check whether the COMP2 EXTI line flag is set or not.
+ * @retval RESET or SET
+ */
+#define __HAL_COMP_COMP2_EXTI_GET_FLAG() READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP2)
+
+/**
+ * @brief Clear the COMP2 EXTI flag.
+ * @retval None
+ */
+#define __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP2)
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+
+/**
+ * @brief Enable the COMP3 EXTI line rising edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP3)
+
+/**
+ * @brief Disable the COMP3 EXTI line rising edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP3)
+
+/**
+ * @brief Enable the COMP3 EXTI line falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP3)
+
+/**
+ * @brief Disable the COMP3 EXTI line falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP3)
+
+/**
+ * @brief Enable the COMP3 EXTI line rising & falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP3_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
+ __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE(); \
+ __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE(); \
+ } while(0U)
+
+/**
+ * @brief Disable the COMP3 EXTI line rising & falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP3_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
+ __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE(); \
+ } while(0U)
+
+/**
+ * @brief Enable the COMP3 EXTI line in interrupt mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP3_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP3)
+
+/**
+ * @brief Disable the COMP3 EXTI line in interrupt mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP3_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP3)
+
+/**
+ * @brief Generate a software interrupt on the COMP3 EXTI line.
+ * @retval None
+ */
+#define __HAL_COMP_COMP3_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, COMP_EXTI_LINE_COMP3)
+
+/**
+ * @brief Enable the COMP3 EXTI line in event mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP3_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP3)
+
+/**
+ * @brief Disable the COMP3 EXTI line in event mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP3_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP3)
+
+/**
+ * @brief Check whether the COMP3 EXTI line flag is set or not.
+ * @retval RESET or SET
+ */
+#define __HAL_COMP_COMP3_EXTI_GET_FLAG() READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP3)
+
+/**
+ * @brief Clear the COMP3 EXTI flag.
+ * @retval None
+ */
+#define __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP3)
+
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+
+/**
+ * @brief Enable the COMP4 EXTI line rising edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP4)
+
+/**
+ * @brief Disable the COMP4 EXTI line rising edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP4)
+
+/**
+ * @brief Enable the COMP4 EXTI line falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP4)
+
+/**
+ * @brief Disable the COMP4 EXTI line falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP4)
+
+/**
+ * @brief Enable the COMP4 EXTI line rising & falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP4_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
+ __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE(); \
+ __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE(); \
+ } while(0U)
+
+/**
+ * @brief Disable the COMP4 EXTI line rising & falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP4_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
+ __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE(); \
+ } while(0U)
+
+/**
+ * @brief Enable the COMP4 EXTI line in interrupt mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP4_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP4)
+
+/**
+ * @brief Disable the COMP4 EXTI line in interrupt mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP4_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP4)
+
+/**
+ * @brief Generate a software interrupt on the COMP4 EXTI line.
+ * @retval None
+ */
+#define __HAL_COMP_COMP4_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, COMP_EXTI_LINE_COMP4)
+
+/**
+ * @brief Enable the COMP4 EXTI line in event mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP4_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP4)
+
+/**
+ * @brief Disable the COMP4 EXTI line in event mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP4_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP4)
+
+/**
+ * @brief Check whether the COMP4 EXTI line flag is set or not.
+ * @retval RESET or SET
+ */
+#define __HAL_COMP_COMP4_EXTI_GET_FLAG() READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP4)
+
+/**
+ * @brief Clear the COMP4 EXTI flag.
+ * @retval None
+ */
+#define __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP4)
+
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+
+/**
+ * @brief Enable the COMP5 EXTI line rising edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP5)
+
+/**
+ * @brief Disable the COMP5 EXTI line rising edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP5)
+
+/**
+ * @brief Enable the COMP5 EXTI line falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP5)
+
+/**
+ * @brief Disable the COMP5 EXTI line falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP5)
+
+/**
+ * @brief Enable the COMP5 EXTI line rising & falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP5_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
+ __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE(); \
+ __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE(); \
+ } while(0U)
+
+/**
+ * @brief Disable the COMP5 EXTI line rising & falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP5_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
+ __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE(); \
+ } while(0U)
+
+/**
+ * @brief Enable the COMP5 EXTI line in interrupt mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP5_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP5)
+
+/**
+ * @brief Disable the COMP5 EXTI line in interrupt mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP5_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP5)
+
+/**
+ * @brief Generate a software interrupt on the COMP5 EXTI line.
+ * @retval None
+ */
+#define __HAL_COMP_COMP5_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, COMP_EXTI_LINE_COMP5)
+
+/**
+ * @brief Enable the COMP5 EXTI line in event mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP5_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP5)
+
+/**
+ * @brief Disable the COMP5 EXTI line in event mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP5_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP5)
+
+/**
+ * @brief Check whether the COMP5 EXTI line flag is set or not.
+ * @retval RESET or SET
+ */
+#define __HAL_COMP_COMP5_EXTI_GET_FLAG() READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP5)
+
+/**
+ * @brief Clear the COMP5 EXTI flag.
+ * @retval None
+ */
+#define __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP5)
+
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+
+/**
+ * @brief Enable the COMP6 EXTI line rising edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, COMP_EXTI_LINE_COMP6)
+
+/**
+ * @brief Disable the COMP6 EXTI line rising edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, COMP_EXTI_LINE_COMP6)
+
+/**
+ * @brief Enable the COMP6 EXTI line falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, COMP_EXTI_LINE_COMP6)
+
+/**
+ * @brief Disable the COMP6 EXTI line falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, COMP_EXTI_LINE_COMP6)
+
+/**
+ * @brief Enable the COMP6 EXTI line rising & falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP6_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
+ __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE(); \
+ __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE(); \
+ } while(0U)
+
+/**
+ * @brief Disable the COMP6 EXTI line rising & falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP6_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
+ __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE(); \
+ } while(0U)
+
+/**
+ * @brief Enable the COMP6 EXTI line in interrupt mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP6_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, COMP_EXTI_LINE_COMP6)
+
+/**
+ * @brief Disable the COMP6 EXTI line in interrupt mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP6_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, COMP_EXTI_LINE_COMP6)
+
+/**
+ * @brief Generate a software interrupt on the COMP6 EXTI line.
+ * @retval None
+ */
+#define __HAL_COMP_COMP6_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, COMP_EXTI_LINE_COMP6)
+
+/**
+ * @brief Enable the COMP6 EXTI line in event mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP6_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, COMP_EXTI_LINE_COMP6)
+
+/**
+ * @brief Disable the COMP6 EXTI line in event mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP6_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, COMP_EXTI_LINE_COMP6)
+
+/**
+ * @brief Check whether the COMP6 EXTI line flag is set or not.
+ * @retval RESET or SET
+ */
+#define __HAL_COMP_COMP6_EXTI_GET_FLAG() READ_BIT(EXTI->PR2, COMP_EXTI_LINE_COMP6)
+
+/**
+ * @brief Clear the COMP6 EXTI flag.
+ * @retval None
+ */
+#define __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, COMP_EXTI_LINE_COMP6)
+
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+/**
+ * @brief Enable the COMP7 EXTI line rising edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, COMP_EXTI_LINE_COMP7)
+
+/**
+ * @brief Disable the COMP7 EXTI line rising edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, COMP_EXTI_LINE_COMP7)
+
+/**
+ * @brief Enable the COMP7 EXTI line falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, COMP_EXTI_LINE_COMP7)
+
+/**
+ * @brief Disable the COMP7 EXTI line falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, COMP_EXTI_LINE_COMP7)
+
+/**
+ * @brief Enable the COMP7 EXTI line rising & falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP7_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
+ __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE(); \
+ __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE(); \
+ } while(0U)
+
+/**
+ * @brief Disable the COMP7 EXTI line rising & falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP7_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
+ __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE(); \
+ } while(0U)
+
+/**
+ * @brief Enable the COMP7 EXTI line in interrupt mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP7_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, COMP_EXTI_LINE_COMP7)
+
+/**
+ * @brief Disable the COMP7 EXTI line in interrupt mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP7_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, COMP_EXTI_LINE_COMP7)
+
+/**
+ * @brief Generate a software interrupt on the COMP7 EXTI line.
+ * @retval None
+ */
+#define __HAL_COMP_COMP7_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, COMP_EXTI_LINE_COMP7)
+
+/**
+ * @brief Enable the COMP7 EXTI line in event mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP7_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, COMP_EXTI_LINE_COMP7)
+
+/**
+ * @brief Disable the COMP7 EXTI line in event mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP7_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, COMP_EXTI_LINE_COMP7)
+
+/**
+ * @brief Check whether the COMP7 EXTI line flag is set or not.
+ * @retval RESET or SET
+ */
+#define __HAL_COMP_COMP7_EXTI_GET_FLAG() READ_BIT(EXTI->PR2, COMP_EXTI_LINE_COMP7)
+
+/**
+ * @brief Clear the COMP7 EXTI flag.
+ * @retval None
+ */
+#define __HAL_COMP_COMP7_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, COMP_EXTI_LINE_COMP7)
+
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup COMPEx_Private_Constants COMP Extended Private Constants
+ * @{
+ */
+/** @defgroup COMPEx_ExtiLineEvent COMP Extended EXTI lines
+ * @{
+ */
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+
+#define COMP_EXTI_LINE_COMP2 EXTI_IMR_MR22 /*!< External interrupt line 22 connected to COMP2 */
+#define COMP_EXTI_LINE_COMP4 EXTI_IMR_MR30 /*!< External interrupt line 30 connected to COMP4 */
+#define COMP_EXTI_LINE_COMP6 EXTI_IMR2_MR32 /*!< External interrupt line 32 connected to COMP6 */
+
+#define COMP_EXTI_LINE_REG2_MASK EXTI_IMR2_MR32 /*!< Mask for External interrupt line control in register xxx2 */
+
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC)
+
+#define COMP_EXTI_LINE_COMP1 EXTI_IMR_MR21 /*!< External interrupt line 21 connected to COMP1 */
+#define COMP_EXTI_LINE_COMP2 EXTI_IMR_MR22 /*!< External interrupt line 22 connected to COMP2 */
+#define COMP_EXTI_LINE_COMP4 EXTI_IMR_MR30 /*!< External interrupt line 30 connected to COMP4 */
+#define COMP_EXTI_LINE_COMP6 EXTI_IMR2_MR32 /*!< External interrupt line 32 connected to COMP6 */
+
+#define COMP_EXTI_LINE_REG2_MASK EXTI_IMR2_MR32 /*!< Mask for External interrupt line control in register xxx2 */
+
+#endif /* STM32F302xE || */
+ /* STM32F302xC */
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+
+#define COMP_EXTI_LINE_COMP1 EXTI_IMR_MR21 /*!< External interrupt line 21 connected to COMP1 */
+#define COMP_EXTI_LINE_COMP2 EXTI_IMR_MR22 /*!< External interrupt line 22 connected to COMP2 */
+#define COMP_EXTI_LINE_COMP3 EXTI_IMR_MR29 /*!< External interrupt line 29 connected to COMP3 */
+#define COMP_EXTI_LINE_COMP4 EXTI_IMR_MR30 /*!< External interrupt line 30 connected to COMP4 */
+#define COMP_EXTI_LINE_COMP5 EXTI_IMR_MR31 /*!< External interrupt line 31 connected to COMP5 */
+#define COMP_EXTI_LINE_COMP6 EXTI_IMR2_MR32 /*!< External interrupt line 32 connected to COMP6 */
+#define COMP_EXTI_LINE_COMP7 EXTI_IMR2_MR33 /*!< External interrupt line 33 connected to COMP7 */
+
+#define COMP_EXTI_LINE_REG2_MASK (EXTI_IMR2_MR33 | EXTI_IMR2_MR32) /*!< Mask for External interrupt line control in register xxx2 */
+
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+
+#define COMP_EXTI_LINE_COMP1 EXTI_IMR_MR21 /*!< External interrupt line 21 connected to COMP1 */
+#define COMP_EXTI_LINE_COMP2 EXTI_IMR_MR22 /*!< External interrupt line 22 connected to COMP2 */
+
+#endif /* STM32F373xC || STM32F378xx */
+
+/**
+ * @}
+ */
+
+/** @defgroup COMPEx_Misc COMP Extended miscellaneous defines
+ * @{
+ */
+
+/* CSR masks redefinition for internal use */
+#define COMP_CSR_COMPxINSEL_MASK COMP_CSR_COMPxINSEL /*!< COMP_CSR_COMPxINSEL Mask */
+#define COMP_CSR_COMPxOUTSEL_MASK COMP_CSR_COMPxOUTSEL /*!< COMP_CSR_COMPxOUTSEL Mask */
+#define COMP_CSR_COMPxPOL_MASK COMP_CSR_COMPxPOL /*!< COMP_CSR_COMPxPOL Mask */
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/* CSR register reset value */
+#define COMP_CSR_RESET_VALUE (0x00000000U)
+#define COMP_CSR_RESET_PARAMETERS_MASK (0x00003FFFU)
+#define COMP_CSR_UPDATE_PARAMETERS_MASK (0x00003FFEU)
+/* CSR COMP1/COMP2 shift */
+#define COMP_CSR_COMP1_SHIFT 0U
+#define COMP_CSR_COMP2_SHIFT 16U
+#else
+/* CSR register reset value */
+#define COMP_CSR_RESET_VALUE (0x00000000U)
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define COMP_CSR_COMPxNONINSEL_MASK (COMP2_CSR_COMP2INPDAC) /*!< COMP_CSR_COMPxNONINSEL mask */
+#define COMP_CSR_COMPxWNDWEN_MASK (0x00000000U) /*!< Mask empty: feature not available */
+#define COMP_CSR_COMPxMODE_MASK (0x00000000U) /*!< Mask empty: feature not available */
+#define COMP_CSR_COMPxHYST_MASK (0x00000000U) /*!< Mask empty: feature not available */
+#define COMP_CSR_COMPxBLANKING_MASK COMP_CSR_COMPxBLANKING /*!< COMP_CSR_COMPxBLANKING mask */
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define COMP_CSR_COMPxNONINSEL_MASK (0x00000000U) /*!< Mask empty: feature not available */
+#define COMP_CSR_COMPxWNDWEN_MASK (0x00000000U) /*!< Mask empty: feature not available */
+#define COMP_CSR_COMPxMODE_MASK (0x00000000U) /*!< Mask empty: feature not available */
+#define COMP_CSR_COMPxHYST_MASK (0x00000000U) /*!< Mask empty: feature not available */
+#define COMP_CSR_COMPxBLANKING_MASK COMP_CSR_COMPxBLANKING /*!< COMP_CSR_COMPxBLANKING mask */
+#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+#define COMP_CSR_COMPxNONINSEL_MASK (COMP_CSR_COMPxNONINSEL | COMP1_CSR_COMP1SW1) /*!< COMP_CSR_COMPxNONINSEL mask */
+#define COMP_CSR_COMPxWNDWEN_MASK COMP_CSR_COMPxWNDWEN /*!< COMP_CSR_COMPxWNDWEN mask */
+#define COMP_CSR_COMPxMODE_MASK COMP_CSR_COMPxMODE /*!< COMP_CSR_COMPxMODE Mask */
+#define COMP_CSR_COMPxHYST_MASK COMP_CSR_COMPxHYST /*!< COMP_CSR_COMPxHYST Mask */
+#define COMP_CSR_COMPxBLANKING_MASK COMP_CSR_COMPxBLANKING /*!< COMP_CSR_COMPxBLANKING mask */
+#endif /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+#define COMP_CSR_COMPxNONINSEL_MASK (COMP1_CSR_COMP1SW1) /*!< COMP_CSR_COMPxNONINSEL mask */
+#define COMP_CSR_COMPxWNDWEN_MASK (0x00000000U) /*!< Mask empty: feature not available */
+#define COMP_CSR_COMPxMODE_MASK (0x00000000U) /*!< Mask empty: feature not available */
+#define COMP_CSR_COMPxHYST_MASK (0x00000000U) /*!< Mask empty: feature not available */
+#define COMP_CSR_COMPxBLANKING_MASK COMP_CSR_COMPxBLANKING /*!< COMP_CSR_COMPxBLANKING mask */
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#define COMP_CSR_COMPxNONINSEL_MASK (COMP_CSR_COMP1SW1) /*!< COMP_CSR_COMPxNONINSEL mask */
+#define COMP_CSR_COMPxWNDWEN_MASK COMP_CSR_COMPxWNDWEN /*!< COMP_CSR_COMPxWNDWEN mask */
+#define COMP_CSR_COMPxMODE_MASK COMP_CSR_COMPxMODE /*!< COMP_CSR_COMPxMODE Mask */
+#define COMP_CSR_COMPxHYST_MASK COMP_CSR_COMPxHYST /*!< COMP_CSR_COMPxHYST Mask */
+#define COMP_CSR_COMPxBLANKING_MASK (0x00000000U) /*!< Mask empty: feature not available */
+#endif /* STM32F373xC || STM32F378xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup COMPEx_Private_Macros COMP Extended Private Macros
+ * @{
+ */
+/** @defgroup COMP_GET_EXTI_LINE COMP Extended Private macro to get the EXTI line associated with a comparator handle
+ * @{
+ */
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+/**
+ * @brief Get the specified EXTI line for a comparator instance
+ * @param __INSTANCE__ specifies the COMP instance.
+ * @retval value of @ref COMPEx_ExtiLineEvent
+ */
+#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP2) ? COMP_EXTI_LINE_COMP2 : \
+ ((__INSTANCE__) == COMP4) ? COMP_EXTI_LINE_COMP4 : \
+ COMP_EXTI_LINE_COMP6)
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC)
+/**
+ * @brief Get the specified EXTI line for a comparator instance
+ * @param __INSTANCE__ specifies the COMP instance.
+ * @retval value of @ref COMPEx_ExtiLineEvent
+ */
+#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 : \
+ ((__INSTANCE__) == COMP2) ? COMP_EXTI_LINE_COMP2 : \
+ ((__INSTANCE__) == COMP4) ? COMP_EXTI_LINE_COMP4 : \
+ COMP_EXTI_LINE_COMP6)
+#endif /* STM32F302xE || */
+ /* STM32F302xC */
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+/**
+ * @brief Get the specified EXTI line for a comparator instance
+ * @param __INSTANCE__ specifies the COMP instance.
+ * @retval value of @ref COMPEx_ExtiLineEvent
+ */
+#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 : \
+ ((__INSTANCE__) == COMP2) ? COMP_EXTI_LINE_COMP2 : \
+ ((__INSTANCE__) == COMP3) ? COMP_EXTI_LINE_COMP3 : \
+ ((__INSTANCE__) == COMP4) ? COMP_EXTI_LINE_COMP4 : \
+ ((__INSTANCE__) == COMP5) ? COMP_EXTI_LINE_COMP5 : \
+ ((__INSTANCE__) == COMP6) ? COMP_EXTI_LINE_COMP6 : \
+ COMP_EXTI_LINE_COMP7)
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Get the specified EXTI line for a comparator instance
+ * @param __INSTANCE__ specifies the COMP instance.
+ * @retval value of @ref COMPEx_ExtiLineEvent
+ */
+#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 : \
+ COMP_EXTI_LINE_COMP2)
+#endif /* STM32F373xC || STM32F378xx */
+
+/**
+ * @}
+ */
+
+/** @defgroup COMPEx_Private_Macros_Misc COMP Extended miscellaneous private macros
+ * @{
+ */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Init a comparator instance
+ * @param __HANDLE__ COMP handle
+ * @note The common output selection is checked versus the COMP instance to set the right output configuration
+ * @retval None.
+ */
+#define COMP_INIT(__HANDLE__) \
+ do { \
+ uint32_t regshift = COMP_CSR_COMP1_SHIFT; \
+ uint32_t compoutput = (__HANDLE__)->Init.Output & COMP_CSR_COMPxOUTSEL_MASK; \
+ \
+ if((__HANDLE__)->Instance == COMP2) \
+ { \
+ regshift = COMP_CSR_COMP2_SHIFT; \
+ } \
+ \
+ MODIFY_REG(COMP->CSR, \
+ (COMP_CSR_COMPxINSEL | COMP_CSR_COMPxNONINSEL_MASK | \
+ COMP_CSR_COMPxOUTSEL | COMP_CSR_COMPxPOL | \
+ COMP_CSR_COMPxHYST | COMP_CSR_COMPxMODE) << regshift, \
+ ((__HANDLE__)->Init.InvertingInput | \
+ (__HANDLE__)->Init.NonInvertingInput | \
+ compoutput | \
+ (__HANDLE__)->Init.OutputPol | \
+ (__HANDLE__)->Init.Hysteresis | \
+ (__HANDLE__)->Init.Mode) << regshift); \
+ \
+ if((__HANDLE__)->Init.WindowMode != COMP_WINDOWMODE_DISABLE) \
+ { \
+ COMP->CSR |= COMP_CSR_WNDWEN; \
+ } \
+ } while(0U)
+
+/**
+ * @brief DeInit a comparator instance
+ * @param __HANDLE__ COMP handle
+ * @retval None.
+ */
+#define COMP_DEINIT(__HANDLE__) \
+ do { \
+ uint32_t regshift = COMP_CSR_COMP1_SHIFT; \
+ \
+ if((__HANDLE__)->Instance == COMP2) \
+ { \
+ regshift = COMP_CSR_COMP2_SHIFT; \
+ } \
+ MODIFY_REG(COMP->CSR, \
+ COMP_CSR_RESET_PARAMETERS_MASK << regshift, \
+ COMP_CSR_RESET_VALUE << regshift); \
+ } while(0U)
+
+
+/**
+ * @brief Enable the Exti Line rising edge trigger.
+ * @param __EXTILINE__ specifies the COMP Exti sources to be enabled.
+ * This parameter can be a value of @ref COMPEx_ExtiLineEvent
+ * @retval None.
+ */
+#define COMP_EXTI_RISING_ENABLE(__EXTILINE__) SET_BIT(EXTI->RTSR, (__EXTILINE__))
+
+/**
+ * @brief Disable the Exti Line rising edge trigger.
+ * @param __EXTILINE__ specifies the COMP Exti sources to be disabled.
+ * This parameter can be a value of @ref COMPEx_ExtiLineEvent
+ * @retval None.
+ */
+#define COMP_EXTI_RISING_DISABLE(__EXTILINE__) CLEAR_BIT(EXTI->RTSR, (__EXTILINE__))
+
+/**
+ * @brief Enable the Exti Line falling edge trigger.
+ * @param __EXTILINE__ specifies the COMP Exti sources to be enabled.
+ * This parameter can be a value of @ref COMPEx_ExtiLineEvent
+ * @retval None.
+ */
+#define COMP_EXTI_FALLING_ENABLE(__EXTILINE__) SET_BIT(EXTI->FTSR, (__EXTILINE__))
+
+/**
+ * @brief Disable the Exti Line falling edge trigger.
+ * @param __EXTILINE__ specifies the COMP Exti sources to be disabled.
+ * This parameter can be a value of @ref COMPEx_ExtiLineEvent
+ * @retval None.
+ */
+#define COMP_EXTI_FALLING_DISABLE(__EXTILINE__) CLEAR_BIT(EXTI->FTSR, (__EXTILINE__))
+
+/**
+ * @brief Enable the COMP Exti Line interrupt generation.
+ * @param __EXTILINE__ specifies the COMP Exti sources to be enabled.
+ * This parameter can be a value of @ref COMPEx_ExtiLineEvent
+ * @retval None.
+ */
+#define COMP_EXTI_ENABLE_IT(__EXTILINE__) SET_BIT(EXTI->IMR, (__EXTILINE__))
+
+/**
+ * @brief Disable the COMP Exti Line interrupt generation.
+ * @param __EXTILINE__ specifies the COMP Exti sources to be disabled.
+ * This parameter can be a value of @ref COMPEx_ExtiLineEvent
+ * @retval None.
+ */
+#define COMP_EXTI_DISABLE_IT(__EXTILINE__) CLEAR_BIT(EXTI->IMR, (__EXTILINE__))
+
+/**
+ * @brief Enable the COMP Exti Line event generation.
+ * @param __EXTILINE__ specifies the COMP Exti sources to be enabled.
+ * This parameter can be a value of @ref COMPEx_ExtiLineEvent
+ * @retval None.
+ */
+#define COMP_EXTI_ENABLE_EVENT(__EXTILINE__) SET_BIT(EXTI->EMR, (__EXTILINE__))
+
+/**
+ * @brief Disable the COMP Exti Line event generation.
+ * @param __EXTILINE__ specifies the COMP Exti sources to be disabled.
+ * This parameter can be a value of @ref COMPEx_ExtiLineEvent
+ * @retval None.
+ */
+#define COMP_EXTI_DISABLE_EVENT(__EXTILINE__) CLEAR_BIT(EXTI->EMR, (__EXTILINE__))
+
+/**
+ * @brief Check whether the specified EXTI line flag is set or not.
+ * @param __FLAG__ specifies the COMP Exti sources to be checked.
+ * This parameter can be a value of @ref COMPEx_ExtiLineEvent
+ * @retval The state of __FLAG__ (SET or RESET).
+ */
+#define COMP_EXTI_GET_FLAG(__FLAG__) READ_BIT(EXTI->PR, (__FLAG__))
+
+/**
+ * @brief Clear the COMP Exti flags.
+ * @param __FLAG__ specifies the COMP Exti sources to be cleared.
+ * This parameter can be a value of @ref COMPEx_ExtiLineEvent
+ * @retval None.
+ */
+#define COMP_EXTI_CLEAR_FLAG(__FLAG__) WRITE_REG(EXTI->PR, (__FLAG__))
+
+#else /* STM32F30x, STM32F32xx, STM32F35x, STM32F39x, STM32F33x */
+
+
+/**
+ * @brief Init a comparator instance
+ * @param __HANDLE__ COMP handle
+ * @retval None.
+ */
+#define COMP_INIT(__HANDLE__) \
+ do { \
+ __IO uint32_t csrreg = 0U; \
+ \
+ csrreg = READ_REG((__HANDLE__)->Instance->CSR); \
+ MODIFY_REG(csrreg, COMP_CSR_COMPxINSEL_MASK, (__HANDLE__)->Init.InvertingInput); \
+ MODIFY_REG(csrreg, COMP_CSR_COMPxNONINSEL_MASK, (__HANDLE__)->Init.NonInvertingInput); \
+ MODIFY_REG(csrreg, COMP_CSR_COMPxBLANKING_MASK, (__HANDLE__)->Init.BlankingSrce); \
+ MODIFY_REG(csrreg, COMP_CSR_COMPxOUTSEL_MASK, (__HANDLE__)->Init.Output & COMP_CSR_COMPxOUTSEL_MASK); \
+ MODIFY_REG(csrreg, COMP_CSR_COMPxPOL_MASK, (__HANDLE__)->Init.OutputPol); \
+ MODIFY_REG(csrreg, COMP_CSR_COMPxHYST_MASK, (__HANDLE__)->Init.Hysteresis); \
+ MODIFY_REG(csrreg, COMP_CSR_COMPxMODE_MASK, (__HANDLE__)->Init.Mode); \
+ MODIFY_REG(csrreg, COMP_CSR_COMPxWNDWEN_MASK, (__HANDLE__)->Init.WindowMode); \
+ WRITE_REG((__HANDLE__)->Instance->CSR, csrreg); \
+ } while(0U)
+
+/**
+ * @brief DeInit a comparator instance
+ * @param __HANDLE__ COMP handle
+ * @retval None.
+ */
+#define COMP_DEINIT(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->CSR, COMP_CSR_RESET_VALUE)
+
+/**
+ * @brief Enable the Exti Line rising edge trigger.
+ * @param __EXTILINE__ specifies the COMP Exti sources to be enabled.
+ * This parameter can be a value of @ref COMPEx_ExtiLineEvent
+ * @retval None.
+ */
+#define COMP_EXTI_RISING_ENABLE(__EXTILINE__) ((((__EXTILINE__) & COMP_EXTI_LINE_REG2_MASK) != RESET) ? SET_BIT(EXTI->RTSR2, (__EXTILINE__)) : SET_BIT(EXTI->RTSR, (__EXTILINE__)))
+
+/**
+ * @brief Disable the Exti Line rising edge trigger.
+ * @param __EXTILINE__ specifies the COMP Exti sources to be disabled.
+ * This parameter can be a value of @ref COMPEx_ExtiLineEvent
+ * @retval None.
+ */
+#define COMP_EXTI_RISING_DISABLE(__EXTILINE__) ((((__EXTILINE__) & COMP_EXTI_LINE_REG2_MASK) != RESET) ? CLEAR_BIT(EXTI->RTSR2, (__EXTILINE__)) : CLEAR_BIT(EXTI->RTSR, (__EXTILINE__)))
+
+/**
+ * @brief Enable the Exti Line falling edge trigger.
+ * @param __EXTILINE__ specifies the COMP Exti sources to be enabled.
+ * This parameter can be a value of @ref COMPEx_ExtiLineEvent
+ * @retval None.
+ */
+#define COMP_EXTI_FALLING_ENABLE(__EXTILINE__) ((((__EXTILINE__) & COMP_EXTI_LINE_REG2_MASK) != RESET) ? SET_BIT(EXTI->FTSR2, (__EXTILINE__)) : SET_BIT(EXTI->FTSR, (__EXTILINE__)))
+
+/**
+ * @brief Disable the Exti Line falling edge trigger.
+ * @param __EXTILINE__ specifies the COMP Exti sources to be disabled.
+ * This parameter can be a value of @ref COMPEx_ExtiLineEvent
+ * @retval None.
+ */
+#define COMP_EXTI_FALLING_DISABLE(__EXTILINE__) ((((__EXTILINE__) & COMP_EXTI_LINE_REG2_MASK) != RESET) ? CLEAR_BIT(EXTI->FTSR2, (__EXTILINE__)) : CLEAR_BIT(EXTI->FTSR, (__EXTILINE__)))
+
+/**
+ * @brief Enable the COMP Exti Line interrupt generation.
+ * @param __EXTILINE__ specifies the COMP Exti sources to be enabled.
+ * This parameter can be a value of @ref COMPEx_ExtiLineEvent
+ * @retval None.
+ */
+#define COMP_EXTI_ENABLE_IT(__EXTILINE__) ((((__EXTILINE__) & COMP_EXTI_LINE_REG2_MASK) != RESET) ? SET_BIT(EXTI->IMR2, (__EXTILINE__)) : SET_BIT(EXTI->IMR, (__EXTILINE__)))
+
+/**
+ * @brief Disable the COMP Exti Line interrupt generation.
+ * @param __EXTILINE__ specifies the COMP Exti sources to be disabled.
+ * This parameter can be a value of @ref COMPEx_ExtiLineEvent
+ * @retval None.
+ */
+#define COMP_EXTI_DISABLE_IT(__EXTILINE__) ((((__EXTILINE__) & COMP_EXTI_LINE_REG2_MASK) != RESET) ? CLEAR_BIT(EXTI->IMR2, (__EXTILINE__)) : CLEAR_BIT(EXTI->IMR, (__EXTILINE__)))
+
+/**
+ * @brief Enable the COMP Exti Line event generation.
+ * @param __EXTILINE__ specifies the COMP Exti sources to be enabled.
+ * This parameter can be a value of @ref COMPEx_ExtiLineEvent
+ * @retval None.
+ */
+#define COMP_EXTI_ENABLE_EVENT(__EXTILINE__) ((((__EXTILINE__) & COMP_EXTI_LINE_REG2_MASK) != RESET) ? SET_BIT(EXTI->EMR2, (__EXTILINE__)) : SET_BIT(EXTI->EMR, (__EXTILINE__)))
+
+/**
+ * @brief Disable the COMP Exti Line event generation.
+ * @param __EXTILINE__ specifies the COMP Exti sources to be disabled.
+ * This parameter can be a value of @ref COMPEx_ExtiLineEvent
+ * @retval None.
+ */
+#define COMP_EXTI_DISABLE_EVENT(__EXTILINE__) ((((__EXTILINE__) & COMP_EXTI_LINE_REG2_MASK) != RESET) ? CLEAR_BIT(EXTI->EMR2, (__EXTILINE__)) : CLEAR_BIT(EXTI->EMR, (__EXTILINE__)))
+
+/**
+ * @brief Check whether the specified EXTI line flag is set or not.
+ * @param __FLAG__ specifies the COMP Exti sources to be checked.
+ * This parameter can be a value of @ref COMPEx_ExtiLineEvent
+ * @retval The state of __FLAG__ (SET or RESET).
+ */
+#define COMP_EXTI_GET_FLAG(__FLAG__) ((((__FLAG__) & COMP_EXTI_LINE_REG2_MASK) != RESET) ? READ_BIT(EXTI->PR2, (__FLAG__)) : READ_BIT(EXTI->PR, (__FLAG__)))
+
+/**
+ * @brief Clear the COMP Exti flags.
+ * @param __FLAG__ specifies the COMP Exti sources to be cleared.
+ * This parameter can be a value of @ref COMPEx_ExtiLineEvent
+ * @retval None.
+ */
+#define COMP_EXTI_CLEAR_FLAG(__FLAG__) ((((__FLAG__) & COMP_EXTI_LINE_REG2_MASK) != RESET) ? WRITE_REG(EXTI->PR2, (__FLAG__)) : WRITE_REG(EXTI->PR, (__FLAG__)))
+
+#endif /* STM32F373xC || STM32F378xx */
+
+
+/**
+ * @brief Manage inverting input comparator inverting input connected to a GPIO
+ * for STM32F302x, STM32F32xx, STM32F33x.
+ * - On devices STM32F302x, STM32F32xx, STM32F33x, there is
+ * only 1 comparator inverting input connected to a GPIO.
+ * Legacy definition of literal COMP_INVERTINGINPUT_IO1
+ * was initially the only selection, but depending on
+ * comparator instance it corresponds to COMP_INVERTINGINPUT_IO2
+ * (for instances COMP4, COMP6).
+ * Since, COMP_INVERTINGINPUT_IO2 has been created and this macro
+ * selects the correct literal COMP_INVERTINGINPUT_IOx in function
+ * of comparator instance.
+ * - On other STM32F3 devices, this macro performs no action.
+ * @param __COMP_INSTANCE__ COMP instance
+ * @param __INVERTINGINPUT__ COMP inverting input
+ * @retval None.
+ */
+#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define COMP_INVERTINGINPUT_SELECTION(__COMP_INSTANCE__, __INVERTINGINPUT__) \
+ (((__INVERTINGINPUT__) != COMP_INVERTINGINPUT_IO1) \
+ ? ( \
+ (__INVERTINGINPUT__) \
+ ) \
+ : \
+ (((__COMP_INSTANCE__) == COMP2) \
+ ? ( \
+ (COMP_INVERTINGINPUT_IO1) \
+ ) \
+ : \
+ ( \
+ (COMP_INVERTINGINPUT_IO2) \
+ ) \
+ ) \
+ )
+#else
+#define COMP_INVERTINGINPUT_SELECTION(__COMP_INSTANCE__, __INVERTINGINPUT__) \
+ (__INVERTINGINPUT__)
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup COMPEx_IS_COMP_Definitions COMP Extended Private macros to check input parameters
+ * @{
+ */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+
+#define IS_COMP_INVERTINGINPUT(INPUT) (((INPUT) == COMP_INVERTINGINPUT_1_4VREFINT) || \
+ ((INPUT) == COMP_INVERTINGINPUT_1_2VREFINT) || \
+ ((INPUT) == COMP_INVERTINGINPUT_3_4VREFINT) || \
+ ((INPUT) == COMP_INVERTINGINPUT_VREFINT) || \
+ ((INPUT) == COMP_INVERTINGINPUT_DAC1_CH1) || \
+ ((INPUT) == COMP_INVERTINGINPUT_IO1))
+
+#define IS_COMP_NONINVERTINGINPUT(INPUT) (((INPUT) == COMP_NONINVERTINGINPUT_IO1) || \
+ ((INPUT) == COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED))
+
+/* STM32F301x6/x8, STM32F302x6/x8, STM32F318xx devices comparator instances non inverting source values */
+#define IS_COMP_NONINVERTINGINPUT_INSTANCE(INSTANCE, INPUT) \
+ ((((INSTANCE) == COMP2) && \
+ (((INPUT) == COMP_NONINVERTINGINPUT_IO1) || \
+ ((INPUT) == COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED))) \
+ || \
+ (((INPUT) == COMP_NONINVERTINGINPUT_IO1)))
+
+#define IS_COMP_WINDOWMODE(WINDOWMODE) ((WINDOWMODE) == (WINDOWMODE)) /*!< Not available: check always true */
+
+#define IS_COMP_MODE(MODE) ((MODE) == (MODE)) /*!< Not available: check always true */
+
+#define IS_COMP_HYSTERESIS(HYSTERESIS) ((HYSTERESIS) == (HYSTERESIS)) /*!< Not available: check always true */
+
+#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_COMP6_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16OCREFCLR))
+
+#define IS_COMP_OUTPUT_INSTANCE(INSTANCE, OUTPUT) \
+ ((((INSTANCE) == COMP2) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR))) \
+ || \
+ (((INSTANCE) == COMP4) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15OCREFCLR))) \
+ || \
+ (((INSTANCE) == COMP6) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_COMP6_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16OCREFCLR))))
+
+#define IS_COMP_BLANKINGSRCE(SOURCE) (((SOURCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM1OC5) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM2OC3) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM3OC3) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM3OC4) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM2OC4) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC1) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC2))
+
+/* STM32F301x6/x8, STM32F302x6/x8, STM32F303x6/x8, STM32F334x4/6U/8U, STM32F318xx/STM32F328xx devices comparator instances blanking source values */
+#define IS_COMP_BLANKINGSRCE_INSTANCE(INSTANCE, BLANKINGSRCE) \
+ ((((INSTANCE) == COMP2) && \
+ (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM1OC5) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC3) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC3))) \
+ || \
+ (((INSTANCE) == COMP4) && \
+ (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC4) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC1))) \
+ || \
+ (((INSTANCE) == COMP6) && \
+ (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC4) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC2))))
+
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+
+#define IS_COMP_INVERTINGINPUT(INPUT) (((INPUT) == COMP_INVERTINGINPUT_1_4VREFINT) || \
+ ((INPUT) == COMP_INVERTINGINPUT_1_2VREFINT) || \
+ ((INPUT) == COMP_INVERTINGINPUT_3_4VREFINT) || \
+ ((INPUT) == COMP_INVERTINGINPUT_VREFINT) || \
+ ((INPUT) == COMP_INVERTINGINPUT_DAC1_CH1) || \
+ ((INPUT) == COMP_INVERTINGINPUT_DAC1_CH2) || \
+ ((INPUT) == COMP_INVERTINGINPUT_IO1) || \
+ ((INPUT) == COMP_INVERTINGINPUT_IO2) || \
+ ((INPUT) == COMP_INVERTINGINPUT_DAC2_CH1))
+
+/*!< Non inverting input not available */
+#define IS_COMP_NONINVERTINGINPUT(INPUT) ((INPUT) == (INPUT)) /*!< Multiple selection not available: check always true */
+
+#define IS_COMP_NONINVERTINGINPUT_INSTANCE(INSTANCE, INPUT) ((INPUT) == (INPUT)) /*!< Multiple selection not available: check always true */
+
+#define IS_COMP_WINDOWMODE(WINDOWMODE) ((WINDOWMODE) == (WINDOWMODE)) /*!< Not available: check always true */
+
+#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_COMP6_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC3) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16OCREFCLR))
+
+#define IS_COMP_OUTPUT_INSTANCE(INSTANCE, OUTPUT) \
+ ((((INSTANCE) == COMP2) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR))) \
+ || \
+ (((INSTANCE) == COMP4) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC3) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15OCREFCLR))) \
+ || \
+ (((INSTANCE) == COMP6) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_COMP6_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16OCREFCLR))))
+
+#define IS_COMP_MODE(MODE) ((MODE) == (MODE)) /*!< Not available: check always true */
+
+#define IS_COMP_HYSTERESIS(HYSTERESIS) ((HYSTERESIS) == (HYSTERESIS)) /*!< Not available: check always true */
+
+#define IS_COMP_BLANKINGSRCE(SOURCE) (((SOURCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM1OC5) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM2OC3) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM3OC3) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM3OC4) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM2OC4) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC1) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC2))
+
+/* STM32F301x6/x8, STM32F302x6/x8, STM32F303x6/x8, STM32F334x4/6U/8U, STM32F318xx/STM32F328xx devices comparator instances blanking source values */
+#define IS_COMP_BLANKINGSRCE_INSTANCE(INSTANCE, BLANKINGSRCE) \
+ ((((INSTANCE) == COMP2) && \
+ (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM1OC5) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC3) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC3))) \
+ || \
+ (((INSTANCE) == COMP4) && \
+ (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC4) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC1))) \
+ || \
+ (((INSTANCE) == COMP6) && \
+ (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC4) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC2))))
+
+#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+
+#define IS_COMP_INVERTINGINPUT(INPUT) (((INPUT) == COMP_INVERTINGINPUT_1_4VREFINT) || \
+ ((INPUT) == COMP_INVERTINGINPUT_1_2VREFINT) || \
+ ((INPUT) == COMP_INVERTINGINPUT_3_4VREFINT) || \
+ ((INPUT) == COMP_INVERTINGINPUT_VREFINT) || \
+ ((INPUT) == COMP_INVERTINGINPUT_DAC1_CH1) || \
+ ((INPUT) == COMP_INVERTINGINPUT_DAC1_CH2) || \
+ ((INPUT) == COMP_INVERTINGINPUT_IO1) || \
+ ((INPUT) == COMP_INVERTINGINPUT_IO2))
+
+#define IS_COMP_NONINVERTINGINPUT(INPUT) (((INPUT) == COMP_NONINVERTINGINPUT_IO1) || \
+ ((INPUT) == COMP_NONINVERTINGINPUT_IO2) || \
+ ((INPUT) == COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED))
+
+/* STM32F302xB/xC, STM32F303xB/xC, STM32F358xx devices comparator instances non inverting source values */
+#define IS_COMP_NONINVERTINGINPUT_INSTANCE(INSTANCE, INPUT) \
+ ((((INSTANCE) == COMP1) && \
+ (((INPUT) == COMP_NONINVERTINGINPUT_IO1) || \
+ ((INPUT) == COMP_NONINVERTINGINPUT_IO2) || \
+ ((INPUT) == COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED))) \
+ || \
+ ((((INPUT) == COMP_NONINVERTINGINPUT_IO1) || \
+ ((INPUT) == COMP_NONINVERTINGINPUT_IO2))))
+
+#define IS_COMP_WINDOWMODE(WINDOWMODE) (((WINDOWMODE) == COMP_WINDOWMODE_DISABLE) || \
+ ((WINDOWMODE) == COMP_WINDOWMODE_ENABLE))
+
+#define IS_COMP_MODE(MODE) (((MODE) == COMP_MODE_HIGHSPEED) || \
+ ((MODE) == COMP_MODE_MEDIUMSPEED) || \
+ ((MODE) == COMP_MODE_LOWPOWER) || \
+ ((MODE) == COMP_MODE_ULTRALOWPOWER))
+
+#define IS_COMP_HYSTERESIS(HYSTERESIS) (((HYSTERESIS) == COMP_HYSTERESIS_NONE) || \
+ ((HYSTERESIS) == COMP_HYSTERESIS_LOW) || \
+ ((HYSTERESIS) == COMP_HYSTERESIS_MEDIUM) || \
+ ((HYSTERESIS) == COMP_HYSTERESIS_HIGH))
+
+#if defined(STM32F302xC)
+
+#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC3) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_COMP6_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC4))
+
+#define IS_COMP_OUTPUT_INSTANCE(INSTANCE, OUTPUT) \
+ ((((INSTANCE) == COMP1) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR))) \
+ || \
+ (((INSTANCE) == COMP2) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR))) \
+ || \
+ (((INSTANCE) == COMP4) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC3) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15OCREFCLR))) \
+ || \
+ (((INSTANCE) == COMP6) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_COMP6_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16OCREFCLR))))
+
+#define IS_COMP_BLANKINGSRCE(SOURCE) (((SOURCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM1OC5) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM2OC3) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM3OC3) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM3OC4) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM2OC4) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC1) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC2))
+
+/* STM32F302xB/STM32F302xC/STM32F302xE devices comparator instances blanking source values */
+#define IS_COMP_BLANKINGSRCE_INSTANCE(INSTANCE, BLANKINGSRCE) \
+ (((((INSTANCE) == COMP1) || ((INSTANCE) == COMP2)) && \
+ (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM1OC5) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC3) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC3))) \
+ || \
+ (((INSTANCE) == COMP4) && \
+ (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC4) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC1))) \
+ || \
+ (((INSTANCE) == COMP6) && \
+ (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC4) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC2))))
+
+#endif /* STM32F302xC */
+
+#if defined(STM32F303xC) || defined(STM32F358xx)
+
+#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC3) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_COMP6_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC3) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC3) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM17BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM17IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM17OCREFCLR))
+
+#define IS_COMP_OUTPUT_INSTANCE(INSTANCE, OUTPUT) \
+ ((((INSTANCE) == COMP1) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR))) \
+ || \
+ (((INSTANCE) == COMP2) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR))) \
+ || \
+ (((INSTANCE) == COMP3) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15BKIN))) \
+ || \
+ (((INSTANCE) == COMP4) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC3) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15OCREFCLR))) \
+ || \
+ (((INSTANCE) == COMP5) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC3) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM17IC1))) \
+ || \
+ (((INSTANCE) == COMP6) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_COMP6_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16OCREFCLR))) \
+ || \
+ (((INSTANCE) == COMP7) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC3) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM17BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM17OCREFCLR))))
+
+#define IS_COMP_BLANKINGSRCE(SOURCE) (((SOURCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM1OC5) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM2OC3) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM3OC3) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM2OC4) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM8OC5) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM3OC4) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC1) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC2))
+
+/* STM32F303xE/STM32F398xx/STM32F303xB/STM32F303xC/STM32F358xx devices comparator instances blanking source values */
+#define IS_COMP_BLANKINGSRCE_INSTANCE(INSTANCE, BLANKINGSRCE) \
+ (((((INSTANCE) == COMP1) || ((INSTANCE) == COMP2)) && \
+ (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM1OC5) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC3) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC3))) \
+ || \
+ (((INSTANCE) == COMP3) && \
+ (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM1OC5) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC4))) \
+ || \
+ (((INSTANCE) == COMP4) && \
+ (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC4) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM8OC5) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC1))) \
+ || \
+ (((INSTANCE) == COMP5) && \
+ (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM8OC5) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC3))) \
+ || \
+ (((INSTANCE) == COMP6) && \
+ (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM8OC5) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC4) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC2))) \
+ || \
+ (((INSTANCE) == COMP7) && \
+ (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM1OC5) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM8OC5) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC2))))
+
+#endif /* STM32F303xC || STM32F358xx */
+
+#endif /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+
+#define IS_COMP_INVERTINGINPUT(INPUT) (((INPUT) == COMP_INVERTINGINPUT_1_4VREFINT) || \
+ ((INPUT) == COMP_INVERTINGINPUT_1_2VREFINT) || \
+ ((INPUT) == COMP_INVERTINGINPUT_3_4VREFINT) || \
+ ((INPUT) == COMP_INVERTINGINPUT_VREFINT) || \
+ ((INPUT) == COMP_INVERTINGINPUT_DAC1_CH1) || \
+ ((INPUT) == COMP_INVERTINGINPUT_DAC1_CH2) || \
+ ((INPUT) == COMP_INVERTINGINPUT_IO1) || \
+ ((INPUT) == COMP_INVERTINGINPUT_IO2))
+
+#define IS_COMP_NONINVERTINGINPUT(INPUT) (((INPUT) == COMP_NONINVERTINGINPUT_IO1) || \
+ ((INPUT) == COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED))
+
+/* STM32F302xE/STM32F303xE/STM32F398xx devices comparator instances non inverting source values */
+#define IS_COMP_NONINVERTINGINPUT_INSTANCE(INSTANCE, INPUT) \
+ ((((INSTANCE) == COMP1) && \
+ (((INPUT) == COMP_NONINVERTINGINPUT_IO1) || \
+ ((INPUT) == COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED))) \
+ || \
+ (((INPUT) == COMP_NONINVERTINGINPUT_IO1)))
+
+#define IS_COMP_WINDOWMODE(WINDOWMODE) ((WINDOWMODE) == (WINDOWMODE)) /*!< Not available: check always true */
+
+#define IS_COMP_MODE(MODE) ((MODE) == (MODE)) /*!< Not available: check always true */
+
+#define IS_COMP_HYSTERESIS(HYSTERESIS) ((HYSTERESIS) == (HYSTERESIS)) /*!< Not available: check always true */
+
+#if defined(STM32F302xE)
+
+#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC3) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_COMP6_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC4))
+
+#define IS_COMP_OUTPUT_INSTANCE(INSTANCE, OUTPUT) \
+ ((((INSTANCE) == COMP1) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR))) \
+ || \
+ (((INSTANCE) == COMP2) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR))) \
+ || \
+ (((INSTANCE) == COMP4) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC3) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15OCREFCLR))) \
+ || \
+ (((INSTANCE) == COMP6) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_COMP6_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16OCREFCLR))))
+
+#define IS_COMP_BLANKINGSRCE(SOURCE) (((SOURCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM1OC5) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM2OC3) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM3OC3) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM3OC4) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM2OC4) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC1) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC2))
+
+/* STM32F302xB/STM32F302xC/STM32F302xE devices comparator instances blanking source values */
+#define IS_COMP_BLANKINGSRCE_INSTANCE(INSTANCE, BLANKINGSRCE) \
+ (((((INSTANCE) == COMP1) || ((INSTANCE) == COMP2)) && \
+ (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM1OC5) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC3) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC3))) \
+ || \
+ (((INSTANCE) == COMP4) && \
+ (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC4) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC1))) \
+ || \
+ (((INSTANCE) == COMP6) && \
+ (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC4) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC2))))
+
+#endif /* STM32F302xE */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)
+
+#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_COMP6_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM20OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM20BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM20BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2_TIM20BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC3) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC3) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM17IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC3) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM17BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM17OCREFCLR))
+
+#define IS_COMP_OUTPUT_INSTANCE(INSTANCE, OUTPUT) \
+ ((((INSTANCE) == COMP1) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM20BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM20BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2_TIM20BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR))) \
+ || \
+ (((INSTANCE) == COMP2) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM20BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM20BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2_TIM20BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM20OCREFCLR))) \
+ || \
+ (((INSTANCE) == COMP3) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM20BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM20BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2_TIM20BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15BKIN))) \
+ || \
+ (((INSTANCE) == COMP4) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM20BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM20BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2_TIM20BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC3) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15OCREFCLR))) \
+ || \
+ (((INSTANCE) == COMP5) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM20BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM20BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2_TIM20BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC3) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM17IC1))) \
+ || \
+ (((INSTANCE) == COMP6) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM20BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM20BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2_TIM20BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_COMP6_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16OCREFCLR))) \
+ || \
+ (((INSTANCE) == COMP7) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM20BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM20BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2_TIM20BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC3) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM17BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM17OCREFCLR))))
+
+#define IS_COMP_BLANKINGSRCE(SOURCE) (((SOURCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM1OC5) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM2OC3) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM3OC3) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM2OC4) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM8OC5) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM3OC4) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC1) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC2))
+
+/* STM32F303xE/STM32F398xx/STM32F303xB/STM32F303xC/STM32F358xx devices comparator instances blanking source values */
+#define IS_COMP_BLANKINGSRCE_INSTANCE(INSTANCE, BLANKINGSRCE) \
+ (((((INSTANCE) == COMP1) || ((INSTANCE) == COMP2)) && \
+ (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM1OC5) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC3) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC3))) \
+ || \
+ (((INSTANCE) == COMP3) && \
+ (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM1OC5) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC4))) \
+ || \
+ (((INSTANCE) == COMP4) && \
+ (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC4) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM8OC5) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC1))) \
+ || \
+ (((INSTANCE) == COMP5) && \
+ (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM8OC5) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC3))) \
+ || \
+ (((INSTANCE) == COMP6) && \
+ (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM8OC5) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC4) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC2))) \
+ || \
+ (((INSTANCE) == COMP7) && \
+ (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM1OC5) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM8OC5) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC2))))
+
+#endif /* STM32F303xE || STM32F398xx */
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+
+#define IS_COMP_INVERTINGINPUT(INPUT) (((INPUT) == COMP_INVERTINGINPUT_1_4VREFINT) || \
+ ((INPUT) == COMP_INVERTINGINPUT_1_2VREFINT) || \
+ ((INPUT) == COMP_INVERTINGINPUT_3_4VREFINT) || \
+ ((INPUT) == COMP_INVERTINGINPUT_VREFINT) || \
+ ((INPUT) == COMP_INVERTINGINPUT_DAC1_CH1) || \
+ ((INPUT) == COMP_INVERTINGINPUT_DAC1_CH2) || \
+ ((INPUT) == COMP_INVERTINGINPUT_IO1) || \
+ ((INPUT) == COMP_INVERTINGINPUT_DAC2_CH1))
+
+#define IS_COMP_NONINVERTINGINPUT(INPUT) (((INPUT) == COMP_NONINVERTINGINPUT_IO1) || \
+ ((INPUT) == COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED))
+
+/* STM32F373xB/xC, STM32F378xx devices comparator instances non inverting source values */
+#define IS_COMP_NONINVERTINGINPUT_INSTANCE(INSTANCE, INPUT) \
+ ((((INSTANCE) == COMP1) && \
+ (((INPUT) == COMP_NONINVERTINGINPUT_IO1) || \
+ ((INPUT) == COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED))) \
+ || \
+ (((INPUT) == COMP_NONINVERTINGINPUT_IO1)))
+
+#define IS_COMP_WINDOWMODE(WINDOWMODE) (((WINDOWMODE) == COMP_WINDOWMODE_DISABLE) || \
+ ((WINDOWMODE) == COMP_WINDOWMODE_ENABLE))
+
+#define IS_COMP_MODE(MODE) (((MODE) == COMP_MODE_HIGHSPEED) || \
+ ((MODE) == COMP_MODE_MEDIUMSPEED) || \
+ ((MODE) == COMP_MODE_LOWPOWER) || \
+ ((MODE) == COMP_MODE_ULTRALOWPOWER))
+
+#define IS_COMP_HYSTERESIS(HYSTERESIS) (((HYSTERESIS) == COMP_HYSTERESIS_NONE) || \
+ ((HYSTERESIS) == COMP_HYSTERESIS_LOW) || \
+ ((HYSTERESIS) == COMP_HYSTERESIS_MEDIUM) || \
+ ((HYSTERESIS) == COMP_HYSTERESIS_HIGH))
+
+#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_COMP1_TIM3IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_COMP1_TIM3OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_COMP2_TIM3IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_COMP2_TIM3OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM5IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM5OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16BKIN))
+
+#define IS_COMP_OUTPUT_INSTANCE(INSTANCE, OUTPUT) \
+ ((((INSTANCE) == COMP1) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_COMP1_TIM3IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_COMP1_TIM3OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM5IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM5OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15BKIN))) \
+ || \
+ (((INSTANCE) == COMP2) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_COMP2_TIM3IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_COMP2_TIM3OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16BKIN))))
+
+#define IS_COMP_BLANKINGSRCE(SOURCE) ((SOURCE) == (SOURCE)) /*!< Not available: check always true */
+
+/* STM32F373xB/STM32F373xC/STM32F378xx devices comparator instances blanking source values */
+#define IS_COMP_BLANKINGSRCE_INSTANCE(INSTANCE, BLANKINGSRCE) \
+ ((((INSTANCE) == COMP1) || ((INSTANCE) == COMP2)) && \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE))
+
+#endif /* STM32F373xC || STM32F378xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_COMP_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_hal_conf_template.h b/Inc/stm32f3xx_hal_conf_template.h
new file mode 100644
index 0000000..cc7a486
--- /dev/null
+++ b/Inc/stm32f3xx_hal_conf_template.h
@@ -0,0 +1,342 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_conf.h
+ * @author MCD Application Team
+ * @brief HAL configuration file.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_CONF_H
+#define __STM32F3xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+ * @brief This is the list of modules to be used in the HAL driver
+ */
+#define HAL_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_CAN_MODULE_ENABLED
+/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
+#define HAL_CEC_MODULE_ENABLED
+#define HAL_COMP_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_CRC_MODULE_ENABLED
+#define HAL_DAC_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_SRAM_MODULE_ENABLED
+#define HAL_NOR_MODULE_ENABLED
+#define HAL_NAND_MODULE_ENABLED
+#define HAL_PCCARD_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_HRTIM_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_I2S_MODULE_ENABLED
+#define HAL_IRDA_MODULE_ENABLED
+#define HAL_IWDG_MODULE_ENABLED
+#define HAL_OPAMP_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+#define HAL_SDADC_MODULE_ENABLED
+#define HAL_SMARTCARD_MODULE_ENABLED
+#define HAL_SMBUS_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_TSC_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+#define HAL_USART_MODULE_ENABLED
+#define HAL_WWDG_MODULE_ENABLED
+
+/* ########################## HSE/HSI Values adaptation ##################### */
+/**
+ * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSE is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE (8000000U) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+/**
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
+ * Timeout value
+ */
+#if !defined (HSE_STARTUP_TIMEOUT)
+ #define HSE_STARTUP_TIMEOUT (100U) /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief Internal High Speed oscillator (HSI) value.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSI is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE (8000000U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+ * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
+ * Timeout value
+ */
+#if !defined (HSI_STARTUP_TIMEOUT)
+ #define HSI_STARTUP_TIMEOUT (5000U) /*!< Time out for HSI start up */
+#endif /* HSI_STARTUP_TIMEOUT */
+
+/**
+ * @brief Internal Low Speed oscillator (LSI) value.
+ */
+#if !defined (LSI_VALUE)
+ #define LSI_VALUE (40000U)
+#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
+ The real value may vary depending on the variations
+ in voltage and temperature. */
+/**
+ * @brief External Low Speed oscillator (LSE) value.
+ */
+#if !defined (LSE_VALUE)
+ #define LSE_VALUE (32768U) /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+/**
+ * @brief Time out for LSE start up value in ms.
+ */
+#if !defined (LSE_STARTUP_TIMEOUT)
+ #define LSE_STARTUP_TIMEOUT (5000U) /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief External clock source for I2S peripheral
+ * This value is used by the I2S HAL module to compute the I2S clock source
+ * frequency, this source is inserted directly through I2S_CKIN pad.
+ * - External clock generated through external PLL component on EVAL 303 (based on MCO or crystal)
+ * - External clock not generated on EVAL 373
+ */
+#if !defined (EXTERNAL_CLOCK_VALUE)
+ #define EXTERNAL_CLOCK_VALUE (8000000U) /*!< Value of the External oscillator in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+ === you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+ * @brief This is the HAL system configuration section
+ */
+#define VDD_VALUE (3300U) /*!< Value of VDD in mv */
+#define TICK_INT_PRIORITY ((uint32_t)(1U<<__NVIC_PRIO_BITS) - 1U) /*!< tick interrupt priority (lowest by default) */
+#define USE_RTOS 0U
+#define PREFETCH_ENABLE 1U
+#define INSTRUCTION_CACHE_ENABLE 0U
+#define DATA_CACHE_ENABLE 0U
+#define USE_SPI_CRC 1U
+
+/* ########################## Assert Selection ############################## */
+/**
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ * HAL drivers code
+ */
+/*#define USE_FULL_ASSERT 1U*/
+
+/* Includes ------------------------------------------------------------------*/
+/**
+ * @brief Include module's header file
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+ #include "stm32f3xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+ #include "stm32f3xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+ #include "stm32f3xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+ #include "stm32f3xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+ #include "stm32f3xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+ #include "stm32f3xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
+ #include "stm32f3xx_hal_can_legacy.h"
+#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+ #include "stm32f3xx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+ #include "stm32f3xx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+ #include "stm32f3xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+ #include "stm32f3xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+ #include "stm32f3xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+ #include "stm32f3xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+ #include "stm32f3xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+ #include "stm32f3xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_PCCARD_MODULE_ENABLED
+ #include "stm32f3xx_hal_pccard.h"
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
+#ifdef HAL_HRTIM_MODULE_ENABLED
+ #include "stm32f3xx_hal_hrtim.h"
+#endif /* HAL_HRTIM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32f3xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32f3xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32f3xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32f3xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_OPAMP_MODULE_ENABLED
+ #include "stm32f3xx_hal_opamp.h"
+#endif /* HAL_OPAMP_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32f3xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32f3xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32f3xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SDADC_MODULE_ENABLED
+ #include "stm32f3xx_hal_sdadc.h"
+#endif /* HAL_SDADC_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32f3xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32f3xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32f3xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32f3xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+ #include "stm32f3xx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32f3xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32f3xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32f3xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval None
+ */
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((char *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+ void assert_failed(char* file, uint32_t line);
+#else
+ #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_CONF_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_hal_cortex.h b/Inc/stm32f3xx_hal_cortex.h
new file mode 100644
index 0000000..b4d76ae
--- /dev/null
+++ b/Inc/stm32f3xx_hal_cortex.h
@@ -0,0 +1,442 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_cortex.h
+ * @author MCD Application Team
+ * @brief Header file of CORTEX HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_CORTEX_H
+#define __STM32F3xx_HAL_CORTEX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CORTEX
+ * @{
+ */
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Types CORTEX Exported Types
+ * @{
+ */
+
+#if (__MPU_PRESENT == 1U)
+/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
+ * @brief MPU Region initialization structure
+ * @{
+ */
+typedef struct
+{
+ uint8_t Enable; /*!< Specifies the status of the region.
+ This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
+ uint8_t Number; /*!< Specifies the number of the region to protect.
+ This parameter can be a value of @ref CORTEX_MPU_Region_Number */
+ uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
+ uint8_t Size; /*!< Specifies the size of the region to protect.
+ This parameter can be a value of @ref CORTEX_MPU_Region_Size */
+ uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+ uint8_t TypeExtField; /*!< Specifies the TEX field level.
+ This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
+ uint8_t AccessPermission; /*!< Specifies the region access permission type.
+ This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
+ uint8_t DisableExec; /*!< Specifies the instruction access status.
+ This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
+ uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
+ This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
+ uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
+ This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
+ uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
+ This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
+}MPU_Region_InitTypeDef;
+/**
+ * @}
+ */
+#endif /* __MPU_PRESENT */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
+ * @{
+ */
+
+/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
+ * @{
+ */
+#define NVIC_PRIORITYGROUP_0 (0x00000007U) /*!< 0 bits for pre-emption priority
+ 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1 (0x00000006U) /*!< 1 bits for pre-emption priority
+ 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2 (0x00000005U) /*!< 2 bits for pre-emption priority
+ 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3 (0x00000004U) /*!< 3 bits for pre-emption priority
+ 1 bits for subpriority */
+#define NVIC_PRIORITYGROUP_4 (0x00000003U) /*!< 4 bits for pre-emption priority
+ 0 bits for subpriority */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
+ * @{
+ */
+#define SYSTICK_CLKSOURCE_HCLK_DIV8 (0x00000000U)
+#define SYSTICK_CLKSOURCE_HCLK (0x00000004U)
+/**
+ * @}
+ */
+
+#if (__MPU_PRESENT == 1U)
+/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
+ * @{
+ */
+#define MPU_HFNMI_PRIVDEF_NONE (0x00000000U)
+#define MPU_HARDFAULT_NMI (0x00000002U)
+#define MPU_PRIVILEGED_DEFAULT (0x00000004U)
+#define MPU_HFNMI_PRIVDEF (0x00000006U)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
+ * @{
+ */
+#define MPU_REGION_ENABLE ((uint8_t)0x01U)
+#define MPU_REGION_DISABLE ((uint8_t)0x00U)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
+ * @{
+ */
+#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U)
+#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
+ * @{
+ */
+#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01U)
+#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
+ * @{
+ */
+#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01U)
+#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
+ * @{
+ */
+#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U)
+#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
+ * @{
+ */
+#define MPU_TEX_LEVEL0 ((uint8_t)0x00U)
+#define MPU_TEX_LEVEL1 ((uint8_t)0x01U)
+#define MPU_TEX_LEVEL2 ((uint8_t)0x02U)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
+ * @{
+ */
+#define MPU_REGION_SIZE_32B ((uint8_t)0x04U)
+#define MPU_REGION_SIZE_64B ((uint8_t)0x05U)
+#define MPU_REGION_SIZE_128B ((uint8_t)0x06U)
+#define MPU_REGION_SIZE_256B ((uint8_t)0x07U)
+#define MPU_REGION_SIZE_512B ((uint8_t)0x08U)
+#define MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
+#define MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
+#define MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
+#define MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
+#define MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
+#define MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
+#define MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
+#define MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
+#define MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
+#define MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
+#define MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
+#define MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
+#define MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
+#define MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
+#define MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
+#define MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
+#define MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
+#define MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
+#define MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
+#define MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
+#define MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
+#define MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
+#define MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
+ * @{
+ */
+#define MPU_REGION_NO_ACCESS ((uint8_t)0x00U)
+#define MPU_REGION_PRIV_RW ((uint8_t)0x01U)
+#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U)
+#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03U)
+#define MPU_REGION_PRIV_RO ((uint8_t)0x05U)
+#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
+ * @{
+ */
+#define MPU_REGION_NUMBER0 ((uint8_t)0x00U)
+#define MPU_REGION_NUMBER1 ((uint8_t)0x01U)
+#define MPU_REGION_NUMBER2 ((uint8_t)0x02U)
+#define MPU_REGION_NUMBER3 ((uint8_t)0x03U)
+#define MPU_REGION_NUMBER4 ((uint8_t)0x04U)
+#define MPU_REGION_NUMBER5 ((uint8_t)0x05U)
+#define MPU_REGION_NUMBER6 ((uint8_t)0x06U)
+#define MPU_REGION_NUMBER7 ((uint8_t)0x07U)
+/**
+ * @}
+ */
+#endif /* __MPU_PRESENT */
+
+/**
+ * @}
+ */
+
+/* Exported Macros -----------------------------------------------------------*/
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CORTEX_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup CORTEX_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SystemReset(void);
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
+/**
+ * @}
+ */
+
+/** @addtogroup CORTEX_Exported_Functions_Group2
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+#if (__MPU_PRESENT == 1U)
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
+#endif /* __MPU_PRESENT */
+uint32_t HAL_NVIC_GetPriorityGrouping(void);
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
+void HAL_SYSTICK_IRQHandler(void);
+void HAL_SYSTICK_Callback(void);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
+ * @{
+ */
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
+ ((GROUP) == NVIC_PRIORITYGROUP_1) || \
+ ((GROUP) == NVIC_PRIORITYGROUP_2) || \
+ ((GROUP) == NVIC_PRIORITYGROUP_3) || \
+ ((GROUP) == NVIC_PRIORITYGROUP_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
+
+#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
+
+/** @defgroup CORTEX_SysTick_clock_source_Macro_Private CORTEX SysTick clock source
+ * @{
+ */
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
+ ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
+/**
+ * @}
+ */
+
+#if (__MPU_PRESENT == 1U)
+#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
+ ((STATE) == MPU_REGION_DISABLE))
+
+#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
+ ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
+
+#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
+ ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
+
+#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
+ ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
+
+#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
+ ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
+
+#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
+ ((TYPE) == MPU_TEX_LEVEL1) || \
+ ((TYPE) == MPU_TEX_LEVEL2))
+
+#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
+ ((TYPE) == MPU_REGION_PRIV_RW) || \
+ ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
+ ((TYPE) == MPU_REGION_FULL_ACCESS) || \
+ ((TYPE) == MPU_REGION_PRIV_RO) || \
+ ((TYPE) == MPU_REGION_PRIV_RO_URO))
+
+#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
+ ((NUMBER) == MPU_REGION_NUMBER1) || \
+ ((NUMBER) == MPU_REGION_NUMBER2) || \
+ ((NUMBER) == MPU_REGION_NUMBER3) || \
+ ((NUMBER) == MPU_REGION_NUMBER4) || \
+ ((NUMBER) == MPU_REGION_NUMBER5) || \
+ ((NUMBER) == MPU_REGION_NUMBER6) || \
+ ((NUMBER) == MPU_REGION_NUMBER7))
+
+#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
+ ((SIZE) == MPU_REGION_SIZE_64B) || \
+ ((SIZE) == MPU_REGION_SIZE_128B) || \
+ ((SIZE) == MPU_REGION_SIZE_256B) || \
+ ((SIZE) == MPU_REGION_SIZE_512B) || \
+ ((SIZE) == MPU_REGION_SIZE_1KB) || \
+ ((SIZE) == MPU_REGION_SIZE_2KB) || \
+ ((SIZE) == MPU_REGION_SIZE_4KB) || \
+ ((SIZE) == MPU_REGION_SIZE_8KB) || \
+ ((SIZE) == MPU_REGION_SIZE_16KB) || \
+ ((SIZE) == MPU_REGION_SIZE_32KB) || \
+ ((SIZE) == MPU_REGION_SIZE_64KB) || \
+ ((SIZE) == MPU_REGION_SIZE_128KB) || \
+ ((SIZE) == MPU_REGION_SIZE_256KB) || \
+ ((SIZE) == MPU_REGION_SIZE_512KB) || \
+ ((SIZE) == MPU_REGION_SIZE_1MB) || \
+ ((SIZE) == MPU_REGION_SIZE_2MB) || \
+ ((SIZE) == MPU_REGION_SIZE_4MB) || \
+ ((SIZE) == MPU_REGION_SIZE_8MB) || \
+ ((SIZE) == MPU_REGION_SIZE_16MB) || \
+ ((SIZE) == MPU_REGION_SIZE_32MB) || \
+ ((SIZE) == MPU_REGION_SIZE_64MB) || \
+ ((SIZE) == MPU_REGION_SIZE_128MB) || \
+ ((SIZE) == MPU_REGION_SIZE_256MB) || \
+ ((SIZE) == MPU_REGION_SIZE_512MB) || \
+ ((SIZE) == MPU_REGION_SIZE_1GB) || \
+ ((SIZE) == MPU_REGION_SIZE_2GB) || \
+ ((SIZE) == MPU_REGION_SIZE_4GB))
+
+#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU)
+#endif /* __MPU_PRESENT */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup CORTEX_Private_Functions CORTEX Private Functions
+ * @brief CORTEX private functions
+ * @{
+ */
+
+#if (__MPU_PRESENT == 1U)
+
+void HAL_MPU_Disable(void);
+void HAL_MPU_Enable(uint32_t MPU_Control);
+
+#endif /* __MPU_PRESENT */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_CORTEX_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_hal_crc.h b/Inc/stm32f3xx_hal_crc.h
new file mode 100644
index 0000000..f4a56c9
--- /dev/null
+++ b/Inc/stm32f3xx_hal_crc.h
@@ -0,0 +1,366 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_crc.h
+ * @author MCD Application Team
+ * @brief Header file of CRC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_CRC_H
+#define __STM32F3xx_HAL_CRC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CRC CRC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CRC_Exported_Types CRC Exported Types
+ * @{
+ */
+/**
+ * @brief CRC HAL State Structure definition
+ */
+typedef enum
+{
+ HAL_CRC_STATE_RESET = 0x00U, /*!< CRC not yet initialized or disabled */
+ HAL_CRC_STATE_READY = 0x01U, /*!< CRC initialized and ready for use */
+ HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */
+ HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */
+ HAL_CRC_STATE_ERROR = 0x04 /*!< CRC error state */
+}HAL_CRC_StateTypeDef;
+
+
+/**
+ * @brief CRC Init Structure definition
+ */
+typedef struct
+{
+ uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.
+ If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default
+ X^32U + X^26U + X^23U + X^22U + X^16U + X^12U + X^11U + X^10U +X^8U + X^7U + X^5U + X^4U + X^2U+ X +1.
+ In that case, there is no need to set GeneratingPolynomial field.
+ If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set. */
+
+ uint8_t DefaultInitValueUse; /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used.
+ If set to DEFAULT_INIT_VALUE_ENABLE, resort to default
+ 0xFFFFFFFF value. In that case, there is no need to set InitValue field.
+ If otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */
+
+ uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial as a 7U, 8U, 16 or 32-bit long value for a polynomial degree
+ respectively equal to 7U, 8U, 16 or 32. This field is written in normal representation,
+ e.g., for a polynomial of degree 7U, X^7U + X^6U + X^5U + X^2U + 1 is written 0x65.
+ No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE. */
+
+ uint32_t CRCLength; /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length.
+ Value can be either one of
+ @arg CRC_POLYLENGTH_32B (32-bit CRC),
+ @arg CRC_POLYLENGTH_16B (16-bit CRC),
+ @arg CRC_POLYLENGTH_8B (8-bit CRC),
+ @arg CRC_POLYLENGTH_7B (7-bit CRC). */
+
+ uint32_t InitValue; /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse
+ is set to DEFAULT_INIT_VALUE_ENABLE. */
+
+ uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode.
+ Can be either one of the following values
+ @arg CRC_INPUTDATA_INVERSION_NONE, no input data inversion
+ @arg CRC_INPUTDATA_INVERSION_BYTE, byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2
+ @arg CRC_INPUTDATA_INVERSION_HALFWORD, halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C
+ @arg CRC_INPUTDATA_INVERSION_WORD, word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458U */
+
+ uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
+ Can be either
+ @arg CRC_OUTPUTDATA_INVERSION_DISABLE: no CRC inversion,
+ @arg CRC_OUTPUTDATA_INVERSION_ENABLE: CRC 0x11223344 is converted into 0x22CC4488U */
+}CRC_InitTypeDef;
+
+
+/**
+ * @brief CRC Handle Structure definition
+ */
+typedef struct
+{
+ CRC_TypeDef *Instance; /*!< Register base address */
+
+ CRC_InitTypeDef Init; /*!< CRC configuration parameters */
+
+ HAL_LockTypeDef Lock; /*!< CRC Locking object */
+
+ __IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */
+
+ uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format.
+ Can be either
+ @arg CRC_INPUTDATA_FORMAT_BYTES, input data is a stream of bytes (8-bit data)
+ @arg CRC_INPUTDATA_FORMAT_HALFWORDS, input data is a stream of half-words (16-bit data)
+ @arg CRC_INPUTDATA_FORMAT_WORDS, input data is a stream of words (32-bit data)
+
+ Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error
+ must occur if InputBufferFormat is not one of the three values listed above */
+}CRC_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRC_Exported_Constants CRC Exported Constants
+ * @{
+ */
+/** @defgroup CRC_Default_Polynomial_Value Default CRC generating polynomial
+ * @{
+ */
+#define DEFAULT_CRC32_POLY 0x04C11DB7 /*!< X^32U + X^26U + X^23U + X^22U + X^16U + X^12U + X^11U + X^10U +X^8U + X^7U + X^5U + X^4U + X^2U+ X +1U */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Default_InitValue Default CRC computation initialization value
+ * @{
+ */
+#define DEFAULT_CRC_INITVALUE 0xFFFFFFFFU /*!< Initial CRC default value */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used
+ * @{
+ */
+#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U) /*!< Enable default generating polynomial 0x04C11DB7 */
+#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U) /*!< Disable default generating polynomial 0x04C11DB7U */
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Default_InitValue_Use Indicates whether or not default init value is used
+ * @{
+ */
+#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U) /*!< Enable initial CRC default value */
+#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U) /*!< Disable initial CRC default value */
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the IP
+ * @{
+ */
+#define CRC_POLYLENGTH_32B (0x00000000U) /*!< Resort to a 32-bit long generating polynomial */
+#define CRC_POLYLENGTH_16B ((uint32_t)CRC_CR_POLYSIZE_0) /*!< Resort to a 16-bit long generating polynomial */
+#define CRC_POLYLENGTH_8B ((uint32_t)CRC_CR_POLYSIZE_1) /*!< Resort to a 8-bit long generating polynomial */
+#define CRC_POLYLENGTH_7B ((uint32_t)CRC_CR_POLYSIZE) /*!< Resort to a 7-bit long generating polynomial */
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions
+ * @{
+ */
+#define HAL_CRC_LENGTH_32B 32 /*!< 32-bit long CRC */
+#define HAL_CRC_LENGTH_16B 16 /*!< 16-bit long CRC */
+#define HAL_CRC_LENGTH_8B 8 /*!< 8-bit long CRC */
+#define HAL_CRC_LENGTH_7B 7 /*!< 7-bit long CRC */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Input_Buffer_Format Input Buffer Format
+ * @{
+ */
+/* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but
+ * an error is triggered in HAL_CRC_Init() if InputDataFormat field is set
+ * to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for
+ * the CRC APIs to provide a correct result */
+#define CRC_INPUTDATA_FORMAT_UNDEFINED (0x00000000U) /*!< Undefined input data format */
+#define CRC_INPUTDATA_FORMAT_BYTES (0x00000001U) /*!< Input data in byte format */
+#define CRC_INPUTDATA_FORMAT_HALFWORDS (0x00000002U) /*!< Input data in half-word format */
+#define CRC_INPUTDATA_FORMAT_WORDS (0x00000003U) /*!< Input data in word format */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup CRC_Exported_Macros CRC Exported Macros
+ * @{
+ */
+
+/** @brief Reset CRC handle state.
+ * @param __HANDLE__ CRC handle.
+ * @retval None
+ */
+#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
+
+/**
+ * @brief Reset CRC Data Register.
+ * @param __HANDLE__ CRC handle
+ * @retval None
+ */
+#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
+
+/**
+ * @brief Set CRC INIT non-default value
+* @param __HANDLE__ CRC handle
+ * @param __INIT__ 32-bit initial value
+ * @retval None
+ */
+#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
+
+/**
+ * @brief Store a 8-bit data in the Independent Data(ID) register.
+ * @param __HANDLE__ CRC handle
+ * @param __VALUE__ 8-bit value to be stored in the ID register
+ * @retval None
+ */
+#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
+
+/**
+ * @brief Return the 8-bit data stored in the Independent Data(ID) register.
+ * @param __HANDLE__ CRC handle
+ * @retval 8-bit value of the ID register
+ */
+#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
+/**
+ * @}
+ */
+
+
+/* Private macros --------------------------------------------------------*/
+/** @addtogroup CRC_Private_Macros CRC Private Macros
+ * @{
+ */
+
+#define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
+ ((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))
+
+
+#define IS_DEFAULT_INIT_VALUE(VALUE) (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
+ ((VALUE) == DEFAULT_INIT_VALUE_DISABLE))
+
+#define IS_CRC_POL_LENGTH(LENGTH) (((LENGTH) == CRC_POLYLENGTH_32B) || \
+ ((LENGTH) == CRC_POLYLENGTH_16B) || \
+ ((LENGTH) == CRC_POLYLENGTH_8B) || \
+ ((LENGTH) == CRC_POLYLENGTH_7B))
+
+#define IS_CRC_INPUTDATA_FORMAT(FORMAT) (((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES) || \
+ ((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
+ ((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS))
+
+/**
+ * @}
+ */
+
+/* Include CRC HAL Extended module */
+#include "stm32f3xx_hal_crc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CRC_Exported_Functions CRC Exported Functions
+ * @{
+ */
+
+/** @addtogroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions.
+ * @{
+ */
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
+HAL_StatusTypeDef HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc);
+void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
+void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Exported_Functions_Group2 Peripheral Control functions
+ * @brief management functions.
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
+uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Exported_Functions_Group3 Peripheral State functions
+ * @brief Peripheral State functions.
+ * @{
+ */
+/* Peripheral State and Error functions ***************************************/
+HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+ /** @defgroup HAL_CRC_Alias_Exported_Functions CRC aliases for Exported Functions
+ * @{
+ */
+/* Aliases for inter STM32 series compatibility */
+#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse
+#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_CRC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_hal_crc_ex.h b/Inc/stm32f3xx_hal_crc_ex.h
new file mode 100644
index 0000000..722d136
--- /dev/null
+++ b/Inc/stm32f3xx_hal_crc_ex.h
@@ -0,0 +1,173 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_crc_ex.h
+ * @author MCD Application Team
+ * @brief Header file of CRC HAL extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_CRC_EX_H
+#define __STM32F3xx_HAL_CRC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CRCEx CRCEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRCEx_Exported_Constants CRC Extended Exported Constants
+ * @{
+ */
+
+/** @defgroup CRCEx_Input_Data_Inversion CRC Extended Input Data Inversion Modes
+ * @{
+ */
+#define CRC_INPUTDATA_INVERSION_NONE (0x00000000U) /*!< No input data inversion */
+#define CRC_INPUTDATA_INVERSION_BYTE ((uint32_t)CRC_CR_REV_IN_0) /*!< Byte-wise input data inversion */
+#define CRC_INPUTDATA_INVERSION_HALFWORD ((uint32_t)CRC_CR_REV_IN_1) /*!< HalfWord-wise input data inversion */
+#define CRC_INPUTDATA_INVERSION_WORD ((uint32_t)CRC_CR_REV_IN) /*!< Word-wise input data inversion */
+/**
+ * @}
+ */
+
+/** @defgroup CRCEx_Output_Data_Inversion CRC Extended Output Data Inversion Modes
+ * @{
+ */
+#define CRC_OUTPUTDATA_INVERSION_DISABLE (0x00000000U) /*!< No output data inversion */
+#define CRC_OUTPUTDATA_INVERSION_ENABLE ((uint32_t)CRC_CR_REV_OUT) /*!< Bit-wise output data inversion */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup CRCEx_Exported_Macros CRC Extended Exported Macros
+ * @{
+ */
+
+/**
+ * @brief Set CRC output reversal
+ * @param __HANDLE__ CRC handle
+ * @retval None.
+ */
+#define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
+
+/**
+ * @brief Unset CRC output reversal
+ * @param __HANDLE__ CRC handle
+ * @retval None.
+ */
+#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
+
+/**
+ * @brief Set CRC non-default polynomial
+ * @param __HANDLE__ CRC handle
+ * @param __POLYNOMIAL__ 7, 8, 16 or 32-bit polynomial
+ * @retval None.
+ */
+#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
+
+/**
+ * @}
+ */
+
+/* Private macros --------------------------------------------------------*/
+/** @addtogroup CRCEx_Private_Macros CRCEx Private Macros
+ * @{
+ */
+
+#define IS_CRC_INPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_INPUTDATA_INVERSION_NONE) || \
+ ((MODE) == CRC_INPUTDATA_INVERSION_BYTE) || \
+ ((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
+ ((MODE) == CRC_INPUTDATA_INVERSION_WORD))
+
+
+#define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
+ ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CRCEx_Exported_Functions CRC Extended Exported Functions
+ * @{
+ */
+
+/** @addtogroup CRCEx_Exported_Functions_Group1 CRC Extended Initialization and de-initialization functions
+ * @brief Extended Initialization and Configuration functions.
+ * @{
+ */
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);
+HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);
+HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);
+/**
+ * @}
+ */
+
+/* Peripheral Control functions ***********************************************/
+/* Peripheral State and Error functions ***************************************/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_CRC_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_hal_dac.h b/Inc/stm32f3xx_hal_dac.h
new file mode 100644
index 0000000..1267f84
--- /dev/null
+++ b/Inc/stm32f3xx_hal_dac.h
@@ -0,0 +1,454 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_dac.h
+ * @author MCD Application Team
+ * @brief Header file of DAC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_DAC_H
+#define __STM32F3xx_HAL_DAC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DAC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup DAC_Exported_Types DAC Exported Types
+ * @{
+ */
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_DAC_STATE_RESET = 0x00U, /*!< DAC not yet initialized or disabled */
+ HAL_DAC_STATE_READY = 0x01U, /*!< DAC initialized and ready for use */
+ HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */
+ HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */
+ HAL_DAC_STATE_ERROR = 0x04 /*!< DAC error state */
+
+}HAL_DAC_StateTypeDef;
+
+/**
+ * @brief DAC Configuration regular Channel structure definition
+ */
+typedef struct
+{
+ uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
+ This parameter can be a value of @ref DACEx_trigger_selection */
+
+ uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
+ This parameter can be a value of @ref DAC_output_buffer
+ For a given DAC channel, is this paramater applies then DAC_OutputSwitch
+ does not apply */
+
+ uint32_t DAC_OutputSwitch; /*!< Specifies whether the DAC channel output switch is enabled or disabled.
+ This parameter can be a value of @ref DAC_OutputSwitch
+ For a given DAC channel, is this paramater applies then DAC_OutputBuffer
+ does not apply */
+
+}DAC_ChannelConfTypeDef;
+
+/**
+ * @brief DAC handle Structure definition
+ */
+typedef struct __DAC_HandleTypeDef
+{
+ DAC_TypeDef *Instance; /*!< Register base address */
+
+ __IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */
+
+ HAL_LockTypeDef Lock; /*!< DAC locking object */
+
+ DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1U */
+
+ DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2U */
+
+ __IO uint32_t ErrorCode; /*!< DAC Error code */
+
+}DAC_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DAC_Exported_Constants DAC Exported Constants
+ * @{
+ */
+
+/** @defgroup DAC_Error_Code DAC Error Code
+ * @{
+ */
+#define HAL_DAC_ERROR_NONE 0x00 /*!< No error */
+#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01 /*!< DAC channel1 DMA underrun error */
+#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02 /*!< DAC channel2 DMA underrun error */
+#define HAL_DAC_ERROR_DMA 0x04 /*!< DMA error */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_lfsrunmask_triangleamplitude DAC lfsrunmask triangleamplitude
+ * @{
+ */
+#define DAC_LFSRUNMASK_BIT0 (0x00000000U) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS4_0 ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS8_0 ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
+#define DAC_TRIANGLEAMPLITUDE_1 (0x00000000U) /*!< Select max triangle amplitude of 1U */
+#define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3U */
+#define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7U */
+#define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15U */
+#define DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31U */
+#define DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63U */
+#define DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127U */
+#define DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255U */
+#define DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511U */
+#define DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023U */
+#define DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047U */
+#define DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095U */
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_output_buffer DAC output buffer
+ * @{
+ */
+#define DAC_OUTPUTBUFFER_ENABLE (0x00000000U)
+#define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1)
+
+/**
+ * @}
+ */
+
+#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+/** @defgroup DAC_output_switch DAC output switch
+ * @{
+ */
+#define DAC_OUTPUTSWITCH_DISABLE (0x00000000U)
+#define DAC_OUTPUTSWITCH_ENABLE ((uint32_t)DAC_CR_OUTEN1)
+
+/**
+ * @}
+ */
+
+#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+/** @defgroup DAC_data_alignement DAC data alignement
+ * @{
+ */
+#define DAC_ALIGN_12B_R (0x00000000U)
+#define DAC_ALIGN_12B_L (0x00000004U)
+#define DAC_ALIGN_8B_R (0x00000008U)
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_flags_definition DAC flags definition
+ * @{
+ */
+#define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
+#define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
+/**
+ * @}
+ */
+
+/** @defgroup DAC_interrupts_definition DAC interrupts definition
+ * @{
+ */
+#define DAC_IT_DMAUDR1 ((uint32_t)DAC_CR_DMAUDRIE1)
+#define DAC_IT_DMAUDR2 ((uint32_t)DAC_CR_DMAUDRIE2)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup DAC_Exported_Macros DAC Exported Macros
+ * @{
+ */
+
+/** @brief Reset DAC handle state
+ * @param __HANDLE__ specifies the DAC handle.
+ * @retval None
+ */
+#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
+
+/** @brief Enable the DAC channel
+ * @param __HANDLE__ specifies the DAC handle.
+ * @param __DAC_Channel__ specifies the DAC channel
+ * @retval None
+ */
+#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
+((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__)))
+
+/** @brief Disable the DAC channel
+ * @param __HANDLE__ specifies the DAC handle
+ * @param __DAC_Channel__ specifies the DAC channel.
+ * @retval None
+ */
+#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
+((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__)))
+
+/** @brief Set DHR12R1 alignment
+ * @param __ALIGNMENT__ specifies the DAC alignment
+ * @retval None
+ */
+#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) ((0x00000008U) + (__ALIGNMENT__))
+
+/** @brief Set DHR12R2 alignment
+ * @param __ALIGNMENT__ specifies the DAC alignment
+ * @retval None
+ */
+#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) ((0x00000014U) + (__ALIGNMENT__))
+
+/** @brief Set DHR12RD alignment
+ * @param __ALIGNMENT__ specifies the DAC alignment
+ * @retval None
+ */
+#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) ((0x00000020U) + (__ALIGNMENT__))
+
+/** @brief Enable the DAC interrupt
+ * @param __HANDLE__ specifies the DAC handle
+ * @param __INTERRUPT__ specifies the DAC interrupt.
+ * This parameter can be any combination of the following values:
+ * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
+ * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
+ * @retval None
+ */
+#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
+
+/** @brief Disable the DAC interrupt
+ * @param __HANDLE__ specifies the DAC handle
+ * @param __INTERRUPT__ specifies the DAC interrupt.
+ * This parameter can be any combination of the following values:
+ * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
+ * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
+ * @retval None
+ */
+#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
+
+/** @brief Check whether the specified DAC interrupt source is enabled or not
+ * @param __HANDLE__ DAC handle
+ * @param __INTERRUPT__ DAC interrupt source to check
+ * This parameter can be any combination of the following values:
+ * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
+ * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
+ * @retval State of interruption (SET or RESET)
+ */
+#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/** @brief Get the selected DAC's flag status
+ * @param __HANDLE__ specifies the DAC handle.
+ * @param __FLAG__ specifies the DAC flag to get.
+ * This parameter can be any combination of the following values:
+ * @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
+ * @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
+ * @retval None
+ */
+#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the DAC's flag
+ * @param __HANDLE__ specifies the DAC handle.
+ * @param __FLAG__ specifies the DAC flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
+ * @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
+ * @retval None
+ */
+#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+
+/** @addtogroup DAC_Private_Macros
+ * @{
+ */
+
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
+
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
+ ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
+
+#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define IS_DAC_OUTPUT_SWITCH_STATE(STATE) (((STATE) == DAC_OUTPUTSWITCH_DISABLE) || \
+ ((STATE) == DAC_OUTPUTSWITCH_ENABLE))
+
+#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
+ ((ALIGN) == DAC_ALIGN_12B_L) || \
+ ((ALIGN) == DAC_ALIGN_8B_R))
+
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U)
+
+
+
+/**
+ * @}
+ */
+
+
+/* Include DAC HAL Extended module */
+#include "stm32f3xx_hal_dac_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup DAC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DAC_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
+HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
+void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
+void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Exported_Functions_Group2
+ * @{
+ */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
+HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
+uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
+
+void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
+void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
+void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
+void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
+void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Exported_Functions_Group4
+ * @{
+ */
+/* Peripheral State and Error functions ***************************************/
+HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
+uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F3xx_HAL_DAC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_hal_dac_ex.h b/Inc/stm32f3xx_hal_dac_ex.h
new file mode 100644
index 0000000..7c35822
--- /dev/null
+++ b/Inc/stm32f3xx_hal_dac_ex.h
@@ -0,0 +1,359 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_dac_ex.h
+ * @author MCD Application Team
+ * @brief Header file of DAC HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_DAC_EX_H
+#define __STM32F3xx_HAL_DAC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DACEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DACEx_Exported_Constants DACEx Exported Constants
+ * @{
+ */
+
+/** @defgroup DACEx_trigger_selection DACEx trigger selection
+ * @{
+ */
+
+#if defined(STM32F301x8) || defined(STM32F318xx)
+#define DAC_TRIGGER_NONE (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
+ has been loaded, and not by external trigger */
+#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
+
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
+ ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
+ ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
+#endif /* STM32F301x8 || STM32F318xx */
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC) || \
+ defined(STM32F302x8)
+
+#define DAC_TRIGGER_NONE (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
+ has been loaded, and not by external trigger */
+#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
+
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
+ ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
+ ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
+
+#endif /* STM32F302xE || */
+ /* STM32F302xC || */
+ /* STM32F302x8 */
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+
+#define DAC_TRIGGER_NONE (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
+ has been loaded, and not by external trigger */
+#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel
+ Use __HAL_REMAPTRIGGER_ENABLE(HAL_REMAPTRIGGER_DAC1_TRIG) for TIM3 selection */
+#define DAC_TRIGGER_T8_TRGO DAC_TRIGGER_T3_TRGO /*!< TIM8 TRGO selected as external conversion trigger for DAC channel
+ Use __HAL_REMAPTRIGGER_DISABLE(HAL_REMAPTRIGGER_DAC1_TRIG) for TIM8 selection */
+
+#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
+
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
+ ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
+ ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+
+#if defined(STM32F303x8) || defined(STM32F328xx)
+
+#define DAC_TRIGGER_NONE (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
+ has been loaded, and not by external trigger */
+#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
+
+#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
+
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
+ ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
+ ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
+
+#endif /* STM32F303x8 || STM32F328xx */
+
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+
+#define DAC_TRIGGER_NONE (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
+ has been loaded, and not by external trigger */
+
+#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T5_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel (DAC1) */
+#define DAC_TRIGGER_T18_TRGO DAC_TRIGGER_T5_TRGO /*!< TIM18 TRGO selected as external conversion trigger for DAC channel (DAC2) */
+#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
+
+#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
+
+
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
+ ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
+ ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F334x8)
+
+#define DAC_TRIGGER_NONE (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
+ has been loaded, and not by external trigger */
+#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel
+ Use __HAL_REMAPTRIGGER_ENABLE(HAL_REMAPTRIGGER_DAC1_TRIG) for TIM3 remap */
+
+#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel
+ Use __HAL_REMAPTRIGGER_DISABLE(HAL_REMAPTRIGGER_DAC1_TRIG3) for TIM15 selection */
+#define DAC_TRIGGER_HRTIM1_DACTRG1 DAC_TRIGGER_T15_TRGO /*!< HRTIM1 DACTRG1 selected as external conversion trigger for DAC
+ Use __HAL_REMAPTRIGGER_ENABLE(HAL_REMAPTRIGGER_DAC1_TRIG3) for HRTIM1 DACTRG1 selection */
+
+#define DAC_TRIGGER_HRTIM1_DACTRG2 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< HRTIM1 DACTRG2 selected as external conversion trigger for DAC channel (DAC1)
+ Use __HAL_REMAPTRIGGER_ENABLE(HAL_REMAPTRIGGER_DAC1_TRIG5) for HRTIM1 DACTRG2 remap */
+#define DAC_TRIGGER_HRTIM1_DACTRG3 DAC_TRIGGER_HRTIM1_DACTRG2 /*!< HRTIM1 DACTRG3 selected as external conversion trigger for DAC channel (DAC2)*/
+
+#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
+
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
+ ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_HRTIM1_DACTRG2) || \
+ ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
+ ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
+
+#endif /* STM32F334x8 */
+
+/**
+ * @}
+ */
+
+/** @defgroup DACEx_Channel_selection DACEx Channel selection
+ * @{
+ */
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define DAC_CHANNEL_1 (0x00000000U) /*!< DAC Channel 1U */
+
+#endif /* STM32F302xE || */
+ /* STM32F302xC || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+#define DAC_CHANNEL_1 (0x00000000U) /*!< DAC Channel 1U */
+#define DAC_CHANNEL_2 (0x00000010U) /*!< DAC Channel 2U */
+
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+
+#define DAC_CHANNEL_1 (0x00000000U) /*!< DAC Channel 1U */
+#define DAC_CHANNEL_2 (0x00000010U) /*!< DAC Channel 2U */
+
+#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F373xC || STM32F378xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+
+/** @defgroup DACEx_Private_Macros DACEx Private Macros
+ * @{
+ */
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+
+#define IS_DAC_CHANNEL(CHANNEL) ((CHANNEL) == DAC_CHANNEL_1)
+#endif /* STM32F302xE || */
+ /* STM32F302xC || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
+ ((CHANNEL) == DAC_CHANNEL_2))
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
+ ((CHANNEL) == DAC_CHANNEL_2))
+#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F373xC || STM32F378xx */
+
+
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup DACEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DACEx_Exported_Functions_Group2
+ * @{
+ */
+/* IO operation functions *****************************************************/
+
+uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
+HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
+HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
+HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
+void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
+void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac);
+void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac);
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F373xC || STM32F378xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_HAL_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_hal_def.h b/Inc/stm32f3xx_hal_def.h
new file mode 100644
index 0000000..32875cc
--- /dev/null
+++ b/Inc/stm32f3xx_hal_def.h
@@ -0,0 +1,181 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_def.h
+ * @author MCD Application Team
+ * @brief This file contains HAL common defines, enumeration, macros and
+ * structures definitions.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_DEF
+#define __STM32F3xx_HAL_DEF
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx.h"
+#if defined USE_LEGACY
+#include "Legacy/stm32_hal_legacy.h"
+#endif
+#include <stdio.h>
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief HAL Status structures definition
+ */
+typedef enum
+{
+ HAL_OK = 0x00U,
+ HAL_ERROR = 0x01U,
+ HAL_BUSY = 0x02U,
+ HAL_TIMEOUT = 0x03
+} HAL_StatusTypeDef;
+
+/**
+ * @brief HAL Lock structures definition
+ */
+typedef enum
+{
+ HAL_UNLOCKED = 0x00U,
+ HAL_LOCKED = 0x01
+} HAL_LockTypeDef;
+
+/* Exported macro ------------------------------------------------------------*/
+
+#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
+
+#define HAL_MAX_DELAY 0xFFFFFFFFU
+
+#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == BIT)
+#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
+
+#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD_, __DMA_HANDLE_) \
+ do{ \
+ (__HANDLE__)->__PPP_DMA_FIELD_ = &(__DMA_HANDLE_); \
+ (__DMA_HANDLE_).Parent = (__HANDLE__); \
+ } while(0U)
+
+/** @brief Reset the Handle's State field.
+ * @param __HANDLE__ specifies the Peripheral Handle.
+ * @note This macro can be used for the following purpose:
+ * - When the Handle is declared as local variable; before passing it as parameter
+ * to HAL_PPP_Init() for the first time, it is mandatory to use this macro
+ * to set to 0 the Handle's "State" field.
+ * Otherwise, "State" field may have any random value and the first time the function
+ * HAL_PPP_Init() is called, the low level hardware initialization will be missed
+ * (i.e. HAL_PPP_MspInit() will not be executed).
+ * - When there is a need to reconfigure the low level hardware: instead of calling
+ * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
+ * In this later function, when the Handle's "State" field is set to 0, it will execute the function
+ * HAL_PPP_MspInit() which will reconfigure the low level hardware.
+ * @retval None
+ */
+#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
+
+#if (USE_RTOS == 1U)
+ #error " USE_RTOS should be 0 in the current HAL release "
+#else
+ #define __HAL_LOCK(__HANDLE__) \
+ do{ \
+ if((__HANDLE__)->Lock == HAL_LOCKED) \
+ { \
+ return HAL_BUSY; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Lock = HAL_LOCKED; \
+ } \
+ }while (0U)
+
+ #define __HAL_UNLOCK(__HANDLE__) \
+ do{ \
+ (__HANDLE__)->Lock = HAL_UNLOCKED; \
+ }while (0U)
+#endif /* USE_RTOS */
+
+#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
+ #ifndef __weak
+ #define __weak __attribute__((weak))
+ #endif /* __weak */
+ #ifndef __packed
+ #define __packed __attribute__((__packed__))
+ #endif /* __packed */
+#endif /* __GNUC__ */
+
+
+/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
+#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
+ #ifndef __ALIGN_END
+ #define __ALIGN_END __attribute__ ((aligned (4)))
+ #endif /* __ALIGN_END */
+ #ifndef __ALIGN_BEGIN
+ #define __ALIGN_BEGIN
+ #endif /* __ALIGN_BEGIN */
+#else
+ #ifndef __ALIGN_END
+ #define __ALIGN_END
+ #endif /* __ALIGN_END */
+ #ifndef __ALIGN_BEGIN
+ #if defined (__CC_ARM) /* ARM Compiler */
+ #define __ALIGN_BEGIN __align(4)
+ #elif defined (__ICCARM__) /* IAR Compiler */
+ #define __ALIGN_BEGIN
+ #endif /* __CC_ARM */
+ #endif /* __ALIGN_BEGIN */
+#endif /* __GNUC__ */
+
+/**
+ * @brief __NOINLINE definition
+ */
+#if defined ( __CC_ARM ) || defined ( __GNUC__ )
+/* ARM & GNUCompiler
+ ----------------
+*/
+#define __NOINLINE __attribute__ ( (noinline) )
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler
+ ---------------
+*/
+#define __NOINLINE _Pragma("optimize = no_inline")
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ___STM32F3xx_HAL_DEF */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_hal_dma.h b/Inc/stm32f3xx_hal_dma.h
new file mode 100644
index 0000000..c755e4f
--- /dev/null
+++ b/Inc/stm32f3xx_hal_dma.h
@@ -0,0 +1,470 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_dma.h
+ * @author MCD Application Team
+ * @brief Header file of DMA HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_DMA_H
+#define __STM32F3xx_HAL_DMA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DMA
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Types DMA Exported Types
+ * @{
+ */
+
+/**
+ * @brief DMA Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
+ from memory to memory or from peripheral to memory.
+ This parameter can be a value of @ref DMA_Data_transfer_direction */
+
+ uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
+ This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
+
+ uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
+ This parameter can be a value of @ref DMA_Memory_incremented_mode */
+
+ uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
+ This parameter can be a value of @ref DMA_Peripheral_data_size */
+
+ uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
+ This parameter can be a value of @ref DMA_Memory_data_size */
+
+ uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
+ This parameter can be a value of @ref DMA_mode
+ @note The circular buffer mode cannot be used if the memory-to-memory
+ data transfer is configured on the selected Channel */
+
+ uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
+ This parameter can be a value of @ref DMA_Priority_level */
+} DMA_InitTypeDef;
+
+/**
+ * @brief HAL DMA State structures definition
+ */
+typedef enum
+{
+ HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
+ HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
+ HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
+ HAL_DMA_STATE_TIMEOUT = 0x03 /*!< DMA timeout state */
+}HAL_DMA_StateTypeDef;
+
+/**
+ * @brief HAL DMA Error Code structure definition
+ */
+typedef enum
+{
+ HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
+ HAL_DMA_HALF_TRANSFER = 0x01 /*!< Half Transfer */
+}HAL_DMA_LevelCompleteTypeDef;
+
+/**
+ * @brief HAL DMA Callback ID structure definition
+ */
+typedef enum
+{
+ HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
+ HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */
+ HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */
+ HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */
+ HAL_DMA_XFER_ALL_CB_ID = 0x04 /*!< All */
+}HAL_DMA_CallbackIDTypeDef;
+
+/**
+ * @brief DMA handle Structure definition
+ */
+typedef struct __DMA_HandleTypeDef
+{
+ DMA_Channel_TypeDef *Instance; /*!< Register base address */
+
+ DMA_InitTypeDef Init; /*!< DMA communication parameters */
+
+ HAL_LockTypeDef Lock; /*!< DMA locking object */
+
+ HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
+
+ void *Parent; /*!< Parent object state */
+
+ void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
+
+ void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
+
+ void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
+
+ void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */
+
+ __IO uint32_t ErrorCode; /*!< DMA Error code */
+
+ DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */
+
+ uint32_t ChannelIndex; /*!< DMA Channel Index */
+} DMA_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Constants DMA Exported Constants
+ * @{
+ */
+
+/** @defgroup DMA_Error_Code DMA Error Code
+ * @{
+ */
+#define HAL_DMA_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_DMA_ERROR_TE (0x00000001U) /*!< Transfer error */
+#define HAL_DMA_ERROR_NO_XFER (0x00000004U) /*!< no ongoin transfer */
+#define HAL_DMA_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
+#define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U) /*!< Not supported mode */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
+ * @{
+ */
+#define DMA_PERIPH_TO_MEMORY (0x00000000U) /*!< Peripheral to memory direction */
+#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
+#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
+ * @{
+ */
+#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
+#define DMA_PINC_DISABLE (0x00000000U) /*!< Peripheral increment mode Disable */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
+ * @{
+ */
+#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
+#define DMA_MINC_DISABLE (0x00000000U) /*!< Memory increment mode Disable */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
+ * @{
+ */
+#define DMA_PDATAALIGN_BYTE (0x00000000U) /*!< Peripheral data alignment : Byte */
+#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */
+#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Memory_data_size DMA Memory data size
+ * @{
+ */
+#define DMA_MDATAALIGN_BYTE (0x00000000U) /*!< Memory data alignment : Byte */
+#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */
+#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_mode DMA mode
+ * @{
+ */
+#define DMA_NORMAL (0x00000000U) /*!< Normal Mode */
+#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Priority_level DMA Priority level
+ * @{
+ */
+#define DMA_PRIORITY_LOW (0x00000000U) /*!< Priority level : Low */
+#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
+#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
+#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
+/**
+ * @}
+ */
+
+
+/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
+ * @{
+ */
+#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
+#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
+#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
+/**
+ * @}
+ */
+
+/** @defgroup DMA_flag_definitions DMA flag definitions
+ * @{
+ */
+#define DMA_FLAG_GL1 (0x00000001U)
+#define DMA_FLAG_TC1 (0x00000002U)
+#define DMA_FLAG_HT1 (0x00000004U)
+#define DMA_FLAG_TE1 (0x00000008U)
+#define DMA_FLAG_GL2 (0x00000010U)
+#define DMA_FLAG_TC2 (0x00000020U)
+#define DMA_FLAG_HT2 (0x00000040U)
+#define DMA_FLAG_TE2 (0x00000080U)
+#define DMA_FLAG_GL3 (0x00000100U)
+#define DMA_FLAG_TC3 (0x00000200U)
+#define DMA_FLAG_HT3 (0x00000400U)
+#define DMA_FLAG_TE3 (0x00000800U)
+#define DMA_FLAG_GL4 (0x00001000U)
+#define DMA_FLAG_TC4 (0x00002000U)
+#define DMA_FLAG_HT4 (0x00004000U)
+#define DMA_FLAG_TE4 (0x00008000U)
+#define DMA_FLAG_GL5 (0x00010000U)
+#define DMA_FLAG_TC5 (0x00020000U)
+#define DMA_FLAG_HT5 (0x00040000U)
+#define DMA_FLAG_TE5 (0x00080000U)
+#define DMA_FLAG_GL6 (0x00100000U)
+#define DMA_FLAG_TC6 (0x00200000U)
+#define DMA_FLAG_HT6 (0x00400000U)
+#define DMA_FLAG_TE6 (0x00800000U)
+#define DMA_FLAG_GL7 (0x01000000U)
+#define DMA_FLAG_TC7 (0x02000000U)
+#define DMA_FLAG_HT7 (0x04000000U)
+#define DMA_FLAG_TE7 (0x08000000U)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DMA_Exported_Macros DMA Exported Macros
+ * @{
+ */
+
+/** @brief Reset DMA handle state
+ * @param __HANDLE__ DMA handle.
+ * @retval None
+ */
+#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
+
+/**
+ * @brief Enable the specified DMA Channel.
+ * @param __HANDLE__ DMA handle
+ * @retval None
+ */
+#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
+
+/**
+ * @brief Disable the specified DMA Channel.
+ * @param __HANDLE__ DMA handle
+ * @retval None
+ */
+#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
+
+
+/* Interrupt & Flag management */
+
+/**
+ * @brief Enables the specified DMA Channel interrupts.
+ * @param __HANDLE__ DMA handle
+ * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_IT_TC: Transfer complete interrupt mask
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask
+ * @arg DMA_IT_TE: Transfer error interrupt mask
+ * @retval None
+ */
+#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
+
+/**
+ * @brief Disables the specified DMA Channel interrupts.
+ * @param __HANDLE__ DMA handle
+ * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_IT_TC: Transfer complete interrupt mask
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask
+ * @arg DMA_IT_TE: Transfer error interrupt mask
+ * @retval None
+ */
+#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
+
+/**
+ * @brief Checks whether the specified DMA Channel interrupt is enabled or disabled.
+ * @param __HANDLE__ DMA handle
+ * @param __INTERRUPT__ specifies the DMA interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg DMA_IT_TC: Transfer complete interrupt mask
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask
+ * @arg DMA_IT_TE: Transfer error interrupt mask
+ * @retval The state of DMA_IT (SET or RESET).
+ */
+#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
+
+/**
+ * @brief Returns the number of remaining data units in the current DMAy Channelx transfer.
+ * @param __HANDLE__ DMA handle
+ *
+ * @retval The number of remaining data units in the current DMA Channel transfer.
+ */
+#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
+
+/**
+ * @}
+ */
+
+/* Include DMA HAL Extended module */
+#include "stm32f3xx_hal_dma_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DMA_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Exported_Functions_Group2 Input and Output operation functions
+ * @{
+ */
+/* Input and Output operation functions *****************************************************/
+HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Exported_Functions_Group3 Peripheral State functions
+ * @{
+ */
+/* Peripheral State and Error functions ***************************************/
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DMA_Private_Macros DMA Private Macros
+ * @brief DMA private macros
+ * @{
+ */
+
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
+
+#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
+ ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
+ ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
+
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
+ ((STATE) == DMA_PINC_DISABLE))
+
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
+ ((STATE) == DMA_MINC_DISABLE))
+
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
+ ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
+ ((SIZE) == DMA_PDATAALIGN_WORD))
+
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
+ ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
+ ((SIZE) == DMA_MDATAALIGN_WORD ))
+
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
+ ((MODE) == DMA_CIRCULAR))
+
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
+ ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
+ ((PRIORITY) == DMA_PRIORITY_HIGH) || \
+ ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_DMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_hal_dma_ex.h b/Inc/stm32f3xx_hal_dma_ex.h
new file mode 100644
index 0000000..409ec13
--- /dev/null
+++ b/Inc/stm32f3xx_hal_dma_ex.h
@@ -0,0 +1,290 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_dma_ex.h
+ * @author MCD Application Team
+ * @brief Header file of DMA HAL extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_DMA_EX_H
+#define __STM32F3xx_HAL_DMA_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DMAEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DMAEx_Exported_Macros DMA Extended Exported Macros
+ * @{
+ */
+/* Interrupt & Flag management */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Returns the current DMA Channel transfer complete flag.
+ * @param __HANDLE__ DMA handle
+ * @retval The specified transfer complete flag index.
+ */
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
+ DMA_FLAG_TC5)
+
+/**
+ * @brief Returns the current DMA Channel half transfer complete flag.
+ * @param __HANDLE__ DMA handle
+ * @retval The specified half transfer complete flag index.
+ */
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
+ DMA_FLAG_HT5)
+
+/**
+ * @brief Returns the current DMA Channel transfer error flag.
+ * @param __HANDLE__ DMA handle
+ * @retval The specified transfer error flag index.
+ */
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
+ DMA_FLAG_TE5)
+
+/**
+ * @brief Return the current DMA Channel Global interrupt flag.
+ * @param __HANDLE__ DMA handle
+ * @retval The specified transfer error flag index.
+ */
+#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_GL7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GL1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GL2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GL3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GL4 :\
+ DMA_FLAG_GL5)
+
+/**
+ * @brief Get the DMA Channel pending flags.
+ * @param __HANDLE__ DMA handle
+ * @param __FLAG__ Get the specified flag.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_FLAG_TCx: Transfer complete flag
+ * @arg DMA_FLAG_HTx: Half transfer complete flag
+ * @arg DMA_FLAG_TEx: Transfer error flag
+ * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
+ * @retval The state of FLAG (SET or RESET).
+ */
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\
+ (DMA1->ISR & (__FLAG__)))
+
+/**
+ * @brief Clears the DMA Channel pending flags.
+ * @param __HANDLE__ DMA handle
+ * @param __FLAG__ specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_FLAG_TCx: Transfer complete flag
+ * @arg DMA_FLAG_HTx: Half transfer complete flag
+ * @arg DMA_FLAG_TEx: Transfer error flag
+ * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
+ * @retval None
+ */
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\
+ (DMA1->IFCR = (__FLAG__)))
+
+/**
+ * @}
+ */
+
+#else /* STM32F301x8_STM32F302x8_STM32F318xx_STM32F303x8_STM32F334x8_STM32F328xx Product devices */
+/** @defgroup DMA_Low_density_Medium_density_Product_devices DMA Low density and Medium density product devices
+ * @{
+ */
+
+/**
+ * @brief Returns the current DMA Channel transfer complete flag.
+ * @param __HANDLE__ DMA handle
+ * @retval The specified transfer complete flag index.
+ */
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
+ DMA_FLAG_TC7)
+
+/**
+ * @brief Returns the current DMA Channel half transfer complete flag.
+ * @param __HANDLE__ DMA handle
+ * @retval The specified half transfer complete flag index.
+ */
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
+ DMA_FLAG_HT7)
+
+/**
+ * @brief Returns the current DMA Channel transfer error flag.
+ * @param __HANDLE__ DMA handle
+ * @retval The specified transfer error flag index.
+ */
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
+ DMA_FLAG_TE7)
+
+/**
+ * @brief Return the current DMA Channel Global interrupt flag.
+ * @param __HANDLE__ DMA handle
+ * @retval The specified transfer error flag index.
+ */
+#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
+ DMA_FLAG_GL7)
+
+/**
+ * @brief Get the DMA Channel pending flags.
+ * @param __HANDLE__ DMA handle
+ * @param __FLAG__ Get the specified flag.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_FLAG_TCx: Transfer complete flag
+ * @arg DMA_FLAG_HTx: Half transfer complete flag
+ * @arg DMA_FLAG_TEx: Transfer error flag
+ * Where x can be 1_7 to select the DMA Channel flag.
+ * @retval The state of FLAG (SET or RESET).
+ */
+
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
+
+/**
+ * @brief Clears the DMA Channel pending flags.
+ * @param __HANDLE__ DMA handle
+ * @param __FLAG__ specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_FLAG_TCx: Transfer complete flag
+ * @arg DMA_FLAG_HTx: Half transfer complete flag
+ * @arg DMA_FLAG_TEx: Transfer error flag
+ * Where x can be 1_7 to select the DMA Channel flag.
+ * @retval None
+ */
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F373xC || STM32F378xx */
+
+#endif /* __STM32F3xx_HAL_DMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_hal_flash.h b/Inc/stm32f3xx_hal_flash.h
new file mode 100644
index 0000000..12a5e6f
--- /dev/null
+++ b/Inc/stm32f3xx_hal_flash.h
@@ -0,0 +1,397 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_flash.h
+ * @author MCD Application Team
+ * @brief Header file of Flash HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_FLASH_H
+#define __STM32F3xx_HAL_FLASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FLASH
+ * @{
+ */
+
+/** @addtogroup FLASH_Private_Constants
+ * @{
+ */
+#define FLASH_TIMEOUT_VALUE (50000U) /* 50 s */
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Private_Macros
+ * @{
+ */
+
+#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \
+ ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \
+ ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))
+
+#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \
+ ((__LATENCY__) == FLASH_LATENCY_1) || \
+ ((__LATENCY__) == FLASH_LATENCY_2))
+
+/**
+ * @}
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Types FLASH Exported Types
+ * @{
+ */
+
+/**
+ * @brief FLASH Procedure structure definition
+ */
+typedef enum
+{
+ FLASH_PROC_NONE = 0U,
+ FLASH_PROC_PAGEERASE = 1U,
+ FLASH_PROC_MASSERASE = 2U,
+ FLASH_PROC_PROGRAMHALFWORD = 3U,
+ FLASH_PROC_PROGRAMWORD = 4U,
+ FLASH_PROC_PROGRAMDOUBLEWORD = 5U
+} FLASH_ProcedureTypeDef;
+
+/**
+ * @brief FLASH handle Structure definition
+ */
+typedef struct
+{
+ __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */
+
+ __IO uint32_t DataRemaining; /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */
+
+ __IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */
+
+ __IO uint64_t Data; /*!< Internal variable to save data to be programmed */
+
+ HAL_LockTypeDef Lock; /*!< FLASH locking object */
+
+ __IO uint32_t ErrorCode; /*!< FLASH error code
+ This parameter can be a value of @ref FLASH_Error_Codes */
+} FLASH_ProcessTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
+ * @{
+ */
+
+/** @defgroup FLASH_Error_Codes FLASH Error Codes
+ * @{
+ */
+
+#define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */
+#define HAL_FLASH_ERROR_PROG 0x01U /*!< Programming error */
+#define HAL_FLASH_ERROR_WRP 0x02U /*!< Write protection error */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Type_Program FLASH Type Program
+ * @{
+ */
+#define FLASH_TYPEPROGRAM_HALFWORD (0x01U) /*!<Program a half-word (16-bit) at a specified address.*/
+#define FLASH_TYPEPROGRAM_WORD (0x02U) /*!<Program a word (32-bit) at a specified address.*/
+#define FLASH_TYPEPROGRAM_DOUBLEWORD (0x03U) /*!<Program a double word (64-bit) at a specified address*/
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Latency FLASH Latency
+ * @{
+ */
+#define FLASH_LATENCY_0 (0x00000000U) /*!< FLASH Zero Latency cycle */
+#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */
+#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two Latency cycles */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup FLASH_Flag_definition FLASH Flag definition
+ * @{
+ */
+#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
+#define FLASH_FLAG_PGERR FLASH_SR_PGERR /*!< FLASH Programming error flag */
+#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */
+#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Operation flag */
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition
+ * @{
+ */
+#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */
+#define FLASH_IT_ERR FLASH_CR_ERRIE /*!< Error Interrupt source */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
+ * @brief macros to control FLASH features
+ * @{
+ */
+
+/** @defgroup FLASH_Half_Cycle FLASH Half Cycle
+ * @brief macros to handle FLASH half cycle
+ * @{
+ */
+
+/**
+ * @brief Enable the FLASH half cycle access.
+ * @retval None
+ */
+#define __HAL_FLASH_HALF_CYCLE_ACCESS_ENABLE() (FLASH->ACR |= FLASH_ACR_HLFCYA)
+
+/**
+ * @brief Disable the FLASH half cycle access.
+ * @retval None
+ */
+#define __HAL_FLASH_HALF_CYCLE_ACCESS_DISABLE() (FLASH->ACR &= (~FLASH_ACR_HLFCYA))
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_EM_Latency FLASH Latency
+ * @brief macros to handle FLASH Latency
+ * @{
+ */
+
+/**
+ * @brief Set the FLASH Latency.
+ * @param __LATENCY__ FLASH Latency
+ * This parameter can be one of the following values:
+ * @arg @ref FLASH_LATENCY_0 FLASH Zero Latency cycle
+ * @arg @ref FLASH_LATENCY_1 FLASH One Latency cycle
+ * @arg @ref FLASH_LATENCY_2 FLASH Two Latency cycles
+ * @retval None
+ */
+#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__))
+
+
+/**
+ * @brief Get the FLASH Latency.
+ * @retval FLASH Latency
+ * This parameter can be one of the following values:
+ * @arg @ref FLASH_LATENCY_0 FLASH Zero Latency cycle
+ * @arg @ref FLASH_LATENCY_1 FLASH One Latency cycle
+ * @arg @ref FLASH_LATENCY_2 FLASH Two Latency cycles
+ */
+#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Prefetch FLASH Prefetch
+ * @brief macros to handle FLASH Prefetch buffer
+ * @{
+ */
+/**
+ * @brief Enable the FLASH prefetch buffer.
+ * @retval None
+ */
+#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE)
+
+/**
+ * @brief Disable the FLASH prefetch buffer.
+ * @retval None
+ */
+#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTBE))
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Interrupt FLASH Interrupts
+ * @brief macros to handle FLASH interrupts
+ * @{
+ */
+
+/**
+ * @brief Enable the specified FLASH interrupt.
+ * @param __INTERRUPT__ FLASH interrupt
+ * This parameter can be any combination of the following values:
+ * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
+ * @arg @ref FLASH_IT_ERR Error Interrupt
+ * @retval none
+ */
+#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) SET_BIT((FLASH->CR), (__INTERRUPT__))
+
+/**
+ * @brief Disable the specified FLASH interrupt.
+ * @param __INTERRUPT__ FLASH interrupt
+ * This parameter can be any combination of the following values:
+ * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
+ * @arg @ref FLASH_IT_ERR Error Interrupt
+ * @retval none
+ */
+#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT((FLASH->CR), (uint32_t)(__INTERRUPT__))
+
+/**
+ * @brief Get the specified FLASH flag status.
+ * @param __FLAG__ specifies the FLASH flag to check.
+ * This parameter can be one of the following values:
+ * @arg @ref FLASH_FLAG_BSY FLASH Busy flag
+ * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag
+ * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag
+ * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag
+ * @retval The new state of __FLAG__ (SET or RESET).
+ */
+#define __HAL_FLASH_GET_FLAG(__FLAG__) (((FLASH->SR) & (__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Clear the specified FLASH flag.
+ * @param __FLAG__ specifies the FLASH flags to clear.
+ * This parameter can be any combination of the following values:
+ * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag
+ * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag
+ * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag
+ * @retval none
+ */
+#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) ((FLASH->SR) = (__FLAG__))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Include FLASH HAL Extended module */
+#include "stm32f3xx_hal_flash_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASH_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup FLASH_Exported_Functions_Group1
+ * @{
+ */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
+
+/* FLASH IRQ handler function */
+void HAL_FLASH_IRQHandler(void);
+/* Callbacks in non blocking modes */
+void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
+void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Exported_Functions_Group2
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_FLASH_Unlock(void);
+HAL_StatusTypeDef HAL_FLASH_Lock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral State and Error functions ***************************************/
+uint32_t HAL_FLASH_GetError(void);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private function -------------------------------------------------*/
+/** @addtogroup FLASH_Private_Functions
+ * @{
+ */
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_FLASH_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Inc/stm32f3xx_hal_flash_ex.h b/Inc/stm32f3xx_hal_flash_ex.h
new file mode 100644
index 0000000..e462580
--- /dev/null
+++ b/Inc/stm32f3xx_hal_flash_ex.h
@@ -0,0 +1,498 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_flash_ex.h
+ * @author MCD Application Team
+ * @brief Header file of Flash HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_FLASH_EX_H
+#define __STM32F3xx_HAL_FLASH_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FLASHEx
+ * @{
+ */
+
+/** @addtogroup FLASHEx_Private_Constants
+ * @{
+ */
+
+#define FLASH_SIZE_DATA_REGISTER (0x1FFFF7CCU)
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASHEx_Private_Macros
+ * @{
+ */
+#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \
+ ((VALUE) == FLASH_TYPEERASE_MASSERASE))
+
+#define IS_OPTIONBYTE(VALUE) ((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA))
+
+#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || \
+ ((VALUE) == OB_WRPSTATE_ENABLE))
+
+#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1))
+
+#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
+ ((LEVEL) == OB_RDP_LEVEL_1))/*||\
+ ((LEVEL) == OB_RDP_LEVEL_2))*/
+
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
+
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
+
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
+
+#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))
+
+#define IS_OB_VDDA_ANALOG(ANALOG) (((ANALOG) == OB_VDDA_ANALOG_ON) || ((ANALOG) == OB_VDDA_ANALOG_OFF))
+
+#define IS_OB_SRAM_PARITY(PARITY) (((PARITY) == OB_SRAM_PARITY_SET) || ((PARITY) == OB_SRAM_PARITY_RESET))
+
+
+#if defined(FLASH_OBR_SDADC12_VDD_MONITOR)
+#define IS_OB_SDACD_VDD_MONITOR(VDD_MONITOR) (((VDD_MONITOR) == OB_SDACD_VDD_MONITOR_SET) || \
+ ((VDD_MONITOR) == OB_SDACD_VDD_MONITOR_RESET))
+#endif /* FLASH_OBR_SDADC12_VDD_MONITOR */
+
+#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000U))
+
+#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) \
+ || defined(STM32F373xC) || defined(STM32F378xx)
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? \
+ ((ADDRESS) <= 0x0803FFFFU) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? \
+ ((ADDRESS) <= 0x0801FFFFU) : ((ADDRESS) <= 0x0800FFFFU))))
+#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= 0x0807FFFFU))
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) \
+ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? \
+ ((ADDRESS) <= 0x0800FFFFU) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? \
+ ((ADDRESS) <= 0x08007FFFU) : ((ADDRESS) <= 0x08003FFFU))))
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) \
+ || defined(STM32F373xC) || defined(STM32F378xx)
+#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x0803FFFFU) : \
+ (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x0801FFFFU) : \
+ ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x0800FFFFU)))
+#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x0807FFFFU)
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) \
+ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x0800FFFFU) : \
+ (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x08007FFFU) : \
+ ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x08003FFFU)))
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+/**
+ * @}
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types
+ * @{
+ */
+/**
+ * @brief FLASH Erase structure definition
+ */
+typedef struct
+{
+ uint32_t TypeErase; /*!< TypeErase: Mass erase or page erase.
+ This parameter can be a value of @ref FLASHEx_Type_Erase */
+
+ uint32_t PageAddress; /*!< PageAdress: Initial FLASH page address to erase when mass erase is disabled
+ This parameter must be a number between Min_Data = FLASH_BASE and Max_Data = FLASH_BANK1_END */
+
+ uint32_t NbPages; /*!< NbPages: Number of pagess to be erased.
+ This parameter must be a value between Min_Data = 1 and Max_Data = (max number of pages - value of initial page)*/
+
+} FLASH_EraseInitTypeDef;
+
+/**
+ * @brief FLASH Options bytes program structure definition
+ */
+typedef struct
+{
+ uint32_t OptionType; /*!< OptionType: Option byte to be configured.
+ This parameter can be a value of @ref FLASHEx_OB_Type */
+
+ uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation.
+ This parameter can be a value of @ref FLASHEx_OB_WRP_State */
+
+ uint32_t WRPPage; /*!< WRPPage: specifies the page(s) to be write protected
+ This parameter can be a value of @ref FLASHEx_OB_Write_Protection */
+
+ uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level..
+ This parameter can be a value of @ref FLASHEx_OB_Read_Protection */
+
+ uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte:
+ IWDG / STOP / STDBY / BOOT1 / VDDA_ANALOG / SRAM_PARITY / SDADC12_VDD_MONITOR
+ This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP,
+ @ref FLASHEx_OB_nRST_STDBY, @ref FLASHEx_OB_BOOT1, @ref FLASHEx_OB_VDDA_Analog_Monitoring,
+ @ref FLASHEx_OB_RAM_Parity_Check_Enable.
+ @if STM32F373xC
+ And @ref FLASHEx_OB_SDADC12_VDD_MONITOR (only for STM32F373xC & STM32F378xx devices)
+ @endif
+ @if STM32F378xx
+ And @ref FLASHEx_OB_SDADC12_VDD_MONITOR (only for STM32F373xC & STM32F378xx devices)
+ @endif
+ */
+
+ uint32_t DATAAddress; /*!< DATAAddress: Address of the option byte DATA to be programmed
+ This parameter can be a value of @ref FLASHEx_OB_Data_Address */
+
+ uint8_t DATAData; /*!< DATAData: Data to be stored in the option byte DATA
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFU */
+} FLASH_OBProgramInitTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants
+ * @{
+ */
+
+/** @defgroup FLASHEx_Page_Size FLASHEx Page Size
+ * @{
+ */
+#define FLASH_PAGE_SIZE 0x800
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Type_Erase FLASH Type Erase
+ * @{
+ */
+#define FLASH_TYPEERASE_PAGES (0x00U) /*!<Pages erase only*/
+#define FLASH_TYPEERASE_MASSERASE (0x01U) /*!<Flash mass erase activation*/
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_OptionByte_Constants Option Byte Constants
+ * @{
+ */
+
+/** @defgroup FLASHEx_OB_Type Option Bytes Type
+ * @{
+ */
+#define OPTIONBYTE_WRP (0x01U) /*!<WRP option byte configuration*/
+#define OPTIONBYTE_RDP (0x02U) /*!<RDP option byte configuration*/
+#define OPTIONBYTE_USER (0x04U) /*!<USER option byte configuration*/
+#define OPTIONBYTE_DATA (0x08U) /*!<DATA option byte configuration*/
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_OB_WRP_State Option Byte WRP State
+ * @{
+ */
+#define OB_WRPSTATE_DISABLE (0x00U) /*!<Disable the write protection of the desired pages*/
+#define OB_WRPSTATE_ENABLE (0x01U) /*!<Enable the write protection of the desired pagess*/
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_OB_Write_Protection FLASHEx OB Write Protection
+ * @{
+ */
+#define OB_WRP_PAGES0TO1 (0x00000001U) /* Write protection of page 0 to 1 */
+#define OB_WRP_PAGES2TO3 (0x00000002U) /* Write protection of page 2 to 3 */
+#define OB_WRP_PAGES4TO5 (0x00000004U) /* Write protection of page 4 to 5 */
+#define OB_WRP_PAGES6TO7 (0x00000008U) /* Write protection of page 6 to 7 */
+#define OB_WRP_PAGES8TO9 (0x00000010U) /* Write protection of page 8 to 9 */
+#define OB_WRP_PAGES10TO11 (0x00000020U) /* Write protection of page 10 to 11 */
+#define OB_WRP_PAGES12TO13 (0x00000040U) /* Write protection of page 12 to 13 */
+#define OB_WRP_PAGES14TO15 (0x00000080U) /* Write protection of page 14 to 15 */
+#define OB_WRP_PAGES16TO17 (0x00000100U) /* Write protection of page 16 to 17 */
+#define OB_WRP_PAGES18TO19 (0x00000200U) /* Write protection of page 18 to 19 */
+#define OB_WRP_PAGES20TO21 (0x00000400U) /* Write protection of page 20 to 21 */
+#define OB_WRP_PAGES22TO23 (0x00000800U) /* Write protection of page 22 to 23 */
+#define OB_WRP_PAGES24TO25 (0x00001000U) /* Write protection of page 24 to 25 */
+#define OB_WRP_PAGES26TO27 (0x00002000U) /* Write protection of page 26 to 27 */
+#define OB_WRP_PAGES28TO29 (0x00004000U) /* Write protection of page 28 to 29 */
+#define OB_WRP_PAGES30TO31 (0x00008000U) /* Write protection of page 30 to 31 */
+
+#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) \
+ || defined(STM32F373xC) || defined(STM32F378xx)
+#define OB_WRP_PAGES32TO33 (0x00010000U) /* Write protection of page 32 to 33 */
+#define OB_WRP_PAGES34TO35 (0x00020000U) /* Write protection of page 34 to 35 */
+#define OB_WRP_PAGES36TO37 (0x00040000U) /* Write protection of page 36 to 37 */
+#define OB_WRP_PAGES38TO39 (0x00080000U) /* Write protection of page 38 to 39 */
+#define OB_WRP_PAGES40TO41 (0x00100000U) /* Write protection of page 40 to 41 */
+#define OB_WRP_PAGES42TO43 (0x00200000U) /* Write protection of page 42 to 43 */
+#define OB_WRP_PAGES44TO45 (0x00400000U) /* Write protection of page 44 to 45 */
+#define OB_WRP_PAGES46TO47 (0x00800000U) /* Write protection of page 46 to 47 */
+#define OB_WRP_PAGES48TO49 (0x01000000U) /* Write protection of page 48 to 49 */
+#define OB_WRP_PAGES50TO51 (0x02000000U) /* Write protection of page 50 to 51 */
+#define OB_WRP_PAGES52TO53 (0x04000000U) /* Write protection of page 52 to 53 */
+#define OB_WRP_PAGES54TO55 (0x08000000U) /* Write protection of page 54 to 55 */
+#define OB_WRP_PAGES56TO57 (0x10000000U) /* Write protection of page 56 to 57 */
+#define OB_WRP_PAGES58TO59 (0x20000000U) /* Write protection of page 58 to 59 */
+#define OB_WRP_PAGES60TO61 (0x40000000U) /* Write protection of page 60 to 61 */
+#define OB_WRP_PAGES62TO127 (0x80000000U) /* Write protection of page 62 to 127 */
+#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+#define OB_WRP_PAGES32TO33 (0x00010000U) /* Write protection of page 32 to 33 */
+#define OB_WRP_PAGES34TO35 (0x00020000U) /* Write protection of page 34 to 35 */
+#define OB_WRP_PAGES36TO37 (0x00040000U) /* Write protection of page 36 to 37 */
+#define OB_WRP_PAGES38TO39 (0x00080000U) /* Write protection of page 38 to 39 */
+#define OB_WRP_PAGES40TO41 (0x00100000U) /* Write protection of page 40 to 41 */
+#define OB_WRP_PAGES42TO43 (0x00200000U) /* Write protection of page 42 to 43 */
+#define OB_WRP_PAGES44TO45 (0x00400000U) /* Write protection of page 44 to 45 */
+#define OB_WRP_PAGES46TO47 (0x00800000U) /* Write protection of page 46 to 47 */
+#define OB_WRP_PAGES48TO49 (0x01000000U) /* Write protection of page 48 to 49 */
+#define OB_WRP_PAGES50TO51 (0x02000000U) /* Write protection of page 50 to 51 */
+#define OB_WRP_PAGES52TO53 (0x04000000U) /* Write protection of page 52 to 53 */
+#define OB_WRP_PAGES54TO55 (0x08000000U) /* Write protection of page 54 to 55 */
+#define OB_WRP_PAGES56TO57 (0x10000000U) /* Write protection of page 56 to 57 */
+#define OB_WRP_PAGES58TO59 (0x20000000U) /* Write protection of page 58 to 59 */
+#define OB_WRP_PAGES60TO61 (0x40000000U) /* Write protection of page 60 to 61 */
+#define OB_WRP_PAGES62TO255 (0x80000000U) /* Write protection of page 62 to 255 */
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+
+#define OB_WRP_PAGES0TO15MASK (0x000000FFU)
+#define OB_WRP_PAGES16TO31MASK (0x0000FF00U)
+
+#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) \
+ || defined(STM32F373xC) || defined(STM32F378xx)
+#define OB_WRP_PAGES32TO47MASK (0x00FF0000U)
+#define OB_WRP_PAGES48TO127MASK (0xFF000000U)
+#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+#define OB_WRP_PAGES32TO47MASK (0x00FF0000U)
+#define OB_WRP_PAGES48TO255MASK (0xFF000000U)
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+
+#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) \
+ || defined(STM32F373xC) || defined(STM32F378xx)
+#define OB_WRP_PAGES32TO47MASK (0x00FF0000U)
+#define OB_WRP_PAGES48TO127MASK (0xFF000000U)
+#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) \
+ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) \
+ || defined(STM32F373xC) || defined(STM32F378xx)
+#define OB_WRP_ALLPAGES (0xFFFFFFFFU) /*!< Write protection of all pages */
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) \
+ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define OB_WRP_ALLPAGES (0x0000FFFFU) /*!< Write protection of all pages */
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_OB_Read_Protection Option Byte Read Protection
+ * @{
+ */
+#define OB_RDP_LEVEL_0 ((uint8_t)0xAAU)
+#define OB_RDP_LEVEL_1 ((uint8_t)0xBBU)
+#define OB_RDP_LEVEL_2 ((uint8_t)0xCCU) /*!< Warning: When enabling read protection level 2
+ it's no more possible to go back to level 1 or 0U */
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_OB_IWatchdog Option Byte IWatchdog
+ * @{
+ */
+#define OB_IWDG_SW ((uint8_t)0x01U) /*!< Software IWDG selected */
+#define OB_IWDG_HW ((uint8_t)0x00U) /*!< Hardware IWDG selected */
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_OB_nRST_STOP Option Byte nRST STOP
+ * @{
+ */
+#define OB_STOP_NO_RST ((uint8_t)0x02U) /*!< No reset generated when entering in STOP */
+#define OB_STOP_RST ((uint8_t)0x00U) /*!< Reset generated when entering in STOP */
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_OB_nRST_STDBY Option Byte nRST STDBY
+ * @{
+ */
+#define OB_STDBY_NO_RST ((uint8_t)0x04U) /*!< No reset generated when entering in STANDBY */
+#define OB_STDBY_RST ((uint8_t)0x00U) /*!< Reset generated when entering in STANDBY */
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_OB_BOOT1 Option Byte BOOT1
+ * @{
+ */
+#define OB_BOOT1_RESET ((uint8_t)0x00U) /*!< BOOT1 Reset */
+#define OB_BOOT1_SET ((uint8_t)0x10U) /*!< BOOT1 Set */
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_OB_VDDA_Analog_Monitoring Option Byte VDDA Analog Monitoring
+ * @{
+ */
+#define OB_VDDA_ANALOG_ON ((uint8_t)0x20U) /*!< Analog monitoring on VDDA Power source ON */
+#define OB_VDDA_ANALOG_OFF ((uint8_t)0x00U) /*!< Analog monitoring on VDDA Power source OFF */
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_OB_RAM_Parity_Check_Enable Option Byte SRAM Parity Check Enable
+ * @{
+ */
+#define OB_SRAM_PARITY_SET ((uint8_t)0x00U) /*!< SRAM parity check enable set */
+#define OB_SRAM_PARITY_RESET ((uint8_t)0x40U) /*!< SRAM parity check enable reset */
+/**
+ * @}
+ */
+
+
+#if defined(FLASH_OBR_SDADC12_VDD_MONITOR)
+/** @defgroup FLASHEx_OB_SDADC12_VDD_MONITOR OB SDADC12 VDD MONITOR
+ * @{
+ */
+#define OB_SDACD_VDD_MONITOR_RESET ((uint8_t)0x00U) /*!< SDADC VDD Monitor reset */
+#define OB_SDACD_VDD_MONITOR_SET ((uint8_t)0x80U) /*!< SDADC VDD Monitor set */
+
+/**
+ * @}
+ */
+#endif /* FLASH_OBR_SDADC12_VDD_MONITOR */
+
+/** @defgroup FLASHEx_OB_Data_Address Option Byte Data Address
+ * @{
+ */
+#define OB_DATA_ADDRESS_DATA0 (0x1FFFF804U)
+#define OB_DATA_ADDRESS_DATA1 (0x1FFFF806U)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASHEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup FLASHEx_Exported_Functions_Group1
+ * @{
+ */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASHEx_Exported_Functions_Group2
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_FLASHEx_OBErase(void);
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
+void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
+uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_FLASH_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Inc/stm32f3xx_hal_gpio.h b/Inc/stm32f3xx_hal_gpio.h
new file mode 100644
index 0000000..4f6b2d8
--- /dev/null
+++ b/Inc/stm32f3xx_hal_gpio.h
@@ -0,0 +1,313 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_gpio.h
+ * @author MCD Application Team
+ * @brief Header file of GPIO HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_GPIO_H
+#define __STM32F3xx_HAL_GPIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup GPIO
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Types GPIO Exported Types
+ * @{
+ */
+/**
+ * @brief GPIO Init structure definition
+ */
+typedef struct
+{
+ uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
+ This parameter can be any value of @ref GPIO_pins */
+
+ uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
+ This parameter can be a value of @ref GPIO_mode */
+
+ uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
+ This parameter can be a value of @ref GPIO_pull */
+
+ uint32_t Speed; /*!< Specifies the speed for the selected pins.
+ This parameter can be a value of @ref GPIO_speed */
+
+ uint32_t Alternate; /*!< Peripheral to be connected to the selected pins
+ This parameter can be a value of @ref GPIOEx_Alternate_function_selection */
+}GPIO_InitTypeDef;
+
+/**
+ * @brief GPIO Bit SET and Bit RESET enumeration
+ */
+typedef enum
+{
+ GPIO_PIN_RESET = 0U,
+ GPIO_PIN_SET
+}GPIO_PinState;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
+ * @{
+ */
+/** @defgroup GPIO_pins GPIO pins
+ * @{
+ */
+#define GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */
+#define GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */
+#define GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */
+#define GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */
+#define GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */
+#define GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */
+#define GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */
+#define GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */
+#define GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */
+#define GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */
+#define GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */
+#define GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */
+#define GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */
+#define GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */
+#define GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */
+#define GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */
+#define GPIO_PIN_All ((uint16_t)0xFFFFU) /* All pins selected */
+
+#define GPIO_PIN_MASK (0x0000FFFFU) /* PIN mask for assert test */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_mode GPIO mode
+ * @brief GPIO Configuration Mode
+ * Elements values convention: 0xX0yz00YZ
+ * - X : GPIO mode or EXTI Mode
+ * - y : External IT or Event trigger detection
+ * - z : IO configuration on External IT or Event
+ * - Y : Output type (Push Pull or Open Drain)
+ * - Z : IO Direction mode (Input, Output, Alternate or Analog)
+ * @{
+ */
+#define GPIO_MODE_INPUT (0x00000000U) /*!< Input Floating Mode */
+#define GPIO_MODE_OUTPUT_PP (0x00000001U) /*!< Output Push Pull Mode */
+#define GPIO_MODE_OUTPUT_OD (0x00000011U) /*!< Output Open Drain Mode */
+#define GPIO_MODE_AF_PP (0x00000002U) /*!< Alternate Function Push Pull Mode */
+#define GPIO_MODE_AF_OD (0x00000012U) /*!< Alternate Function Open Drain Mode */
+#define GPIO_MODE_ANALOG (0x00000003U) /*!< Analog Mode */
+#define GPIO_MODE_IT_RISING (0x10110000U) /*!< External Interrupt Mode with Rising edge trigger detection */
+#define GPIO_MODE_IT_FALLING (0x10210000U) /*!< External Interrupt Mode with Falling edge trigger detection */
+#define GPIO_MODE_IT_RISING_FALLING (0x10310000U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+#define GPIO_MODE_EVT_RISING (0x10120000U) /*!< External Event Mode with Rising edge trigger detection */
+#define GPIO_MODE_EVT_FALLING (0x10220000U) /*!< External Event Mode with Falling edge trigger detection */
+#define GPIO_MODE_EVT_RISING_FALLING (0x10320000U) /*!< External Event Mode with Rising/Falling edge trigger detection */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_speed GPIO speed
+ * @brief GPIO Output Maximum frequency
+ * @{
+ */
+#define GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< range up to 2 MHz, please refer to the product datasheet */
+#define GPIO_SPEED_FREQ_MEDIUM (0x00000001U) /*!< range 4 MHz to 10 MHz, please refer to the product datasheet */
+#define GPIO_SPEED_FREQ_HIGH (0x00000003U) /*!< range 10 MHz to 50 MHz, please refer to the product datasheet */
+/**
+ * @}
+ */
+
+ /** @defgroup GPIO_pull GPIO pull
+ * @brief GPIO Pull-Up or Pull-Down Activation
+ * @{
+ */
+#define GPIO_NOPULL (0x00000000U) /*!< No Pull-up or Pull-down activation */
+#define GPIO_PULLUP (0x00000001U) /*!< Pull-up activation */
+#define GPIO_PULLDOWN (0x00000002U) /*!< Pull-down activation */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
+ * @{
+ */
+
+/**
+ * @brief Check whether the specified EXTI line flag is set or not.
+ * @param __EXTI_LINE__ specifies the EXTI line flag to check.
+ * This parameter can be GPIO_PIN_x where x can be(0..15)
+ * @retval The new state of __EXTI_LINE__ (SET or RESET).
+ */
+#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
+
+/**
+ * @brief Clear the EXTI's line pending flags.
+ * @param __EXTI_LINE__ specifies the EXTI lines flags to clear.
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+ * @retval None
+ */
+#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
+
+/**
+ * @brief Check whether the specified EXTI line is asserted or not.
+ * @param __EXTI_LINE__ specifies the EXTI line to check.
+ * This parameter can be GPIO_PIN_x where x can be(0..15)
+ * @retval The new state of __EXTI_LINE__ (SET or RESET).
+ */
+#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
+
+/**
+ * @brief Clear the EXTI's line pending bits.
+ * @param __EXTI_LINE__ specifies the EXTI lines to clear.
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+ * @retval None
+ */
+#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
+
+/**
+ * @brief Generate a Software interrupt on selected EXTI line.
+ * @param __EXTI_LINE__ specifies the EXTI line to check.
+ * This parameter can be GPIO_PIN_x where x can be(0..15)
+ * @retval None
+ */
+#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup GPIO_Private_Macros GPIO Private Macros
+ * @{
+ */
+#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
+
+#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
+ (((__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
+
+#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\
+ ((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\
+ ((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\
+ ((__MODE__) == GPIO_MODE_AF_PP) ||\
+ ((__MODE__) == GPIO_MODE_AF_OD) ||\
+ ((__MODE__) == GPIO_MODE_IT_RISING) ||\
+ ((__MODE__) == GPIO_MODE_IT_FALLING) ||\
+ ((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\
+ ((__MODE__) == GPIO_MODE_EVT_RISING) ||\
+ ((__MODE__) == GPIO_MODE_EVT_FALLING) ||\
+ ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\
+ ((__MODE__) == GPIO_MODE_ANALOG))
+
+#define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_FREQ_LOW) ||\
+ ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) ||\
+ ((__SPEED__) == GPIO_SPEED_FREQ_HIGH))
+
+#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) ||\
+ ((__PULL__) == GPIO_PULLUP) || \
+ ((__PULL__) == GPIO_PULLDOWN))
+/**
+ * @}
+ */
+
+/* Include GPIO HAL Extended module */
+#include "stm32f3xx_hal_gpio_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup GPIO_Exported_Functions GPIO Exported Functions
+ * @{
+ */
+
+/** @addtogroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
+ * @brief Initialization and Configuration functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions *****************************/
+void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
+void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
+
+/**
+ * @}
+ */
+
+/** @addtogroup GPIO_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+
+/* IO operation functions *****************************************************/
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
+void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
+void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_GPIO_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_hal_gpio_ex.h b/Inc/stm32f3xx_hal_gpio_ex.h
new file mode 100644
index 0000000..272c8f7
--- /dev/null
+++ b/Inc/stm32f3xx_hal_gpio_ex.h
@@ -0,0 +1,1538 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_gpio_ex.h
+ * @author MCD Application Team
+ * @brief Header file of GPIO HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_GPIO_EX_H
+#define __STM32F3xx_HAL_GPIO_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup GPIOEx GPIOEx
+ * @brief GPIO Extended HAL module driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
+ * @{
+ */
+
+/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection
+ * @{
+ */
+
+#if defined (STM32F302xC)
+/*---------------------------------- STM32F302xC ------------------------------*/
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */
+#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */
+#define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */
+#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /* TIM2 Alternate Function mapping */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF2_COMP1 ((uint8_t)0x02U) /* COMP1 Alternate Function mapping */
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */
+#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /* TIM15 Alternate Function mapping */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_TIM1 ((uint8_t)0x04U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF4_TIM16 ((uint8_t)0x04U) /* TIM16 Alternate Function mapping */
+#define GPIO_AF4_TIM17 ((uint8_t)0x04U) /* TIM17 Alternate Function mapping */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1/I2S1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF5_I2S ((uint8_t)0x05U) /* I2S Alternate Function mapping */
+#define GPIO_AF5_I2S2ext ((uint8_t)0x05U) /* I2S2ext Alternate Function mapping */
+#define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */
+#define GPIO_AF5_UART4 ((uint8_t)0x05U) /* UART4 Alternate Function mapping */
+#define GPIO_AF5_UART5 ((uint8_t)0x05U) /* UART5 Alternate Function mapping */
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_SPI2 ((uint8_t)0x06U) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_I2S3ext ((uint8_t)0x06U) /* I2S3ext Alternate Function mapping */
+#define GPIO_AF6_TIM1 ((uint8_t)0x06U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_COMP6 ((uint8_t)0x07U) /* COMP6 Alternate Function mapping */
+#define GPIO_AF7_CAN ((uint8_t)0x07U) /* CAN Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_COMP1 ((uint8_t)0x08U) /* COMP1 Alternate Function mapping */
+#define GPIO_AF8_COMP2 ((uint8_t)0x08U) /* COMP2 Alternate Function mapping */
+#define GPIO_AF8_COMP4 ((uint8_t)0x08U) /* COMP4 Alternate Function mapping */
+#define GPIO_AF8_COMP6 ((uint8_t)0x08U) /* COMP6 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */
+#define GPIO_AF9_TIM1 ((uint8_t)0x09U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */
+
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */
+#define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */
+#define GPIO_AF10_TIM4 ((uint8_t)0xAU) /* TIM4 Alternate Function mapping */
+#define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */
+/**
+ * @brief AF 11 selection
+ */
+#define GPIO_AF11_TIM1 ((uint8_t)0x0BU) /* TIM1 Alternate Function mapping */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF12_TIM1 ((uint8_t)0xCU) /* TIM1 Alternate Function mapping */
+
+/**
+ * @brief AF 14 selection
+ */
+
+#define GPIO_AF14_USB ((uint8_t)0x0EU) /* USB Alternate Function mapping */
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0CU) || ((AF) == (uint8_t)0x0EU) || ((AF) == (uint8_t)0x0FU))
+/*------------------------------------------------------------------------------------------*/
+#endif /* STM32F302xC */
+
+#if defined (STM32F303xC)
+/*---------------------------------- STM32F303xC ------------------------------*/
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */
+#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */
+#define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */
+#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /* TIM2 Alternate Function mapping */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM8 ((uint8_t)0x02U) /* TIM8 Alternate Function mapping */
+#define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF2_COMP1 ((uint8_t)0x02U) /* COMP1 Alternate Function mapping */
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */
+#define GPIO_AF3_TIM8 ((uint8_t)0x03U) /* TIM8 Alternate Function mapping */
+#define GPIO_AF3_COMP7 ((uint8_t)0x03U) /* COMP7 Alternate Function mapping */
+#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /* TIM15 Alternate Function mapping */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_TIM1 ((uint8_t)0x04U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF4_TIM8 ((uint8_t)0x04U) /* TIM8 Alternate Function mapping */
+#define GPIO_AF4_TIM16 ((uint8_t)0x04U) /* TIM16 Alternate Function mapping */
+#define GPIO_AF4_TIM17 ((uint8_t)0x04U) /* TIM17 Alternate Function mapping */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1/I2S1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF5_I2S ((uint8_t)0x05U) /* I2S Alternate Function mapping */
+#define GPIO_AF5_I2S2ext ((uint8_t)0x05U) /* I2S2ext Alternate Function mapping */
+#define GPIO_AF5_TIM8 ((uint8_t)0x05U) /* TIM8 Alternate Function mapping */
+#define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */
+#define GPIO_AF5_UART4 ((uint8_t)0x05U) /* UART4 Alternate Function mapping */
+#define GPIO_AF5_UART5 ((uint8_t)0x05U) /* UART5 Alternate Function mapping */
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_SPI2 ((uint8_t)0x06U) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_I2S3ext ((uint8_t)0x06U) /* I2S3ext Alternate Function mapping */
+#define GPIO_AF6_TIM1 ((uint8_t)0x06U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF6_TIM8 ((uint8_t)0x06U) /* TIM8 Alternate Function mapping */
+#define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_COMP3 ((uint8_t)0x07U) /* COMP3 Alternate Function mapping */
+#define GPIO_AF7_COMP5 ((uint8_t)0x07U) /* COMP5 Alternate Function mapping */
+#define GPIO_AF7_COMP6 ((uint8_t)0x07U) /* COMP6 Alternate Function mapping */
+#define GPIO_AF7_CAN ((uint8_t)0x07U) /* CAN Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_COMP1 ((uint8_t)0x08U) /* COMP1 Alternate Function mapping */
+#define GPIO_AF8_COMP2 ((uint8_t)0x08U) /* COMP2 Alternate Function mapping */
+#define GPIO_AF8_COMP3 ((uint8_t)0x08U) /* COMP3 Alternate Function mapping */
+#define GPIO_AF8_COMP4 ((uint8_t)0x08U) /* COMP4 Alternate Function mapping */
+#define GPIO_AF8_COMP5 ((uint8_t)0x08U) /* COMP5 Alternate Function mapping */
+#define GPIO_AF8_COMP6 ((uint8_t)0x08U) /* COMP6 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */
+#define GPIO_AF9_TIM1 ((uint8_t)0x09U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF9_TIM8 ((uint8_t)0x09U) /* TIM8 Alternate Function mapping */
+#define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */
+
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */
+#define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */
+#define GPIO_AF10_TIM4 ((uint8_t)0xAU) /* TIM4 Alternate Function mapping */
+#define GPIO_AF10_TIM8 ((uint8_t)0xAU) /* TIM8 Alternate Function mapping */
+#define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */
+/**
+ * @brief AF 11 selection
+ */
+#define GPIO_AF11_TIM1 ((uint8_t)0x0BU) /* TIM1 Alternate Function mapping */
+#define GPIO_AF11_TIM8 ((uint8_t)0x0BU) /* TIM8 Alternate Function mapping */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF12_TIM1 ((uint8_t)0xCU) /* TIM1 Alternate Function mapping */
+
+/**
+ * @brief AF 14 selection
+ */
+
+#define GPIO_AF14_USB ((uint8_t)0x0EU) /* USB Alternate Function mapping */
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0CU) || ((AF) == (uint8_t)0x0EU) || ((AF) == (uint8_t)0x0FU))
+/*------------------------------------------------------------------------------------------*/
+#endif /* STM32F303xC */
+
+#if defined (STM32F303xE)
+/*---------------------------------- STM32F303xE ------------------------------*/
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */
+#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */
+#define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */
+#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */
+
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /* TIM2 Alternate Function mapping */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM8 ((uint8_t)0x02U) /* TIM8 Alternate Function mapping */
+#define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF2_COMP1 ((uint8_t)0x02U) /* COMP1 Alternate Function mapping */
+#define GPIO_AF2_I2C3 ((uint8_t)0x02U) /* I2C3 Alternate Function mapping */
+#define GPIO_AF2_TIM20 ((uint8_t)0x02U) /* TIM20 Alternate Function mapping */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */
+#define GPIO_AF3_TIM8 ((uint8_t)0x03U) /* TIM8 Alternate Function mapping */
+#define GPIO_AF3_COMP7 ((uint8_t)0x03U) /* COMP7 Alternate Function mapping */
+#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF3_I2C3 ((uint8_t)0x03U) /* I2C3 Alternate Function mapping */
+#define GPIO_AF3_TIM20 ((uint8_t)0x03U) /* TIM20 Alternate Function mapping */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_TIM1 ((uint8_t)0x04U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF4_TIM8 ((uint8_t)0x04U) /* TIM8 Alternate Function mapping */
+#define GPIO_AF4_TIM16 ((uint8_t)0x04U) /* TIM16 Alternate Function mapping */
+#define GPIO_AF4_TIM17 ((uint8_t)0x04U) /* TIM17 Alternate Function mapping */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF5_I2S ((uint8_t)0x05U) /* I2S Alternate Function mapping */
+#define GPIO_AF5_I2S2ext ((uint8_t)0x05U) /* I2S2ext Alternate Function mapping */
+#define GPIO_AF5_TIM8 ((uint8_t)0x05U) /* TIM8 Alternate Function mapping */
+#define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */
+#define GPIO_AF5_UART4 ((uint8_t)0x05U) /* UART4 Alternate Function mapping */
+#define GPIO_AF5_UART5 ((uint8_t)0x05U) /* UART5 Alternate Function mapping */
+#define GPIO_AF5_SPI4 ((uint8_t)0x05U) /* SPI4 Alternate Function mapping */
+
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_SPI2 ((uint8_t)0x06U) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_I2S3ext ((uint8_t)0x06U) /* I2S3ext Alternate Function mapping */
+#define GPIO_AF6_TIM1 ((uint8_t)0x06U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF6_TIM8 ((uint8_t)0x06U) /* TIM8 Alternate Function mapping */
+#define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */
+#define GPIO_AF6_TIM20 ((uint8_t)0x06U) /* TIM20 Alternate Function mapping */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_COMP3 ((uint8_t)0x07U) /* COMP3 Alternate Function mapping */
+#define GPIO_AF7_COMP5 ((uint8_t)0x07U) /* COMP5 Alternate Function mapping */
+#define GPIO_AF7_COMP6 ((uint8_t)0x07U) /* COMP6 Alternate Function mapping */
+#define GPIO_AF7_CAN ((uint8_t)0x07U) /* CAN Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_COMP1 ((uint8_t)0x08U) /* COMP1 Alternate Function mapping */
+#define GPIO_AF8_COMP2 ((uint8_t)0x08U) /* COMP2 Alternate Function mapping */
+#define GPIO_AF8_COMP3 ((uint8_t)0x08U) /* COMP3 Alternate Function mapping */
+#define GPIO_AF8_COMP4 ((uint8_t)0x08U) /* COMP4 Alternate Function mapping */
+#define GPIO_AF8_COMP5 ((uint8_t)0x08U) /* COMP5 Alternate Function mapping */
+#define GPIO_AF8_COMP6 ((uint8_t)0x08U) /* COMP6 Alternate Function mapping */
+#define GPIO_AF8_I2C3 ((uint8_t)0x08U) /* I2C3 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */
+#define GPIO_AF9_TIM1 ((uint8_t)0x09U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF9_TIM8 ((uint8_t)0x09U) /* TIM8 Alternate Function mapping */
+#define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */
+
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */
+#define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */
+#define GPIO_AF10_TIM4 ((uint8_t)0xAU) /* TIM4 Alternate Function mapping */
+#define GPIO_AF10_TIM8 ((uint8_t)0xAU) /* TIM8 Alternate Function mapping */
+#define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */
+/**
+ * @brief AF 11 selection
+ */
+#define GPIO_AF11_TIM1 ((uint8_t)0x0BU) /* TIM1 Alternate Function mapping */
+#define GPIO_AF11_TIM8 ((uint8_t)0x0BU) /* TIM8 Alternate Function mapping */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF12_TIM1 ((uint8_t)0xCU) /* TIM1 Alternate Function mapping */
+#define GPIO_AF12_FMC ((uint8_t)0xCU) /* FMC Alternate Function mapping */
+#define GPIO_AF12_SDIO ((uint8_t)0xCU) /* SDIO Alternate Function mapping */
+
+/**
+ * @brief AF 14 selection
+ */
+#define GPIO_AF14_USB ((uint8_t)0x0EU) /* USB Alternate Function mapping */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0CU) || ((AF) == (uint8_t)0x0EU) || ((AF) == (uint8_t)0x0FU))
+/*------------------------------------------------------------------------------------------*/
+#endif /* STM32F303xE */
+
+#if defined (STM32F302xE)
+/*---------------------------------- STM32F302xE ------------------------------*/
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */
+#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */
+#define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */
+#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */
+
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /* TIM2 Alternate Function mapping */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF2_COMP1 ((uint8_t)0x02U) /* COMP1 Alternate Function mapping */
+#define GPIO_AF2_I2C3 ((uint8_t)0x02U) /* I2C3 Alternate Function mapping */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */
+#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF3_I2C3 ((uint8_t)0x03U) /* I2C3 Alternate Function mapping */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_TIM1 ((uint8_t)0x04U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF4_TIM16 ((uint8_t)0x04U) /* TIM16 Alternate Function mapping */
+#define GPIO_AF4_TIM17 ((uint8_t)0x04U) /* TIM17 Alternate Function mapping */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF5_I2S ((uint8_t)0x05U) /* I2S Alternate Function mapping */
+#define GPIO_AF5_I2S2ext ((uint8_t)0x05U) /* I2S2ext Alternate Function mapping */
+#define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */
+#define GPIO_AF5_UART4 ((uint8_t)0x05U) /* UART4 Alternate Function mapping */
+#define GPIO_AF5_UART5 ((uint8_t)0x05U) /* UART5 Alternate Function mapping */
+#define GPIO_AF5_SPI4 ((uint8_t)0x05U) /* SPI4 Alternate Function mapping */
+
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_SPI2 ((uint8_t)0x06U) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_I2S3ext ((uint8_t)0x06U) /* I2S3ext Alternate Function mapping */
+#define GPIO_AF6_TIM1 ((uint8_t)0x06U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_COMP6 ((uint8_t)0x07U) /* COMP6 Alternate Function mapping */
+#define GPIO_AF7_CAN ((uint8_t)0x07U) /* CAN Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_COMP1 ((uint8_t)0x08U) /* COMP1 Alternate Function mapping */
+#define GPIO_AF8_COMP2 ((uint8_t)0x08U) /* COMP2 Alternate Function mapping */
+#define GPIO_AF8_COMP4 ((uint8_t)0x08U) /* COMP4 Alternate Function mapping */
+#define GPIO_AF8_COMP6 ((uint8_t)0x08U) /* COMP6 Alternate Function mapping */
+#define GPIO_AF8_I2C3 ((uint8_t)0x08U) /* I2C3 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */
+#define GPIO_AF9_TIM1 ((uint8_t)0x09U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */
+
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */
+#define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */
+#define GPIO_AF10_TIM4 ((uint8_t)0xAU) /* TIM4 Alternate Function mapping */
+#define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */
+/**
+ * @brief AF 11 selection
+ */
+#define GPIO_AF11_TIM1 ((uint8_t)0x0BU) /* TIM1 Alternate Function mapping */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF12_TIM1 ((uint8_t)0xCU) /* TIM1 Alternate Function mapping */
+#define GPIO_AF12_FMC ((uint8_t)0xCU) /* FMC Alternate Function mapping */
+#define GPIO_AF12_SDIO ((uint8_t)0xCU) /* SDIO Alternate Function mapping */
+
+/**
+ * @brief AF 14 selection
+ */
+#define GPIO_AF14_USB ((uint8_t)0x0EU) /* USB Alternate Function mapping */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0CU) || ((AF) == (uint8_t)0x0EU) || ((AF) == (uint8_t)0x0FU))
+/*------------------------------------------------------------------------------------------*/
+#endif /* STM32F302xE */
+
+#if defined (STM32F398xx)
+/*---------------------------------- STM32F398xx ------------------------------*/
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */
+#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */
+#define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */
+#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */
+
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /* TIM2 Alternate Function mapping */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM8 ((uint8_t)0x02U) /* TIM8 Alternate Function mapping */
+#define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF2_COMP1 ((uint8_t)0x02U) /* COMP1 Alternate Function mapping */
+#define GPIO_AF2_I2C3 ((uint8_t)0x02U) /* I2C3 Alternate Function mapping */
+#define GPIO_AF2_TIM20 ((uint8_t)0x02U) /* TIM20 Alternate Function mapping */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */
+#define GPIO_AF3_TIM8 ((uint8_t)0x03U) /* TIM8 Alternate Function mapping */
+#define GPIO_AF3_COMP7 ((uint8_t)0x03U) /* COMP7 Alternate Function mapping */
+#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF3_I2C3 ((uint8_t)0x03U) /* I2C3 Alternate Function mapping */
+#define GPIO_AF3_TIM20 ((uint8_t)0x03U) /* TIM20 Alternate Function mapping */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_TIM1 ((uint8_t)0x04U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF4_TIM8 ((uint8_t)0x04U) /* TIM8 Alternate Function mapping */
+#define GPIO_AF4_TIM16 ((uint8_t)0x04U) /* TIM16 Alternate Function mapping */
+#define GPIO_AF4_TIM17 ((uint8_t)0x04U) /* TIM17 Alternate Function mapping */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF5_I2S ((uint8_t)0x05U) /* I2S Alternate Function mapping */
+#define GPIO_AF5_I2S2ext ((uint8_t)0x05U) /* I2S2ext Alternate Function mapping */
+#define GPIO_AF5_TIM8 ((uint8_t)0x05U) /* TIM8 Alternate Function mapping */
+#define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */
+#define GPIO_AF5_UART4 ((uint8_t)0x05U) /* UART4 Alternate Function mapping */
+#define GPIO_AF5_UART5 ((uint8_t)0x05U) /* UART5 Alternate Function mapping */
+#define GPIO_AF5_SPI4 ((uint8_t)0x05U) /* SPI4 Alternate Function mapping */
+
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_SPI2 ((uint8_t)0x06U) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_I2S3ext ((uint8_t)0x06U) /* I2S3ext Alternate Function mapping */
+#define GPIO_AF6_TIM1 ((uint8_t)0x06U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF6_TIM8 ((uint8_t)0x06U) /* TIM8 Alternate Function mapping */
+#define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */
+#define GPIO_AF6_TIM20 ((uint8_t)0x06U) /* TIM20 Alternate Function mapping */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_COMP3 ((uint8_t)0x07U) /* COMP3 Alternate Function mapping */
+#define GPIO_AF7_COMP5 ((uint8_t)0x07U) /* COMP5 Alternate Function mapping */
+#define GPIO_AF7_COMP6 ((uint8_t)0x07U) /* COMP6 Alternate Function mapping */
+#define GPIO_AF7_CAN ((uint8_t)0x07U) /* CAN Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_COMP1 ((uint8_t)0x08U) /* COMP1 Alternate Function mapping */
+#define GPIO_AF8_COMP2 ((uint8_t)0x08U) /* COMP2 Alternate Function mapping */
+#define GPIO_AF8_COMP3 ((uint8_t)0x08U) /* COMP3 Alternate Function mapping */
+#define GPIO_AF8_COMP4 ((uint8_t)0x08U) /* COMP4 Alternate Function mapping */
+#define GPIO_AF8_COMP5 ((uint8_t)0x08U) /* COMP5 Alternate Function mapping */
+#define GPIO_AF8_COMP6 ((uint8_t)0x08U) /* COMP6 Alternate Function mapping */
+#define GPIO_AF8_I2C3 ((uint8_t)0x08U) /* I2C3 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */
+#define GPIO_AF9_TIM1 ((uint8_t)0x09U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF9_TIM8 ((uint8_t)0x09U) /* TIM8 Alternate Function mapping */
+#define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */
+
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */
+#define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */
+#define GPIO_AF10_TIM4 ((uint8_t)0xAU) /* TIM4 Alternate Function mapping */
+#define GPIO_AF10_TIM8 ((uint8_t)0xAU) /* TIM8 Alternate Function mapping */
+#define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */
+/**
+ * @brief AF 11 selection
+ */
+#define GPIO_AF11_TIM1 ((uint8_t)0x0BU) /* TIM1 Alternate Function mapping */
+#define GPIO_AF11_TIM8 ((uint8_t)0x0BU) /* TIM8 Alternate Function mapping */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF12_TIM1 ((uint8_t)0xCU) /* TIM1 Alternate Function mapping */
+#define GPIO_AF12_FMC ((uint8_t)0xCU) /* FMC Alternate Function mapping */
+#define GPIO_AF12_SDIO ((uint8_t)0xCU) /* SDIO Alternate Function mapping */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0CU) || ((AF) == (uint8_t)0x0FU))
+/*------------------------------------------------------------------------------------------*/
+#endif /* STM32F398xx */
+
+#if defined (STM32F358xx)
+/*---------------------------------- STM32F358xx -------------------------------------------*/
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */
+#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */
+#define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */
+#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /* TIM2 Alternate Function mapping */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM8 ((uint8_t)0x02U) /* TIM8 Alternate Function mapping */
+#define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF2_COMP1 ((uint8_t)0x02U) /* COMP1 Alternate Function mapping */
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */
+#define GPIO_AF3_TIM8 ((uint8_t)0x03U) /* TIM8 Alternate Function mapping */
+#define GPIO_AF3_COMP7 ((uint8_t)0x03U) /* COMP7 Alternate Function mapping */
+#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /* TIM15 Alternate Function mapping */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_TIM1 ((uint8_t)0x04U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF4_TIM8 ((uint8_t)0x04U) /* TIM8 Alternate Function mapping */
+#define GPIO_AF4_TIM16 ((uint8_t)0x04U) /* TIM16 Alternate Function mapping */
+#define GPIO_AF4_TIM17 ((uint8_t)0x04U) /* TIM17 Alternate Function mapping */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1/I2S1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF5_I2S ((uint8_t)0x05U) /* I2S Alternate Function mapping */
+#define GPIO_AF5_I2S2ext ((uint8_t)0x05U) /* I2S2ext Alternate Function mapping */
+#define GPIO_AF5_TIM8 ((uint8_t)0x05U) /* TIM8 Alternate Function mapping */
+#define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */
+#define GPIO_AF5_UART4 ((uint8_t)0x05U) /* UART4 Alternate Function mapping */
+#define GPIO_AF5_UART5 ((uint8_t)0x05U) /* UART5 Alternate Function mapping */
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_SPI2 ((uint8_t)0x06U) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_I2S3ext ((uint8_t)0x06U) /* I2S3ext Alternate Function mapping */
+#define GPIO_AF6_TIM1 ((uint8_t)0x06U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF6_TIM8 ((uint8_t)0x06U) /* TIM8 Alternate Function mapping */
+#define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_COMP3 ((uint8_t)0x07U) /* COMP3 Alternate Function mapping */
+#define GPIO_AF7_COMP5 ((uint8_t)0x07U) /* COMP5 Alternate Function mapping */
+#define GPIO_AF7_COMP6 ((uint8_t)0x07U) /* COMP6 Alternate Function mapping */
+#define GPIO_AF7_CAN ((uint8_t)0x07U) /* CAN Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_COMP1 ((uint8_t)0x08U) /* COMP1 Alternate Function mapping */
+#define GPIO_AF8_COMP2 ((uint8_t)0x08U) /* COMP2 Alternate Function mapping */
+#define GPIO_AF8_COMP3 ((uint8_t)0x08U) /* COMP3 Alternate Function mapping */
+#define GPIO_AF8_COMP4 ((uint8_t)0x08U) /* COMP4 Alternate Function mapping */
+#define GPIO_AF8_COMP5 ((uint8_t)0x08U) /* COMP5 Alternate Function mapping */
+#define GPIO_AF8_COMP6 ((uint8_t)0x08U) /* COMP6 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */
+#define GPIO_AF9_TIM1 ((uint8_t)0x09U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF9_TIM8 ((uint8_t)0x09U) /* TIM8 Alternate Function mapping */
+#define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */
+
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */
+#define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */
+#define GPIO_AF10_TIM4 ((uint8_t)0xAU) /* TIM4 Alternate Function mapping */
+#define GPIO_AF10_TIM8 ((uint8_t)0xAU) /* TIM8 Alternate Function mapping */
+#define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */
+/**
+ * @brief AF 11 selection
+ */
+#define GPIO_AF11_TIM1 ((uint8_t)0x0BU) /* TIM1 Alternate Function mapping */
+#define GPIO_AF11_TIM8 ((uint8_t)0x0BU) /* TIM8 Alternate Function mapping */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF12_TIM1 ((uint8_t)0xCU) /* TIM1 Alternate Function mapping */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0CU) || ((AF) == (uint8_t)0x0FU))
+/*------------------------------------------------------------------------------------------*/
+#endif /* STM32F358xx */
+
+#if defined (STM32F373xC)
+/*---------------------------------- STM32F373xC--------------------------------*/
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */
+#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */
+#define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */
+#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5 ((uint8_t)0x02U) /* TIM5 Alternate Function mapping */
+#define GPIO_AF2_TIM13 ((uint8_t)0x02U) /* TIM13 Alternate Function mapping */
+#define GPIO_AF2_TIM14 ((uint8_t)0x02U) /* TIM14 Alternate Function mapping */
+#define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF2_TIM19 ((uint8_t)0x02U) /* TIM19 Alternate Function mapping */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1/I2S1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_SPI1 ((uint8_t)0x06U) /* SPI1/I2S1 Alternate Function mapping */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */
+#define GPIO_AF6_CEC ((uint8_t)0x06U) /* CEC Alternate Function mapping */
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_CAN ((uint8_t)0x07U) /* CAN Alternate Function mapping */
+#define GPIO_AF7_CEC ((uint8_t)0x07U) /* CEC Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_COMP1 ((uint8_t)0x08U) /* COMP1 Alternate Function mapping */
+#define GPIO_AF8_COMP2 ((uint8_t)0x08U) /* COMP2 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */
+#define GPIO_AF9_TIM12 ((uint8_t)0x09U) /* TIM12 Alternate Function mapping */
+#define GPIO_AF9_TIM13 ((uint8_t)0x09U) /* TIM13 Alternate Function mapping */
+#define GPIO_AF9_TIM14 ((uint8_t)0x09U) /* TIM14 Alternate Function mapping */
+#define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */
+#define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */
+#define GPIO_AF10_TIM4 ((uint8_t)0xAU) /* TIM4 Alternate Function mapping */
+#define GPIO_AF10_TIM12 ((uint8_t)0xAU) /* TIM12 Alternate Function mapping */
+#define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */
+/**
+ * @brief AF 11 selection
+ */
+#define GPIO_AF11_TIM19 ((uint8_t)0x0BU) /* TIM19 Alternate Function mapping */
+
+
+/**
+ * @brief AF 14 selection
+ */
+#define GPIO_AF14_USB ((uint8_t)0x0EU) /* USB Alternate Function mapping */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0BU) || ((AF) == (uint8_t)0x0EU) || ((AF) == (uint8_t)0x0FU))
+/*------------------------------------------------------------------------------------------*/
+#endif /* STM32F373xC */
+
+
+#if defined (STM32F378xx)
+/*---------------------------------------- STM32F378xx--------------------------------------*/
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */
+#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */
+#define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */
+#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5 ((uint8_t)0x02U) /* TIM5 Alternate Function mapping */
+#define GPIO_AF2_TIM13 ((uint8_t)0x02U) /* TIM13 Alternate Function mapping */
+#define GPIO_AF2_TIM14 ((uint8_t)0x02U) /* TIM14 Alternate Function mapping */
+#define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF2_TIM19 ((uint8_t)0x02U) /* TIM19 Alternate Function mapping */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1/I2S1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */
+
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_SPI1 ((uint8_t)0x06U) /* SPI1/I2S1 Alternate Function mapping */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */
+#define GPIO_AF6_CEC ((uint8_t)0x06U) /* CEC Alternate Function mapping */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_CAN ((uint8_t)0x07U) /* CAN Alternate Function mapping */
+#define GPIO_AF7_CEC ((uint8_t)0x07U) /* CEC Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_COMP1 ((uint8_t)0x08U) /* COMP1 Alternate Function mapping */
+#define GPIO_AF8_COMP2 ((uint8_t)0x08U) /* COMP2 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */
+#define GPIO_AF9_TIM12 ((uint8_t)0x09U) /* TIM12 Alternate Function mapping */
+#define GPIO_AF9_TIM13 ((uint8_t)0x09U) /* TIM13 Alternate Function mapping */
+#define GPIO_AF9_TIM14 ((uint8_t)0x09U) /* TIM14 Alternate Function mapping */
+#define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */
+
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */
+#define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */
+#define GPIO_AF10_TIM4 ((uint8_t)0xAU) /* TIM4 Alternate Function mapping */
+#define GPIO_AF10_TIM12 ((uint8_t)0xAU) /* TIM12 Alternate Function mapping */
+#define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */
+
+/**
+ * @brief AF 11 selection
+ */
+#define GPIO_AF11_TIM19 ((uint8_t)0x0BU) /* TIM19 Alternate Function mapping */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0BU) || ((AF) == (uint8_t)0x0FU))
+/*------------------------------------------------------------------------------------------*/
+#endif /* STM32F378xx */
+
+#if defined (STM32F303x8)
+/*---------------------------------- STM32F303x8--------------------------------*/
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */
+#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */
+#define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */
+#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /* TIM16 Alternate Function mapping */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_TIM1 ((uint8_t)0x04U) /* TIM1 Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */
+#define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_TIM1 ((uint8_t)0x06U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_GPCOMP6 ((uint8_t)0x07U) /* GPCOMP6 Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_GPCOMP2 ((uint8_t)0x08U) /* GPCOMP2 Alternate Function mapping */
+#define GPIO_AF8_GPCOMP4 ((uint8_t)0x08U) /* GPCOMP4 Alternate Function mapping */
+#define GPIO_AF8_GPCOMP6 ((uint8_t)0x08U) /* GPCOMP6 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */
+#define GPIO_AF9_TIM1 ((uint8_t)0x09U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */
+#define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */
+#define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */
+
+/**
+ * @brief AF 11 selection
+ */
+#define GPIO_AF11_TIM1 ((uint8_t)0x0BU) /* TIM1 Alternate Function mapping */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF12_TIM1 ((uint8_t)0x0CU) /* TIM1 Alternate Function mapping */
+
+/**
+ * @brief AF 13 selection
+ */
+#define GPIO_AF13_OPAMP2 ((uint8_t)0x0DU) /* OPAMP2 Alternate Function mapping */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0DU) || ((AF) == (uint8_t)0x0FU))
+/*------------------------------------------------------------------------------------------*/
+#endif /* STM32F303x8 */
+
+#if defined (STM32F334x8) || defined (STM32F328xx)
+/*---------------------------------- STM32F334x8/STM32F328xx -------------------------------*/
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */
+#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */
+#define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */
+#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /* TIM16 Alternate Function mapping */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */
+#define GPIO_AF3_HRTIM1 ((uint8_t)0x03U) /* HRTIM1 Alternate Function mapping */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_TIM1 ((uint8_t)0x04U) /* TIM1 Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */
+#define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_TIM1 ((uint8_t)0x06U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_GPCOMP6 ((uint8_t)0x07U) /* GPCOMP6 Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_GPCOMP2 ((uint8_t)0x08U) /* GPCOMP2 Alternate Function mapping */
+#define GPIO_AF8_GPCOMP4 ((uint8_t)0x08U) /* GPCOMP4 Alternate Function mapping */
+#define GPIO_AF8_GPCOMP6 ((uint8_t)0x08U) /* GPCOMP6 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */
+#define GPIO_AF9_TIM1 ((uint8_t)0x09U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */
+#define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */
+#define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */
+
+/**
+ * @brief AF 11 selection
+ */
+#define GPIO_AF11_TIM1 ((uint8_t)0x0BU) /* TIM1 Alternate Function mapping */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF12_TIM1 ((uint8_t)0x0CU) /* TIM1 Alternate Function mapping */
+#define GPIO_AF12_HRTIM1 ((uint8_t)0x0CU) /* HRTIM1 Alternate Function mapping */
+
+/**
+ * @brief AF 13 selection
+ */
+#define GPIO_AF13_OPAMP2 ((uint8_t)0x0DU) /* OPAMP2 Alternate Function mapping */
+#define GPIO_AF13_HRTIM1 ((uint8_t)0x0DU) /* HRTIM1 Alternate Function mapping */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0DU) || ((AF) == (uint8_t)0x0FU))
+/*------------------------------------------------------------------------------------------*/
+#endif /* STM32F334x8 || STM32F328xx */
+
+#if defined (STM32F301x8) || defined (STM32F318xx)
+/*---------------------------------- STM32F301x8 / STM32F318xx ------------------------------------------*/
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */
+#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */
+#define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */
+#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_I2C3 ((uint8_t)0x02U) /* I2C3 Alternate Function mapping */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /* TIM2 Alternate Function mapping */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */
+#define GPIO_AF3_I2C3 ((uint8_t)0x03U) /* I2C3 Alternate Function mapping */
+#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /* TIM15 Alternate Function mapping */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_TIM1 ((uint8_t)0x04U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF4_TIM16 ((uint8_t)0x04U) /* TIM16 Alternate Function mapping */
+#define GPIO_AF4_TIM17 ((uint8_t)0x04U) /* TIM17 Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_TIM1 ((uint8_t)0x06U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */
+#define GPIO_AF6_SPI2 ((uint8_t)0x06U) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_GPCOMP6 ((uint8_t)0x07U) /* GPCOMP6 Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_I2C3 ((uint8_t)0x08U) /* I2C3 Alternate Function mapping */
+#define GPIO_AF8_GPCOMP2 ((uint8_t)0x08U) /* GPCOMP2 Alternate Function mapping */
+#define GPIO_AF8_GPCOMP4 ((uint8_t)0x08U) /* GPCOMP4 Alternate Function mapping */
+#define GPIO_AF8_GPCOMP6 ((uint8_t)0x08U) /* GPCOMP6 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_TIM1 ((uint8_t)0x09U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */
+
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */
+#define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */
+
+/**
+ * @brief AF 11 selection
+ */
+#define GPIO_AF11_TIM1 ((uint8_t)0x0BU) /* TIM1 Alternate Function mapping */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF12_TIM1 ((uint8_t)0x0CU) /* TIM1 Alternate Function mapping */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0CU) || ((AF) == (uint8_t)0x0FU))
+/*------------------------------------------------------------------------------------------*/
+#endif /* STM32F301x8 || STM32F318xx */
+
+#if defined (STM32F302x8)
+/*---------------------------------- STM32F302x8------------------------------------------*/
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */
+#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */
+#define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */
+#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_I2C3 ((uint8_t)0x02U) /* I2C3 Alternate Function mapping */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /* TIM2 Alternate Function mapping */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */
+#define GPIO_AF3_I2C3 ((uint8_t)0x03U) /* I2C3 Alternate Function mapping */
+#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /* TIM15 Alternate Function mapping */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_TIM1 ((uint8_t)0x04U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF4_TIM16 ((uint8_t)0x04U) /* TIM16 Alternate Function mapping */
+#define GPIO_AF4_TIM17 ((uint8_t)0x04U) /* TIM17 Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_TIM1 ((uint8_t)0x06U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */
+#define GPIO_AF6_SPI2 ((uint8_t)0x06U) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_GPCOMP6 ((uint8_t)0x07U) /* GPCOMP6 Alternate Function mapping */
+#define GPIO_AF7_CAN ((uint8_t)0x07U) /* CAN Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_I2C3 ((uint8_t)0x08U) /* I2C3 Alternate Function mapping */
+#define GPIO_AF8_GPCOMP2 ((uint8_t)0x08U) /* GPCOMP2 Alternate Function mapping */
+#define GPIO_AF8_GPCOMP4 ((uint8_t)0x08U) /* GPCOMP4 Alternate Function mapping */
+#define GPIO_AF8_GPCOMP6 ((uint8_t)0x08U) /* GPCOMP6 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_TIM1 ((uint8_t)0x09U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */
+
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */
+#define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */
+
+/**
+ * @brief AF 11 selection
+ */
+#define GPIO_AF11_TIM1 ((uint8_t)0x0BU) /* TIM1 Alternate Function mapping */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF12_TIM1 ((uint8_t)0x0CU) /* TIM1 Alternate Function mapping */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0CU) || ((AF) == (uint8_t)0x0FU))
+/*------------------------------------------------------------------------------------------*/
+#endif /* STM32F302x8 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros
+ * @{
+ */
+
+/** @defgroup GPIOEx_Get_Port_Index GPIOEx_Get Port Index
+* @{
+ */
+#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
+ ((__GPIOx__) == (GPIOB))? 1U :\
+ ((__GPIOx__) == (GPIOC))? 2U :\
+ ((__GPIOx__) == (GPIOD))? 3U : 5U)
+#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
+ ((__GPIOx__) == (GPIOB))? 1U :\
+ ((__GPIOx__) == (GPIOC))? 2U :\
+ ((__GPIOx__) == (GPIOD))? 3U :\
+ ((__GPIOx__) == (GPIOE))? 4U : 5U)
+#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
+ ((__GPIOx__) == (GPIOB))? 1U :\
+ ((__GPIOx__) == (GPIOC))? 2U :\
+ ((__GPIOx__) == (GPIOD))? 3U :\
+ ((__GPIOx__) == (GPIOE))? 4U :\
+ ((__GPIOx__) == (GPIOF))? 5U :\
+ ((__GPIOx__) == (GPIOG))? 6U : 7U)
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_GPIO_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_hal_hrtim.h b/Inc/stm32f3xx_hal_hrtim.h
new file mode 100644
index 0000000..2aecbb0
--- /dev/null
+++ b/Inc/stm32f3xx_hal_hrtim.h
@@ -0,0 +1,3621 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_hrtim.h
+ * @author MCD Application Team
+ * @brief Header file of HRTIM HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_HRTIM_H
+#define __STM32F3xx_HAL_HRTIM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(HRTIM1)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup HRTIM HRTIM
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @addtogroup HRTIM_Exported_Constants HRTIM Exported Constants
+ * @{
+ */
+/** @defgroup HRTIM_Max_Timer HRTIM Max Timer
+ * @{
+ */
+#define MAX_HRTIM_TIMER 6U
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Exported_Types HRTIM Exported Types
+ * @{
+ */
+
+/**
+ * @brief HRTIM Configuration Structure definition - Time base related parameters
+ */
+typedef struct
+{
+ uint32_t HRTIMInterruptResquests; /*!< Specifies which interrupts requests must enabled for the HRTIM instance.
+ This parameter can be any combination of @ref HRTIM_Common_Interrupt_Enable */
+ uint32_t SyncOptions; /*!< Specifies how the HRTIM instance handles the external synchronization signals.
+ The HRTIM instance can be configured to act as a slave (waiting for a trigger
+ to be synchronized) or a master (generating a synchronization signal) or both.
+ This parameter can be a combination of @ref HRTIM_Synchronization_Options.*/
+ uint32_t SyncInputSource; /*!< Specifies the external synchronization input source (significant only when
+ the HRTIM instance is configured as a slave).
+ This parameter can be a value of @ref HRTIM_Synchronization_Input_Source. */
+ uint32_t SyncOutputSource; /*!< Specifies the source and event to be sent on the external synchronization outputs
+ (significant only when the HRTIM instance is configured as a master).
+ This parameter can be a value of @ref HRTIM_Synchronization_Output_Source */
+ uint32_t SyncOutputPolarity; /*!< Specifies the conditioning of the event to be sent on the external synchronization
+ outputs (significant only when the HRTIM instance is configured as a master).
+ This parameter can be a value of @ref HRTIM_Synchronization_Output_Polarity */
+} HRTIM_InitTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_HRTIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
+ HAL_HRTIM_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
+ HAL_HRTIM_STATE_TIMEOUT = 0x06U, /*!< Timeout state */
+ HAL_HRTIM_STATE_ERROR = 0x07U, /*!< Error state */
+} HAL_HRTIM_StateTypeDef;
+
+/**
+ * @brief HRTIM Timer Structure definition
+ */
+typedef struct
+{
+ uint32_t CaptureTrigger1; /*!< Event(s) triggering capture unit 1.
+ When the timer operates in Simple mode, this parameter can be a value of @ref HRTIM_External_Event_Channels.
+ When the timer operates in Waveform mode, this parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger. */
+ uint32_t CaptureTrigger2; /*!< Event(s) triggering capture unit 2.
+ When the timer operates in Simple mode, this parameter can be a value of @ref HRTIM_External_Event_Channels.
+ When the timer operates in Waveform mode, this parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger. */
+ uint32_t InterruptRequests; /*!< Interrupts requests enabled for the timer. */
+ uint32_t DMARequests; /*!< DMA requests enabled for the timer. */
+ uint32_t DMASrcAddress; /*!< Address of the source address of the DMA transfer. */
+ uint32_t DMADstAddress; /*!< Address of the destination address of the DMA transfer. */
+ uint32_t DMASize; /*!< Size of the DMA transfer */
+} HRTIM_TimerParamTypeDef;
+
+/**
+ * @brief HRTIM Handle Structure definition
+ */
+typedef struct __HRTIM_HandleTypeDef
+{
+ HRTIM_TypeDef * Instance; /*!< Register base address */
+
+ HRTIM_InitTypeDef Init; /*!< HRTIM required parameters */
+
+ HRTIM_TimerParamTypeDef TimerParam[MAX_HRTIM_TIMER]; /*!< HRTIM timers - including the master - parameters */
+
+ HAL_LockTypeDef Lock; /*!< Locking object */
+
+ __IO HAL_HRTIM_StateTypeDef State; /*!< HRTIM communication state */
+
+ DMA_HandleTypeDef * hdmaMaster; /*!< Master timer DMA handle parameters */
+ DMA_HandleTypeDef * hdmaTimerA; /*!< Timer A DMA handle parameters */
+ DMA_HandleTypeDef * hdmaTimerB; /*!< Timer B DMA handle parameters */
+ DMA_HandleTypeDef * hdmaTimerC; /*!< Timer C DMA handle parameters */
+ DMA_HandleTypeDef * hdmaTimerD; /*!< Timer D DMA handle parameters */
+ DMA_HandleTypeDef * hdmaTimerE; /*!< Timer E DMA handle parameters */
+} HRTIM_HandleTypeDef;
+
+/**
+ * @brief Simple output compare mode configuration definition
+ */
+typedef struct {
+ uint32_t Period; /*!< Specifies the timer period.
+ The period value must be above 3 periods of the fHRTIM clock.
+ Maximum value is = 0xFFDFU */
+ uint32_t RepetitionCounter; /*!< Specifies the timer repetition period.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+ uint32_t PrescalerRatio; /*!< Specifies the timer clock prescaler ratio.
+ This parameter can be any value of @ref HRTIM_Prescaler_Ratio */
+ uint32_t Mode; /*!< Specifies the counter operating mode.
+ This parameter can be any value of @ref HRTIM_Counter_Operating_Mode */
+} HRTIM_TimeBaseCfgTypeDef;
+
+/**
+ * @brief Simple output compare mode configuration definition
+ */
+typedef struct {
+ uint32_t Mode; /*!< Specifies the output compare mode (toggle, active, inactive).
+ This parameter can be any value of of @ref HRTIM_Simple_OC_Mode */
+ uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
+ The compare value must be above or equal to 3 periods of the fHRTIM clock */
+ uint32_t Polarity; /*!< Specifies the output polarity.
+ This parameter can be any value of @ref HRTIM_Output_Polarity */
+ uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state.
+ This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
+} HRTIM_SimpleOCChannelCfgTypeDef;
+
+/**
+ * @brief Simple PWM output mode configuration definition
+ */
+typedef struct {
+ uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
+ The compare value must be above or equal to 3 periods of the fHRTIM clock */
+ uint32_t Polarity; /*!< Specifies the output polarity.
+ This parameter can be any value of @ref HRTIM_Output_Polarity */
+ uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state.
+ This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
+} HRTIM_SimplePWMChannelCfgTypeDef;
+
+/**
+ * @brief Simple capture mode configuration definition
+ */
+typedef struct {
+ uint32_t Event; /*!< Specifies the external event triggering the capture.
+ This parameter can be any 'EEVx' value of @ref HRTIM_External_Event_Channels */
+ uint32_t EventPolarity; /*!< Specifies the polarity of the external event (in case of level sensitivity).
+ This parameter can be a value of @ref HRTIM_External_Event_Polarity */
+ uint32_t EventSensitivity; /*!< Specifies the sensitivity of the external event.
+ This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */
+ uint32_t EventFilter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter.
+ This parameter can be a value of @ref HRTIM_External_Event_Filter */
+} HRTIM_SimpleCaptureChannelCfgTypeDef;
+
+/**
+ * @brief Simple One Pulse mode configuration definition
+ */
+typedef struct {
+ uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
+ The compare value must be above or equal to 3 periods of the fHRTIM clock */
+ uint32_t OutputPolarity; /*!< Specifies the output polarity.
+ This parameter can be any value of @ref HRTIM_Output_Polarity */
+ uint32_t OutputIdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state.
+ This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
+ uint32_t Event; /*!< Specifies the external event triggering the pulse generation.
+ This parameter can be any 'EEVx' value of @ref HRTIM_External_Event_Channels */
+ uint32_t EventPolarity; /*!< Specifies the polarity of the external event (in case of level sensitivity).
+ This parameter can be a value of @ref HRTIM_External_Event_Polarity */
+ uint32_t EventSensitivity; /*!< Specifies the sensitivity of the external event.
+ This parameter can be a value of @ref HRTIM_External_Event_Sensitivity. */
+ uint32_t EventFilter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter.
+ This parameter can be a value of @ref HRTIM_External_Event_Filter */
+} HRTIM_SimpleOnePulseChannelCfgTypeDef;
+
+/**
+ * @brief Timer configuration definition
+ */
+typedef struct {
+ uint32_t InterruptRequests; /*!< Relevant for all HRTIM timers, including the master.
+ Specifies which interrupts requests must enabled for the timer.
+ This parameter can be any combination of @ref HRTIM_Master_Interrupt_Enable
+ or @ref HRTIM_Timing_Unit_Interrupt_Enable */
+ uint32_t DMARequests; /*!< Relevant for all HRTIM timers, including the master.
+ Specifies which DMA requests must be enabled for the timer.
+ This parameter can be any combination of @ref HRTIM_Master_DMA_Request_Enable
+ or @ref HRTIM_Timing_Unit_DMA_Request_Enable */
+ uint32_t DMASrcAddress; /*!< Relevant for all HRTIM timers, including the master.
+ Specifies the address of the source address of the DMA transfer */
+ uint32_t DMADstAddress; /*!< Relevant for all HRTIM timers, including the master.
+ Specifies the address of the destination address of the DMA transfer */
+ uint32_t DMASize; /*!< Relevant for all HRTIM timers, including the master.
+ Specifies the size of the DMA transfer */
+ uint32_t HalfModeEnable; /*!< Relevant for all HRTIM timers, including the master.
+ Specifies whether or not half mode is enabled
+ This parameter can be any value of @ref HRTIM_Half_Mode_Enable */
+ uint32_t StartOnSync; /*!< Relevant for all HRTIM timers, including the master.
+ Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled).
+ This parameter can be any value of @ref HRTIM_Start_On_Sync_Input_Event */
+ uint32_t ResetOnSync; /*!< Relevant for all HRTIM timers, including the master.
+ Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled).
+ This parameter can be any value of @ref HRTIM_Reset_On_Sync_Input_Event */
+ uint32_t DACSynchro; /*!< Relevant for all HRTIM timers, including the master.
+ Indicates whether or not the a DAC synchronization event is generated.
+ This parameter can be any value of @ref HRTIM_DAC_Synchronization */
+ uint32_t PreloadEnable; /*!< Relevant for all HRTIM timers, including the master.
+ Specifies whether or not register preload is enabled.
+ This parameter can be any value of @ref HRTIM_Register_Preload_Enable */
+ uint32_t UpdateGating; /*!< Relevant for all HRTIM timers, including the master.
+ Specifies how the update occurs with respect to a burst DMA transaction or
+ update enable inputs (Slave timers only).
+ This parameter can be any value of @ref HRTIM_Update_Gating */
+ uint32_t BurstMode; /*!< Relevant for all HRTIM timers, including the master.
+ Specifies how the timer behaves during a burst mode operation.
+ This parameter can be any value of @ref HRTIM_Timer_Burst_Mode */
+ uint32_t RepetitionUpdate; /*!< Relevant for all HRTIM timers, including the master.
+ Specifies whether or not registers update is triggered by the repetition event.
+ This parameter can be any value of @ref HRTIM_Timer_Repetition_Update */
+ uint32_t PushPull; /*!< Relevant for Timer A to Timer E.
+ Specifies whether or not the push-pull mode is enabled.
+ This parameter can be any value of @ref HRTIM_Timer_Push_Pull_Mode */
+ uint32_t FaultEnable; /*!< Relevant for Timer A to Timer E.
+ Specifies which fault channels are enabled for the timer.
+ This parameter can be a combination of @ref HRTIM_Timer_Fault_Enabling */
+ uint32_t FaultLock; /*!< Relevant for Timer A to Timer E.
+ Specifies whether or not fault enabling status is write protected.
+ This parameter can be a value of @ref HRTIM_Timer_Fault_Lock */
+ uint32_t DeadTimeInsertion; /*!< Relevant for Timer A to Timer E.
+ Specifies whether or not dead-time insertion is enabled for the timer.
+ This parameter can be a value of @ref HRTIM_Timer_Deadtime_Insertion */
+ uint32_t DelayedProtectionMode; /*!< Relevant for Timer A to Timer E.
+ Specifies the delayed protection mode.
+ This parameter can be a value of @ref HRTIM_Timer_Delayed_Protection_Mode */
+ uint32_t UpdateTrigger; /*!< Relevant for Timer A to Timer E.
+ Specifies source(s) triggering the timer registers update.
+ This parameter can be a combination of @ref HRTIM_Timer_Update_Trigger */
+ uint32_t ResetTrigger; /*!< Relevant for Timer A to Timer E.
+ Specifies source(s) triggering the timer counter reset.
+ This parameter can be a combination of @ref HRTIM_Timer_Reset_Trigger */
+ uint32_t ResetUpdate; /*!< Relevant for Timer A to Timer E.
+ Specifies whether or not registers update is triggered when the timer counter is reset.
+ This parameter can be a value of @ref HRTIM_Timer_Reset_Update */
+} HRTIM_TimerCfgTypeDef;
+
+/**
+ * @brief Compare unit configuration definition
+ */
+typedef struct {
+ uint32_t CompareValue; /*!< Specifies the compare value of the timer compare unit.
+ The minimum value must be greater than or equal to 3 periods of the fHRTIM clock.
+ The maximum value must be less than or equal to 0xFFFFU - 1 periods of the fHRTIM clock */
+ uint32_t AutoDelayedMode; /*!< Specifies the auto delayed mode for compare unit 2 or 4.
+ This parameter can be a value of @ref HRTIM_Compare_Unit_Auto_Delayed_Mode */
+ uint32_t AutoDelayedTimeout; /*!< Specifies compare value for timing unit 1 or 3 when auto delayed mode with time out is selected.
+ CompareValue + AutoDelayedTimeout must be less than 0xFFFFU */
+} HRTIM_CompareCfgTypeDef;
+
+/**
+ * @brief Capture unit configuration definition
+ */
+typedef struct {
+ uint32_t Trigger; /*!< Specifies source(s) triggering the capture.
+ This parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger */
+} HRTIM_CaptureCfgTypeDef;
+
+/**
+ * @brief Output configuration definition
+ */
+typedef struct {
+ uint32_t Polarity; /*!< Specifies the output polarity.
+ This parameter can be any value of @ref HRTIM_Output_Polarity */
+ uint32_t SetSource; /*!< Specifies the event(s) transitioning the output from its inactive level to its active level.
+ This parameter can be a combination of @ref HRTIM_Output_Set_Source */
+ uint32_t ResetSource; /*!< Specifies the event(s) transitioning the output from its active level to its inactive level.
+ This parameter can be a combination of @ref HRTIM_Output_Reset_Source */
+ uint32_t IdleMode; /*!< Specifies whether or not the output is affected by a burst mode operation.
+ This parameter can be any value of @ref HRTIM_Output_Idle_Mode */
+ uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state.
+ This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
+ uint32_t FaultLevel; /*!< Specifies whether the output level is active or inactive when in FAULT state.
+ This parameter can be any value of @ref HRTIM_Output_FAULT_Level */
+ uint32_t ChopperModeEnable; /*!< Indicates whether or not the chopper mode is enabled
+ This parameter can be any value of @ref HRTIM_Output_Chopper_Mode_Enable */
+ uint32_t BurstModeEntryDelayed; /*!< Indicates whether or not dead-time is inserted when entering the IDLE state during a burst mode operation.
+ This parameters can be any value of @ref HRTIM_Output_Burst_Mode_Entry_Delayed */
+} HRTIM_OutputCfgTypeDef;
+
+/**
+ * @brief External event filtering in timing units configuration definition
+ */
+typedef struct {
+ uint32_t Filter; /*!< Specifies the type of event filtering within the timing unit.
+ This parameter can be a value of @ref HRTIM_Timer_External_Event_Filter */
+ uint32_t Latch; /*!< Specifies whether or not the signal is latched.
+ This parameter can be a value of @ref HRTIM_Timer_External_Event_Latch */
+} HRTIM_TimerEventFilteringCfgTypeDef;
+
+/**
+ * @brief Dead time feature configuration definition
+ */
+typedef struct {
+ uint32_t Prescaler; /*!< Specifies the Deadtime Prescaler.
+ This parameter can be a value of @ref HRTIM_Deadtime_Prescaler_Ratio */
+ uint32_t RisingValue; /*!< Specifies the Deadtime following a rising edge.
+ This parameter can be a number between 0x0 and 0x1FFU */
+ uint32_t RisingSign; /*!< Specifies whether the deadtime is positive or negative on rising edge.
+ This parameter can be a value of @ref HRTIM_Deadtime_Rising_Sign */
+ uint32_t RisingLock; /*!< Specifies whether or not deadtime rising settings (value and sign) are write protected.
+ This parameter can be a value of @ref HRTIM_Deadtime_Rising_Lock */
+ uint32_t RisingSignLock; /*!< Specifies whether or not deadtime rising sign is write protected.
+ This parameter can be a value of @ref HRTIM_Deadtime_Rising_Sign_Lock */
+ uint32_t FallingValue; /*!< Specifies the Deadtime following a falling edge.
+ This parameter can be a number between 0x0 and 0x1FFU */
+ uint32_t FallingSign; /*!< Specifies whether the deadtime is positive or negative on falling edge.
+ This parameter can be a value of @ref HRTIM_Deadtime_Falling_Sign */
+ uint32_t FallingLock; /*!< Specifies whether or not deadtime falling settings (value and sign) are write protected.
+ This parameter can be a value of @ref HRTIM_Deadtime_Falling_Lock */
+ uint32_t FallingSignLock; /*!< Specifies whether or not deadtime falling sign is write protected.
+ This parameter can be a value of @ref HRTIM_Deadtime_Falling_Sign_Lock */
+} HRTIM_DeadTimeCfgTypeDef ;
+
+/**
+ * @brief Chopper mode configuration definition
+ */
+typedef struct {
+ uint32_t CarrierFreq; /*!< Specifies the Timer carrier frequency value.
+ This parameter can be a value of @ref HRTIM_Chopper_Frequency */
+ uint32_t DutyCycle; /*!< Specifies the Timer chopper duty cycle value.
+ This parameter can be a value of @ref HRTIM_Chopper_Duty_Cycle */
+ uint32_t StartPulse; /*!< Specifies the Timer pulse width value.
+ This parameter can be a value of @ref HRTIM_Chopper_Start_Pulse_Width */
+} HRTIM_ChopperModeCfgTypeDef;
+
+/**
+ * @brief External event channel configuration definition
+ */
+typedef struct {
+ uint32_t Source; /*!< Identifies the source of the external event.
+ This parameter can be a value of @ref HRTIM_External_Event_Sources */
+ uint32_t Polarity; /*!< Specifies the polarity of the external event (in case of level sensitivity).
+ This parameter can be a value of @ref HRTIM_External_Event_Polarity */
+ uint32_t Sensitivity; /*!< Specifies the sensitivity of the external event.
+ This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */
+ uint32_t Filter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter.
+ This parameter can be a value of @ref HRTIM_External_Event_Filter */
+ uint32_t FastMode; /*!< Indicates whether or not low latency mode is enabled for the external event.
+ This parameter can be a value of @ref HRTIM_External_Event_Fast_Mode */
+} HRTIM_EventCfgTypeDef;
+
+/**
+ * @brief Fault channel configuration definition
+ */
+typedef struct {
+ uint32_t Source; /*!< Identifies the source of the fault.
+ This parameter can be a value of @ref HRTIM_Fault_Sources */
+ uint32_t Polarity; /*!< Specifies the polarity of the fault event.
+ This parameter can be a value of @ref HRTIM_Fault_Polarity */
+ uint32_t Filter; /*!< Defines the frequency used to sample the Fault input and the length of the digital filter.
+ This parameter can be a value of @ref HRTIM_Fault_Filter */
+ uint32_t Lock; /*!< Indicates whether or not fault programming bits are write protected.
+ This parameter can be a value of @ref HRTIM_Fault_Lock */
+} HRTIM_FaultCfgTypeDef;
+
+/**
+ * @brief Burst mode configuration definition
+ */
+typedef struct {
+ uint32_t Mode; /*!< Specifies the burst mode operating mode.
+ This parameter can be a value of @ref HRTIM_Burst_Mode_Operating_Mode */
+ uint32_t ClockSource; /*!< Specifies the burst mode clock source.
+ This parameter can be a value of @ref HRTIM_Burst_Mode_Clock_Source */
+ uint32_t Prescaler; /*!< Specifies the burst mode prescaler.
+ This parameter can be a value of @ref HRTIM_Burst_Mode_Prescaler */
+ uint32_t PreloadEnable; /*!< Specifies whether or not preload is enabled for burst mode related registers (HRTIM_BMCMPR and HRTIM_BMPER).
+ This parameter can be a combination of @ref HRTIM_Burst_Mode_Register_Preload_Enable */
+ uint32_t Trigger; /*!< Specifies the event(s) triggering the burst operation.
+ This parameter can be a combination of @ref HRTIM_Burst_Mode_Trigger */
+ uint32_t IdleDuration; /*!< Specifies number of periods during which the selected timers are in idle state.
+ This parameter can be a number between 0x0 and 0xFFFF */
+ uint32_t Period; /*!< Specifies burst mode repetition period.
+ This parameter can be a number between 0x1 and 0xFFFF */
+} HRTIM_BurstModeCfgTypeDef;
+
+/**
+ * @brief ADC trigger configuration definition
+ */
+typedef struct {
+ uint32_t UpdateSource; /*!< Specifies the ADC trigger update source.
+ This parameter can be a combination of @ref HRTIM_ADC_Trigger_Update_Source */
+ uint32_t Trigger; /*!< Specifies the event(s) triggering the ADC conversion.
+ This parameter can be a value of @ref HRTIM_ADC_Trigger_Event */
+} HRTIM_ADCTriggerCfgTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup HRTIM_Exported_Constants HRTIM Exported Constants
+ * @{
+ */
+
+/** @defgroup HRTIM_Timer_Index HRTIM Timer Index
+ * @{
+ * @brief Constants defining the timer indexes
+ */
+#define HRTIM_TIMERINDEX_TIMER_A 0x0U /*!< Index used to access timer A registers */
+#define HRTIM_TIMERINDEX_TIMER_B 0x1U /*!< Index used to access timer B registers */
+#define HRTIM_TIMERINDEX_TIMER_C 0x2U /*!< Index used to access timer C registers */
+#define HRTIM_TIMERINDEX_TIMER_D 0x3U /*!< Index used to access timer D registers */
+#define HRTIM_TIMERINDEX_TIMER_E 0x4U /*!< Index used to access timer E registers */
+#define HRTIM_TIMERINDEX_MASTER 0x5U /*!< Index used to access master registers */
+#define HRTIM_TIMERINDEX_COMMON 0xFFU /*!< Index used to access HRTIM common registers */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Timer_identifier HRTIM Timer identifier
+ * @{
+ * @brief Constants defining timer identifiers
+ */
+#define HRTIM_TIMERID_MASTER (HRTIM_MCR_MCEN) /*!< Master identifier*/
+#define HRTIM_TIMERID_TIMER_A (HRTIM_MCR_TACEN) /*!< Timer A identifier */
+#define HRTIM_TIMERID_TIMER_B (HRTIM_MCR_TBCEN) /*!< Timer B identifier */
+#define HRTIM_TIMERID_TIMER_C (HRTIM_MCR_TCCEN) /*!< Timer C identifier */
+#define HRTIM_TIMERID_TIMER_D (HRTIM_MCR_TDCEN) /*!< Timer D identifier */
+#define HRTIM_TIMERID_TIMER_E (HRTIM_MCR_TECEN) /*!< Timer E identifier */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Compare_Unit HRTIM Compare Unit
+ * @{
+ * @brief Constants defining compare unit identifiers
+ */
+#define HRTIM_COMPAREUNIT_1 0x00000001U /*!< Compare unit 1 identifier */
+#define HRTIM_COMPAREUNIT_2 0x00000002U /*!< Compare unit 2 identifier */
+#define HRTIM_COMPAREUNIT_3 0x00000004U /*!< Compare unit 3 identifier */
+#define HRTIM_COMPAREUNIT_4 0x00000008U /*!< Compare unit 4 identifier */
+ /**
+ * @}
+ */
+
+/** @defgroup HRTIM_Capture_Unit HRTIM Capture Unit
+ * @{
+ * @brief Constants defining capture unit identifiers
+ */
+#define HRTIM_CAPTUREUNIT_1 0x00000001U /*!< Capture unit 1 identifier */
+#define HRTIM_CAPTUREUNIT_2 0x00000002U /*!< Capture unit 2 identifier */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Timer_Output HRTIM Timer Output
+ * @{
+ * @brief Constants defining timer output identifiers
+ */
+#define HRTIM_OUTPUT_TA1 0x00000001U /*!< Timer A - Output 1 identifier */
+#define HRTIM_OUTPUT_TA2 0x00000002U /*!< Timer A - Output 2 identifier */
+#define HRTIM_OUTPUT_TB1 0x00000004U /*!< Timer B - Output 1 identifier */
+#define HRTIM_OUTPUT_TB2 0x00000008U /*!< Timer B - Output 2 identifier */
+#define HRTIM_OUTPUT_TC1 0x00000010U /*!< Timer C - Output 1 identifier */
+#define HRTIM_OUTPUT_TC2 0x00000020U /*!< Timer C - Output 2 identifier */
+#define HRTIM_OUTPUT_TD1 0x00000040U /*!< Timer D - Output 1 identifier */
+#define HRTIM_OUTPUT_TD2 0x00000080U /*!< Timer D - Output 2 identifier */
+#define HRTIM_OUTPUT_TE1 0x00000100U /*!< Timer E - Output 1 identifier */
+#define HRTIM_OUTPUT_TE2 0x00000200U /*!< Timer E - Output 2 identifier */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_ADC_Trigger HRTIM ADC Trigger
+ * @{
+ * @brief Constants defining ADC triggers identifiers
+ */
+#define HRTIM_ADCTRIGGER_1 0x00000001U /*!< ADC trigger 1 identifier */
+#define HRTIM_ADCTRIGGER_2 0x00000002U /*!< ADC trigger 2 identifier */
+#define HRTIM_ADCTRIGGER_3 0x00000004U /*!< ADC trigger 3 identifier */
+#define HRTIM_ADCTRIGGER_4 0x00000008U /*!< ADC trigger 4 identifier */
+
+#define IS_HRTIM_ADCTRIGGER(ADCTRIGGER)\
+ (((ADCTRIGGER) == HRTIM_ADCTRIGGER_1) || \
+ ((ADCTRIGGER) == HRTIM_ADCTRIGGER_2) || \
+ ((ADCTRIGGER) == HRTIM_ADCTRIGGER_3) || \
+ ((ADCTRIGGER) == HRTIM_ADCTRIGGER_4))
+/**
+ * @}
+ */
+/** @defgroup HRTIM_External_Event_Channels HRTIM External Event Channels
+ * @{
+ * @brief Constants defining external event channel identifiers
+ */
+#define HRTIM_EVENT_NONE (0x00000000U) /*!< Undefined event channel */
+#define HRTIM_EVENT_1 (0x00000001U) /*!< External event channel 1 identifier */
+#define HRTIM_EVENT_2 (0x00000002U) /*!< External event channel 2 identifier */
+#define HRTIM_EVENT_3 (0x00000003U) /*!< External event channel 3 identifier */
+#define HRTIM_EVENT_4 (0x00000004U) /*!< External event channel 4 identifier */
+#define HRTIM_EVENT_5 (0x00000005U) /*!< External event channel 5 identifier */
+#define HRTIM_EVENT_6 (0x00000006U) /*!< External event channel 6 identifier */
+#define HRTIM_EVENT_7 (0x00000007U) /*!< External event channel 7 identifier */
+#define HRTIM_EVENT_8 (0x00000008U) /*!< External event channel 8 identifier */
+#define HRTIM_EVENT_9 (0x00000009U) /*!< External event channel 9 identifier */
+#define HRTIM_EVENT_10 (0x00000010U) /*!< External event channel 10 identifier */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Fault_Channel HRTIM Fault Channel
+ * @{
+ * @brief Constants defining fault channel identifiers
+ */
+#define HRTIM_FAULT_1 (0x01U) /*!< Fault channel 1 identifier */
+#define HRTIM_FAULT_2 (0x02U) /*!< Fault channel 2 identifier */
+#define HRTIM_FAULT_3 (0x04U) /*!< Fault channel 3 identifier */
+#define HRTIM_FAULT_4 (0x08U) /*!< Fault channel 4 identifier */
+#define HRTIM_FAULT_5 (0x10U) /*!< Fault channel 5 identifier */
+/**
+ * @}
+ */
+
+
+ /** @defgroup HRTIM_Prescaler_Ratio HRTIM Prescaler Ratio
+ * @{
+ * @brief Constants defining timer high-resolution clock prescaler ratio.
+ */
+#define HRTIM_PRESCALERRATIO_MUL32 (0x00000000U) /*!< fHRCK: fHRTIM x 32U = 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz) */
+#define HRTIM_PRESCALERRATIO_MUL16 (0x00000001U) /*!< fHRCK: fHRTIM x 16U = 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz) */
+#define HRTIM_PRESCALERRATIO_MUL8 (0x00000002U) /*!< fHRCK: fHRTIM x 8U = 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz) */
+#define HRTIM_PRESCALERRATIO_MUL4 (0x00000003U) /*!< fHRCK: fHRTIM x 4U = 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz) */
+#define HRTIM_PRESCALERRATIO_MUL2 (0x00000004U) /*!< fHRCK: fHRTIM x 2U = 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz) */
+#define HRTIM_PRESCALERRATIO_DIV1 (0x00000005U) /*!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) */
+#define HRTIM_PRESCALERRATIO_DIV2 (0x00000006U) /*!< fHRCK: fHRTIM / 2U = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) */
+#define HRTIM_PRESCALERRATIO_DIV4 (0x00000007U) /*!< fHRCK: fHRTIM / 4U = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Counter_Operating_Mode HRTIM Counter Operating Mode
+ * @{
+ * @brief Constants defining timer counter operating mode.
+ */
+#define HRTIM_MODE_CONTINUOUS (0x00000008U) /*!< The timer operates in continuous (free-running) mode */
+#define HRTIM_MODE_SINGLESHOT (0x00000000U) /*!< The timer operates in non retriggerable single-shot mode */
+#define HRTIM_MODE_SINGLESHOT_RETRIGGERABLE (0x00000010U) /*!< The timer operates in retriggerable single-shot mode */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Half_Mode_Enable HRTIM Half Mode Enable
+ * @{
+ * @brief Constants defining half mode enabling status.
+ */
+#define HRTIM_HALFMODE_DISABLED (0x00000000U) /*!< Half mode is disabled */
+#define HRTIM_HALFMODE_ENABLED (0x00000020U) /*!< Half mode is enabled */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Start_On_Sync_Input_Event HRTIM Start On Sync Input Event
+ * @{
+ * @brief Constants defining the timer behavior following the synchronization event
+ */
+#define HRTIM_SYNCSTART_DISABLED (0x00000000U) /*!< Synchronization input event has effect on the timer */
+#define HRTIM_SYNCSTART_ENABLED (HRTIM_MCR_SYNCSTRTM) /*!< Synchronization input event starts the timer */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Reset_On_Sync_Input_Event HRTIM Reset On Sync Input Event
+ * @{
+ * @brief Constants defining the timer behavior following the synchronization event
+ */
+#define HRTIM_SYNCRESET_DISABLED (0x00000000U) /*!< Synchronization input event has effect on the timer */
+#define HRTIM_SYNCRESET_ENABLED (HRTIM_MCR_SYNCRSTM) /*!< Synchronization input event resets the timer */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_DAC_Synchronization HRTIM DAC Synchronization
+ * @{
+ * @brief Constants defining on which output the DAC synchronization event is sent
+ */
+#define HRTIM_DACSYNC_NONE 0x00000000U /*!< No DAC synchronization event generated */
+#define HRTIM_DACSYNC_DACTRIGOUT_1 (HRTIM_MCR_DACSYNC_0) /*!< DAC synchronization event generated on DACTrigOut1 output upon timer update */
+#define HRTIM_DACSYNC_DACTRIGOUT_2 (HRTIM_MCR_DACSYNC_1) /*!< DAC synchronization event generated on DACTrigOut2 output upon timer update */
+#define HRTIM_DACSYNC_DACTRIGOUT_3 (HRTIM_MCR_DACSYNC_1 | HRTIM_MCR_DACSYNC_0) /*!< DAC update generated on DACTrigOut3 output upon timer update */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Register_Preload_Enable HRTIM Register Preload Enable
+ * @{
+ * @brief Constants defining whether a write access into a preloadable
+ * register is done into the active or the preload register.
+ */
+#define HRTIM_PRELOAD_DISABLED (0x00000000U) /*!< Preload disabled: the write access is directly done into the active register */
+#define HRTIM_PRELOAD_ENABLED (HRTIM_MCR_PREEN) /*!< Preload enabled: the write access is done into the preload register */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Update_Gating HRTIM Update Gating
+ * @{
+ * @brief Constants defining how the update occurs relatively to the burst DMA
+ * transaction and the external update request on update enable inputs 1 to 3.
+ */
+#define HRTIM_UPDATEGATING_INDEPENDENT 0x00000000U /*!< Update done independently from the DMA burst transfer completion */
+#define HRTIM_UPDATEGATING_DMABURST (HRTIM_TIMCR_UPDGAT_0) /*!< Update done when the DMA burst transfer is completed */
+#define HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1) /*!< Update done on timer roll-over following a DMA burst transfer completion*/
+#define HRTIM_UPDATEGATING_UPDEN1 (HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 1U */
+#define HRTIM_UPDATEGATING_UPDEN2 (HRTIM_TIMCR_UPDGAT_2) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 2U */
+#define HRTIM_UPDATEGATING_UPDEN3 (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 3U */
+#define HRTIM_UPDATEGATING_UPDEN1_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 1U */
+#define HRTIM_UPDATEGATING_UPDEN2_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 2U */
+#define HRTIM_UPDATEGATING_UPDEN3_UPDATE (HRTIM_TIMCR_UPDGAT_3) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 3U */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Timer_Burst_Mode HRTIM Timer Burst Mode
+ * @{
+ * @brief Constants defining how the timer behaves during a burst
+ mode operation.
+ */
+#define HRTIM_TIMERBURSTMODE_MAINTAINCLOCK 0x000000U /*!< Timer counter clock is maintained and the timer operates normally */
+#define HRTIM_TIMERBURSTMODE_RESETCOUNTER (HRTIM_BMCR_MTBM) /*!< Timer counter clock is stopped and the counter is reset */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Timer_Repetition_Update HRTIM Timer Repetition Update
+ * @{
+ * @brief Constants defining whether registers are updated when the timer
+ * repetition period is completed (either due to roll-over or
+ * reset events)
+ */
+#define HRTIM_UPDATEONREPETITION_DISABLED 0x00000000U /*!< Update on repetition disabled */
+#define HRTIM_UPDATEONREPETITION_ENABLED (HRTIM_MCR_MREPU) /*!< Update on repetition enabled */
+/**
+ * @}
+ */
+
+
+/** @defgroup HRTIM_Timer_Push_Pull_Mode HRTIM Timer Push Pull Mode
+ * @{
+ * @brief Constants defining whether or not the puhs-pull mode is enabled for
+ * a timer.
+ */
+#define HRTIM_TIMPUSHPULLMODE_DISABLED (0x00000000U) /*!< Push-Pull mode disabled */
+#define HRTIM_TIMPUSHPULLMODE_ENABLED ((uint32_t)HRTIM_TIMCR_PSHPLL) /*!< Push-Pull mode enabled */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Timer_Fault_Enabling HRTIM Timer Fault Enabling
+ * @{
+ * @brief Constants defining whether a faut channel is enabled for a timer
+ */
+#define HRTIM_TIMFAULTENABLE_NONE 0x00000000U /*!< No fault enabled */
+#define HRTIM_TIMFAULTENABLE_FAULT1 (HRTIM_FLTR_FLT1EN) /*!< Fault 1 enabled */
+#define HRTIM_TIMFAULTENABLE_FAULT2 (HRTIM_FLTR_FLT2EN) /*!< Fault 2 enabled */
+#define HRTIM_TIMFAULTENABLE_FAULT3 (HRTIM_FLTR_FLT3EN) /*!< Fault 3 enabled */
+#define HRTIM_TIMFAULTENABLE_FAULT4 (HRTIM_FLTR_FLT4EN) /*!< Fault 4 enabled */
+#define HRTIM_TIMFAULTENABLE_FAULT5 (HRTIM_FLTR_FLT5EN) /*!< Fault 5 enabled */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Timer_Fault_Lock HRTIM Timer Fault Lock
+ * @{
+ * @brief Constants defining whether or not fault enabling bits are write
+ * protected for a timer
+ */
+#define HRTIM_TIMFAULTLOCK_READWRITE (0x00000000U) /*!< Timer fault enabling bits are read/write */
+#define HRTIM_TIMFAULTLOCK_READONLY (HRTIM_FLTR_FLTLCK) /*!< Timer fault enabling bits are read only */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Timer_Deadtime_Insertion HRTIM Timer Deadtime Insertion
+ * @{
+ * @brief Constants defining whether or not fault the dead time insertion
+ * feature is enabled for a timer
+ */
+#define HRTIM_TIMDEADTIMEINSERTION_DISABLED (0x00000000U) /*!< Output 1 and output 2 signals are independent */
+#define HRTIM_TIMDEADTIMEINSERTION_ENABLED HRTIM_OUTR_DTEN /*!< Deadtime is inserted between output 1 and output 2U */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Timer_Delayed_Protection_Mode HRTIM Timer Delayed Protection Mode
+ * @{
+ * @brief Constants defining all possible delayed protection modes
+ * for a timer. Also definethe source and outputs on which the delayed
+ * protection schemes are applied
+ */
+#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED (0x00000000U) /*!< No action */
+#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 (HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 delayed Idle on external Event 6U */
+#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 6U */
+#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 and output 2 delayed Idle on external Event 6U */
+#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Balanced Idle on external Event 6U */
+#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 delayed Idle on external Event 7U */
+#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 7U */
+#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 and output2 delayed Idle on external Event 7U */
+#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Balanced Idle on external Event 7U */
+
+#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DISABLED (0x00000000U) /*!< No action */
+#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_EEV8 (HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 delayed Idle on external Event 6U */
+#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_EEV8 (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 2 delayed Idle on external Event 6U */
+#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 and output 2 delayed Idle on external Event 6U */
+#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Balanced Idle on external Event 6U */
+#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_DEEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 delayed Idle on external Event 7U */
+#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_DEEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 2 delayed Idle on external Event 7U */
+#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 and output2 delayed Idle on external Event 7U */
+#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Balanced Idle on external Event 7U */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Timer_Update_Trigger HRTIM Timer Update Trigger
+ * @{
+ * @brief Constants defining whether the registers update is done synchronously
+ * with any other timer or master update
+ */
+#define HRTIM_TIMUPDATETRIGGER_NONE 0x00000000U /*!< Register update is disabled */
+#define HRTIM_TIMUPDATETRIGGER_MASTER (HRTIM_TIMCR_MSTU) /*!< Register update is triggered by the master timer update */
+#define HRTIM_TIMUPDATETRIGGER_TIMER_A (HRTIM_TIMCR_TAU) /*!< Register update is triggered by the timer A update */
+#define HRTIM_TIMUPDATETRIGGER_TIMER_B (HRTIM_TIMCR_TBU) /*!< Register update is triggered by the timer B update */
+#define HRTIM_TIMUPDATETRIGGER_TIMER_C (HRTIM_TIMCR_TCU) /*!< Register update is triggered by the timer C update*/
+#define HRTIM_TIMUPDATETRIGGER_TIMER_D (HRTIM_TIMCR_TDU) /*!< Register update is triggered by the timer D update */
+#define HRTIM_TIMUPDATETRIGGER_TIMER_E (HRTIM_TIMCR_TEU) /*!< Register update is triggered by the timer E update */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Timer_Reset_Trigger HRTIM Timer Reset Trigger
+ * @{
+ * @brief Constants defining the events that can be selected to trigger the reset
+ * of the timer counter
+ */
+#define HRTIM_TIMRESETTRIGGER_NONE 0x00000000U /*!< No counter reset trigger */
+#define HRTIM_TIMRESETTRIGGER_UPDATE (HRTIM_RSTR_UPDATE) /*!< The timer counter is reset upon update event */
+#define HRTIM_TIMRESETTRIGGER_CMP2 (HRTIM_RSTR_CMP2) /*!< The timer counter is reset upon Timer Compare 2 event */
+#define HRTIM_TIMRESETTRIGGER_CMP4 (HRTIM_RSTR_CMP4) /*!< The timer counter is reset upon Timer Compare 4 event */
+#define HRTIM_TIMRESETTRIGGER_MASTER_PER (HRTIM_RSTR_MSTPER) /*!< The timer counter is reset upon master timer period event */
+#define HRTIM_TIMRESETTRIGGER_MASTER_CMP1 (HRTIM_RSTR_MSTCMP1) /*!< The timer counter is reset upon master timer Compare 1 event */
+#define HRTIM_TIMRESETTRIGGER_MASTER_CMP2 (HRTIM_RSTR_MSTCMP2) /*!< The timer counter is reset upon master timer Compare 2 event */
+#define HRTIM_TIMRESETTRIGGER_MASTER_CMP3 (HRTIM_RSTR_MSTCMP3) /*!< The timer counter is reset upon master timer Compare 3 event */
+#define HRTIM_TIMRESETTRIGGER_MASTER_CMP4 (HRTIM_RSTR_MSTCMP4) /*!< The timer counter is reset upon master timer Compare 4 event */
+#define HRTIM_TIMRESETTRIGGER_EEV_1 (HRTIM_RSTR_EXTEVNT1) /*!< The timer counter is reset upon external event 1U */
+#define HRTIM_TIMRESETTRIGGER_EEV_2 (HRTIM_RSTR_EXTEVNT2) /*!< The timer counter is reset upon external event 2U */
+#define HRTIM_TIMRESETTRIGGER_EEV_3 (HRTIM_RSTR_EXTEVNT3) /*!< The timer counter is reset upon external event 3U */
+#define HRTIM_TIMRESETTRIGGER_EEV_4 (HRTIM_RSTR_EXTEVNT4) /*!< The timer counter is reset upon external event 4U */
+#define HRTIM_TIMRESETTRIGGER_EEV_5 (HRTIM_RSTR_EXTEVNT5) /*!< The timer counter is reset upon external event 5U */
+#define HRTIM_TIMRESETTRIGGER_EEV_6 (HRTIM_RSTR_EXTEVNT6) /*!< The timer counter is reset upon external event 6U */
+#define HRTIM_TIMRESETTRIGGER_EEV_7 (HRTIM_RSTR_EXTEVNT7) /*!< The timer counter is reset upon external event 7U */
+#define HRTIM_TIMRESETTRIGGER_EEV_8 (HRTIM_RSTR_EXTEVNT8) /*!< The timer counter is reset upon external event 8U */
+#define HRTIM_TIMRESETTRIGGER_EEV_9 (HRTIM_RSTR_EXTEVNT9) /*!< The timer counter is reset upon external event 9U */
+#define HRTIM_TIMRESETTRIGGER_EEV_10 (HRTIM_RSTR_EXTEVNT10) /*!< The timer counter is reset upon external event 10U */
+#define HRTIM_TIMRESETTRIGGER_OTHER1_CMP1 (HRTIM_RSTR_TIMBCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */
+#define HRTIM_TIMRESETTRIGGER_OTHER1_CMP2 (HRTIM_RSTR_TIMBCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */
+#define HRTIM_TIMRESETTRIGGER_OTHER1_CMP4 (HRTIM_RSTR_TIMBCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */
+#define HRTIM_TIMRESETTRIGGER_OTHER2_CMP1 (HRTIM_RSTR_TIMCCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */
+#define HRTIM_TIMRESETTRIGGER_OTHER2_CMP2 (HRTIM_RSTR_TIMCCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */
+#define HRTIM_TIMRESETTRIGGER_OTHER2_CMP4 (HRTIM_RSTR_TIMCCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */
+#define HRTIM_TIMRESETTRIGGER_OTHER3_CMP1 (HRTIM_RSTR_TIMDCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */
+#define HRTIM_TIMRESETTRIGGER_OTHER3_CMP2 (HRTIM_RSTR_TIMDCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */
+#define HRTIM_TIMRESETTRIGGER_OTHER3_CMP4 (HRTIM_RSTR_TIMDCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */
+#define HRTIM_TIMRESETTRIGGER_OTHER4_CMP1 (HRTIM_RSTR_TIMECMP1) /*!< The timer counter is reset upon other timer Compare 1 event */
+#define HRTIM_TIMRESETTRIGGER_OTHER4_CMP2 (HRTIM_RSTR_TIMECMP2) /*!< The timer counter is reset upon other timer Compare 2 event */
+#define HRTIM_TIMRESETTRIGGER_OTHER4_CMP4 (HRTIM_RSTR_TIMECMP4) /*!< The timer counter is reset upon other timer Compare 4 event */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Timer_Reset_Update HRTIM Timer Reset Update
+ * @{
+ * @brief Constants defining whether the register are updated upon Timerx
+ * counter reset or roll-over to 0 after reaching the period value
+ * in continuous mode
+ */
+#define HRTIM_TIMUPDATEONRESET_DISABLED 0x00000000U /*!< Update by timer x reset / roll-over disabled */
+#define HRTIM_TIMUPDATEONRESET_ENABLED (HRTIM_TIMCR_TRSTU) /*!< Update by timer x reset / roll-over enabled */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Compare_Unit_Auto_Delayed_Mode HRTIM Compare Unit Auto Delayed Mode
+ * @{
+ * @brief Constants defining whether the compare register is behaving in
+ * regular mode (compare match issued as soon as counter equal compare),
+ * or in auto-delayed mode
+ */
+#define HRTIM_AUTODELAYEDMODE_REGULAR (0x00000000U) /*!< standard compare mode */
+#define HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT (HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated only if a capture has occurred */
+#define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1 (HRTIM_TIMCR_DELCMP2_1) /*!< Compare event generated if a capture has occurred or after a Compare 1 match (timeout if capture event is missing) */
+#define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3 (HRTIM_TIMCR_DELCMP2_1 | HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated if a capture has occurred or after a Compare 3 match (timeout if capture event is missing) */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Simple_OC_Mode HRTIM Simple OC Mode
+ * @{
+ * @brief Constants defining the behavior of the output signal when the timer
+ operates in basic output compare mode
+ */
+#define HRTIM_BASICOCMODE_TOGGLE (0x00000001U) /*!< Output toggles when the timer counter reaches the compare value */
+#define HRTIM_BASICOCMODE_INACTIVE (0x00000002U) /*!< Output forced to active level when the timer counter reaches the compare value */
+#define HRTIM_BASICOCMODE_ACTIVE (0x00000003U) /*!< Output forced to inactive level when the timer counter reaches the compare value */
+
+#define IS_HRTIM_BASICOCMODE(BASICOCMODE)\
+ (((BASICOCMODE) == HRTIM_BASICOCMODE_TOGGLE) || \
+ ((BASICOCMODE) == HRTIM_BASICOCMODE_INACTIVE) || \
+ ((BASICOCMODE) == HRTIM_BASICOCMODE_ACTIVE))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Output_Polarity HRTIM Output Polarity
+ * @{
+ * @brief Constants defining the polarity of a timer output
+ */
+#define HRTIM_OUTPUTPOLARITY_HIGH (0x00000000U) /*!< Output is acitve HIGH */
+#define HRTIM_OUTPUTPOLARITY_LOW (HRTIM_OUTR_POL1) /*!< Output is active LOW */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Output_Set_Source HRTIM Output Set Source
+ * @{
+ * @brief Constants defining the events that can be selected to configure the
+ * set crossbar of a timer output
+ */
+#define HRTIM_OUTPUTSET_NONE 0x00000000U /*!< Reset the output set crossbar */
+#define HRTIM_OUTPUTSET_RESYNC (HRTIM_SET1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMPER (HRTIM_SET1R_PER) /*!< Timer period event forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMCMP1 (HRTIM_SET1R_CMP1) /*!< Timer compare 1 event forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMCMP2 (HRTIM_SET1R_CMP2) /*!< Timer compare 2 event forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMCMP3 (HRTIM_SET1R_CMP3) /*!< Timer compare 3 event forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMCMP4 (HRTIM_SET1R_CMP4) /*!< Timer compare 4 event forces the output to its active state */
+#define HRTIM_OUTPUTSET_MASTERPER (HRTIM_SET1R_MSTPER) /*!< The master timer period event forces the output to its active state */
+#define HRTIM_OUTPUTSET_MASTERCMP1 (HRTIM_SET1R_MSTCMP1) /*!< Master Timer compare 1 event forces the output to its active state */
+#define HRTIM_OUTPUTSET_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its active state */
+#define HRTIM_OUTPUTSET_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its active state */
+#define HRTIM_OUTPUTSET_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_1 (HRTIM_SET1R_EXTVNT1) /*!< External event 1 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_2 (HRTIM_SET1R_EXTVNT2) /*!< External event 2 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_3 (HRTIM_SET1R_EXTVNT3) /*!< External event 3 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_4 (HRTIM_SET1R_EXTVNT4) /*!< External event 4 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_5 (HRTIM_SET1R_EXTVNT5) /*!< External event 5 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_6 (HRTIM_SET1R_EXTVNT6) /*!< External event 6 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_7 (HRTIM_SET1R_EXTVNT7) /*!< External event 7 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_8 (HRTIM_SET1R_EXTVNT8) /*!< External event 8 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_9 (HRTIM_SET1R_EXTVNT9) /*!< External event 9 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_10 (HRTIM_SET1R_EXTVNT10) /*!< External event 10 forces the output to its active state */
+#define HRTIM_OUTPUTSET_UPDATE (HRTIM_SET1R_UPDATE) /*!< Timer register update event forces the output to its active state */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Output_Reset_Source HRTIM Output Reset Source
+ * @{
+ * @brief Constants defining the events that can be selected to configure the
+ * set crossbar of a timer output
+ */
+#define HRTIM_OUTPUTRESET_NONE 0x00000000U /*!< Reset the output reset crossbar */
+#define HRTIM_OUTPUTRESET_RESYNC (HRTIM_RST1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMPER (HRTIM_RST1R_PER) /*!< Timer period event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMCMP1 (HRTIM_RST1R_CMP1) /*!< Timer compare 1 event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMCMP2 (HRTIM_RST1R_CMP2) /*!< Timer compare 2 event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMCMP3 (HRTIM_RST1R_CMP3) /*!< Timer compare 3 event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMCMP4 (HRTIM_RST1R_CMP4) /*!< Timer compare 4 event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_MASTERPER (HRTIM_RST1R_MSTPER) /*!< The master timer period event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_MASTERCMP1 (HRTIM_RST1R_MSTCMP1) /*!< Master Timer compare 1 event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_1 (HRTIM_RST1R_EXTVNT1) /*!< External event 1 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_2 (HRTIM_RST1R_EXTVNT2) /*!< External event 2 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_3 (HRTIM_RST1R_EXTVNT3) /*!< External event 3 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_4 (HRTIM_RST1R_EXTVNT4) /*!< External event 4 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_5 (HRTIM_RST1R_EXTVNT5) /*!< External event 5 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_6 (HRTIM_RST1R_EXTVNT6) /*!< External event 6 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_7 (HRTIM_RST1R_EXTVNT7) /*!< External event 7 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_8 (HRTIM_RST1R_EXTVNT8) /*!< External event 8 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_9 (HRTIM_RST1R_EXTVNT9) /*!< External event 9 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_10 (HRTIM_RST1R_EXTVNT10) /*!< External event 10 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_UPDATE (HRTIM_RST1R_UPDATE) /*!< Timer register update event forces the output to its inactive state */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Output_Idle_Mode HRTIM Output Idle Mode
+ * @{
+ * @brief Constants defining whether or not the timer output transition to its
+ IDLE state when burst mode is entered
+ */
+#define HRTIM_OUTPUTIDLEMODE_NONE 0x00000000U /*!< The output is not affected by the burst mode operation */
+#define HRTIM_OUTPUTIDLEMODE_IDLE (HRTIM_OUTR_IDLM1) /*!< The output is in idle state when requested by the burst mode controller */
+ /**
+ * @}
+ */
+
+/** @defgroup HRTIM_Output_IDLE_Level HRTIM Output IDLE Level
+ * @{
+ * @brief Constants defining the output level when output is in IDLE state
+ */
+#define HRTIM_OUTPUTIDLELEVEL_INACTIVE 0x00000000U /*!< Output at inactive level when in IDLE state */
+#define HRTIM_OUTPUTIDLELEVEL_ACTIVE (HRTIM_OUTR_IDLES1) /*!< Output at active level when in IDLE state */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Output_FAULT_Level HRTIM Output FAULT Level
+ * @{
+ * @brief Constants defining the output level when output is in FAULT state
+ */
+#define HRTIM_OUTPUTFAULTLEVEL_NONE 0x00000000U /*!< The output is not affected by the fault input */
+#define HRTIM_OUTPUTFAULTLEVEL_ACTIVE (HRTIM_OUTR_FAULT1_0) /*!< Output at active level when in FAULT state */
+#define HRTIM_OUTPUTFAULTLEVEL_INACTIVE (HRTIM_OUTR_FAULT1_1) /*!< Output at inactive level when in FAULT state */
+#define HRTIM_OUTPUTFAULTLEVEL_HIGHZ (HRTIM_OUTR_FAULT1_1 | HRTIM_OUTR_FAULT1_0) /*!< Output is tri-stated when in FAULT state */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Output_Chopper_Mode_Enable HRTIM Output Chopper Mode Enable
+ * @{
+ * @brief Constants defining whether or not chopper mode is enabled for a timer
+ output
+ */
+#define HRTIM_OUTPUTCHOPPERMODE_DISABLED 0x00000000U /*!< Output signal is not altered */
+#define HRTIM_OUTPUTCHOPPERMODE_ENABLED (HRTIM_OUTR_CHP1) /*!< Output signal is chopped by a carrier signal */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Output_Burst_Mode_Entry_Delayed HRTIM Output Burst Mode Entry Delayed
+ * @{
+ * @brief Constants defining the idle mode entry is delayed by forcing a
+ deadtime insertion before switching the outputs to their idle state
+ */
+#define HRTIM_OUTPUTBURSTMODEENTRY_REGULAR 0x00000000U /*!< The programmed Idle state is applied immediately to the Output */
+#define HRTIM_OUTPUTBURSTMODEENTRY_DELAYED (HRTIM_OUTR_DIDL1) /*!< Deadtime is inserted on output before entering the idle mode */
+/**
+ * @}
+ */
+
+
+/** @defgroup HRTIM_Capture_Unit_Trigger HRTIM Capture Unit Trigger
+ * @{
+ * @brief Constants defining the events that can be selected to trigger the
+ * capture of the timing unit counter
+ */
+#define HRTIM_CAPTURETRIGGER_NONE 0x00000000U /*!< Capture trigger is disabled */
+#define HRTIM_CAPTURETRIGGER_UPDATE (HRTIM_CPT1CR_UPDCPT) /*!< The update event triggers the Capture */
+#define HRTIM_CAPTURETRIGGER_EEV_1 (HRTIM_CPT1CR_EXEV1CPT) /*!< The External event 1 triggers the Capture */
+#define HRTIM_CAPTURETRIGGER_EEV_2 (HRTIM_CPT1CR_EXEV2CPT) /*!< The External event 2 triggers the Capture */
+#define HRTIM_CAPTURETRIGGER_EEV_3 (HRTIM_CPT1CR_EXEV3CPT) /*!< The External event 3 triggers the Capture */
+#define HRTIM_CAPTURETRIGGER_EEV_4 (HRTIM_CPT1CR_EXEV4CPT) /*!< The External event 4 triggers the Capture */
+#define HRTIM_CAPTURETRIGGER_EEV_5 (HRTIM_CPT1CR_EXEV5CPT) /*!< The External event 5 triggers the Capture */
+#define HRTIM_CAPTURETRIGGER_EEV_6 (HRTIM_CPT1CR_EXEV6CPT) /*!< The External event 6 triggers the Capture */
+#define HRTIM_CAPTURETRIGGER_EEV_7 (HRTIM_CPT1CR_EXEV7CPT) /*!< The External event 7 triggers the Capture */
+#define HRTIM_CAPTURETRIGGER_EEV_8 (HRTIM_CPT1CR_EXEV8CPT) /*!< The External event 8 triggers the Capture */
+#define HRTIM_CAPTURETRIGGER_EEV_9 (HRTIM_CPT1CR_EXEV9CPT) /*!< The External event 9 triggers the Capture */
+#define HRTIM_CAPTURETRIGGER_EEV_10 (HRTIM_CPT1CR_EXEV10CPT) /*!< The External event 10 triggers the Capture */
+#define HRTIM_CAPTURETRIGGER_TA1_SET (HRTIM_CPT1CR_TA1SET) /*!< Capture is triggered by TA1 output inactive to active transition */
+#define HRTIM_CAPTURETRIGGER_TA1_RESET (HRTIM_CPT1CR_TA1RST) /*!< Capture is triggered by TA1 output active to inactive transition */
+#define HRTIM_CAPTURETRIGGER_TIMERA_CMP1 (HRTIM_CPT1CR_TIMACMP1) /*!< Timer A Compare 1 triggers Capture */
+#define HRTIM_CAPTURETRIGGER_TIMERA_CMP2 (HRTIM_CPT1CR_TIMACMP2) /*!< Timer A Compare 2 triggers Capture */
+#define HRTIM_CAPTURETRIGGER_TB1_SET (HRTIM_CPT1CR_TB1SET) /*!< Capture is triggered by TB1 output inactive to active transition */
+#define HRTIM_CAPTURETRIGGER_TB1_RESET (HRTIM_CPT1CR_TB1RST) /*!< Capture is triggered by TB1 output active to inactive transition */
+#define HRTIM_CAPTURETRIGGER_TIMERB_CMP1 (HRTIM_CPT1CR_TIMBCMP1) /*!< Timer B Compare 1 triggers Capture */
+#define HRTIM_CAPTURETRIGGER_TIMERB_CMP2 (HRTIM_CPT1CR_TIMBCMP2) /*!< Timer B Compare 2 triggers Capture */
+#define HRTIM_CAPTURETRIGGER_TC1_SET (HRTIM_CPT1CR_TC1SET) /*!< Capture is triggered by TC1 output inactive to active transition */
+#define HRTIM_CAPTURETRIGGER_TC1_RESET (HRTIM_CPT1CR_TC1RST) /*!< Capture is triggered by TC1 output active to inactive transition */
+#define HRTIM_CAPTURETRIGGER_TIMERC_CMP1 (HRTIM_CPT1CR_TIMCCMP1) /*!< Timer C Compare 1 triggers Capture */
+#define HRTIM_CAPTURETRIGGER_TIMERC_CMP2 (HRTIM_CPT1CR_TIMCCMP2) /*!< Timer C Compare 2 triggers Capture */
+#define HRTIM_CAPTURETRIGGER_TD1_SET (HRTIM_CPT1CR_TD1SET) /*!< Capture is triggered by TD1 output inactive to active transition */
+#define HRTIM_CAPTURETRIGGER_TD1_RESET (HRTIM_CPT1CR_TD1RST) /*!< Capture is triggered by TD1 output active to inactive transition */
+#define HRTIM_CAPTURETRIGGER_TIMERD_CMP1 (HRTIM_CPT1CR_TIMDCMP1) /*!< Timer D Compare 1 triggers Capture */
+#define HRTIM_CAPTURETRIGGER_TIMERD_CMP2 (HRTIM_CPT1CR_TIMDCMP2) /*!< Timer D Compare 2 triggers Capture */
+#define HRTIM_CAPTURETRIGGER_TE1_SET (HRTIM_CPT1CR_TE1SET) /*!< Capture is triggered by TE1 output inactive to active transition */
+#define HRTIM_CAPTURETRIGGER_TE1_RESET (HRTIM_CPT1CR_TE1RST) /*!< Capture is triggered by TE1 output active to inactive transition */
+#define HRTIM_CAPTURETRIGGER_TIMERE_CMP1 (HRTIM_CPT1CR_TIMECMP1) /*!< Timer E Compare 1 triggers Capture */
+#define HRTIM_CAPTURETRIGGER_TIMERE_CMP2 (HRTIM_CPT1CR_TIMECMP2) /*!< Timer E Compare 2 triggers Capture */
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Timer_External_Event_Filter HRTIM Timer External Event Filter
+ * @{
+ * @brief Constants defining the event filtering apploed to external events
+ * by a timer
+ */
+#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U)
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 1U */
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from counter reset/roll-over to Compare 2U */
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 3U */
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from counter reset/roll-over to Compare 4U */
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
+#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from counter reset/roll-over to Compare 2U */
+#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Windowing from counter reset/roll-over to Compare 3U */
+#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from another timing unit: TIMWIN source */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Timer_External_Event_Latch HRTIM Timer External Event Latch
+ * @{
+ * @brief Constants defining whether or not the external event is
+ * memorized (latched) and generated as soon as the blanking period
+ * is completed or the window ends
+ */
+#define HRTIM_TIMEVENTLATCH_DISABLED (0x00000000U) /*!< Event is ignored if it happens during a blank, or passed through during a window */
+#define HRTIM_TIMEVENTLATCH_ENABLED HRTIM_EEFR1_EE1LTCH /*!< Event is latched and delayed till the end of the blanking or windowing period */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Deadtime_Prescaler_Ratio HRTIM Deadtime Prescaler Ratio
+ * @{
+ * @brief Constants defining division ratio between the timer clock frequency
+ * (fHRTIM) and the deadtime generator clock (fDTG)
+ */
+#define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8 (0x00000000U) /*!< fDTG = fHRTIM * 8U */
+#define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4 (HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM * 4U */
+#define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2 (HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM * 2U */
+#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1 (HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM */
+#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2 (HRTIM_DTR_DTPRSC_2) /*!< fDTG = fHRTIM / 2U */
+#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 4U */
+#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM / 8U */
+#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 16U */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Deadtime_Rising_Sign HRTIM Deadtime Rising Sign
+ * @{
+ * @brief Constants defining whether the deadtime is positive or negative
+ * (overlapping signal) on rising edge
+ */
+#define HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE (0x00000000U) /*!< Positive deadtime on rising edge */
+#define HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE (HRTIM_DTR_SDTR) /*!< Negative deadtime on rising edge */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Deadtime_Rising_Lock HRTIM Deadtime Rising Lock
+ * @{
+ * @brief Constants defining whether or not the deadtime (rising sign and
+ * value) is write protected
+ */
+#define HRTIM_TIMDEADTIME_RISINGLOCK_WRITE (0x00000000U) /*!< Deadtime rising value and sign is writeable */
+#define HRTIM_TIMDEADTIME_RISINGLOCK_READONLY (HRTIM_DTR_DTRLK) /*!< Deadtime rising value and sign is read-only */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Deadtime_Rising_Sign_Lock HRTIM Deadtime Rising Sign Lock
+ * @{
+ * @brief Constants defining whether or not the deadtime rising sign is write
+ * protected
+ */
+#define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE (0x00000000U) /*!< Deadtime rising sign is writeable */
+#define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY (HRTIM_DTR_DTRSLK) /*!< Deadtime rising sign is read-only */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Deadtime_Falling_Sign HRTIM Deadtime Falling Sign
+ * @{
+ * @brief Constants defining whether the deadtime is positive or negative
+ * (overlapping signal) on falling edge
+ */
+#define HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE (0x00000000U) /*!< Positive deadtime on falling edge */
+#define HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE (HRTIM_DTR_SDTF) /*!< Negative deadtime on falling edge */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Deadtime_Falling_Lock HRTIM Deadtime Falling Lock
+ * @{
+ * @brief Constants defining whether or not the deadtime (falling sign and
+ * value) is write protected
+ */
+#define HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE (0x00000000U) /*!< Deadtime falling value and sign is writeable */
+#define HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY (HRTIM_DTR_DTFLK) /*!< Deadtime falling value and sign is read-only */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Deadtime_Falling_Sign_Lock HRTIM Deadtime Falling Sign Lock
+ * @{
+ * @brief Constants defining whether or not the deadtime falling sign is write
+ * protected
+ */
+#define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE (0x00000000U) /*!< Deadtime falling sign is writeable */
+#define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY (HRTIM_DTR_DTFSLK) /*!< Deadtime falling sign is read-only */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Chopper_Frequency HRTIM Chopper Frequency
+ * @{
+ * @brief Constants defining the frequency of the generated high frequency carrier
+ */
+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV16 (0x000000U) /*!< fCHPFRQ = fHRTIM / 16 */
+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV32 (HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 32 */
+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV48 (HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 48 */
+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV64 (HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 64 */
+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV80 (HRTIM_CHPR_CARFRQ_2) /*!< fCHPFRQ = fHRTIM / 80 */
+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV96 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 96 */
+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV112 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 112 */
+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV128 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 128 */
+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV144 (HRTIM_CHPR_CARFRQ_3) /*!< fCHPFRQ = fHRTIM / 144 */
+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV160 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 160 */
+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV176 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 176 */
+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV192 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 192 */
+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV208 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2) /*!< fCHPFRQ = fHRTIM / 208 */
+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV224 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 224 */
+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV240 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 240 */
+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV256 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 256 */
+ /**
+ * @}
+ */
+
+/** @defgroup HRTIM_Chopper_Duty_Cycle HRTIM Chopper Duty Cycle
+ * @{
+ * @brief Constants defining the duty cycle of the generated high frequency carrier
+ * Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8)
+ */
+#define HRTIM_CHOPPER_DUTYCYCLE_0 (0x000000U) /*!< Only 1st pulse is present */
+#define HRTIM_CHOPPER_DUTYCYCLE_125 (HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 12.5U % */
+#define HRTIM_CHOPPER_DUTYCYCLE_250 (HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 25U % */
+#define HRTIM_CHOPPER_DUTYCYCLE_375 (HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 37.5U % */
+#define HRTIM_CHOPPER_DUTYCYCLE_500 (HRTIM_CHPR_CARDTY_2) /*!< Duty cycle of the carrier signal is 50U % */
+#define HRTIM_CHOPPER_DUTYCYCLE_625 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 62.5U % */
+#define HRTIM_CHOPPER_DUTYCYCLE_750 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 75U % */
+#define HRTIM_CHOPPER_DUTYCYCLE_875 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 87.5U % */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Chopper_Start_Pulse_Width HRTIM Chopper Start Pulse Width
+ * @{
+ * @brief Constants defining the pulse width of the first pulse of the generated
+ * high frequency carrier
+ */
+#define HRTIM_CHOPPER_PULSEWIDTH_16 (0x000000U) /*!< tSTPW = tHRTIM x 16 */
+#define HRTIM_CHOPPER_PULSEWIDTH_32 (HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 32 */
+#define HRTIM_CHOPPER_PULSEWIDTH_48 (HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 48 */
+#define HRTIM_CHOPPER_PULSEWIDTH_64 (HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 64 */
+#define HRTIM_CHOPPER_PULSEWIDTH_80 (HRTIM_CHPR_STRPW_2) /*!< tSTPW = tHRTIM x 80 */
+#define HRTIM_CHOPPER_PULSEWIDTH_96 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 96 */
+#define HRTIM_CHOPPER_PULSEWIDTH_112 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 112 */
+#define HRTIM_CHOPPER_PULSEWIDTH_128 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 128 */
+#define HRTIM_CHOPPER_PULSEWIDTH_144 (HRTIM_CHPR_STRPW_3) /*!< tSTPW = tHRTIM x 144 */
+#define HRTIM_CHOPPER_PULSEWIDTH_160 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 160 */
+#define HRTIM_CHOPPER_PULSEWIDTH_176 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 176 */
+#define HRTIM_CHOPPER_PULSEWIDTH_192 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 192 */
+#define HRTIM_CHOPPER_PULSEWIDTH_208 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2) /*!< tSTPW = tHRTIM x 208 */
+#define HRTIM_CHOPPER_PULSEWIDTH_224 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 224 */
+#define HRTIM_CHOPPER_PULSEWIDTH_240 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 240 */
+#define HRTIM_CHOPPER_PULSEWIDTH_256 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 256 */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Synchronization_Options HRTIM Synchronization Options
+ * @{
+ * @brief Constants defining the options for synchronizing multiple HRTIM
+ * instances, as a master unit (generating a synchronization signal)
+ * or as a slave (waiting for a trigger to be synchronized)
+ */
+#define HRTIM_SYNCOPTION_NONE 0x00000000U /*!< HRTIM instance doesn't handle external synchronization signals (SYNCIN, SYNCOUT) */
+#define HRTIM_SYNCOPTION_MASTER 0x00000001U /*!< HRTIM instance acts as a MASTER, i.e. generates external synchronization output (SYNCOUT)*/
+#define HRTIM_SYNCOPTION_SLAVE 0x00000002U /*!< HRTIM instance acts as a SLAVE, i.e. it is synchronized by external sources (SYNCIN) */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Synchronization_Input_Source HRTIM Synchronization Input Source
+ * @{
+ * @brief Constants defining defining the synchronization input source
+ */
+#define HRTIM_SYNCINPUTSOURCE_NONE 0x00000000U /*!< disabled. HRTIM is not synchronized and runs in standalone mode */
+#define HRTIM_SYNCINPUTSOURCE_INTERNALEVENT HRTIM_MCR_SYNC_IN_1 /*!< The HRTIM is synchronized with the on-chip timer */
+#define HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT (HRTIM_MCR_SYNC_IN_1 | HRTIM_MCR_SYNC_IN_0) /*!< A positive pulse on SYNCIN input triggers the HRTIM */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Synchronization_Output_Source HRTIM Synchronization Output Source
+ * @{
+ * @brief Constants defining the source and event to be sent on the
+ * synchronization outputs
+ */
+#define HRTIM_SYNCOUTPUTSOURCE_MASTER_START 0x00000000U /*!< A pulse is sent on the SYNCOUT output upon master timer start event */
+#define HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output upon master timer compare 1 event*/
+#define HRTIM_SYNCOUTPUTSOURCE_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /*!< A pulse is sent on the SYNCOUT output upon timer A start or reset events */
+#define HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output upon timer A compare 1 event */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Synchronization_Output_Polarity HRTIM Synchronization Output Polarity
+ * @{
+ * @brief Constants defining the routing and conditioning of the synchronization output event
+ */
+#define HRTIM_SYNCOUTPUTPOLARITY_NONE 0x00000000U /*!< Synchronization output event is disabled */
+#define HRTIM_SYNCOUTPUTPOLARITY_POSITIVE (HRTIM_MCR_SYNC_OUT_1) /*!< SCOUT pin has a low idle level and issues a positive pulse of 16 fHRTIM clock cycles length for the synchronization */
+#define HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE (HRTIM_MCR_SYNC_OUT_1 | HRTIM_MCR_SYNC_OUT_0) /*!< SCOUT pin has a high idle level and issues a negative pulse of 16 fHRTIM clock cycles length for the synchronization */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_External_Event_Sources HRTIM External Event Sources
+ * @{
+ * @brief Constants defining available sources associated to external events
+ */
+#define HRTIM_EVENTSRC_1 (0x00000000U) /*!< External event source 1U */
+#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2U */
+#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3U */
+#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_External_Event_Polarity HRTIM External Event Polarity
+ * @{
+ * @brief Constants defining the polarity of an external event
+ */
+#define HRTIM_EVENTPOLARITY_HIGH (0x00000000U) /*!< External event is active high */
+#define HRTIM_EVENTPOLARITY_LOW (HRTIM_EECR1_EE1POL) /*!< External event is active low */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_External_Event_Sensitivity HRTIM External Event Sensitivity
+ * @{
+ * @brief Constants defining the sensitivity (level-sensitive or edge-sensitive)
+ * of an external event
+ */
+#define HRTIM_EVENTSENSITIVITY_LEVEL (0x00000000U) /*!< External event is active on level */
+#define HRTIM_EVENTSENSITIVITY_RISINGEDGE (HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising edge */
+#define HRTIM_EVENTSENSITIVITY_FALLINGEDGE (HRTIM_EECR1_EE1SNS_1) /*!< External event is active on Falling edge */
+#define HRTIM_EVENTSENSITIVITY_BOTHEDGES (HRTIM_EECR1_EE1SNS_1 | HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising and Falling edges */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_External_Event_Fast_Mode HRTIM External Event Fast Mode
+ * @{
+ * @brief Constants defining whether or not an external event is programmed in
+ fast mode
+ */
+#define HRTIM_EVENTFASTMODE_ENABLE (0x00000000U) /*!< External Event is re-synchronized by the HRTIM logic before acting on outputs */
+#define HRTIM_EVENTFASTMODE_DISABLE (HRTIM_EECR1_EE1FAST) /*!< External Event is acting asynchronously on outputs (low latency mode) */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_External_Event_Filter HRTIM External Event Filter
+ * @{
+ * @brief Constants defining the frequency used to sample an external event 6
+ * input and the length (N) of the digital filter applied
+ */
+#define HRTIM_EVENTFILTER_NONE (0x00000000U) /*!< Filter disabled */
+#define HRTIM_EVENTFILTER_1 (HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fHRTIM, N=2U */
+#define HRTIM_EVENTFILTER_2 (HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fHRTIM, N=4U */
+#define HRTIM_EVENTFILTER_3 (HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fHRTIM, N=8U */
+#define HRTIM_EVENTFILTER_4 (HRTIM_EECR3_EE6F_2) /*!< fSAMPLING= fEEVS/2U, N=6U */
+#define HRTIM_EVENTFILTER_5 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/2U, N=8U */
+#define HRTIM_EVENTFILTER_6 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/4U, N=6U */
+#define HRTIM_EVENTFILTER_7 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/4U, N=8U */
+#define HRTIM_EVENTFILTER_8 (HRTIM_EECR3_EE6F_3) /*!< fSAMPLING= fEEVS/8U, N=6U */
+#define HRTIM_EVENTFILTER_9 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/8U, N=8U */
+#define HRTIM_EVENTFILTER_10 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/16U, N=5U */
+#define HRTIM_EVENTFILTER_11 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/16U, N=6U */
+#define HRTIM_EVENTFILTER_12 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2) /*!< fSAMPLING= fEEVS/16U, N=8U */
+#define HRTIM_EVENTFILTER_13 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/32U, N=5U */
+#define HRTIM_EVENTFILTER_14 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/32U, N=6U */
+#define HRTIM_EVENTFILTER_15 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/32U, N=8U */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_External_Event_Prescaler HRTIM External Event Prescaler
+ * @{
+ * @brief Constants defining division ratio between the timer clock frequency
+ * fHRTIM) and the external event signal sampling clock (fEEVS)
+ * used by the digital filters
+ */
+#define HRTIM_EVENTPRESCALER_DIV1 (0x00000000U) /*!< fEEVS=fHRTIM */
+#define HRTIM_EVENTPRESCALER_DIV2 (HRTIM_EECR3_EEVSD_0) /*!< fEEVS=fHRTIM / 2U */
+#define HRTIM_EVENTPRESCALER_DIV4 (HRTIM_EECR3_EEVSD_1) /*!< fEEVS=fHRTIM / 4U */
+#define HRTIM_EVENTPRESCALER_DIV8 (HRTIM_EECR3_EEVSD_1 | HRTIM_EECR3_EEVSD_0) /*!< fEEVS=fHRTIM / 8U */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Fault_Sources HRTIM Fault Sources
+ * @{
+ * @brief Constants defining whether a fault is triggered by any external
+ * or internal fault source
+ */
+#define HRTIM_FAULTSOURCE_DIGITALINPUT (0x00000000U) /*!< Fault input is FLT input pin */
+#define HRTIM_FAULTSOURCE_INTERNAL (HRTIM_FLTINR1_FLT1SRC) /*!< Fault input is FLT_Int signal (e.g. internal comparator) */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Fault_Polarity HRTIM Fault Polarity
+ * @{
+ * @brief Constants defining the polarity of a fault event
+ */
+#define HRTIM_FAULTPOLARITY_LOW (0x00000000U) /*!< Fault input is active low */
+#define HRTIM_FAULTPOLARITY_HIGH (HRTIM_FLTINR1_FLT1P) /*!< Fault input is active high */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Fault_Filter HRTIM Fault Filter
+ * @{
+ * @ brief Constants defining the frequency used to sample the fault input and
+ * the length (N) of the digital filter applied
+ */
+#define HRTIM_FAULTFILTER_NONE (0x00000000U) /*!< Filter disabled */
+#define HRTIM_FAULTFILTER_1 (HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=2U */
+#define HRTIM_FAULTFILTER_2 (HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fHRTIM, N=4U */
+#define HRTIM_FAULTFILTER_3 (HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=8U */
+#define HRTIM_FAULTFILTER_4 (HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/2U, N=6U */
+#define HRTIM_FAULTFILTER_5 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/2U, N=8U */
+#define HRTIM_FAULTFILTER_6 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/4U, N=6U */
+#define HRTIM_FAULTFILTER_7 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/4U, N=8U */
+#define HRTIM_FAULTFILTER_8 (HRTIM_FLTINR1_FLT1F_3) /*!< fSAMPLING= fFLTS/8U, N=6U */
+#define HRTIM_FAULTFILTER_9 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/8U, N=8U */
+#define HRTIM_FAULTFILTER_10 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/16U, N=5U */
+#define HRTIM_FAULTFILTER_11 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/16U, N=6U */
+#define HRTIM_FAULTFILTER_12 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/16U, N=8U */
+#define HRTIM_FAULTFILTER_13 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32U, N=5U */
+#define HRTIM_FAULTFILTER_14 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/32U, N=6U */
+#define HRTIM_FAULTFILTER_15 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32U, N=8U */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Fault_Lock HRTIM Fault Lock
+ * @{
+ * @brief Constants defining whether or not the fault programming bits are
+ write protected
+ */
+#define HRTIM_FAULTLOCK_READWRITE (0x00000000U) /*!< Fault settings bits are read/write */
+#define HRTIM_FAULTLOCK_READONLY (HRTIM_FLTINR1_FLT1LCK) /*!< Fault settings bits are read only */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_External_Fault_Prescaler HRTIM External Fault Prescaler
+ * @{
+ * @brief Constants defining the division ratio between the timer clock
+ * frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used
+ * by the digital filters.
+ */
+#define HRTIM_FAULTPRESCALER_DIV1 (0x00000000U) /*!< fFLTS=fHRTIM */
+#define HRTIM_FAULTPRESCALER_DIV2 (HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS=fHRTIM / 2U */
+#define HRTIM_FAULTPRESCALER_DIV4 (HRTIM_FLTINR2_FLTSD_1) /*!< fFLTS=fHRTIM / 4U */
+#define HRTIM_FAULTPRESCALER_DIV8 (HRTIM_FLTINR2_FLTSD_1 | HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS=fHRTIM / 8U */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Burst_Mode_Operating_Mode HRTIM Burst Mode Operating Mode
+ * @{
+ * @brief Constants defining if the burst mode is entered once or if it is
+ * continuously operating
+ */
+#define HRTIM_BURSTMODE_SINGLESHOT (0x00000000U) /*!< Burst mode operates in single shot mode */
+#define HRTIM_BURSTMODE_CONTINOUS (HRTIM_BMCR_BMOM) /*!< Burst mode operates in continuous mode */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Burst_Mode_Clock_Source HRTIM Burst Mode Clock Source
+ * @{
+ * @brief Constants defining the clock source for the burst mode counter
+ */
+#define HRTIM_BURSTMODECLOCKSOURCE_MASTER (0x00000000U) /*!< Master timer counter reset/roll-over is used as clock source for the burst mode counter */
+#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_A (HRTIM_BMCR_BMCLK_0) /*!< Timer A counter reset/roll-over is used as clock source for the burst mode counter */
+#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_B (HRTIM_BMCR_BMCLK_1) /*!< Timer B counter reset/roll-over is used as clock source for the burst mode counter */
+#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_C (HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< Timer C counter reset/roll-over is used as clock source for the burst mode counter */
+#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_D (HRTIM_BMCR_BMCLK_2) /*!< Timer D counter reset/roll-over is used as clock source for the burst mode counter */
+#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_E (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0) /*!< Timer E counter reset/roll-over is used as clock source for the burst mode counter */
+#define HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1) /*!< On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock */
+#define HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock */
+#define HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO (HRTIM_BMCR_BMCLK_3) /*!< On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock */
+#define HRTIM_BURSTMODECLOCKSOURCE_FHRTIM (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1) /*!< Prescaled fHRTIM clock is used as clock source for the burst mode counter */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Burst_Mode_Prescaler HRTIM Burst Mode Prescaler
+ * @{
+ * @brief Constants defining the prescaling ratio of the fHRTIM clock
+ * for the burst mode controller
+ */
+#define HRTIM_BURSTMODEPRESCALER_DIV1 (0x00000000U) /*!< fBRST = fHRTIM */
+#define HRTIM_BURSTMODEPRESCALER_DIV2 (HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2U */
+#define HRTIM_BURSTMODEPRESCALER_DIV4 (HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/4U */
+#define HRTIM_BURSTMODEPRESCALER_DIV8 (HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8U */
+#define HRTIM_BURSTMODEPRESCALER_DIV16 (HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/16U */
+#define HRTIM_BURSTMODEPRESCALER_DIV32 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32U */
+#define HRTIM_BURSTMODEPRESCALER_DIV64 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/64U */
+#define HRTIM_BURSTMODEPRESCALER_DIV128 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/128U */
+#define HRTIM_BURSTMODEPRESCALER_DIV256 (HRTIM_BMCR_BMPRSC_3) /*!< fBRST = fHRTIM/256U */
+#define HRTIM_BURSTMODEPRESCALER_DIV512 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/512U */
+#define HRTIM_BURSTMODEPRESCALER_DIV1024 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/1024U */
+#define HRTIM_BURSTMODEPRESCALER_DIV2048 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2048U*/
+#define HRTIM_BURSTMODEPRESCALER_DIV4096 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/4096U */
+#define HRTIM_BURSTMODEPRESCALER_DIV8192 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8192U */
+#define HRTIM_BURSTMODEPRESCALER_DIV16384 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/16384U */
+#define HRTIM_BURSTMODEPRESCALER_DIV32768 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32768U */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Burst_Mode_Register_Preload_Enable HRTIM Burst Mode Register Preload Enable
+ * @{
+ * @brief Constants defining whether or not burst mode registers preload
+ mechanism is enabled, i.e. a write access into a preloadable register
+ (HRTIM_BMCMPR, HRTIM_BMPER) is done into the active or the preload register
+ */
+#define HRIM_BURSTMODEPRELOAD_DISABLED (0x00000000U) /*!< Preload disabled: the write access is directly done into active registers */
+#define HRIM_BURSTMODEPRELOAD_ENABLED (HRTIM_BMCR_BMPREN) /*!< Preload enabled: the write access is done into preload registers */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Burst_Mode_Trigger HRTIM Burst Mode Trigger
+ * @{
+ * @brief Constants defining the events that can be used tor trig the burst
+ * mode operation
+ */
+#define HRTIM_BURSTMODETRIGGER_NONE 0x00000000U /*!< No trigger */
+#define HRTIM_BURSTMODETRIGGER_MASTER_RESET (HRTIM_BMTRGR_MSTRST) /*!< Master reset */
+#define HRTIM_BURSTMODETRIGGER_MASTER_REPETITION (HRTIM_BMTRGR_MSTREP) /*!< Master repetition */
+#define HRTIM_BURSTMODETRIGGER_MASTER_CMP1 (HRTIM_BMTRGR_MSTCMP1) /*!< Master compare 1U */
+#define HRTIM_BURSTMODETRIGGER_MASTER_CMP2 (HRTIM_BMTRGR_MSTCMP2) /*!< Master compare 2U */
+#define HRTIM_BURSTMODETRIGGER_MASTER_CMP3 (HRTIM_BMTRGR_MSTCMP3) /*!< Master compare 3U */
+#define HRTIM_BURSTMODETRIGGER_MASTER_CMP4 (HRTIM_BMTRGR_MSTCMP4) /*!< Master compare 4U */
+#define HRTIM_BURSTMODETRIGGER_TIMERA_RESET (HRTIM_BMTRGR_TARST) /*!< Timer A reset */
+#define HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION (HRTIM_BMTRGR_TAREP) /*!< Timer A repetition */
+#define HRTIM_BURSTMODETRIGGER_TIMERA_CMP1 (HRTIM_BMTRGR_TACMP1) /*!< Timer A compare 1 */
+#define HRTIM_BURSTMODETRIGGER_TIMERA_CMP2 (HRTIM_BMTRGR_TACMP2) /*!< Timer A compare 2 */
+#define HRTIM_BURSTMODETRIGGER_TIMERB_RESET (HRTIM_BMTRGR_TBRST) /*!< Timer B reset */
+#define HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION (HRTIM_BMTRGR_TBREP) /*!< Timer B repetition */
+#define HRTIM_BURSTMODETRIGGER_TIMERB_CMP1 (HRTIM_BMTRGR_TBCMP1) /*!< Timer B compare 1 */
+#define HRTIM_BURSTMODETRIGGER_TIMERB_CMP2 (HRTIM_BMTRGR_TBCMP2) /*!< Timer B compare 2 */
+#define HRTIM_BURSTMODETRIGGER_TIMERC_RESET (HRTIM_BMTRGR_TCRST) /*!< Timer C reset */
+#define HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION (HRTIM_BMTRGR_TCREP) /*!< Timer C repetition */
+#define HRTIM_BURSTMODETRIGGER_TIMERC_CMP1 (HRTIM_BMTRGR_TCCMP1) /*!< Timer C compare 1 */
+#define HRTIM_BURSTMODETRIGGER_TIMERC_CMP2 (HRTIM_BMTRGR_TCCMP2) /*!< Timer C compare 2 */
+#define HRTIM_BURSTMODETRIGGER_TIMERD_RESET (HRTIM_BMTRGR_TDRST) /*!< Timer D reset */
+#define HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION (HRTIM_BMTRGR_TDREP) /*!< Timer D repetition */
+#define HRTIM_BURSTMODETRIGGER_TIMERD_CMP1 (HRTIM_BMTRGR_TDCMP1) /*!< Timer D compare 1 */
+#define HRTIM_BURSTMODETRIGGER_TIMERD_CMP2 (HRTIM_BMTRGR_TDCMP2) /*!< Timer D compare 2 */
+#define HRTIM_BURSTMODETRIGGER_TIMERE_RESET (HRTIM_BMTRGR_TERST) /*!< Timer E reset */
+#define HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION (HRTIM_BMTRGR_TEREP) /*!< Timer E repetition */
+#define HRTIM_BURSTMODETRIGGER_TIMERE_CMP1 (HRTIM_BMTRGR_TECMP1) /*!< Timer E compare 1 */
+#define HRTIM_BURSTMODETRIGGER_TIMERE_CMP2 (HRTIM_BMTRGR_TECMP2) /*!< Timer E compare 2 */
+#define HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7 (HRTIM_BMTRGR_TAEEV7) /*!< Timer A period following External Event 7 */
+#define HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8 (HRTIM_BMTRGR_TDEEV8) /*!< Timer D period following External Event 8 */
+#define HRTIM_BURSTMODETRIGGER_EVENT_7 (HRTIM_BMTRGR_EEV7) /*!< External Event 7 (timer A filters applied) */
+#define HRTIM_BURSTMODETRIGGER_EVENT_8 (HRTIM_BMTRGR_EEV8) /*!< External Event 8 (timer D filters applied)*/
+#define HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP (HRTIM_BMTRGR_OCHPEV) /*!< On-chip Event */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_ADC_Trigger_Update_Source HRTIM ADC Trigger Update Source
+ * @{
+ * @brief constants defining the source triggering the update of the
+ HRTIM_ADCxR register (transfer from preload to active register).
+ */
+#define HRTIM_ADCTRIGGERUPDATE_MASTER 0x00000000U /*!< Master timer */
+#define HRTIM_ADCTRIGGERUPDATE_TIMER_A (HRTIM_CR1_ADC1USRC_0) /*!< Timer A */
+#define HRTIM_ADCTRIGGERUPDATE_TIMER_B (HRTIM_CR1_ADC1USRC_1) /*!< Timer B */
+#define HRTIM_ADCTRIGGERUPDATE_TIMER_C (HRTIM_CR1_ADC1USRC_1 | HRTIM_CR1_ADC1USRC_0) /*!< Timer C */
+#define HRTIM_ADCTRIGGERUPDATE_TIMER_D (HRTIM_CR1_ADC1USRC_2) /*!< Timer D */
+#define HRTIM_ADCTRIGGERUPDATE_TIMER_E (HRTIM_CR1_ADC1USRC_2 | HRTIM_CR1_ADC1USRC_0) /*!< Timer E */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_ADC_Trigger_Event HRTIM ADC Trigger Event
+ * @{
+ * @brief constants defining the events triggering ADC conversion.
+ * HRTIM_ADCTRIGGEREVENT13_*: ADC Triggers 1 and 3
+ * HRTIM_ADCTRIGGEREVENT24_*: ADC Triggers 2 and 4
+ */
+#define HRTIM_ADCTRIGGEREVENT13_NONE 0x00000000U /*!< No ADC trigger event */
+#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP1 (HRTIM_ADC1R_AD1MC1) /*!< ADC Trigger on master compare 1U */
+#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP2 (HRTIM_ADC1R_AD1MC2) /*!< ADC Trigger on master compare 2U */
+#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP3 (HRTIM_ADC1R_AD1MC3) /*!< ADC Trigger on master compare 3U */
+#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP4 (HRTIM_ADC1R_AD1MC4) /*!< ADC Trigger on master compare 4U */
+#define HRTIM_ADCTRIGGEREVENT13_MASTER_PERIOD (HRTIM_ADC1R_AD1MPER) /*!< ADC Trigger on master period */
+#define HRTIM_ADCTRIGGEREVENT13_EVENT_1 (HRTIM_ADC1R_AD1EEV1) /*!< ADC Trigger on external event 1U */
+#define HRTIM_ADCTRIGGEREVENT13_EVENT_2 (HRTIM_ADC1R_AD1EEV2) /*!< ADC Trigger on external event 2U */
+#define HRTIM_ADCTRIGGEREVENT13_EVENT_3 (HRTIM_ADC1R_AD1EEV3) /*!< ADC Trigger on external event 3U */
+#define HRTIM_ADCTRIGGEREVENT13_EVENT_4 (HRTIM_ADC1R_AD1EEV4) /*!< ADC Trigger on external event 4U */
+#define HRTIM_ADCTRIGGEREVENT13_EVENT_5 (HRTIM_ADC1R_AD1EEV5) /*!< ADC Trigger on external event 5U */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP2 (HRTIM_ADC1R_AD1TAC2) /*!< ADC Trigger on Timer A compare 2U */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP3 (HRTIM_ADC1R_AD1TAC3) /*!< ADC Trigger on Timer A compare 3U */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP4 (HRTIM_ADC1R_AD1TAC4) /*!< ADC Trigger on Timer A compare 4U */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERA_PERIOD (HRTIM_ADC1R_AD1TAPER) /*!< ADC Trigger on Timer A period */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERA_RESET (HRTIM_ADC1R_AD1TARST) /*!< ADC Trigger on Timer A reset */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP2 (HRTIM_ADC1R_AD1TBC2) /*!< ADC Trigger on Timer B compare 2U */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP3 (HRTIM_ADC1R_AD1TBC3) /*!< ADC Trigger on Timer B compare 3U */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP4 (HRTIM_ADC1R_AD1TBC4) /*!< ADC Trigger on Timer B compare 4U */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERB_PERIOD (HRTIM_ADC1R_AD1TBPER) /*!< ADC Trigger on Timer B period */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERB_RESET (HRTIM_ADC1R_AD1TBRST) /*!< ADC Trigger on Timer B reset */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP2 (HRTIM_ADC1R_AD1TCC2) /*!< ADC Trigger on Timer C compare 2U */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP3 (HRTIM_ADC1R_AD1TCC3) /*!< ADC Trigger on Timer C compare 3U */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP4 (HRTIM_ADC1R_AD1TCC4) /*!< ADC Trigger on Timer C compare 4U */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERC_PERIOD (HRTIM_ADC1R_AD1TCPER) /*!< ADC Trigger on Timer C period */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP2 (HRTIM_ADC1R_AD1TDC2) /*!< ADC Trigger on Timer D compare 2U */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP3 (HRTIM_ADC1R_AD1TDC3) /*!< ADC Trigger on Timer D compare 3U */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP4 (HRTIM_ADC1R_AD1TDC4) /*!< ADC Trigger on Timer D compare 4U */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERD_PERIOD (HRTIM_ADC1R_AD1TDPER) /*!< ADC Trigger on Timer D period */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP2 (HRTIM_ADC1R_AD1TEC2) /*!< ADC Trigger on Timer E compare 2U */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP3 (HRTIM_ADC1R_AD1TEC3) /*!< ADC Trigger on Timer E compare 3U */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP4 (HRTIM_ADC1R_AD1TEC4) /*!< ADC Trigger on Timer E compare 4U */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERE_PERIOD (HRTIM_ADC1R_AD1TEPER) /*!< ADC Trigger on Timer E period */
+
+#define HRTIM_ADCTRIGGEREVENT24_NONE 0x00000000U /*!< No ADC trigger event */
+#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP1 (HRTIM_ADC2R_AD2MC1) /*!< ADC Trigger on master compare 1U */
+#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP2 (HRTIM_ADC2R_AD2MC2) /*!< ADC Trigger on master compare 2U */
+#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP3 (HRTIM_ADC2R_AD2MC3) /*!< ADC Trigger on master compare 3U */
+#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP4 (HRTIM_ADC2R_AD2MC4) /*!< ADC Trigger on master compare 4U */
+#define HRTIM_ADCTRIGGEREVENT24_MASTER_PERIOD (HRTIM_ADC2R_AD2MPER) /*!< ADC Trigger on master period */
+#define HRTIM_ADCTRIGGEREVENT24_EVENT_6 (HRTIM_ADC2R_AD2EEV6) /*!< ADC Trigger on external event 6U */
+#define HRTIM_ADCTRIGGEREVENT24_EVENT_7 (HRTIM_ADC2R_AD2EEV7) /*!< ADC Trigger on external event 7U */
+#define HRTIM_ADCTRIGGEREVENT24_EVENT_8 (HRTIM_ADC2R_AD2EEV8) /*!< ADC Trigger on external event 8U */
+#define HRTIM_ADCTRIGGEREVENT24_EVENT_9 (HRTIM_ADC2R_AD2EEV9) /*!< ADC Trigger on external event 9U */
+#define HRTIM_ADCTRIGGEREVENT24_EVENT_10 (HRTIM_ADC2R_AD2EEV10) /*!< ADC Trigger on external event 10U */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP2 (HRTIM_ADC2R_AD2TAC2) /*!< ADC Trigger on Timer A compare 2U */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP3 (HRTIM_ADC2R_AD2TAC3) /*!< ADC Trigger on Timer A compare 3U */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP4 (HRTIM_ADC2R_AD2TAC4) /*!< ADC Trigger on Timer A compare 4U */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERA_PERIOD (HRTIM_ADC2R_AD2TAPER) /*!< ADC Trigger on Timer A period */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP2 (HRTIM_ADC2R_AD2TBC2) /*!< ADC Trigger on Timer B compare 2U */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP3 (HRTIM_ADC2R_AD2TBC3) /*!< ADC Trigger on Timer B compare 3U */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP4 (HRTIM_ADC2R_AD2TBC4) /*!< ADC Trigger on Timer B compare 4U */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERB_PERIOD (HRTIM_ADC2R_AD2TBPER) /*!< ADC Trigger on Timer B period */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP2 (HRTIM_ADC2R_AD2TCC2) /*!< ADC Trigger on Timer C compare 2U */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP3 (HRTIM_ADC2R_AD2TCC3) /*!< ADC Trigger on Timer C compare 3U */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP4 (HRTIM_ADC2R_AD2TCC4) /*!< ADC Trigger on Timer C compare 4U */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERC_PERIOD (HRTIM_ADC2R_AD2TCPER) /*!< ADC Trigger on Timer C period */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERC_RESET (HRTIM_ADC2R_AD2TCRST) /*!< ADC Trigger on Timer C reset */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP2 (HRTIM_ADC2R_AD2TDC2) /*!< ADC Trigger on Timer D compare 2U */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP3 (HRTIM_ADC2R_AD2TDC3) /*!< ADC Trigger on Timer D compare 3U */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP4 (HRTIM_ADC2R_AD2TDC4) /*!< ADC Trigger on Timer D compare 4U */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERD_PERIOD (HRTIM_ADC2R_AD2TDPER) /*!< ADC Trigger on Timer D period */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERD_RESET (HRTIM_ADC2R_AD2TDRST) /*!< ADC Trigger on Timer D reset */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP2 (HRTIM_ADC2R_AD2TEC2) /*!< ADC Trigger on Timer E compare 2U */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP3 (HRTIM_ADC2R_AD2TEC3) /*!< ADC Trigger on Timer E compare 3U */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP4 (HRTIM_ADC2R_AD2TEC4) /*!< ADC Trigger on Timer E compare 4U */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERE_RESET (HRTIM_ADC2R_AD2TERST) /*!< ADC Trigger on Timer E reset */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_DLL_Calibration_Rate HRTIM DLL Calibration Rate
+ * @{
+ * @brief Constants defining the DLL calibration periods (in micro seconds)
+ */
+#define HRTIM_SINGLE_CALIBRATION 0xFFFFFFFFU /*!< Non periodic DLL calibration */
+#define HRTIM_CALIBRATIONRATE_7300 0x00000000U /*!< Periodic DLL calibration: T = 1048576U * tHRTIM (7.3 ms) */
+#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) /*!< Periodic DLL calibration: T = 131072U * tHRTIM (910 ms) */
+#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) /*!< Periodic DLL calibration: T = 16384U * tHRTIM (114 ms) */
+#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) /*!< Periodic DLL calibration: T = 2048U * tHRTIM (14 ms) */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Burst_DMA_Registers_Update HRTIM Burst DMA Registers Update
+ * @{
+ * @brief Constants defining the registers that can be written during a burst
+ * DMA operation
+ */
+#define HRTIM_BURSTDMA_NONE 0x00000000U /*!< No register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_CR (HRTIM_BDTUPR_TIMCR) /*!< MCR or TIMxCR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_ICR (HRTIM_BDTUPR_TIMICR) /*!< MICR or TIMxICR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_DIER (HRTIM_BDTUPR_TIMDIER) /*!< MDIER or TIMxDIER register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_CNT (HRTIM_BDTUPR_TIMCNT) /*!< MCNTR or CNTxCR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_PER (HRTIM_BDTUPR_TIMPER) /*!< MPER or PERxR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_REP (HRTIM_BDTUPR_TIMREP) /*!< MREPR or REPxR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_CMP1 (HRTIM_BDTUPR_TIMCMP1) /*!< MCMP1R or CMP1xR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_CMP2 (HRTIM_BDTUPR_TIMCMP2) /*!< MCMP2R or CMP2xR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_CMP3 (HRTIM_BDTUPR_TIMCMP3) /*!< MCMP3R or CMP3xR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_CMP4 (HRTIM_BDTUPR_TIMCMP4) /*!< MCMP4R or CMP4xR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_DTR (HRTIM_BDTUPR_TIMDTR) /*!< TDxR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_SET1R (HRTIM_BDTUPR_TIMSET1R) /*!< SET1R register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_RST1R (HRTIM_BDTUPR_TIMRST1R) /*!< RST1R register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_SET2R (HRTIM_BDTUPR_TIMSET2R) /*!< SET2R register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_RST2R (HRTIM_BDTUPR_TIMRST2R) /*!< RST1R register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_EEFR1 (HRTIM_BDTUPR_TIMEEFR1) /*!< EEFxR1 register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_EEFR2 (HRTIM_BDTUPR_TIMEEFR2) /*!< EEFxR2 register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_RSTR (HRTIM_BDTUPR_TIMRSTR) /*!< RSTxR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_CHPR (HRTIM_BDTUPR_TIMCHPR) /*!< CHPxR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_OUTR (HRTIM_BDTUPR_TIMOUTR) /*!< OUTxR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_FLTR (HRTIM_BDTUPR_TIMFLTR) /*!< FLTxR register is updated by Burst DMA accesses */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Burst_Mode_Control HRTIM Burst Mode Control
+ * @{
+ * @brief Constants used to enable or disable the burst mode controller
+ */
+#define HRTIM_BURSTMODECTL_DISABLED 0x00000000U /*!< Burst mode disabled */
+#define HRTIM_BURSTMODECTL_ENABLED (HRTIM_BMCR_BME) /*!< Burst mode enabled */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Fault_Mode_Control HRTIM Fault Mode Control
+ * @{
+ * @brief Constants used to enable or disable a fault channel
+ */
+#define HRTIM_FAULTMODECTL_DISABLED 0x00000000U /*!< Fault channel is disabled */
+#define HRTIM_FAULTMODECTL_ENABLED 0x00000001U /*!< Fault channel is enabled */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Software_Timer_Update HRTIM Software Timer Update
+ * @{
+ * @brief Constants used to force timer registers update
+ */
+#define HRTIM_TIMERUPDATE_MASTER (HRTIM_CR2_MSWU) /*!< Forces an immediate transfer from the preload to the active register in the master timer */
+#define HRTIM_TIMERUPDATE_A (HRTIM_CR2_TASWU) /*!< Forces an immediate transfer from the preload to the active register in the timer A */
+#define HRTIM_TIMERUPDATE_B (HRTIM_CR2_TBSWU) /*!< Forces an immediate transfer from the preload to the active register in the timer B */
+#define HRTIM_TIMERUPDATE_C (HRTIM_CR2_TCSWU) /*!< Forces an immediate transfer from the preload to the active register in the timer C */
+#define HRTIM_TIMERUPDATE_D (HRTIM_CR2_TDSWU) /*!< Forces an immediate transfer from the preload to the active register in the timer D */
+#define HRTIM_TIMERUPDATE_E (HRTIM_CR2_TESWU) /*!< Forces an immediate transfer from the preload to the active register in the timer E */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Software_Timer_Reset HRTIM Software Timer Reset
+ * @{
+ * @brief Constants used to force timer counter reset
+ */
+#define HRTIM_TIMERRESET_MASTER (HRTIM_CR2_MRST) /*!< Resets the master timer counter */
+#define HRTIM_TIMERRESET_TIMER_A (HRTIM_CR2_TARST) /*!< Resets the timer A counter */
+#define HRTIM_TIMERRESET_TIMER_B (HRTIM_CR2_TBRST) /*!< Resets the timer B counter */
+#define HRTIM_TIMERRESET_TIMER_C (HRTIM_CR2_TCRST) /*!< Resets the timer C counter */
+#define HRTIM_TIMERRESET_TIMER_D (HRTIM_CR2_TDRST) /*!< Resets the timer D counter */
+#define HRTIM_TIMERRESET_TIMER_E (HRTIM_CR2_TERST) /*!< Resets the timer E counter */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Output_Level HRTIM Output Level
+ * @{
+ * @brief Constants defining the level of a timer output
+ */
+#define HRTIM_OUTPUTLEVEL_ACTIVE (0x00000001U) /*!< Forces the output to its active state */
+#define HRTIM_OUTPUTLEVEL_INACTIVE (0x00000002U) /*!< Forces the output to its inactive state */
+
+#define IS_HRTIM_OUTPUTLEVEL(OUTPUTLEVEL)\
+ (((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_ACTIVE) || \
+ ((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_INACTIVE))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Output_State HRTIM Output State
+ * @{
+ * @brief Constants defining the state of a timer output
+ */
+#define HRTIM_OUTPUTSTATE_IDLE (0x00000001U) /*!< Main operating mode, where the output can take the active or
+ inactive level as programmed in the crossbar unit */
+#define HRTIM_OUTPUTSTATE_RUN (0x00000002U) /*!< Default operating state (e.g. after an HRTIM reset, when the
+ outputs are disabled by software or during a burst mode operation */
+#define HRTIM_OUTPUTSTATE_FAULT (0x00000003U) /*!< Safety state, entered in case of a shut-down request on
+ FAULTx inputs */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Burst_Mode_Status HRTIM Burst Mode Status
+ * @{
+ * @brief Constants defining the operating state of the burst mode controller
+ */
+#define HRTIM_BURSTMODESTATUS_NORMAL 0x00000000U /*!< Normal operation */
+#define HRTIM_BURSTMODESTATUS_ONGOING (HRTIM_BMCR_BMSTAT) /*!< Burst operation on-going */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Current_Push_Pull_Status HRTIM Current Push Pull Status
+ * @{
+ * @brief Constants defining on which output the signal is currently applied
+ * in push-pull mode
+ */
+#define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT1 0x00000000U /*!< Signal applied on output 1 and output 2 forced inactive */
+#define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT2 (HRTIM_TIMISR_CPPSTAT) /*!< Signal applied on output 2 and output 1 forced inactive */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Idle_Push_Pull_Status HRTIM Idle Push Pull Status
+ * @{
+ * @brief Constants defining on which output the signal was applied, in
+ * push-pull mode balanced fault mode or delayed idle mode, when the
+ * protection was triggered
+ */
+#define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT1 0x00000000U /*!< Protection occurred when the output 1 was active and output 2 forced inactive */
+#define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT2 (HRTIM_TIMISR_IPPSTAT) /*!< Protection occurred when the output 2 was active and output 1 forced inactive */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Common_Interrupt_Enable HRTIM Common Interrupt Enable
+ * @{
+ */
+#define HRTIM_IT_NONE 0x00000000U /*!< No interrupt enabled */
+#define HRTIM_IT_FLT1 HRTIM_IER_FLT1 /*!< Fault 1 interrupt enable */
+#define HRTIM_IT_FLT2 HRTIM_IER_FLT2 /*!< Fault 2 interrupt enable */
+#define HRTIM_IT_FLT3 HRTIM_IER_FLT3 /*!< Fault 3 interrupt enable */
+#define HRTIM_IT_FLT4 HRTIM_IER_FLT4 /*!< Fault 4 interrupt enable */
+#define HRTIM_IT_FLT5 HRTIM_IER_FLT5 /*!< Fault 5 interrupt enable */
+#define HRTIM_IT_SYSFLT HRTIM_IER_SYSFLT /*!< System Fault interrupt enable */
+#define HRTIM_IT_DLLRDY HRTIM_IER_DLLRDY /*!< DLL ready interrupt enable */
+#define HRTIM_IT_BMPER HRTIM_IER_BMPER /*!< Burst mode period interrupt enable */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Master_Interrupt_Enable HRTIM Master Interrupt Enable
+ * @{
+ */
+#define HRTIM_MASTER_IT_NONE 0x00000000U /*!< No interrupt enabled */
+#define HRTIM_MASTER_IT_MCMP1 HRTIM_MDIER_MCMP1IE /*!< Master compare 1 interrupt enable */
+#define HRTIM_MASTER_IT_MCMP2 HRTIM_MDIER_MCMP2IE /*!< Master compare 2 interrupt enable */
+#define HRTIM_MASTER_IT_MCMP3 HRTIM_MDIER_MCMP3IE /*!< Master compare 3 interrupt enable */
+#define HRTIM_MASTER_IT_MCMP4 HRTIM_MDIER_MCMP4IE /*!< Master compare 4 interrupt enable */
+#define HRTIM_MASTER_IT_MREP HRTIM_MDIER_MREPIE /*!< Master Repetition interrupt enable */
+#define HRTIM_MASTER_IT_SYNC HRTIM_MDIER_SYNCIE /*!< Synchronization input interrupt enable */
+#define HRTIM_MASTER_IT_MUPD HRTIM_MDIER_MUPDIE /*!< Master update interrupt enable */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Timing_Unit_Interrupt_Enable HRTIM Timing Unit Interrupt Enable
+ * @{
+ */
+#define HRTIM_TIM_IT_NONE 0x00000000U /*!< No interrupt enabled */
+#define HRTIM_TIM_IT_CMP1 HRTIM_TIMDIER_CMP1IE /*!< Timer compare 1 interrupt enable */
+#define HRTIM_TIM_IT_CMP2 HRTIM_TIMDIER_CMP2IE /*!< Timer compare 2 interrupt enable */
+#define HRTIM_TIM_IT_CMP3 HRTIM_TIMDIER_CMP3IE /*!< Timer compare 3 interrupt enable */
+#define HRTIM_TIM_IT_CMP4 HRTIM_TIMDIER_CMP4IE /*!< Timer compare 4 interrupt enable */
+#define HRTIM_TIM_IT_REP HRTIM_TIMDIER_REPIE /*!< Timer repetition interrupt enable */
+#define HRTIM_TIM_IT_UPD HRTIM_TIMDIER_UPDIE /*!< Timer update interrupt enable */
+#define HRTIM_TIM_IT_CPT1 HRTIM_TIMDIER_CPT1IE /*!< Timer capture 1 interrupt enable */
+#define HRTIM_TIM_IT_CPT2 HRTIM_TIMDIER_CPT2IE /*!< Timer capture 2 interrupt enable */
+#define HRTIM_TIM_IT_SET1 HRTIM_TIMDIER_SET1IE /*!< Timer output 1 set interrupt enable */
+#define HRTIM_TIM_IT_RST1 HRTIM_TIMDIER_RST1IE /*!< Timer output 1 reset interrupt enable */
+#define HRTIM_TIM_IT_SET2 HRTIM_TIMDIER_SET2IE /*!< Timer output 2 set interrupt enable */
+#define HRTIM_TIM_IT_RST2 HRTIM_TIMDIER_RST2IE /*!< Timer output 2 reset interrupt enable */
+#define HRTIM_TIM_IT_RST HRTIM_TIMDIER_RSTIE /*!< Timer reset interrupt enable */
+#define HRTIM_TIM_IT_DLYPRT HRTIM_TIMDIER_DLYPRTIE /*!< Timer delay protection interrupt enable */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Common_Interrupt_Flag HRTIM Common Interrupt Flag
+ * @{
+ */
+#define HRTIM_FLAG_FLT1 HRTIM_ISR_FLT1 /*!< Fault 1 interrupt flag */
+#define HRTIM_FLAG_FLT2 HRTIM_ISR_FLT2 /*!< Fault 2 interrupt flag */
+#define HRTIM_FLAG_FLT3 HRTIM_ISR_FLT3 /*!< Fault 3 interrupt flag */
+#define HRTIM_FLAG_FLT4 HRTIM_ISR_FLT4 /*!< Fault 4 interrupt flag */
+#define HRTIM_FLAG_FLT5 HRTIM_ISR_FLT5 /*!< Fault 5 interrupt flag */
+#define HRTIM_FLAG_SYSFLT HRTIM_ISR_SYSFLT /*!< System Fault interrupt flag */
+#define HRTIM_FLAG_DLLRDY HRTIM_ISR_DLLRDY /*!< DLL ready interrupt flag */
+#define HRTIM_FLAG_BMPER HRTIM_ISR_BMPER /*!< Burst mode period interrupt flag */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Master_Interrupt_Flag HRTIM Master Interrupt Flag
+ * @{
+ */
+#define HRTIM_MASTER_FLAG_MCMP1 HRTIM_MISR_MCMP1 /*!< Master compare 1 interrupt flag */
+#define HRTIM_MASTER_FLAG_MCMP2 HRTIM_MISR_MCMP2 /*!< Master compare 2 interrupt flag */
+#define HRTIM_MASTER_FLAG_MCMP3 HRTIM_MISR_MCMP3 /*!< Master compare 3 interrupt flag */
+#define HRTIM_MASTER_FLAG_MCMP4 HRTIM_MISR_MCMP4 /*!< Master compare 4 interrupt flag */
+#define HRTIM_MASTER_FLAG_MREP HRTIM_MISR_MREP /*!< Master Repetition interrupt flag */
+#define HRTIM_MASTER_FLAG_SYNC HRTIM_MISR_SYNC /*!< Synchronization input interrupt flag */
+#define HRTIM_MASTER_FLAG_MUPD HRTIM_MISR_MUPD /*!< Master update interrupt flag */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Timing_Unit_Interrupt_Flag HRTIM Timing Unit Interrupt Flag
+ * @{
+ */
+#define HRTIM_TIM_FLAG_CMP1 HRTIM_TIMISR_CMP1 /*!< Timer compare 1 interrupt flag */
+#define HRTIM_TIM_FLAG_CMP2 HRTIM_TIMISR_CMP2 /*!< Timer compare 2 interrupt flag */
+#define HRTIM_TIM_FLAG_CMP3 HRTIM_TIMISR_CMP3 /*!< Timer compare 3 interrupt flag */
+#define HRTIM_TIM_FLAG_CMP4 HRTIM_TIMISR_CMP4 /*!< Timer compare 4 interrupt flag */
+#define HRTIM_TIM_FLAG_REP HRTIM_TIMISR_REP /*!< Timer repetition interrupt flag */
+#define HRTIM_TIM_FLAG_UPD HRTIM_TIMISR_UPD /*!< Timer update interrupt flag */
+#define HRTIM_TIM_FLAG_CPT1 HRTIM_TIMISR_CPT1 /*!< Timer capture 1 interrupt flag */
+#define HRTIM_TIM_FLAG_CPT2 HRTIM_TIMISR_CPT2 /*!< Timer capture 2 interrupt flag */
+#define HRTIM_TIM_FLAG_SET1 HRTIM_TIMISR_SET1 /*!< Timer output 1 set interrupt flag */
+#define HRTIM_TIM_FLAG_RST1 HRTIM_TIMISR_RST1 /*!< Timer output 1 reset interrupt flag */
+#define HRTIM_TIM_FLAG_SET2 HRTIM_TIMISR_SET2 /*!< Timer output 2 set interrupt flag */
+#define HRTIM_TIM_FLAG_RST2 HRTIM_TIMISR_RST2 /*!< Timer output 2 reset interrupt flag */
+#define HRTIM_TIM_FLAG_RST HRTIM_TIMISR_RST /*!< Timer reset interrupt flag */
+#define HRTIM_TIM_FLAG_DLYPRT HRTIM_TIMISR_DLYPRT /*!< Timer delay protection interrupt flag */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Master_DMA_Request_Enable HRTIM Master DMA Request Enable
+ * @{
+ */
+#define HRTIM_MASTER_DMA_NONE 0x00000000U /*!< No DMA request enable */
+#define HRTIM_MASTER_DMA_MCMP1 HRTIM_MDIER_MCMP1DE /*!< Master compare 1 DMA request enable */
+#define HRTIM_MASTER_DMA_MCMP2 HRTIM_MDIER_MCMP2DE /*!< Master compare 2 DMA request enable */
+#define HRTIM_MASTER_DMA_MCMP3 HRTIM_MDIER_MCMP3DE /*!< Master compare 3 DMA request enable */
+#define HRTIM_MASTER_DMA_MCMP4 HRTIM_MDIER_MCMP4DE /*!< Master compare 4 DMA request enable */
+#define HRTIM_MASTER_DMA_MREP HRTIM_MDIER_MREPDE /*!< Master Repetition DMA request enable */
+#define HRTIM_MASTER_DMA_SYNC HRTIM_MDIER_SYNCDE /*!< Synchronization input DMA request enable */
+#define HRTIM_MASTER_DMA_MUPD HRTIM_MDIER_MUPDDE /*!< Master update DMA request enable */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Timing_Unit_DMA_Request_Enable HRTIM Timing Unit DMA Request Enable
+ * @{
+ */
+#define HRTIM_TIM_DMA_NONE 0x00000000U /*!< No DMA request enable */
+#define HRTIM_TIM_DMA_CMP1 HRTIM_TIMDIER_CMP1DE /*!< Timer compare 1 DMA request enable */
+#define HRTIM_TIM_DMA_CMP2 HRTIM_TIMDIER_CMP2DE /*!< Timer compare 2 DMA request enable */
+#define HRTIM_TIM_DMA_CMP3 HRTIM_TIMDIER_CMP3DE /*!< Timer compare 3 DMA request enable */
+#define HRTIM_TIM_DMA_CMP4 HRTIM_TIMDIER_CMP4DE /*!< Timer compare 4 DMA request enable */
+#define HRTIM_TIM_DMA_REP HRTIM_TIMDIER_REPDE /*!< Timer repetition DMA request enable */
+#define HRTIM_TIM_DMA_UPD HRTIM_TIMDIER_UPDDE /*!< Timer update DMA request enable */
+#define HRTIM_TIM_DMA_CPT1 HRTIM_TIMDIER_CPT1DE /*!< Timer capture 1 DMA request enable */
+#define HRTIM_TIM_DMA_CPT2 HRTIM_TIMDIER_CPT2DE /*!< Timer capture 2 DMA request enable */
+#define HRTIM_TIM_DMA_SET1 HRTIM_TIMDIER_SET1DE /*!< Timer output 1 set DMA request enable */
+#define HRTIM_TIM_DMA_RST1 HRTIM_TIMDIER_RST1DE /*!< Timer output 1 reset DMA request enable */
+#define HRTIM_TIM_DMA_SET2 HRTIM_TIMDIER_SET2DE /*!< Timer output 2 set DMA request enable */
+#define HRTIM_TIM_DMA_RST2 HRTIM_TIMDIER_RST2DE /*!< Timer output 2 reset DMA request enable */
+#define HRTIM_TIM_DMA_RST HRTIM_TIMDIER_RSTDE /*!< Timer reset DMA request enable */
+#define HRTIM_TIM_DMA_DLYPRT HRTIM_TIMDIER_DLYPRTDE /*!< Timer delay protection DMA request enable */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros --------------------------------------------------------*/
+/** @addtogroup HRTIM_Private_Macros HRTIM Private Macros
+ * @{
+ */
+#define IS_HRTIM_TIMERINDEX(TIMERINDEX)\
+ (((TIMERINDEX) == HRTIM_TIMERINDEX_MASTER) || \
+ ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \
+ ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \
+ ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \
+ ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \
+ ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E))
+
+#define IS_HRTIM_TIMING_UNIT(TIMERINDEX)\
+ (((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \
+ ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \
+ ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \
+ ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \
+ ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E))
+
+#define IS_HRTIM_TIMERID(TIMERID) (((TIMERID) & 0xFFC0FFFFU) == 0x00000000U)
+
+#define IS_HRTIM_COMPAREUNIT(COMPAREUNIT)\
+ (((COMPAREUNIT) == HRTIM_COMPAREUNIT_1) || \
+ ((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) || \
+ ((COMPAREUNIT) == HRTIM_COMPAREUNIT_3) || \
+ ((COMPAREUNIT) == HRTIM_COMPAREUNIT_4))
+
+#define IS_HRTIM_CAPTUREUNIT(CAPTUREUNIT)\
+ (((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_1) || \
+ ((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_2))
+
+#define IS_HRTIM_OUTPUT(OUTPUT) (((OUTPUT) & 0xFFFFFC00U) == 0x00000000U)
+
+#define IS_HRTIM_TIMER_OUTPUT(TIMER, OUTPUT)\
+ ((((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \
+ (((OUTPUT) == HRTIM_OUTPUT_TA1) || \
+ ((OUTPUT) == HRTIM_OUTPUT_TA2))) \
+ || \
+ (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \
+ (((OUTPUT) == HRTIM_OUTPUT_TB1) || \
+ ((OUTPUT) == HRTIM_OUTPUT_TB2))) \
+ || \
+ (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \
+ (((OUTPUT) == HRTIM_OUTPUT_TC1) || \
+ ((OUTPUT) == HRTIM_OUTPUT_TC2))) \
+ || \
+ (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \
+ (((OUTPUT) == HRTIM_OUTPUT_TD1) || \
+ ((OUTPUT) == HRTIM_OUTPUT_TD2))) \
+ || \
+ (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \
+ (((OUTPUT) == HRTIM_OUTPUT_TE1) || \
+ ((OUTPUT) == HRTIM_OUTPUT_TE2))))
+
+#define IS_HRTIM_EVENT(EVENT)\
+ (((EVENT) == HRTIM_EVENT_NONE)|| \
+ ((EVENT) == HRTIM_EVENT_1) || \
+ ((EVENT) == HRTIM_EVENT_2) || \
+ ((EVENT) == HRTIM_EVENT_3) || \
+ ((EVENT) == HRTIM_EVENT_4) || \
+ ((EVENT) == HRTIM_EVENT_5) || \
+ ((EVENT) == HRTIM_EVENT_6) || \
+ ((EVENT) == HRTIM_EVENT_7) || \
+ ((EVENT) == HRTIM_EVENT_8) || \
+ ((EVENT) == HRTIM_EVENT_9) || \
+ ((EVENT) == HRTIM_EVENT_10))
+
+#define IS_HRTIM_FAULT(FAULT)\
+ (((FAULT) == HRTIM_FAULT_1) || \
+ ((FAULT) == HRTIM_FAULT_2) || \
+ ((FAULT) == HRTIM_FAULT_3) || \
+ ((FAULT) == HRTIM_FAULT_4) || \
+ ((FAULT) == HRTIM_FAULT_5))
+
+#define IS_HRTIM_PRESCALERRATIO(PRESCALERRATIO)\
+ (((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL32) || \
+ ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL16) || \
+ ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL8) || \
+ ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL4) || \
+ ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL2) || \
+ ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1) || \
+ ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV2) || \
+ ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV4))
+
+#define IS_HRTIM_MODE(MODE)\
+ (((MODE) == HRTIM_MODE_CONTINUOUS) || \
+ ((MODE) == HRTIM_MODE_SINGLESHOT) || \
+ ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE))
+
+#define IS_HRTIM_MODE_ONEPULSE(MODE)\
+ (((MODE) == HRTIM_MODE_SINGLESHOT) || \
+ ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE))
+
+
+#define IS_HRTIM_HALFMODE(HALFMODE)\
+ (((HALFMODE) == HRTIM_HALFMODE_DISABLED) || \
+ ((HALFMODE) == HRTIM_HALFMODE_ENABLED))
+
+#define IS_HRTIM_SYNCSTART(SYNCSTART)\
+ (((SYNCSTART) == HRTIM_SYNCSTART_DISABLED) || \
+ ((SYNCSTART) == HRTIM_SYNCSTART_ENABLED))
+
+#define IS_HRTIM_SYNCRESET(SYNCRESET)\
+ (((SYNCRESET) == HRTIM_SYNCRESET_DISABLED) || \
+ ((SYNCRESET) == HRTIM_SYNCRESET_ENABLED))
+
+#define IS_HRTIM_DACSYNC(DACSYNC)\
+ (((DACSYNC) == HRTIM_DACSYNC_NONE) || \
+ ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_1) || \
+ ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_2) || \
+ ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_3))
+
+#define IS_HRTIM_PRELOAD(PRELOAD)\
+ (((PRELOAD) == HRTIM_PRELOAD_DISABLED) || \
+ ((PRELOAD) == HRTIM_PRELOAD_ENABLED))
+
+#define IS_HRTIM_UPDATEGATING_MASTER(UPDATEGATING)\
+ (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \
+ ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \
+ ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE))
+
+#define IS_HRTIM_UPDATEGATING_TIM(UPDATEGATING)\
+ (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \
+ ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \
+ ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE) || \
+ ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1) || \
+ ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2) || \
+ ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3) || \
+ ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1_UPDATE) || \
+ ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2_UPDATE) || \
+ ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3_UPDATE))
+
+#define IS_HRTIM_TIMERBURSTMODE(MODE) \
+ (((MODE) == HRTIM_TIMERBURSTMODE_MAINTAINCLOCK) || \
+ ((MODE) == HRTIM_TIMERBURSTMODE_RESETCOUNTER))
+#define IS_HRTIM_UPDATEONREPETITION(UPDATEONREPETITION) \
+ (((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_DISABLED) || \
+ ((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_ENABLED))
+
+#define IS_HRTIM_TIMPUSHPULLMODE(TIMPUSHPULLMODE)\
+ (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) || \
+ ((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED))
+#define IS_HRTIM_TIMFAULTENABLE(TIMFAULTENABLE) (((TIMFAULTENABLE) & 0xFFFFFFE0U) == 0x00000000U)
+
+#define IS_HRTIM_TIMFAULTLOCK(TIMFAULTLOCK)\
+ (((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READWRITE) || \
+ ((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READONLY))
+
+#define IS_HRTIM_TIMDEADTIMEINSERTION(TIMPUSHPULLMODE, TIMDEADTIMEINSERTION)\
+ ((((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) && \
+ ((((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED) || \
+ ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_ENABLED)))) \
+ || \
+ (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \
+ ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED)))
+
+#define IS_HRTIM_TIMDELAYEDPROTECTION(TIMPUSHPULLMODE, TIMDELAYEDPROTECTION)\
+ ((((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED) || \
+ ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6) || \
+ ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6) || \
+ ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6) || \
+ ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7) || \
+ ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7) || \
+ ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7)) \
+ || \
+ (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \
+ (((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6) || \
+ ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7))))
+
+#define IS_HRTIM_TIMUPDATETRIGGER(TIMUPDATETRIGGER) (((TIMUPDATETRIGGER) & 0xFE07FFFFU) == 0x00000000U)
+
+#define IS_HRTIM_TIMRESETTRIGGER(TIMRESETTRIGGER) (((TIMRESETTRIGGER) & 0x80000001U) == 0x00000000U)
+
+#define IS_HRTIM_ADCTRIGGER(ADCTRIGGER)\
+ (((ADCTRIGGER) == HRTIM_ADCTRIGGER_1) || \
+ ((ADCTRIGGER) == HRTIM_ADCTRIGGER_2) || \
+ ((ADCTRIGGER) == HRTIM_ADCTRIGGER_3) || \
+ ((ADCTRIGGER) == HRTIM_ADCTRIGGER_4))
+
+#define IS_HRTIM_OUTPUTLEVEL(OUTPUTLEVEL)\
+ (((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_ACTIVE) || \
+ ((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_INACTIVE))
+
+#define IS_HRTIM_BASICOCMODE(BASICOCMODE)\
+ (((BASICOCMODE) == HRTIM_BASICOCMODE_TOGGLE) || \
+ ((BASICOCMODE) == HRTIM_BASICOCMODE_INACTIVE) || \
+ ((BASICOCMODE) == HRTIM_BASICOCMODE_ACTIVE))
+
+
+#define IS_HRTIM_TIMUPDATEONRESET(TIMUPDATEONRESET) \
+ (((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_DISABLED) || \
+ ((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_ENABLED))
+
+#define IS_HRTIM_AUTODELAYEDMODE(AUTODELAYEDMODE)\
+ (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \
+ ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \
+ ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \
+ ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))
+
+/* Auto delayed mode is only available for compare units 2 and 4U */
+#define IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(COMPAREUNIT, AUTODELAYEDMODE) \
+ ((((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) && \
+ (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \
+ ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \
+ ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \
+ ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))) \
+ || \
+ (((COMPAREUNIT) == HRTIM_COMPAREUNIT_4) && \
+ (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \
+ ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \
+ ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \
+ ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))))
+
+#define IS_HRTIM_OUTPUTPOLARITY(OUTPUTPOLARITY)\
+ (((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_HIGH) || \
+ ((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_LOW))
+
+#define IS_HRTIM_OUTPUTSET(OUTPUTSET)\
+ (((OUTPUTSET) == HRTIM_OUTPUTSET_NONE) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_RESYNC) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMPER) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP1) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP2) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP3) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP4) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERPER) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP1) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP2) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP3) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP4) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_1) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_2) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_3) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_4) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_5) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_6) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_7) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_8) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_9) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_1) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_2) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_3) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_4) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_5) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_6) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_7) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_8) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_9) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_10) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_UPDATE))
+
+#define IS_HRTIM_OUTPUTRESET(OUTPUTRESET)\
+ (((OUTPUTRESET) == HRTIM_OUTPUTRESET_NONE) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_RESYNC) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMPER) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP1) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP2) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP3) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP4) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERPER) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP1) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP2) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP3) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP4) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_1) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_2) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_3) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_4) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_5) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_6) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_7) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_8) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_9) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_1) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_2) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_3) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_4) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_5) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_6) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_7) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_8) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_9) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_10) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_UPDATE))
+
+#define IS_HRTIM_OUTPUTIDLEMODE(OUTPUTIDLEMODE)\
+ (((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_NONE) || \
+ ((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_IDLE))
+
+#define IS_HRTIM_OUTPUTIDLELEVEL(OUTPUTIDLELEVEL)\
+ (((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_INACTIVE) || \
+ ((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_ACTIVE))
+
+#define IS_HRTIM_OUTPUTFAULTLEVEL(OUTPUTFAULTLEVEL)\
+ (((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_NONE) || \
+ ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_ACTIVE) || \
+ ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_INACTIVE) || \
+ ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_HIGHZ))
+
+#define IS_HRTIM_OUTPUTCHOPPERMODE(OUTPUTCHOPPERMODE)\
+ (((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_DISABLED) || \
+ ((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_ENABLED))
+
+#define IS_HRTIM_OUTPUTBURSTMODEENTRY(OUTPUTBURSTMODEENTRY)\
+ (((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_REGULAR) || \
+ ((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_DELAYED))
+
+
+#define IS_HRTIM_TIMER_CAPTURETRIGGER(TIMER, CAPTURETRIGGER) \
+ (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_NONE) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_UPDATE) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_1) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_2) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_3) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_4) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_5) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_6) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_7) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_8) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_9) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_10) \
+ || \
+ (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \
+ (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \
+ || \
+ (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \
+ (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \
+ || \
+ (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \
+ (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \
+ || \
+ (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \
+ (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \
+ || \
+ (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \
+ (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2))))
+
+#define IS_HRTIM_TIMEVENTFILTER(TIMEVENTFILTER)\
+ (((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_NONE) || \
+ ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP1) || \
+ ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP2) || \
+ ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP3) || \
+ ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP4) || \
+ ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR1) || \
+ ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR2) || \
+ ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR3) || \
+ ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR4) || \
+ ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR5) || \
+ ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR6) || \
+ ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR7) || \
+ ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR8) || \
+ ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP2) || \
+ ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP3) || \
+ ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGTIM))
+
+#define IS_HRTIM_TIMEVENTLATCH(TIMEVENTLATCH)\
+ (((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_DISABLED) || \
+ ((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_ENABLED))
+
+#define IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(PRESCALERRATIO)\
+ (((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8) || \
+ ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4) || \
+ ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2) || \
+ ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1) || \
+ ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2) || \
+ ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4) || \
+ ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8) || \
+ ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16))
+
+#define IS_HRTIM_TIMDEADTIME_RISINGSIGN(RISINGSIGN)\
+ (((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE) || \
+ ((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE))
+
+#define IS_HRTIM_TIMDEADTIME_RISINGLOCK(RISINGLOCK)\
+ (((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_WRITE) || \
+ ((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_READONLY))
+
+#define IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(RISINGSIGNLOCK)\
+ (((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE) || \
+ ((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY))
+
+#define IS_HRTIM_TIMDEADTIME_FALLINGSIGN(FALLINGSIGN)\
+ (((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE) || \
+ ((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE))
+
+#define IS_HRTIM_TIMDEADTIME_FALLINGLOCK(FALLINGLOCK)\
+ (((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE) || \
+ ((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY))
+
+#define IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(FALLINGSIGNLOCK)\
+ (((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE) || \
+ ((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY))
+
+#define IS_HRTIM_CHOPPER_PRESCALERRATIO(PRESCALERRATIO)\
+ (((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV16) || \
+ ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV32) || \
+ ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV48) || \
+ ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV64) || \
+ ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV80) || \
+ ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV96) || \
+ ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV112) || \
+ ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV128) || \
+ ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV144) || \
+ ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV160) || \
+ ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV176) || \
+ ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV192) || \
+ ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV208) || \
+ ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV224) || \
+ ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV240) || \
+ ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV256))
+
+#define IS_HRTIM_CHOPPER_DUTYCYCLE(DUTYCYCLE)\
+ (((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_0) || \
+ ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_125) || \
+ ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_250) || \
+ ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_375) || \
+ ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_500) || \
+ ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_625) || \
+ ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_750) || \
+ ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_875))
+
+#define IS_HRTIM_CHOPPER_PULSEWIDTH(PULSEWIDTH)\
+ (((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_16) || \
+ ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_32) || \
+ ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_48) || \
+ ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_64) || \
+ ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_80) || \
+ ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_96) || \
+ ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_112) || \
+ ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_128) || \
+ ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_144) || \
+ ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_160) || \
+ ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_176) || \
+ ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_192) || \
+ ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_208) || \
+ ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_224) || \
+ ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_240) || \
+ ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_256))
+
+#define IS_HRTIM_SYNCINPUTSOURCE(SYNCINPUTSOURCE)\
+ (((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_NONE) || \
+ ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_INTERNALEVENT) || \
+ ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT))
+
+#define IS_HRTIM_SYNCOUTPUTSOURCE(SYNCOUTPUTSOURCE)\
+ (((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_START) || \
+ ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1) || \
+ ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_START) || \
+ ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1))
+
+#define IS_HRTIM_SYNCOUTPUTPOLARITY(SYNCOUTPUTPOLARITY)\
+ (((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NONE) || \
+ ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_POSITIVE) || \
+ ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE))
+
+#define IS_HRTIM_EVENTSRC(EVENTSRC)\
+ (((EVENTSRC) == HRTIM_EVENTSRC_1) || \
+ ((EVENTSRC) == HRTIM_EVENTSRC_2) || \
+ ((EVENTSRC) == HRTIM_EVENTSRC_3) || \
+ ((EVENTSRC) == HRTIM_EVENTSRC_4))
+
+#define IS_HRTIM_EVENTPOLARITY(EVENTSENSITIVITY, EVENTPOLARITY)\
+ ((((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) && \
+ (((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_HIGH) || \
+ ((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_LOW))) \
+ || \
+ (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \
+ ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE)|| \
+ ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES)))
+
+#define IS_HRTIM_EVENTSENSITIVITY(EVENTSENSITIVITY)\
+ (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) || \
+ ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \
+ ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE) || \
+ ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES))
+
+#define IS_HRTIM_EVENTFASTMODE(EVENT, FASTMODE)\
+ (((((EVENT) == HRTIM_EVENT_1) || \
+ ((EVENT) == HRTIM_EVENT_2) || \
+ ((EVENT) == HRTIM_EVENT_3) || \
+ ((EVENT) == HRTIM_EVENT_4) || \
+ ((EVENT) == HRTIM_EVENT_5)) && \
+ (((FASTMODE) == HRTIM_EVENTFASTMODE_ENABLE) || \
+ ((FASTMODE) == HRTIM_EVENTFASTMODE_DISABLE))) \
+ || \
+ (((EVENT) == HRTIM_EVENT_6) || \
+ ((EVENT) == HRTIM_EVENT_7) || \
+ ((EVENT) == HRTIM_EVENT_8) || \
+ ((EVENT) == HRTIM_EVENT_9) || \
+ ((EVENT) == HRTIM_EVENT_10)))
+
+
+#define IS_HRTIM_EVENTFILTER(EVENT, FILTER)\
+ ((((EVENT) == HRTIM_EVENT_1) || \
+ ((EVENT) == HRTIM_EVENT_2) || \
+ ((EVENT) == HRTIM_EVENT_3) || \
+ ((EVENT) == HRTIM_EVENT_4) || \
+ ((EVENT) == HRTIM_EVENT_5)) \
+ || \
+ ((((EVENT) == HRTIM_EVENT_6) || \
+ ((EVENT) == HRTIM_EVENT_7) || \
+ ((EVENT) == HRTIM_EVENT_8) || \
+ ((EVENT) == HRTIM_EVENT_9) || \
+ ((EVENT) == HRTIM_EVENT_10)) && \
+ (((FILTER) == HRTIM_EVENTFILTER_NONE) || \
+ ((FILTER) == HRTIM_EVENTFILTER_1) || \
+ ((FILTER) == HRTIM_EVENTFILTER_2) || \
+ ((FILTER) == HRTIM_EVENTFILTER_3) || \
+ ((FILTER) == HRTIM_EVENTFILTER_4) || \
+ ((FILTER) == HRTIM_EVENTFILTER_5) || \
+ ((FILTER) == HRTIM_EVENTFILTER_6) || \
+ ((FILTER) == HRTIM_EVENTFILTER_7) || \
+ ((FILTER) == HRTIM_EVENTFILTER_8) || \
+ ((FILTER) == HRTIM_EVENTFILTER_9) || \
+ ((FILTER) == HRTIM_EVENTFILTER_10) || \
+ ((FILTER) == HRTIM_EVENTFILTER_11) || \
+ ((FILTER) == HRTIM_EVENTFILTER_12) || \
+ ((FILTER) == HRTIM_EVENTFILTER_13) || \
+ ((FILTER) == HRTIM_EVENTFILTER_14) || \
+ ((FILTER) == HRTIM_EVENTFILTER_15))))
+
+#define IS_HRTIM_EVENTPRESCALER(EVENTPRESCALER)\
+ (((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV1) || \
+ ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV2) || \
+ ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV4) || \
+ ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV8))
+
+#define IS_HRTIM_FAULTSOURCE(FAULTSOURCE)\
+ (((FAULTSOURCE) == HRTIM_FAULTSOURCE_DIGITALINPUT) || \
+ ((FAULTSOURCE) == HRTIM_FAULTSOURCE_INTERNAL))
+
+#define IS_HRTIM_FAULTPOLARITY(HRTIM_FAULTPOLARITY)\
+ (((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_LOW) || \
+ ((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_HIGH))
+
+#define IS_HRTIM_FAULTMODECTL(FAULTMODECTL)\
+ (((FAULTMODECTL) == HRTIM_FAULTMODECTL_DISABLED) || \
+ ((FAULTMODECTL) == HRTIM_FAULTMODECTL_ENABLED))
+
+#define IS_HRTIM_FAULTFILTER(FAULTFILTER)\
+ (((FAULTFILTER) == HRTIM_FAULTFILTER_NONE) || \
+ ((FAULTFILTER) == HRTIM_FAULTFILTER_1) || \
+ ((FAULTFILTER) == HRTIM_FAULTFILTER_2) || \
+ ((FAULTFILTER) == HRTIM_FAULTFILTER_3) || \
+ ((FAULTFILTER) == HRTIM_FAULTFILTER_4) || \
+ ((FAULTFILTER) == HRTIM_FAULTFILTER_5) || \
+ ((FAULTFILTER) == HRTIM_FAULTFILTER_6) || \
+ ((FAULTFILTER) == HRTIM_FAULTFILTER_7) || \
+ ((FAULTFILTER) == HRTIM_FAULTFILTER_8) || \
+ ((FAULTFILTER) == HRTIM_FAULTFILTER_9) || \
+ ((FAULTFILTER) == HRTIM_FAULTFILTER_10) || \
+ ((FAULTFILTER) == HRTIM_FAULTFILTER_11) || \
+ ((FAULTFILTER) == HRTIM_FAULTFILTER_12) || \
+ ((FAULTFILTER) == HRTIM_FAULTFILTER_13) || \
+ ((FAULTFILTER) == HRTIM_FAULTFILTER_14) || \
+ ((FAULTFILTER) == HRTIM_FAULTFILTER_15))
+
+#define IS_HRTIM_FAULTLOCK(FAULTLOCK)\
+ (((FAULTLOCK) == HRTIM_FAULTLOCK_READWRITE) || \
+ ((FAULTLOCK) == HRTIM_FAULTLOCK_READONLY))
+
+#define IS_HRTIM_FAULTPRESCALER(FAULTPRESCALER)\
+ (((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV1) || \
+ ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV2) || \
+ ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV4) || \
+ ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV8))
+
+#define IS_HRTIM_BURSTMODE(BURSTMODE)\
+ (((BURSTMODE) == HRTIM_BURSTMODE_SINGLESHOT) || \
+ ((BURSTMODE) == HRTIM_BURSTMODE_CONTINOUS))
+
+#define IS_HRTIM_BURSTMODECLOCKSOURCE(BURSTMODECLOCKSOURCE)\
+ (((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_MASTER) || \
+ ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_A) || \
+ ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_B) || \
+ ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_C) || \
+ ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_D) || \
+ ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_E) || \
+ ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC) || \
+ ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC) || \
+ ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO) || \
+ ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_FHRTIM))
+
+#define IS_HRTIM_HRTIM_BURSTMODEPRESCALER(BURSTMODEPRESCALER)\
+ (((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1) || \
+ ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2) || \
+ ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4) || \
+ ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8) || \
+ ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16) || \
+ ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32) || \
+ ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV64) || \
+ ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV128) || \
+ ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV256) || \
+ ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV512) || \
+ ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1024) || \
+ ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2048) || \
+ ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4096) || \
+ ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8192) || \
+ ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16384) || \
+ ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32768))
+
+#define IS_HRTIM_BURSTMODEPRELOAD(BURSTMODEPRELOAD)\
+ (((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_DISABLED) || \
+ ((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_ENABLED))
+
+#define IS_HRTIM_BURSTMODETRIGGER(BURSTMODETRIGGER)\
+ (((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_NONE) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_RESET) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_REPETITION) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP1) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP2) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP3) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP4) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_RESET) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP1) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP2) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_RESET) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP1) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP2) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_RESET) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP1) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP2) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_RESET) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP1) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP2) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_RESET) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP1) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP2) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_7) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_8) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP))
+
+#define IS_HRTIM_ADCTRIGGERUPDATE(ADCTRIGGERUPDATE)\
+ (((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_MASTER) || \
+ ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_A) || \
+ ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_B) || \
+ ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_C) || \
+ ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_D) || \
+ ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_E))
+
+#define IS_HRTIM_CALIBRATIONRATE(CALIBRATIONRATE)\
+ (((CALIBRATIONRATE) == HRTIM_SINGLE_CALIBRATION) || \
+ ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_7300) || \
+ ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_910) || \
+ ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_114) || \
+ ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_14))
+
+#define IS_HRTIM_TIMER_BURSTDMA(TIMER, BURSTDMA) \
+ ((((TIMER) == HRTIM_TIMERINDEX_MASTER) && (((BURSTDMA) & 0xFFFFFC000U) == 0x00000000U)) \
+ || \
+ (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
+ || \
+ (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
+ || \
+ (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
+ || \
+ (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
+ || \
+ (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)))
+
+#define IS_HRTIM_BURSTMODECTL(BURSTMODECTL)\
+ (((BURSTMODECTL) == HRTIM_BURSTMODECTL_DISABLED) || \
+ ((BURSTMODECTL) == HRTIM_BURSTMODECTL_ENABLED))
+
+
+#define IS_HRTIM_TIMERUPDATE(TIMERUPDATE) (((TIMERUPDATE) & 0xFFFFFFC0U) == 0x00000000U)
+
+#define IS_HRTIM_TIMERRESET(TIMERRESET) (((TIMERRESET) & 0xFFFFC0FFU) == 0x00000000U)
+
+#define IS_HRTIM_IT(IT) (((IT) & 0xFFFCFFC0U) == 0x00000000U)
+
+
+#define IS_HRTIM_MASTER_IT(MASTER_IT) (((MASTER_IT) & 0xFFFFFF80U) == 0x00000000U)
+
+
+#define IS_HRTIM_TIM_IT(TIM_IT) (((TIM_IT) & 0xFFFF8020U) == 0x00000000U)
+
+
+#define IS_HRTIM_MASTER_DMA(MASTER_DMA) (((MASTER_DMA) & 0xFF80FFFFU) == 0x00000000U)
+
+#define IS_HRTIM_TIM_DMA(TIM_DMA) (((TIM_DMA) & 0x8020FFFFU) == 0x00000000U)
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup HRTIM_Exported_Macros HRTIM Exported Macros
+ * @{
+ */
+
+/** @brief Reset HRTIM handle state
+ * @param __HANDLE__ HRTIM handle.
+ * @retval None
+ */
+#define __HAL_HRTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HRTIM_STATE_RESET)
+
+/** @brief Enables or disables the timer counter(s)
+ * @param __HANDLE__ specifies the HRTIM Handle.
+ * @param __TIMERS__ timers to enable/disable
+ * This parameter can be any combinations of the following values:
+ * @arg HRTIM_TIMERID_MASTER: Master timer identifier
+ * @arg HRTIM_TIMERID_TIMER_A: Timer A identifier
+ * @arg HRTIM_TIMERID_TIMER_B: Timer B identifier
+ * @arg HRTIM_TIMERID_TIMER_C: Timer C identifier
+ * @arg HRTIM_TIMERID_TIMER_D: Timer D identifier
+ * @arg HRTIM_TIMERID_TIMER_E: Timer E identifier
+ * @retval None
+ */
+#define __HAL_HRTIM_ENABLE(__HANDLE__, __TIMERS__) ((__HANDLE__)->Instance->sMasterRegs.MCR |= (__TIMERS__))
+
+/* The counter of a timing unit is disabled only if all the timer outputs */
+/* are disabled and no capture is configured */
+#define HRTIM_TAOEN_MASK (HRTIM_OENR_TA2OEN | HRTIM_OENR_TA1OEN)
+#define HRTIM_TBOEN_MASK (HRTIM_OENR_TB2OEN | HRTIM_OENR_TB1OEN)
+#define HRTIM_TCOEN_MASK (HRTIM_OENR_TC2OEN | HRTIM_OENR_TC1OEN)
+#define HRTIM_TDOEN_MASK (HRTIM_OENR_TD2OEN | HRTIM_OENR_TD1OEN)
+#define HRTIM_TEOEN_MASK (HRTIM_OENR_TE2OEN | HRTIM_OENR_TE1OEN)
+#define __HAL_HRTIM_DISABLE(__HANDLE__, __TIMERS__)\
+ do {\
+ if (((__TIMERS__) & HRTIM_TIMERID_MASTER) == HRTIM_TIMERID_MASTER)\
+ {\
+ ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_MASTER);\
+ }\
+ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_A) == HRTIM_TIMERID_TIMER_A)\
+ {\
+ if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TAOEN_MASK) == RESET)\
+ {\
+ ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_A);\
+ }\
+ }\
+ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_B) == HRTIM_TIMERID_TIMER_B)\
+ {\
+ if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TBOEN_MASK) == RESET)\
+ {\
+ ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_B);\
+ }\
+ }\
+ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_C) == HRTIM_TIMERID_TIMER_C)\
+ {\
+ if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TCOEN_MASK) == RESET)\
+ {\
+ ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_C);\
+ }\
+ }\
+ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_D) == HRTIM_TIMERID_TIMER_D)\
+ {\
+ if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TDOEN_MASK) == RESET)\
+ {\
+ ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_D);\
+ }\
+ }\
+ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_E) == HRTIM_TIMERID_TIMER_E)\
+ {\
+ if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TEOEN_MASK) == RESET)\
+ {\
+ ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_E);\
+ }\
+ }\
+ } while(0U)
+
+
+/** @brief Enables or disables the specified HRTIM common interrupts.
+ * @param __HANDLE__ specifies the HRTIM Handle.
+ * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
+ * @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
+ * @arg HRTIM_IT_FLT3: Fault 3 interrupt enable
+ * @arg HRTIM_IT_FLT4: Fault 4 interrupt enable
+ * @arg HRTIM_IT_FLT5: Fault 5 interrupt enable
+ * @arg HRTIM_IT_SYSFLT: System Fault interrupt enable
+ * @arg HRTIM_IT_DLLRDY: DLL ready interrupt enable
+ * @arg HRTIM_IT_BMPER: Burst mode period interrupt enable
+ * @retval None
+ */
+#define __HAL_HRTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER |= (__INTERRUPT__))
+#define __HAL_HRTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER &= ~(__INTERRUPT__))
+
+/** @brief Enables or disables the specified HRTIM Master timer interrupts.
+ * @param __HANDLE__ specifies the HRTIM Handle.
+ * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
+ * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
+ * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
+ * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
+ * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
+ * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
+ * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
+ * @retval None
+ */
+#define __HAL_HRTIM_MASTER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__INTERRUPT__))
+#define __HAL_HRTIM_MASTER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__INTERRUPT__))
+
+/** @brief Enables or disables the specified HRTIM Timerx interrupts.
+ * @param __HANDLE__ specifies the HRTIM Handle.
+ * @param __TIMER__ specified the timing unit (Timer A to E)
+ * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable
+ * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable
+ * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt enable
+ * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt enable
+ * @arg HRTIM_TIM_IT_REP: Timer repetition interrupt enable
+ * @arg HRTIM_TIM_IT_UPD: Timer update interrupt enable
+ * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt enable
+ * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt enable
+ * @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt enable
+ * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt enable
+ * @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt enable
+ * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt enable
+ * @arg HRTIM_TIM_IT_RST: Timer reset interrupt enable
+ * @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable
+ * @retval None
+ */
+#define __HAL_HRTIM_TIMER_ENABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__INTERRUPT__))
+#define __HAL_HRTIM_TIMER_DISABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__INTERRUPT__))
+
+/** @brief Checks if the specified HRTIM common interrupt source is enabled or disabled.
+ * @param __HANDLE__ specifies the HRTIM Handle.
+ * @param __INTERRUPT__ specifies the interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
+ * @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
+ * @arg HRTIM_IT_FLT3: Fault 3 enable
+ * @arg HRTIM_IT_FLT4: Fault 4 enable
+ * @arg HRTIM_IT_FLT5: Fault 5 enable
+ * @arg HRTIM_IT_SYSFLT: System Fault interrupt enable
+ * @arg HRTIM_IT_DLLRDY: DLL ready interrupt enable
+ * @arg HRTIM_IT_BMPER: Burst mode period interrupt enable
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+ */
+#define __HAL_HRTIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sCommonRegs.IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Checks if the specified HRTIM Master interrupt source is enabled or disabled.
+ * @param __HANDLE__ specifies the HRTIM Handle.
+ * @param __INTERRUPT__ specifies the interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
+ * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
+ * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
+ * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
+ * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
+ * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
+ * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+ */
+#define __HAL_HRTIM_MASTER_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sMasterRegs.MDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Checks if the specified HRTIM Timerx interrupt source is enabled or disabled.
+ * @param __HANDLE__ specifies the HRTIM Handle.
+ * @param __TIMER__ specified the timing unit (Timer A to E)
+ * @param __INTERRUPT__ specifies the interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
+ * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
+ * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
+ * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
+ * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
+ * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
+ * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
+ * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable
+ * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable
+ * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt enable
+ * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt enable
+ * @arg HRTIM_TIM_IT_REP: Timer repetition interrupt enable
+ * @arg HRTIM_TIM_IT_UPD: Timer update interrupt enable
+ * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt enable
+ * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt enable
+ * @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt enable
+ * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt enable
+ * @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt enable
+ * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt enable
+ * @arg HRTIM_TIM_IT_RST: Timer reset interrupt enable
+ * @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+ */
+#define __HAL_HRTIM_TIMER_GET_ITSTATUS(__HANDLE__, __TIMER__, __INTERRUPT__) ((((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Clears the specified HRTIM common pending flag.
+ * @param __HANDLE__ specifies the HRTIM Handle.
+ * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
+ * This parameter can be one of the following values:
+ * @arg HRTIM_IT_FLT1: Fault 1 interrupt clear flag
+ * @arg HRTIM_IT_FLT2: Fault 2 interrupt clear flag
+ * @arg HRTIM_IT_FLT3: Fault 3 clear flag
+ * @arg HRTIM_IT_FLT4: Fault 4 clear flag
+ * @arg HRTIM_IT_FLT5: Fault 5 clear flag
+ * @arg HRTIM_IT_SYSFLT: System Fault interrupt clear flag
+ * @arg HRTIM_IT_DLLRDY: DLL ready interrupt clear flag
+ * @arg HRTIM_IT_BMPER: Burst mode period interrupt clear flag
+ * @retval None
+ */
+#define __HAL_HRTIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.ICR = (__INTERRUPT__))
+
+/** @brief Clears the specified HRTIM Master pending flag.
+ * @param __HANDLE__ specifies the HRTIM Handle.
+ * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
+ * This parameter can be one of the following values:
+ * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt clear flag
+ * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt clear flag
+ * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt clear flag
+ * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt clear flag
+ * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt clear flag
+ * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt clear flag
+ * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt clear flag
+ * @retval None
+ */
+#define __HAL_HRTIM_MASTER_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MICR = (__INTERRUPT__))
+
+/** @brief Clears the specified HRTIM Timerx pending flag.
+ * @param __HANDLE__ specifies the HRTIM Handle.
+ * @param __TIMER__ specified the timing unit (Timer A to E)
+ * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt clear flag
+ * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt clear flag
+ * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt clear flag
+ * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt clear flag
+ * @arg HRTIM_TIM_IT_REP: Timer repetition interrupt clear flag
+ * @arg HRTIM_TIM_IT_UPD: Timer update interrupt clear flag
+ * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt clear flag
+ * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt clear flag
+ * @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt clear flag
+ * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt clear flag
+ * @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt clear flag
+ * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt clear flag
+ * @arg HRTIM_TIM_IT_RST: Timer reset interrupt clear flag
+ * @arg HRTIM_TIM_IT_DLYPRT: Timer output 1 delay protection interrupt clear flag
+ * @retval None
+ */
+#define __HAL_HRTIM_TIMER_CLEAR_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__INTERRUPT__))
+
+/* DMA HANDLING */
+/** @brief Enables or disables the specified HRTIM common interrupts.
+ * @param __HANDLE__ specifies the HRTIM Handle.
+ * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
+ * @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
+ * @arg HRTIM_IT_FLT3: Fault 3 interrupt enable
+ * @arg HRTIM_IT_FLT4: Fault 4 interrupt enable
+ * @arg HRTIM_IT_FLT5: Fault 5 interrupt enable
+ * @arg HRTIM_IT_SYSFLT: System Fault interrupt enable
+ * @arg HRTIM_IT_DLLRDY: DLL ready interrupt enable
+ * @arg HRTIM_IT_BMPER: Burst mode period interrupt enable
+ * @retval None
+ */
+#define __HAL_HRTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER |= (__INTERRUPT__))
+#define __HAL_HRTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER &= ~(__INTERRUPT__))
+
+/** @brief Enables or disables the specified HRTIM Master timer DMA requets.
+ * @param __HANDLE__ specifies the HRTIM Handle.
+ * @param __DMA__ specifies the DMA request to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg HRTIM_MASTER_DMA_MCMP1: Master compare 1 DMA resquest enable
+ * @arg HRTIM_MASTER_DMA_MCMP2: Master compare 2 DMA resquest enable
+ * @arg HRTIM_MASTER_DMA_MCMP3: Master compare 3 DMA resquest enable
+ * @arg HRTIM_MASTER_DMA_MCMP4: Master compare 4 DMA resquest enable
+ * @arg HRTIM_MASTER_DMA_MREP: Master Repetition DMA resquest enable
+ * @arg HRTIM_MASTER_DMA_SYNC: Synchronization input DMA resquest enable
+ * @arg HRTIM_MASTER_DMA_MUPD: Master update DMA resquest enable
+ * @retval None
+ */
+#define __HAL_HRTIM_MASTER_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__DMA__))
+#define __HAL_HRTIM_MASTER_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__DMA__))
+
+/** @brief Enables or disables the specified HRTIM Timerx DMA requests.
+ * @param __HANDLE__ specifies the HRTIM Handle.
+ * @param __TIMER__ specified the timing unit (Timer A to E)
+ * @param __DMA__ specifies the DMA request to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIM_DMA_CMP1: Timer compare 1 DMA resquest enable
+ * @arg HRTIM_TIM_DMA_CMP2: Timer compare 2 DMA resquest enable
+ * @arg HRTIM_TIM_DMA_CMP3: Timer compare 3 DMA resquest enable
+ * @arg HRTIM_TIM_DMA_CMP4: Timer compare 4 DMA resquest enable
+ * @arg HRTIM_TIM_DMA_REP: Timer repetition DMA resquest enable
+ * @arg HRTIM_TIM_DMA_UPD: Timer update DMA resquest enable
+ * @arg HRTIM_TIM_DMA_CPT1: Timer capture 1 DMA resquest enable
+ * @arg HRTIM_TIM_DMA_CPT2: Timer capture 2 DMA resquest enable
+ * @arg HRTIM_TIM_DMA_SET1: Timer output 1 set DMA resquest enable
+ * @arg HRTIM_TIM_DMA_RST1: Timer output 1 reset DMA resquest enable
+ * @arg HRTIM_TIM_DMA_SET2: Timer output 2 set DMA resquest enable
+ * @arg HRTIM_TIM_DMA_RST2: Timer output 2 reset DMA resquest enable
+ * @arg HRTIM_TIM_DMA_RST: Timer reset DMA resquest enable
+ * @arg HRTIM_TIM_DMA_DLYPRT: Timer delay protection DMA resquest enable
+ * @retval None
+ */
+#define __HAL_HRTIM_TIMER_ENABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__DMA__))
+#define __HAL_HRTIM_TIMER_DISABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__DMA__))
+
+#define __HAL_HRTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sCommonRegs.ISR & (__FLAG__)) == (__FLAG__))
+#define __HAL_HRTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->sCommonRegs.ICR = (__FLAG__))
+
+#define __HAL_HRTIM_MASTER_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sMasterRegs.MISR & (__FLAG__)) == (__FLAG__))
+#define __HAL_HRTIM_MASTER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->sMasterRegs.MICR = (__FLAG__))
+
+#define __HAL_HRTIM_TIMER_GET_FLAG(__HANDLE__, __TIMER__, __FLAG__) (((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxISR & (__FLAG__)) == (__FLAG__))
+#define __HAL_HRTIM_TIMER_CLEAR_FLAG(__HANDLE__, __TIMER__, __FLAG__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__FLAG__))
+
+/** @brief Sets the HRTIM timer Counter Register value on runtime
+ * @param __HANDLE__ HRTIM Handle.
+ * @param __TIMER__ HRTIM timer
+ * This parameter can be one of the following values:
+ * @arg 0x5 for master timer
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param __COUNTER__ specifies the Counter Register new value.
+ * @retval None
+ */
+#define __HAL_HRTIM_SETCOUNTER(__HANDLE__, __TIMER__, __COUNTER__) \
+ (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCNTR = (__COUNTER__)) :\
+ ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR = (__COUNTER__)))
+
+/** @brief Gets the HRTIM timer Counter Register value on runtime
+ * @param __HANDLE__ HRTIM Handle.
+ * @param __TIMER__ HRTIM timer
+ * This parameter can be one of the following values:
+ * @arg 0x5 for master timer
+ * @arg 0x0 to 0x4 for timers A to E
+ * @retval HRTIM timer Counter Register value
+ */
+#define __HAL_HRTIM_GETCOUNTER(__HANDLE__, __TIMER__) \
+ (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCNTR) :\
+ ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR))
+
+/** @brief Sets the HRTIM timer Period value on runtime
+ * @param __HANDLE__ HRTIM Handle.
+ * @param __TIMER__ HRTIM timer
+ * This parameter can be one of the following values:
+ * @arg 0x5 for master timer
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param __PERIOD__ specifies the Period Register new value.
+ * @retval None
+ */
+#define __HAL_HRTIM_SETPERIOD(__HANDLE__, __TIMER__, __PERIOD__) \
+ (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MPER = (__PERIOD__)) :\
+ ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR = (__PERIOD__)))
+
+/** @brief Gets the HRTIM timer Period Register value on runtime
+ * @param __HANDLE__ HRTIM Handle.
+ * @param __TIMER__ HRTIM timer
+ * This parameter can be one of the following values:
+ * @arg 0x5 for master timer
+ * @arg 0x0 to 0x4 for timers A to E
+ * @retval timer Period Register
+ */
+#define __HAL_HRTIM_GETPERIOD(__HANDLE__, __TIMER__) \
+ (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MPER) :\
+ ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR))
+
+/** @brief Sets the HRTIM timer clock prescaler value on runtime
+ * @param __HANDLE__ HRTIM Handle.
+ * @param __TIMER__ HRTIM timer
+ * This parameter can be one of the following values:
+ * @arg 0x5 for master timer
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param __PRESCALER__ specifies the clock prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg HRTIM_PRESCALERRATIO_MUL32: fHRCK: 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz)
+ * @arg HRTIM_PRESCALERRATIO_MUL16: fHRCK: 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz)
+ * @arg HRTIM_PRESCALERRATIO_MUL8: fHRCK: 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz)
+ * @arg HRTIM_PRESCALERRATIO_MUL4: fHRCK: 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz)
+ * @arg HRTIM_PRESCALERRATIO_MUL2: fHRCK: 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz)
+ * @arg HRTIM_PRESCALERRATIO_DIV1: fHRCK: 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz)
+ * @arg HRTIM_PRESCALERRATIO_DIV2: fHRCK: 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz)
+ * @arg HRTIM_PRESCALERRATIO_DIV4: fHRCK: 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz)
+ * @retval None
+ */
+#define __HAL_HRTIM_SETCLOCKPRESCALER(__HANDLE__, __TIMER__, __PRESCALER__) \
+ (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? (MODIFY_REG((__HANDLE__)->Instance->sMasterRegs.MCR, HRTIM_MCR_CK_PSC, (__PRESCALER__))) :\
+ (MODIFY_REG((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR, HRTIM_TIMCR_CK_PSC, (__PRESCALER__))))
+
+/** @brief Gets the HRTIM timer clock prescaler value on runtime
+ * @param __HANDLE__ HRTIM Handle.
+ * @param __TIMER__ HRTIM timer
+ * This parameter can be one of the following values:
+ * @arg 0x5 for master timer
+ * @arg 0x0 to 0x4 for timers A to E
+ * @retval timer clock prescaler value
+ */
+#define __HAL_HRTIM_GETCLOCKPRESCALER(__HANDLE__, __TIMER__) \
+ (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCR & HRTIM_MCR_CK_PSC) :\
+ ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR & HRTIM_TIMCR_CK_PSC))
+
+/** @brief Sets the HRTIM timer Compare Register value on runtime
+ * @param __HANDLE__ HRTIM Handle.
+ * @param __TIMER__ HRTIM timer
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param __COMPAREUNIT__ timer compare unit
+ * This parameter can be one of the following values:
+ * @arg HRTIM_COMPAREUNIT_1: Compare unit 1
+ * @arg HRTIM_COMPAREUNIT_2: Compare unit 2
+ * @arg HRTIM_COMPAREUNIT_3: Compare unit 3
+ * @arg HRTIM_COMPAREUNIT_4: Compare unit 4
+ * @param __COMPARE__ specifies the Compare new value.
+ * @retval None
+ */
+#define __HAL_HRTIM_SETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__, __COMPARE__) \
+ (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \
+ (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R = (__COMPARE__)) :\
+ ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R = (__COMPARE__)) :\
+ ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R = (__COMPARE__)) :\
+ ((__HANDLE__)->Instance->sMasterRegs.MCMP4R = (__COMPARE__))) \
+ : \
+ (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR = (__COMPARE__)) :\
+ ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR = (__COMPARE__)) :\
+ ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR = (__COMPARE__)) :\
+ ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR = (__COMPARE__))))
+
+/** @brief Gets the HRTIM timer Compare Register value on runtime
+ * @param __HANDLE__ HRTIM Handle.
+ * @param __TIMER__ HRTIM timer
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param __COMPAREUNIT__ timer compare unit
+ * This parameter can be one of the following values:
+ * @arg HRTIM_COMPAREUNIT_1: Compare unit 1
+ * @arg HRTIM_COMPAREUNIT_2: Compare unit 2
+ * @arg HRTIM_COMPAREUNIT_3: Compare unit 3
+ * @arg HRTIM_COMPAREUNIT_4: Compare unit 4
+ * @retval Compare value
+ */
+#define __HAL_HRTIM_GETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__) \
+ (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \
+ (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R) :\
+ ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R) :\
+ ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R) :\
+ ((__HANDLE__)->Instance->sMasterRegs.MCMP4R)) \
+ : \
+ (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR) :\
+ ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR) :\
+ ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR) :\
+ ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR)))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup HRTIM_Exported_Functions
+* @{
+*/
+
+/** @addtogroup HRTIM_Exported_Functions_Group1
+* @{
+*/
+
+/* Initialization and Configuration functions ********************************/
+HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef *hhrtim);
+
+HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef *hhrtim);
+
+void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef *hhrtim);
+
+void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef *hhrtim);
+
+HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
+
+HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t CalibrationRate);
+
+HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart_IT(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t CalibrationRate);
+
+HAL_StatusTypeDef HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t Timeout);
+
+/**
+ * @}
+ */
+
+/** @addtogroup HRTIM_Exported_Functions_Group2
+* @{
+*/
+
+/* Simple time base related functions *****************************************/
+HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t SrcAddr,
+ uint32_t DestAddr,
+ uint32_t Length);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx);
+
+/**
+ * @}
+ */
+
+/** @addtogroup HRTIM_Exported_Functions_Group3
+* @{
+*/
+/* Simple output compare related functions ************************************/
+HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OCChannel,
+ HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OCChannel);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OCChannel);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OCChannel);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OCChannel);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OCChannel,
+ uint32_t SrcAddr,
+ uint32_t DestAddr,
+ uint32_t Length);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OCChannel);
+
+/**
+ * @}
+ */
+
+/** @addtogroup HRTIM_Exported_Functions_Group4
+* @{
+*/
+/* Simple PWM output related functions ****************************************/
+HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t PWMChannel,
+ HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg);
+
+HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t PWMChannel);
+
+HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t PWMChannel);
+
+HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t PWMChannel);
+
+HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t PWMChannel);
+
+HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t PWMChannel,
+ uint32_t SrcAddr,
+ uint32_t DestAddr,
+ uint32_t Length);
+
+HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t PWMChannel);
+
+/**
+ * @}
+ */
+
+/** @addtogroup HRTIM_Exported_Functions_Group5
+* @{
+*/
+/* Simple capture related functions *******************************************/
+HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureChannel,
+ HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureChannel);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureChannel);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureChannel);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureChannel);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureChannel,
+ uint32_t SrcAddr,
+ uint32_t DestAddr,
+ uint32_t Length);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureChannel);
+
+/**
+ * @}
+ */
+
+/** @addtogroup HRTIM_Exported_Functions_Group6
+* @{
+*/
+/* Simple one pulse related functions *****************************************/
+HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OnePulseChannel,
+ HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OnePulseChannel);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OnePulseChannel);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OnePulseChannel);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OnePulseChannel);
+
+/**
+ * @}
+ */
+
+/** @addtogroup HRTIM_Exported_Functions_Group7
+* @{
+*/
+HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef *hhrtim,
+ HRTIM_BurstModeCfgTypeDef* pBurstModeCfg);
+
+HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t Event,
+ HRTIM_EventCfgTypeDef* pEventCfg);
+
+HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t Prescaler);
+
+HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t Fault,
+ HRTIM_FaultCfgTypeDef* pFaultCfg);
+
+HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t Prescaler);
+
+void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t Faults,
+ uint32_t Enable);
+
+HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t ADCTrigger,
+ HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg);
+
+/**
+ * @}
+ */
+
+/** @addtogroup HRTIM_Exported_Functions_Group8
+* @{
+*/
+/* Waveform related functions *************************************************/
+HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ HRTIM_TimerCfgTypeDef * pTimerCfg);
+
+HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CompareUnit,
+ HRTIM_CompareCfgTypeDef* pCompareCfg);
+
+HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureUnit,
+ HRTIM_CaptureCfgTypeDef* pCaptureCfg);
+
+HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t Output,
+ HRTIM_OutputCfgTypeDef * pOutputCfg);
+
+HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t Output,
+ uint32_t OutputLevel);
+
+HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t Event,
+ HRTIM_TimerEventFilteringCfgTypeDef * pTimerEventFilteringCfg);
+
+HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg);
+
+HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg);
+
+HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t RegistersToUpdate);
+
+
+HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t Timers);
+
+HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t Timers);
+
+HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart_IT(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t Timers);
+
+HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop_IT(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t Timers);
+
+HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart_DMA(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t Timers);
+
+HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop_DMA(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t Timers);
+
+HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t OutputsToStart);
+
+HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t OutputsToStop);
+
+HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t Enable);
+
+HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim);
+
+HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureUnit);
+
+HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t Timers);
+
+HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t Timers);
+
+HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t BurstBufferAddress,
+ uint32_t BurstBufferLength);
+
+HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t Timers);
+
+HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t Timers);
+
+/**
+ * @}
+ */
+
+/** @addtogroup HRTIM_Exported_Functions_Group9
+* @{
+*/
+/* HRTIM peripheral state functions */
+HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(HRTIM_HandleTypeDef* hhrtim);
+
+uint32_t HAL_HRTIM_GetCapturedValue(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureUnit);
+
+uint32_t HAL_HRTIM_WaveformGetOutputLevel(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t Output);
+
+uint32_t HAL_HRTIM_WaveformGetOutputState(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t Output);
+
+uint32_t HAL_HRTIM_GetDelayedProtectionStatus(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t Output);
+
+uint32_t HAL_HRTIM_GetBurstStatus(HRTIM_HandleTypeDef *hhrtim);
+
+uint32_t HAL_HRTIM_GetCurrentPushPullStatus(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx);
+
+uint32_t HAL_HRTIM_GetIdlePushPullStatus(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx);
+
+/**
+ * @}
+ */
+
+/** @addtogroup HRTIM_Exported_Functions_Group10
+* @{
+*/
+/* IRQ handler */
+void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx);
+
+/* HRTIM events related callback functions */
+void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef *hhrtim);
+void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef *hhrtim);
+void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef *hhrtim);
+void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef *hhrtim);
+void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef *hhrtim);
+void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef *hhrtim);
+void HAL_HRTIM_DLLCalbrationReadyCallback(HRTIM_HandleTypeDef *hhrtim);
+void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef *hhrtim);
+void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef *hhrtim);
+
+/* Timer events related callback functions */
+void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx);
+void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx);
+void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx);
+void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx);
+void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx);
+void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx);
+void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx);
+void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx);
+void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx);
+void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx);
+void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx);
+void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx);
+void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx);
+void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx);
+void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx);
+void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HRTIM1 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_HRTIM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_hal_i2c.h b/Inc/stm32f3xx_hal_i2c.h
new file mode 100644
index 0000000..682e06b
--- /dev/null
+++ b/Inc/stm32f3xx_hal_i2c.h
@@ -0,0 +1,710 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_i2c.h
+ * @author MCD Application Team
+ * @brief Header file of I2C HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_I2C_H
+#define __STM32F3xx_HAL_I2C_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup I2C
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup I2C_Exported_Types I2C Exported Types
+ * @{
+ */
+
+/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
+ * @brief I2C Configuration Structure definition
+ * @{
+ */
+typedef struct
+{
+ uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value.
+ This parameter calculated by referring to I2C initialization
+ section in Reference manual */
+
+ uint32_t OwnAddress1; /*!< Specifies the first device own address.
+ This parameter can be a 7-bit or 10-bit address. */
+
+ uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
+ This parameter can be a value of @ref I2C_ADDRESSING_MODE */
+
+ uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
+ This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
+
+ uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
+ This parameter can be a 7-bit address. */
+
+ uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
+ This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
+
+ uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
+ This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
+
+ uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
+ This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
+
+} I2C_InitTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_state_structure_definition HAL state structure definition
+ * @brief HAL State structure definition
+ * @note HAL I2C State value coding follow below described bitmap :\n
+ * b7-b6 Error information\n
+ * 00 : No Error\n
+ * 01 : Abort (Abort user request on going)\n
+ * 10 : Timeout\n
+ * 11 : Error\n
+ * b5 IP initilisation status\n
+ * 0 : Reset (IP not initialized)\n
+ * 1 : Init done (IP initialized and ready to use. HAL I2C Init function called)\n
+ * b4 (not used)\n
+ * x : Should be set to 0\n
+ * b3\n
+ * 0 : Ready or Busy (No Listen mode ongoing)\n
+ * 1 : Listen (IP in Address Listen Mode)\n
+ * b2 Intrinsic process state\n
+ * 0 : Ready\n
+ * 1 : Busy (IP busy with some configuration or internal operations)\n
+ * b1 Rx state\n
+ * 0 : Ready (no Rx operation ongoing)\n
+ * 1 : Busy (Rx operation ongoing)\n
+ * b0 Tx state\n
+ * 0 : Ready (no Tx operation ongoing)\n
+ * 1 : Busy (Tx operation ongoing)
+ * @{
+ */
+typedef enum
+{
+ HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
+ HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
+ HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
+ HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */
+ HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
+ HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */
+ HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
+ process is ongoing */
+ HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
+ process is ongoing */
+ HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
+ HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
+ HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
+
+} HAL_I2C_StateTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_mode_structure_definition HAL mode structure definition
+ * @brief HAL Mode structure definition
+ * @note HAL I2C Mode value coding follow below described bitmap :\n
+ * b7 (not used)\n
+ * x : Should be set to 0\n
+ * b6\n
+ * 0 : None\n
+ * 1 : Memory (HAL I2C communication is in Memory Mode)\n
+ * b5\n
+ * 0 : None\n
+ * 1 : Slave (HAL I2C communication is in Slave Mode)\n
+ * b4\n
+ * 0 : None\n
+ * 1 : Master (HAL I2C communication is in Master Mode)\n
+ * b3-b2-b1-b0 (not used)\n
+ * xxxx : Should be set to 0000
+ * @{
+ */
+typedef enum
+{
+ HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */
+ HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */
+ HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
+ HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */
+
+} HAL_I2C_ModeTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Error_Code_definition I2C Error Code definition
+ * @brief I2C Error Code definition
+ * @{
+ */
+#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */
+#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */
+#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */
+#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */
+#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
+#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
+#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */
+/**
+ * @}
+ */
+
+/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
+ * @brief I2C handle Structure definition
+ * @{
+ */
+typedef struct __I2C_HandleTypeDef
+{
+ I2C_TypeDef *Instance; /*!< I2C registers base address */
+
+ I2C_InitTypeDef Init; /*!< I2C communication parameters */
+
+ uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
+
+ uint16_t XferSize; /*!< I2C transfer size */
+
+ __IO uint16_t XferCount; /*!< I2C transfer counter */
+
+ __IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can
+ be a value of @ref I2C_XFEROPTIONS */
+
+ __IO uint32_t PreviousState; /*!< I2C communication Previous state */
+
+ HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */
+
+ DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< I2C locking object */
+
+ __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
+
+ __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */
+
+ __IO uint32_t ErrorCode; /*!< I2C Error code */
+
+ __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */
+} I2C_HandleTypeDef;
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Constants I2C Exported Constants
+ * @{
+ */
+
+/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options
+ * @{
+ */
+#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)
+#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
+#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
+#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
+#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
+#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE)
+/**
+ * @}
+ */
+
+/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
+ * @{
+ */
+#define I2C_ADDRESSINGMODE_7BIT (0x00000001U)
+#define I2C_ADDRESSINGMODE_10BIT (0x00000002U)
+/**
+ * @}
+ */
+
+/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
+ * @{
+ */
+#define I2C_DUALADDRESS_DISABLE (0x00000000U)
+#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
+/**
+ * @}
+ */
+
+/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
+ * @{
+ */
+#define I2C_OA2_NOMASK ((uint8_t)0x00U)
+#define I2C_OA2_MASK01 ((uint8_t)0x01U)
+#define I2C_OA2_MASK02 ((uint8_t)0x02U)
+#define I2C_OA2_MASK03 ((uint8_t)0x03U)
+#define I2C_OA2_MASK04 ((uint8_t)0x04U)
+#define I2C_OA2_MASK05 ((uint8_t)0x05U)
+#define I2C_OA2_MASK06 ((uint8_t)0x06U)
+#define I2C_OA2_MASK07 ((uint8_t)0x07U)
+/**
+ * @}
+ */
+
+/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
+ * @{
+ */
+#define I2C_GENERALCALL_DISABLE (0x00000000U)
+#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
+/**
+ * @}
+ */
+
+/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
+ * @{
+ */
+#define I2C_NOSTRETCH_DISABLE (0x00000000U)
+#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
+/**
+ * @}
+ */
+
+/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
+ * @{
+ */
+#define I2C_MEMADD_SIZE_8BIT (0x00000001U)
+#define I2C_MEMADD_SIZE_16BIT (0x00000002U)
+/**
+ * @}
+ */
+
+/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
+ * @{
+ */
+#define I2C_DIRECTION_TRANSMIT (0x00000000U)
+#define I2C_DIRECTION_RECEIVE (0x00000001U)
+/**
+ * @}
+ */
+
+/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
+ * @{
+ */
+#define I2C_RELOAD_MODE I2C_CR2_RELOAD
+#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
+#define I2C_SOFTEND_MODE (0x00000000U)
+/**
+ * @}
+ */
+
+/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
+ * @{
+ */
+#define I2C_NO_STARTSTOP (0x00000000U)
+#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
+#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
+#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
+ * @brief I2C Interrupt definition
+ * Elements values convention: 0xXXXXXXXX
+ * - XXXXXXXX : Interrupt control mask
+ * @{
+ */
+#define I2C_IT_ERRI I2C_CR1_ERRIE
+#define I2C_IT_TCI I2C_CR1_TCIE
+#define I2C_IT_STOPI I2C_CR1_STOPIE
+#define I2C_IT_NACKI I2C_CR1_NACKIE
+#define I2C_IT_ADDRI I2C_CR1_ADDRIE
+#define I2C_IT_RXI I2C_CR1_RXIE
+#define I2C_IT_TXI I2C_CR1_TXIE
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Flag_definition I2C Flag definition
+ * @{
+ */
+#define I2C_FLAG_TXE I2C_ISR_TXE
+#define I2C_FLAG_TXIS I2C_ISR_TXIS
+#define I2C_FLAG_RXNE I2C_ISR_RXNE
+#define I2C_FLAG_ADDR I2C_ISR_ADDR
+#define I2C_FLAG_AF I2C_ISR_NACKF
+#define I2C_FLAG_STOPF I2C_ISR_STOPF
+#define I2C_FLAG_TC I2C_ISR_TC
+#define I2C_FLAG_TCR I2C_ISR_TCR
+#define I2C_FLAG_BERR I2C_ISR_BERR
+#define I2C_FLAG_ARLO I2C_ISR_ARLO
+#define I2C_FLAG_OVR I2C_ISR_OVR
+#define I2C_FLAG_PECERR I2C_ISR_PECERR
+#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
+#define I2C_FLAG_ALERT I2C_ISR_ALERT
+#define I2C_FLAG_BUSY I2C_ISR_BUSY
+#define I2C_FLAG_DIR I2C_ISR_DIR
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Macros I2C Exported Macros
+ * @{
+ */
+
+/** @brief Reset I2C handle state.
+ * @param __HANDLE__ specifies the I2C Handle.
+ * @retval None
+ */
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
+
+/** @brief Enable the specified I2C interrupt.
+ * @param __HANDLE__ specifies the I2C Handle.
+ * @param __INTERRUPT__ specifies the interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg @ref I2C_IT_ERRI Errors interrupt enable
+ * @arg @ref I2C_IT_TCI Transfer complete interrupt enable
+ * @arg @ref I2C_IT_STOPI STOP detection interrupt enable
+ * @arg @ref I2C_IT_NACKI NACK received interrupt enable
+ * @arg @ref I2C_IT_ADDRI Address match interrupt enable
+ * @arg @ref I2C_IT_RXI RX interrupt enable
+ * @arg @ref I2C_IT_TXI TX interrupt enable
+ *
+ * @retval None
+ */
+#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
+
+/** @brief Disable the specified I2C interrupt.
+ * @param __HANDLE__ specifies the I2C Handle.
+ * @param __INTERRUPT__ specifies the interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg @ref I2C_IT_ERRI Errors interrupt enable
+ * @arg @ref I2C_IT_TCI Transfer complete interrupt enable
+ * @arg @ref I2C_IT_STOPI STOP detection interrupt enable
+ * @arg @ref I2C_IT_NACKI NACK received interrupt enable
+ * @arg @ref I2C_IT_ADDRI Address match interrupt enable
+ * @arg @ref I2C_IT_RXI RX interrupt enable
+ * @arg @ref I2C_IT_TXI TX interrupt enable
+ *
+ * @retval None
+ */
+#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
+
+/** @brief Check whether the specified I2C interrupt source is enabled or not.
+ * @param __HANDLE__ specifies the I2C Handle.
+ * @param __INTERRUPT__ specifies the I2C interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg @ref I2C_IT_ERRI Errors interrupt enable
+ * @arg @ref I2C_IT_TCI Transfer complete interrupt enable
+ * @arg @ref I2C_IT_STOPI STOP detection interrupt enable
+ * @arg @ref I2C_IT_NACKI NACK received interrupt enable
+ * @arg @ref I2C_IT_ADDRI Address match interrupt enable
+ * @arg @ref I2C_IT_RXI RX interrupt enable
+ * @arg @ref I2C_IT_TXI TX interrupt enable
+ *
+ * @retval The new state of __INTERRUPT__ (SET or RESET).
+ */
+#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Check whether the specified I2C flag is set or not.
+ * @param __HANDLE__ specifies the I2C Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg @ref I2C_FLAG_TXE Transmit data register empty
+ * @arg @ref I2C_FLAG_TXIS Transmit interrupt status
+ * @arg @ref I2C_FLAG_RXNE Receive data register not empty
+ * @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
+ * @arg @ref I2C_FLAG_AF Acknowledge failure received flag
+ * @arg @ref I2C_FLAG_STOPF STOP detection flag
+ * @arg @ref I2C_FLAG_TC Transfer complete (master mode)
+ * @arg @ref I2C_FLAG_TCR Transfer complete reload
+ * @arg @ref I2C_FLAG_BERR Bus error
+ * @arg @ref I2C_FLAG_ARLO Arbitration lost
+ * @arg @ref I2C_FLAG_OVR Overrun/Underrun
+ * @arg @ref I2C_FLAG_PECERR PEC error in reception
+ * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
+ * @arg @ref I2C_FLAG_ALERT SMBus alert
+ * @arg @ref I2C_FLAG_BUSY Bus busy
+ * @arg @ref I2C_FLAG_DIR Transfer direction (slave mode)
+ *
+ * @retval The new state of __FLAG__ (SET or RESET).
+ */
+#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+
+/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
+ * @param __HANDLE__ specifies the I2C Handle.
+ * @param __FLAG__ specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg @ref I2C_FLAG_TXE Transmit data register empty
+ * @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
+ * @arg @ref I2C_FLAG_AF Acknowledge failure received flag
+ * @arg @ref I2C_FLAG_STOPF STOP detection flag
+ * @arg @ref I2C_FLAG_BERR Bus error
+ * @arg @ref I2C_FLAG_ARLO Arbitration lost
+ * @arg @ref I2C_FLAG_OVR Overrun/Underrun
+ * @arg @ref I2C_FLAG_PECERR PEC error in reception
+ * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
+ * @arg @ref I2C_FLAG_ALERT SMBus alert
+ *
+ * @retval None
+ */
+#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \
+ : ((__HANDLE__)->Instance->ICR = (__FLAG__)))
+
+/** @brief Enable the specified I2C peripheral.
+ * @param __HANDLE__ specifies the I2C Handle.
+ * @retval None
+ */
+#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
+
+/** @brief Disable the specified I2C peripheral.
+ * @param __HANDLE__ specifies the I2C Handle.
+ * @retval None
+ */
+#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
+
+/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode.
+ * @param __HANDLE__ specifies the I2C Handle.
+ * @retval None
+ */
+#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
+/**
+ * @}
+ */
+
+/* Include I2C HAL Extended module */
+#include "stm32f3xx_hal_i2c_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2C_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+/* Initialization and de-initialization functions******************************/
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
+ * @{
+ */
+/* IO operation functions ****************************************************/
+/******* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
+
+/******* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
+
+/******* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
+void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
+ * @{
+ */
+/* Peripheral State, Mode and Error functions *********************************/
+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
+HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
+uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2C_Private_Constants I2C Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2C_Private_Macro I2C Private Macros
+ * @{
+ */
+
+#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
+ ((MODE) == I2C_ADDRESSINGMODE_10BIT))
+
+#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
+ ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
+
+#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \
+ ((MASK) == I2C_OA2_MASK01) || \
+ ((MASK) == I2C_OA2_MASK02) || \
+ ((MASK) == I2C_OA2_MASK03) || \
+ ((MASK) == I2C_OA2_MASK04) || \
+ ((MASK) == I2C_OA2_MASK05) || \
+ ((MASK) == I2C_OA2_MASK06) || \
+ ((MASK) == I2C_OA2_MASK07))
+
+#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
+ ((CALL) == I2C_GENERALCALL_ENABLE))
+
+#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
+ ((STRETCH) == I2C_NOSTRETCH_ENABLE))
+
+#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
+ ((SIZE) == I2C_MEMADD_SIZE_16BIT))
+
+#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \
+ ((MODE) == I2C_AUTOEND_MODE) || \
+ ((MODE) == I2C_SOFTEND_MODE))
+
+#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \
+ ((REQUEST) == I2C_GENERATE_START_READ) || \
+ ((REQUEST) == I2C_GENERATE_START_WRITE) || \
+ ((REQUEST) == I2C_NO_STARTSTOP))
+
+#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
+ ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
+ ((REQUEST) == I2C_NEXT_FRAME) || \
+ ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
+ ((REQUEST) == I2C_LAST_FRAME) || \
+ ((REQUEST) == I2C_LAST_FRAME_NO_STOP))
+
+#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
+
+#define I2C_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U)
+#define I2C_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
+#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
+#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)
+#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)
+
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
+#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
+
+#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
+#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
+
+#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
+ (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
+/**
+ * @}
+ */
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup I2C_Private_Functions I2C Private Functions
+ * @{
+ */
+/* Private functions are defined in stm32f3xx_hal_i2c.c file */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F3xx_HAL_I2C_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_hal_i2c_ex.h b/Inc/stm32f3xx_hal_i2c_ex.h
new file mode 100644
index 0000000..5be5fd6
--- /dev/null
+++ b/Inc/stm32f3xx_hal_i2c_ex.h
@@ -0,0 +1,179 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_i2c_ex.h
+ * @author MCD Application Team
+ * @brief Header file of I2C HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_I2C_EX_H
+#define __STM32F3xx_HAL_I2C_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup I2CEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
+ * @{
+ */
+
+/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
+ * @{
+ */
+#define I2C_ANALOGFILTER_ENABLE 0x00000000U
+#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
+/**
+ * @}
+ */
+
+/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
+ * @{
+ */
+#define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */
+#define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
+#define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
+#define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
+#define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
+#define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
+#if defined(SYSCFG_CFGR1_I2C2_FMP)
+#define I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
+#else
+#define I2C_FASTMODEPLUS_I2C2 (uint32_t)(0x00000200U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C2 not supported */
+#endif
+#if defined(SYSCFG_CFGR1_I2C3_FMP)
+#define I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
+#else
+#define I2C_FASTMODEPLUS_I2C3 (uint32_t)(0x00000400U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C3 not supported */
+#endif
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
+ * @{
+ */
+
+/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions
+ * @brief Extended features functions
+ * @{
+ */
+
+/* Peripheral Control functions ************************************************/
+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
+HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
+void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
+void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
+ * @{
+ */
+#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
+ ((FILTER) == I2C_ANALOGFILTER_DISABLE))
+
+#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
+
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) && \
+ ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \
+ (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \
+ (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \
+ (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \
+ (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \
+ (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2) || \
+ (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3)))
+/**
+ * @}
+ */
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
+ * @{
+ */
+/* Private functions are defined in stm32f3xx_hal_i2c_ex.c file */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_I2C_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_hal_i2s.h b/Inc/stm32f3xx_hal_i2s.h
new file mode 100644
index 0000000..3360ecf
--- /dev/null
+++ b/Inc/stm32f3xx_hal_i2s.h
@@ -0,0 +1,486 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_i2s.h
+ * @author MCD Application Team
+ * @brief Header file of I2S HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_I2S_H
+#define __STM32F3xx_HAL_I2S_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup I2S
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup I2S_Exported_Types I2S Exported Types
+ * @{
+ */
+
+/**
+ * @brief I2S Init structure definition
+ */
+typedef struct
+{
+ uint32_t Mode; /*!< Specifies the I2S operating mode.
+ This parameter can be a value of @ref I2S_Mode */
+
+ uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
+ This parameter can be a value of @ref I2S_Standard */
+
+ uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
+ This parameter can be a value of @ref I2S_Data_Format */
+
+ uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
+ This parameter can be a value of @ref I2S_MCLK_Output */
+
+ uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
+ This parameter can be a value of @ref I2S_Audio_Frequency */
+
+ uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
+ This parameter can be a value of @ref I2S_Clock_Polarity */
+
+ uint32_t ClockSource; /*!< Specifies the I2S Clock Source.
+ This parameter can be a value of @ref I2S_Clock_Source */
+
+ uint32_t FullDuplexMode; /*!< Specifies the I2S FullDuplex mode.
+ This parameter can be a value of @ref I2S_FullDuplex_Mode */
+
+}I2S_InitTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */
+ HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */
+ HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */
+ HAL_I2S_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
+ HAL_I2S_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
+ HAL_I2S_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
+ HAL_I2S_STATE_TIMEOUT = 0x06U, /*!< I2S timeout state */
+ HAL_I2S_STATE_ERROR = 0x07 /*!< I2S error state */
+}HAL_I2S_StateTypeDef;
+
+/**
+ * @brief I2S handle Structure definition
+ */
+typedef struct
+{
+ SPI_TypeDef *Instance; /*!< I2S registers base address */
+
+ I2S_InitTypeDef Init; /*!< I2S communication parameters */
+
+ uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */
+
+ __IO uint16_t TxXferSize; /*!< I2S Tx transfer size */
+
+ __IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */
+
+ uint16_t *pRxBuffPtr; /*!< Pointer to I2S Rx transfer buffer */
+
+ __IO uint16_t RxXferSize; /*!< I2S Rx transfer size */
+
+ __IO uint16_t RxXferCount; /*!< I2S Rx transfer counter
+ (This field is initialized at the
+ same value as transfer size at the
+ beginning of the transfer and
+ decremented when a sample is received.
+ NbSamplesReceived = RxBufferSize-RxBufferCount) */
+
+ DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */
+
+ __IO HAL_LockTypeDef Lock; /*!< I2S locking object */
+
+ __IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */
+
+ __IO uint32_t ErrorCode; /*!< I2S Error code
+ This parameter can be a value of @ref I2S_Error */
+
+}I2S_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup I2S_Exported_Constants I2S Exported Constants
+ * @{
+ */
+/** @defgroup I2S_Error I2S Error
+ * @{
+ */
+#define HAL_I2S_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_I2S_ERROR_TIMEOUT (0x00000001U) /*!< Timeout error */
+#define HAL_I2S_ERROR_OVR (0x00000002U) /*!< OVR error */
+#define HAL_I2S_ERROR_UDR (0x00000004U) /*!< UDR error */
+#define HAL_I2S_ERROR_DMA (0x00000008U) /*!< DMA transfer error */
+#define HAL_I2S_ERROR_UNKNOW (0x00000010U) /*!< Unknow Error error */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Clock_Source I2S Clock Source
+ * @{
+ */
+#define I2S_CLOCK_EXTERNAL (0x00000001U)
+#define I2S_CLOCK_SYSCLK (0x00000002U)
+
+#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) || \
+ ((CLOCK) == I2S_CLOCK_SYSCLK))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Mode I2S Mode
+ * @{
+ */
+#define I2S_MODE_SLAVE_TX (0x00000000U)
+#define I2S_MODE_SLAVE_RX (0x00000100U)
+#define I2S_MODE_MASTER_TX (0x00000200U)
+#define I2S_MODE_MASTER_RX (0x00000300U)
+
+#define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
+ ((MODE) == I2S_MODE_SLAVE_RX) || \
+ ((MODE) == I2S_MODE_MASTER_TX)|| \
+ ((MODE) == I2S_MODE_MASTER_RX))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Standard I2S Standard
+ * @{
+ */
+#define I2S_STANDARD_PHILIPS (0x00000000U)
+#define I2S_STANDARD_MSB (0x00000010U)
+#define I2S_STANDARD_LSB (0x00000020U)
+#define I2S_STANDARD_PCM_SHORT (0x00000030U)
+#define I2S_STANDARD_PCM_LONG (0x000000B0U)
+
+#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \
+ ((STANDARD) == I2S_STANDARD_MSB) || \
+ ((STANDARD) == I2S_STANDARD_LSB) || \
+ ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
+ ((STANDARD) == I2S_STANDARD_PCM_LONG))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Data_Format I2S Data Format
+ * @{
+ */
+#define I2S_DATAFORMAT_16B (0x00000000U)
+#define I2S_DATAFORMAT_16B_EXTENDED (0x00000001U)
+#define I2S_DATAFORMAT_24B (0x00000003U)
+#define I2S_DATAFORMAT_32B (0x00000005U)
+
+#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \
+ ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
+ ((FORMAT) == I2S_DATAFORMAT_24B) || \
+ ((FORMAT) == I2S_DATAFORMAT_32B))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_MCLK_Output I2S MCLK Output
+ * @{
+ */
+#define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE)
+#define I2S_MCLKOUTPUT_DISABLE (0x00000000U)
+
+#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
+ ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Audio_Frequency I2S Audio Frequency
+ * @{
+ */
+#define I2S_AUDIOFREQ_192K (192000U)
+#define I2S_AUDIOFREQ_96K (96000U)
+#define I2S_AUDIOFREQ_48K (48000U)
+#define I2S_AUDIOFREQ_44K (44100U)
+#define I2S_AUDIOFREQ_32K (32000U)
+#define I2S_AUDIOFREQ_22K (22050U)
+#define I2S_AUDIOFREQ_16K (16000U)
+#define I2S_AUDIOFREQ_11K (11025U)
+#define I2S_AUDIOFREQ_8K (8000U)
+#define I2S_AUDIOFREQ_DEFAULT (2U)
+
+#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
+ ((FREQ) <= I2S_AUDIOFREQ_192K)) || \
+ ((FREQ) == I2S_AUDIOFREQ_DEFAULT))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_FullDuplex_Mode I2S Full Duplex Mode
+ * @{
+ */
+#define I2S_FULLDUPLEXMODE_DISABLE (0x00000000U)
+#define I2S_FULLDUPLEXMODE_ENABLE (0x00000001U)
+
+#define IS_I2S_FULLDUPLEX_MODE(MODE) (((MODE) == I2S_FULLDUPLEXMODE_DISABLE) || \
+ ((MODE) == I2S_FULLDUPLEXMODE_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
+ * @{
+ */
+#define I2S_CPOL_LOW (0x00000000U)
+#define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL)
+
+#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
+ ((CPOL) == I2S_CPOL_HIGH))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Interrupt_configuration_definition I2S Interrupt configuration definition
+ * @{
+ */
+#define I2S_IT_TXE SPI_CR2_TXEIE
+#define I2S_IT_RXNE SPI_CR2_RXNEIE
+#define I2S_IT_ERR SPI_CR2_ERRIE
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Flag_definition I2S Flag definition
+ * @{
+ */
+#define I2S_FLAG_TXE SPI_SR_TXE
+#define I2S_FLAG_RXNE SPI_SR_RXNE
+
+#define I2S_FLAG_UDR SPI_SR_UDR
+#define I2S_FLAG_OVR SPI_SR_OVR
+#define I2S_FLAG_FRE SPI_SR_FRE
+
+#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
+#define I2S_FLAG_BSY SPI_SR_BSY
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup I2S_Exported_Macros I2S Exported Macros
+ * @{
+ */
+
+/** @brief Reset I2S handle state
+ * @param __HANDLE__ I2S handle.
+ * @retval None
+ */
+#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
+
+/** @brief Enable or disable the specified SPI peripheral (in I2S mode).
+ * @param __HANDLE__ specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE)
+#define __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &= (uint16_t)(~SPI_I2SCFGR_I2SE))
+
+/** @brief Enable or disable the specified I2S interrupts.
+ * @param __HANDLE__ specifies the I2S Handle.
+ * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
+ * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg I2S_IT_ERR: Error interrupt enable
+ * @retval None
+ */
+#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
+#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (uint16_t)(~(__INTERRUPT__)))
+
+/** @brief Checks if the specified I2S interrupt source is enabled or disabled.
+ * @param __HANDLE__ specifies the I2S Handle.
+ * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
+ * @param __INTERRUPT__ specifies the I2S interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
+ * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg I2S_IT_ERR: Error interrupt enable
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Checks whether the specified I2S flag is set or not.
+ * @param __HANDLE__ specifies the I2S Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg I2S_FLAG_RXNE: Receive buffer not empty flag
+ * @arg I2S_FLAG_TXE: Transmit buffer empty flag
+ * @arg I2S_FLAG_UDR: Underrun flag
+ * @arg I2S_FLAG_OVR: Overrun flag
+ * @arg I2S_FLAG_FRE: Frame error flag
+ * @arg I2S_FLAG_CHSIDE: Channel Side flag
+ * @arg I2S_FLAG_BSY: Busy flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clears the I2S OVR pending flag.
+ * @param __HANDLE__ specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ \
+ __IO uint32_t tmpreg; \
+ tmpreg = (__HANDLE__)->Instance->DR; \
+ tmpreg = (__HANDLE__)->Instance->SR; \
+ UNUSED(tmpreg); \
+ }while(0U)
+/** @brief Clears the I2S UDR pending flag.
+ * @param __HANDLE__ specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{\
+ __IO uint32_t tmpreg;\
+ tmpreg = ((__HANDLE__)->Instance->SR);\
+ UNUSED(tmpreg); \
+ }while(0U)
+/**
+ * @}
+ */
+
+/* Include I2S HAL Extended module */
+#include "stm32f3xx_hal_i2s_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2S_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup I2S_Exported_Functions_Group1
+ * @{
+ */
+
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
+HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);
+void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
+/**
+ * @}
+ */
+
+/** @addtogroup I2S_Exported_Functions_Group2
+ * @{
+ */
+/* I/O operation functions ***************************************************/
+ /* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
+
+ /* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
+void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
+
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
+HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
+HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
+
+/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
+void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
+/**
+ * @}
+ */
+
+/** @addtogroup I2S_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral Control and State functions ************************************/
+HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
+uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
+ /* STM32F373xC || STM32F378xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F3xx_HAL_I2S_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_hal_i2s_ex.h b/Inc/stm32f3xx_hal_i2s_ex.h
new file mode 100644
index 0000000..99f102f
--- /dev/null
+++ b/Inc/stm32f3xx_hal_i2s_ex.h
@@ -0,0 +1,219 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_i2s_ex.h
+ * @author MCD Application Team
+ * @brief Header file of I2S HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_I2S_EX_H
+#define __STM32F3xx_HAL_I2S_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup I2SEx I2SEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros ------------------------------------------------------------*/
+/** @defgroup I2SEx_Exported_Macros I2S Extended Exported Macros
+ * @{
+ */
+#if defined(SPI_I2S_FULLDUPLEX_SUPPORT)
+#define I2SxEXT(__INSTANCE__) ((__INSTANCE__) == (SPI2)? (SPI_TypeDef *)(I2S2ext_BASE): (SPI_TypeDef *)(I2S3ext_BASE))
+
+/** @brief Enable or disable the specified I2SExt peripheral.
+ * @param __HANDLE__ specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2SEXT_ENABLE(__HANDLE__) (I2SxEXT((__HANDLE__)->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE)
+#define __HAL_I2SEXT_DISABLE(__HANDLE__) (I2SxEXT((__HANDLE__)->Instance)->I2SCFGR &= ~SPI_I2SCFGR_I2SE)
+
+/** @brief Enable or disable the specified I2SExt interrupts.
+ * @param __HANDLE__ specifies the I2S Handle.
+ * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
+ * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg I2S_IT_ERR: Error interrupt enable
+ * @retval None
+ */
+#define __HAL_I2SEXT_ENABLE_IT(__HANDLE__, __INTERRUPT__) (I2SxEXT((__HANDLE__)->Instance)->CR2 |= (__INTERRUPT__))
+#define __HAL_I2SEXT_DISABLE_IT(__HANDLE__, __INTERRUPT__) (I2SxEXT((__HANDLE__)->Instance)->CR2 &= ~(__INTERRUPT__))
+
+/** @brief Checks if the specified I2SExt interrupt source is enabled or disabled.
+ * @param __HANDLE__ specifies the I2S Handle.
+ * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
+ * @param __INTERRUPT__ specifies the I2S interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
+ * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg I2S_IT_ERR: Error interrupt enable
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_I2SEXT_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((I2SxEXT((__HANDLE__)->Instance)->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Checks whether the specified I2SExt flag is set or not.
+ * @param __HANDLE__ specifies the I2S Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg I2S_FLAG_RXNE: Receive buffer not empty flag
+ * @arg I2S_FLAG_TXE: Transmit buffer empty flag
+ * @arg I2S_FLAG_UDR: Underrun flag
+ * @arg I2S_FLAG_OVR: Overrun flag
+ * @arg I2S_FLAG_FRE: Frame error flag
+ * @arg I2S_FLAG_CHSIDE: Channel Side flag
+ * @arg I2S_FLAG_BSY: Busy flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_I2SEXT_GET_FLAG(__HANDLE__, __FLAG__) (((I2SxEXT((__HANDLE__)->Instance)->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clears the I2SExt OVR pending flag.
+ * @param __HANDLE__ specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2SEXT_CLEAR_OVRFLAG(__HANDLE__) do{(I2SxEXT((__HANDLE__)->Instance)->DR;\
+ (I2SxEXT((__HANDLE__)->Instance)->SR;}while(0U)
+/** @brief Clears the I2SExt UDR pending flag.
+ * @param __HANDLE__ specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2SEXT_CLEAR_UDRFLAG(__HANDLE__)(I2SxEXT((__HANDLE__)->Instance)->SR)
+#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
+ /**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/* Initialization/de-initialization functions ********************************/
+/** @addtogroup I2SEx_Exported_Functions I2S Extended Exported Functions
+ * @{
+ */
+
+#if defined(SPI_I2S_FULLDUPLEX_SUPPORT)
+/** @addtogroup I2SEx_Exported_Functions_Group1 I2S Extended Features Functions
+ * @{
+ */
+
+/* Extended features functions ************************************************/
+ /* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size, uint32_t Timeout);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size);
+/**
+ * @}
+ */
+#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2S I2S
+ * @{
+ */
+
+/** @addtogroup I2S_Exported_Functions I2S Exported Functions
+ * @{
+ */
+#if defined(SPI_I2S_FULLDUPLEX_SUPPORT)
+/** @addtogroup I2S_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+/* I2S IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
+void HAL_I2S_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_TxRxCpltCallback(I2S_HandleTypeDef *hi2s);
+/* Callback used in non blocking modes (DMA only) */
+void HAL_I2S_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
+/**
+ * @}
+ */
+#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
+
+/** @addtogroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @{
+ */
+/* Peripheral Control and State functions ************************************/
+HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
+HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
+HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
+ /* STM32F373xC || STM32F378xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F3xx_HAL_I2S_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_hal_irda.h b/Inc/stm32f3xx_hal_irda.h
new file mode 100644
index 0000000..8594766
--- /dev/null
+++ b/Inc/stm32f3xx_hal_irda.h
@@ -0,0 +1,788 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_irda.h
+ * @author MCD Application Team
+ * @brief This file contains all the functions prototypes for the IRDA
+ * firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_IRDA_H
+#define __STM32F3xx_HAL_IRDA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup IRDA
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup IRDA_Exported_Types IRDA Exported Types
+ * @{
+ */
+
+/**
+ * @brief IRDA Init Structure definition
+ */
+typedef struct
+{
+ uint32_t BaudRate; /*!< This member configures the IRDA communication baud rate.
+ The baud rate register is computed using the following formula:
+ Baud Rate Register = ((PCLKx) / ((hirda->Init.BaudRate))) */
+
+ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter can be a value of @ref IRDAEx_Word_Length */
+
+ uint32_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref IRDA_Parity
+ @note When parity is enabled, the computed parity is inserted
+ at the MSB position of the transmitted data (9th bit when
+ the word length is set to 9 data bits; 8th bit when the
+ word length is set to 8 data bits). */
+
+ uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref IRDA_Transfer_Mode */
+
+ uint8_t Prescaler; /*!< Specifies the Prescaler value for dividing the UART/USART source clock
+ to achieve low-power frequency.
+ @note Prescaler value 0 is forbidden */
+
+ uint16_t PowerMode; /*!< Specifies the IRDA power mode.
+ This parameter can be a value of @ref IRDA_Low_Power */
+}IRDA_InitTypeDef;
+
+/**
+ * @brief HAL IRDA State structures definition
+ * @note HAL IRDA State value is a combination of 2 different substates: gState and RxState.
+ * - gState contains IRDA state information related to global Handle management
+ * and also information related to Tx operations.
+ * gState value coding follow below described bitmap :
+ * b7-b6 Error information
+ * 00 : No Error
+ * 01 : (Not Used)
+ * 10 : Timeout
+ * 11 : Error
+ * b5 IP initilisation status
+ * 0 : Reset (IP not initialized)
+ * 1 : Init done (IP not initialized. HAL IRDA Init function already called)
+ * b4-b3 (not used)
+ * xx : Should be set to 00
+ * b2 Intrinsic process state
+ * 0 : Ready
+ * 1 : Busy (IP busy with some configuration or internal operations)
+ * b1 (not used)
+ * x : Should be set to 0
+ * b0 Tx state
+ * 0 : Ready (no Tx operation ongoing)
+ * 1 : Busy (Tx operation ongoing)
+ * - RxState contains information related to Rx operations.
+ * RxState value coding follow below described bitmap :
+ * b7-b6 (not used)
+ * xx : Should be set to 00
+ * b5 IP initilisation status
+ * 0 : Reset (IP not initialized)
+ * 1 : Init done (IP not initialized)
+ * b4-b2 (not used)
+ * xxx : Should be set to 000
+ * b1 Rx state
+ * 0 : Ready (no Rx operation ongoing)
+ * 1 : Busy (Rx operation ongoing)
+ * b0 (not used)
+ * x : Should be set to 0.
+ */
+typedef enum
+{
+ HAL_IRDA_STATE_RESET = 0x00U, /*!< Peripheral is not initialized
+ Value is allowed for gState and RxState */
+ HAL_IRDA_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
+ Value is allowed for gState and RxState */
+ HAL_IRDA_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
+ Value is allowed for gState only */
+ HAL_IRDA_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
+ Value is allowed for gState only */
+ HAL_IRDA_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
+ Value is allowed for RxState only */
+ HAL_IRDA_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
+ Not to be used for neither gState nor RxState.
+ Value is result of combination (Or) between gState and RxState values */
+ HAL_IRDA_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
+ Value is allowed for gState only */
+ HAL_IRDA_STATE_ERROR = 0xE0U /*!< Error
+ Value is allowed for gState only */
+}HAL_IRDA_StateTypeDef;
+
+/**
+ * @brief IRDA clock sources definition
+ */
+typedef enum
+{
+ IRDA_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
+ IRDA_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */
+ IRDA_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
+ IRDA_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
+ IRDA_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */
+ IRDA_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */
+}IRDA_ClockSourceTypeDef;
+
+/**
+ * @brief IRDA handle Structure definition
+ */
+typedef struct
+{
+ USART_TypeDef *Instance; /*!< IRDA registers base address */
+
+ IRDA_InitTypeDef Init; /*!< IRDA communication parameters */
+
+ uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */
+
+ uint16_t TxXferSize; /*!< IRDA Tx Transfer size */
+
+ __IO uint16_t TxXferCount; /*!< IRDA Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /*!< Pointer to IRDA Rx transfer Buffer */
+
+ uint16_t RxXferSize; /*!< IRDA Rx Transfer size */
+
+ __IO uint16_t RxXferCount; /*!< IRDA Rx Transfer Counter */
+
+ uint16_t Mask; /*!< IRDA RX RDR register mask */
+
+ DMA_HandleTypeDef *hdmatx; /*!< IRDA Tx DMA Handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< IRDA Rx DMA Handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< Locking object */
+
+ __IO HAL_IRDA_StateTypeDef gState; /*!< IRDA state information related to global Handle management
+ and also related to Tx operations.
+ This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
+
+ __IO HAL_IRDA_StateTypeDef RxState; /*!< IRDA state information related to Rx operations.
+ This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
+
+ __IO uint32_t ErrorCode; /*!< IRDA Error code
+ This parameter can be a value of @ref IRDA_Error */
+
+}IRDA_HandleTypeDef;
+
+/**
+ * @brief IRDA Configuration enumeration values definition
+ */
+typedef enum
+{
+ IRDA_BAUDRATE = 0x00U, /*!< IRDA Baud rate */
+ IRDA_PARITY = 0x01U, /*!< IRDA frame parity */
+ IRDA_WORDLENGTH = 0x02U, /*!< IRDA frame length */
+ IRDA_MODE = 0x03U, /*!< IRDA communication mode */
+ IRDA_PRESCALER = 0x04U, /*!< IRDA prescaling */
+ IRDA_POWERMODE = 0x05U /*!< IRDA power mode */
+}IRDA_ControlTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup IRDA_Exported_Constants IRDA Exported Constants
+ * @{
+ */
+
+/** @defgroup IRDA_Error IRDA Error
+ * @{
+ */
+#define HAL_IRDA_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_IRDA_ERROR_PE (0x00000001U) /*!< Parity error */
+#define HAL_IRDA_ERROR_NE (0x00000002U) /*!< Noise error */
+#define HAL_IRDA_ERROR_FE (0x00000004U) /*!< frame error */
+#define HAL_IRDA_ERROR_ORE (0x00000008U) /*!< Overrun error */
+#define HAL_IRDA_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
+#define HAL_IRDA_ERROR_BUSY (0x00000020U) /*!< Busy Error */
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Parity IRDA Parity
+ * @{
+ */
+#define IRDA_PARITY_NONE (0x00000000U) /*!< No parity */
+#define IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /*!< Even parity */
+#define IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< Odd parity */
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode
+ * @{
+ */
+#define IRDA_MODE_RX ((uint32_t)USART_CR1_RE) /*!< RX mode */
+#define IRDA_MODE_TX ((uint32_t)USART_CR1_TE) /*!< TX mode */
+#define IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) /*!< RX and TX mode */
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Low_Power IRDA Low Power
+ * @{
+ */
+#define IRDA_POWERMODE_NORMAL (0x00000000U) /*!< IRDA normal power mode */
+#define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP) /*!< IRDA low power mode */
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_State IRDA State
+ * @{
+ */
+#define IRDA_STATE_DISABLE (0x00000000U) /*!< IRDA disabled */
+#define IRDA_STATE_ENABLE ((uint32_t)USART_CR1_UE) /*!< IRDA enabled */
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Mode IRDA Mode
+ * @{
+ */
+#define IRDA_MODE_DISABLE (0x00000000U) /*!< Associated UART disabled in IRDA mode */
+#define IRDA_MODE_ENABLE ((uint32_t)USART_CR3_IREN) /*!< Associated UART enabled in IRDA mode */
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_One_Bit IRDA One Bit Sampling
+ * @{
+ */
+#define IRDA_ONE_BIT_SAMPLE_DISABLE (0x00000000U) /*!< One-bit sampling disabled */
+#define IRDA_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) /*!< One-bit sampling enabled */
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_DMA_Tx IRDA DMA Tx
+ * @{
+ */
+#define IRDA_DMA_TX_DISABLE (0x00000000U) /*!< IRDA DMA TX disabled */
+#define IRDA_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT) /*!< IRDA DMA TX enabled */
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_DMA_Rx IRDA DMA Rx
+ * @{
+ */
+#define IRDA_DMA_RX_DISABLE (0x00000000U) /*!< IRDA DMA RX disabled */
+#define IRDA_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR) /*!< IRDA DMA RX enabled */
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Request_Parameters IRDA Request Parameters
+ * @{
+ */
+#define IRDA_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ) /*!< Auto-Baud Rate Request */
+#define IRDA_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */
+#define IRDA_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Flags IRDA Flags
+ * Elements values convention: 0xXXXX
+ * - 0xXXXX : Flag mask in the ISR register
+ * @{
+ */
+#define IRDA_FLAG_REACK (0x00400000U) /*!< IRDA Receive enable acknowledge flag */
+#define IRDA_FLAG_TEACK (0x00200000U) /*!< IRDA Transmit enable acknowledge flag */
+#define IRDA_FLAG_BUSY (0x00010000U) /*!< IRDA Busy flag */
+#define IRDA_FLAG_ABRF (0x00008000U) /*!< IRDA Auto baud rate flag */
+#define IRDA_FLAG_ABRE (0x00004000U) /*!< IRDA Auto baud rate error */
+#define IRDA_FLAG_TXE (0x00000080U) /*!< IRDA Transmit data register empty */
+#define IRDA_FLAG_TC (0x00000040U) /*!< IRDA Transmission complete */
+#define IRDA_FLAG_RXNE (0x00000020U) /*!< IRDA Read data register not empty */
+#define IRDA_FLAG_ORE (0x00000008U) /*!< IRDA Overrun error */
+#define IRDA_FLAG_NE (0x00000004U) /*!< IRDA Noise error */
+#define IRDA_FLAG_FE (0x00000002U) /*!< IRDA Framing error */
+#define IRDA_FLAG_PE (0x00000001U) /*!< IRDA Parity error */
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Interrupt_definition IRDA Interrupts Definition
+ * Elements values convention: 0000ZZZZ0XXYYYYYb
+ * - YYYYY : Interrupt source position in the XX register (5bits)
+ * - XX : Interrupt source register (2bits)
+ * - 01: CR1 register
+ * - 10: CR2 register
+ * - 11: CR3 register
+ * - ZZZZ : Flag position in the ISR register(4bits)
+ * @{
+ */
+#define IRDA_IT_PE ((uint16_t)0x0028U) /*!< IRDA Parity error interruption */
+#define IRDA_IT_TXE ((uint16_t)0x0727U) /*!< IRDA Transmit data register empty interruption */
+#define IRDA_IT_TC ((uint16_t)0x0626U) /*!< IRDA Transmission complete interruption */
+#define IRDA_IT_RXNE ((uint16_t)0x0525U) /*!< IRDA Read data register not empty interruption */
+#define IRDA_IT_IDLE ((uint16_t)0x0424U) /*!< IRDA Idle interruption */
+#define IRDA_IT_ERR ((uint16_t)0x0060U) /*!< IRDA Error interruption */
+#define IRDA_IT_ORE ((uint16_t)0x0300U) /*!< IRDA Overrun error interruption */
+#define IRDA_IT_NE ((uint16_t)0x0200U) /*!< IRDA Noise error interruption */
+#define IRDA_IT_FE ((uint16_t)0x0100U) /*!< IRDA Frame error interruption */
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_IT_CLEAR_Flags IRDA Interruption Clear Flags
+ * @{
+ */
+#define IRDA_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
+#define IRDA_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
+#define IRDA_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */
+#define IRDA_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
+#define IRDA_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
+#define IRDA_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Interruption_Mask IRDA interruptions flags mask
+ * @{
+ */
+#define IRDA_IT_MASK ((uint16_t)0x001FU) /*!< IRDA Interruptions flags mask */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup IRDA_Exported_Macros IRDA Exported Macros
+ * @{
+ */
+
+/** @brief Reset IRDA handle state.
+ * @param __HANDLE__ IRDA handle.
+ * @retval None
+ */
+#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \
+ (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \
+ } while(0U)
+
+/** @brief Flush the IRDA DR register.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * @retval None
+ */
+#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) \
+ do{ \
+ SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
+ SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
+ } while(0U)
+
+/** @brief Clear the specified IRDA pending flag.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg @ref IRDA_CLEAR_PEF
+ * @arg @ref IRDA_CLEAR_FEF
+ * @arg @ref IRDA_CLEAR_NEF
+ * @arg @ref IRDA_CLEAR_OREF
+ * @arg @ref IRDA_CLEAR_TCF
+ * @arg @ref IRDA_CLEAR_IDLEF
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/** @brief Clear the IRDA PE pending flag.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)
+
+
+/** @brief Clear the IRDA FE pending flag.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)
+
+/** @brief Clear the IRDA NE pending flag.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)
+
+/** @brief Clear the IRDA ORE pending flag.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)
+
+/** @brief Clear the IRDA IDLE pending flag.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)
+
+/** @brief Check whether the specified IRDA flag is set or not.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg @ref IRDA_FLAG_REACK Receive enable acknowledge flag
+ * @arg @ref IRDA_FLAG_TEACK Transmit enable acknowledge flag
+ * @arg @ref IRDA_FLAG_BUSY Busy flag
+ * @arg @ref IRDA_FLAG_ABRF Auto Baud rate detection flag
+ * @arg @ref IRDA_FLAG_ABRE Auto Baud rate detection error flag
+ * @arg @ref IRDA_FLAG_TXE Transmit data register empty flag
+ * @arg @ref IRDA_FLAG_TC Transmission Complete flag
+ * @arg @ref IRDA_FLAG_RXNE Receive data register not empty flag
+ * @arg @ref IRDA_FLAG_ORE OverRun Error flag
+ * @arg @ref IRDA_FLAG_NE Noise Error flag
+ * @arg @ref IRDA_FLAG_FE Framing Error flag
+ * @arg @ref IRDA_FLAG_PE Parity Error flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
+
+
+/** @brief Enable the specified IRDA interrupt.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * @param __INTERRUPT__ specifies the IRDA interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref IRDA_IT_TC Transmission complete interrupt
+ * @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref IRDA_IT_IDLE Idle line detection interrupt
+ * @arg @ref IRDA_IT_PE Parity Error interrupt
+ * @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
+ * @retval None
+ */
+#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
+ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
+
+/** @brief Disable the specified IRDA interrupt.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * @param __INTERRUPT__ specifies the IRDA interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref IRDA_IT_TC Transmission complete interrupt
+ * @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref IRDA_IT_IDLE Idle line detection interrupt
+ * @arg @ref IRDA_IT_PE Parity Error interrupt
+ * @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
+ * @retval None
+ */
+#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
+ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
+
+
+/** @brief Check whether the specified IRDA interrupt has occurred or not.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * @param __IT__ specifies the IRDA interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref IRDA_IT_TC Transmission complete interrupt
+ * @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref IRDA_IT_IDLE Idle line detection interrupt
+ * @arg @ref IRDA_IT_ORE OverRun Error interrupt
+ * @arg @ref IRDA_IT_NE Noise Error interrupt
+ * @arg @ref IRDA_IT_FE Framing Error interrupt
+ * @arg @ref IRDA_IT_PE Parity Error interrupt
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U)))
+
+/** @brief Check whether the specified IRDA interrupt source is enabled or not.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * @param __IT__ specifies the IRDA interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref IRDA_IT_TC Transmission complete interrupt
+ * @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref IRDA_IT_IDLE Idle line detection interrupt
+ * @arg @ref IRDA_IT_ERR Framing, overrun or noise error interrupt
+ * @arg @ref IRDA_IT_PE Parity Error interrupt
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2U)? \
+ (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__IT__)) & IRDA_IT_MASK)))
+
+
+/** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
+ * to clear the corresponding interrupt
+ * This parameter can be one of the following values:
+ * @arg @ref IRDA_CLEAR_PEF Parity Error Clear Flag
+ * @arg @ref IRDA_CLEAR_FEF Framing Error Clear Flag
+ * @arg @ref IRDA_CLEAR_NEF Noise detected Clear Flag
+ * @arg @ref IRDA_CLEAR_OREF OverRun Error Clear Flag
+ * @arg @ref IRDA_CLEAR_TCF Transmission Complete Clear Flag
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
+
+
+/** @brief Set a specific IRDA request flag.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * @param __REQ__ specifies the request flag to set
+ * This parameter can be one of the following values:
+ * @arg @ref IRDA_AUTOBAUD_REQUEST Auto-Baud Rate Request
+ * @arg @ref IRDA_RXDATA_FLUSH_REQUEST Receive Data flush Request
+ * @arg @ref IRDA_TXDATA_FLUSH_REQUEST Transmit data flush Request
+ *
+ * @retval None
+ */
+#define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
+
+/** @brief Enable the IRDA one bit sample method.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * @retval None
+ */
+#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+
+/** @brief Disable the IRDA one bit sample method.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * @retval None
+ */
+#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
+
+/** @brief Enable UART/USART associated to IRDA Handle.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * @retval None
+ */
+#define __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+
+/** @brief Disable UART/USART associated to IRDA Handle.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * @retval None
+ */
+#define __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+
+/**
+ * @}
+ */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup IRDA_Private_Macros IRDA Private Macros
+ * @{
+ */
+
+/** @brief Ensure that IRDA Baud rate is less or equal to maximum value.
+ * @param __BAUDRATE__ specifies the IRDA Baudrate set by the user.
+ * @retval True or False
+ */
+#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201U)
+
+/** @brief Ensure that IRDA prescaler value is strictly larger than 0.
+ * @param __PRESCALER__ specifies the IRDA prescaler value set by the user.
+ * @retval True or False
+ */
+#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0U)
+
+/**
+ * @brief Ensure that IRDA frame parity is valid.
+ * @param __PARITY__ IRDA frame parity.
+ * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
+ */
+#define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \
+ ((__PARITY__) == IRDA_PARITY_EVEN) || \
+ ((__PARITY__) == IRDA_PARITY_ODD))
+
+/**
+ * @brief Ensure that IRDA communication mode is valid.
+ * @param __MODE__ IRDA communication mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
+
+/**
+ * @brief Ensure that IRDA power mode is valid.
+ * @param __MODE__ IRDA power mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \
+ ((__MODE__) == IRDA_POWERMODE_NORMAL))
+
+/**
+ * @brief Ensure that IRDA state is valid.
+ * @param __STATE__ IRDA state mode.
+ * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
+ */
+#define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \
+ ((__STATE__) == IRDA_STATE_ENABLE))
+
+/**
+ * @brief Ensure that IRDA associated UART/USART mode is valid.
+ * @param __MODE__ IRDA associated UART/USART mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_IRDA_MODE(__MODE__) (((__MODE__) == IRDA_MODE_DISABLE) || \
+ ((__MODE__) == IRDA_MODE_ENABLE))
+
+/**
+ * @brief Ensure that IRDA sampling rate is valid.
+ * @param __ONEBIT__ IRDA sampling rate.
+ * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
+ */
+#define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \
+ ((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE))
+
+/**
+ * @brief Ensure that IRDA DMA TX mode is valid.
+ * @param __DMATX__ IRDA DMA TX mode.
+ * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
+ */
+#define IS_IRDA_DMA_TX(__DMATX__) (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \
+ ((__DMATX__) == IRDA_DMA_TX_ENABLE))
+
+/**
+ * @brief Ensure that IRDA DMA RX mode is valid.
+ * @param __DMARX__ IRDA DMA RX mode.
+ * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
+ */
+#define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \
+ ((__DMARX__) == IRDA_DMA_RX_ENABLE))
+
+/**
+ * @brief Ensure that IRDA request is valid.
+ * @param __PARAM__ IRDA request.
+ * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
+ */
+#define IS_IRDA_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \
+ ((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \
+ ((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST))
+/**
+ * @}
+ */
+
+/* Include IRDA HAL Extended module */
+#include "stm32f3xx_hal_irda_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup IRDA_Exported_Functions IRDA Exported Functions
+ * @{
+ */
+
+/** @addtogroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
+
+/**
+ * @}
+ */
+
+/** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda);
+
+void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda);
+
+/**
+ * @}
+ */
+
+/* Peripheral Control functions ************************************************/
+
+/** @addtogroup IRDA_Exported_Functions_Group3 Peripheral State and Error functions
+ * @{
+ */
+
+/* Peripheral State and Error functions ***************************************/
+HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
+uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_IRDA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_hal_irda_ex.h b/Inc/stm32f3xx_hal_irda_ex.h
new file mode 100644
index 0000000..0ccb541
--- /dev/null
+++ b/Inc/stm32f3xx_hal_irda_ex.h
@@ -0,0 +1,440 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_irda_ex.h
+ * @author MCD Application Team
+ * @brief Header file of IRDA HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_IRDA_EX_H
+#define __STM32F3xx_HAL_IRDA_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup IRDAEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup IRDAEx_Exported_Constants IRDAEx Exported Constants
+ * @{
+ */
+
+/** @defgroup IRDAEx_Word_Length IRDA Word Length
+ * @{
+ */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F334x8) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define IRDA_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long frame */
+#define IRDA_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long frame */
+#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long frame */
+#else
+#define IRDA_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long frame */
+#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M) /*!< 9-bit long frame */
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F334x8 || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @defgroup IRDAEx_Private_Macros IRDAEx Private Macros
+ * @{
+ */
+
+/** @brief Report the IRDA clock source.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * @param __CLOCKSOURCE__ output variable.
+ * @retval IRDA clocking source, written in __CLOCKSOURCE__.
+ */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK2: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
+ case RCC_USART2CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART2CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART2CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART2CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \
+ { \
+ case RCC_USART3CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART3CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART3CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART3CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == UART4) \
+ { \
+ switch(__HAL_RCC_GET_UART4_SOURCE()) \
+ { \
+ case RCC_UART4CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_UART4CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_UART4CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_UART4CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if ((__HANDLE__)->Instance == UART5) \
+ { \
+ switch(__HAL_RCC_GET_UART5_SOURCE()) \
+ { \
+ case RCC_UART5CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_UART5CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_UART5CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_UART5CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0U)
+#elif defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0U)
+#else
+#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK2: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
+ case RCC_USART2CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART2CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART2CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART2CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \
+ { \
+ case RCC_USART3CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART3CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART3CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART3CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0U)
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+
+
+/** @brief Compute the mask to apply to retrieve the received data
+ * according to the word length and to the parity bits activation.
+ * @note If PCE = 1, the parity bit is not included in the data extracted
+ * by the reception API().
+ * This masking operation is not carried out in the case of
+ * DMA transfers.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * @retval None, the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field.
+ */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
+ defined(STM32F334x8)
+#define IRDA_MASK_COMPUTATION(__HANDLE__) \
+ do { \
+ if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x01FFU ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x00FFU ; \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x00FFU ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x007FU ; \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x007FU ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x003FU ; \
+ } \
+ } \
+} while(0U)
+#else
+#define IRDA_MASK_COMPUTATION(__HANDLE__) \
+ do { \
+ if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x01FFU ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x00FFU ; \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x00FFU ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x007FU ; \
+ } \
+ } \
+} while(0U)
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
+ /* STM32F334x8 */
+/**
+ * @brief Ensure that IRDA frame length is valid.
+ * @param __LENGTH__ IRDA frame length.
+ * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+ */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F334x8) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_7B) || \
+ ((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
+ ((__LENGTH__) == IRDA_WORDLENGTH_9B))
+#else
+#define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
+ ((__LENGTH__) == IRDA_WORDLENGTH_9B))
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F334x8 || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_IRDA_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Inc/stm32f3xx_hal_iwdg.h b/Inc/stm32f3xx_hal_iwdg.h
new file mode 100644
index 0000000..093b5e9
--- /dev/null
+++ b/Inc/stm32f3xx_hal_iwdg.h
@@ -0,0 +1,253 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_iwdg.h
+ * @author MCD Application Team
+ * @brief Header file of IWDG HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_IWDG_H
+#define __STM32F3xx_HAL_IWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup IWDG IWDG
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Types IWDG Exported Types
+ * @{
+ */
+
+/**
+ * @brief IWDG Init structure definition
+ */
+typedef struct
+{
+ uint32_t Prescaler; /*!< Select the prescaler of the IWDG.
+ This parameter can be a value of @ref IWDG_Prescaler */
+
+ uint32_t Reload; /*!< Specifies the IWDG down-counter reload value.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFFU */
+
+ uint32_t Window; /*!< Specifies the window value to be compared to the down-counter.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFFU */
+
+} IWDG_InitTypeDef;
+
+/**
+ * @brief IWDG Handle Structure definition
+ */
+typedef struct
+{
+ IWDG_TypeDef *Instance; /*!< Register base address */
+
+ IWDG_InitTypeDef Init; /*!< IWDG required parameters */
+
+}IWDG_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Constants IWDG Exported Constants
+ * @{
+ */
+
+/** @defgroup IWDG_Prescaler IWDG Prescaler
+ * @{
+ */
+#define IWDG_PRESCALER_4 0x00000000u /*!< IWDG prescaler set to 4 */
+#define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */
+#define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */
+#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */
+#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */
+#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128U */
+#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256U */
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Window_option IWDG Window option
+ * @{
+ */
+#define IWDG_WINDOW_DISABLE IWDG_WINR_WIN
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Macros IWDG Exported Macros
+ * @{
+ */
+
+/**
+ * @brief Enable the IWDG peripheral.
+ * @param __HANDLE__ IWDG handle
+ * @retval None
+ */
+#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
+
+/**
+ * @brief Reload IWDG counter with value defined in the reload register
+ * (write access to IWDG_PR, IWDG_RLR & IWDG_WINR registers disabled).
+ * @param __HANDLE__ IWDG handle
+ * @retval None
+ */
+#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Functions IWDG Exported Functions
+ * @{
+ */
+
+/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
+ * @{
+ */
+/* Initialization/Start functions ********************************************/
+HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+/* I/O operation functions ****************************************************/
+HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup IWDG_Private_Constants IWDG Private Constants
+ * @{
+ */
+/**
+ * @brief IWDG Key Register BitMask
+ */
+#define IWDG_KEY_RELOAD 0x0000AAAAu /*!< IWDG Reload Counter Enable */
+#define IWDG_KEY_ENABLE 0x0000CCCCu /*!< IWDG Peripheral Enable */
+#define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u /*!< IWDG KR Write Access Enable */
+#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u /*!< IWDG KR Write Access Disable */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup IWDG_Private_Macros IWDG Private Macros
+ * @{
+ */
+/**
+ * @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
+ * @param __HANDLE__ IWDG handle
+ * @retval None
+ */
+#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
+
+/**
+ * @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
+ * @param __HANDLE__ IWDG handle
+ * @retval None
+ */
+#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
+
+/**
+ * @brief Check IWDG prescaler value.
+ * @param __PRESCALER__ IWDG prescaler value
+ * @retval None
+ */
+#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_8) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_16) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_32) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_64) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
+ ((__PRESCALER__) == IWDG_PRESCALER_256))
+
+/**
+ * @brief Check IWDG reload value.
+ * @param __RELOAD__ IWDG reload value
+ * @retval None
+ */
+#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
+
+/**
+ * @brief Check IWDG window value.
+ * @param __WINDOW__ IWDG window value
+ * @retval None
+ */
+#define IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_IWDG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_hal_nand.h b/Inc/stm32f3xx_hal_nand.h
new file mode 100644
index 0000000..0c290fc
--- /dev/null
+++ b/Inc/stm32f3xx_hal_nand.h
@@ -0,0 +1,344 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_nand.h
+ * @author MCD Application Team
+ * @brief Header file of NAND HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_NAND_H
+#define __STM32F3xx_HAL_NAND_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+#include "stm32f3xx_ll_fmc.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup NAND
+ * @{
+ */
+
+/* Exported typedef ----------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup NAND_Exported_Types NAND Exported Types
+ * @{
+ */
+
+/**
+ * @brief HAL NAND State structures definition
+ */
+typedef enum
+{
+ HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */
+ HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */
+ HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */
+ HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */
+}HAL_NAND_StateTypeDef;
+
+/**
+ * @brief NAND Memory electronic signature Structure definition
+ */
+typedef struct
+{
+ /*<! NAND memory electronic signature maker and device IDs */
+
+ uint8_t Maker_Id;
+
+ uint8_t Device_Id;
+
+ uint8_t Third_Id;
+
+ uint8_t Fourth_Id;
+}NAND_IDTypeDef;
+
+/**
+ * @brief NAND Memory address Structure definition
+ */
+typedef struct
+{
+ uint16_t Page; /*!< NAND memory Page address */
+
+ uint16_t Plane; /*!< NAND memory Plane address */
+
+ uint16_t Block; /*!< NAND memory Block address */
+
+}NAND_AddressTypeDef;
+
+/**
+ * @brief NAND Memory info Structure definition
+ */
+typedef struct
+{
+ uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes
+ for 8 bits adressing or words for 16 bits addressing */
+
+ uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes
+ for 8 bits adressing or words for 16 bits addressing */
+
+ uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */
+
+ uint32_t BlockNbr; /*!< NAND memory number of total blocks */
+
+ uint32_t PlaneNbr; /*!< NAND memory number of planes */
+
+ uint32_t PlaneSize; /*!< NAND memory plane size measured in number of blocks */
+
+ FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This
+ parameter is mandatory for some NAND parts after the read
+ command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
+ Example: Toshiba THTH58BYG3S0HBAI6.
+ This parameter could be ENABLE or DISABLE
+ Please check the Read Mode sequnece in the NAND device datasheet */
+}NAND_DeviceConfigTypeDef;
+
+/**
+ * @brief NAND handle Structure definition
+ */
+typedef struct
+{
+ FMC_NAND_TypeDef *Instance; /*!< Register base address */
+
+ FMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */
+
+ HAL_LockTypeDef Lock; /*!< NAND locking object */
+
+ __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */
+
+ NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */
+
+}NAND_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros ------------------------------------------------------------*/
+/** @defgroup NAND_Exported_Macros NAND Exported Macros
+ * @{
+ */
+
+/** @brief Reset NAND handle state
+ * @param __HANDLE__ specifies the NAND handle.
+ * @retval None
+ */
+#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup NAND_Exported_Functions NAND Exported Functions
+ * @{
+ */
+
+/** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization/de-initialization functions ********************************/
+/* Initialization/de-initialization functions ********************************/
+HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
+HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
+
+HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
+
+HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
+
+void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
+void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
+void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
+void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
+
+/**
+ * @}
+ */
+
+/** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
+ * @{
+ */
+
+/* IO operation functions ****************************************************/
+HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
+
+HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
+HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
+
+HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead);
+HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite);
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
+
+HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
+
+uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
+uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
+
+/**
+ * @}
+ */
+
+/** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+
+/* NAND Control functions ****************************************************/
+HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
+HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
+HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
+
+/**
+ * @}
+ */
+
+/** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
+ * @{
+ */
+/* NAND State functions *******************************************************/
+HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup NAND_Private_Constants NAND Private Constants
+ * @{
+ */
+#define NAND_DEVICE1 FMC_BANK2
+#define NAND_DEVICE2 FMC_BANK3
+#define NAND_WRITE_TIMEOUT 0x01000000U
+
+#define CMD_AREA ((uint32_t)(1U<<16U)) /* A16 = CLE high */
+#define ADDR_AREA ((uint32_t)(1U<<17U)) /* A17 = ALE high */
+
+#define NAND_CMD_AREA_A ((uint8_t)0x00)
+#define NAND_CMD_AREA_B ((uint8_t)0x01)
+#define NAND_CMD_AREA_C ((uint8_t)0x50)
+#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)
+
+#define NAND_CMD_WRITE0 ((uint8_t)0x80)
+#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
+#define NAND_CMD_ERASE0 ((uint8_t)0x60)
+#define NAND_CMD_ERASE1 ((uint8_t)0xD0)
+#define NAND_CMD_READID ((uint8_t)0x90)
+#define NAND_CMD_STATUS ((uint8_t)0x70)
+#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
+#define NAND_CMD_RESET ((uint8_t)0xFF)
+
+/* NAND memory status */
+#define NAND_VALID_ADDRESS 0x00000100U
+#define NAND_INVALID_ADDRESS 0x00000200U
+#define NAND_TIMEOUT_ERROR 0x00000400U
+#define NAND_BUSY 0x00000000U
+#define NAND_ERROR 0x00000001U
+#define NAND_READY 0x00000040U
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup NAND_Private_Macros NAND Private Macros
+ * @{
+ */
+
+/**
+ * @brief NAND memory address computation.
+ * @param __ADDRESS__ NAND memory address.
+ * @param __HANDLE__ NAND handle.
+ * @retval NAND Raw address value
+ */
+#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
+ (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
+
+/**
+ * @brief NAND memory Column address computation.
+ * @param __HANDLE__ NAND handle.
+ * @retval NAND Raw address value
+ */
+#define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)
+
+/**
+ * @brief NAND memory address cycling.
+ * @param __ADDRESS__ NAND memory address.
+ * @retval NAND address cycling value.
+ */
+#define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
+#define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */
+#define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */
+#define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */
+
+/**
+ * @brief NAND memory Columns cycling.
+ * @param __ADDRESS__ NAND memory address.
+ * @retval NAND Column address cycling value.
+ */
+#define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st Column addressing cycle */
+#define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_NAND_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_hal_nor.h b/Inc/stm32f3xx_hal_nor.h
new file mode 100644
index 0000000..a5cd859
--- /dev/null
+++ b/Inc/stm32f3xx_hal_nor.h
@@ -0,0 +1,298 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_nor.h
+ * @author MCD Application Team
+ * @brief Header file of NOR HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_NOR_H
+#define __STM32F3xx_HAL_NOR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+#include "stm32f3xx_ll_fmc.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup NOR
+ * @{
+ */
+
+
+/** @addtogroup NOR_Private_Constants
+ * @{
+ */
+
+/* NOR device IDs addresses */
+#define MC_ADDRESS ((uint16_t)0x0000U)
+#define DEVICE_CODE1_ADDR ((uint16_t)0x0001U)
+#define DEVICE_CODE2_ADDR ((uint16_t)0x000EU)
+#define DEVICE_CODE3_ADDR ((uint16_t)0x000FU)
+
+/* NOR CFI IDs addresses */
+#define CFI1_ADDRESS ((uint16_t)0x10U)
+#define CFI2_ADDRESS ((uint16_t)0x11U)
+#define CFI3_ADDRESS ((uint16_t)0x12U)
+#define CFI4_ADDRESS ((uint16_t)0x13U)
+
+/* NOR memory data width */
+#define NOR_MEMORY_8B ((uint8_t)0x0U)
+#define NOR_MEMORY_16B ((uint8_t)0x1U)
+
+/* NOR memory device read/write start address */
+#define NOR_MEMORY_ADRESS1 FMC_BANK1_1
+#define NOR_MEMORY_ADRESS2 FMC_BANK1_2
+#define NOR_MEMORY_ADRESS3 FMC_BANK1_3
+#define NOR_MEMORY_ADRESS4 FMC_BANK1_4
+
+/**
+ * @}
+ */
+
+/** @addtogroup NOR_Private_Macros
+ * @{
+ */
+
+/**
+ * @brief NOR memory address shifting.
+ * @param __NOR_ADDRESS NOR base address
+ * @param __NOR_MEMORY_WIDTH_ NOR memory width
+ * @param __ADDRESS__ NOR memory address
+ * @retval NOR shifted address value
+ */
+#define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \
+ ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \
+ ((uint32_t)((__NOR_ADDRESS) + (2U * (__ADDRESS__)))): \
+ ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
+
+/**
+ * @brief NOR memory write data to specified address.
+ * @param __ADDRESS__ NOR memory address
+ * @param __DATA__ Data to write
+ * @retval None
+ */
+#define NOR_WRITE(__ADDRESS__, __DATA__) (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__))
+
+/**
+ * @}
+ */
+
+/* Exported typedef ----------------------------------------------------------*/
+/** @defgroup NOR_Exported_Types NOR Exported Types
+ * @{
+ */
+
+/**
+ * @brief HAL SRAM State structures definition
+ */
+typedef enum
+{
+ HAL_NOR_STATE_RESET = 0x00U, /*!< NOR not yet initialized or disabled */
+ HAL_NOR_STATE_READY = 0x01U, /*!< NOR initialized and ready for use */
+ HAL_NOR_STATE_BUSY = 0x02U, /*!< NOR internal processing is ongoing */
+ HAL_NOR_STATE_ERROR = 0x03U, /*!< NOR error state */
+ HAL_NOR_STATE_PROTECTED = 0x04 /*!< NOR NORSRAM device write protected */
+}HAL_NOR_StateTypeDef;
+
+/**
+ * @brief FMC NOR Status typedef
+ */
+typedef enum
+{
+ HAL_NOR_STATUS_SUCCESS = 0U,
+ HAL_NOR_STATUS_ONGOING,
+ HAL_NOR_STATUS_ERROR,
+ HAL_NOR_STATUS_TIMEOUT
+}HAL_NOR_StatusTypeDef;
+
+/**
+ * @brief FMC NOR ID typedef
+ */
+typedef struct
+{
+ uint16_t Manufacturer_Code; /*!< Defines the device's manufacturer code used to identify the memory */
+
+ uint16_t Device_Code1;
+
+ uint16_t Device_Code2;
+
+ uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory.
+ These codes can be accessed by performing read operations with specific
+ control signals and addresses set.They can also be accessed by issuing
+ an Auto Select command. */
+}NOR_IDTypeDef;
+
+/**
+ * @brief FMC NOR CFI typedef
+ */
+typedef struct
+{
+ uint16_t CFI_1;
+
+ uint16_t CFI_2;
+
+ uint16_t CFI_3;
+
+ uint16_t CFI_4; /*!< Defines the information stored in the memory's Common flash interface
+ which contains a description of various electrical and timing parameters,
+ density information and functions supported by the memory. */
+}NOR_CFITypeDef;
+
+/**
+ * @brief NOR handle Structure definition
+ */
+typedef struct
+{
+ FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
+
+ FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
+
+ FMC_NORSRAM_InitTypeDef Init; /*!< NOR device control configuration parameters */
+
+ HAL_LockTypeDef Lock; /*!< NOR locking object */
+
+ __IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */
+
+}NOR_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup NOR_Exported_Macros NOR Exported Macros
+ * @{
+ */
+
+/** @brief Reset NOR handle state
+ * @param __HANDLE__ NOR handle
+ * @retval None
+ */
+#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup NOR_Exported_Functions NOR Exported Functions
+ * @{
+ */
+
+/** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization/de-initialization functions ********************************/
+HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
+HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
+void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
+void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
+void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
+
+/**
+ * @}
+ */
+
+/** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions
+ * @{
+ */
+
+/* I/O operation functions ***************************************************/
+HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
+HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
+HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
+HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
+
+HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
+HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
+
+HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
+HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
+HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
+
+/**
+ * @}
+ */
+
+/** @addtogroup NOR_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+
+/* NOR Control functions *****************************************************/
+HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
+HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
+
+/**
+ * @}
+ */
+
+/** @addtogroup NOR_Exported_Functions_Group4 Peripheral State functions
+ * @{
+ */
+
+/* NOR State functions ********************************************************/
+HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
+HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_NOR_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_hal_opamp.h b/Inc/stm32f3xx_hal_opamp.h
new file mode 100644
index 0000000..9c970e9
--- /dev/null
+++ b/Inc/stm32f3xx_hal_opamp.h
@@ -0,0 +1,507 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_opamp.h
+ * @author MCD Application Team
+ * @brief Header file of OPAMP HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_OPAMP_H
+#define __STM32F3xx_HAL_OPAMP_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup OPAMP
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup OPAMP_Exported_Types OPAMP Exported Types
+ * @{
+ */
+
+/**
+ * @brief OPAMP Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t Mode; /*!< Specifies the OPAMP mode
+ This parameter must be a value of @ref OPAMP_Mode
+ mode is either Standalone, - Follower or PGA */
+
+ uint32_t InvertingInput; /*!< Specifies the inverting input in Standalone & Pga modes
+ - In Standalone mode: i.e when mode is OPAMP_STANDALONE_MODE
+ This parameter must be a value of @ref OPAMP_InvertingInput
+ InvertingInput is either VM0 or VM1
+ - In PGA mode: i.e when mode is OPAMP_PGA_MODE
+ & in Follower mode i.e when mode is OPAMP_FOLLOWER_MODE
+ This parameter is Not Applicable */
+
+ uint32_t NonInvertingInput; /*!< Specifies the non inverting input of the opamp:
+ This parameter must be a value of @ref OPAMP_NonInvertingInput
+ NonInvertingInput is either VP0, VP1, VP2 or VP3 */
+
+ uint32_t TimerControlledMuxmode; /*!< Specifies if the Timer controlled Mux mode is enabled or disabled
+ This parameter must be a value of @ref OPAMP_TimerControlledMuxmode */
+
+ uint32_t InvertingInputSecondary; /*!< Specifies the inverting input (secondary) of the opamp when
+ TimerControlledMuxmode is enabled
+ i.e. when TimerControlledMuxmode is OPAMP_TIMERCONTROLLEDMUXMODE_ENABLE
+ - In Standalone mode: i.e when mode is OPAMP_STANDALONE_MODE
+ This parameter must be a value of @ref OPAMP_InvertingInputSecondary
+ InvertingInputSecondary is either VM0 or VM1
+ - In PGA mode: i.e when mode is OPAMP_PGA_MODE
+ & in Follower mode i.e when mode is OPAMP_FOLLOWER_MODE
+ This parameter is Not Applicable */
+
+ uint32_t NonInvertingInputSecondary; /*!< Specifies the non inverting input (secondary) of the opamp when
+ TimerControlledMuxmode is enabled
+ i.e. when TimerControlledMuxmode is OPAMP_TIMERCONTROLLEDMUXMODE_ENABLE
+ This parameter must be a value of @ref OPAMP_NonInvertingInputSecondary
+ NonInvertingInput is either VP0, VP1, VP2 or VP3 */
+
+ uint32_t PgaConnect; /*!< Specifies the inverting pin in PGA mode
+ i.e. when mode is OPAMP_PGA_MODE
+ This parameter must be a value of @ref OPAMP_PgaConnect
+ Either: not connected, connected to VM0, connected to VM1
+ (VM0 or VM1 are typically used for external filtering) */
+
+ uint32_t PgaGain; /*!< Specifies the gain in PGA mode
+ i.e. when mode is OPAMP_PGA_MODE.
+ This parameter must be a value of @ref OPAMP_PgaGain (2U, 4U, 8 or 16U ) */
+
+ uint32_t UserTrimming; /*!< Specifies the trimming mode
+ This parameter must be a value of @ref OPAMP_UserTrimming
+ UserTrimming is either factory or user trimming */
+
+ uint32_t TrimmingValueP; /*!< Specifies the offset trimming value (PMOS)
+ i.e. when UserTrimming is OPAMP_TRIMMING_USER.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 31U */
+
+ uint32_t TrimmingValueN; /*!< Specifies the offset trimming value (NMOS)
+ i.e. when UserTrimming is OPAMP_TRIMMING_USER.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 31U */
+
+}OPAMP_InitTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+
+typedef enum
+{
+ HAL_OPAMP_STATE_RESET = 0x00000000U, /*!< OPMAP is not yet Initialized */
+
+ HAL_OPAMP_STATE_READY = 0x00000001U, /*!< OPAMP is initialized and ready for use */
+ HAL_OPAMP_STATE_CALIBBUSY = 0x00000002U, /*!< OPAMP is enabled in auto calibration mode */
+
+ HAL_OPAMP_STATE_BUSY = 0x00000004U, /*!< OPAMP is enabled and running in normal mode */
+ HAL_OPAMP_STATE_BUSYLOCKED = 0x00000005U, /*!< OPAMP is locked
+ only system reset allows reconfiguring the opamp. */
+
+}HAL_OPAMP_StateTypeDef;
+
+/**
+ * @brief OPAMP Handle Structure definition to @brief OPAMP Handle Structure definition
+ */
+typedef struct
+{
+ OPAMP_TypeDef *Instance; /*!< OPAMP instance's registers base address */
+ OPAMP_InitTypeDef Init; /*!< OPAMP required parameters */
+ HAL_StatusTypeDef Status; /*!< OPAMP peripheral status */
+ HAL_LockTypeDef Lock; /*!< Locking object */
+ __IO HAL_OPAMP_StateTypeDef State; /*!< OPAMP communication state */
+
+} OPAMP_HandleTypeDef;
+
+/**
+ * @brief OPAMP_TrimmingValueTypeDef @brief definition
+ */
+
+typedef uint32_t OPAMP_TrimmingValueTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup OPAMP_Exported_Constants OPAMP Exported Constants
+ * @{
+ */
+
+/** @defgroup OPAMP_CSR_INIT OPAMP CSR init register Mask
+ * @{
+ */
+/* Used for Init phase */
+#define OPAMP_CSR_UPDATE_PARAMETERS_INIT_MASK (OPAMP_CSR_TRIMOFFSETN | OPAMP_CSR_TRIMOFFSETP \
+ | OPAMP_CSR_USERTRIM | OPAMP_CSR_PGGAIN | OPAMP_CSR_VPSSEL \
+ | OPAMP_CSR_VMSSEL | OPAMP_CSR_TCMEN | OPAMP_CSR_VPSEL \
+ | OPAMP_CSR_VMSEL | OPAMP_CSR_FORCEVP)
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_Mode OPAMP Mode
+ * @{
+ */
+#define OPAMP_STANDALONE_MODE (0x00000000U) /*!< standalone mode */
+#define OPAMP_PGA_MODE OPAMP_CSR_VMSEL_1 /*!< PGA mode */
+#define OPAMP_FOLLOWER_MODE OPAMP_CSR_VMSEL /*!< follower mode */
+
+
+#define IS_OPAMP_FUNCTIONAL_NORMALMODE(INPUT) (((INPUT) == OPAMP_STANDALONE_MODE) || \
+ ((INPUT) == OPAMP_PGA_MODE) || \
+ ((INPUT) == OPAMP_FOLLOWER_MODE))
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_NonInvertingInput OPAMP Non Inverting Input
+ * @{
+ */
+
+#define OPAMP_NONINVERTINGINPUT_IO0 OPAMP_CSR_VPSEL /*!< VP0 (PA1 for OPAMP1, VP0 PA7 for OPAMP2, VP0 PB0 for OPAMP3, VP0 PB13 for OPAMP4)
+ connected to OPAMPx non inverting input */
+#define OPAMP_NONINVERTINGINPUT_IO1 (0x00000000U) /*!< VP1 (PA7 for OPAMP1, VP3 PD14 for OPAMP2, VP1 PB13 for OPAMP3, VP1 PD11 for OPAMP4)
+ connected to OPAMPx non inverting input */
+#define OPAMP_NONINVERTINGINPUT_IO2 OPAMP_CSR_VPSEL_1 /*!< VP2 (PA3 for OPAMP1, VP2 PB0 for OPAMP2, VP2 PA1 for OPAMP3, VP3 PA4 for OPAMP4)
+ connected to OPAMPx non inverting input */
+#define OPAMP_NONINVERTINGINPUT_IO3 OPAMP_CSR_VPSEL_0 /*!< VP3 (PA5 for OPAMP1, VP1 PB14 for OPAMP2, VP3 PA5 for OPAMP3, VP2 PB11 for OPAMP4)
+ connected to OPAMPx non inverting input */
+
+#define IS_OPAMP_NONINVERTING_INPUT(INPUT) (((INPUT) == OPAMP_NONINVERTINGINPUT_IO0) || \
+ ((INPUT) == OPAMP_NONINVERTINGINPUT_IO1) || \
+ ((INPUT) == OPAMP_NONINVERTINGINPUT_IO2) || \
+ ((INPUT) == OPAMP_NONINVERTINGINPUT_IO3))
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_InvertingInput OPAMP Inverting Input
+ * @{
+ */
+
+#define OPAMP_INVERTINGINPUT_IO0 (0x00000000U) /*!< inverting input connected to VM0 */
+#define OPAMP_INVERTINGINPUT_IO1 OPAMP_CSR_VMSEL_0 /*!< inverting input connected to VM1 */
+
+#define IS_OPAMP_INVERTING_INPUT(INPUT) (((INPUT) == OPAMP_INVERTINGINPUT_IO0) || \
+ ((INPUT) == OPAMP_INVERTINGINPUT_IO1))
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_TimerControlledMuxmode OPAMP Timer Controlled Mux mode
+ * @{
+ */
+ #define OPAMP_TIMERCONTROLLEDMUXMODE_DISABLE (0x00000000U) /*!< Timer controlled Mux mode disabled */
+ #define OPAMP_TIMERCONTROLLEDMUXMODE_ENABLE OPAMP_CSR_TCMEN /*!< Timer controlled Mux mode enabled */
+
+ #define IS_OPAMP_TIMERCONTROLLED_MUXMODE(MUXMODE) (((MUXMODE) == OPAMP_TIMERCONTROLLEDMUXMODE_DISABLE) || \
+ ((MUXMODE) == OPAMP_TIMERCONTROLLEDMUXMODE_ENABLE))
+/**
+ * @}
+ */
+
+ /** @defgroup OPAMP_NonInvertingInputSecondary OPAMP Non Inverting Input Secondary
+ * @{
+ */
+
+#define OPAMP_SEC_NONINVERTINGINPUT_IO0 OPAMP_CSR_VPSSEL /*!< VP0 (PA1 for OPAMP1, PA7 for OPAMP2, PB0 for OPAMP3, PB13 for OPAMP4)
+ connected to OPAMPx non inverting input */
+#define OPAMP_SEC_NONINVERTINGINPUT_IO1 (0x00000000U) /*!< VP1 (PA7 for OPAMP1, PD14 for OPAMP2, PB13 for OPAMP3, PD11 for OPAMP4)
+ connected to OPAMPx non inverting input */
+#define OPAMP_SEC_NONINVERTINGINPUT_IO2 OPAMP_CSR_VPSSEL_1 /*!< VP2 (PA3 for OPAMP1, PB0 for OPAMP2, PA1 for OPAMP3, PA4 for OPAMP4)
+ connected to OPAMPx non inverting input */
+#define OPAMP_SEC_NONINVERTINGINPUT_IO3 OPAMP_CSR_VPSSEL_0 /*!< VP3 (PA5 for OPAMP1, PB14 for OPAMP2, PA5 for OPAMP3, PB11 for OPAMP4)
+ connected to OPAMPx non inverting input */
+
+#define IS_OPAMP_SEC_NONINVERTINGINPUT(INPUT) (((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_IO0) || \
+ ((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_IO1) || \
+ ((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_IO2) || \
+ ((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_IO3))
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_InvertingInputSecondary OPAMP Inverting Input Secondary
+ * @{
+ */
+
+#define OPAMP_SEC_INVERTINGINPUT_IO0 (0x00000000U) /*!< VM0 (PC5 for OPAMP1 and OPAMP2, PB10 for OPAMP3 and OPAMP4)
+ connected to OPAMPx inverting input */
+#define OPAMP_SEC_INVERTINGINPUT_IO1 OPAMP_CSR_VMSSEL /*!< VM1 (PA3 for OPAMP1, PA5 for OPAMP2, PB2 for OPAMP3, PD8 for OPAMP4)
+ connected to OPAMPx inverting input */
+
+#define IS_OPAMP_SEC_INVERTINGINPUT(INPUT) (((INPUT) == OPAMP_SEC_INVERTINGINPUT_IO0) || \
+ ((INPUT) == OPAMP_SEC_INVERTINGINPUT_IO1))
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_PgaConnect OPAMP Pga Connect
+ * @{
+ */
+
+#define OPAMP_PGA_CONNECT_INVERTINGINPUT_NO (0x00000000U) /*!< In PGA mode, the non inverting input is not connected */
+#define OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 OPAMP_CSR_PGGAIN_3 /*!< In PGA mode, the non inverting input is connected to VM0 */
+#define OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 (OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_PGGAIN_3) /*!< In PGA mode, the non inverting input is connected to VM1 */
+
+#define IS_OPAMP_PGACONNECT(CONNECT) (((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_NO) || \
+ ((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0) || \
+ ((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1))
+/**
+ * @}
+ */
+
+
+/** @defgroup OPAMP_PgaGain OPAMP Pga Gain
+ * @{
+ */
+
+#define OPAMP_PGA_GAIN_2 (0x00000000U) /*!< PGA gain = 2 */
+#define OPAMP_PGA_GAIN_4 OPAMP_CSR_PGGAIN_0 /*!< PGA gain = 4 */
+#define OPAMP_PGA_GAIN_8 OPAMP_CSR_PGGAIN_1 /*!< PGA gain = 8 */
+#define OPAMP_PGA_GAIN_16 (OPAMP_CSR_PGGAIN_0 | OPAMP_CSR_PGGAIN_1) /*!< PGA gain = 16 */
+
+#define IS_OPAMP_PGA_GAIN(GAIN) (((GAIN) == OPAMP_PGA_GAIN_2) || \
+ ((GAIN) == OPAMP_PGA_GAIN_4) || \
+ ((GAIN) == OPAMP_PGA_GAIN_8) || \
+ ((GAIN) == OPAMP_PGA_GAIN_16))
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_UserTrimming OPAMP User Trimming
+ * @{
+ */
+
+#define OPAMP_TRIMMING_FACTORY (0x00000000U) /*!< Factory trimming */
+#define OPAMP_TRIMMING_USER OPAMP_CSR_USERTRIM /*!< User trimming */
+
+#define IS_OPAMP_TRIMMING(TRIMMING) (((TRIMMING) == OPAMP_TRIMMING_FACTORY) || \
+ ((TRIMMING) == OPAMP_TRIMMING_USER))
+
+/** @defgroup OPAMP_FactoryTrimming OPAMP Factory Trimming
+ * @{
+ */
+
+#define OPAMP_FACTORYTRIMMING_DUMMY (0xFFFFFFFFU) /*!< Dummy trimming value */
+
+#define OPAMP_FACTORYTRIMMING_N (0x00000000U) /*!< Offset trimming N */
+#define OPAMP_FACTORYTRIMMING_P (0x00000001U) /*!< Offset trimming P */
+
+#define IS_OPAMP_FACTORYTRIMMING(TRIMMING) (((TRIMMING) == OPAMP_FACTORYTRIMMING_N) || \
+ ((TRIMMING) == OPAMP_FACTORYTRIMMING_P))
+
+/**
+ * @}
+ */
+
+
+/** @defgroup OPAMP_TrimmingValue OPAMP Trimming Value
+ * @{
+ */
+
+#define IS_OPAMP_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)
+
+
+/**
+ * @}
+ */
+
+
+/** @defgroup OPAMP_Input OPAMP Input
+ * @{
+ */
+
+#define OPAMP_INPUT_INVERTING ( 24U) /*!< Inverting input */
+#define OPAMP_INPUT_NONINVERTING ( 19U) /*!< Non inverting input */
+
+#define IS_OPAMP_INPUT(INPUT) (((INPUT) == OPAMP_INPUT_INVERTING) || \
+ ((INPUT) == OPAMP_INPUT_NONINVERTING))
+/**
+ * @}
+ */
+
+
+/** @defgroup OPAMP_VREF OPAMP VREF
+ * @{
+ */
+
+#define OPAMP_VREF_3VDDA (0x00000000U) /*!< OPMAP Vref = 3.3U% VDDA */
+#define OPAMP_VREF_10VDDA OPAMP_CSR_CALSEL_0 /*!< OPMAP Vref = 10U% VDDA */
+#define OPAMP_VREF_50VDDA OPAMP_CSR_CALSEL_1 /*!< OPMAP Vref = 50U% VDDA */
+#define OPAMP_VREF_90VDDA OPAMP_CSR_CALSEL /*!< OPMAP Vref = 90U% VDDA */
+
+#define IS_OPAMP_VREF(VREF) (((VREF) == OPAMP_VREF_3VDDA) || \
+ ((VREF) == OPAMP_VREF_10VDDA) || \
+ ((VREF) == OPAMP_VREF_50VDDA) || \
+ ((VREF) == OPAMP_VREF_90VDDA))
+
+/**
+ * @}
+ */
+
+ /** @defgroup OPAMP_Vref2ADCforCalib OPAMP Vref2ADCforCalib
+ */
+
+#define OPAMP_VREF_NOTCONNECTEDTO_ADC (0x00000000U) /*!< VREF not connected to ADC */
+#define OPAMP_VREF_CONNECTEDTO_ADC (0x00000001U) /*!< VREF not connected to ADC */
+
+#define IS_OPAMP_ALLOPAMPVREF_CONNECT(CONNECT) (((CONNECT) == OPAMP_VREF_NOTCONNECTEDTO_ADC) || \
+ ((CONNECT) == OPAMP_VREF_CONNECTEDTO_ADC))
+
+
+ /**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup OPAMP_Exported_Macros OPAMP Exported Macros
+ * @{
+ */
+
+/** @brief Reset OPAMP handle state
+ * @param __HANDLE__ OPAMP handle.
+ * @retval None
+ */
+#define __HAL_OPAMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OPAMP_STATE_RESET)
+
+/**
+ * @}
+ */
+
+/* Include OPAMP HAL Extended module */
+#include "stm32f3xx_hal_opamp_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup OPAMP_Exported_Functions OPAMP Exported Functions
+ * @{
+ */
+
+/** @defgroup OPAMP_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp);
+HAL_StatusTypeDef HAL_OPAMP_DeInit (OPAMP_HandleTypeDef *hopamp);
+void HAL_OPAMP_MspInit(OPAMP_HandleTypeDef *hopamp);
+void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef *hopamp);
+/**
+ * @}
+ */
+
+
+/** @defgroup OPAMP_Exported_Functions_Group2 Input and Output operation functions
+ * @{
+ */
+
+/* I/O operation functions *****************************************************/
+HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef *hopamp);
+HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp);
+HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp);
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+
+/* Peripheral Control functions ************************************************/
+HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp);
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_Exported_Functions_Group4 Peripheral State functions
+ * @{
+ */
+
+/* Peripheral State functions **************************************************/
+HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp);
+OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_OPAMP_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_hal_opamp_ex.h b/Inc/stm32f3xx_hal_opamp_ex.h
new file mode 100644
index 0000000..41176c7
--- /dev/null
+++ b/Inc/stm32f3xx_hal_opamp_ex.h
@@ -0,0 +1,115 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_opamp_ex.h
+ * @author MCD Application Team
+ * @brief Header file of OPAMP HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_OPAMP_EX_H
+#define __STM32F3xx_HAL_OPAMP_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup OPAMPEx OPAMPEx
+ * @{
+ */
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup OPAMPEx_Exported_Functions OPAMP Extended Exported Functions
+ * @{
+ */
+
+/** @addtogroup OPAMPEx_Exported_Functions_Group1 Extended Input and Output operation functions
+ * @{
+ */
+
+/* I/O operation functions *****************************************************/
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC)
+
+HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2);
+
+#endif /* STM32F302xE || */
+ /* STM32F302xC */
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2, OPAMP_HandleTypeDef *hopamp3, OPAMP_HandleTypeDef *hopamp4);
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F3xx_HAL_OPAMP_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_hal_pccard.h b/Inc/stm32f3xx_hal_pccard.h
new file mode 100644
index 0000000..fe633cc
--- /dev/null
+++ b/Inc/stm32f3xx_hal_pccard.h
@@ -0,0 +1,247 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_pccard.h
+ * @author MCD Application Team
+ * @brief Header file of PCCARD HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_PCCARD_H
+#define __STM32F3xx_HAL_PCCARD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+#include "stm32f3xx_ll_fmc.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup PCCARD
+ * @{
+ */
+
+/** @addtogroup PCCARD_Private_Constants
+ * @{
+ */
+
+#define PCCARD_DEVICE_ADDRESS FMC_BANK4
+#define PCCARD_ATTRIBUTE_SPACE_ADDRESS ((uint32_t)(FMC_BANK4 + 0x08000000U)) /* Attribute space size to @0x9BFF FFFF */
+#define PCCARD_COMMON_SPACE_ADDRESS PCCARD_DEVICE_ADDRESS /* Common space size to @0x93FF FFFF */
+#define PCCARD_IO_SPACE_ADDRESS ((uint32_t)(FMC_BANK4 + 0x0C000000U)) /* IO space size to @0x9FFF FFFF */
+#define PCCARD_IO_SPACE_PRIMARY_ADDR ((uint32_t)(FMC_BANK4 + 0x0C0001F0U)) /* IO space size to @0x9FFF FFFF */
+
+/* Compact Flash-ATA registers description */
+#define ATA_DATA ((uint8_t)0x00U) /* Data register */
+#define ATA_SECTOR_COUNT ((uint8_t)0x02U) /* Sector Count register */
+#define ATA_SECTOR_NUMBER ((uint8_t)0x03U) /* Sector Number register */
+#define ATA_CYLINDER_LOW ((uint8_t)0x04U) /* Cylinder low register */
+#define ATA_CYLINDER_HIGH ((uint8_t)0x05U) /* Cylinder high register */
+#define ATA_CARD_HEAD ((uint8_t)0x06U) /* Card/Head register */
+#define ATA_STATUS_CMD ((uint8_t)0x07U) /* Status(read)/Command(write) register */
+#define ATA_STATUS_CMD_ALTERNATE ((uint8_t)0x0EU) /* Alternate Status(read)/Command(write) register */
+#define ATA_COMMON_DATA_AREA ((uint16_t)0x0400U) /* Start of data area (for Common access only!) */
+#define ATA_CARD_CONFIGURATION ((uint16_t)0x0202U) /* Card Configuration and Status Register */
+
+/* Compact Flash-ATA commands */
+#define ATA_READ_SECTOR_CMD ((uint8_t)0x20U)
+#define ATA_WRITE_SECTOR_CMD ((uint8_t)0x30U)
+#define ATA_ERASE_SECTOR_CMD ((uint8_t)0xC0U)
+#define ATA_IDENTIFY_CMD ((uint8_t)0xECU)
+
+/* Compact Flash status */
+#define PCCARD_TIMEOUT_ERROR ((uint8_t)0x60U)
+#define PCCARD_BUSY ((uint8_t)0x80U)
+#define PCCARD_PROGR ((uint8_t)0x01U)
+#define PCCARD_READY ((uint8_t)0x40U)
+
+#define PCCARD_SECTOR_SIZE (255U) /* In half words */
+
+
+/* Compact Flash redefinition */
+#define HAL_CF_Read_ID HAL_PCCARD_Read_ID
+#define HAL_CF_Write_Sector HAL_PCCARD_Write_Sector
+#define HAL_CF_Read_Sector HAL_PCCARD_Read_Sector
+#define HAL_CF_Erase_Sector HAL_PCCARD_Erase_Sector
+#define HAL_CF_Reset HAL_PCCARD_Reset
+
+#define HAL_CF_GetStatus HAL_PCCARD_GetStatus
+#define HAL_CF_ReadStatus HAL_PCCARD_ReadStatus
+
+#define CF_SUCCESS HAL_PCCARD_STATUS_SUCCESS
+#define CF_ONGOING HAL_PCCARD_STATUS_ONGOING
+#define CF_ERROR HAL_PCCARD_STATUS_ERROR
+#define CF_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
+#define HAL_PCCARD_StatusTypeDef HAL_PCCARD_StatusTypeDef
+
+
+#define CF_DEVICE_ADDRESS PCCARD_DEVICE_ADDRESS
+#define CF_ATTRIBUTE_SPACE_ADDRESS PCCARD_ATTRIBUTE_SPACE_ADDRESS
+#define CF_COMMON_SPACE_ADDRESS PCCARD_COMMON_SPACE_ADDRESS
+#define CF_IO_SPACE_ADDRESS PCCARD_IO_SPACE_ADDRESS
+#define CF_IO_SPACE_PRIMARY_ADDR PCCARD_IO_SPACE_PRIMARY_ADDR
+
+#define CF_TIMEOUT_ERROR PCCARD_TIMEOUT_ERROR
+#define CF_BUSY PCCARD_BUSY
+#define CF_PROGR PCCARD_PROGR
+#define CF_READY PCCARD_READY
+
+#define CF_SECTOR_SIZE PCCARD_SECTOR_SIZE
+
+/**
+ * @}
+ */
+
+/* Exported typedef ----------------------------------------------------------*/
+/** @defgroup PCCARD_Exported_Types PCCARD Exported Types
+ * @{
+ */
+
+/**
+ * @brief HAL PCCARD State structures definition
+ */
+typedef enum
+{
+ HAL_PCCARD_STATE_RESET = 0x00U, /*!< PCCARD peripheral not yet initialized or disabled */
+ HAL_PCCARD_STATE_READY = 0x01U, /*!< PCCARD peripheral ready */
+ HAL_PCCARD_STATE_BUSY = 0x02U, /*!< PCCARD peripheral busy */
+ HAL_PCCARD_STATE_ERROR = 0x04 /*!< PCCARD peripheral error */
+}HAL_PCCARD_StateTypeDef;
+
+typedef enum
+{
+ HAL_PCCARD_STATUS_SUCCESS = 0U,
+ HAL_PCCARD_STATUS_ONGOING,
+ HAL_PCCARD_STATUS_ERROR,
+ HAL_PCCARD_STATUS_TIMEOUT
+}HAL_PCCARD_StatusTypeDef;
+
+/**
+ * @brief FMC_PCCARD handle Structure definition
+ */
+typedef struct
+{
+ FMC_PCCARD_TypeDef *Instance; /*!< Register base address for PCCARD device */
+
+ FMC_PCCARD_InitTypeDef Init; /*!< PCCARD device control configuration parameters */
+
+ __IO HAL_PCCARD_StateTypeDef State; /*!< PCCARD device access state */
+
+ HAL_LockTypeDef Lock; /*!< PCCARD Lock */
+
+}PCCARD_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup PCCARD_Exported_Macros PCCARD Exported Macros
+ * @{
+ */
+
+/** @brief Reset PCCARD handle state
+ * @param __HANDLE__ specifies the PCCARD handle.
+ * @retval None
+ */
+#define __HAL_PCCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_PCCARD_STATE_RESET)
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PCCARD_Exported_Functions PCCARD Exported Functions
+ * @{
+ */
+
+/** @addtogroup PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming);
+HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard);
+void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard);
+void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard);
+/**
+ * @}
+ */
+
+/** @addtogroup PCCARD_Exported_Functions_Group2 Input Output and memory functions
+ * @{
+ */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus);
+HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus);
+HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus);
+HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus);
+HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard);
+void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard);
+void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard);
+
+/**
+ * @}
+ */
+
+/** @defgroup PCCARD_Exported_Functions_Group3 Peripheral State functions
+ * @{
+ */
+/* PCCARD State functions *******************************************************/
+HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard);
+HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard);
+HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_PCCARD_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_hal_pcd.h b/Inc/stm32f3xx_hal_pcd.h
new file mode 100644
index 0000000..026795b
--- /dev/null
+++ b/Inc/stm32f3xx_hal_pcd.h
@@ -0,0 +1,891 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_pcd.h
+ * @author MCD Application Team
+ * @brief Header file of PCD HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_PCD_H
+#define __STM32F3xx_HAL_PCD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || \
+ defined(STM32F302x8) || \
+ defined(STM32F373xC)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup PCD
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup PCD_Exported_Types PCD Exported Types
+ * @{
+ */
+
+/**
+ * @brief PCD State structure definition
+ */
+typedef enum
+{
+ HAL_PCD_STATE_RESET = 0x00U,
+ HAL_PCD_STATE_READY = 0x01U,
+ HAL_PCD_STATE_ERROR = 0x02U,
+ HAL_PCD_STATE_BUSY = 0x03U,
+ HAL_PCD_STATE_TIMEOUT = 0x04U
+} PCD_StateTypeDef;
+
+/**
+ * @brief PCD double buffered endpoint direction
+ */
+typedef enum
+{
+ PCD_EP_DBUF_OUT,
+ PCD_EP_DBUF_IN,
+ PCD_EP_DBUF_ERR,
+}PCD_EP_DBUF_DIR;
+
+/**
+ * @brief PCD endpoint buffer number
+ */
+typedef enum
+{
+ PCD_EP_NOBUF,
+ PCD_EP_BUF0,
+ PCD_EP_BUF1
+}PCD_EP_BUF_NUM;
+
+/**
+ * @brief PCD Initialization Structure definition
+ */
+typedef struct
+{
+ uint32_t dev_endpoints; /*!< Device Endpoints number.
+ This parameter depends on the used USB core.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+
+ uint32_t speed; /*!< USB Core speed.
+ This parameter can be any value of @ref PCD_Core_Speed */
+
+ uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size.
+ This parameter can be any value of @ref PCD_EP0_MPS */
+
+ uint32_t phy_itface; /*!< Select the used PHY interface.
+ This parameter can be any value of @ref PCD_Core_PHY */
+
+ uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal.
+ This parameter can be set to ENABLE or DISABLE */
+
+ uint32_t low_power_enable; /*!< Enable or disable Low Power mode
+ This parameter can be set to ENABLE or DISABLE */
+
+ uint32_t lpm_enable; /*!< Enable or disable the Link Power Management .
+ This parameter can be set to ENABLE or DISABLE */
+
+ uint32_t battery_charging_enable; /*!< Enable or disable Battery charging.
+ This parameter can be set to ENABLE or DISABLE */
+
+}PCD_InitTypeDef;
+
+typedef struct
+{
+ uint8_t num; /*!< Endpoint number
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+
+ uint8_t is_in; /*!< Endpoint direction
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+
+ uint8_t is_stall; /*!< Endpoint stall condition
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+
+ uint8_t type; /*!< Endpoint type
+ This parameter can be any value of @ref PCD_EP_Type */
+
+ uint16_t pmaadress; /*!< PMA Address
+ This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
+
+
+ uint16_t pmaaddr0; /*!< PMA Address0
+ This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
+
+
+ uint16_t pmaaddr1; /*!< PMA Address1
+ This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
+
+
+ uint8_t doublebuffer; /*!< Double buffer enable
+ This parameter can be 0 or 1 */
+
+ uint32_t maxpacket; /*!< Endpoint Max packet size
+ This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
+
+ uint8_t *xfer_buff; /*!< Pointer to transfer buffer */
+
+
+ uint32_t xfer_len; /*!< Current transfer length */
+
+ uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
+
+}PCD_EPTypeDef;
+
+typedef USB_TypeDef PCD_TypeDef;
+
+/**
+ * @brief PCD Handle Structure definition
+ */
+typedef struct
+{
+ PCD_TypeDef *Instance; /*!< Register base address */
+ PCD_InitTypeDef Init; /*!< PCD required parameters */
+ __IO uint8_t USB_Address; /*!< USB Address */
+ PCD_EPTypeDef IN_ep[15]; /*!< IN endpoint parameters */
+ PCD_EPTypeDef OUT_ep[15]; /*!< OUT endpoint parameters */
+ HAL_LockTypeDef Lock; /*!< PCD peripheral status */
+ __IO PCD_StateTypeDef State; /*!< PCD communication state */
+ uint32_t Setup[12]; /*!< Setup packet buffer */
+ void *pData; /*!< Pointer to upper stack Handler */
+
+} PCD_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Include PCD HAL Extension module */
+#include "stm32f3xx_hal_pcd_ex.h"
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PCD_Exported_Constants PCD Exported Constants
+ * @{
+ */
+
+/** @defgroup PCD_Core_Speed PCD Core Speed
+ * @{
+ */
+#define PCD_SPEED_HIGH 0U /* Not Supported */
+#define PCD_SPEED_FULL 2U
+/**
+ * @}
+ */
+
+ /** @defgroup PCD_Core_PHY PCD Core PHY
+ * @{
+ */
+#define PCD_PHY_EMBEDDED 2U
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup PCD_Exported_Macros PCD Exported Macros
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISTR) & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISTR) = (uint16_t)(~(__INTERRUPT__))))
+
+#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_WAKEUP_EXTI_LINE
+#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_WAKEUP_EXTI_LINE)
+#define __HAL_USB_EXTI_GENERATE_SWIT(__EXTILINE__) (EXTI->SWIER |= (__EXTILINE__))
+
+#define __HAL_USB_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_WAKEUP_EXTI_LINE)
+#define __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_WAKEUP_EXTI_LINE
+
+#define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE() do {\
+ EXTI->FTSR &= ~(USB_WAKEUP_EXTI_LINE);\
+ EXTI->RTSR |= USB_WAKEUP_EXTI_LINE;\
+ } while(0U)
+
+#define __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE() do {\
+ EXTI->FTSR |= (USB_WAKEUP_EXTI_LINE);\
+ EXTI->RTSR &= ~(USB_WAKEUP_EXTI_LINE);\
+ } while(0U)
+
+#define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() do {\
+ EXTI->RTSR &= ~(USB_WAKEUP_EXTI_LINE);\
+ EXTI->FTSR &= ~(USB_WAKEUP_EXTI_LINE);\
+ EXTI->RTSR |= USB_WAKEUP_EXTI_LINE;\
+ EXTI->FTSR |= USB_WAKEUP_EXTI_LINE;\
+ } while(0U)
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PCD_Exported_Functions PCD Exported Functions
+ * @{
+ */
+
+/* Initialization/de-initialization functions ********************************/
+/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd);
+void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
+/**
+ * @}
+ */
+
+/* I/O operation functions ***************************************************/
+/* Non-Blocking mode: Interrupt */
+/** @addtogroup PCD_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
+
+void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
+/**
+ * @}
+ */
+
+/* Peripheral Control functions **********************************************/
+/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
+HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
+HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
+uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
+/**
+ * @}
+ */
+
+/* Peripheral State functions ************************************************/
+/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
+ * @{
+ */
+PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup PCD_Private_Constants PCD Private Constants
+ * @{
+ */
+/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt
+ * @{
+ */
+#define USB_WAKEUP_EXTI_LINE ((uint32_t)EXTI_IMR_MR18) /*!< External interrupt line 18 Connected to the USB FS EXTI Line */
+/**
+ * @}
+ */
+
+/** @defgroup PCD_EP0_MPS PCD EP0 MPS
+ * @{
+ */
+#define DEP0CTL_MPS_64 0U
+#define DEP0CTL_MPS_32 1U
+#define DEP0CTL_MPS_16 2U
+#define DEP0CTL_MPS_8 3U
+
+#define PCD_EP0MPS_64 DEP0CTL_MPS_64
+#define PCD_EP0MPS_32 DEP0CTL_MPS_32
+#define PCD_EP0MPS_16 DEP0CTL_MPS_16
+#define PCD_EP0MPS_08 DEP0CTL_MPS_8
+/**
+ * @}
+ */
+
+/** @defgroup PCD_EP_Type PCD EP Type
+ * @{
+ */
+#define PCD_EP_TYPE_CTRL 0U
+#define PCD_EP_TYPE_ISOC 1U
+#define PCD_EP_TYPE_BULK 2U
+#define PCD_EP_TYPE_INTR 3U
+/**
+ * @}
+ */
+
+/** @defgroup PCD_ENDP PCD ENDP
+ * @{
+ */
+#define PCD_ENDP0 ((uint8_t)0U)
+#define PCD_ENDP1 ((uint8_t)1U)
+#define PCD_ENDP2 ((uint8_t)2U)
+#define PCD_ENDP3 ((uint8_t)3U)
+#define PCD_ENDP4 ((uint8_t)4U)
+#define PCD_ENDP5 ((uint8_t)5U)
+#define PCD_ENDP6 ((uint8_t)6U)
+#define PCD_ENDP7 ((uint8_t)7U)
+/**
+ * @}
+ */
+
+/** @defgroup PCD_ENDP_Kind PCD Endpoint Kind
+ * @{
+ */
+#define PCD_SNG_BUF 0U
+#define PCD_DBL_BUF 1U
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Internal macros -----------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup PCD_Private_Macros PCD Private Macros
+ * @{
+ */
+
+/* SetENDPOINT */
+#define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue) (*((__IO uint16_t *)(((uint32_t)(&(USBx)->EP0R + (bEpNum) * 2U))))= (uint16_t)(wRegValue))
+
+/* GetENDPOINT */
+#define PCD_GET_ENDPOINT(USBx, bEpNum) (*((__IO uint16_t *)(((uint32_t)(&(USBx)->EP0R + (bEpNum) * 2U)))))
+
+
+
+/**
+ * @brief sets the type in the endpoint register(bits EP_TYPE[1:0])
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @param wType Endpoint Type.
+ * @retval None
+ */
+#define PCD_SET_EPTYPE(USBx, bEpNum,wType) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
+ ((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & ((uint32_t)(USB_EP_T_MASK))) | ((uint32_t)(wType)) )))
+
+/**
+ * @brief gets the type in the endpoint register(bits EP_TYPE[1:0])
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @retval Endpoint Type
+ */
+#define PCD_GET_EPTYPE(USBx, bEpNum) (((uint16_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_T_FIELD)
+
+
+/**
+ * @brief free buffer used from the application realizing it to the line
+ toggles bit SW_BUF in the double buffered endpoint register
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @param bDir Direction
+ * @retval None
+ */
+#define PCD_FreeUserBuffer(USBx, bEpNum, bDir)\
+{\
+ if ((bDir) == PCD_EP_DBUF_OUT)\
+ { /* OUT double buffered endpoint */\
+ PCD_TX_DTOG((USBx), (bEpNum));\
+ }\
+ else if ((bDir) == PCD_EP_DBUF_IN)\
+ { /* IN double buffered endpoint */\
+ PCD_RX_DTOG((USBx), (bEpNum));\
+ }\
+}
+
+/**
+ * @brief gets direction of the double buffered endpoint
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @retval EP_DBUF_OUT, EP_DBUF_IN,
+ * EP_DBUF_ERR if the endpoint counter not yet programmed.
+ */
+#define PCD_GET_DB_DIR(USBx, bEpNum)\
+{\
+ if ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum)) & 0xFC00U) != 0U)\
+ return(PCD_EP_DBUF_OUT);\
+ else if (((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x03FFU) != 0U)\
+ return(PCD_EP_DBUF_IN);\
+ else\
+ return(PCD_EP_DBUF_ERR);\
+}
+
+/**
+ * @brief sets the status for tx transfer (bits STAT_TX[1:0]).
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @param wState new state
+ * @retval None
+ */
+#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) { register uint16_t _wRegVal;\
+ \
+ _wRegVal = (uint32_t) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPTX_DTOGMASK);\
+ /* toggle first bit ? */ \
+ if((USB_EPTX_DTOG1 & (wState))!= 0U)\
+ { \
+ _wRegVal ^=(uint16_t) USB_EPTX_DTOG1; \
+ } \
+ /* toggle second bit ? */ \
+ if((USB_EPTX_DTOG2 & ((uint32_t)(wState)))!= 0U) \
+ { \
+ _wRegVal ^=(uint16_t) USB_EPTX_DTOG2; \
+ } \
+ PCD_SET_ENDPOINT((USBx), (bEpNum), (((uint32_t)(_wRegVal)) | USB_EP_CTR_RX|USB_EP_CTR_TX));\
+ } /* PCD_SET_EP_TX_STATUS */
+
+/**
+ * @brief sets the status for rx transfer (bits STAT_TX[1:0])
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @param wState new state
+ * @retval None
+ */
+#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) {\
+ register uint16_t _wRegVal; \
+ \
+ _wRegVal = (uint32_t) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPRX_DTOGMASK);\
+ /* toggle first bit ? */ \
+ if((USB_EPRX_DTOG1 & (wState))!= 0U) \
+ { \
+ _wRegVal ^= (uint16_t) USB_EPRX_DTOG1; \
+ } \
+ /* toggle second bit ? */ \
+ if((USB_EPRX_DTOG2 & ((uint32_t)(wState)))!= 0U) \
+ { \
+ _wRegVal ^= (uint16_t) USB_EPRX_DTOG2; \
+ } \
+ PCD_SET_ENDPOINT((USBx), (bEpNum), (((uint32_t)(_wRegVal)) | USB_EP_CTR_RX|USB_EP_CTR_TX)); \
+ } /* PCD_SET_EP_RX_STATUS */
+
+/**
+ * @brief sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @param wStaterx new state.
+ * @param wStatetx new state.
+ * @retval None
+ */
+#define PCD_SET_EP_TXRX_STATUS(USBx,bEpNum,wStaterx,wStatetx) {\
+ register uint32_t _wRegVal; \
+ \
+ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK |USB_EPTX_STAT) ;\
+ /* toggle first bit ? */ \
+ if((USB_EPRX_DTOG1 & ((wStaterx)))!= 0U) \
+ { \
+ _wRegVal ^= USB_EPRX_DTOG1; \
+ } \
+ /* toggle second bit ? */ \
+ if((USB_EPRX_DTOG2 & (wStaterx))!= 0U) \
+ { \
+ _wRegVal ^= USB_EPRX_DTOG2; \
+ } \
+ /* toggle first bit ? */ \
+ if((USB_EPTX_DTOG1 & (wStatetx))!= 0U) \
+ { \
+ _wRegVal ^= USB_EPTX_DTOG1; \
+ } \
+ /* toggle second bit ? */ \
+ if((USB_EPTX_DTOG2 & (wStatetx))!= 0U) \
+ { \
+ _wRegVal ^= USB_EPTX_DTOG2; \
+ } \
+ PCD_SET_ENDPOINT((USBx), (bEpNum), _wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX); \
+ } /* PCD_SET_EP_TXRX_STATUS */
+
+/**
+ * @brief gets the status for tx/rx transfer (bits STAT_TX[1:0]
+ * /STAT_RX[1:0])
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @retval status
+ */
+#define PCD_GET_EP_TX_STATUS(USBx, bEpNum) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPTX_STAT)
+#define PCD_GET_EP_RX_STATUS(USBx, bEpNum) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPRX_STAT)
+
+/**
+ * @brief sets directly the VALID tx/rx-status into the endpoint register
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @retval None
+ */
+#define PCD_SET_EP_TX_VALID(USBx, bEpNum) (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID))
+
+#define PCD_SET_EP_RX_VALID(USBx, bEpNum) (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID))
+
+/**
+ * @brief checks stall condition in an endpoint.
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @retval TRUE = endpoint in stall condition.
+ */
+#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) \
+ == USB_EP_TX_STALL)
+#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) \
+ == USB_EP_RX_STALL)
+
+/**
+ * @brief set & clear EP_KIND bit.
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @retval None
+ */
+#define PCD_SET_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
+ (USB_EP_CTR_RX|USB_EP_CTR_TX|((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) | USB_EP_KIND) & USB_EPREG_MASK))))
+#define PCD_CLEAR_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
+ (USB_EP_CTR_RX|USB_EP_CTR_TX|((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPKIND_MASK))))
+
+/**
+ * @brief Sets/clears directly STATUS_OUT bit in the endpoint register.
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @retval None
+ */
+#define PCD_SET_OUT_STATUS(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
+#define PCD_CLEAR_OUT_STATUS(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
+
+/**
+ * @brief Sets/clears directly EP_KIND bit in the endpoint register.
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @retval None
+ */
+#define PCD_SET_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
+#define PCD_CLEAR_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
+
+/**
+ * @brief Clears bit CTR_RX / CTR_TX in the endpoint register.
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @retval None
+ */
+#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
+ PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0x7FFFU & USB_EPREG_MASK))
+#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
+ PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0xFF7FU & USB_EPREG_MASK))
+
+/**
+ * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @retval None
+ */
+#define PCD_RX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
+ USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX | (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK)))
+#define PCD_TX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
+ USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX | (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK)))
+
+/**
+ * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register.
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @retval None
+ */
+#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) if((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_DTOG_RX) != 0)\
+ { \
+ PCD_RX_DTOG((USBx),(bEpNum));\
+ }
+#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) if((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_DTOG_TX) != 0)\
+ {\
+ PCD_TX_DTOG((USBx),(bEpNum));\
+ }
+
+/**
+ * @brief Sets address in an endpoint register.
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @param bAddr Address.
+ * @retval None
+ */
+#define PCD_SET_EP_ADDRESS(USBx, bEpNum,bAddr) PCD_SET_ENDPOINT((USBx), (bEpNum),\
+ USB_EP_CTR_RX|USB_EP_CTR_TX|(((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK) | (bAddr))
+
+/**
+ * @brief Gets address in an endpoint register.
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @retval None
+ */
+#define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
+
+/**
+ * @brief sets address of the tx/rx buffer.
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @param wAddr address to be set (must be word aligned).
+ * @retval None
+ */
+#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_TX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1U) << 1U))
+#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_RX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1U) << 1U))
+
+/**
+ * @brief Gets address of the tx/rx buffer.
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @retval address of the buffer.
+ */
+#define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum)))
+#define PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum)))
+
+/**
+ * @brief Sets counter of rx buffer with no. of blocks.
+ * @param dwReg Register
+ * @param wCount Counter.
+ * @param wNBlocks no. of Blocks.
+ * @retval None
+ */
+#define PCD_CALC_BLK32(dwReg,wCount,wNBlocks) {\
+ (wNBlocks) = (wCount) >> 5U;\
+ if(((wCount) & 0x1fU) == 0U)\
+ { \
+ (wNBlocks)--;\
+ } \
+ *pdwReg = (uint16_t)((uint16_t)((wNBlocks) << 10U) | (uint16_t)0x8000U); \
+ }/* PCD_CALC_BLK32 */
+
+
+#define PCD_CALC_BLK2(dwReg,wCount,wNBlocks) {\
+ (wNBlocks) = (wCount) >> 1U;\
+ if(((wCount) & 0x1U) != 0U)\
+ { \
+ (wNBlocks)++;\
+ } \
+ *pdwReg = (uint16_t)((wNBlocks) << 10U);\
+ }/* PCD_CALC_BLK2 */
+
+#define PCD_SET_EP_CNT_RX_REG(dwReg,wCount) {\
+ uint16_t wNBlocks;\
+ if((wCount) > 62U) \
+ { \
+ PCD_CALC_BLK32((dwReg),(wCount),wNBlocks) \
+ } \
+ else \
+ { \
+ PCD_CALC_BLK2((dwReg),(wCount),wNBlocks) \
+ } \
+ }/* PCD_SET_EP_CNT_RX_REG */
+
+#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum,wCount) {\
+ uint16_t *pdwReg = PCD_EP_TX_CNT((USBx), (bEpNum)); \
+ PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount))\
+ }
+
+/**
+ * @brief sets counter for the tx/rx buffer.
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @param wCount Counter value.
+ * @retval None
+ */
+#define PCD_SET_EP_TX_CNT(USBx, bEpNum,wCount) (*PCD_EP_TX_CNT((USBx), (bEpNum)) = (wCount))
+
+/**
+ * @brief gets counter of the tx buffer.
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @retval Counter value
+ */
+#define PCD_GET_EP_TX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ffU)
+#define PCD_GET_EP_RX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ffU)
+
+/**
+ * @brief Sets buffer 0/1 address in a double buffer endpoint.
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @param wBuf0Addr: buffer 0 address.
+ * @retval Counter value
+ */
+#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum,wBuf0Addr) (PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr)))
+#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum,wBuf1Addr) (PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr)))
+
+/**
+ * @brief Sets addresses in a double buffer endpoint.
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @param wBuf0Addr: buffer 0 address.
+ * @param wBuf1Addr = buffer 1 address.
+ * @retval None
+ */
+#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum,wBuf0Addr,wBuf1Addr) { \
+ PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr));\
+ PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr));\
+ } /* PCD_SET_EP_DBUF_ADDR */
+
+/**
+ * @brief Gets buffer 0/1 address of a double buffer endpoint.
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @retval None
+ */
+#define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum)))
+#define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum) (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum)))
+
+/**
+ * @brief Gets buffer 0/1 address of a double buffer endpoint.
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @param bDir endpoint dir EP_DBUF_OUT = OUT
+ * EP_DBUF_IN = IN
+ * @param wCount Counter value
+ * @retval None
+ */
+#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) { \
+ if((bDir) == PCD_EP_DBUF_OUT)\
+ /* OUT endpoint */ \
+ {PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum),(wCount))} \
+ else if((bDir) == PCD_EP_DBUF_IN)\
+ { \
+ *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \
+ } \
+ } /* SetEPDblBuf0Count*/
+
+#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) { \
+ if((bDir) == PCD_EP_DBUF_OUT)\
+ {/* OUT endpoint */ \
+ PCD_SET_EP_RX_CNT((USBx), (bEpNum),(wCount)) \
+ } \
+ else if((bDir) == PCD_EP_DBUF_IN)\
+ {/* IN endpoint */ \
+ *PCD_EP_RX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \
+ } \
+ } /* SetEPDblBuf1Count */
+
+#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) {\
+ PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)) \
+ PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)) \
+ } /
+
+/**
+ * @brief Gets buffer 0/1 rx/tx counter for double buffering.
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @retval None
+ */
+#define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum)))
+#define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT((USBx), (bEpNum)))
+/**
+ * @}
+ */
+
+/** @defgroup PCD_Instance_definition PCD Instance definition
+ * @{
+ */
+#define IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE
+/**
+ * @}
+ */
+
+/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+/* Peripheral Control functions ************************************************/
+HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
+HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
+HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
+uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_ActiveRemoteWakeup(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DeActiveRemoteWakeup(PCD_HandleTypeDef *hpcd);
+/**
+ * @}
+ */
+
+/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
+ * @{
+ */
+/* Peripheral State functions **************************************************/
+PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
+/**
+ * @}
+ */
+
+/** @addtogroup PCDEx_Private_Functions PCD Extended Private Functions
+ * @{
+ */
+void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
+void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F302xE || STM32F303xE || */
+ /* STM32F302xC || STM32F303xC || */
+ /* STM32F302x8 || */
+ /* STM32F373xC */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F3xx_HAL_PCD_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_hal_pcd_ex.h b/Inc/stm32f3xx_hal_pcd_ex.h
new file mode 100644
index 0000000..78bd5ae
--- /dev/null
+++ b/Inc/stm32f3xx_hal_pcd_ex.h
@@ -0,0 +1,152 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_pcd_ex.h
+ * @author MCD Application Team
+ * @brief Header file of PCD HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_PCD_EX_H
+#define __STM32F3xx_HAL_PCD_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || \
+ defined(STM32F302x8) || \
+ defined(STM32F373xC)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup PCDEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup PCDEx_Exported_Macros PCD Extended Exported Macros
+ * @{
+ */
+/**
+ * @brief Gets address in an endpoint register.
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @retval None
+ */
+
+#if defined(STM32F302xC) || defined(STM32F303xC) || \
+ defined(STM32F373xC)
+
+#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8)*2+ ((uint32_t)(USBx) + 0x400U)))))
+#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+2)*2+ ((uint32_t)(USBx) + 0x400U)))))
+#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+4)*2+ ((uint32_t)(USBx) + 0x400U)))))
+#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+6)*2+ ((uint32_t)(USBx) + 0x400U)))))
+
+
+#define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) {\
+ uint16_t *pdwReg =PCD_EP_RX_CNT((USBx),(bEpNum)); \
+ PCD_SET_EP_CNT_RX_REG((pdwReg), (wCount))\
+ }
+
+#endif /* STM32F302xC || STM32F303xC || */
+ /* STM32F373xC */
+
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || \
+ defined(STM32F302x8)
+
+#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8)+ ((uint32_t)(USBx) + 0x400U)))))
+#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+2)+ ((uint32_t)(USBx) + 0x400U)))))
+#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+4)+ ((uint32_t)(USBx) + 0x400U)))))
+#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+6)+ ((uint32_t)(USBx) + 0x400U)))))
+
+#define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) {\
+ uint16_t *pdwReg = PCD_EP_RX_CNT((USBx), (bEpNum));\
+ PCD_SET_EP_CNT_RX_REG((pdwReg), (wCount))\
+ }
+
+#endif /* STM32F302xE || STM32F303xE || */
+ /* STM32F302x8 */
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
+ * @{
+ */
+/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
+ uint16_t ep_addr,
+ uint16_t ep_kind,
+ uint32_t pmaadress);
+
+void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F302xE || STM32F303xE || */
+ /* STM32F302xC || STM32F303xC || */
+ /* STM32F302x8 || */
+ /* STM32F373xC */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F3xx_HAL_PCD_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_hal_pwr.h b/Inc/stm32f3xx_hal_pwr.h
new file mode 100644
index 0000000..91c10a3
--- /dev/null
+++ b/Inc/stm32f3xx_hal_pwr.h
@@ -0,0 +1,235 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_pwr.h
+ * @author MCD Application Team
+ * @brief Header file of PWR HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_PWR_H
+#define __STM32F3xx_HAL_PWR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup PWR PWR
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PWR_Exported_Constants PWR Exported Constants
+ * @{
+ */
+
+/** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
+ * @{
+ */
+
+#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1) /*!< Wakeup pin 1U */
+#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2) /*!< Wakeup pin 2U */
+#define PWR_WAKEUP_PIN3 ((uint32_t)PWR_CSR_EWUP3) /*!< Wakeup pin 3U */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in STOP mode
+ * @{
+ */
+#define PWR_MAINREGULATOR_ON (0x00000000U) /*!< Voltage regulator on during STOP mode */
+#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS /*!< Voltage regulator in low-power mode during STOP mode */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
+ * @{
+ */
+#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U) /*!< Wait For Interruption instruction to enter SLEEP mode */
+#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U) /*!< Wait For Event instruction to enter SLEEP mode */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
+ * @{
+ */
+#define PWR_STOPENTRY_WFI ((uint8_t)0x01U) /*!< Wait For Interruption instruction to enter STOP mode */
+#define PWR_STOPENTRY_WFE ((uint8_t)0x02U) /*!< Wait For Event instruction to enter STOP mode */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Flag PWR Flag
+ * @{
+ */
+#define PWR_FLAG_WU PWR_CSR_WUF /*!< Wakeup event from wakeup pin or RTC alarm */
+#define PWR_FLAG_SB PWR_CSR_SBF /*!< Standby flag */
+#define PWR_FLAG_PVDO PWR_CSR_PVDO /*!< Power Voltage Detector output flag */
+#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF /*!< VREFINT reference voltage ready */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup PWR_Exported_Macro PWR Exported Macro
+ * @{
+ */
+
+/** @brief Check PWR flag is set or not.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
+ * was received from the WKUP pin or from the RTC alarm (Alarm A
+ * or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
+ * An additional wakeup event is detected if the WKUP pin is enabled
+ * (by setting the EWUP bit) when the WKUP pin level is already high.
+ * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
+ * resumed from StandBy mode.
+ * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
+ * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
+ * For this reason, this bit is equal to 0 after Standby or reset
+ * until the PVDE bit is set.
+ * @arg PWR_FLAG_VREFINTRDY: This flag indicates that the internal reference
+ * voltage VREFINT is ready.
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the PWR's pending flags.
+ * @param __FLAG__ specifies the flag to clear.
+ * This parameter can be one of the following values:
+ * @arg PWR_FLAG_WU: Wake Up flag
+ * @arg PWR_FLAG_SB: StandBy flag
+ */
+#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2U)
+
+/**
+ * @}
+ */
+
+/* Private macros --------------------------------------------------------*/
+/** @addtogroup PWR_Private_Macros PWR Private Macros
+ * @{
+ */
+
+#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
+ ((PIN) == PWR_WAKEUP_PIN2) || \
+ ((PIN) == PWR_WAKEUP_PIN3))
+
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
+ ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
+
+#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
+
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
+
+/**
+ * @}
+ */
+
+/* Include PWR HAL Extended module */
+#include "stm32f3xx_hal_pwr_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup PWR_Exported_Functions PWR Exported Functions
+ * @{
+ */
+
+/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions *****************************/
+void HAL_PWR_DeInit(void);
+
+/**
+ * @}
+ */
+
+/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
+ * @{
+ */
+
+/* Peripheral Control functions **********************************************/
+void HAL_PWR_EnableBkUpAccess(void);
+void HAL_PWR_DisableBkUpAccess(void);
+
+/* WakeUp pins configuration functions ****************************************/
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
+
+/* Low Power modes configuration functions ************************************/
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
+void HAL_PWR_EnterSTANDBYMode(void);
+
+void HAL_PWR_EnableSleepOnExit(void);
+void HAL_PWR_DisableSleepOnExit(void);
+void HAL_PWR_EnableSEVOnPend(void);
+void HAL_PWR_DisableSEVOnPend(void);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F3xx_HAL_PWR_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_hal_pwr_ex.h b/Inc/stm32f3xx_hal_pwr_ex.h
new file mode 100644
index 0000000..e892e7b
--- /dev/null
+++ b/Inc/stm32f3xx_hal_pwr_ex.h
@@ -0,0 +1,338 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_pwr_ex.h
+ * @author MCD Application Team
+ * @brief Header file of PWR HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_PWR_EX_H
+#define __STM32F3xx_HAL_PWR_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup PWREx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup PWREx_Exported_Types PWR Extended Exported Types
+ * @{
+ */
+#if defined(STM32F302xE) || defined(STM32F303xE) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || \
+ defined(STM32F373xC)
+/**
+ * @brief PWR PVD configuration structure definition
+ */
+typedef struct
+{
+ uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level
+ This parameter can be a value of @ref PWREx_PVD_detection_level */
+
+ uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
+ This parameter can be a value of @ref PWREx_PVD_Mode */
+}PWR_PVDTypeDef;
+#endif /* STM32F302xE || STM32F303xE || */
+ /* STM32F302xC || STM32F303xC || */
+ /* STM32F303x8 || STM32F334x8 || */
+ /* STM32F301x8 || STM32F302x8 || */
+ /* STM32F373xC */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants
+ * @{
+ */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || \
+ defined(STM32F373xC)
+
+/** @defgroup PWREx_PVD_detection_level PWR Extended PVD detection level
+ * @{
+ */
+#define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0 /*!< PVD threshold around 2.2 V */
+#define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1 /*!< PVD threshold around 2.3 V */
+#define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2 /*!< PVD threshold around 2.4 V */
+#define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3 /*!< PVD threshold around 2.5 V */
+#define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4 /*!< PVD threshold around 2.6 V */
+#define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5 /*!< PVD threshold around 2.7 V */
+#define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6 /*!< PVD threshold around 2.8 V */
+#define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7 /*!< PVD threshold around 2.9 V */
+/**
+ * @}
+ */
+
+/** @defgroup PWREx_PVD_Mode PWR Extended PVD Mode
+ * @{
+ */
+#define PWR_PVD_MODE_NORMAL (0x00000000U) /*!< Basic mode is used */
+#define PWR_PVD_MODE_IT_RISING (0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */
+#define PWR_PVD_MODE_IT_FALLING (0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */
+#define PWR_PVD_MODE_IT_RISING_FALLING (0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING (0x00020001U) /*!< Event Mode with Rising edge trigger detection */
+#define PWR_PVD_MODE_EVENT_FALLING (0x00020002U) /*!< Event Mode with Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */
+/**
+ * @}
+ */
+
+#define PWR_EXTI_LINE_PVD EXTI_IMR_MR16 /*!< External interrupt line 16 Connected to the PVD EXTI Line */
+
+#endif /* STM32F302xE || STM32F303xE || */
+ /* STM32F302xC || STM32F303xC || */
+ /* STM32F303x8 || STM32F334x8 || */
+ /* STM32F301x8 || STM32F302x8 || */
+ /* STM32F373xC */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/** @defgroup PWREx_SDADC_ANALOGx PWR Extended SDADC ANALOGx
+ * @{
+ */
+#define PWR_SDADC_ANALOG1 ((uint32_t)PWR_CR_ENSD1) /*!< Enable SDADC1 */
+#define PWR_SDADC_ANALOG2 ((uint32_t)PWR_CR_ENSD2) /*!< Enable SDADC2 */
+#define PWR_SDADC_ANALOG3 ((uint32_t)PWR_CR_ENSD3) /*!< Enable SDADC3 */
+/**
+ * @}
+ */
+#endif /* STM32F373xC || STM32F378xx */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros
+ * @{
+ */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || \
+ defined(STM32F373xC)
+
+/**
+ * @brief Enable interrupt on PVD Exti Line 16.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD))
+
+/**
+ * @brief Disable interrupt on PVD Exti Line 16.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))
+
+/**
+ * @brief Generate a Software interrupt on selected EXTI line.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))
+
+/**
+ * @brief Enable event on PVD Exti Line 16.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD))
+
+/**
+ * @brief Disable event on PVD Exti Line 16.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))
+
+/**
+ * @brief Disable the PVD Extended Interrupt Rising Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief Disable the PVD Extended Interrupt Falling Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
+ * @retval None
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
+
+/**
+ * @brief PVD EXTI line configuration: set falling edge trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief PVD EXTI line configuration: set rising edge trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() EXTI->RTSR |= (PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief Enable the PVD Extended Interrupt Rising & Falling Trigger.
+ * @retval None
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
+
+/**
+ * @brief Check whether the specified PVD EXTI interrupt flag is set or not.
+ * @retval EXTI PVD Line Status.
+ */
+#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
+
+/**
+ * @brief Clear the PVD EXTI flag.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
+
+#endif /* STM32F302xE || STM32F303xE || */
+ /* STM32F302xC || STM32F303xC || */
+ /* STM32F303x8 || STM32F334x8 || */
+ /* STM32F301x8 || STM32F302x8 || */
+ /* STM32F373xC */
+
+/**
+ * @}
+ */
+
+/* Private macros --------------------------------------------------------*/
+/** @addtogroup PWREx_Private_Macros PWR Extended Private Macros
+ * @{
+ */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || \
+ defined(STM32F373xC)
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
+ ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
+ ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
+ ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
+
+#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
+ ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
+ ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
+ ((MODE) == PWR_PVD_MODE_NORMAL))
+#endif /* STM32F302xE || STM32F303xE || */
+ /* STM32F302xC || STM32F303xC || */
+ /* STM32F303x8 || STM32F334x8 || */
+ /* STM32F301x8 || STM32F302x8 || */
+ /* STM32F373xC */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#define IS_PWR_SDADC_ANALOG(SDADC) (((SDADC) == PWR_SDADC_ANALOG1) || \
+ ((SDADC) == PWR_SDADC_ANALOG2) || \
+ ((SDADC) == PWR_SDADC_ANALOG3))
+#endif /* STM32F373xC || STM32F378xx */
+
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions
+ * @{
+ */
+
+/** @addtogroup PWREx_Exported_Functions_Group1 Peripheral Extended Control Functions
+ * @{
+ */
+/* Peripheral Extended control functions **************************************/
+#if defined(STM32F302xE) || defined(STM32F303xE) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || \
+ defined(STM32F373xC)
+void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
+void HAL_PWR_EnablePVD(void);
+void HAL_PWR_DisablePVD(void);
+void HAL_PWR_PVD_IRQHandler(void);
+void HAL_PWR_PVDCallback(void);
+#endif /* STM32F302xE || STM32F303xE || */
+ /* STM32F302xC || STM32F303xC || */
+ /* STM32F303x8 || STM32F334x8 || */
+ /* STM32F301x8 || STM32F302x8 || */
+ /* STM32F373xC */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+void HAL_PWREx_EnableSDADC(uint32_t Analogx);
+void HAL_PWREx_DisableSDADC(uint32_t Analogx);
+#endif /* STM32F373xC || STM32F378xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_PWR_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_hal_rcc.h b/Inc/stm32f3xx_hal_rcc.h
new file mode 100644
index 0000000..749b974
--- /dev/null
+++ b/Inc/stm32f3xx_hal_rcc.h
@@ -0,0 +1,1756 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_rcc.h
+ * @author MCD Application Team
+ * @brief Header file of RCC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_RCC_H
+#define __STM32F3xx_HAL_RCC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup RCC
+ * @{
+ */
+
+/** @addtogroup RCC_Private_Constants
+ * @{
+ */
+
+/** @defgroup RCC_Timeout RCC Timeout
+ * @{
+ */
+
+/* Disable Backup domain write protection state change timeout */
+#define RCC_DBP_TIMEOUT_VALUE (100U) /* 100 ms */
+/* LSE state change timeout */
+#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
+#define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */
+#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
+#define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
+#define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
+#define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Register_Offset Register offsets
+ * @{
+ */
+#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
+#define RCC_CR_OFFSET 0x00
+#define RCC_CFGR_OFFSET 0x04
+#define RCC_CIR_OFFSET 0x08
+#define RCC_BDCR_OFFSET 0x20
+#define RCC_CSR_OFFSET 0x24
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion
+ * @brief RCC registers bit address in the alias region
+ * @{
+ */
+#define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET)
+#define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET)
+#define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET)
+#define RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET)
+#define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET)
+
+/* --- CR Register ---*/
+/* Alias word address of HSION bit */
+#define RCC_HSION_BIT_NUMBER POSITION_VAL(RCC_CR_HSION)
+#define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U)))
+/* Alias word address of HSEON bit */
+#define RCC_HSEON_BIT_NUMBER POSITION_VAL(RCC_CR_HSEON)
+#define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U)))
+/* Alias word address of CSSON bit */
+#define RCC_CSSON_BIT_NUMBER POSITION_VAL(RCC_CR_CSSON)
+#define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U)))
+/* Alias word address of PLLON bit */
+#define RCC_PLLON_BIT_NUMBER POSITION_VAL(RCC_CR_PLLON)
+#define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U)))
+
+/* --- CSR Register ---*/
+/* Alias word address of LSION bit */
+#define RCC_LSION_BIT_NUMBER POSITION_VAL(RCC_CSR_LSION)
+#define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U)))
+
+/* Alias word address of RMVF bit */
+#define RCC_RMVF_BIT_NUMBER POSITION_VAL(RCC_CSR_RMVF)
+#define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U)))
+
+/* --- BDCR Registers ---*/
+/* Alias word address of LSEON bit */
+#define RCC_LSEON_BIT_NUMBER POSITION_VAL(RCC_BDCR_LSEON)
+#define RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U)))
+
+/* Alias word address of LSEON bit */
+#define RCC_LSEBYP_BIT_NUMBER POSITION_VAL(RCC_BDCR_LSEBYP)
+#define RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U)))
+
+/* Alias word address of RTCEN bit */
+#define RCC_RTCEN_BIT_NUMBER POSITION_VAL(RCC_BDCR_RTCEN)
+#define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U)))
+
+/* Alias word address of BDRST bit */
+#define RCC_BDRST_BIT_NUMBER POSITION_VAL(RCC_BDCR_BDRST)
+#define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_BDRST_BIT_NUMBER * 4U)))
+
+/**
+ * @}
+ */
+
+/* CR register byte 2 (Bits[23:16]) base address */
+#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))
+
+/* CIR register byte 1 (Bits[15:8]) base address */
+#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))
+
+/* CIR register byte 2 (Bits[23:16]) base address */
+#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))
+
+/* Defines used for Flags */
+#define CR_REG_INDEX ((uint8_t)1U)
+#define BDCR_REG_INDEX ((uint8_t)2U)
+#define CSR_REG_INDEX ((uint8_t)3U)
+#define CFGR_REG_INDEX ((uint8_t)4U)
+
+#define RCC_FLAG_MASK ((uint8_t)0x1FU)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Private_Macros
+ * @{
+ */
+#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) || \
+ ((__SOURCE__) == RCC_PLLSOURCE_HSE))
+#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
+ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
+ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
+ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
+ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
+#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
+ ((__HSE__) == RCC_HSE_BYPASS))
+#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
+ ((__LSE__) == RCC_LSE_BYPASS))
+#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
+#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)
+#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
+#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \
+ ((__PLL__) == RCC_PLL_ON))
+#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
+#define IS_RCC_PREDIV(__PREDIV__) (((__PREDIV__) == RCC_PREDIV_DIV1) || ((__PREDIV__) == RCC_PREDIV_DIV2) || \
+ ((__PREDIV__) == RCC_PREDIV_DIV3) || ((__PREDIV__) == RCC_PREDIV_DIV4) || \
+ ((__PREDIV__) == RCC_PREDIV_DIV5) || ((__PREDIV__) == RCC_PREDIV_DIV6) || \
+ ((__PREDIV__) == RCC_PREDIV_DIV7) || ((__PREDIV__) == RCC_PREDIV_DIV8) || \
+ ((__PREDIV__) == RCC_PREDIV_DIV9) || ((__PREDIV__) == RCC_PREDIV_DIV10) || \
+ ((__PREDIV__) == RCC_PREDIV_DIV11) || ((__PREDIV__) == RCC_PREDIV_DIV12) || \
+ ((__PREDIV__) == RCC_PREDIV_DIV13) || ((__PREDIV__) == RCC_PREDIV_DIV14) || \
+ ((__PREDIV__) == RCC_PREDIV_DIV15) || ((__PREDIV__) == RCC_PREDIV_DIV16))
+#else
+#define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLL_DIV2) || \
+ ((__DIV__) == RCC_PLL_DIV3) || ((__DIV__) == RCC_PLL_DIV4))
+#endif
+#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
+#define IS_RCC_HSE_PREDIV(DIV) (((DIV) == RCC_HSE_PREDIV_DIV1) || ((DIV) == RCC_HSE_PREDIV_DIV2) || \
+ ((DIV) == RCC_HSE_PREDIV_DIV3) || ((DIV) == RCC_HSE_PREDIV_DIV4) || \
+ ((DIV) == RCC_HSE_PREDIV_DIV5) || ((DIV) == RCC_HSE_PREDIV_DIV6) || \
+ ((DIV) == RCC_HSE_PREDIV_DIV7) || ((DIV) == RCC_HSE_PREDIV_DIV8) || \
+ ((DIV) == RCC_HSE_PREDIV_DIV9) || ((DIV) == RCC_HSE_PREDIV_DIV10) || \
+ ((DIV) == RCC_HSE_PREDIV_DIV11) || ((DIV) == RCC_HSE_PREDIV_DIV12) || \
+ ((DIV) == RCC_HSE_PREDIV_DIV13) || ((DIV) == RCC_HSE_PREDIV_DIV14) || \
+ ((DIV) == RCC_HSE_PREDIV_DIV15) || ((DIV) == RCC_HSE_PREDIV_DIV16))
+#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
+
+#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) || ((__MUL__) == RCC_PLL_MUL3) || \
+ ((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \
+ ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \
+ ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \
+ ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || \
+ ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) || \
+ ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || \
+ ((__MUL__) == RCC_PLL_MUL16))
+#define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \
+ (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \
+ (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \
+ (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2))
+#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
+ ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
+ ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
+#define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
+ ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
+ ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
+#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
+ ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
+ ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
+ ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
+ ((__HCLK__) == RCC_SYSCLK_DIV512))
+#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
+ ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
+ ((__PCLK__) == RCC_HCLK_DIV16))
+#define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO)
+#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
+#if defined(RCC_CFGR3_USART2SW)
+#define IS_RCC_USART2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \
+ ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \
+ ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
+#endif /* RCC_CFGR3_USART2SW */
+#if defined(RCC_CFGR3_USART3SW)
+#define IS_RCC_USART3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \
+ ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \
+ ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI))
+#endif /* RCC_CFGR3_USART3SW */
+#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI) || \
+ ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK))
+
+/**
+ * @}
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Types RCC Exported Types
+ * @{
+ */
+
+/**
+ * @brief RCC PLL configuration structure definition
+ */
+typedef struct
+{
+ uint32_t PLLState; /*!< PLLState: The new state of the PLL.
+ This parameter can be a value of @ref RCC_PLL_Config */
+
+ uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
+ This parameter must be a value of @ref RCC_PLL_Clock_Source */
+
+ uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
+ This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/
+
+#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
+ uint32_t PREDIV; /*!< PREDIV: Predivision factor for PLL VCO input clock
+ This parameter must be a value of @ref RCC_PLL_Prediv_Factor */
+
+#endif
+} RCC_PLLInitTypeDef;
+
+/**
+ * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
+ */
+typedef struct
+{
+ uint32_t OscillatorType; /*!< The oscillators to be configured.
+ This parameter can be a value of @ref RCC_Oscillator_Type */
+
+ uint32_t HSEState; /*!< The new state of the HSE.
+ This parameter can be a value of @ref RCC_HSE_Config */
+
+#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
+ uint32_t HSEPredivValue; /*!< The HSE predivision factor value.
+ This parameter can be a value of @ref RCC_PLL_HSE_Prediv_Factor */
+
+#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
+ uint32_t LSEState; /*!< The new state of the LSE.
+ This parameter can be a value of @ref RCC_LSE_Config */
+
+ uint32_t HSIState; /*!< The new state of the HSI.
+ This parameter can be a value of @ref RCC_HSI_Config */
+
+ uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU */
+
+ uint32_t LSIState; /*!< The new state of the LSI.
+ This parameter can be a value of @ref RCC_LSI_Config */
+
+ RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
+
+} RCC_OscInitTypeDef;
+
+/**
+ * @brief RCC System, AHB and APB busses clock configuration structure definition
+ */
+typedef struct
+{
+ uint32_t ClockType; /*!< The clock to be configured.
+ This parameter can be a value of @ref RCC_System_Clock_Type */
+
+ uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
+ This parameter can be a value of @ref RCC_System_Clock_Source */
+
+ uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
+ This parameter can be a value of @ref RCC_AHB_Clock_Source */
+
+ uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
+ This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
+
+ uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
+ This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
+} RCC_ClkInitTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCC_Exported_Constants RCC Exported Constants
+ * @{
+ */
+
+/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
+ * @{
+ */
+
+#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
+#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV /*!< HSI clock selected as PLL entry clock source */
+#endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */
+#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
+#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2 /*!< HSI clock divided by 2 selected as PLL entry clock source */
+#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
+#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< HSE clock selected as PLL entry clock source */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Oscillator_Type Oscillator Type
+ * @{
+ */
+#define RCC_OSCILLATORTYPE_NONE (0x00000000U)
+#define RCC_OSCILLATORTYPE_HSE (0x00000001U)
+#define RCC_OSCILLATORTYPE_HSI (0x00000002U)
+#define RCC_OSCILLATORTYPE_LSE (0x00000004U)
+#define RCC_OSCILLATORTYPE_LSI (0x00000008U)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_HSE_Config HSE Config
+ * @{
+ */
+#define RCC_HSE_OFF (0x00000000U) /*!< HSE clock deactivation */
+#define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */
+#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LSE_Config LSE Config
+ * @{
+ */
+#define RCC_LSE_OFF (0x00000000U) /*!< LSE clock deactivation */
+#define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */
+#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_HSI_Config HSI Config
+ * @{
+ */
+#define RCC_HSI_OFF (0x00000000U) /*!< HSI clock deactivation */
+#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */
+
+#define RCC_HSICALIBRATION_DEFAULT (0x10U) /* Default HSI calibration trimming value */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LSI_Config LSI Config
+ * @{
+ */
+#define RCC_LSI_OFF (0x00000000U) /*!< LSI clock deactivation */
+#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL_Config PLL Config
+ * @{
+ */
+#define RCC_PLL_NONE (0x00000000U) /*!< PLL is not configured */
+#define RCC_PLL_OFF (0x00000001U) /*!< PLL deactivation */
+#define RCC_PLL_ON (0x00000002U) /*!< PLL activation */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_System_Clock_Type System Clock Type
+ * @{
+ */
+#define RCC_CLOCKTYPE_SYSCLK (0x00000001U) /*!< SYSCLK to configure */
+#define RCC_CLOCKTYPE_HCLK (0x00000002U) /*!< HCLK to configure */
+#define RCC_CLOCKTYPE_PCLK1 (0x00000004U) /*!< PCLK1 to configure */
+#define RCC_CLOCKTYPE_PCLK2 (0x00000008U) /*!< PCLK2 to configure */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_System_Clock_Source System Clock Source
+ * @{
+ */
+#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selected as system clock */
+#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selected as system clock */
+#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selected as system clock */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
+ * @{
+ */
+#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
+ * @{
+ */
+#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
+#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
+#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
+#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
+#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
+#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
+#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
+#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
+#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
+ * @{
+ */
+#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
+#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
+#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
+#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
+#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
+ * @{
+ */
+#define RCC_RTCCLKSOURCE_NO_CLK RCC_BDCR_RTCSEL_NOCLOCK /*!< No clock */
+#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */
+#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL_HSE /*!< HSE oscillator clock divided by 32 used as RTC clock */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor
+ * @{
+ */
+#define RCC_PLL_MUL2 RCC_CFGR_PLLMUL2
+#define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3
+#define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4
+#define RCC_PLL_MUL5 RCC_CFGR_PLLMUL5
+#define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6
+#define RCC_PLL_MUL7 RCC_CFGR_PLLMUL7
+#define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8
+#define RCC_PLL_MUL9 RCC_CFGR_PLLMUL9
+#define RCC_PLL_MUL10 RCC_CFGR_PLLMUL10
+#define RCC_PLL_MUL11 RCC_CFGR_PLLMUL11
+#define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12
+#define RCC_PLL_MUL13 RCC_CFGR_PLLMUL13
+#define RCC_PLL_MUL14 RCC_CFGR_PLLMUL14
+#define RCC_PLL_MUL15 RCC_CFGR_PLLMUL15
+#define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16
+
+/**
+ * @}
+ */
+
+#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
+/** @defgroup RCC_PLL_Prediv_Factor RCC PLL Prediv Factor
+ * @{
+ */
+
+#define RCC_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1
+#define RCC_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2
+#define RCC_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3
+#define RCC_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4
+#define RCC_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5
+#define RCC_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6
+#define RCC_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7
+#define RCC_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8
+#define RCC_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9
+#define RCC_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10
+#define RCC_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11
+#define RCC_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12
+#define RCC_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13
+#define RCC_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14
+#define RCC_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
+#define RCC_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16
+
+/**
+ * @}
+ */
+
+#endif
+#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
+/** @defgroup RCC_PLL_HSE_Prediv_Factor RCC PLL HSE Prediv Factor
+ * @{
+ */
+
+#define RCC_HSE_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1
+#define RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2
+#define RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3
+#define RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4
+#define RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5
+#define RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6
+#define RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7
+#define RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8
+#define RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9
+#define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10
+#define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11
+#define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12
+#define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13
+#define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14
+#define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
+#define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16
+
+/**
+ * @}
+ */
+#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
+
+#if defined(RCC_CFGR3_USART2SW)
+/** @defgroup RCC_USART2_Clock_Source RCC USART2 Clock Source
+ * @{
+ */
+#define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK
+#define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK
+#define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE
+#define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI
+
+/**
+ * @}
+ */
+#endif /* RCC_CFGR3_USART2SW */
+
+#if defined(RCC_CFGR3_USART3SW)
+/** @defgroup RCC_USART3_Clock_Source RCC USART3 Clock Source
+ * @{
+ */
+#define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK
+#define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK
+#define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE
+#define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI
+
+/**
+ * @}
+ */
+#endif /* RCC_CFGR3_USART3SW */
+
+/** @defgroup RCC_I2C1_Clock_Source RCC I2C1 Clock Source
+ * @{
+ */
+#define RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI
+#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK
+
+/**
+ * @}
+ */
+/** @defgroup RCC_MCO_Index MCO Index
+ * @{
+ */
+#define RCC_MCO1 (0x00000000U)
+#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Interrupt Interrupts
+ * @{
+ */
+#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */
+#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */
+#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */
+#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */
+#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */
+#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Flag Flags
+ * Elements values convention: XXXYYYYYb
+ * - YYYYY : Flag position in the register
+ * - XXX : Register index
+ * - 001: CR register
+ * - 010: BDCR register
+ * - 011: CSR register
+ * - 100: CFGR register
+ * @{
+ */
+/* Flags in the CR register */
+#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSIRDY))) /*!< Internal High Speed clock ready flag */
+#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSERDY))) /*!< External High Speed clock ready flag */
+#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLRDY))) /*!< PLL clock ready flag */
+
+/* Flags in the CSR register */
+#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LSIRDY))) /*!< Internal Low Speed oscillator Ready */
+#if defined(RCC_CSR_V18PWRRSTF)
+#define RCC_FLAG_V18PWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_V18PWRRSTF)))
+#endif
+#define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_OBLRSTF))) /*!< Options bytes loading reset flag */
+#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PINRSTF))) /*!< PIN reset flag */
+#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PORRSTF))) /*!< POR/PDR reset flag */
+#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_SFTRSTF))) /*!< Software Reset flag */
+#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_IWDGRSTF))) /*!< Independent Watchdog reset flag */
+#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_WWDGRSTF))) /*!< Window watchdog reset flag */
+#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LPWRRSTF))) /*!< Low-Power reset flag */
+
+/* Flags in the BDCR register */
+#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) | POSITION_VAL(RCC_BDCR_LSERDY))) /*!< External Low Speed oscillator Ready */
+
+/* Flags in the CFGR register */
+#if defined(RCC_CFGR_MCOF)
+#define RCC_FLAG_MCO ((uint8_t)((CFGR_REG_INDEX << 5U) | POSITION_VAL(RCC_CFGR_MCOF))) /*!< Microcontroller Clock Output Flag */
+#endif /* RCC_CFGR_MCOF */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Macros RCC Exported Macros
+ * @{
+ */
+
+/** @defgroup RCC_AHB_Clock_Enable_Disable RCC AHB Clock Enable Disable
+ * @brief Enable or disable the AHB peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_CRC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_SRAM_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_FLITF_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TSC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+
+#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
+#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
+#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN))
+#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
+#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))
+#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
+#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
+#define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
+#define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
+#define __HAL_RCC_TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_Clock_Enable_Disable RCC APB1 Clock Enable Disable
+ * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_USART2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_USART3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_PWR_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_DAC1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC1EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+
+#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
+#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
+#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
+#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
+#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
+#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
+#define __HAL_RCC_DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC1EN))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB2_Clock_Enable_Disable RCC APB2 Clock Enable Disable
+ * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM15_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM16_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM17_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_USART1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+
+#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
+#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
+#define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
+#define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
+#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the AHB peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) != RESET)
+#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) != RESET)
+#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) != RESET)
+#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) != RESET)
+#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) != RESET)
+#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)
+#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)
+#define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET)
+#define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)
+#define __HAL_RCC_TSC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) != RESET)
+
+#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) == RESET)
+#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) == RESET)
+#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) == RESET)
+#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) == RESET)
+#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) == RESET)
+#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)
+#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)
+#define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET)
+#define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)
+#define __HAL_RCC_TSC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) == RESET)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the APB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
+#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
+#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
+#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
+#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
+#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
+#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
+#define __HAL_RCC_DAC1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) != RESET)
+
+#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
+#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
+#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
+#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
+#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
+#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
+#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
+#define __HAL_RCC_DAC1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) == RESET)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
+ * @brief EGet the enable or disable status of the APB2 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
+#define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET)
+#define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET)
+#define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET)
+#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
+
+#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
+#define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET)
+#define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET)
+#define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET)
+#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB_Force_Release_Reset RCC AHB Force Release Reset
+ * @brief Force or release AHB peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST))
+#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST))
+#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST))
+#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST))
+#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST))
+#define __HAL_RCC_TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST))
+
+#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00000000U)
+#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))
+#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))
+#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))
+#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
+#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST))
+#define __HAL_RCC_TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_Force_Release_Reset RCC APB1 Force Release Reset
+ * @brief Force or release APB1 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
+#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
+#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
+#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
+#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
+#define __HAL_RCC_DAC1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC1RST))
+
+#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00000000U)
+#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
+#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
+#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
+#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
+#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
+#define __HAL_RCC_DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC1RST))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB2_Force_Release_Reset RCC APB2 Force Release Reset
+ * @brief Force or release APB2 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
+#define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST))
+#define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST))
+#define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST))
+#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
+
+#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00000000U)
+#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
+#define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
+#define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
+#define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
+#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_HSI_Configuration HSI Configuration
+ * @{
+ */
+
+/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
+ * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
+ * It is used (enabled by hardware) as system clock source after startup
+ * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
+ * of the HSE used directly or indirectly as system clock (if the Clock
+ * Security System CSS is enabled).
+ * @note HSI can not be stopped if it is used as system clock source. In this case,
+ * you have to select another source of the system clock then stop the HSI.
+ * @note After enabling the HSI, the application software should wait on HSIRDY
+ * flag to be set indicating that HSI clock is stable and can be used as
+ * system clock source.
+ * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
+ * clock cycles.
+ */
+#define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
+#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
+
+/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
+ * @note The calibration is used to compensate for the variations in voltage
+ * and temperature that influence the frequency of the internal HSI RC.
+ * @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value.
+ * (default is RCC_HSICALIBRATION_DEFAULT).
+ * This parameter must be a number between 0 and 0x1F.
+ */
+#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
+ (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << POSITION_VAL(RCC_CR_HSITRIM)))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LSI_Configuration LSI Configuration
+ * @{
+ */
+
+/** @brief Macro to enable the Internal Low Speed oscillator (LSI).
+ * @note After enabling the LSI, the application software should wait on
+ * LSIRDY flag to be set indicating that LSI clock is stable and can
+ * be used to clock the IWDG and/or the RTC.
+ */
+#define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
+
+/** @brief Macro to disable the Internal Low Speed oscillator (LSI).
+ * @note LSI can not be disabled if the IWDG is running.
+ * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
+ * clock cycles.
+ */
+#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_HSE_Configuration HSE Configuration
+ * @{
+ */
+
+/**
+ * @brief Macro to configure the External High Speed oscillator (HSE).
+ * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
+ * supported by this macro. User should request a transition to HSE Off
+ * first and then HSE On or HSE Bypass.
+ * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
+ * software should wait on HSERDY flag to be set indicating that HSE clock
+ * is stable and can be used to clock the PLL and/or system clock.
+ * @note HSE state can not be changed if it is used directly or through the
+ * PLL as system clock. In this case, you have to select another source
+ * of the system clock then change the HSE state (ex. disable it).
+ * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
+ * @note This function reset the CSSON bit, so if the clock security system(CSS)
+ * was previously enabled you have to enable it again after calling this
+ * function.
+ * @param __STATE__ specifies the new state of the HSE.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after
+ * 6 HSE oscillator clock cycles.
+ * @arg @ref RCC_HSE_ON turn ON the HSE oscillator
+ * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock
+ */
+#define __HAL_RCC_HSE_CONFIG(__STATE__) \
+ do{ \
+ if ((__STATE__) == RCC_HSE_ON) \
+ { \
+ SET_BIT(RCC->CR, RCC_CR_HSEON); \
+ } \
+ else if ((__STATE__) == RCC_HSE_OFF) \
+ { \
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
+ } \
+ else if ((__STATE__) == RCC_HSE_BYPASS) \
+ { \
+ SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
+ SET_BIT(RCC->CR, RCC_CR_HSEON); \
+ } \
+ else \
+ { \
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
+ } \
+ }while(0U)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LSE_Configuration LSE Configuration
+ * @{
+ */
+
+/**
+ * @brief Macro to configure the External Low Speed oscillator (LSE).
+ * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
+ * @note As the LSE is in the Backup domain and write access is denied to
+ * this domain after reset, you have to enable write access using
+ * @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE
+ * (to be done once after reset).
+ * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
+ * software should wait on LSERDY flag to be set indicating that LSE clock
+ * is stable and can be used to clock the RTC.
+ * @param __STATE__ specifies the new state of the LSE.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after
+ * 6 LSE oscillator clock cycles.
+ * @arg @ref RCC_LSE_ON turn ON the LSE oscillator.
+ * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
+ */
+#define __HAL_RCC_LSE_CONFIG(__STATE__) \
+ do{ \
+ if ((__STATE__) == RCC_LSE_ON) \
+ { \
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
+ } \
+ else if ((__STATE__) == RCC_LSE_OFF) \
+ { \
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
+ } \
+ else if ((__STATE__) == RCC_LSE_BYPASS) \
+ { \
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
+ } \
+ else \
+ { \
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
+ } \
+ }while(0U)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_USARTx_Clock_Config RCC USARTx Clock Config
+ * @{
+ */
+
+/** @brief Macro to configure the USART1 clock (USART1CLK).
+ * @param __USART1CLKSOURCE__ specifies the USART1 clock source.
+ * This parameter can be one of the following values:
+ @if STM32F302xC
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
+ @endif
+ @if STM32F303xC
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
+ @endif
+ @if STM32F358xx
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
+ @endif
+ @if STM32F302xE
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
+ @endif
+ @if STM32F303xE
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
+ @endif
+ @if STM32F398xx
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
+ @endif
+ @if STM32F373xC
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
+ @endif
+ @if STM32F378xx
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
+ @endif
+ @if STM32F301x8
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
+ @endif
+ @if STM32F302x8
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
+ @endif
+ @if STM32F318xx
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
+ @endif
+ @if STM32F303x8
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
+ @endif
+ @if STM32F334x8
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
+ @endif
+ @if STM32F328xx
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
+ @endif
+ * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
+ * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
+ * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
+ */
+#define __HAL_RCC_USART1_CONFIG(__USART1CLKSOURCE__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSOURCE__))
+
+/** @brief Macro to get the USART1 clock source.
+ * @retval The clock source can be one of the following values:
+ @if STM32F302xC
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
+ @endif
+ @if STM32F303xC
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
+ @endif
+ @if STM32F358xx
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
+ @endif
+ @if STM32F302xE
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
+ @endif
+ @if STM32F303xE
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
+ @endif
+ @if STM32F398xx
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
+ @endif
+ @if STM32F373xC
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
+ @endif
+ @if STM32F378xx
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
+ @endif
+ @if STM32F301x8
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
+ @endif
+ @if STM32F302x8
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
+ @endif
+ @if STM32F318xx
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
+ @endif
+ @if STM32F303x8
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
+ @endif
+ @if STM32F334x8
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
+ @endif
+ @if STM32F328xx
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
+ @endif
+ * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
+ * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
+ * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
+ */
+#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART1SW)))
+
+#if defined(RCC_CFGR3_USART2SW)
+/** @brief Macro to configure the USART2 clock (USART2CLK).
+ * @param __USART2CLKSOURCE__ specifies the USART2 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
+ * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
+ * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
+ * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
+ */
+#define __HAL_RCC_USART2_CONFIG(__USART2CLKSOURCE__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSOURCE__))
+
+/** @brief Macro to get the USART2 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
+ * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
+ * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
+ * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
+ */
+#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW)))
+#endif /* RCC_CFGR3_USART2SW */
+
+#if defined(RCC_CFGR3_USART3SW)
+/** @brief Macro to configure the USART3 clock (USART3CLK).
+ * @param __USART3CLKSOURCE__ specifies the USART3 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
+ * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
+ * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
+ * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
+ */
+#define __HAL_RCC_USART3_CONFIG(__USART3CLKSOURCE__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSOURCE__))
+
+/** @brief Macro to get the USART3 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
+ * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
+ * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
+ * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
+ */
+#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW)))
+#endif /* RCC_CFGR3_USART2SW */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_I2Cx_Clock_Config RCC I2Cx Clock Config
+ * @{
+ */
+
+/** @brief Macro to configure the I2C1 clock (I2C1CLK).
+ * @param __I2C1CLKSOURCE__ specifies the I2C1 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
+ * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
+ */
+#define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSOURCE__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSOURCE__))
+
+/** @brief Macro to get the I2C1 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
+ * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
+ */
+#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C1SW)))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL_Configuration PLL Configuration
+ * @{
+ */
+
+/** @brief Macro to enable the main PLL.
+ * @note After enabling the main PLL, the application software should wait on
+ * PLLRDY flag to be set indicating that PLL clock is stable and can
+ * be used as system clock source.
+ * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
+ */
+#define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
+
+/** @brief Macro to disable the main PLL.
+ * @note The main PLL can not be disabled if it is used as system clock source
+ */
+#define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
+
+
+/** @brief Get oscillator clock selected as PLL input clock
+ * @retval The clock source used for PLL entry. The returned value can be one
+ * of the following:
+ * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL input clock
+ * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock
+ */
+#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Get_Clock_source Get Clock source
+ * @{
+ */
+
+/**
+ * @brief Macro to configure the system clock source.
+ * @param __SYSCLKSOURCE__ specifies the system clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
+ * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
+ * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
+ */
+#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
+
+/** @brief Macro to get the clock source used as system clock.
+ * @retval The clock source used as system clock. The returned value can be one
+ * of the following:
+ * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock
+ * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock
+ * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock
+ */
+#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
+ * @{
+ */
+
+#if defined(RCC_CFGR_MCOPRE)
+/** @brief Macro to configure the MCO clock.
+ * @param __MCOCLKSOURCE__ specifies the MCO clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_HSI HSI oscillator clock selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock
+ * @param __MCODIV__ specifies the MCO clock prescaler.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1
+ * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2
+ * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4
+ * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8
+ * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16
+ * @arg @ref RCC_MCODIV_32 MCO clock source is divided by 32
+ * @arg @ref RCC_MCODIV_64 MCO clock source is divided by 64
+ * @arg @ref RCC_MCODIV_128 MCO clock source is divided by 128
+ */
+#else
+/** @brief Macro to configure the MCO clock.
+ * @param __MCOCLKSOURCE__ specifies the MCO clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock
+ * @param __MCODIV__ specifies the MCO clock prescaler.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source
+ */
+#endif
+#if defined(RCC_CFGR_MCOPRE)
+#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
+ MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
+#else
+
+#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__))
+
+#endif
+
+/**
+ * @}
+ */
+
+ /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
+ * @{
+ */
+
+/** @brief Macro to configure the RTC clock (RTCCLK).
+ * @note As the RTC clock configuration bits are in the Backup domain and write
+ * access is denied to this domain after reset, you have to enable write
+ * access using the Power Backup Access macro before to configure
+ * the RTC clock source (to be done once after reset).
+ * @note Once the RTC clock is configured it cannot be changed unless the
+ * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by
+ * a Power On Reset (POR).
+ *
+ * @param __RTC_CLKSOURCE__ specifies the RTC clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
+ * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
+ * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
+ * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32
+ * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
+ * work in STOP and STANDBY modes, and can be used as wakeup source.
+ * However, when the LSI clock and HSE clock divided by 32 is used as RTC clock source,
+ * the RTC cannot be used in STOP and STANDBY modes.
+ * @note The system must always be configured so as to get a PCLK frequency greater than or
+ * equal to the RTCCLK frequency for a proper operation of the RTC.
+ */
+#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
+
+/** @brief Macro to get the RTC clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
+ * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
+ * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
+ * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32
+ */
+#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
+
+/** @brief Macro to enable the the RTC clock.
+ * @note These macros must be used only after the RTC clock source was selected.
+ */
+#define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
+
+/** @brief Macro to disable the the RTC clock.
+ * @note These macros must be used only after the RTC clock source was selected.
+ */
+#define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
+
+/** @brief Macro to force the Backup domain reset.
+ * @note This function resets the RTC peripheral (including the backup registers)
+ * and the RTC clock source selection in RCC_BDCR register.
+ */
+#define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
+
+/** @brief Macros to release the Backup domain reset.
+ */
+#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
+ * @brief macros to manage the specified RCC Flags and interrupts.
+ * @{
+ */
+
+/** @brief Enable RCC interrupt.
+ * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
+ * This parameter can be any combination of the following values:
+ * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
+ * @arg @ref RCC_IT_LSERDY LSE ready interrupt
+ * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
+ * @arg @ref RCC_IT_HSERDY HSE ready interrupt
+ * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
+ */
+#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
+
+/** @brief Disable RCC interrupt.
+ * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
+ * This parameter can be any combination of the following values:
+ * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
+ * @arg @ref RCC_IT_LSERDY LSE ready interrupt
+ * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
+ * @arg @ref RCC_IT_HSERDY HSE ready interrupt
+ * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
+ */
+#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
+
+/** @brief Clear the RCC's interrupt pending bits.
+ * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
+ * @arg @ref RCC_IT_LSERDY LSE ready interrupt.
+ * @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
+ * @arg @ref RCC_IT_HSERDY HSE ready interrupt.
+ * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
+ * @arg @ref RCC_IT_CSS Clock Security System interrupt
+ */
+#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
+
+/** @brief Check the RCC's interrupt has occurred or not.
+ * @param __INTERRUPT__ specifies the RCC interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
+ * @arg @ref RCC_IT_LSERDY LSE ready interrupt.
+ * @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
+ * @arg @ref RCC_IT_HSERDY HSE ready interrupt.
+ * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
+ * @arg @ref RCC_IT_CSS Clock Security System interrupt
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+ */
+#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/** @brief Set RMVF bit to clear the reset flags.
+ * The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
+ * RCC_FLAG_OBLRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
+ */
+#define __HAL_RCC_CLEAR_RESET_FLAGS() (*(__IO uint32_t *)RCC_CSR_RMVF_BB = ENABLE)
+
+/** @brief Check RCC flag is set or not.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready.
+ * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready.
+ * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready.
+ * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready.
+ * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready.
+ * @arg @ref RCC_FLAG_OBLRST Option Byte Load reset
+ * @arg @ref RCC_FLAG_PINRST Pin reset.
+ * @arg @ref RCC_FLAG_PORRST POR/PDR reset.
+ * @arg @ref RCC_FLAG_SFTRST Software reset.
+ * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset.
+ * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset.
+ * @arg @ref RCC_FLAG_LPWRRST Low Power reset.
+ @if defined(STM32F301x8)
+ * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
+ @endif
+ @if defined(STM32F302x8)
+ * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
+ @endif
+ @if defined(STM32F302xC)
+ * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
+ * @arg @ref RCC_FLAG_MCO Microcontroller Clock Output
+ @endif
+ @if defined(STM32F302xE)
+ * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
+ @endif
+ @if defined(STM32F303x8)
+ * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
+ @endif
+ @if defined(STM32F303xC)
+ * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
+ * @arg @ref RCC_FLAG_MCO Microcontroller Clock Output
+ @endif
+ @if defined(STM32F303xE)
+ * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
+ @endif
+ @if defined(STM32F334x8)
+ * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
+ @endif
+ @if defined(STM32F358xx)
+ * @arg @ref RCC_FLAG_MCO Microcontroller Clock Output
+ @endif
+ @if defined(STM32F373xC)
+ * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
+ @endif
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX) ? RCC->CR : \
+ (((__FLAG__) >> 5U) == BDCR_REG_INDEX)? RCC->BDCR : \
+ (((__FLAG__) >> 5U) == CFGR_REG_INDEX)? RCC->CFGR : \
+ RCC->CSR) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Include RCC HAL Extension module */
+#include "stm32f3xx_hal_rcc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RCC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup RCC_Exported_Functions_Group1
+ * @{
+ */
+
+/* Initialization and de-initialization functions ******************************/
+HAL_StatusTypeDef HAL_RCC_DeInit(void);
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Exported_Functions_Group2
+ * @{
+ */
+
+/* Peripheral Control functions ************************************************/
+void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
+void HAL_RCC_EnableCSS(void);
+/* CSS NMI IRQ handler */
+void HAL_RCC_NMI_IRQHandler(void);
+/* User Callbacks in non blocking mode (IT mode) */
+void HAL_RCC_CSSCallback(void);
+void HAL_RCC_DisableCSS(void);
+uint32_t HAL_RCC_GetSysClockFreq(void);
+uint32_t HAL_RCC_GetHCLKFreq(void);
+uint32_t HAL_RCC_GetPCLK1Freq(void);
+uint32_t HAL_RCC_GetPCLK2Freq(void);
+void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
+void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_RCC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Inc/stm32f3xx_hal_rcc_ex.h b/Inc/stm32f3xx_hal_rcc_ex.h
new file mode 100644
index 0000000..aadf44b
--- /dev/null
+++ b/Inc/stm32f3xx_hal_rcc_ex.h
@@ -0,0 +1,3843 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_rcc_ex.h
+ * @author MCD Application Team
+ * @brief Header file of RCC HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_RCC_EX_H
+#define __STM32F3xx_HAL_RCC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup RCCEx
+ * @{
+ */
+
+/** @addtogroup RCCEx_Private_Macros
+ * @{
+ */
+
+#if defined(RCC_CFGR_PLLNODIV)
+#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \
+ ((SOURCE) == RCC_MCO1SOURCE_LSI) || \
+ ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
+ ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \
+ ((SOURCE) == RCC_MCO1SOURCE_HSI) || \
+ ((SOURCE) == RCC_MCO1SOURCE_HSE) || \
+ ((SOURCE) == RCC_MCO1SOURCE_PLLCLK) || \
+ ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2))
+#else
+#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \
+ ((SOURCE) == RCC_MCO1SOURCE_LSI) || \
+ ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
+ ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \
+ ((SOURCE) == RCC_MCO1SOURCE_HSI) || \
+ ((SOURCE) == RCC_MCO1SOURCE_HSE) || \
+ ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2))
+#endif /* RCC_CFGR_PLLNODIV */
+
+#if defined(STM32F301x8) || defined(STM32F318xx)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
+ RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_I2S | \
+ RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_TIM1 | \
+ RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \
+ RCC_PERIPHCLK_TIM17 | RCC_PERIPHCLK_RTC))
+#endif /* STM32F301x8 || STM32F318xx */
+#if defined(STM32F302x8)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
+ RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_I2S | \
+ RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_TIM1 | \
+ RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB | \
+ RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \
+ RCC_PERIPHCLK_TIM17))
+#endif /* STM32F302x8 */
+#if defined(STM32F302xC)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
+ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
+ RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_I2S | \
+ RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC | \
+ RCC_PERIPHCLK_USB))
+#endif /* STM32F302xC */
+#if defined(STM32F303xC)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
+ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
+ RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \
+ RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \
+ RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC | \
+ RCC_PERIPHCLK_USB))
+#endif /* STM32F303xC */
+#if defined(STM32F302xE)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
+ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
+ RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_I2S | \
+ RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC | \
+ RCC_PERIPHCLK_USB | RCC_PERIPHCLK_I2C3 | \
+ RCC_PERIPHCLK_TIM2 | RCC_PERIPHCLK_TIM34 | \
+ RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \
+ RCC_PERIPHCLK_TIM17))
+#endif /* STM32F302xE */
+#if defined(STM32F303xE)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
+ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
+ RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \
+ RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \
+ RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC | \
+ RCC_PERIPHCLK_USB | RCC_PERIPHCLK_I2C3 | \
+ RCC_PERIPHCLK_TIM2 | RCC_PERIPHCLK_TIM34 | \
+ RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \
+ RCC_PERIPHCLK_TIM17 | RCC_PERIPHCLK_TIM20))
+#endif /* STM32F303xE */
+#if defined(STM32F398xx)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
+ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
+ RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \
+ RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \
+ RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC | \
+ RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_TIM2 | \
+ RCC_PERIPHCLK_TIM34 | RCC_PERIPHCLK_TIM15 | \
+ RCC_PERIPHCLK_TIM16 | RCC_PERIPHCLK_TIM17 | \
+ RCC_PERIPHCLK_TIM20))
+#endif /* STM32F398xx */
+#if defined(STM32F358xx)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
+ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
+ RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \
+ RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \
+ RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC))
+#endif /* STM32F358xx */
+#if defined(STM32F303x8)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_ADC12 | \
+ RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC))
+#endif /* STM32F303x8 */
+#if defined(STM32F334x8)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_ADC12 | \
+ RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_HRTIM1 | \
+ RCC_PERIPHCLK_RTC))
+#endif /* STM32F334x8 */
+#if defined(STM32F328xx)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_ADC12 | \
+ RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC))
+#endif /* STM32F328xx */
+#if defined(STM32F373xC)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
+ RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_SDADC | \
+ RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC | \
+ RCC_PERIPHCLK_USB))
+#endif /* STM32F373xC */
+#if defined(STM32F378xx)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
+ RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_SDADC | \
+ RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC))
+#endif /* STM32F378xx */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK1) || \
+ ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
+ ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
+ ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
+#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \
+ ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
+#define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_HSI) || \
+ ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK))
+#define IS_RCC_ADC1PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC1PLLCLK_OFF) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV1) || \
+ ((ADCCLK) == RCC_ADC1PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV4) || \
+ ((ADCCLK) == RCC_ADC1PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV8) || \
+ ((ADCCLK) == RCC_ADC1PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV12) || \
+ ((ADCCLK) == RCC_ADC1PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV32) || \
+ ((ADCCLK) == RCC_ADC1PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV128) || \
+ ((ADCCLK) == RCC_ADC1PLLCLK_DIV256))
+#define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) || \
+ ((SOURCE) == RCC_I2SCLKSOURCE_EXT))
+#define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \
+ ((SOURCE) == RCC_TIM1CLK_PLLCLK))
+#define IS_RCC_TIM15CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM15CLK_HCLK) || \
+ ((SOURCE) == RCC_TIM15CLK_PLLCLK))
+#define IS_RCC_TIM16CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM16CLK_HCLK) || \
+ ((SOURCE) == RCC_TIM16CLK_PLLCLK))
+#define IS_RCC_TIM17CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM17CLK_HCLK) || \
+ ((SOURCE) == RCC_TIM17CLK_PLLCLK))
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \
+ ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
+ ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
+ ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
+#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \
+ ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
+#define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_DIV256))
+#define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) || \
+ ((SOURCE) == RCC_I2SCLKSOURCE_EXT))
+#define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \
+ ((SOURCE) == RCC_TIM1CLK_PLLCLK))
+#define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) || \
+ ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \
+ ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \
+ ((SOURCE) == RCC_UART4CLKSOURCE_HSI))
+#define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) || \
+ ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \
+ ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \
+ ((SOURCE) == RCC_UART5CLKSOURCE_HSI))
+#endif /* STM32F302xC || STM32F303xC || STM32F358xx */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \
+ ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
+ ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
+ ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
+#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \
+ ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
+#define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_HSI) || \
+ ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK))
+#define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_DIV256))
+#define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) || \
+ ((SOURCE) == RCC_I2SCLKSOURCE_EXT))
+#define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \
+ ((SOURCE) == RCC_TIM1CLK_PLLCLK))
+#define IS_RCC_TIM2CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM2CLK_HCLK) || \
+ ((SOURCE) == RCC_TIM2CLK_PLLCLK))
+#define IS_RCC_TIM3CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM34CLK_HCLK) || \
+ ((SOURCE) == RCC_TIM34CLK_PLLCLK))
+#define IS_RCC_TIM15CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM15CLK_HCLK) || \
+ ((SOURCE) == RCC_TIM15CLK_PLLCLK))
+#define IS_RCC_TIM16CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM16CLK_HCLK) || \
+ ((SOURCE) == RCC_TIM16CLK_PLLCLK))
+#define IS_RCC_TIM17CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM17CLK_HCLK) || \
+ ((SOURCE) == RCC_TIM17CLK_PLLCLK))
+#define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) || \
+ ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \
+ ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \
+ ((SOURCE) == RCC_UART4CLKSOURCE_HSI))
+#define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) || \
+ ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \
+ ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \
+ ((SOURCE) == RCC_UART5CLKSOURCE_HSI))
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+#if defined(STM32F303xE) || defined(STM32F398xx)
+#define IS_RCC_TIM20CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM20CLK_HCLK) || \
+ ((SOURCE) == RCC_TIM20CLK_PLLCLK))
+#endif /* STM32F303xE || STM32F398xx */
+#if defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F303xC) || defined(STM32F358xx)
+#define IS_RCC_ADC34PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC34PLLCLK_OFF) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV1) || \
+ ((ADCCLK) == RCC_ADC34PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV4) || \
+ ((ADCCLK) == RCC_ADC34PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV8) || \
+ ((ADCCLK) == RCC_ADC34PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV12) || \
+ ((ADCCLK) == RCC_ADC34PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV32) || \
+ ((ADCCLK) == RCC_ADC34PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV128) || \
+ ((ADCCLK) == RCC_ADC34PLLCLK_DIV256))
+#define IS_RCC_TIM8CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM8CLK_HCLK) || \
+ ((SOURCE) == RCC_TIM8CLK_PLLCLK))
+#endif /* STM32F303xC || STM32F303xE || STM32F398xx || STM32F358xx */
+#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK1) || \
+ ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
+ ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
+ ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
+#define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_DIV256))
+#define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \
+ ((SOURCE) == RCC_TIM1CLK_PLLCLK))
+#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+#if defined(STM32F334x8)
+#define IS_RCC_HRTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_HRTIM1CLK_HCLK) || \
+ ((SOURCE) == RCC_HRTIM1CLK_PLLCLK))
+#endif /* STM32F334x8 */
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \
+ ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
+ ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
+ ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
+#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \
+ ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
+#define IS_RCC_ADC1PCLK2_DIV(ADCCLK) (((ADCCLK) == RCC_ADC1PCLK2_DIV2) || ((ADCCLK) == RCC_ADC1PCLK2_DIV4) || \
+ ((ADCCLK) == RCC_ADC1PCLK2_DIV6) || ((ADCCLK) == RCC_ADC1PCLK2_DIV8))
+#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \
+ ((SOURCE) == RCC_CECCLKSOURCE_LSE))
+#define IS_RCC_SDADCSYSCLK_DIV(DIV) (((DIV) == RCC_SDADCSYSCLK_DIV1) || ((DIV) == RCC_SDADCSYSCLK_DIV2) || \
+ ((DIV) == RCC_SDADCSYSCLK_DIV4) || ((DIV) == RCC_SDADCSYSCLK_DIV6) || \
+ ((DIV) == RCC_SDADCSYSCLK_DIV8) || ((DIV) == RCC_SDADCSYSCLK_DIV10) || \
+ ((DIV) == RCC_SDADCSYSCLK_DIV12) || ((DIV) == RCC_SDADCSYSCLK_DIV14) || \
+ ((DIV) == RCC_SDADCSYSCLK_DIV16) || ((DIV) == RCC_SDADCSYSCLK_DIV20) || \
+ ((DIV) == RCC_SDADCSYSCLK_DIV24) || ((DIV) == RCC_SDADCSYSCLK_DIV28) || \
+ ((DIV) == RCC_SDADCSYSCLK_DIV32) || ((DIV) == RCC_SDADCSYSCLK_DIV36) || \
+ ((DIV) == RCC_SDADCSYSCLK_DIV40) || ((DIV) == RCC_SDADCSYSCLK_DIV44) || \
+ ((DIV) == RCC_SDADCSYSCLK_DIV48))
+#endif /* STM32F373xC || STM32F378xx */
+#if defined(STM32F302xE) || defined(STM32F303xE)\
+ || defined(STM32F302xC) || defined(STM32F303xC)\
+ || defined(STM32F302x8) \
+ || defined(STM32F373xC)
+#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_PLL) || \
+ ((SOURCE) == RCC_USBCLKSOURCE_PLL_DIV1_5))
+#endif /* STM32F302xE || STM32F303xE || */
+ /* STM32F302xC || STM32F303xC || */
+ /* STM32F302x8 || */
+ /* STM32F373xC */
+#if defined(RCC_CFGR_MCOPRE)
+#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
+ ((DIV) == RCC_MCODIV_4) || ((DIV) == RCC_MCODIV_8) || \
+ ((DIV) == RCC_MCODIV_16) || ((DIV) == RCC_MCODIV_32) || \
+ ((DIV) == RCC_MCODIV_64) || ((DIV) == RCC_MCODIV_128))
+#else
+#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1))
+#endif /* RCC_CFGR_MCOPRE */
+
+#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \
+ ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \
+ ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \
+ ((__DRIVE__) == RCC_LSEDRIVE_HIGH))
+
+/**
+ * @}
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
+ * @{
+ */
+
+/**
+ * @brief RCC extended clocks structure definition
+ */
+#if defined(STM32F301x8) || defined(STM32F318xx)
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+ uint32_t Usart1ClockSelection; /*!< USART1 clock source
+ This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
+
+ uint32_t I2c1ClockSelection; /*!< I2C1 clock source
+ This parameter can be a value of @ref RCC_I2C1_Clock_Source */
+
+ uint32_t I2c2ClockSelection; /*!< I2C2 clock source
+ This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
+
+ uint32_t I2c3ClockSelection; /*!< I2C3 clock source
+ This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
+
+ uint32_t Adc1ClockSelection; /*!< ADC1 clock source
+ This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
+
+ uint32_t I2sClockSelection; /*!< I2S clock source
+ This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
+
+ uint32_t Tim1ClockSelection; /*!< TIM1 clock source
+ This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
+
+ uint32_t Tim15ClockSelection; /*!< TIM15 clock source
+ This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
+
+ uint32_t Tim16ClockSelection; /*!< TIM16 clock source
+ This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
+
+ uint32_t Tim17ClockSelection; /*!< TIM17 clock source
+ This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F301x8 || STM32F318xx */
+
+#if defined(STM32F302x8)
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+ uint32_t Usart1ClockSelection; /*!< USART1 clock source
+ This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
+
+ uint32_t I2c1ClockSelection; /*!< I2C1 clock source
+ This parameter can be a value of @ref RCC_I2C1_Clock_Source */
+
+ uint32_t I2c2ClockSelection; /*!< I2C2 clock source
+ This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
+
+ uint32_t I2c3ClockSelection; /*!< I2C3 clock source
+ This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
+
+ uint32_t Adc1ClockSelection; /*!< ADC1 clock source
+ This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
+
+ uint32_t I2sClockSelection; /*!< I2S clock source
+ This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
+
+ uint32_t Tim1ClockSelection; /*!< TIM1 clock source
+ This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
+
+ uint32_t Tim15ClockSelection; /*!< TIM15 clock source
+ This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
+
+ uint32_t Tim16ClockSelection; /*!< TIM16 clock source
+ This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
+
+ uint32_t Tim17ClockSelection; /*!< TIM17 clock source
+ This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
+
+ uint32_t USBClockSelection; /*!< USB clock source
+ This parameter can be a value of @ref RCCEx_USB_Clock_Source */
+
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F302x8 */
+
+#if defined(STM32F302xC)
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+ uint32_t Usart1ClockSelection; /*!< USART1 clock source
+ This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
+
+ uint32_t Usart2ClockSelection; /*!< USART2 clock source
+ This parameter can be a value of @ref RCC_USART2_Clock_Source */
+
+ uint32_t Usart3ClockSelection; /*!< USART3 clock source
+ This parameter can be a value of @ref RCC_USART3_Clock_Source */
+
+ uint32_t Uart4ClockSelection; /*!< UART4 clock source
+ This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
+
+ uint32_t Uart5ClockSelection; /*!< UART5 clock source
+ This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
+
+ uint32_t I2c1ClockSelection; /*!< I2C1 clock source
+ This parameter can be a value of @ref RCC_I2C1_Clock_Source */
+
+ uint32_t I2c2ClockSelection; /*!< I2C2 clock source
+ This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
+
+ uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
+ This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
+
+ uint32_t I2sClockSelection; /*!< I2S clock source
+ This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
+
+ uint32_t Tim1ClockSelection; /*!< TIM1 clock source
+ This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
+
+ uint32_t USBClockSelection; /*!< USB clock source
+ This parameter can be a value of @ref RCCEx_USB_Clock_Source */
+
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F302xC */
+
+#if defined(STM32F303xC)
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+ uint32_t Usart1ClockSelection; /*!< USART1 clock source
+ This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
+
+ uint32_t Usart2ClockSelection; /*!< USART2 clock source
+ This parameter can be a value of @ref RCC_USART2_Clock_Source */
+
+ uint32_t Usart3ClockSelection; /*!< USART3 clock source
+ This parameter can be a value of @ref RCC_USART3_Clock_Source */
+
+ uint32_t Uart4ClockSelection; /*!< UART4 clock source
+ This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
+
+ uint32_t Uart5ClockSelection; /*!< UART5 clock source
+ This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
+
+ uint32_t I2c1ClockSelection; /*!< I2C1 clock source
+ This parameter can be a value of @ref RCC_I2C1_Clock_Source */
+
+ uint32_t I2c2ClockSelection; /*!< I2C2 clock source
+ This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
+
+ uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
+ This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
+
+ uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
+ This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
+
+ uint32_t I2sClockSelection; /*!< I2S clock source
+ This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
+
+ uint32_t Tim1ClockSelection; /*!< TIM1 clock source
+ This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
+
+ uint32_t Tim8ClockSelection; /*!< TIM8 clock source
+ This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
+
+ uint32_t USBClockSelection; /*!< USB clock source
+ This parameter can be a value of @ref RCCEx_USB_Clock_Source */
+
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F303xC */
+
+#if defined(STM32F302xE)
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+ uint32_t Usart1ClockSelection; /*!< USART1 clock source
+ This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
+
+ uint32_t Usart2ClockSelection; /*!< USART2 clock source
+ This parameter can be a value of @ref RCC_USART2_Clock_Source */
+
+ uint32_t Usart3ClockSelection; /*!< USART3 clock source
+ This parameter can be a value of @ref RCC_USART3_Clock_Source */
+
+ uint32_t Uart4ClockSelection; /*!< UART4 clock source
+ This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
+
+ uint32_t Uart5ClockSelection; /*!< UART5 clock source
+ This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
+
+ uint32_t I2c1ClockSelection; /*!< I2C1 clock source
+ This parameter can be a value of @ref RCC_I2C1_Clock_Source */
+
+ uint32_t I2c2ClockSelection; /*!< I2C2 clock source
+ This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
+
+ uint32_t I2c3ClockSelection; /*!< I2C3 clock source
+ This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
+
+ uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
+ This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
+
+ uint32_t I2sClockSelection; /*!< I2S clock source
+ This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
+
+ uint32_t Tim1ClockSelection; /*!< TIM1 clock source
+ This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
+
+ uint32_t Tim2ClockSelection; /*!< TIM2 clock source
+ This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */
+
+ uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source
+ This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */
+
+ uint32_t Tim15ClockSelection; /*!< TIM15 clock source
+ This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
+
+ uint32_t Tim16ClockSelection; /*!< TIM16 clock source
+ This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
+
+ uint32_t Tim17ClockSelection; /*!< TIM17 clock source
+ This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
+
+ uint32_t USBClockSelection; /*!< USB clock source
+ This parameter can be a value of @ref RCCEx_USB_Clock_Source */
+
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F302xE */
+
+#if defined(STM32F303xE)
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+ uint32_t Usart1ClockSelection; /*!< USART1 clock source
+ This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
+
+ uint32_t Usart2ClockSelection; /*!< USART2 clock source
+ This parameter can be a value of @ref RCC_USART2_Clock_Source */
+
+ uint32_t Usart3ClockSelection; /*!< USART3 clock source
+ This parameter can be a value of @ref RCC_USART3_Clock_Source */
+
+ uint32_t Uart4ClockSelection; /*!< UART4 clock source
+ This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
+
+ uint32_t Uart5ClockSelection; /*!< UART5 clock source
+ This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
+
+ uint32_t I2c1ClockSelection; /*!< I2C1 clock source
+ This parameter can be a value of @ref RCC_I2C1_Clock_Source */
+
+ uint32_t I2c2ClockSelection; /*!< I2C2 clock source
+ This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
+
+ uint32_t I2c3ClockSelection; /*!< I2C3 clock source
+ This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
+
+ uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
+ This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
+
+ uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
+ This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
+
+ uint32_t I2sClockSelection; /*!< I2S clock source
+ This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
+
+ uint32_t Tim1ClockSelection; /*!< TIM1 clock source
+ This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
+
+ uint32_t Tim2ClockSelection; /*!< TIM2 clock source
+ This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */
+
+ uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source
+ This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */
+
+ uint32_t Tim8ClockSelection; /*!< TIM8 clock source
+ This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
+
+ uint32_t Tim15ClockSelection; /*!< TIM15 clock source
+ This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
+
+ uint32_t Tim16ClockSelection; /*!< TIM16 clock source
+ This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
+
+ uint32_t Tim17ClockSelection; /*!< TIM17 clock source
+ This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
+
+ uint32_t Tim20ClockSelection; /*!< TIM20 clock source
+ This parameter can be a value of @ref RCCEx_TIM20_Clock_Source */
+
+ uint32_t USBClockSelection; /*!< USB clock source
+ This parameter can be a value of @ref RCCEx_USB_Clock_Source */
+
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F303xE */
+
+#if defined(STM32F398xx)
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+ uint32_t Usart1ClockSelection; /*!< USART1 clock source
+ This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
+
+ uint32_t Usart2ClockSelection; /*!< USART2 clock source
+ This parameter can be a value of @ref RCC_USART2_Clock_Source */
+
+ uint32_t Usart3ClockSelection; /*!< USART3 clock source
+ This parameter can be a value of @ref RCC_USART3_Clock_Source */
+
+ uint32_t Uart4ClockSelection; /*!< UART4 clock source
+ This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
+
+ uint32_t Uart5ClockSelection; /*!< UART5 clock source
+ This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
+
+ uint32_t I2c1ClockSelection; /*!< I2C1 clock source
+ This parameter can be a value of @ref RCC_I2C1_Clock_Source */
+
+ uint32_t I2c2ClockSelection; /*!< I2C2 clock source
+ This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
+
+ uint32_t I2c3ClockSelection; /*!< I2C3 clock source
+ This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
+
+ uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
+ This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
+
+ uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
+ This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
+
+ uint32_t I2sClockSelection; /*!< I2S clock source
+ This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
+
+ uint32_t Tim1ClockSelection; /*!< TIM1 clock source
+ This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
+
+ uint32_t Tim2ClockSelection; /*!< TIM2 clock source
+ This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */
+
+ uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source
+ This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */
+
+ uint32_t Tim8ClockSelection; /*!< TIM8 clock source
+ This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
+
+ uint32_t Tim15ClockSelection; /*!< TIM15 clock source
+ This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
+
+ uint32_t Tim16ClockSelection; /*!< TIM16 clock source
+ This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
+
+ uint32_t Tim17ClockSelection; /*!< TIM17 clock source
+ This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
+
+ uint32_t Tim20ClockSelection; /*!< TIM20 clock source
+ This parameter can be a value of @ref RCCEx_TIM20_Clock_Source */
+
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F398xx */
+
+#if defined(STM32F358xx)
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+ uint32_t Usart1ClockSelection; /*!< USART1 clock source
+ This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
+
+ uint32_t Usart2ClockSelection; /*!< USART2 clock source
+ This parameter can be a value of @ref RCC_USART2_Clock_Source */
+
+ uint32_t Usart3ClockSelection; /*!< USART3 clock source
+ This parameter can be a value of @ref RCC_USART3_Clock_Source */
+
+ uint32_t Uart4ClockSelection; /*!< UART4 clock source
+ This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
+
+ uint32_t Uart5ClockSelection; /*!< UART5 clock source
+ This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
+
+ uint32_t I2c1ClockSelection; /*!< I2C1 clock source
+ This parameter can be a value of @ref RCC_I2C1_Clock_Source */
+
+ uint32_t I2c2ClockSelection; /*!< I2C2 clock source
+ This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
+
+ uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
+ This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
+
+ uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
+ This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
+
+ uint32_t I2sClockSelection; /*!< I2S clock source
+ This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
+
+ uint32_t Tim1ClockSelection; /*!< TIM1 clock source
+ This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
+
+ uint32_t Tim8ClockSelection; /*!< TIM8 clock source
+ This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
+
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F358xx */
+
+#if defined(STM32F303x8)
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+ uint32_t Usart1ClockSelection; /*!< USART1 clock source
+ This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
+
+ uint32_t I2c1ClockSelection; /*!< I2C1 clock source
+ This parameter can be a value of @ref RCC_I2C1_Clock_Source */
+
+ uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
+ This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
+
+ uint32_t Tim1ClockSelection; /*!< TIM1 clock source
+ This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
+
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F303x8 */
+
+#if defined(STM32F334x8)
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+ uint32_t Usart1ClockSelection; /*!< USART1 clock source
+ This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
+
+ uint32_t I2c1ClockSelection; /*!< I2C1 clock source
+ This parameter can be a value of @ref RCC_I2C1_Clock_Source */
+
+ uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
+ This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
+
+ uint32_t Tim1ClockSelection; /*!< TIM1 clock source
+ This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
+
+ uint32_t Hrtim1ClockSelection; /*!< HRTIM1 clock source
+ This parameter can be a value of @ref RCCEx_HRTIM1_Clock_Source */
+
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F334x8 */
+
+#if defined(STM32F328xx)
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+ uint32_t Usart1ClockSelection; /*!< USART1 clock source
+ This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
+
+ uint32_t I2c1ClockSelection; /*!< I2C1 clock source
+ This parameter can be a value of @ref RCC_I2C1_Clock_Source */
+
+ uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
+ This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
+
+ uint32_t Tim1ClockSelection; /*!< TIM1 clock source
+ This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
+
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F328xx */
+
+#if defined(STM32F373xC)
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+ uint32_t Usart1ClockSelection; /*!< USART1 clock source
+ This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
+
+ uint32_t Usart2ClockSelection; /*!< USART2 clock source
+ This parameter can be a value of @ref RCC_USART2_Clock_Source */
+
+ uint32_t Usart3ClockSelection; /*!< USART3 clock source
+ This parameter can be a value of @ref RCC_USART3_Clock_Source */
+
+ uint32_t I2c1ClockSelection; /*!< I2C1 clock source
+ This parameter can be a value of @ref RCC_I2C1_Clock_Source */
+
+ uint32_t I2c2ClockSelection; /*!< I2C2 clock source
+ This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
+
+ uint32_t Adc1ClockSelection; /*!< ADC1 clock source
+ This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
+
+ uint32_t SdadcClockSelection; /*!< SDADC clock prescaler
+ This parameter can be a value of @ref RCCEx_SDADC_Clock_Prescaler */
+
+ uint32_t CecClockSelection; /*!< HDMI CEC clock source
+ This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
+
+ uint32_t USBClockSelection; /*!< USB clock source
+ This parameter can be a value of @ref RCCEx_USB_Clock_Source */
+
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F373xC */
+
+#if defined(STM32F378xx)
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+ uint32_t Usart1ClockSelection; /*!< USART1 clock source
+ This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
+
+ uint32_t Usart2ClockSelection; /*!< USART2 clock source
+ This parameter can be a value of @ref RCC_USART2_Clock_Source */
+
+ uint32_t Usart3ClockSelection; /*!< USART3 clock source
+ This parameter can be a value of @ref RCC_USART3_Clock_Source */
+
+ uint32_t I2c1ClockSelection; /*!< I2C1 clock source
+ This parameter can be a value of @ref RCC_I2C1_Clock_Source */
+
+ uint32_t I2c2ClockSelection; /*!< I2C2 clock source
+ This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
+
+ uint32_t Adc1ClockSelection; /*!< ADC1 clock source
+ This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
+
+ uint32_t SdadcClockSelection; /*!< SDADC clock prescaler
+ This parameter can be a value of @ref RCCEx_SDADC_Clock_Prescaler */
+
+ uint32_t CecClockSelection; /*!< HDMI CEC clock source
+ This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
+
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F378xx */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Constants RCC Extended Exported Constants
+ * @{
+ */
+/** @defgroup RCCEx_MCO_Clock_Source RCC Extended MCO Clock Source
+ * @{
+ */
+#define RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK
+#define RCC_MCO1SOURCE_LSI RCC_CFGR_MCO_LSI
+#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO_LSE
+#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
+#define RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI
+#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE
+#if defined(RCC_CFGR_PLLNODIV)
+#define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_PLLNODIV | RCC_CFGR_MCO_PLL)
+#endif /* RCC_CFGR_PLLNODIV */
+#define RCC_MCO1SOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_Periph_Clock_Selection RCC Extended Periph Clock Selection
+ * @{
+ */
+#if defined(STM32F301x8) || defined(STM32F318xx)
+#define RCC_PERIPHCLK_USART1 (0x00000001U)
+#define RCC_PERIPHCLK_I2C1 (0x00000020U)
+#define RCC_PERIPHCLK_I2C2 (0x00000040U)
+#define RCC_PERIPHCLK_ADC1 (0x00000080U)
+#define RCC_PERIPHCLK_I2S (0x00000200U)
+#define RCC_PERIPHCLK_TIM1 (0x00001000U)
+#define RCC_PERIPHCLK_I2C3 (0x00008000U)
+#define RCC_PERIPHCLK_RTC (0x00010000U)
+#define RCC_PERIPHCLK_TIM15 (0x00040000U)
+#define RCC_PERIPHCLK_TIM16 (0x00080000U)
+#define RCC_PERIPHCLK_TIM17 (0x00100000U)
+
+#endif /* STM32F301x8 || STM32F318xx */
+
+#if defined(STM32F302x8)
+#define RCC_PERIPHCLK_USART1 (0x00000001U)
+#define RCC_PERIPHCLK_I2C1 (0x00000020U)
+#define RCC_PERIPHCLK_I2C2 (0x00000040U)
+#define RCC_PERIPHCLK_ADC1 (0x00000080U)
+#define RCC_PERIPHCLK_I2S (0x00000200U)
+#define RCC_PERIPHCLK_TIM1 (0x00001000U)
+#define RCC_PERIPHCLK_I2C3 (0x00008000U)
+#define RCC_PERIPHCLK_RTC (0x00010000U)
+#define RCC_PERIPHCLK_USB (0x00020000U)
+#define RCC_PERIPHCLK_TIM15 (0x00040000U)
+#define RCC_PERIPHCLK_TIM16 (0x00080000U)
+#define RCC_PERIPHCLK_TIM17 (0x00100000U)
+
+
+#endif /* STM32F302x8 */
+
+#if defined(STM32F302xC)
+#define RCC_PERIPHCLK_USART1 (0x00000001U)
+#define RCC_PERIPHCLK_USART2 (0x00000002U)
+#define RCC_PERIPHCLK_USART3 (0x00000004U)
+#define RCC_PERIPHCLK_UART4 (0x00000008U)
+#define RCC_PERIPHCLK_UART5 (0x00000010U)
+#define RCC_PERIPHCLK_I2C1 (0x00000020U)
+#define RCC_PERIPHCLK_I2C2 (0x00000040U)
+#define RCC_PERIPHCLK_ADC12 (0x00000080U)
+#define RCC_PERIPHCLK_I2S (0x00000200U)
+#define RCC_PERIPHCLK_TIM1 (0x00001000U)
+#define RCC_PERIPHCLK_RTC (0x00010000U)
+#define RCC_PERIPHCLK_USB (0x00020000U)
+
+#endif /* STM32F302xC */
+
+#if defined(STM32F303xC)
+#define RCC_PERIPHCLK_USART1 (0x00000001U)
+#define RCC_PERIPHCLK_USART2 (0x00000002U)
+#define RCC_PERIPHCLK_USART3 (0x00000004U)
+#define RCC_PERIPHCLK_UART4 (0x00000008U)
+#define RCC_PERIPHCLK_UART5 (0x00000010U)
+#define RCC_PERIPHCLK_I2C1 (0x00000020U)
+#define RCC_PERIPHCLK_I2C2 (0x00000040U)
+#define RCC_PERIPHCLK_ADC12 (0x00000080U)
+#define RCC_PERIPHCLK_ADC34 (0x00000100U)
+#define RCC_PERIPHCLK_I2S (0x00000200U)
+#define RCC_PERIPHCLK_TIM1 (0x00001000U)
+#define RCC_PERIPHCLK_TIM8 (0x00002000U)
+#define RCC_PERIPHCLK_RTC (0x00010000U)
+#define RCC_PERIPHCLK_USB (0x00020000U)
+
+#endif /* STM32F303xC */
+
+#if defined(STM32F302xE)
+#define RCC_PERIPHCLK_USART1 (0x00000001U)
+#define RCC_PERIPHCLK_USART2 (0x00000002U)
+#define RCC_PERIPHCLK_USART3 (0x00000004U)
+#define RCC_PERIPHCLK_UART4 (0x00000008U)
+#define RCC_PERIPHCLK_UART5 (0x00000010U)
+#define RCC_PERIPHCLK_I2C1 (0x00000020U)
+#define RCC_PERIPHCLK_I2C2 (0x00000040U)
+#define RCC_PERIPHCLK_ADC12 (0x00000080U)
+#define RCC_PERIPHCLK_I2S (0x00000200U)
+#define RCC_PERIPHCLK_TIM1 (0x00001000U)
+#define RCC_PERIPHCLK_RTC (0x00010000U)
+#define RCC_PERIPHCLK_USB (0x00020000U)
+#define RCC_PERIPHCLK_I2C3 (0x00040000U)
+#define RCC_PERIPHCLK_TIM2 (0x00100000U)
+#define RCC_PERIPHCLK_TIM34 (0x00200000U)
+#define RCC_PERIPHCLK_TIM15 (0x00400000U)
+#define RCC_PERIPHCLK_TIM16 (0x00800000U)
+#define RCC_PERIPHCLK_TIM17 (0x01000000U)
+
+#endif /* STM32F302xE */
+
+#if defined(STM32F303xE)
+#define RCC_PERIPHCLK_USART1 (0x00000001U)
+#define RCC_PERIPHCLK_USART2 (0x00000002U)
+#define RCC_PERIPHCLK_USART3 (0x00000004U)
+#define RCC_PERIPHCLK_UART4 (0x00000008U)
+#define RCC_PERIPHCLK_UART5 (0x00000010U)
+#define RCC_PERIPHCLK_I2C1 (0x00000020U)
+#define RCC_PERIPHCLK_I2C2 (0x00000040U)
+#define RCC_PERIPHCLK_ADC12 (0x00000080U)
+#define RCC_PERIPHCLK_ADC34 (0x00000100U)
+#define RCC_PERIPHCLK_I2S (0x00000200U)
+#define RCC_PERIPHCLK_TIM1 (0x00001000U)
+#define RCC_PERIPHCLK_TIM8 (0x00002000U)
+#define RCC_PERIPHCLK_RTC (0x00010000U)
+#define RCC_PERIPHCLK_USB (0x00020000U)
+#define RCC_PERIPHCLK_I2C3 (0x00040000U)
+#define RCC_PERIPHCLK_TIM2 (0x00100000U)
+#define RCC_PERIPHCLK_TIM34 (0x00200000U)
+#define RCC_PERIPHCLK_TIM15 (0x00400000U)
+#define RCC_PERIPHCLK_TIM16 (0x00800000U)
+#define RCC_PERIPHCLK_TIM17 (0x01000000U)
+#define RCC_PERIPHCLK_TIM20 (0x02000000U)
+
+#endif /* STM32F303xE */
+
+#if defined(STM32F398xx)
+#define RCC_PERIPHCLK_USART1 (0x00000001U)
+#define RCC_PERIPHCLK_USART2 (0x00000002U)
+#define RCC_PERIPHCLK_USART3 (0x00000004U)
+#define RCC_PERIPHCLK_UART4 (0x00000008U)
+#define RCC_PERIPHCLK_UART5 (0x00000010U)
+#define RCC_PERIPHCLK_I2C1 (0x00000020U)
+#define RCC_PERIPHCLK_I2C2 (0x00000040U)
+#define RCC_PERIPHCLK_ADC12 (0x00000080U)
+#define RCC_PERIPHCLK_ADC34 (0x00000100U)
+#define RCC_PERIPHCLK_I2S (0x00000200U)
+#define RCC_PERIPHCLK_TIM1 (0x00001000U)
+#define RCC_PERIPHCLK_TIM8 (0x00002000U)
+#define RCC_PERIPHCLK_RTC (0x00010000U)
+#define RCC_PERIPHCLK_I2C3 (0x00040000U)
+#define RCC_PERIPHCLK_TIM2 (0x00100000U)
+#define RCC_PERIPHCLK_TIM34 (0x00200000U)
+#define RCC_PERIPHCLK_TIM15 (0x00400000U)
+#define RCC_PERIPHCLK_TIM16 (0x00800000U)
+#define RCC_PERIPHCLK_TIM17 (0x01000000U)
+#define RCC_PERIPHCLK_TIM20 (0x02000000U)
+
+
+#endif /* STM32F398xx */
+
+#if defined(STM32F358xx)
+#define RCC_PERIPHCLK_USART1 (0x00000001U)
+#define RCC_PERIPHCLK_USART2 (0x00000002U)
+#define RCC_PERIPHCLK_USART3 (0x00000004U)
+#define RCC_PERIPHCLK_UART4 (0x00000008U)
+#define RCC_PERIPHCLK_UART5 (0x00000010U)
+#define RCC_PERIPHCLK_I2C1 (0x00000020U)
+#define RCC_PERIPHCLK_I2C2 (0x00000040U)
+#define RCC_PERIPHCLK_ADC12 (0x00000080U)
+#define RCC_PERIPHCLK_ADC34 (0x00000100U)
+#define RCC_PERIPHCLK_I2S (0x00000200U)
+#define RCC_PERIPHCLK_TIM1 (0x00001000U)
+#define RCC_PERIPHCLK_TIM8 (0x00002000U)
+#define RCC_PERIPHCLK_RTC (0x00010000U)
+
+#endif /* STM32F358xx */
+
+#if defined(STM32F303x8)
+#define RCC_PERIPHCLK_USART1 (0x00000001U)
+#define RCC_PERIPHCLK_I2C1 (0x00000020U)
+#define RCC_PERIPHCLK_ADC12 (0x00000080U)
+#define RCC_PERIPHCLK_TIM1 (0x00001000U)
+#define RCC_PERIPHCLK_RTC (0x00010000U)
+
+#endif /* STM32F303x8 */
+
+#if defined(STM32F334x8)
+#define RCC_PERIPHCLK_USART1 (0x00000001U)
+#define RCC_PERIPHCLK_I2C1 (0x00000020U)
+#define RCC_PERIPHCLK_ADC12 (0x00000080U)
+#define RCC_PERIPHCLK_TIM1 (0x00001000U)
+#define RCC_PERIPHCLK_HRTIM1 (0x00004000U)
+#define RCC_PERIPHCLK_RTC (0x00010000U)
+
+
+#endif /* STM32F334x8 */
+
+#if defined(STM32F328xx)
+#define RCC_PERIPHCLK_USART1 (0x00000001U)
+#define RCC_PERIPHCLK_I2C1 (0x00000020U)
+#define RCC_PERIPHCLK_ADC12 (0x00000080U)
+#define RCC_PERIPHCLK_TIM1 (0x00001000U)
+#define RCC_PERIPHCLK_RTC (0x00010000U)
+
+#endif /* STM32F328xx */
+
+#if defined(STM32F373xC)
+#define RCC_PERIPHCLK_USART1 (0x00000001U)
+#define RCC_PERIPHCLK_USART2 (0x00000002U)
+#define RCC_PERIPHCLK_USART3 (0x00000004U)
+#define RCC_PERIPHCLK_I2C1 (0x00000020U)
+#define RCC_PERIPHCLK_I2C2 (0x00000040U)
+#define RCC_PERIPHCLK_ADC1 (0x00000080U)
+#define RCC_PERIPHCLK_CEC (0x00000400U)
+#define RCC_PERIPHCLK_SDADC (0x00000800U)
+#define RCC_PERIPHCLK_RTC (0x00010000U)
+#define RCC_PERIPHCLK_USB (0x00020000U)
+
+#endif /* STM32F373xC */
+
+#if defined(STM32F378xx)
+#define RCC_PERIPHCLK_USART1 (0x00000001U)
+#define RCC_PERIPHCLK_USART2 (0x00000002U)
+#define RCC_PERIPHCLK_USART3 (0x00000004U)
+#define RCC_PERIPHCLK_I2C1 (0x00000020U)
+#define RCC_PERIPHCLK_I2C2 (0x00000040U)
+#define RCC_PERIPHCLK_ADC1 (0x00000080U)
+#define RCC_PERIPHCLK_CEC (0x00000400U)
+#define RCC_PERIPHCLK_SDADC (0x00000800U)
+#define RCC_PERIPHCLK_RTC (0x00010000U)
+
+#endif /* STM32F378xx */
+/**
+ * @}
+ */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+
+/** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
+ * @{
+ */
+#define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK1
+#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
+#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
+#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
+ * @{
+ */
+#define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
+#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_I2C3_Clock_Source RCC Extended I2C3 Clock Source
+ * @{
+ */
+#define RCC_I2C3CLKSOURCE_HSI RCC_CFGR3_I2C3SW_HSI
+#define RCC_I2C3CLKSOURCE_SYSCLK RCC_CFGR3_I2C3SW_SYSCLK
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_ADC1_Clock_Source RCC Extended ADC1 Clock Source
+ * @{
+ */
+#define RCC_ADC1PLLCLK_OFF RCC_CFGR2_ADC1PRES_NO
+#define RCC_ADC1PLLCLK_DIV1 RCC_CFGR2_ADC1PRES_DIV1
+#define RCC_ADC1PLLCLK_DIV2 RCC_CFGR2_ADC1PRES_DIV2
+#define RCC_ADC1PLLCLK_DIV4 RCC_CFGR2_ADC1PRES_DIV4
+#define RCC_ADC1PLLCLK_DIV6 RCC_CFGR2_ADC1PRES_DIV6
+#define RCC_ADC1PLLCLK_DIV8 RCC_CFGR2_ADC1PRES_DIV8
+#define RCC_ADC1PLLCLK_DIV10 RCC_CFGR2_ADC1PRES_DIV10
+#define RCC_ADC1PLLCLK_DIV12 RCC_CFGR2_ADC1PRES_DIV12
+#define RCC_ADC1PLLCLK_DIV16 RCC_CFGR2_ADC1PRES_DIV16
+#define RCC_ADC1PLLCLK_DIV32 RCC_CFGR2_ADC1PRES_DIV32
+#define RCC_ADC1PLLCLK_DIV64 RCC_CFGR2_ADC1PRES_DIV64
+#define RCC_ADC1PLLCLK_DIV128 RCC_CFGR2_ADC1PRES_DIV128
+#define RCC_ADC1PLLCLK_DIV256 RCC_CFGR2_ADC1PRES_DIV256
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source
+ * @{
+ */
+#define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK
+#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
+ * @{
+ */
+#define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
+#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_TIM15_Clock_Source RCC Extended TIM15 Clock Source
+ * @{
+ */
+#define RCC_TIM15CLK_HCLK RCC_CFGR3_TIM15SW_HCLK
+#define RCC_TIM15CLK_PLLCLK RCC_CFGR3_TIM15SW_PLL
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_TIM16_Clock_Source RCC Extended TIM16 Clock Source
+ * @{
+ */
+#define RCC_TIM16CLK_HCLK RCC_CFGR3_TIM16SW_HCLK
+#define RCC_TIM16CLK_PLLCLK RCC_CFGR3_TIM16SW_PLL
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_TIM17_Clock_Source RCC Extended TIM17 Clock Source
+ * @{
+ */
+#define RCC_TIM17CLK_HCLK RCC_CFGR3_TIM17SW_HCLK
+#define RCC_TIM17CLK_PLLCLK RCC_CFGR3_TIM17SW_PLL
+
+/**
+ * @}
+ */
+
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+
+/** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
+ * @{
+ */
+#define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK2
+#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
+#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
+#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
+ * @{
+ */
+#define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
+#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source
+ * @{
+ */
+
+/* ADC1 & ADC2 */
+#define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO
+#define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1
+#define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2
+#define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4
+#define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6
+#define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8
+#define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10
+#define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12
+#define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16
+#define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32
+#define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64
+#define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128
+#define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source
+ * @{
+ */
+#define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK
+#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT
+
+/**
+ * @}
+ */
+/** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
+ * @{
+ */
+#define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
+#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_UART4_Clock_Source RCC Extended UART4 Clock Source
+ * @{
+ */
+#define RCC_UART4CLKSOURCE_PCLK1 RCC_CFGR3_UART4SW_PCLK
+#define RCC_UART4CLKSOURCE_SYSCLK RCC_CFGR3_UART4SW_SYSCLK
+#define RCC_UART4CLKSOURCE_LSE RCC_CFGR3_UART4SW_LSE
+#define RCC_UART4CLKSOURCE_HSI RCC_CFGR3_UART4SW_HSI
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_UART5_Clock_Source RCC Extended UART5 Clock Source
+ * @{
+ */
+#define RCC_UART5CLKSOURCE_PCLK1 RCC_CFGR3_UART5SW_PCLK
+#define RCC_UART5CLKSOURCE_SYSCLK RCC_CFGR3_UART5SW_SYSCLK
+#define RCC_UART5CLKSOURCE_LSE RCC_CFGR3_UART5SW_LSE
+#define RCC_UART5CLKSOURCE_HSI RCC_CFGR3_UART5SW_HSI
+
+/**
+ * @}
+ */
+
+#endif /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+
+/** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
+ * @{
+ */
+#define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK2
+#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
+#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
+#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
+ * @{
+ */
+#define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
+#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_I2C3_Clock_Source RCC Extended I2C3 Clock Source
+ * @{
+ */
+#define RCC_I2C3CLKSOURCE_HSI RCC_CFGR3_I2C3SW_HSI
+#define RCC_I2C3CLKSOURCE_SYSCLK RCC_CFGR3_I2C3SW_SYSCLK
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source
+ * @{
+ */
+
+/* ADC1 & ADC2 */
+#define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO
+#define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1
+#define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2
+#define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4
+#define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6
+#define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8
+#define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10
+#define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12
+#define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16
+#define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32
+#define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64
+#define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128
+#define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source
+ * @{
+ */
+#define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK
+#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
+ * @{
+ */
+#define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
+#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_TIM2_Clock_Source RCC Extended TIM2 Clock Source
+ * @{
+ */
+#define RCC_TIM2CLK_HCLK RCC_CFGR3_TIM2SW_HCLK
+#define RCC_TIM2CLK_PLLCLK RCC_CFGR3_TIM2SW_PLL
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_TIM34_Clock_Source RCC Extended TIM3 & TIM4 Clock Source
+ * @{
+ */
+#define RCC_TIM34CLK_HCLK RCC_CFGR3_TIM34SW_HCLK
+#define RCC_TIM34CLK_PLLCLK RCC_CFGR3_TIM34SW_PLL
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_TIM15_Clock_Source RCC Extended TIM15 Clock Source
+ * @{
+ */
+#define RCC_TIM15CLK_HCLK RCC_CFGR3_TIM15SW_HCLK
+#define RCC_TIM15CLK_PLLCLK RCC_CFGR3_TIM15SW_PLL
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_TIM16_Clock_Source RCC Extended TIM16 Clock Source
+ * @{
+ */
+#define RCC_TIM16CLK_HCLK RCC_CFGR3_TIM16SW_HCLK
+#define RCC_TIM16CLK_PLLCLK RCC_CFGR3_TIM16SW_PLL
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_TIM17_Clock_Source RCC Extended TIM17 Clock Source
+ * @{
+ */
+#define RCC_TIM17CLK_HCLK RCC_CFGR3_TIM17SW_HCLK
+#define RCC_TIM17CLK_PLLCLK RCC_CFGR3_TIM17SW_PLL
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_UART4_Clock_Source RCC Extended UART4 Clock Source
+ * @{
+ */
+#define RCC_UART4CLKSOURCE_PCLK1 RCC_CFGR3_UART4SW_PCLK
+#define RCC_UART4CLKSOURCE_SYSCLK RCC_CFGR3_UART4SW_SYSCLK
+#define RCC_UART4CLKSOURCE_LSE RCC_CFGR3_UART4SW_LSE
+#define RCC_UART4CLKSOURCE_HSI RCC_CFGR3_UART4SW_HSI
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_UART5_Clock_Source RCC Extended UART5 Clock Source
+ * @{
+ */
+#define RCC_UART5CLKSOURCE_PCLK1 RCC_CFGR3_UART5SW_PCLK
+#define RCC_UART5CLKSOURCE_SYSCLK RCC_CFGR3_UART5SW_SYSCLK
+#define RCC_UART5CLKSOURCE_LSE RCC_CFGR3_UART5SW_LSE
+#define RCC_UART5CLKSOURCE_HSI RCC_CFGR3_UART5SW_HSI
+
+/**
+ * @}
+ */
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)
+/** @defgroup RCCEx_TIM20_Clock_Source RCC Extended TIM20 Clock Source
+ * @{
+ */
+#define RCC_TIM20CLK_HCLK RCC_CFGR3_TIM20SW_HCLK
+#define RCC_TIM20CLK_PLLCLK RCC_CFGR3_TIM20SW_PLL
+
+/**
+ * @}
+ */
+#endif /* STM32F303xE || STM32F398xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F303xC) || defined(STM32F358xx)
+
+/** @defgroup RCCEx_ADC34_Clock_Source RCC Extended ADC34 Clock Source
+ * @{
+ */
+
+/* ADC3 & ADC4 */
+#define RCC_ADC34PLLCLK_OFF RCC_CFGR2_ADCPRE34_NO
+#define RCC_ADC34PLLCLK_DIV1 RCC_CFGR2_ADCPRE34_DIV1
+#define RCC_ADC34PLLCLK_DIV2 RCC_CFGR2_ADCPRE34_DIV2
+#define RCC_ADC34PLLCLK_DIV4 RCC_CFGR2_ADCPRE34_DIV4
+#define RCC_ADC34PLLCLK_DIV6 RCC_CFGR2_ADCPRE34_DIV6
+#define RCC_ADC34PLLCLK_DIV8 RCC_CFGR2_ADCPRE34_DIV8
+#define RCC_ADC34PLLCLK_DIV10 RCC_CFGR2_ADCPRE34_DIV10
+#define RCC_ADC34PLLCLK_DIV12 RCC_CFGR2_ADCPRE34_DIV12
+#define RCC_ADC34PLLCLK_DIV16 RCC_CFGR2_ADCPRE34_DIV16
+#define RCC_ADC34PLLCLK_DIV32 RCC_CFGR2_ADCPRE34_DIV32
+#define RCC_ADC34PLLCLK_DIV64 RCC_CFGR2_ADCPRE34_DIV64
+#define RCC_ADC34PLLCLK_DIV128 RCC_CFGR2_ADCPRE34_DIV128
+#define RCC_ADC34PLLCLK_DIV256 RCC_CFGR2_ADCPRE34_DIV256
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_TIM8_Clock_Source RCC Extended TIM8 Clock Source
+ * @{
+ */
+#define RCC_TIM8CLK_HCLK RCC_CFGR3_TIM8SW_HCLK
+#define RCC_TIM8CLK_PLLCLK RCC_CFGR3_TIM8SW_PLL
+
+/**
+ * @}
+ */
+
+#endif /* STM32F303xC || STM32F303xE || STM32F398xx || STM32F358xx */
+
+#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+
+/** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
+ * @{
+ */
+#define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK1
+#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
+#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
+#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source
+ * @{
+ */
+/* ADC1 & ADC2 */
+#define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO
+#define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1
+#define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2
+#define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4
+#define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6
+#define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8
+#define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10
+#define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12
+#define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16
+#define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32
+#define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64
+#define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128
+#define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
+ * @{
+ */
+#define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
+#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
+
+/**
+ * @}
+ */
+
+#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F334x8)
+
+/** @defgroup RCCEx_HRTIM1_Clock_Source RCC Extended HRTIM1 Clock Source
+ * @{
+ */
+#define RCC_HRTIM1CLK_HCLK RCC_CFGR3_HRTIM1SW_HCLK
+#define RCC_HRTIM1CLK_PLLCLK RCC_CFGR3_HRTIM1SW_PLL
+
+/**
+ * @}
+ */
+
+#endif /* STM32F334x8 */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+
+/** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
+ * @{
+ */
+#define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK2
+#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
+#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
+#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
+ * @{
+ */
+#define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
+#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_ADC1_Clock_Source RCC Extended ADC1 Clock Source
+ * @{
+ */
+
+/* ADC1 */
+#define RCC_ADC1PCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2
+#define RCC_ADC1PCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4
+#define RCC_ADC1PCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6
+#define RCC_ADC1PCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_CEC_Clock_Source RCC Extended CEC Clock Source
+ * @{
+ */
+#define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244
+#define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_SDADC_Clock_Prescaler RCC Extended SDADC Clock Prescaler
+ * @{
+ */
+#define RCC_SDADCSYSCLK_DIV1 RCC_CFGR_SDPRE_DIV1
+#define RCC_SDADCSYSCLK_DIV2 RCC_CFGR_SDPRE_DIV2
+#define RCC_SDADCSYSCLK_DIV4 RCC_CFGR_SDPRE_DIV4
+#define RCC_SDADCSYSCLK_DIV6 RCC_CFGR_SDPRE_DIV6
+#define RCC_SDADCSYSCLK_DIV8 RCC_CFGR_SDPRE_DIV8
+#define RCC_SDADCSYSCLK_DIV10 RCC_CFGR_SDPRE_DIV10
+#define RCC_SDADCSYSCLK_DIV12 RCC_CFGR_SDPRE_DIV12
+#define RCC_SDADCSYSCLK_DIV14 RCC_CFGR_SDPRE_DIV14
+#define RCC_SDADCSYSCLK_DIV16 RCC_CFGR_SDPRE_DIV16
+#define RCC_SDADCSYSCLK_DIV20 RCC_CFGR_SDPRE_DIV20
+#define RCC_SDADCSYSCLK_DIV24 RCC_CFGR_SDPRE_DIV24
+#define RCC_SDADCSYSCLK_DIV28 RCC_CFGR_SDPRE_DIV28
+#define RCC_SDADCSYSCLK_DIV32 RCC_CFGR_SDPRE_DIV32
+#define RCC_SDADCSYSCLK_DIV36 RCC_CFGR_SDPRE_DIV36
+#define RCC_SDADCSYSCLK_DIV40 RCC_CFGR_SDPRE_DIV40
+#define RCC_SDADCSYSCLK_DIV44 RCC_CFGR_SDPRE_DIV44
+#define RCC_SDADCSYSCLK_DIV48 RCC_CFGR_SDPRE_DIV48
+
+/**
+ * @}
+ */
+
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE)\
+ || defined(STM32F302xC) || defined(STM32F303xC)\
+ || defined(STM32F302x8) \
+ || defined(STM32F373xC)
+/** @defgroup RCCEx_USB_Clock_Source RCC Extended USB Clock Source
+ * @{
+ */
+
+#define RCC_USBCLKSOURCE_PLL RCC_CFGR_USBPRE_DIV1
+#define RCC_USBCLKSOURCE_PLL_DIV1_5 RCC_CFGR_USBPRE_DIV1_5
+
+/**
+ * @}
+ */
+
+#endif /* STM32F302xE || STM32F303xE || */
+ /* STM32F302xC || STM32F303xC || */
+ /* STM32F302x8 || */
+ /* STM32F373xC */
+
+
+/** @defgroup RCCEx_MCOx_Clock_Prescaler RCC Extended MCOx Clock Prescaler
+ * @{
+ */
+#if defined(RCC_CFGR_MCOPRE)
+
+#define RCC_MCODIV_1 (0x00000000U)
+#define RCC_MCODIV_2 (0x10000000U)
+#define RCC_MCODIV_4 (0x20000000U)
+#define RCC_MCODIV_8 (0x30000000U)
+#define RCC_MCODIV_16 (0x40000000U)
+#define RCC_MCODIV_32 (0x50000000U)
+#define RCC_MCODIV_64 (0x60000000U)
+#define RCC_MCODIV_128 (0x70000000U)
+
+#else
+
+#define RCC_MCODIV_1 (0x00000000U)
+
+#endif /* RCC_CFGR_MCOPRE */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_LSEDrive_Configuration RCC LSE Drive Configuration
+ * @{
+ */
+
+#define RCC_LSEDRIVE_LOW (0x00000000U) /*!< Xtal mode lower driving capability */
+#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium low driving capability */
+#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium high driving capability */
+#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Macros RCC Extended Exported Macros
+ * @{
+ */
+
+/** @defgroup RCCEx_PLL_Configuration RCC Extended PLL Configuration
+ * @{
+ */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+/** @brief Macro to configure the PLL clock source, multiplication and division factors.
+ * @note This macro must be used only when the PLL is disabled.
+ *
+ * @param __RCC_PLLSource__ specifies the PLL entry clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
+ * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
+ * @param __PREDIV__ specifies the predivider factor for PLL VCO input clock
+ * This parameter must be a number between RCC_PREDIV_DIV1 and RCC_PREDIV_DIV16.
+ * @param __PLLMUL__ specifies the multiplication factor for PLL VCO input clock
+ * This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.
+ *
+ */
+#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PREDIV__, __PLLMUL__) \
+ do { \
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSource__))); \
+ } while(0U)
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+
+#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
+ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
+ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\
+ || defined(STM32F373xC) || defined(STM32F378xx)
+/** @brief Macro to configure the PLL clock source and multiplication factor.
+ * @note This macro must be used only when the PLL is disabled.
+ *
+ * @param __RCC_PLLSource__ specifies the PLL entry clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
+ * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
+ * @param __PLLMUL__ specifies the multiplication factor for PLL VCO input clock
+ * This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.
+ *
+ */
+#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PLLMUL__) \
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSource__)))
+#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+ /* STM32F373xC || STM32F378xx */
+/**
+ * @}
+ */
+
+#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
+ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
+ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\
+ || defined(STM32F373xC) || defined(STM32F378xx)
+/** @defgroup RCCEx_HSE_Configuration RCC Extended HSE Configuration
+ * @{
+ */
+
+/**
+ * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
+ * @note Predivision factor can not be changed if PLL is used as system clock
+ * In this case, you have to select another source of the system clock, disable the PLL and
+ * then change the HSE predivision factor.
+ * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE.
+ * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.
+ */
+#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSE_PREDIV_VALUE__))
+
+/**
+ * @brief Macro to get prediv1 factor for PLL.
+ */
+#define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV)
+
+/**
+ * @}
+ */
+#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+ /* STM32F373xC || STM32F378xx */
+
+/** @defgroup RCCEx_AHB_Clock_Enable_Disable RCC Extended AHB Clock Enable Disable
+ * @brief Enable or disable the AHB peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_ADC1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC1EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+
+#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC1EN))
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_ADC12_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+/* Aliases for STM32 F3 compatibility */
+#define __HAL_RCC_ADC1_CLK_ENABLE() __HAL_RCC_ADC12_CLK_ENABLE()
+#define __HAL_RCC_ADC2_CLK_ENABLE() __HAL_RCC_ADC12_CLK_ENABLE()
+
+#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
+#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
+#define __HAL_RCC_ADC12_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC12EN))
+/* Aliases for STM32 F3 compatibility */
+#define __HAL_RCC_ADC1_CLK_DISABLE() __HAL_RCC_ADC12_CLK_DISABLE()
+#define __HAL_RCC_ADC2_CLK_DISABLE() __HAL_RCC_ADC12_CLK_DISABLE()
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_RCC_ADC34_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_ADC34EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC34EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_ADC34_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC34EN))
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define __HAL_RCC_ADC12_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+/* Aliases for STM32 F3 compatibility */
+#define __HAL_RCC_ADC1_CLK_ENABLE() __HAL_RCC_ADC12_CLK_ENABLE()
+#define __HAL_RCC_ADC2_CLK_ENABLE() __HAL_RCC_ADC12_CLK_ENABLE()
+
+#define __HAL_RCC_ADC12_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC12EN))
+/* Aliases for STM32 F3 compatibility */
+#define __HAL_RCC_ADC1_CLK_DISABLE() __HAL_RCC_ADC12_CLK_DISABLE()
+#define __HAL_RCC_ADC2_CLK_DISABLE() __HAL_RCC_ADC12_CLK_DISABLE()
+#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+
+#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
+#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+#define __HAL_RCC_FMC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_FMCEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FMCEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+
+#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FMCEN))
+#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOGEN))
+#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOHEN))
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_Clock_Enable_Disable RCC Extended APB1 Clock Enable Disable
+ * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+
+#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
+#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
+#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
+#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_UART4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_UART5_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+
+#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
+#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
+#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
+#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
+#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
+#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
+#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_DAC2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+
+#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
+#define __HAL_RCC_DAC2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC2EN))
+#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM18_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM18EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM18EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_DAC2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_CEC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+
+#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
+#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
+#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
+#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
+#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
+#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
+#define __HAL_RCC_TIM18_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM18EN))
+#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
+#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
+#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
+#define __HAL_RCC_DAC2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC2EN))
+#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx) \
+ || defined(STM32F303xC) || defined(STM32F358xx) \
+ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
+ || defined(STM32F373xC) || defined(STM32F378xx)
+#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+
+#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE)\
+ || defined(STM32F302xC) || defined(STM32F303xC)\
+ || defined(STM32F302x8) \
+ || defined(STM32F373xC)
+#define __HAL_RCC_USB_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+
+#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
+#endif /* STM32F302xE || STM32F303xE || */
+ /* STM32F302xC || STM32F303xC || */
+ /* STM32F302x8 || */
+ /* STM32F373xC */
+
+#if !defined(STM32F301x8)
+#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+
+#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN))
+#endif /* STM32F301x8*/
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+
+#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_Clock_Enable_Disable RCC Extended APB2 Clock Enable Disable
+ * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+
+#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+
+#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+
+#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
+#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F334x8)
+#define __HAL_RCC_HRTIM1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+
+#define __HAL_RCC_HRTIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_HRTIM1EN))
+#endif /* STM32F334x8 */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM19_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM19EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM19EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_SDADC1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC1EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_SDADC2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC2EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_SDADC3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC3EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+
+#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
+#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
+#define __HAL_RCC_TIM19_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM19EN))
+#define __HAL_RCC_SDADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC1EN))
+#define __HAL_RCC_SDADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC2EN))
+#define __HAL_RCC_SDADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC3EN))
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
+ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
+ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+
+#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+
+#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)
+#define __HAL_RCC_TIM20_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM20_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM20EN))
+#endif /* STM32F303xE || STM32F398xx */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB_Peripheral_Clock_Enable_Disable_Status RCC Extended AHB Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the AHB peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC1EN)) != RESET)
+
+#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC1EN)) == RESET)
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)
+#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != RESET)
+#define __HAL_RCC_ADC12_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC12EN)) != RESET)
+
+#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)
+#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == RESET)
+#define __HAL_RCC_ADC12_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC12EN)) == RESET)
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_RCC_ADC34_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC34EN)) != RESET)
+
+#define __HAL_RCC_ADC34_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC34EN)) == RESET)
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define __HAL_RCC_ADC12_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC12EN)) != RESET)
+
+#define __HAL_RCC_ADC12_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC12EN)) == RESET)
+#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)
+#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != RESET)
+
+#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)
+#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == RESET)
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FMCEN)) != RESET)
+#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) != RESET)
+#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOHEN)) != RESET)
+
+#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FMCEN)) == RESET)
+#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) == RESET)
+#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOHEN)) == RESET)
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_Clock_Enable_Disable_Status RCC Extended APB1 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the APB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
+#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
+#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
+#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
+
+#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
+#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
+#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
+#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
+#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
+#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
+#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
+#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
+#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
+#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
+
+#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
+#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
+#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
+#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
+#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
+#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
+#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
+#define __HAL_RCC_DAC2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC2EN)) != RESET)
+
+#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
+#define __HAL_RCC_DAC2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC2EN)) == RESET)
+#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
+#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
+#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
+#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
+#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
+#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
+#define __HAL_RCC_TIM18_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM18EN)) != RESET)
+#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
+#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
+#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
+#define __HAL_RCC_DAC2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC2EN)) != RESET)
+#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
+
+#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
+#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
+#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
+#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
+#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
+#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
+#define __HAL_RCC_TIM18_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM18EN)) == RESET)
+#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
+#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
+#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
+#define __HAL_RCC_DAC2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC2EN)) == RESET)
+#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx) \
+ || defined(STM32F303xC) || defined(STM32F358xx) \
+ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
+ || defined(STM32F373xC) || defined(STM32F378xx)
+#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
+
+#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE)\
+ || defined(STM32F302xC) || defined(STM32F303xC)\
+ || defined(STM32F302x8) \
+ || defined(STM32F373xC)
+#define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET)
+
+#define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET)
+#endif /* STM32F302xE || STM32F303xE || */
+ /* STM32F302xC || STM32F303xC || */
+ /* STM32F302x8 || */
+ /* STM32F373xC */
+
+#if !defined(STM32F301x8)
+#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CANEN)) != RESET)
+
+#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CANEN)) == RESET)
+#endif /* STM32F301x8*/
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
+
+#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_Clock_Enable_Disable_Status RCC Extended APB2 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the APB2 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
+
+#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
+
+#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
+
+#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
+#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F334x8)
+#define __HAL_RCC_HRTIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_HRTIM1EN)) != RESET)
+
+#define __HAL_RCC_HRTIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_HRTIM1EN)) == RESET)
+#endif /* STM32F334x8 */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
+#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
+#define __HAL_RCC_TIM19_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM19EN)) != RESET)
+#define __HAL_RCC_SDADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC1EN)) != RESET)
+#define __HAL_RCC_SDADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC2EN)) != RESET)
+#define __HAL_RCC_SDADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC3EN)) != RESET)
+
+#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
+#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
+#define __HAL_RCC_TIM19_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM19EN)) == RESET)
+#define __HAL_RCC_SDADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC1EN)) == RESET)
+#define __HAL_RCC_SDADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC2EN)) == RESET)
+#define __HAL_RCC_SDADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC3EN)) == RESET)
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
+ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
+ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
+
+#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
+
+#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)
+#define __HAL_RCC_TIM20_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM20EN)) != RESET)
+
+#define __HAL_RCC_TIM20_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM20EN)) == RESET)
+#endif /* STM32F303xE || STM32F398xx */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB_Force_Release_Reset RCC Extended AHB Force Release Reset
+ * @brief Force or release AHB peripheral reset.
+ * @{
+ */
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC1RST))
+
+#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC1RST))
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST))
+#define __HAL_RCC_ADC12_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC12RST))
+/* Aliases for STM32 F3 compatibility */
+#define __HAL_RCC_ADC1_FORCE_RESET() __HAL_RCC_ADC12_FORCE_RESET()
+#define __HAL_RCC_ADC2_FORCE_RESET() __HAL_RCC_ADC12_FORCE_RESET()
+
+#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
+#define __HAL_RCC_ADC12_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC12RST))
+/* Aliases for STM32 F3 compatibility */
+#define __HAL_RCC_ADC1_RELEASE_RESET() __HAL_RCC_ADC12_RELEASE_RESET()
+#define __HAL_RCC_ADC2_RELEASE_RESET() __HAL_RCC_ADC12_RELEASE_RESET()
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_RCC_ADC34_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC34RST))
+
+#define __HAL_RCC_ADC34_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC34RST))
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define __HAL_RCC_ADC12_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC12RST))
+/* Aliases for STM32 F3 compatibility */
+#define __HAL_RCC_ADC1_FORCE_RESET() __HAL_RCC_ADC12_FORCE_RESET()
+#define __HAL_RCC_ADC2_FORCE_RESET() __HAL_RCC_ADC12_FORCE_RESET()
+
+#define __HAL_RCC_ADC12_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC12RST))
+/* Aliases for STM32 F3 compatibility */
+#define __HAL_RCC_ADC1_RELEASE_RESET() __HAL_RCC_ADC12_RELEASE_RESET()
+#define __HAL_RCC_ADC2_RELEASE_RESET() __HAL_RCC_ADC12_RELEASE_RESET()
+#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST))
+
+#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_FMCRST))
+#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOGRST))
+#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOHRST))
+
+#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FMCRST))
+#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOGRST))
+#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOHRST))
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_Force_Release_Reset RCC Extended APB1 Force Release Reset
+ * @brief Force or release APB1 peripheral reset.
+ * @{
+ */
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
+#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
+#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
+
+#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
+#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
+#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
+#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
+#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
+#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
+
+#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
+#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
+#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
+#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_DAC2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC2RST))
+
+#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_DAC2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC2RST))
+#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
+#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
+#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
+#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
+#define __HAL_RCC_TIM18_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM18RST))
+#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
+#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
+#define __HAL_RCC_DAC2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC2RST))
+#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
+
+#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
+#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
+#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
+#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
+#define __HAL_RCC_TIM18_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM18RST))
+#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
+#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
+#define __HAL_RCC_DAC2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC2RST))
+#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F303xC) || defined(STM32F358xx)\
+ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
+ || defined(STM32F373xC) || defined(STM32F378xx)
+#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
+
+#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE)\
+ || defined(STM32F302xC) || defined(STM32F303xC)\
+ || defined(STM32F302x8) \
+ || defined(STM32F373xC)
+#define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
+
+#define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
+#endif /* STM32F302xE || STM32F303xE || */
+ /* STM32F302xC || STM32F303xC || */
+ /* STM32F302x8 || */
+ /* STM32F373xC */
+
+#if !defined(STM32F301x8)
+#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CANRST))
+
+#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST))
+#endif /* STM32F301x8*/
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
+
+#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_Force_Release_Reset RCC Extended APB2 Force Release Reset
+ * @brief Force or release APB2 peripheral reset.
+ * @{
+ */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
+
+#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
+
+#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
+
+#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
+#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F334x8)
+#define __HAL_RCC_HRTIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_HRTIM1RST))
+
+#define __HAL_RCC_HRTIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_HRTIM1RST))
+#endif /* STM32F334x8 */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
+#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
+#define __HAL_RCC_TIM19_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM19RST))
+#define __HAL_RCC_SDADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC1RST))
+#define __HAL_RCC_SDADC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC2RST))
+#define __HAL_RCC_SDADC3_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC3RST))
+
+#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
+#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
+#define __HAL_RCC_TIM19_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM19RST))
+#define __HAL_RCC_SDADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC1RST))
+#define __HAL_RCC_SDADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC2RST))
+#define __HAL_RCC_SDADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC3RST))
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
+ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
+ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
+
+#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
+
+#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)
+#define __HAL_RCC_TIM20_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM20RST))
+
+#define __HAL_RCC_TIM20_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM20RST))
+#endif /* STM32F303xE || STM32F398xx */
+
+/**
+ * @}
+ */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
+ * @{
+ */
+
+/** @brief Macro to configure the I2C2 clock (I2C2CLK).
+ * @param __I2C2CLKSource__ specifies the I2C2 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
+ * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
+ */
+#define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))
+
+/** @brief Macro to get the I2C2 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
+ * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
+ */
+#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
+
+/** @brief Macro to configure the I2C3 clock (I2C3CLK).
+ * @param __I2C3CLKSource__ specifies the I2C3 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
+ * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
+ */
+#define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C3SW, (uint32_t)(__I2C3CLKSource__))
+
+/** @brief Macro to get the I2C3 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
+ * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
+ */
+#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C3SW)))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
+ * @{
+ */
+/** @brief Macro to configure the TIM1 clock (TIM1CLK).
+ * @param __TIM1CLKSource__ specifies the TIM1 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock
+ * @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock
+ */
+#define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__))
+
+/** @brief Macro to get the TIM1 clock (TIM1CLK).
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock
+ * @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock
+ */
+#define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW)))
+
+/** @brief Macro to configure the TIM15 clock (TIM15CLK).
+ * @param __TIM15CLKSource__ specifies the TIM15 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_TIM15CLK_HCLK HCLK selected as TIM15 clock
+ * @arg @ref RCC_TIM15CLK_PLL PLL Clock selected as TIM15 clock
+ */
+#define __HAL_RCC_TIM15_CONFIG(__TIM15CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM15SW, (uint32_t)(__TIM15CLKSource__))
+
+/** @brief Macro to get the TIM15 clock (TIM15CLK).
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_TIM15CLK_HCLK HCLK selected as TIM15 clock
+ * @arg @ref RCC_TIM15CLK_PLL PLL Clock selected as TIM15 clock
+ */
+#define __HAL_RCC_GET_TIM15_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM15SW)))
+
+/** @brief Macro to configure the TIM16 clock (TIM16CLK).
+ * @param __TIM16CLKSource__ specifies the TIM16 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_TIM16CLK_HCLK HCLK selected as TIM16 clock
+ * @arg @ref RCC_TIM16CLK_PLL PLL Clock selected as TIM16 clock
+ */
+#define __HAL_RCC_TIM16_CONFIG(__TIM16CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM16SW, (uint32_t)(__TIM16CLKSource__))
+
+/** @brief Macro to get the TIM16 clock (TIM16CLK).
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_TIM16CLK_HCLK HCLK selected as TIM16 clock
+ * @arg @ref RCC_TIM16CLK_PLL PLL Clock selected as TIM16 clock
+ */
+#define __HAL_RCC_GET_TIM16_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM16SW)))
+
+/** @brief Macro to configure the TIM17 clock (TIM17CLK).
+ * @param __TIM17CLKSource__ specifies the TIM17 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_TIM17CLK_HCLK HCLK selected as TIM17 clock
+ * @arg @ref RCC_TIM17CLK_PLL PLL Clock selected as TIM17 clock
+ */
+#define __HAL_RCC_TIM17_CONFIG(__TIM17CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM17SW, (uint32_t)(__TIM17CLKSource__))
+
+/** @brief Macro to get the TIM17 clock (TIM17CLK).
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_TIM17CLK_HCLK HCLK selected as TIM17 clock
+ * @arg @ref RCC_TIM17CLK_PLL PLL Clock selected as TIM17 clock
+ */
+#define __HAL_RCC_GET_TIM17_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM17SW)))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_I2Sx_Clock_Config RCC Extended I2Sx Clock Config
+ * @{
+ */
+/** @brief Macro to configure the I2S clock source (I2SCLK).
+ * @note This function must be called before enabling the I2S APB clock.
+ * @param __I2SCLKSource__ specifies the I2S clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_I2SCLKSOURCE_SYSCLK SYSCLK clock used as I2S clock source
+ * @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin
+ * used as I2S clock source
+ */
+#define __HAL_RCC_I2S_CONFIG(__I2SCLKSource__) \
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, (uint32_t)(__I2SCLKSource__))
+
+/** @brief Macro to get the I2S clock source (I2SCLK).
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_I2SCLKSOURCE_SYSCLK SYSCLK clock used as I2S clock source
+ * @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin
+ * used as I2S clock source
+ */
+#define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
+ * @{
+ */
+
+/** @brief Macro to configure the ADC1 clock (ADC1CLK).
+ * @param __ADC1CLKSource__ specifies the ADC1 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_ADC1PLLCLK_OFF ADC1 PLL clock disabled, ADC1 can use AHB clock
+ * @arg @ref RCC_ADC1PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 clock
+ */
+#define __HAL_RCC_ADC1_CONFIG(__ADC1CLKSource__) \
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADC1PRES, (uint32_t)(__ADC1CLKSource__))
+
+/** @brief Macro to get the ADC1 clock
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_ADC1PLLCLK_OFF ADC1 PLL clock disabled, ADC1 can use AHB clock
+ * @arg @ref RCC_ADC1PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 clock
+ */
+#define __HAL_RCC_GET_ADC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADC1PRES)))
+/**
+ * @}
+ */
+
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+/** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
+ * @{
+ */
+
+/** @brief Macro to configure the I2C2 clock (I2C2CLK).
+ * @param __I2C2CLKSource__ specifies the I2C2 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
+ * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
+ */
+#define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))
+
+/** @brief Macro to get the I2C2 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
+ * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
+ */
+#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
+ * @{
+ */
+
+/** @brief Macro to configure the ADC1 & ADC2 clock (ADC12CLK).
+ * @param __ADC12CLKSource__ specifies the ADC1 & ADC2 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_ADC12PLLCLK_OFF ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 & ADC2 clock
+ */
+#define __HAL_RCC_ADC12_CONFIG(__ADC12CLKSource__) \
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, (uint32_t)(__ADC12CLKSource__))
+
+/** @brief Macro to get the ADC1 & ADC2 clock
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_ADC12PLLCLK_OFF ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 & ADC2 clock
+ */
+#define __HAL_RCC_GET_ADC12_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE12)))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
+ * @{
+ */
+
+/** @brief Macro to configure the TIM1 clock (TIM1CLK).
+ * @param __TIM1CLKSource__ specifies the TIM1 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock
+ * @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock
+ */
+#define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__))
+
+/** @brief Macro to get the TIM1 clock (TIM1CLK).
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock
+ * @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock
+ */
+#define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW)))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_I2Sx_Clock_Config RCC Extended I2Sx Clock Config
+ * @{
+ */
+
+/** @brief Macro to configure the I2S clock source (I2SCLK).
+ * @note This function must be called before enabling the I2S APB clock.
+ * @param __I2SCLKSource__ specifies the I2S clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_I2SCLKSOURCE_SYSCLK SYSCLK clock used as I2S clock source
+ * @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin
+ * used as I2S clock source
+ */
+#define __HAL_RCC_I2S_CONFIG(__I2SCLKSource__) \
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, (uint32_t)(__I2SCLKSource__))
+
+/** @brief Macro to get the I2S clock source (I2SCLK).
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_I2SCLKSOURCE_SYSCLK SYSCLK clock used as I2S clock source
+ * @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin
+ * used as I2S clock source
+ */
+#define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_UARTx_Clock_Config RCC Extended UARTx Clock Config
+ * @{
+ */
+
+/** @brief Macro to configure the UART4 clock (UART4CLK).
+ * @param __UART4CLKSource__ specifies the UART4 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock
+ * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock
+ * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock
+ * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock
+ */
+#define __HAL_RCC_UART4_CONFIG(__UART4CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_UART4SW, (uint32_t)(__UART4CLKSource__))
+
+/** @brief Macro to get the UART4 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock
+ * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock
+ * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock
+ * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock
+ */
+#define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_UART4SW)))
+
+/** @brief Macro to configure the UART5 clock (UART5CLK).
+ * @param __UART5CLKSource__ specifies the UART5 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock
+ * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock
+ * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock
+ * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock
+ */
+#define __HAL_RCC_UART5_CONFIG(__UART5CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_UART5SW, (uint32_t)(__UART5CLKSource__))
+
+/** @brief Macro to get the UART5 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock
+ * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock
+ * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock
+ * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock
+ */
+#define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_UART5SW)))
+/**
+ * @}
+ */
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F303xC) || defined(STM32F358xx)
+/** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
+ * @{
+ */
+
+/** @brief Macro to configure the ADC3 & ADC4 clock (ADC34CLK).
+ * @param __ADC34CLKSource__ specifies the ADC3 & ADC4 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_ADC34PLLCLK_OFF ADC3 & ADC4 PLL clock disabled, ADC3 & ADC4 can use AHB clock
+ * @arg @ref RCC_ADC34PLLCLK_DIV1 PLL clock divided by 1 selected as ADC3 & ADC4 clock
+ * @arg @ref RCC_ADC34PLLCLK_DIV2 PLL clock divided by 2 selected as ADC3 & ADC4 clock
+ * @arg @ref RCC_ADC34PLLCLK_DIV4 PLL clock divided by 4 selected as ADC3 & ADC4 clock
+ * @arg @ref RCC_ADC34PLLCLK_DIV6 PLL clock divided by 6 selected as ADC3 & ADC4 clock
+ * @arg @ref RCC_ADC34PLLCLK_DIV8 PLL clock divided by 8 selected as ADC3 & ADC4 clock
+ * @arg @ref RCC_ADC34PLLCLK_DIV10 PLL clock divided by 10 selected as ADC3 & ADC4 clock
+ * @arg @ref RCC_ADC34PLLCLK_DIV12 PLL clock divided by 12 selected as ADC3 & ADC4 clock
+ * @arg @ref RCC_ADC34PLLCLK_DIV16 PLL clock divided by 16 selected as ADC3 & ADC4 clock
+ * @arg @ref RCC_ADC34PLLCLK_DIV32 PLL clock divided by 32 selected as ADC3 & ADC4 clock
+ * @arg @ref RCC_ADC34PLLCLK_DIV64 PLL clock divided by 64 selected as ADC3 & ADC4 clock
+ * @arg @ref RCC_ADC34PLLCLK_DIV128 PLL clock divided by 128 selected as ADC3 & ADC4 clock
+ * @arg @ref RCC_ADC34PLLCLK_DIV256 PLL clock divided by 256 selected as ADC3 & ADC4 clock
+ */
+#define __HAL_RCC_ADC34_CONFIG(__ADC34CLKSource__) \
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE34, (uint32_t)(__ADC34CLKSource__))
+
+/** @brief Macro to get the ADC3 & ADC4 clock
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_ADC34PLLCLK_OFF ADC3 & ADC4 PLL clock disabled, ADC3 & ADC4 can use AHB clock
+ * @arg @ref RCC_ADC34PLLCLK_DIV1 PLL clock divided by 1 selected as ADC3 & ADC4 clock
+ * @arg @ref RCC_ADC34PLLCLK_DIV2 PLL clock divided by 2 selected as ADC3 & ADC4 clock
+ * @arg @ref RCC_ADC34PLLCLK_DIV4 PLL clock divided by 4 selected as ADC3 & ADC4 clock
+ * @arg @ref RCC_ADC34PLLCLK_DIV6 PLL clock divided by 6 selected as ADC3 & ADC4 clock
+ * @arg @ref RCC_ADC34PLLCLK_DIV8 PLL clock divided by 8 selected as ADC3 & ADC4 clock
+ * @arg @ref RCC_ADC34PLLCLK_DIV10 PLL clock divided by 10 selected as ADC3 & ADC4 clock
+ * @arg @ref RCC_ADC34PLLCLK_DIV12 PLL clock divided by 12 selected as ADC3 & ADC4 clock
+ * @arg @ref RCC_ADC34PLLCLK_DIV16 PLL clock divided by 16 selected as ADC3 & ADC4 clock
+ * @arg @ref RCC_ADC34PLLCLK_DIV32 PLL clock divided by 32 selected as ADC3 & ADC4 clock
+ * @arg @ref RCC_ADC34PLLCLK_DIV64 PLL clock divided by 64 selected as ADC3 & ADC4 clock
+ * @arg @ref RCC_ADC34PLLCLK_DIV128 PLL clock divided by 128 selected as ADC3 & ADC4 clock
+ * @arg @ref RCC_ADC34PLLCLK_DIV256 PLL clock divided by 256 selected as ADC3 & ADC4 clock
+ */
+#define __HAL_RCC_GET_ADC34_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE34)))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
+ * @{
+ */
+
+/** @brief Macro to configure the TIM8 clock (TIM8CLK).
+ * @param __TIM8CLKSource__ specifies the TIM8 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_TIM8CLK_HCLK HCLK selected as TIM8 clock
+ * @arg @ref RCC_TIM8CLK_PLLCLK PLL Clock selected as TIM8 clock
+ */
+#define __HAL_RCC_TIM8_CONFIG(__TIM8CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM8SW, (uint32_t)(__TIM8CLKSource__))
+
+/** @brief Macro to get the TIM8 clock (TIM8CLK).
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_TIM8CLK_HCLK HCLK selected as TIM8 clock
+ * @arg @ref RCC_TIM8CLK_PLLCLK PLL Clock selected as TIM8 clock
+ */
+#define __HAL_RCC_GET_TIM8_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM8SW)))
+
+/**
+ * @}
+ */
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+/** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
+ * @{
+ */
+
+/** @brief Macro to configure the ADC1 & ADC2 clock (ADC12CLK).
+ * @param __ADC12CLKSource__ specifies the ADC1 & ADC2 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_ADC12PLLCLK_OFF ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 & ADC2 clock
+ */
+#define __HAL_RCC_ADC12_CONFIG(__ADC12CLKSource__) \
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, (uint32_t)(__ADC12CLKSource__))
+
+/** @brief Macro to get the ADC1 & ADC2 clock
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_ADC12PLLCLK_OFF ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 & ADC2 clock
+ */
+#define __HAL_RCC_GET_ADC12_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE12)))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
+ * @{
+ */
+/** @brief Macro to configure the TIM1 clock (TIM1CLK).
+ * @param __TIM1CLKSource__ specifies the TIM1 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock
+ * @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock
+ */
+#define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__))
+
+/** @brief Macro to get the TIM1 clock (TIM1CLK).
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock
+ * @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock
+ */
+#define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW)))
+/**
+ * @}
+ */
+#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F334x8)
+/** @defgroup RCCEx_HRTIMx_Clock_Config RCC Extended HRTIMx Clock Config
+ * @{
+ */
+/** @brief Macro to configure the HRTIM1 clock.
+ * @param __HRTIM1CLKSource__ specifies the HRTIM1 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_HRTIM1CLK_HCLK HCLK selected as HRTIM1 clock
+ * @arg @ref RCC_HRTIM1CLK_PLLCLK PLL Clock selected as HRTIM1 clock
+ */
+#define __HAL_RCC_HRTIM1_CONFIG(__HRTIM1CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_HRTIM1SW, (uint32_t)(__HRTIM1CLKSource__))
+
+/** @brief Macro to get the HRTIM1 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_HRTIM1CLK_HCLK HCLK selected as HRTIM1 clock
+ * @arg @ref RCC_HRTIM1CLK_PLLCLK PLL Clock selected as HRTIM1 clock
+ */
+#define __HAL_RCC_GET_HRTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_HRTIM1SW)))
+/**
+ * @}
+ */
+#endif /* STM32F334x8 */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
+ * @{
+ */
+/** @brief Macro to configure the I2C2 clock (I2C2CLK).
+ * @param __I2C2CLKSource__ specifies the I2C2 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
+ * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
+ */
+#define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))
+
+/** @brief Macro to get the I2C2 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
+ * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
+ */
+#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
+ * @{
+ */
+/** @brief Macro to configure the ADC1 clock (ADC1CLK).
+ * @param __ADC1CLKSource__ specifies the ADC1 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_ADC1PCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC1 clock
+ */
+#define __HAL_RCC_ADC1_CONFIG(__ADC1CLKSource__) \
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADC1CLKSource__))
+
+/** @brief Macro to get the ADC1 clock (ADC1CLK).
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_ADC1PCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC1 clock
+ */
+#define __HAL_RCC_GET_ADC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE)))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_SDADCx_Clock_Config RCC Extended SDADCx Clock Config
+ * @{
+ */
+/** @brief Macro to configure the SDADCx clock (SDADCxCLK).
+ * @param __SDADCPrescaler__ specifies the SDADCx system clock prescaler.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_SDADCSYSCLK_DIV1 SYSCLK clock selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV2 SYSCLK clock divided by 2 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV4 SYSCLK clock divided by 4 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV6 SYSCLK clock divided by 6 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV8 SYSCLK clock divided by 8 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV10 SYSCLK clock divided by 10 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV12 SYSCLK clock divided by 12 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV14 SYSCLK clock divided by 14 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV16 SYSCLK clock divided by 16 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV20 SYSCLK clock divided by 20 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV24 SYSCLK clock divided by 24 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV28 SYSCLK clock divided by 28 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV32 SYSCLK clock divided by 32 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV36 SYSCLK clock divided by 36 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV40 SYSCLK clock divided by 40 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV44 SYSCLK clock divided by 44 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV48 SYSCLK clock divided by 48 selected as SDADCx clock
+ */
+#define __HAL_RCC_SDADC_CONFIG(__SDADCPrescaler__) \
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_SDPRE, (uint32_t)(__SDADCPrescaler__))
+
+/** @brief Macro to get the SDADCx clock prescaler.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_SDADCSYSCLK_DIV1 SYSCLK clock selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV2 SYSCLK clock divided by 2 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV4 SYSCLK clock divided by 4 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV6 SYSCLK clock divided by 6 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV8 SYSCLK clock divided by 8 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV10 SYSCLK clock divided by 10 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV12 SYSCLK clock divided by 12 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV14 SYSCLK clock divided by 14 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV16 SYSCLK clock divided by 16 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV20 SYSCLK clock divided by 20 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV24 SYSCLK clock divided by 24 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV28 SYSCLK clock divided by 28 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV32 SYSCLK clock divided by 32 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV36 SYSCLK clock divided by 36 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV40 SYSCLK clock divided by 40 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV44 SYSCLK clock divided by 44 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV48 SYSCLK clock divided by 48 selected as SDADCx clock
+ */
+#define __HAL_RCC_GET_SDADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SDPRE)))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_CECx_Clock_Config RCC Extended CECx Clock Config
+ * @{
+ */
+/** @brief Macro to configure the CEC clock.
+ * @param __CECCLKSource__ specifies the CEC clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_CECCLKSOURCE_HSI HSI selected as CEC clock
+ * @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock
+ */
+#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSource__))
+
+/** @brief Macro to get the HDMI CEC clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_CECCLKSOURCE_HSI HSI selected as CEC clock
+ * @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock
+ */
+#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW)))
+/**
+ * @}
+ */
+
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE)\
+ || defined(STM32F302xC) || defined(STM32F303xC)\
+ || defined(STM32F302x8) \
+ || defined(STM32F373xC)
+
+/** @defgroup RCCEx_USBx_Clock_Config RCC Extended USBx Clock Config
+ * @{
+ */
+/** @brief Macro to configure the USB clock (USBCLK).
+ * @param __USBCLKSource__ specifies the USB clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock divided by 1 selected as USB clock
+ * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL Clock divided by 1.5 selected as USB clock
+ */
+#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSource__))
+
+/** @brief Macro to get the USB clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock divided by 1 selected as USB clock
+ * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL Clock divided by 1.5 selected as USB clock
+ */
+#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE)))
+/**
+ * @}
+ */
+
+#endif /* STM32F302xE || STM32F303xE || */
+ /* STM32F302xC || STM32F303xC || */
+ /* STM32F302x8 || */
+ /* STM32F373xC */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+
+/** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
+ * @{
+ */
+/** @brief Macro to configure the I2C3 clock (I2C3CLK).
+ * @param __I2C3CLKSource__ specifies the I2C3 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
+ * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
+ */
+#define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C3SW, (uint32_t)(__I2C3CLKSource__))
+
+/** @brief Macro to get the I2C3 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
+ * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
+ */
+#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C3SW)))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
+ * @{
+ */
+/** @brief Macro to configure the TIM2 clock (TIM2CLK).
+ * @param __TIM2CLKSource__ specifies the TIM2 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_TIM2CLK_HCLK HCLK selected as TIM2 clock
+ * @arg @ref RCC_TIM2CLK_PLL PLL Clock selected as TIM2 clock
+ */
+#define __HAL_RCC_TIM2_CONFIG(__TIM2CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM2SW, (uint32_t)(__TIM2CLKSource__))
+
+/** @brief Macro to get the TIM2 clock (TIM2CLK).
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_TIM2CLK_HCLK HCLK selected as TIM2 clock
+ * @arg @ref RCC_TIM2CLK_PLL PLL Clock selected as TIM2 clock
+ */
+#define __HAL_RCC_GET_TIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM2SW)))
+
+/** @brief Macro to configure the TIM3 & TIM4 clock (TIM34CLK).
+ * @param __TIM34CLKSource__ specifies the TIM3 & TIM4 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_TIM34CLK_HCLK HCLK selected as TIM3 & TIM4 clock
+ * @arg @ref RCC_TIM34CLK_PLL PLL Clock selected as TIM3 & TIM4 clock
+ */
+#define __HAL_RCC_TIM34_CONFIG(__TIM34CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM34SW, (uint32_t)(__TIM34CLKSource__))
+
+/** @brief Macro to get the TIM3 & TIM4 clock (TIM34CLK).
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_TIM34CLK_HCLK HCLK selected as TIM3 & TIM4 clock
+ * @arg @ref RCC_TIM34CLK_PLL PLL Clock selected as TIM3 & TIM4 clock
+ */
+#define __HAL_RCC_GET_TIM34_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM34SW)))
+
+/** @brief Macro to configure the TIM15 clock (TIM15CLK).
+ * @param __TIM15CLKSource__ specifies the TIM15 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_TIM15CLK_HCLK HCLK selected as TIM15 clock
+ * @arg @ref RCC_TIM15CLK_PLL PLL Clock selected as TIM15 clock
+ */
+#define __HAL_RCC_TIM15_CONFIG(__TIM15CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM15SW, (uint32_t)(__TIM15CLKSource__))
+
+/** @brief Macro to get the TIM15 clock (TIM15CLK).
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_TIM15CLK_HCLK HCLK selected as TIM15 clock
+ * @arg @ref RCC_TIM15CLK_PLL PLL Clock selected as TIM15 clock
+ */
+#define __HAL_RCC_GET_TIM15_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM15SW)))
+
+/** @brief Macro to configure the TIM16 clock (TIM16CLK).
+ * @param __TIM16CLKSource__ specifies the TIM16 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_TIM16CLK_HCLK HCLK selected as TIM16 clock
+ * @arg @ref RCC_TIM16CLK_PLL PLL Clock selected as TIM16 clock
+ */
+#define __HAL_RCC_TIM16_CONFIG(__TIM16CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM16SW, (uint32_t)(__TIM16CLKSource__))
+
+/** @brief Macro to get the TIM16 clock (TIM16CLK).
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_TIM16CLK_HCLK HCLK selected as TIM16 clock
+ * @arg @ref RCC_TIM16CLK_PLL PLL Clock selected as TIM16 clock
+ */
+#define __HAL_RCC_GET_TIM16_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM16SW)))
+
+/** @brief Macro to configure the TIM17 clock (TIM17CLK).
+ * @param __TIM17CLKSource__ specifies the TIM17 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_TIM17CLK_HCLK HCLK selected as TIM17 clock
+ * @arg @ref RCC_TIM17CLK_PLL PLL Clock selected as TIM17 clock
+ */
+#define __HAL_RCC_TIM17_CONFIG(__TIM17CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM17SW, (uint32_t)(__TIM17CLKSource__))
+
+/** @brief Macro to get the TIM17 clock (TIM17CLK).
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_TIM17CLK_HCLK HCLK selected as TIM17 clock
+ * @arg @ref RCC_TIM17CLK_PLL PLL Clock selected as TIM17 clock
+ */
+#define __HAL_RCC_GET_TIM17_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM17SW)))
+
+/**
+ * @}
+ */
+
+#endif /* STM32f302xE || STM32f303xE || STM32F398xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)
+/** @addtogroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
+ * @{
+ */
+/** @brief Macro to configure the TIM20 clock (TIM20CLK).
+ * @param __TIM20CLKSource__ specifies the TIM20 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_TIM20CLK_HCLK HCLK selected as TIM20 clock
+ * @arg @ref RCC_TIM20CLK_PLL PLL Clock selected as TIM20 clock
+ */
+#define __HAL_RCC_TIM20_CONFIG(__TIM20CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM20SW, (uint32_t)(__TIM20CLKSource__))
+
+/** @brief Macro to get the TIM20 clock (TIM20CLK).
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_TIM20CLK_HCLK HCLK selected as TIM20 clock
+ * @arg @ref RCC_TIM20CLK_PLL PLL Clock selected as TIM20 clock
+ */
+#define __HAL_RCC_GET_TIM20_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM20SW)))
+
+/**
+ * @}
+ */
+#endif /* STM32f303xE || STM32F398xx */
+
+/** @defgroup RCCEx_LSE_Configuration LSE Drive Configuration
+ * @{
+ */
+
+/**
+ * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability.
+ * @param __RCC_LSEDRIVE__ specifies the new state of the LSE drive capability.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability.
+ * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability.
+ * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability.
+ * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability.
+ * @retval None
+ */
+#define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) (MODIFY_REG(RCC->BDCR,\
+ RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) ))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RCCEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup RCCEx_Exported_Functions_Group1
+ * @{
+ */
+
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_RCC_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Inc/stm32f3xx_hal_rtc.h b/Inc/stm32f3xx_hal_rtc.h
new file mode 100644
index 0000000..c909e94
--- /dev/null
+++ b/Inc/stm32f3xx_hal_rtc.h
@@ -0,0 +1,842 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_rtc.h
+ * @author MCD Application Team
+ * @brief Header file of RTC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_RTC_H
+#define __STM32F3xx_HAL_RTC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup RTC RTC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup RTC_Exported_Types RTC Exported Types
+ * @{
+ */
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_RTC_STATE_RESET = 0x00U, /*!< RTC not yet initialized or disabled */
+ HAL_RTC_STATE_READY = 0x01U, /*!< RTC initialized and ready for use */
+ HAL_RTC_STATE_BUSY = 0x02U, /*!< RTC process is ongoing */
+ HAL_RTC_STATE_TIMEOUT = 0x03U, /*!< RTC timeout state */
+ HAL_RTC_STATE_ERROR = 0x04U /*!< RTC error state */
+
+}HAL_RTCStateTypeDef;
+
+/**
+ * @brief RTC Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t HourFormat; /*!< Specifies the RTC Hour Format.
+ This parameter can be a value of @ref RTC_Hour_Formats */
+
+ uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
+
+ uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */
+
+ uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output.
+ This parameter can be a value of @ref RTCEx_Output_selection_Definitions */
+
+ uint32_t OutPutPolarity; /*!< Specifies the polarity of the output signal.
+ This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
+
+ uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode.
+ This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
+}RTC_InitTypeDef;
+
+/**
+ * @brief RTC Time structure definition
+ */
+typedef struct
+{
+ uint8_t Hours; /*!< Specifies the RTC Time Hour.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */
+
+ uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
+
+ uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
+
+ uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
+ This parameter can be a value of @ref RTC_AM_PM_Definitions */
+
+ uint32_t SubSeconds; /*!< Specifies the RTC_SSR RTC Sub Second register content.
+ This parameter corresponds to a time unit range between [0-1] Second
+ with [1 Sec / SecondFraction +1] granularity */
+
+ uint32_t SecondFraction; /*!< Specifies the range or granularity of Sub Second register content
+ corresponding to Synchronous pre-scaler factor value (PREDIV_S)
+ This parameter corresponds to a time unit range between [0-1] Second
+ with [1 Sec / SecondFraction +1] granularity.
+ This field will be used only by HAL_RTC_GetTime function */
+
+ uint32_t DayLightSaving; /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment.
+ This parameter can be a value of @ref RTC_DayLightSaving_Definitions */
+
+ uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BCK bit
+ in CR register to store the operation.
+ This parameter can be a value of @ref RTC_StoreOperation_Definitions */
+}RTC_TimeTypeDef;
+
+/**
+ * @brief RTC Date structure definition
+ */
+typedef struct
+{
+ uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay.
+ This parameter can be a value of @ref RTC_WeekDay_Definitions */
+
+ uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format).
+ This parameter can be a value of @ref RTC_Month_Date_Definitions */
+
+ uint8_t Date; /*!< Specifies the RTC Date.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
+
+ uint8_t Year; /*!< Specifies the RTC Date Year.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
+
+}RTC_DateTypeDef;
+
+/**
+ * @brief RTC Alarm structure definition
+ */
+typedef struct
+{
+ RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members */
+
+ uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks.
+ This parameter can be a value of @ref RTC_AlarmMask_Definitions */
+
+ uint32_t AlarmSubSecondMask; /*!< Specifies the RTC Alarm SubSeconds Masks.
+ This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */
+
+ uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.
+ This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
+
+ uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.
+ If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.
+ If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */
+
+ uint32_t Alarm; /*!< Specifies the alarm .
+ This parameter can be a value of @ref RTC_Alarms_Definitions */
+}RTC_AlarmTypeDef;
+
+/**
+ * @brief RTC Handle Structure definition
+ */
+typedef struct
+{
+ RTC_TypeDef *Instance; /*!< Register base address */
+
+ RTC_InitTypeDef Init; /*!< RTC required parameters */
+
+ HAL_LockTypeDef Lock; /*!< RTC locking object */
+
+ __IO HAL_RTCStateTypeDef State; /*!< Time communication state */
+
+}RTC_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RTC_Exported_Constants RTC Exported Constants
+ * @{
+ */
+
+/** @defgroup RTC_Hour_Formats RTC Hour Formats
+ * @{
+ */
+#define RTC_HOURFORMAT_24 0x00000000U
+#define RTC_HOURFORMAT_12 RTC_CR_FMT
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
+ * @{
+ */
+#define RTC_OUTPUT_POLARITY_HIGH 0x00000000U
+#define RTC_OUTPUT_POLARITY_LOW RTC_CR_POL
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
+ * @{
+ */
+#define RTC_OUTPUT_TYPE_OPENDRAIN 0x00000000U
+#define RTC_OUTPUT_TYPE_PUSHPULL RTC_TAFCR_ALARMOUTTYPE
+/**
+ * @}
+ */
+
+/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
+ * @{
+ */
+#define RTC_HOURFORMAT12_AM ((uint8_t)0x00)
+#define RTC_HOURFORMAT12_PM ((uint8_t)0x40)
+/**
+ * @}
+ */
+
+/** @defgroup RTC_DayLightSaving_Definitions RTC DayLightSaving Definitions
+ * @{
+ */
+#define RTC_DAYLIGHTSAVING_NONE 0x00000000U
+#define RTC_DAYLIGHTSAVING_SUB1H RTC_CR_SUB1H
+#define RTC_DAYLIGHTSAVING_ADD1H RTC_CR_ADD1H
+/**
+ * @}
+ */
+
+/** @defgroup RTC_StoreOperation_Definitions RTC StoreOperation Definitions
+ * @{
+ */
+#define RTC_STOREOPERATION_RESET 0x00000000U
+#define RTC_STOREOPERATION_SET RTC_CR_BCK
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Input_parameter_format_definitions RTC Input parameter format definitions
+ * @{
+ */
+#define RTC_FORMAT_BIN 0x000000000U
+#define RTC_FORMAT_BCD 0x000000001U
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions
+ * @{
+ */
+/* Coded in BCD format */
+#define RTC_MONTH_JANUARY ((uint8_t)0x01)
+#define RTC_MONTH_FEBRUARY ((uint8_t)0x02)
+#define RTC_MONTH_MARCH ((uint8_t)0x03)
+#define RTC_MONTH_APRIL ((uint8_t)0x04)
+#define RTC_MONTH_MAY ((uint8_t)0x05)
+#define RTC_MONTH_JUNE ((uint8_t)0x06)
+#define RTC_MONTH_JULY ((uint8_t)0x07)
+#define RTC_MONTH_AUGUST ((uint8_t)0x08)
+#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09)
+#define RTC_MONTH_OCTOBER ((uint8_t)0x10)
+#define RTC_MONTH_NOVEMBER ((uint8_t)0x11)
+#define RTC_MONTH_DECEMBER ((uint8_t)0x12)
+/**
+ * @}
+ */
+
+/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions
+ * @{
+ */
+#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01)
+#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)
+#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)
+#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04)
+#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)
+#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)
+#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07)
+/**
+ * @}
+ */
+
+/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC AlarmDateWeekDay Definitions
+ * @{
+ */
+#define RTC_ALARMDATEWEEKDAYSEL_DATE 0x00000000U
+#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL
+/**
+ * @}
+ */
+
+/** @defgroup RTC_AlarmMask_Definitions RTC AlarmMask Definitions
+ * @{
+ */
+#define RTC_ALARMMASK_NONE 0x00000000U
+#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4
+#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
+#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
+#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
+#define RTC_ALARMMASK_ALL (RTC_ALARMMASK_NONE | \
+ RTC_ALARMMASK_DATEWEEKDAY | \
+ RTC_ALARMMASK_HOURS | \
+ RTC_ALARMMASK_MINUTES | \
+ RTC_ALARMMASK_SECONDS)
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions
+ * @{
+ */
+#define RTC_ALARM_A RTC_CR_ALRAE
+#define RTC_ALARM_B RTC_CR_ALRBE
+/**
+ * @}
+ */
+
+ /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions
+ * @{
+ */
+#define RTC_ALARMSUBSECONDMASK_ALL 0x00000000U /*!< All Alarm SS fields are masked.
+ There is no comparison on sub seconds
+ for Alarm */
+#define RTC_ALARMSUBSECONDMASK_SS14_1 RTC_ALRMASSR_MASKSS_0 /*!< SS[14:1] are ignored in Alarm
+ comparison. Only SS[0] is compared. */
+#define RTC_ALARMSUBSECONDMASK_SS14_2 RTC_ALRMASSR_MASKSS_1 /*!< SS[14:2] are ignored in Alarm
+ comparison. Only SS[1:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_3 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1) /*!< SS[14:3] are ignored in Alarm
+ comparison. Only SS[2:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_4 RTC_ALRMASSR_MASKSS_2 /*!< SS[14:4] are ignored in Alarm
+ comparison. Only SS[3:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_5 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2) /*!< SS[14:5] are ignored in Alarm
+ comparison. Only SS[4:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_6 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2) /*!< SS[14:6] are ignored in Alarm
+ comparison. Only SS[5:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_7 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2) /*!< SS[14:7] are ignored in Alarm
+ comparison. Only SS[6:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_8 RTC_ALRMASSR_MASKSS_3 /*!< SS[14:8] are ignored in Alarm
+ comparison. Only SS[7:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_9 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:9] are ignored in Alarm
+ comparison. Only SS[8:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_10 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:10] are ignored in Alarm
+ comparison. Only SS[9:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_11 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:11] are ignored in Alarm
+ comparison. Only SS[10:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_12 (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:12] are ignored in Alarm
+ comparison.Only SS[11:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_13 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:13] are ignored in Alarm
+ comparison. Only SS[12:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14] is don't care in Alarm
+ comparison.Only SS[13:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_NONE RTC_ALRMASSR_MASKSS /*!< SS[14:0] are compared and must match
+ to activate alarm. */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
+ * @{
+ */
+#define RTC_IT_TS RTC_CR_TSIE
+#define RTC_IT_WUT RTC_CR_WUTIE
+#define RTC_IT_ALRB RTC_CR_ALRBIE
+#define RTC_IT_ALRA RTC_CR_ALRAIE
+#define RTC_IT_TAMP RTC_TAFCR_TAMPIE /* Used only to Enable the Tamper Interrupt */
+#define RTC_IT_TAMP1 0x00020000U /*only for RTC_ISR flag check*/
+#define RTC_IT_TAMP2 0x00040000U /*only for RTC_ISR flag check*/
+#if defined(RTC_TAMPER3_SUPPORT)
+#define RTC_IT_TAMP3 0x00080000U /*only for RTC_ISR flag check*/
+#endif /* RTC_TAMPER3_SUPPORT */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Flags_Definitions RTC Flags Definitions
+ * @{
+ */
+#define RTC_FLAG_RECALPF RTC_ISR_RECALPF
+#if defined(RTC_TAMPER3_SUPPORT)
+#define RTC_FLAG_TAMP3F RTC_ISR_TAMP3F
+#endif /* RTC_TAMPER3_SUPPORT */
+#define RTC_FLAG_TAMP2F RTC_ISR_TAMP2F
+#define RTC_FLAG_TAMP1F RTC_ISR_TAMP1F
+#define RTC_FLAG_TSOVF RTC_ISR_TSOVF
+#define RTC_FLAG_TSF RTC_ISR_TSF
+#define RTC_FLAG_WUTF RTC_ISR_WUTF
+#define RTC_FLAG_ALRBF RTC_ISR_ALRBF
+#define RTC_FLAG_ALRAF RTC_ISR_ALRAF
+#define RTC_FLAG_INITF RTC_ISR_INITF
+#define RTC_FLAG_RSF RTC_ISR_RSF
+#define RTC_FLAG_INITS RTC_ISR_INITS
+#define RTC_FLAG_SHPF RTC_ISR_SHPF
+#define RTC_FLAG_WUTWF RTC_ISR_WUTWF
+#define RTC_FLAG_ALRBWF RTC_ISR_ALRBWF
+#define RTC_FLAG_ALRAWF RTC_ISR_ALRAWF
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup RTC_Exported_Macros RTC Exported Macros
+ * @{
+ */
+
+/** @brief Reset RTC handle state
+ * @param __HANDLE__ RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
+
+/**
+ * @brief Disable the write protection for RTC registers.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \
+ do{ \
+ (__HANDLE__)->Instance->WPR = 0xCAU; \
+ (__HANDLE__)->Instance->WPR = 0x53U; \
+ } while(0U)
+
+/**
+ * @brief Enable the write protection for RTC registers.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \
+ do{ \
+ (__HANDLE__)->Instance->WPR = 0xFFU; \
+ } while(0U)
+
+/**
+ * @brief Enable the RTC ALARMA peripheral.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
+
+/**
+ * @brief Disable the RTC ALARMA peripheral.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
+
+/**
+ * @brief Enable the RTC ALARMB peripheral.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
+
+/**
+ * @brief Disable the RTC ALARMB peripheral.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
+
+/**
+ * @brief Enable the RTC Alarm interrupt.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_IT_ALRA: Alarm A interrupt
+ * @arg RTC_IT_ALRB: Alarm B interrupt
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the RTC Alarm interrupt.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_IT_ALRA: Alarm A interrupt
+ * @arg RTC_IT_ALRB: Alarm B interrupt
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified RTC Alarm interrupt has occurred or not.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC Alarm interrupt to check.
+ * This parameter can be:
+ * @arg RTC_IT_ALRA: Alarm A interrupt
+ * @arg RTC_IT_ALRB: Alarm B interrupt
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
+
+/**
+ * @brief Check whether the specified RTC Alarm interrupt has been enabled or not.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to check.
+ * This parameter can be:
+ * @arg RTC_IT_ALRA: Alarm A interrupt
+ * @arg RTC_IT_ALRB: Alarm B interrupt
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
+
+/**
+ * @brief Get the selected RTC Alarm's flag status.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __FLAG__ specifies the RTC Alarm Flag sources to check.
+ * This parameter can be:
+ * @arg RTC_FLAG_ALRAF
+ * @arg RTC_FLAG_ALRBF
+ * @arg RTC_FLAG_ALRAWF
+ * @arg RTC_FLAG_ALRBWF
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+
+/**
+ * @brief Clear the RTC Alarm's pending flags.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __FLAG__ specifies the RTC Alarm Flag sources to clear.
+ * This parameter can be:
+ * @arg RTC_FLAG_ALRAF
+ * @arg RTC_FLAG_ALRBF
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT) | ((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+
+/**
+ * @brief Enable interrupt on the RTC Alarm associated Exti line.
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_ALARM_EVENT)
+
+/**
+ * @brief Disable interrupt on the RTC Alarm associated Exti line.
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
+
+/**
+ * @brief Enable event on the RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT)
+
+/**
+ * @brief Disable event on the RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
+
+/**
+ * @brief Enable falling edge trigger on the RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT)
+
+/**
+ * @brief Disable falling edge trigger on the RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
+
+/**
+ * @brief Enable rising edge trigger on the RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT)
+
+/**
+ * @brief Disable rising edge trigger on the RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
+
+/**
+ * @brief Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE();
+
+/**
+ * @brief Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE();
+
+/**
+ * @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not.
+ * @retval Line Status.
+ */
+#define __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_ALARM_EVENT)
+
+/**
+ * @brief Clear the RTC Alarm associated Exti line flag.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_ALARM_EVENT)
+
+/**
+ * @brief Generate a Software interrupt on RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT)
+/**
+ * @}
+ */
+
+/* Include RTC HAL Extended module */
+#include "stm32f3xx_hal_rtc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RTC_Exported_Functions RTC Exported Functions
+ * @{
+ */
+
+/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
+void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
+void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions
+ * @{
+ */
+
+/* RTC Time and Date functions ************************************************/
+HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions
+ * @{
+ */
+/* RTC Alarm functions ********************************************************/
+HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
+HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
+void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc);
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions
+ * @{
+ */
+/* Peripheral State functions *************************************************/
+HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RTC_Private_Constants RTC Private Constants
+ * @{
+ */
+/* Masks Definition */
+#define RTC_TR_RESERVED_MASK 0x007F7F7FU
+#define RTC_DR_RESERVED_MASK 0x00FFFF3FU
+#define RTC_INIT_MASK 0xFFFFFFFFU
+#define RTC_RSF_MASK 0xFFFFFF5FU
+#define RTC_FLAGS_MASK ((uint32_t) (RTC_FLAG_RECALPF | RTC_FLAG_TAMP3F | RTC_FLAG_TAMP2F | \
+ RTC_FLAG_TAMP1F| RTC_FLAG_TSOVF | RTC_FLAG_TSF | \
+ RTC_FLAG_WUTF | RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | \
+ RTC_FLAG_INITF | RTC_FLAG_RSF | \
+ RTC_FLAG_INITS | RTC_FLAG_SHPF | RTC_FLAG_WUTWF | \
+ RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF))
+
+#define RTC_TIMEOUT_VALUE 1000
+
+#define RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR_MR17 /*!< External interrupt line 17 Connected to the RTC Alarm event */
+#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT EXTI_IMR_MR19 /*!< External interrupt line 19 Connected to the RTC Tamper and Time Stamp events */
+#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT EXTI_IMR_MR20 /*!< External interrupt line 20 Connected to the RTC Wakeup event */
+/**
+ * @}
+ */
+/* Private macros -----------------------------------------------------------*/
+/** @defgroup RTC_Private_Macros RTC Private Macros
+ * @{
+ */
+
+/** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters
+ * @{
+ */
+
+#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \
+ ((FORMAT) == RTC_HOURFORMAT_24))
+
+#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
+ ((POL) == RTC_OUTPUT_POLARITY_LOW))
+
+#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
+ ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
+#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0U) && ((HOUR) <= 12U))
+#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23U)
+#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FU)
+#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFFU)
+#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59U)
+#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59U)
+
+#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || \
+ ((PM) == RTC_HOURFORMAT12_PM))
+
+#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
+ ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
+ ((SAVE) == RTC_DAYLIGHTSAVING_NONE))
+
+#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
+ ((OPERATION) == RTC_STOREOPERATION_SET))
+
+#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
+
+#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99U)
+
+#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1U) && ((MONTH) <= 12U))
+
+#define IS_RTC_DATE(DATE) (((DATE) >= 1U) && ((DATE) <= 31U))
+
+#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
+
+#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0U) && ((DATE) <= 31U))
+
+#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
+
+#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
+ ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
+
+#define IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7FU) == (uint32_t)RESET)
+
+#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
+
+#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFFU)
+
+#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_NONE))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions -------------------------------------------------------------*/
+/** @defgroup RTC_Private_Functions RTC Private Functions
+ * @{
+ */
+HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc);
+uint8_t RTC_ByteToBcd2(uint8_t Value);
+uint8_t RTC_Bcd2ToByte(uint8_t Value);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_RTC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_hal_rtc_ex.h b/Inc/stm32f3xx_hal_rtc_ex.h
new file mode 100644
index 0000000..671b78e
--- /dev/null
+++ b/Inc/stm32f3xx_hal_rtc_ex.h
@@ -0,0 +1,1022 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_rtc_ex.h
+ * @author MCD Application Team
+ * @brief Header file of RTC HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_RTC_EX_H
+#define __STM32F3xx_HAL_RTC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup RTCEx RTCEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup RTCEx_Exported_Types RTC Extended Exported Types
+ * @{
+ */
+
+/**
+ * @brief RTC Tamper structure definition
+ */
+typedef struct
+{
+ uint32_t Tamper; /*!< Specifies the Tamper Pin.
+ This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions */
+
+ uint32_t Trigger; /*!< Specifies the Tamper Trigger.
+ This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */
+
+ uint32_t Filter; /*!< Specifies the RTC Filter Tamper.
+ This parameter can be a value of @ref RTCEx_Tamper_Filter_Definitions */
+
+ uint32_t SamplingFrequency; /*!< Specifies the sampling frequency.
+ This parameter can be a value of @ref RTCEx_Tamper_Sampling_Frequencies_Definitions */
+
+ uint32_t PrechargeDuration; /*!< Specifies the Precharge Duration .
+ This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration_Definitions */
+
+ uint32_t TamperPullUp; /*!< Specifies the Tamper PullUp .
+ This parameter can be a value of @ref RTCEx_Tamper_Pull_UP_Definitions */
+
+ uint32_t TimeStampOnTamperDetection; /*!< Specifies the TimeStampOnTamperDetection.
+ This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */
+}RTC_TamperTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RTCEx_Exported_Constants RTC Extended Exported Constants
+ * @{
+ */
+
+/** @defgroup RTCEx_Output_selection_Definitions RTC Extended Output Selection Definition
+ * @{
+ */
+#define RTC_OUTPUT_DISABLE 0x00000000U
+#define RTC_OUTPUT_ALARMA RTC_CR_OSEL_0
+#define RTC_OUTPUT_ALARMB RTC_CR_OSEL_1
+#define RTC_OUTPUT_WAKEUP RTC_CR_OSEL
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Backup_Registers_Definitions RTC Extended Backup Registers Definition
+ * @{
+ */
+#if RTC_BKP_NUMBER > 0U
+#define RTC_BKP_DR0 0x00000000U
+#define RTC_BKP_DR1 0x00000001U
+#define RTC_BKP_DR2 0x00000002U
+#define RTC_BKP_DR3 0x00000003U
+#define RTC_BKP_DR4 0x00000004U
+#endif /* RTC_BKP_NUMBER > 0U */
+
+#if RTC_BKP_NUMBER > 5U
+#define RTC_BKP_DR5 0x00000005U
+#define RTC_BKP_DR6 0x00000006U
+#define RTC_BKP_DR7 0x00000007U
+#define RTC_BKP_DR8 0x00000008U
+#define RTC_BKP_DR9 0x00000009U
+#define RTC_BKP_DR10 0x0000000AU
+#define RTC_BKP_DR11 0x0000000BU
+#define RTC_BKP_DR12 0x0000000CU
+#define RTC_BKP_DR13 0x0000000DU
+#define RTC_BKP_DR14 0x0000000EU
+#define RTC_BKP_DR15 0x0000000FU
+#endif /* RTC_BKP_NUMBER > 5U */
+
+#if RTC_BKP_NUMBER > 16U
+#define RTC_BKP_DR16 0x00000010U
+#define RTC_BKP_DR17 0x00000011U
+#define RTC_BKP_DR18 0x00000012U
+#define RTC_BKP_DR19 0x00000013U
+#endif /* RTC_BKP_NUMBER > 16U */
+
+#if RTC_BKP_NUMBER > 20U
+#define RTC_BKP_DR20 0x00000014U
+#define RTC_BKP_DR21 0x00000015U
+#define RTC_BKP_DR22 0x00000016U
+#define RTC_BKP_DR23 0x00000017U
+#define RTC_BKP_DR24 0x00000018U
+#define RTC_BKP_DR25 0x00000019U
+#define RTC_BKP_DR26 0x0000001AU
+#define RTC_BKP_DR27 0x0000001BU
+#define RTC_BKP_DR28 0x0000001CU
+#define RTC_BKP_DR29 0x0000001DU
+#define RTC_BKP_DR30 0x0000001EU
+#define RTC_BKP_DR31 0x0000001FU
+#endif /* RTC_BKP_NUMBER > 20U */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Time_Stamp_Edges_definitions RTC Extended Time Stamp Edges definition
+ * @{
+ */
+#define RTC_TIMESTAMPEDGE_RISING 0x00000000U
+#define RTC_TIMESTAMPEDGE_FALLING RTC_CR_TSEDGE
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_TimeStamp_Pin_Selections RTC Extended TimeStamp Pin Selection
+ * @{
+ */
+#define RTC_TIMESTAMPPIN_DEFAULT 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_Pins_Definitions RTC Extended Tamper Pins Definition
+ * @{
+ */
+#define RTC_TAMPER_1 RTC_TAFCR_TAMP1E
+#define RTC_TAMPER_2 RTC_TAFCR_TAMP2E
+#if defined(RTC_TAMPER3_SUPPORT)
+#define RTC_TAMPER_3 RTC_TAFCR_TAMP3E
+#endif /* RTC_TAMPER3_SUPPORT */
+/**
+ * @}
+ */
+
+
+/** @defgroup RTCEx_Tamper_Trigger_Definitions RTC Extended Tamper Trigger Definition
+ * @{
+ */
+#define RTC_TAMPERTRIGGER_RISINGEDGE 0x00000000U
+#define RTC_TAMPERTRIGGER_FALLINGEDGE RTC_TAFCR_TAMP1TRG
+#define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE
+#define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_Filter_Definitions RTC Extended Tamper Filter Definition
+ * @{
+ */
+#define RTC_TAMPERFILTER_DISABLE 0x00000000U /*!< Tamper filter is disabled */
+
+#define RTC_TAMPERFILTER_2SAMPLE RTC_TAFCR_TAMPFLT_0 /*!< Tamper is activated after 2
+ consecutive samples at the active level */
+#define RTC_TAMPERFILTER_4SAMPLE RTC_TAFCR_TAMPFLT_1 /*!< Tamper is activated after 4
+ consecutive samples at the active level */
+#define RTC_TAMPERFILTER_8SAMPLE RTC_TAFCR_TAMPFLT /*!< Tamper is activated after 8
+ consecutive samples at the active level. */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTC Extended Tamper Sampling Frequencies Definition
+ * @{
+ */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 0x00000000U /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 32768U */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 RTC_TAFCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 16384U */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 RTC_TAFCR_TAMPFREQ_1 /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 8192 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 (RTC_TAFCR_TAMPFREQ_0 | RTC_TAFCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 4096 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 RTC_TAFCR_TAMPFREQ_2 /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 2048 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 (RTC_TAFCR_TAMPFREQ_0 | RTC_TAFCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 1024 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 (RTC_TAFCR_TAMPFREQ_1 | RTC_TAFCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 512 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 (RTC_TAFCR_TAMPFREQ_0 | RTC_TAFCR_TAMPFREQ_1 | RTC_TAFCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 256 */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTC Extended Tamper Pin Precharge Duration Definition
+ * @{
+ */
+#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK 0x00000000U /*!< Tamper pins are pre-charged before
+ sampling during 1 RTCCLK cycle */
+#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK RTC_TAFCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before
+ sampling during 2 RTCCLK cycles */
+#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK RTC_TAFCR_TAMPPRCH_1 /*!< Tamper pins are pre-charged before
+ sampling during 4 RTCCLK cycles */
+#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK (RTC_TAFCR_TAMPPRCH_0 | RTC_TAFCR_TAMPPRCH_1) /*!< Tamper pins are pre-charged before
+ sampling during 8 RTCCLK cycles */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions RTC Extended Tamper TimeStampOnTamperDetection Definition
+ * @{
+ */
+#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAFCR_TAMPTS) /*!< TimeStamp on Tamper Detection event saved */
+#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE 0x00000000U /*!< TimeStamp on Tamper Detection event is not saved */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_Pull_UP_Definitions RTC Extended Tamper Pull UP Definition
+ * @{
+ */
+#define RTC_TAMPER_PULLUP_ENABLE 0x00000000U /*!< Tamper pins are pre-charged before sampling */
+#define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAFCR_TAMPPUDIS) /*!< Tamper pins are not pre-charged before sampling */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Wakeup_Timer_Definitions RTC Extended Wakeup Timer Definition
+ * @{
+ */
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 0x00000000U
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 RTC_CR_WUCKSEL_0
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 RTC_CR_WUCKSEL_1
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1)
+#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS (RTC_CR_WUCKSEL_2)
+#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2)
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Smooth_calib_period_Definitions RTC Extended Smooth calib period Definition
+ * @{
+ */
+#define RTC_SMOOTHCALIB_PERIOD_32SEC 0x00000000U /*!< If RTCCLK = 32768 Hz, Smooth calibation
+ period is 32s, else 2exp20 RTCCLK seconds */
+#define RTC_SMOOTHCALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< If RTCCLK = 32768 Hz, Smooth calibation
+ period is 16s, else 2exp19 RTCCLK seconds */
+#define RTC_SMOOTHCALIB_PERIOD_8SEC RTC_CALR_CALW8 /*!< If RTCCLK = 32768 Hz, Smooth calibation
+ period is 8s, else 2exp18 RTCCLK seconds */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTC Extended Smooth calib Plus pulses Definition
+ * @{
+ */
+#define RTC_SMOOTHCALIB_PLUSPULSES_RESET 0x00000000U /*!< The number of RTCCLK pulses subbstited
+ during a 32-second window = CALM[8:0] */
+#define RTC_SMOOTHCALIB_PLUSPULSES_SET RTC_CALR_CALP /*!< The number of RTCCLK pulses added
+ during a X -second window = Y - CALM[8:0]
+ with Y = 512U, 256U, 128 when X = 32U, 16U, 8U */
+/**
+ * @}
+ */
+
+ /** @defgroup RTCEx_Calib_Output_selection_Definitions RTC Extended Calib Output selection Definition
+ * @{
+ */
+#define RTC_CALIBOUTPUT_512HZ 0x00000000U
+#define RTC_CALIBOUTPUT_1HZ RTC_CR_COSEL
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Add_1_Second_Parameter_Definition RTC Extended Add 1 Second Parameter Definition
+ * @{
+ */
+#define RTC_SHIFTADD1S_RESET 0x00000000U
+#define RTC_SHIFTADD1S_SET RTC_SHIFTR_ADD1S
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RTCEx_Exported_Macros RTC Extended Exported Macros
+ * @{
+ */
+
+/* ---------------------------------WAKEUPTIMER---------------------------------*/
+/** @defgroup RTCEx_WakeUp_Timer RTC Extended WakeUp Timer
+ * @{
+ */
+/**
+ * @brief Enable the RTC WakeUp Timer peripheral.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
+
+/**
+ * @brief Disable the RTC WakeUp Timer peripheral.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
+
+/**
+ * @brief Enable the RTC WakeUpTimer interrupt.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled.
+ * This parameter can be:
+ * @arg RTC_IT_WUT: WakeUpTimer interrupt
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the RTC WakeUpTimer interrupt.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be disabled.
+ * This parameter can be:
+ * @arg RTC_IT_WUT: WakeUpTimer interrupt
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt to check.
+ * This parameter can be:
+ * @arg RTC_IT_WUT: WakeUpTimer interrupt
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET) ? SET : RESET)
+
+/**
+ * @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check.
+ * This parameter can be:
+ * @arg RTC_IT_WUT: WakeUpTimer interrupt
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
+
+/**
+ * @brief Get the selected RTC WakeUpTimer's flag status.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __FLAG__ specifies the RTC WakeUpTimer Flag is pending or not.
+ * This parameter can be:
+ * @arg RTC_FLAG_WUTF
+ * @arg RTC_FLAG_WUTWF
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
+
+/**
+ * @brief Clear the RTC Wake Up timer's pending flags.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __FLAG__ specifies the RTC WakeUpTimer Flag to clear.
+ * This parameter can be:
+ * @arg RTC_FLAG_WUTF
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+
+/* WAKE-UP TIMER EXTI */
+/* ------------------ */
+/**
+ * @brief Enable interrupt on the RTC WakeUp Timer associated Exti line.
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @brief Disable interrupt on the RTC WakeUp Timer associated Exti line.
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
+
+/**
+ * @brief Enable event on the RTC WakeUp Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @brief Disable event on the RTC WakeUp Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
+
+/**
+ * @brief Enable falling edge trigger on the RTC WakeUp Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @brief Disable falling edge trigger on the RTC WakeUp Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
+
+/**
+ * @brief Enable rising edge trigger on the RTC WakeUp Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @brief Disable rising edge trigger on the RTC WakeUp Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
+
+/**
+ * @brief Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();
+
+/**
+ * @brief Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
+ * This parameter can be:
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();
+
+/**
+ * @brief Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not.
+ * @retval Line Status.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @brief Clear the RTC WakeUp Timer associated Exti line flag.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @brief Generate a Software interrupt on the RTC WakeUp Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+/**
+ * @}
+ */
+
+/* ---------------------------------TIMESTAMP---------------------------------*/
+/** @defgroup RTCEx_Timestamp RTC Extended Timestamp
+ * @{
+ */
+/**
+ * @brief Enable the RTC TimeStamp peripheral.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
+
+/**
+ * @brief Disable the RTC TimeStamp peripheral.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
+
+/**
+ * @brief Enable the RTC TimeStamp interrupt.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be enabled.
+ * This parameter can be:
+ * @arg RTC_IT_TS: TimeStamp interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the RTC TimeStamp interrupt.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be disabled.
+ * This parameter can be:
+ * @arg RTC_IT_TS: TimeStamp interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified RTC TimeStamp interrupt has occurred or not.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt to check.
+ * This parameter can be:
+ * @arg RTC_IT_TS: TimeStamp interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
+
+/**
+ * @brief Check whether the specified RTC Time Stamp interrupt has been enabled or not.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC Time Stamp interrupt source to check.
+ * This parameter can be:
+ * @arg RTC_IT_TS: TimeStamp interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
+
+/**
+ * @brief Get the selected RTC TimeStamp's flag status.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __FLAG__ specifies the RTC TimeStamp Flag is pending or not.
+ * This parameter can be:
+ * @arg RTC_FLAG_TSF
+ * @arg RTC_FLAG_TSOVF
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+
+/**
+ * @brief Clear the RTC Time Stamp's pending flags.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __FLAG__ specifies the RTC Alarm Flag to clear.
+ * This parameter can be:
+ * @arg RTC_FLAG_TSF
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+
+/**
+ * @}
+ */
+
+/* ---------------------------------TAMPER------------------------------------*/
+/** @defgroup RTCEx_Tamper RTC Extended Tamper
+ * @{
+ */
+
+/**
+ * @brief Enable the RTC Tamper1 input detection.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP1E))
+
+/**
+ * @brief Disable the RTC Tamper1 input detection.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP1E))
+
+/**
+ * @brief Enable the RTC Tamper2 input detection.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP2E))
+
+/**
+ * @brief Disable the RTC Tamper2 input detection.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP2E))
+
+#if defined(RTC_TAMPER3_SUPPORT)
+/**
+ * @brief Enable the RTC Tamper3 input detection.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER3_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP3E))
+
+/**
+ * @brief Disable the RTC Tamper3 input detection.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER3_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP3E))
+#endif /* RTC_TAMPER3_SUPPORT */
+
+/**
+ * @brief Enable the RTC Tamper interrupt.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be enabled.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_IT_TAMP: Tamper interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAFCR |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the RTC Tamper interrupt.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be disabled.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_IT_TAMP: Tamper interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAFCR &= ~(__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified RTC Tamper interrupt has occurred or not.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC Tamper interrupt to check.
+ * This parameter can be:
+ * @arg RTC_IT_TAMP1: Tamper1 interrupt
+ * @arg RTC_IT_TAMP2: Tamper2 interrupt
+ * @arg RTC_IT_TAMP3: Tamper3 interrupt (*)
+ * @note (*) RTC_IT_TAMP3 not present on all the devices
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
+
+/**
+ * @brief Check whether the specified RTC Tamper interrupt has been enabled or not.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC Tamper interrupt source to check.
+ * This parameter can be:
+ * @arg RTC_IT_TAMP: Tamper interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAFCR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
+
+ /**
+ * @brief Get the selected RTC Tamper's flag status.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __FLAG__ specifies the RTC Tamper Flag is pending or not.
+ * This parameter can be:
+ * @arg RTC_FLAG_TAMP1F
+ * @arg RTC_FLAG_TAMP2F
+ * @arg RTC_FLAG_TAMP3F (*)
+ * @note (*) RTC_FLAG_TAMP3F not present on all the devices
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+
+
+/**
+ * @brief Clear the RTC Tamper's pending flags.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __FLAG__ specifies the RTC Tamper Flag to clear.
+ * This parameter can be:
+ * @arg RTC_FLAG_TAMP1F
+ * @arg RTC_FLAG_TAMP2F
+ * @arg RTC_FLAG_TAMP3F (*)
+ * @note (*) RTC_FLAG_TAMP3F not present on all the devices
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+
+
+/**
+ * @}
+ */
+
+/* --------------------------TAMPER/TIMESTAMP---------------------------------*/
+/** @defgroup RTCEx_Tamper_Timestamp EXTI RTC Extended Tamper Timestamp EXTI
+ * @{
+ */
+
+/* TAMPER TIMESTAMP EXTI */
+/* --------------------- */
+/**
+ * @brief Enable interrupt on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+
+/**
+ * @brief Disable interrupt on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
+
+/**
+ * @brief Enable event on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+
+/**
+ * @brief Disable event on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
+
+/**
+ * @brief Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+
+/**
+ * @brief Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
+
+/**
+ * @brief Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+
+/**
+ * @brief Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
+
+/**
+ * @brief Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE();
+
+/**
+ * @brief Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * This parameter can be:
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE();
+
+/**
+ * @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.
+ * @retval Line Status.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+
+/**
+ * @brief Clear the RTC Tamper and Timestamp associated Exti line flag.
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+
+/**
+ * @brief Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+/**
+ * @}
+ */
+
+/* ------------------------------Calibration----------------------------------*/
+/** @defgroup RTCEx_Calibration RTC Extended Calibration
+ * @{
+ */
+
+/**
+ * @brief Enable the RTC calibration output.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
+
+/**
+ * @brief Disable the calibration output.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
+
+/**
+ * @brief Enable the clock reference detection.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
+
+/**
+ * @brief Disable the clock reference detection.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
+
+/**
+ * @brief Get the selected RTC shift operation's flag status.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __FLAG__ specifies the RTC shift operation Flag is pending or not.
+ * This parameter can be:
+ * @arg RTC_FLAG_SHPF
+ * @retval None
+ */
+#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
+ * @{
+ */
+
+/* RTC TimeStamp and Tamper functions *****************************************/
+/** @defgroup RTCEx_Exported_Functions_Group1 Extended RTC TimeStamp and Tamper functions
+ * @{
+ */
+
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format);
+
+HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
+HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);
+void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc);
+
+void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/* RTC Wake-up functions ******************************************************/
+/** @defgroup RTCEx_Exported_Functions_Group2 Extended RTC Wake-up functions
+ * @{
+ */
+
+HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
+HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
+uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);
+uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/* Extended Control functions ************************************************/
+/** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions
+ * @{
+ */
+
+void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
+uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
+
+HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue);
+HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS);
+HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc);
+/**
+ * @}
+ */
+
+/* Extended RTC features functions *******************************************/
+/** @defgroup RTCEx_Exported_Functions_Group4 Extended features functions
+ * @{
+ */
+void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup RTCEx_Private_Macros RTCEx Private Macros
+ * @{
+ */
+
+/** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters
+ * @{
+ */
+#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
+ ((OUTPUT) == RTC_OUTPUT_ALARMA) || \
+ ((OUTPUT) == RTC_OUTPUT_ALARMB) || \
+ ((OUTPUT) == RTC_OUTPUT_WAKEUP))
+
+#define IS_RTC_BKP(BKP) ((BKP) < (uint32_t) RTC_BKP_NUMBER)
+
+#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
+ ((EDGE) == RTC_TIMESTAMPEDGE_FALLING))
+
+#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & 0xFFFFFFD6U) == 0x00U) && ((TAMPER) != (uint32_t)RESET))
+
+
+#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT))
+
+
+#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
+ ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
+ ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
+ ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL))
+#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TAMPERFILTER_DISABLE) || \
+ ((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || \
+ ((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || \
+ ((FILTER) == RTC_TAMPERFILTER_8SAMPLE))
+#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512) || \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))
+#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \
+ ((DURATION) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \
+ ((DURATION) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \
+ ((DURATION) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))
+#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
+ ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
+#define IS_RTC_TAMPER_PULLUP_STATE(STATE) (((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \
+ ((STATE) == RTC_TAMPER_PULLUP_DISABLE))
+#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))
+
+#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFFU)
+
+
+#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
+ ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \
+ ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC))
+#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
+ ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))
+
+
+#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FFU)
+#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \
+ ((SEL) == RTC_SHIFTADD1S_SET))
+#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFFU)
+#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \
+ ((OUTPUT) == RTC_CALIBOUTPUT_1HZ))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_RTC_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_hal_sdadc.h b/Inc/stm32f3xx_hal_sdadc.h
new file mode 100644
index 0000000..60a8ebf
--- /dev/null
+++ b/Inc/stm32f3xx_hal_sdadc.h
@@ -0,0 +1,704 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_sdadc.h
+ * @author MCD Application Team
+ * @brief This file contains all the functions prototypes for the SDADC
+ * firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_SDADC_H
+#define __STM32F3xx_SDADC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SDADC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SDADC_Exported_Types SDADC Exported Types
+ * @{
+ */
+
+
+/**
+ * @brief HAL SDADC States definition
+ */
+typedef enum
+{
+ HAL_SDADC_STATE_RESET = 0x00U, /*!< SDADC not initialized */
+ HAL_SDADC_STATE_READY = 0x01U, /*!< SDADC initialized and ready for use */
+ HAL_SDADC_STATE_CALIB = 0x02U, /*!< SDADC calibration in progress */
+ HAL_SDADC_STATE_REG = 0x03U, /*!< SDADC regular conversion in progress */
+ HAL_SDADC_STATE_INJ = 0x04U, /*!< SDADC injected conversion in progress */
+ HAL_SDADC_STATE_REG_INJ = 0x05U, /*!< SDADC regular and injected conversions in progress */
+ HAL_SDADC_STATE_ERROR = 0xFFU, /*!< SDADC state error */
+}HAL_SDADC_StateTypeDef;
+
+/**
+ * @brief SDADC Init Structure definition
+ */
+typedef struct
+{
+ uint32_t IdleLowPowerMode; /*!< Specifies if SDADC can enter in power down or standby when idle.
+ This parameter can be a value of @ref SDADC_Idle_Low_Power_Mode */
+ uint32_t FastConversionMode; /*!< Specifies if Fast conversion mode is enabled or not.
+ This parameter can be a value of @ref SDADC_Fast_Conv_Mode */
+ uint32_t SlowClockMode; /*!< Specifies if slow clock mode is enabled or not.
+ This parameter can be a value of @ref SDADC_Slow_Clock_Mode */
+ uint32_t ReferenceVoltage; /*!< Specifies the reference voltage.
+ Note: This parameter is common to all SDADC instances.
+ This parameter can be a value of @ref SDADC_Reference_Voltage */
+}SDADC_InitTypeDef;
+
+/**
+ * @brief SDADC handle Structure definition
+ */
+typedef struct
+{
+ SDADC_TypeDef *Instance; /*!< SDADC registers base address */
+ SDADC_InitTypeDef Init; /*!< SDADC init parameters */
+ DMA_HandleTypeDef *hdma; /*!< SDADC DMA Handle parameters */
+ uint32_t RegularContMode; /*!< Regular conversion continuous mode */
+ uint32_t InjectedContMode; /*!< Injected conversion continuous mode */
+ uint32_t InjectedChannelsNbr; /*!< Number of channels in injected sequence */
+ uint32_t InjConvRemaining; /*!< Injected conversion remaining */
+ uint32_t RegularTrigger; /*!< Current trigger used for regular conversion */
+ uint32_t InjectedTrigger; /*!< Current trigger used for injected conversion */
+ uint32_t ExtTriggerEdge; /*!< Rising, falling or both edges selected */
+ uint32_t RegularMultimode; /*!< current type of regular multimode */
+ uint32_t InjectedMultimode; /*!< Current type of injected multimode */
+ HAL_SDADC_StateTypeDef State; /*!< SDADC state */
+ uint32_t ErrorCode; /*!< SDADC Error code */
+}SDADC_HandleTypeDef;
+
+/**
+ * @brief SDADC Configuration Register Parameter Structure
+ */
+typedef struct
+{
+ uint32_t InputMode; /*!< Specifies the input mode (single ended, differential...)
+ This parameter can be any value of @ref SDADC_InputMode */
+ uint32_t Gain; /*!< Specifies the gain setting.
+ This parameter can be any value of @ref SDADC_Gain */
+ uint32_t CommonMode; /*!< Specifies the common mode setting (VSSA, VDDA, VDDA/2U).
+ This parameter can be any value of @ref SDADC_CommonMode */
+ uint32_t Offset; /*!< Specifies the 12-bit offset value.
+ This parameter can be any value lower or equal to 0x00000FFFU */
+}SDADC_ConfParamTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SDADC_Exported_Constants SDADC Exported Constants
+ * @{
+ */
+
+/** @defgroup SDADC_Idle_Low_Power_Mode SDADC Idle Low Power Mode
+ * @{
+ */
+#define SDADC_LOWPOWER_NONE (0x00000000UL)
+#define SDADC_LOWPOWER_POWERDOWN SDADC_CR1_PDI
+#define SDADC_LOWPOWER_STANDBY SDADC_CR1_SBI
+/**
+ * @}
+ */
+
+/** @defgroup SDADC_Fast_Conv_Mode SDADC Fast Conversion Mode
+ * @{
+ */
+#define SDADC_FAST_CONV_DISABLE (0x00000000UL)
+#define SDADC_FAST_CONV_ENABLE SDADC_CR2_FAST
+/**
+ * @}
+ */
+
+/** @defgroup SDADC_Slow_Clock_Mode SDADC Slow Clock Mode
+ * @{
+ */
+#define SDADC_SLOW_CLOCK_DISABLE (0x00000000UL)
+#define SDADC_SLOW_CLOCK_ENABLE SDADC_CR1_SLOWCK
+/**
+ * @}
+ */
+
+/** @defgroup SDADC_Reference_Voltage SDADC Reference Voltage
+ * @{
+ */
+#define SDADC_VREF_EXT (0x00000000UL) /*!< The reference voltage is forced externally using VREF pin */
+#define SDADC_VREF_VREFINT1 SDADC_CR1_REFV_0 /*!< The reference voltage is forced internally to 1.22V VREFINT */
+#define SDADC_VREF_VREFINT2 SDADC_CR1_REFV_1 /*!< The reference voltage is forced internally to 1.8V VREFINT */
+#define SDADC_VREF_VDDA SDADC_CR1_REFV /*!< The reference voltage is forced internally to VDDA */
+/**
+ * @}
+ */
+
+/** @defgroup SDADC_ConfIndex SDADC Configuration Index
+ * @{
+ */
+
+#define SDADC_CONF_INDEX_0 (0x00000000UL) /*!< Configuration 0 Register selected */
+#define SDADC_CONF_INDEX_1 (0x00000001U) /*!< Configuration 1 Register selected */
+#define SDADC_CONF_INDEX_2 (0x00000002U) /*!< Configuration 2 Register selected */
+/**
+ * @}
+ */
+
+/** @defgroup SDADC_InputMode SDADC Input Mode
+ * @{
+ */
+#define SDADC_INPUT_MODE_DIFF (0x00000000UL) /*!< Conversions are executed in differential mode */
+#define SDADC_INPUT_MODE_SE_OFFSET SDADC_CONF0R_SE0_0 /*!< Conversions are executed in single ended offset mode */
+#define SDADC_INPUT_MODE_SE_ZERO_REFERENCE SDADC_CONF0R_SE0 /*!< Conversions are executed in single ended zero-volt reference mode */
+/**
+ * @}
+ */
+
+/** @defgroup SDADC_Gain SDADC Gain
+ * @{
+ */
+#define SDADC_GAIN_1 (0x00000000UL) /*!< Gain equal to 1U */
+#define SDADC_GAIN_2 SDADC_CONF0R_GAIN0_0 /*!< Gain equal to 2U */
+#define SDADC_GAIN_4 SDADC_CONF0R_GAIN0_1 /*!< Gain equal to 4U */
+#define SDADC_GAIN_8 (0x00300000U) /*!< Gain equal to 8U */
+#define SDADC_GAIN_16 SDADC_CONF0R_GAIN0_2 /*!< Gain equal to 16U */
+#define SDADC_GAIN_32 (0x00500000U) /*!< Gain equal to 32U */
+#define SDADC_GAIN_1_2 SDADC_CONF0R_GAIN0 /*!< Gain equal to 1U/2U */
+/**
+ * @}
+ */
+
+/** @defgroup SDADC_CommonMode SDADC Common Mode
+ * @{
+ */
+#define SDADC_COMMON_MODE_VSSA (0x00000000UL) /*!< Select SDADC VSSA as common mode */
+#define SDADC_COMMON_MODE_VDDA_2 SDADC_CONF0R_COMMON0_0 /*!< Select SDADC VDDA/2 as common mode */
+#define SDADC_COMMON_MODE_VDDA SDADC_CONF0R_COMMON0_1 /*!< Select SDADC VDDA as common mode */
+/**
+ * @}
+ */
+
+
+
+/** @defgroup SDADC_Channel_Selection SDADC Channel Selection
+ * @{
+ */
+
+/* SDADC Channels ------------------------------------------------------------*/
+/* The SDADC channels are defined as follows:
+ - in 16-bit LSB the channel mask is set
+ - in 16-bit MSB the channel number is set
+ e.g. for channel 5 definition:
+ - the channel mask is 0x00000020 (bit 5 is set)
+ - the channel number 5 is 0x00050000
+ --> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */
+#define SDADC_CHANNEL_0 (0x00000001UL)
+#define SDADC_CHANNEL_1 (0x00010002UL)
+#define SDADC_CHANNEL_2 (0x00020004UL)
+#define SDADC_CHANNEL_3 (0x00030008UL)
+#define SDADC_CHANNEL_4 (0x00040010UL)
+#define SDADC_CHANNEL_5 (0x00050020UL)
+#define SDADC_CHANNEL_6 (0x00060040UL)
+#define SDADC_CHANNEL_7 (0x00070080UL)
+#define SDADC_CHANNEL_8 (0x00080100UL)
+/**
+ * @}
+ */
+
+/** @defgroup SDADC_CalibrationSequence SDADC Calibration Sequence
+ * @{
+ */
+#define SDADC_CALIBRATION_SEQ_1 (0x00000000UL) /*!< One calibration sequence to calculate offset of conf0 (OFFSET0[11:0]) */
+#define SDADC_CALIBRATION_SEQ_2 SDADC_CR2_CALIBCNT_0 /*!< Two calibration sequences to calculate offset of conf0 and conf1 (OFFSET0[11:0] and OFFSET1[11:0]) */
+#define SDADC_CALIBRATION_SEQ_3 SDADC_CR2_CALIBCNT_1 /*!< Three calibration sequences to calculate offset of conf0, conf1 and conf2 (OFFSET0[11:0], OFFSET1[11:0], and OFFSET2[11:0]) */
+/**
+ * @}
+ */
+
+/** @defgroup SDADC_ContinuousMode SDADC Continuous Mode
+ * @{
+ */
+#define SDADC_CONTINUOUS_CONV_OFF (0x00000000UL) /*!< Conversion are not continuous */
+#define SDADC_CONTINUOUS_CONV_ON (0x00000001UL) /*!< Conversion are continuous */
+/**
+ * @}
+ */
+
+/** @defgroup SDADC_Trigger SDADC Trigger
+ * @{
+ */
+#define SDADC_SOFTWARE_TRIGGER (0x00000000UL) /*!< Software trigger */
+#define SDADC_SYNCHRONOUS_TRIGGER (0x00000001UL) /*!< Synchronous with SDADC1 (only for SDADC2 and SDADC3) */
+#define SDADC_EXTERNAL_TRIGGER (0x00000002UL) /*!< External trigger */
+/**
+ * @}
+ */
+
+/** @defgroup SDADC_InjectedExtTrigger SDADC Injected External Trigger
+ * @{
+ */
+#define SDADC_EXT_TRIG_TIM13_CC1 (0x00000000UL) /*!< Trigger source for SDADC1 */
+#define SDADC_EXT_TRIG_TIM14_CC1 (0x00000100UL) /*!< Trigger source for SDADC1 */
+#define SDADC_EXT_TRIG_TIM16_CC1 (0x00000000UL) /*!< Trigger source for SDADC3 */
+#define SDADC_EXT_TRIG_TIM17_CC1 (0x00000000UL) /*!< Trigger source for SDADC2 */
+#define SDADC_EXT_TRIG_TIM12_CC1 (0x00000100UL) /*!< Trigger source for SDADC2 */
+#define SDADC_EXT_TRIG_TIM12_CC2 (0x00000100UL) /*!< Trigger source for SDADC3 */
+#define SDADC_EXT_TRIG_TIM15_CC2 (0x00000200UL) /*!< Trigger source for SDADC1 */
+#define SDADC_EXT_TRIG_TIM2_CC3 (0x00000200UL) /*!< Trigger source for SDADC2 */
+#define SDADC_EXT_TRIG_TIM2_CC4 (0x00000200UL) /*!< Trigger source for SDADC3 */
+#define SDADC_EXT_TRIG_TIM3_CC1 (0x00000300UL) /*!< Trigger source for SDADC1 */
+#define SDADC_EXT_TRIG_TIM3_CC2 (0x00000300UL) /*!< Trigger source for SDADC2 */
+#define SDADC_EXT_TRIG_TIM3_CC3 (0x00000300UL) /*!< Trigger source for SDADC3 */
+#define SDADC_EXT_TRIG_TIM4_CC1 (0x00000400UL) /*!< Trigger source for SDADC1 */
+#define SDADC_EXT_TRIG_TIM4_CC2 (0x00000400UL) /*!< Trigger source for SDADC2 */
+#define SDADC_EXT_TRIG_TIM4_CC3 (0x00000400UL) /*!< Trigger source for SDADC3 */
+#define SDADC_EXT_TRIG_TIM19_CC2 (0x00000500UL) /*!< Trigger source for SDADC1 */
+#define SDADC_EXT_TRIG_TIM19_CC3 (0x00000500UL) /*!< Trigger source for SDADC2 */
+#define SDADC_EXT_TRIG_TIM19_CC4 (0x00000500UL) /*!< Trigger source for SDADC3 */
+#define SDADC_EXT_TRIG_EXTI11 (0x00000700UL) /*!< Trigger source for SDADC1, SDADC2 and SDADC3 */
+#define SDADC_EXT_TRIG_EXTI15 (0x00000600UL) /*!< Trigger source for SDADC1, SDADC2 and SDADC3 */
+/**
+ * @}
+ */
+
+/** @defgroup SDADC_ExtTriggerEdge SDADC External Trigger Edge
+ * @{
+ */
+#define SDADC_EXT_TRIG_RISING_EDGE SDADC_CR2_JEXTEN_0 /*!< External rising edge */
+#define SDADC_EXT_TRIG_FALLING_EDGE SDADC_CR2_JEXTEN_1 /*!< External falling edge */
+#define SDADC_EXT_TRIG_BOTH_EDGES SDADC_CR2_JEXTEN /*!< External rising and falling edges */
+/**
+ * @}
+ */
+
+/** @defgroup SDADC_InjectedDelay SDADC Injected Conversion Delay
+ * @{
+ */
+#define SDADC_INJECTED_DELAY_NONE (0x00000000UL) /*!< No delay on injected conversion */
+#define SDADC_INJECTED_DELAY SDADC_CR2_JDS /*!< Delay on injected conversion */
+/**
+ * @}
+ */
+
+/** @defgroup SDADC_MultimodeType SDADC Multimode Type
+ * @{
+ */
+#define SDADC_MULTIMODE_SDADC1_SDADC2 (0x00000000UL) /*!< Get conversion values for SDADC1 and SDADC2 */
+#define SDADC_MULTIMODE_SDADC1_SDADC3 (0x00000001U) /*!< Get conversion values for SDADC1 and SDADC3 */
+/**
+ * @}
+ */
+
+/** @defgroup SDADC_ErrorCode SDADC Error Code
+ * @{
+ */
+#define SDADC_ERROR_NONE (0x00000000UL) /*!< No error */
+#define SDADC_ERROR_REGULAR_OVERRUN (0x00000001UL) /*!< Overrun occurs during regular conversion */
+#define SDADC_ERROR_INJECTED_OVERRUN (0x00000002UL) /*!< Overrun occurs during injected conversion */
+#define SDADC_ERROR_DMA (0x00000003UL) /*!< DMA error occurs */
+/**
+ * @}
+ */
+
+/** @defgroup SDADC_interrupts_definition SDADC interrupts definition
+ * @{
+ */
+#define SDADC_IT_EOCAL SDADC_CR1_EOCALIE /*!< End of calibration interrupt enable */
+#define SDADC_IT_JEOC SDADC_CR1_JEOCIE /*!< Injected end of conversion interrupt enable */
+#define SDADC_IT_JOVR SDADC_CR1_JOVRIE /*!< Injected data overrun interrupt enable */
+#define SDADC_IT_REOC SDADC_CR1_REOCIE /*!< Regular end of conversion interrupt enable */
+#define SDADC_IT_ROVR SDADC_CR1_ROVRIE /*!< Regular data overrun interrupt enable */
+/**
+ * @}
+ */
+
+/** @defgroup SDADC_flags_definition SDADC flags definition
+ * @{
+ */
+#define SDADC_FLAG_EOCAL SDADC_ISR_EOCALF /*!< End of calibration flag */
+#define SDADC_FLAG_JEOC SDADC_ISR_JEOCF /*!< End of injected conversion flag */
+#define SDADC_FLAG_JOVR SDADC_ISR_JOVRF /*!< Injected conversion overrun flag */
+#define SDADC_FLAG_REOC SDADC_ISR_REOCF /*!< End of regular conversion flag */
+#define SDADC_FLAG_ROVR SDADC_ISR_ROVRF /*!< Regular conversion overrun flag */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup SDADC_Exported_Macros SDADC Exported Macros
+ * @{
+ */
+
+/* Macro for internal HAL driver usage, and possibly can be used into code of */
+/* final user. */
+
+/** @brief Enable the ADC end of conversion interrupt.
+ * @param __HANDLE__ ADC handle
+ * @param __INTERRUPT__ ADC Interrupt
+ * This parameter can be any combination of the following values:
+ * @arg SDADC_IT_EOCAL: End of calibration interrupt enable
+ * @arg SDADC_IT_JEOC: Injected end of conversion interrupt enable
+ * @arg SDADC_IT_JOVR: Injected data overrun interrupt enable
+ * @arg SDADC_IT_REOC: Regular end of conversion interrupt enable
+ * @arg SDADC_IT_ROVR: Regular data overrun interrupt enable
+ * @retval None
+ */
+#define __HAL_SDADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
+ (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
+
+/** @brief Disable the ADC end of conversion interrupt.
+ * @param __HANDLE__ ADC handle
+ * @param __INTERRUPT__ ADC Interrupt
+ * This parameter can be any combination of the following values:
+ * @arg SDADC_IT_EOCAL: End of calibration interrupt enable
+ * @arg SDADC_IT_JEOC: Injected end of conversion interrupt enable
+ * @arg SDADC_IT_JOVR: Injected data overrun interrupt enable
+ * @arg SDADC_IT_REOC: Regular end of conversion interrupt enable
+ * @arg SDADC_IT_ROVR: Regular data overrun interrupt enable
+ * @retval None
+ */
+#define __HAL_SDADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
+ (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
+
+/** @brief Checks if the specified ADC interrupt source is enabled or disabled.
+ * @param __HANDLE__ ADC handle
+ * @param __INTERRUPT__ ADC interrupt source to check
+ * This parameter can be any combination of the following values:
+ * @arg SDADC_IT_EOCAL: End of calibration interrupt enable
+ * @arg SDADC_IT_JEOC: Injected end of conversion interrupt enable
+ * @arg SDADC_IT_JOVR: Injected data overrun interrupt enable
+ * @arg SDADC_IT_REOC: Regular end of conversion interrupt enable
+ * @arg SDADC_IT_ROVR: Regular data overrun interrupt enable
+ * @retval State of interruption (SET or RESET)
+ */
+#define __HAL_SDADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/** @brief Get the selected ADC's flag status.
+ * @param __HANDLE__ ADC handle
+ * @param __FLAG__ ADC flag
+ * This parameter can be any combination of the following values:
+ * @arg SDADC_FLAG_EOCAL: End of calibration flag
+ * @arg SDADC_FLAG_JEOC: End of injected conversion flag
+ * @arg SDADC_FLAG_JOVR: Injected conversion overrun flag
+ * @arg SDADC_FLAG_REOC: End of regular conversion flag
+ * @arg SDADC_FLAG_ROVR: Regular conversion overrun flag
+ * @retval None
+ */
+#define __HAL_SDADC_GET_FLAG(__HANDLE__, __FLAG__) \
+ ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the ADC's pending flags
+ * @param __HANDLE__ ADC handle
+ * @param __FLAG__ ADC flag
+ * This parameter can be any combination of the following values:
+ * @arg SDADC_FLAG_EOCAL: End of calibration flag
+ * @arg SDADC_FLAG_JEOC: End of injected conversion flag
+ * @arg SDADC_FLAG_JOVR: Injected conversion overrun flag
+ * @arg SDADC_FLAG_REOC: End of regular conversion flag
+ * @arg SDADC_FLAG_ROVR: Regular conversion overrun flag
+ * @retval None
+ */
+#define __HAL_SDADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+ (CLEAR_BIT((__HANDLE__)->Instance->ISR, (__FLAG__)))
+
+/** @brief Reset SDADC handle state
+ * @param __HANDLE__ SDADC handle.
+ * @retval None
+ */
+#define __HAL_SDADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDADC_STATE_RESET)
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SDADC_Private_Macros SDADC Private Macros
+ * @{
+ */
+
+#define IS_SDADC_LOWPOWER_MODE(LOWPOWER) (((LOWPOWER) == SDADC_LOWPOWER_NONE) || \
+ ((LOWPOWER) == SDADC_LOWPOWER_POWERDOWN) || \
+ ((LOWPOWER) == SDADC_LOWPOWER_STANDBY))
+
+#define IS_SDADC_FAST_CONV_MODE(FAST) (((FAST) == SDADC_FAST_CONV_DISABLE) || \
+ ((FAST) == SDADC_FAST_CONV_ENABLE))
+
+#define IS_SDADC_SLOW_CLOCK_MODE(MODE) (((MODE) == SDADC_SLOW_CLOCK_DISABLE) || \
+ ((MODE) == SDADC_SLOW_CLOCK_ENABLE))
+
+#define IS_SDADC_VREF(VREF) (((VREF) == SDADC_VREF_EXT) || \
+ ((VREF) == SDADC_VREF_VREFINT1) || \
+ ((VREF) == SDADC_VREF_VREFINT2) || \
+ ((VREF) == SDADC_VREF_VDDA))
+
+#define IS_SDADC_CONF_INDEX(CONF) (((CONF) == SDADC_CONF_INDEX_0) || \
+ ((CONF) == SDADC_CONF_INDEX_1) || \
+ ((CONF) == SDADC_CONF_INDEX_2))
+
+#define IS_SDADC_INPUT_MODE(MODE) (((MODE) == SDADC_INPUT_MODE_DIFF) || \
+ ((MODE) == SDADC_INPUT_MODE_SE_OFFSET) || \
+ ((MODE) == SDADC_INPUT_MODE_SE_ZERO_REFERENCE))
+
+#define IS_SDADC_GAIN(GAIN) (((GAIN) == SDADC_GAIN_1) || \
+ ((GAIN) == SDADC_GAIN_2) || \
+ ((GAIN) == SDADC_GAIN_4) || \
+ ((GAIN) == SDADC_GAIN_8) || \
+ ((GAIN) == SDADC_GAIN_16) || \
+ ((GAIN) == SDADC_GAIN_32) || \
+ ((GAIN) == SDADC_GAIN_1_2))
+
+#define IS_SDADC_COMMON_MODE(MODE) (((MODE) == SDADC_COMMON_MODE_VSSA) || \
+ ((MODE) == SDADC_COMMON_MODE_VDDA_2) || \
+ ((MODE) == SDADC_COMMON_MODE_VDDA))
+
+#define IS_SDADC_OFFSET_VALUE(VALUE) ((VALUE) <= 0x00000FFFU)
+
+/* Just one channel of the 9 channels can be selected for regular conversion */
+#define IS_SDADC_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == SDADC_CHANNEL_0) || \
+ ((CHANNEL) == SDADC_CHANNEL_1) || \
+ ((CHANNEL) == SDADC_CHANNEL_2) || \
+ ((CHANNEL) == SDADC_CHANNEL_3) || \
+ ((CHANNEL) == SDADC_CHANNEL_4) || \
+ ((CHANNEL) == SDADC_CHANNEL_5) || \
+ ((CHANNEL) == SDADC_CHANNEL_6) || \
+ ((CHANNEL) == SDADC_CHANNEL_7) || \
+ ((CHANNEL) == SDADC_CHANNEL_8))
+
+/* Any or all of the 9 channels can be selected for injected conversion */
+#define IS_SDADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x000F01FFU))
+
+
+#define IS_SDADC_CALIB_SEQUENCE(SEQUENCE) (((SEQUENCE) == SDADC_CALIBRATION_SEQ_1) || \
+ ((SEQUENCE) == SDADC_CALIBRATION_SEQ_2) || \
+ ((SEQUENCE) == SDADC_CALIBRATION_SEQ_3))
+
+#define IS_SDADC_CONTINUOUS_MODE(MODE) (((MODE) == SDADC_CONTINUOUS_CONV_OFF) || \
+ ((MODE) == SDADC_CONTINUOUS_CONV_ON))
+
+
+#define IS_SDADC_REGULAR_TRIGGER(TRIGGER) (((TRIGGER) == SDADC_SOFTWARE_TRIGGER) || \
+ ((TRIGGER) == SDADC_SYNCHRONOUS_TRIGGER))
+
+#define IS_SDADC_INJECTED_TRIGGER(TRIGGER) (((TRIGGER) == SDADC_SOFTWARE_TRIGGER) || \
+ ((TRIGGER) == SDADC_SYNCHRONOUS_TRIGGER) || \
+ ((TRIGGER) == SDADC_EXTERNAL_TRIGGER))
+
+
+#define IS_SDADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == SDADC_EXT_TRIG_TIM13_CC1) || \
+ ((INJTRIG) == SDADC_EXT_TRIG_TIM14_CC1) || \
+ ((INJTRIG) == SDADC_EXT_TRIG_TIM16_CC1) || \
+ ((INJTRIG) == SDADC_EXT_TRIG_TIM17_CC1) || \
+ ((INJTRIG) == SDADC_EXT_TRIG_TIM12_CC1) || \
+ ((INJTRIG) == SDADC_EXT_TRIG_TIM12_CC2) || \
+ ((INJTRIG) == SDADC_EXT_TRIG_TIM15_CC2) || \
+ ((INJTRIG) == SDADC_EXT_TRIG_TIM2_CC3) || \
+ ((INJTRIG) == SDADC_EXT_TRIG_TIM2_CC4) || \
+ ((INJTRIG) == SDADC_EXT_TRIG_TIM3_CC1) || \
+ ((INJTRIG) == SDADC_EXT_TRIG_TIM3_CC2) || \
+ ((INJTRIG) == SDADC_EXT_TRIG_TIM3_CC3) || \
+ ((INJTRIG) == SDADC_EXT_TRIG_TIM4_CC1) || \
+ ((INJTRIG) == SDADC_EXT_TRIG_TIM4_CC2) || \
+ ((INJTRIG) == SDADC_EXT_TRIG_TIM4_CC3) || \
+ ((INJTRIG) == SDADC_EXT_TRIG_TIM19_CC2) || \
+ ((INJTRIG) == SDADC_EXT_TRIG_TIM19_CC3) || \
+ ((INJTRIG) == SDADC_EXT_TRIG_TIM19_CC4) || \
+ ((INJTRIG) == SDADC_EXT_TRIG_EXTI11) || \
+ ((INJTRIG) == SDADC_EXT_TRIG_EXTI15))
+
+#define IS_SDADC_EXT_TRIG_EDGE(TRIGGER) (((TRIGGER) == SDADC_EXT_TRIG_RISING_EDGE) || \
+ ((TRIGGER) == SDADC_EXT_TRIG_FALLING_EDGE) || \
+ ((TRIGGER) == SDADC_EXT_TRIG_BOTH_EDGES))
+
+
+#define IS_SDADC_INJECTED_DELAY(DELAY) (((DELAY) == SDADC_INJECTED_DELAY_NONE) || \
+ ((DELAY) == SDADC_INJECTED_DELAY))
+
+#define IS_SDADC_MULTIMODE_TYPE(TYPE) (((TYPE) == SDADC_MULTIMODE_SDADC1_SDADC2) || \
+ ((TYPE) == SDADC_MULTIMODE_SDADC1_SDADC3))
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SDADC_Exported_Functions SDADC Exported Functions
+ * @{
+ */
+
+/** @addtogroup SDADC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_SDADC_Init(SDADC_HandleTypeDef *hsdadc);
+HAL_StatusTypeDef HAL_SDADC_DeInit(SDADC_HandleTypeDef *hsdadc);
+void HAL_SDADC_MspInit(SDADC_HandleTypeDef* hsdadc);
+void HAL_SDADC_MspDeInit(SDADC_HandleTypeDef* hsdadc);
+
+/**
+ * @}
+ */
+
+/** @addtogroup SDADC_Exported_Functions_Group2 peripheral control functions
+ * @{
+ */
+
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_SDADC_PrepareChannelConfig(SDADC_HandleTypeDef *hsdadc,
+ uint32_t ConfIndex,
+ SDADC_ConfParamTypeDef* ConfParamStruct);
+HAL_StatusTypeDef HAL_SDADC_AssociateChannelConfig(SDADC_HandleTypeDef *hsdadc,
+ uint32_t Channel,
+ uint32_t ConfIndex);
+HAL_StatusTypeDef HAL_SDADC_ConfigChannel(SDADC_HandleTypeDef *hsdadc,
+ uint32_t Channel,
+ uint32_t ContinuousMode);
+HAL_StatusTypeDef HAL_SDADC_InjectedConfigChannel(SDADC_HandleTypeDef *hsdadc,
+ uint32_t Channel,
+ uint32_t ContinuousMode);
+HAL_StatusTypeDef HAL_SDADC_SelectInjectedExtTrigger(SDADC_HandleTypeDef *hsdadc,
+ uint32_t InjectedExtTrigger,
+ uint32_t ExtTriggerEdge);
+HAL_StatusTypeDef HAL_SDADC_SelectInjectedDelay(SDADC_HandleTypeDef *hsdadc,
+ uint32_t InjectedDelay);
+HAL_StatusTypeDef HAL_SDADC_SelectRegularTrigger(SDADC_HandleTypeDef *hsdadc, uint32_t Trigger);
+HAL_StatusTypeDef HAL_SDADC_SelectInjectedTrigger(SDADC_HandleTypeDef *hsdadc, uint32_t Trigger);
+HAL_StatusTypeDef HAL_SDADC_MultiModeConfigChannel(SDADC_HandleTypeDef* hsdadc, uint32_t MultimodeType);
+HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeConfigChannel(SDADC_HandleTypeDef* hsdadc, uint32_t MultimodeType);
+
+/**
+ * @}
+ */
+
+/** @addtogroup SDADC_Exported_Functions_Group3 Input and Output operation functions
+ * @{
+ */
+
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_SDADC_CalibrationStart(SDADC_HandleTypeDef *hsdadc, uint32_t CalibrationSequence);
+HAL_StatusTypeDef HAL_SDADC_CalibrationStart_IT(SDADC_HandleTypeDef *hsdadc, uint32_t CalibrationSequence);
+
+HAL_StatusTypeDef HAL_SDADC_Start(SDADC_HandleTypeDef *hsdadc);
+HAL_StatusTypeDef HAL_SDADC_Start_IT(SDADC_HandleTypeDef *hsdadc);
+HAL_StatusTypeDef HAL_SDADC_Start_DMA(SDADC_HandleTypeDef *hsdadc, uint32_t *pData, uint32_t Length);
+HAL_StatusTypeDef HAL_SDADC_Stop(SDADC_HandleTypeDef *hsdadc);
+HAL_StatusTypeDef HAL_SDADC_Stop_IT(SDADC_HandleTypeDef *hsdadc);
+HAL_StatusTypeDef HAL_SDADC_Stop_DMA(SDADC_HandleTypeDef *hsdadc);
+
+HAL_StatusTypeDef HAL_SDADC_InjectedStart(SDADC_HandleTypeDef *hsdadc);
+HAL_StatusTypeDef HAL_SDADC_InjectedStart_IT(SDADC_HandleTypeDef *hsdadc);
+HAL_StatusTypeDef HAL_SDADC_InjectedStart_DMA(SDADC_HandleTypeDef *hsdadc, uint32_t *pData, uint32_t Length);
+HAL_StatusTypeDef HAL_SDADC_InjectedStop(SDADC_HandleTypeDef *hsdadc);
+HAL_StatusTypeDef HAL_SDADC_InjectedStop_IT(SDADC_HandleTypeDef *hsdadc);
+HAL_StatusTypeDef HAL_SDADC_InjectedStop_DMA(SDADC_HandleTypeDef *hsdadc);
+
+HAL_StatusTypeDef HAL_SDADC_MultiModeStart_DMA(SDADC_HandleTypeDef* hsdadc, uint32_t* pData, uint32_t Length);
+HAL_StatusTypeDef HAL_SDADC_MultiModeStop_DMA(SDADC_HandleTypeDef* hsdadc);
+HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeStart_DMA(SDADC_HandleTypeDef* hsdadc, uint32_t* pData, uint32_t Length);
+HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeStop_DMA(SDADC_HandleTypeDef* hsdadc);
+
+uint32_t HAL_SDADC_GetValue(SDADC_HandleTypeDef *hsdadc);
+uint32_t HAL_SDADC_InjectedGetValue(SDADC_HandleTypeDef *hsdadc, uint32_t* Channel);
+uint32_t HAL_SDADC_MultiModeGetValue(SDADC_HandleTypeDef* hsdadc);
+uint32_t HAL_SDADC_InjectedMultiModeGetValue(SDADC_HandleTypeDef* hsdadc);
+
+void HAL_SDADC_IRQHandler(SDADC_HandleTypeDef* hsdadc);
+
+HAL_StatusTypeDef HAL_SDADC_PollForCalibEvent(SDADC_HandleTypeDef* hsdadc, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SDADC_PollForConversion(SDADC_HandleTypeDef* hsdadc, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SDADC_PollForInjectedConversion(SDADC_HandleTypeDef* hsdadc, uint32_t Timeout);
+
+void HAL_SDADC_CalibrationCpltCallback(SDADC_HandleTypeDef* hsdadc);
+void HAL_SDADC_ConvHalfCpltCallback(SDADC_HandleTypeDef* hsdadc);
+void HAL_SDADC_ConvCpltCallback(SDADC_HandleTypeDef* hsdadc);
+void HAL_SDADC_InjectedConvHalfCpltCallback(SDADC_HandleTypeDef* hsdadc);
+void HAL_SDADC_InjectedConvCpltCallback(SDADC_HandleTypeDef* hsdadc);
+void HAL_SDADC_ErrorCallback(SDADC_HandleTypeDef* hsdadc);
+
+/**
+ * @}
+ */
+
+/** @defgroup SDADC_Exported_Functions_Group4 Peripheral State functions
+ * @{
+ */
+
+/* Peripheral State and Error functions ***************************************/
+HAL_SDADC_StateTypeDef HAL_SDADC_GetState(SDADC_HandleTypeDef* hsdadc);
+uint32_t HAL_SDADC_GetError(SDADC_HandleTypeDef* hsdadc);
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(STM32F373xC) || defined(STM32F378xx) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F3xx_SDADC_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_hal_smartcard.h b/Inc/stm32f3xx_hal_smartcard.h
new file mode 100644
index 0000000..1b16961
--- /dev/null
+++ b/Inc/stm32f3xx_hal_smartcard.h
@@ -0,0 +1,1070 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_smartcard.h
+ * @author MCD Application Team
+ * @brief Header file of SMARTCARD HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_SMARTCARD_H
+#define __STM32F3xx_HAL_SMARTCARD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SMARTCARD
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types
+ * @{
+ */
+
+/**
+ * @brief SMARTCARD Init Structure definition
+ */
+typedef struct
+{
+ uint32_t BaudRate; /*!< Configures the SmartCard communication baud rate.
+ The baud rate register is computed using the following formula:
+ Baud Rate Register = ((PCLKx) / ((hsmartcard->Init.BaudRate))) */
+
+ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter @ref SMARTCARD_Word_Length can only be set to 9 (8 data + 1 parity bits). */
+
+ uint32_t StopBits; /*!< Specifies the number of stop bits.
+ This parameter can be a value of @ref SMARTCARD_Stop_Bits. */
+
+ uint16_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref SMARTCARD_Parity
+ @note The parity is enabled by default (PCE is forced to 1U).
+ Since the WordLength is forced to 8 bits + parity, M is
+ forced to 1 and the parity bit is the 9th bit. */
+
+ uint16_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref SMARTCARD_Mode */
+
+ uint16_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
+ This parameter can be a value of @ref SMARTCARD_Clock_Polarity */
+
+ uint16_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.
+ This parameter can be a value of @ref SMARTCARD_Clock_Phase */
+
+ uint16_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
+ data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+ This parameter can be a value of @ref SMARTCARD_Last_Bit */
+
+ uint16_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected.
+ Selecting the single sample method increases the receiver tolerance to clock
+ deviations. This parameter can be a value of @ref SMARTCARD_OneBit_Sampling. */
+
+ uint8_t Prescaler; /*!< Specifies the SmartCard Prescaler. */
+
+ uint8_t GuardTime; /*!< Specifies the SmartCard Guard Time applied after stop bits. */
+
+ uint16_t NACKEnable; /*!< Specifies whether the SmartCard NACK transmission is enabled
+ in case of parity error.
+ This parameter can be a value of @ref SMARTCARD_NACK_Enable */
+
+ uint32_t TimeOutEnable; /*!< Specifies whether the receiver timeout is enabled.
+ This parameter can be a value of @ref SMARTCARD_Timeout_Enable*/
+
+ uint32_t TimeOutValue; /*!< Specifies the receiver time out value in number of baud blocks:
+ it is used to implement the Character Wait Time (CWT) and
+ Block Wait Time (BWT). It is coded over 24 bits. */
+
+ uint8_t BlockLength; /*!< Specifies the SmartCard Block Length in T=1 Reception mode.
+ This parameter can be any value from 0x0 to 0xFFU */
+
+ uint8_t AutoRetryCount; /*!< Specifies the SmartCard auto-retry count (number of retries in
+ receive and transmit mode). When set to 0U, retransmission is
+ disabled. Otherwise, its maximum value is 7 (before signalling
+ an error) */
+
+}SMARTCARD_InitTypeDef;
+
+/**
+ * @brief SMARTCARD advanced features initalization structure definition
+ */
+typedef struct
+{
+ uint32_t AdvFeatureInit; /*!< Specifies which advanced SMARTCARD features is initialized. Several
+ advanced features may be initialized at the same time. This parameter
+ can be a value of @ref SMARTCARD_Advanced_Features_Initialization_Type */
+
+ uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted.
+ This parameter can be a value of @ref SMARTCARD_Tx_Inv */
+
+ uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted.
+ This parameter can be a value of @ref SMARTCARD_Rx_Inv */
+
+ uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic
+ vs negative/inverted logic).
+ This parameter can be a value of @ref SMARTCARD_Data_Inv */
+
+ uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped.
+ This parameter can be a value of @ref SMARTCARD_Rx_Tx_Swap */
+
+ uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled.
+ This parameter can be a value of @ref SMARTCARD_Overrun_Disable */
+
+ uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error.
+ This parameter can be a value of @ref SMARTCARD_DMA_Disable_on_Rx_Error */
+
+ uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line.
+ This parameter can be a value of @ref SMARTCARD_MSB_First */
+}SMARTCARD_AdvFeatureInitTypeDef;
+
+/**
+ * @brief HAL SMARTCARD State structures definition
+ * @note HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState.
+ * - gState contains SMARTCARD state information related to global Handle management
+ * and also information related to Tx operations.
+ * gState value coding follow below described bitmap :
+ * b7-b6 Error information
+ * 00 : No Error
+ * 01 : (Not Used)
+ * 10 : Timeout
+ * 11 : Error
+ * b5 IP initilisation status
+ * 0 : Reset (IP not initialized)
+ * 1 : Init done (IP not initialized. HAL SMARTCARD Init function already called)
+ * b4-b3 (not used)
+ * xx : Should be set to 00
+ * b2 Intrinsic process state
+ * 0 : Ready
+ * 1 : Busy (IP busy with some configuration or internal operations)
+ * b1 (not used)
+ * x : Should be set to 0
+ * b0 Tx state
+ * 0 : Ready (no Tx operation ongoing)
+ * 1 : Busy (Tx operation ongoing)
+ * - RxState contains information related to Rx operations.
+ * RxState value coding follow below described bitmap :
+ * b7-b6 (not used)
+ * xx : Should be set to 00
+ * b5 IP initilisation status
+ * 0 : Reset (IP not initialized)
+ * 1 : Init done (IP not initialized)
+ * b4-b2 (not used)
+ * xxx : Should be set to 000
+ * b1 Rx state
+ * 0 : Ready (no Rx operation ongoing)
+ * 1 : Busy (Rx operation ongoing)
+ * b0 (not used)
+ * x : Should be set to 0.
+ */
+typedef enum
+{
+ HAL_SMARTCARD_STATE_RESET = 0x00U, /*!< Peripheral is not initialized
+ Value is allowed for gState and RxState */
+ HAL_SMARTCARD_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
+ Value is allowed for gState and RxState */
+ HAL_SMARTCARD_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
+ Value is allowed for gState only */
+ HAL_SMARTCARD_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
+ Value is allowed for gState only */
+ HAL_SMARTCARD_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
+ Value is allowed for RxState only */
+ HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
+ Not to be used for neither gState nor RxState.
+ Value is result of combination (Or) between gState and RxState values */
+ HAL_SMARTCARD_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
+ Value is allowed for gState only */
+ HAL_SMARTCARD_STATE_ERROR = 0xE0U /*!< Error
+ Value is allowed for gState only */
+}HAL_SMARTCARD_StateTypeDef;
+
+/**
+ * @brief SMARTCARD handle Structure definition
+ */
+typedef struct
+{
+ USART_TypeDef *Instance; /*!< USART registers base address */
+
+ SMARTCARD_InitTypeDef Init; /*!< SmartCard communication parameters */
+
+ SMARTCARD_AdvFeatureInitTypeDef AdvancedInit; /*!< SmartCard advanced features initialization parameters */
+
+ uint8_t *pTxBuffPtr; /*!< Pointer to SmartCard Tx transfer Buffer */
+
+ uint16_t TxXferSize; /*!< SmartCard Tx Transfer size */
+
+ __IO uint16_t TxXferCount; /*!< SmartCard Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /*!< Pointer to SmartCard Rx transfer Buffer */
+
+ uint16_t RxXferSize; /*!< SmartCard Rx Transfer size */
+
+ __IO uint16_t RxXferCount; /*!< SmartCard Rx Transfer Counter */
+
+ DMA_HandleTypeDef *hdmatx; /*!< SmartCard Tx DMA Handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< SmartCard Rx DMA Handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< Locking object */
+
+ __IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global Handle management
+ and also related to Tx operations.
+ This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
+
+ __IO HAL_SMARTCARD_StateTypeDef RxState; /*!< SmartCard state information related to Rx operations.
+ This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
+
+ __IO uint32_t ErrorCode; /*!< SmartCard Error code
+ This parameter can be a value of @ref SMARTCARD_Error */
+
+}SMARTCARD_HandleTypeDef;
+
+/**
+ * @brief SMARTCARD clock sources
+ */
+typedef enum
+{
+ SMARTCARD_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
+ SMARTCARD_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */
+ SMARTCARD_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
+ SMARTCARD_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
+ SMARTCARD_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */
+ SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10U /*!< undefined clock source */
+}SMARTCARD_ClockSourceTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SMARTCARD_Exported_Constants SMARTCARD Exported Constants
+ * @{
+ */
+
+/** @defgroup SMARTCARD_Error SMARTCARD Error
+ * @{
+ */
+#define HAL_SMARTCARD_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_SMARTCARD_ERROR_PE (0x00000001U) /*!< Parity error */
+#define HAL_SMARTCARD_ERROR_NE (0x00000002U) /*!< Noise error */
+#define HAL_SMARTCARD_ERROR_FE (0x00000004U) /*!< frame error */
+#define HAL_SMARTCARD_ERROR_ORE (0x00000008U) /*!< Overrun error */
+#define HAL_SMARTCARD_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
+#define HAL_SMARTCARD_ERROR_RTO (0x00000020U) /*!< Receiver TimeOut error */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
+ * @{
+ */
+#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< SMARTCARD frame length */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits
+ * @{
+ */
+#define SMARTCARD_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0) /*!< SMARTCARD frame with 0.5 stop bit */
+#define SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) /*!< SMARTCARD frame with 1.5 stop bits */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Parity SMARTCARD Parity
+ * @{
+ */
+#define SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /*!< SMARTCARD frame even parity */
+#define SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< SMARTCARD frame odd parity */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Mode SMARTCARD Transfer Mode
+ * @{
+ */
+#define SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE) /*!< SMARTCARD RX mode */
+#define SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE) /*!< SMARTCARD TX mode */
+#define SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) /*!< SMARTCARD RX and TX mode */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity
+ * @{
+ */
+#define SMARTCARD_POLARITY_LOW (0x00000000U) /*!< SMARTCARD frame low polarity */
+#define SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL) /*!< SMARTCARD frame high polarity */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase
+ * @{
+ */
+#define SMARTCARD_PHASE_1EDGE (0x00000000U) /*!< SMARTCARD frame phase on first clock transition */
+#define SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA) /*!< SMARTCARD frame phase on second clock transition */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit
+ * @{
+ */
+#define SMARTCARD_LASTBIT_DISABLE (0x00000000U) /*!< SMARTCARD frame last data bit clock pulse not output to SCLK pin */
+#define SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL) /*!< SMARTCARD frame last data bit clock pulse output to SCLK pin */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_OneBit_Sampling SMARTCARD One Bit Sampling Method
+ * @{
+ */
+#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE (0x00000000U) /*!< SMARTCARD frame one-bit sample disabled */
+#define SMARTCARD_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) /*!< SMARTCARD frame one-bit sample enabled */
+/**
+ * @}
+ */
+
+
+/** @defgroup SMARTCARD_NACK_Enable SMARTCARD NACK Enable
+ * @{
+ */
+#define SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK) /*!< SMARTCARD NACK transmission disabled */
+#define SMARTCARD_NACK_DISABLE (0x00000000U) /*!< SMARTCARD NACK transmission enabled */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Timeout_Enable SMARTCARD Timeout Enable
+ * @{
+ */
+#define SMARTCARD_TIMEOUT_DISABLE (0x00000000U) /*!< SMARTCARD receiver timeout disabled */
+#define SMARTCARD_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN) /*!< SMARTCARD receiver timeout enabled */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Advanced_Features_Initialization_Type SMARTCARD advanced feature initialization type
+ * @{
+ */
+#define SMARTCARD_ADVFEATURE_NO_INIT (0x00000000U) /*!< No advanced feature initialization */
+#define SMARTCARD_ADVFEATURE_TXINVERT_INIT (0x00000001U) /*!< TX pin active level inversion */
+#define SMARTCARD_ADVFEATURE_RXINVERT_INIT (0x00000002U) /*!< RX pin active level inversion */
+#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT (0x00000004U) /*!< Binary data inversion */
+#define SMARTCARD_ADVFEATURE_SWAP_INIT (0x00000008U) /*!< TX/RX pins swap */
+#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT (0x00000010U) /*!< RX overrun disable */
+#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT (0x00000020U) /*!< DMA disable on Reception Error */
+#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT (0x00000080U) /*!< Most significant bit sent/received first */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Tx_Inv SMARTCARD advanced feature TX pin active level inversion
+ * @{
+ */
+#define SMARTCARD_ADVFEATURE_TXINV_DISABLE (0x00000000U) /*!< TX pin active level inversion disable */
+#define SMARTCARD_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV) /*!< TX pin active level inversion enable */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Rx_Inv SMARTCARD advanced feature RX pin active level inversion
+ * @{
+ */
+#define SMARTCARD_ADVFEATURE_RXINV_DISABLE (0x00000000U) /*!< RX pin active level inversion disable */
+#define SMARTCARD_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV) /*!< RX pin active level inversion enable */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Data_Inv SMARTCARD advanced feature Binary Data inversion
+ * @{
+ */
+#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE (0x00000000U) /*!< Binary data inversion disable */
+#define SMARTCARD_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV) /*!< Binary data inversion enable */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Rx_Tx_Swap SMARTCARD advanced feature RX TX pins swap
+ * @{
+ */
+#define SMARTCARD_ADVFEATURE_SWAP_DISABLE (0x00000000U) /*!< TX/RX pins swap disable */
+#define SMARTCARD_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP) /*!< TX/RX pins swap enable */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Overrun_Disable SMARTCARD advanced feature Overrun Disable
+ * @{
+ */
+#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE (0x00000000U) /*!< RX overrun enable */
+#define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS) /*!< RX overrun disable */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_DMA_Disable_on_Rx_Error SMARTCARD advanced feature DMA Disable on Rx Error
+ * @{
+ */
+#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR (0x00000000U) /*!< DMA enable on Reception Error */
+#define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE) /*!< DMA disable on Reception Error */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_MSB_First SMARTCARD advanced feature MSB first
+ * @{
+ */
+#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE (0x00000000U) /*!< Most significant bit sent/received first disable */
+#define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST) /*!< Most significant bit sent/received first enable */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Flags SMARTCARD Flags
+ * Elements values convention: 0xXXXX
+ * - 0xXXXX : Flag mask in the ISR register
+ * @{
+ */
+#define SMARTCARD_FLAG_REACK USART_ISR_REACK /*!< SMARTCARD receive enable acknowledge flag */
+#define SMARTCARD_FLAG_TEACK USART_ISR_TEACK /*!< SMARTCARD transmit enable acknowledge flag */
+#define SMARTCARD_FLAG_BUSY USART_ISR_BUSY /*!< SMARTCARD busy flag */
+#define SMARTCARD_FLAG_EOBF USART_ISR_EOBF /*!< SMARTCARD end of block flag */
+#define SMARTCARD_FLAG_RTOF USART_ISR_RTOF /*!< SMARTCARD receiver timeout flag */
+#define SMARTCARD_FLAG_TXE USART_ISR_TXE /*!< SMARTCARD transmit data register empty */
+#define SMARTCARD_FLAG_TC USART_ISR_TC /*!< SMARTCARD transmission complete */
+#define SMARTCARD_FLAG_RXNE USART_ISR_RXNE /*!< SMARTCARD read data register not empty */
+#define SMARTCARD_FLAG_IDLE USART_ISR_IDLE /*!< SMARTCARD idle line detection */
+#define SMARTCARD_FLAG_ORE USART_ISR_ORE /*!< SMARTCARD overrun error */
+#define SMARTCARD_FLAG_NE USART_ISR_NE /*!< SMARTCARD noise error */
+#define SMARTCARD_FLAG_FE USART_ISR_FE /*!< SMARTCARD frame error */
+#define SMARTCARD_FLAG_PE USART_ISR_PE /*!< SMARTCARD parity error */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Interrupt_definition SMARTCARD Interrupts Definition
+ * Elements values convention: 0000ZZZZ0XXYYYYYb
+ * - YYYYY : Interrupt source position in the XX register (5bits)
+ * - XX : Interrupt source register (2bits)
+ * - 01: CR1 register
+ * - 10: CR2 register
+ * - 11: CR3 register
+ * - ZZZZ : Flag position in the ISR register(4bits)
+ * @{
+ */
+
+#define SMARTCARD_IT_PE ((uint16_t)0x0028U) /*!< SMARTCARD parity error interruption */
+#define SMARTCARD_IT_TXE ((uint16_t)0x0727U) /*!< SMARTCARD transmit data register empty interruption */
+#define SMARTCARD_IT_TC ((uint16_t)0x0626U) /*!< SMARTCARD transmission complete interruption */
+#define SMARTCARD_IT_RXNE ((uint16_t)0x0525U) /*!< SMARTCARD read data register not empty interruption */
+#define SMARTCARD_IT_IDLE ((uint16_t)0x0424U) /*!< SMARTCARD idle line detection interruption */
+
+#define SMARTCARD_IT_ERR ((uint16_t)0x0060U) /*!< SMARTCARD error interruption */
+#define SMARTCARD_IT_ORE ((uint16_t)0x0300U) /*!< SMARTCARD overrun error interruption */
+#define SMARTCARD_IT_NE ((uint16_t)0x0200U) /*!< SMARTCARD noise error interruption */
+#define SMARTCARD_IT_FE ((uint16_t)0x0100U) /*!< SMARTCARD frame error interruption */
+
+#define SMARTCARD_IT_EOB ((uint16_t)0x0C3BU) /*!< SMARTCARD end of block interruption */
+#define SMARTCARD_IT_RTO ((uint16_t)0x0B3AU) /*!< SMARTCARD receiver timeout interruption */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_IT_CLEAR_Flags SMARTCARD Interruption Clear Flags
+ * @{
+ */
+#define SMARTCARD_CLEAR_PEF USART_ICR_PECF /*!< SMARTCARD parity error clear flag */
+#define SMARTCARD_CLEAR_FEF USART_ICR_FECF /*!< SMARTCARD framing error clear flag */
+#define SMARTCARD_CLEAR_NEF USART_ICR_NCF /*!< SMARTCARD noise detected clear flag */
+#define SMARTCARD_CLEAR_OREF USART_ICR_ORECF /*!< SMARTCARD overrun error clear flag */
+#define SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF /*!< SMARTCARD idle line detected clear flag */
+#define SMARTCARD_CLEAR_TCF USART_ICR_TCCF /*!< SMARTCARD transmission complete clear flag */
+#define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF /*!< SMARTCARD receiver time out clear flag */
+#define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF /*!< SMARTCARD end of block clear flag */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_CR3_SCARCNT_LSB_POS SMARTCARD auto retry counter LSB position in CR3 register
+ * @{
+ */
+#define SMARTCARD_CR3_SCARCNT_LSB_POS ( 17U) /*!< SMARTCARD auto retry counter LSB position in CR3 register */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_GTPR_GT_LSB_POS SMARTCARD guard time value LSB position in GTPR register
+ * @{
+ */
+#define SMARTCARD_GTPR_GT_LSB_POS ( 8U) /*!< SMARTCARD guard time value LSB position in GTPR register */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_RTOR_BLEN_LSB_POS SMARTCARD block length LSB position in RTOR register
+ * @{
+ */
+#define SMARTCARD_RTOR_BLEN_LSB_POS ( 24U) /*!< SMARTCARD block length LSB position in RTOR register */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Interruption_Mask SMARTCARD interruptions flags mask
+ * @{
+ */
+#define SMARTCARD_IT_MASK ((uint16_t)0x001FU) /*!< SMARTCARD interruptions flags mask */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Request_Parameters SMARTCARD Request Parameters
+ * @{
+ */
+#define SMARTCARD_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive data flush request */
+#define SMARTCARD_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush request */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup SMARTCARD_Exported_Macros SMARTCARD Exported Macros
+ * @{
+ */
+
+/** @brief Reset SMARTCARD handle states.
+ * @param __HANDLE__ SMARTCARD handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \
+ (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \
+ } while(0U)
+
+/** @brief Flush the Smartcard Data registers.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) \
+ do{ \
+ SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \
+ SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \
+ } while(0U)
+
+/** @brief Clear the specified SMARTCARD pending flag.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg @ref SMARTCARD_CLEAR_PEF Parity error clear flag
+ * @arg @ref SMARTCARD_CLEAR_FEF Framing error clear flag
+ * @arg @ref SMARTCARD_CLEAR_NEF Noise detected clear flag
+ * @arg @ref SMARTCARD_CLEAR_OREF OverRun error clear flag
+ * @arg @ref SMARTCARD_CLEAR_IDLEF Idle line detected clear flag
+ * @arg @ref SMARTCARD_CLEAR_TCF Transmission complete clear flag
+ * @arg @ref SMARTCARD_CLEAR_RTOF Receiver timeout clear flag
+ * @arg @ref SMARTCARD_CLEAR_EOBF End of block clear flag
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/** @brief Clear the SMARTCARD PE pending flag.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF)
+
+
+/** @brief Clear the SMARTCARD FE pending flag.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF)
+
+/** @brief Clear the SMARTCARD NE pending flag.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF)
+
+/** @brief Clear the SMARTCARD ORE pending flag.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF)
+
+/** @brief Clear the SMARTCARD IDLE pending flag.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF)
+
+/** @brief Check whether the specified Smartcard flag is set or not.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg @ref SMARTCARD_FLAG_REACK Receive enable acknowledge flag
+ * @arg @ref SMARTCARD_FLAG_TEACK Transmit enable acknowledge flag
+ * @arg @ref SMARTCARD_FLAG_BUSY Busy flag
+ * @arg @ref SMARTCARD_FLAG_EOBF End of block flag
+ * @arg @ref SMARTCARD_FLAG_RTOF Receiver timeout flag
+ * @arg @ref SMARTCARD_FLAG_TXE Transmit data register empty flag
+ * @arg @ref SMARTCARD_FLAG_TC Transmission complete flag
+ * @arg @ref SMARTCARD_FLAG_RXNE Receive data register not empty flag
+ * @arg @ref SMARTCARD_FLAG_IDLE Idle line detection flag
+ * @arg @ref SMARTCARD_FLAG_ORE Overrun error flag
+ * @arg @ref SMARTCARD_FLAG_NE Noise error flag
+ * @arg @ref SMARTCARD_FLAG_FE Framing error flag
+ * @arg @ref SMARTCARD_FLAG_PE Parity error flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
+
+
+/** @brief Enable the specified SmartCard interrupt.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @param __INTERRUPT__ specifies the SMARTCARD interrupt to enable.
+ * This parameter can be one of the following values:
+ * @arg @ref SMARTCARD_IT_EOB End of block interrupt
+ * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
+ * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
+ * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
+ * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
+ * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
+ * @arg @ref SMARTCARD_IT_PE Parity error interrupt
+ * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
+ * @retval None
+ */
+#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & 0xFFU) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+ ((((__INTERRUPT__) & 0xFFU) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
+
+/** @brief Disable the specified SmartCard interrupt.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @param __INTERRUPT__ specifies the SMARTCARD interrupt to disable.
+ * This parameter can be one of the following values:
+ * @arg @ref SMARTCARD_IT_EOB End of block interrupt
+ * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
+ * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
+ * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
+ * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
+ * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
+ * @arg @ref SMARTCARD_IT_PE Parity error interrupt
+ * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
+ * @retval None
+ */
+#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & 0xFFU) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+ ((((__INTERRUPT__) & 0xFFU) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
+
+
+/** @brief Check whether the specified SmartCard interrupt has occurred or not.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @param __IT__ specifies the SMARTCARD interrupt to check.
+ * This parameter can be one of the following values:
+ * @arg @ref SMARTCARD_IT_EOB End of block interrupt
+ * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
+ * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
+ * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
+ * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
+ * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
+ * @arg @ref SMARTCARD_IT_ORE Overrun error interrupt
+ * @arg @ref SMARTCARD_IT_NE Noise error interrupt
+ * @arg @ref SMARTCARD_IT_FE Framing error interrupt
+ * @arg @ref SMARTCARD_IT_PE Parity error interrupt
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U)))
+
+/** @brief Check whether the specified SmartCard interrupt source is enabled or not.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @param __IT__ specifies the SMARTCARD interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg @ref SMARTCARD_IT_EOB End of block interrupt
+ * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
+ * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
+ * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
+ * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
+ * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
+ * @arg @ref SMARTCARD_IT_ERR Framing, overrun or noise error interrupt
+ * @arg @ref SMARTCARD_IT_PE Parity error interrupt
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((__IT__) & 0xFFU) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1 : \
+ (((((__IT__) & 0xFFU) >> 5U) == 2U)? (__HANDLE__)->Instance->CR2 : \
+ (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__IT__)) & SMARTCARD_IT_MASK)))
+
+
+/** @brief Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
+ * to clear the corresponding interrupt.
+ * This parameter can be one of the following values:
+ * @arg @ref SMARTCARD_CLEAR_PEF Parity error clear flag
+ * @arg @ref SMARTCARD_CLEAR_FEF Framing error clear flag
+ * @arg @ref SMARTCARD_CLEAR_NEF Noise detected clear flag
+ * @arg @ref SMARTCARD_CLEAR_OREF OverRun error clear flag
+ * @arg @ref SMARTCARD_CLEAR_IDLEF Idle line detection clear flag
+ * @arg @ref SMARTCARD_CLEAR_TCF Transmission complete clear flag
+ * @arg @ref SMARTCARD_CLEAR_RTOF Receiver timeout clear flag
+ * @arg @ref SMARTCARD_CLEAR_EOBF End of block clear flag
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
+
+/** @brief Set a specific SMARTCARD request flag.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @param __REQ__ specifies the request flag to set
+ * This parameter can be one of the following values:
+ * @arg @ref SMARTCARD_RXDATA_FLUSH_REQUEST Receive data flush Request
+ * @arg @ref SMARTCARD_TXDATA_FLUSH_REQUEST Transmit data flush Request
+ *
+ * @retval None
+ */
+#define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
+
+/** @brief Enable the SMARTCARD one bit sample method.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+
+/** @brief Disable the SMARTCARD one bit sample method.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
+
+/** @brief Enable the USART associated to the SMARTCARD Handle.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+
+/** @brief Disable the USART associated to the SMARTCARD Handle
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+
+/**
+ * @}
+ */
+
+/* Private macros -------------------------------------------------------------*/
+/** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros
+ * @{
+ */
+
+/** @brief Check the Baud rate range.
+ * @note The maximum Baud Rate is derived from the maximum clock on F3 (72 MHz)
+ * divided by the oversampling used on the SMARTCARD (i.e. 16).
+ * @param __BAUDRATE__ Baud rate set by the configuration function.
+ * @retval Test result (TRUE or FALSE)
+ */
+#define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4500001U)
+
+/** @brief Check the block length range.
+ * @note The maximum SMARTCARD block length is 0xFF.
+ * @param __LENGTH__ block length.
+ * @retval Test result (TRUE or FALSE)
+ */
+#define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFFU)
+
+/** @brief Check the receiver timeout value.
+ * @note The maximum SMARTCARD receiver timeout value is 0xFFFFFF.
+ * @param __TIMEOUTVALUE__ receiver timeout value.
+ * @retval Test result (TRUE or FALSE)
+ */
+#define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
+
+/** @brief Check the SMARTCARD autoretry counter value.
+ * @note The maximum number of retransmissions is 0x7.
+ * @param __COUNT__ number of retransmissions.
+ * @retval Test result (TRUE or FALSE)
+ */
+#define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7U)
+
+/**
+ * @brief Ensure that SMARTCARD frame length is valid.
+ * @param __LENGTH__ SMARTCARD frame length.
+ * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+ */
+#define IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)
+
+/**
+ * @brief Ensure that SMARTCARD frame number of stop bits is valid.
+ * @param __STOPBITS__ SMARTCARD frame number of stop bits.
+ * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
+ */
+#define IS_SMARTCARD_STOPBITS(__STOPBITS__) (((__STOPBITS__) == SMARTCARD_STOPBITS_0_5) ||\
+ ((__STOPBITS__) == SMARTCARD_STOPBITS_1_5))
+
+/**
+ * @brief Ensure that SMARTCARD frame parity is valid.
+ * @param __PARITY__ SMARTCARD frame parity.
+ * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
+ */
+#define IS_SMARTCARD_PARITY(__PARITY__) (((__PARITY__) == SMARTCARD_PARITY_EVEN) || \
+ ((__PARITY__) == SMARTCARD_PARITY_ODD))
+
+/**
+ * @brief Ensure that SMARTCARD communication mode is valid.
+ * @param __MODE__ SMARTCARD communication mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & (uint16_t)0xFFF3U) == 0x00U) && ((__MODE__) != (uint16_t)0x00U))
+
+/**
+ * @brief Ensure that SMARTCARD frame polarity is valid.
+ * @param __CPOL__ SMARTCARD frame polarity.
+ * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
+ */
+#define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))
+
+/**
+ * @brief Ensure that SMARTCARD frame phase is valid.
+ * @param __CPHA__ SMARTCARD frame phase.
+ * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
+ */
+#define IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))
+
+/**
+ * @brief Ensure that SMARTCARD frame last bit clock pulse setting is valid.
+ * @param __LASTBIT__ SMARTCARD frame last bit clock pulse setting.
+ * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
+ */
+#define IS_SMARTCARD_LASTBIT(__LASTBIT__) (((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \
+ ((__LASTBIT__) == SMARTCARD_LASTBIT_ENABLE))
+
+/**
+ * @brief Ensure that SMARTCARD frame sampling is valid.
+ * @param __ONEBIT__ SMARTCARD frame sampling.
+ * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
+ */
+#define IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \
+ ((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_ENABLE))
+
+/**
+ * @brief Ensure that SMARTCARD NACK transmission setting is valid.
+ * @param __NACK__ SMARTCARD NACK transmission setting.
+ * @retval SET (__NACK__ is valid) or RESET (__NACK__ is invalid)
+ */
+#define IS_SMARTCARD_NACK(__NACK__) (((__NACK__) == SMARTCARD_NACK_ENABLE) || \
+ ((__NACK__) == SMARTCARD_NACK_DISABLE))
+
+/**
+ * @brief Ensure that SMARTCARD receiver timeout setting is valid.
+ * @param __TIMEOUT__ SMARTCARD receiver timeout setting.
+ * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
+ */
+#define IS_SMARTCARD_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \
+ ((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE))
+
+/**
+ * @brief Ensure that SMARTCARD advanced features initialization is valid.
+ * @param __INIT__ SMARTCARD advanced features initialization.
+ * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
+ */
+#define IS_SMARTCARD_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (SMARTCARD_ADVFEATURE_NO_INIT | \
+ SMARTCARD_ADVFEATURE_TXINVERT_INIT | \
+ SMARTCARD_ADVFEATURE_RXINVERT_INIT | \
+ SMARTCARD_ADVFEATURE_DATAINVERT_INIT | \
+ SMARTCARD_ADVFEATURE_SWAP_INIT | \
+ SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT | \
+ SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT | \
+ SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
+
+/**
+ * @brief Ensure that SMARTCARD frame TX inversion setting is valid.
+ * @param __TXINV__ SMARTCARD frame TX inversion setting.
+ * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
+ */
+#define IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \
+ ((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_ENABLE))
+
+/**
+ * @brief Ensure that SMARTCARD frame RX inversion setting is valid.
+ * @param __RXINV__ SMARTCARD frame RX inversion setting.
+ * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
+ */
+#define IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \
+ ((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_ENABLE))
+
+/**
+ * @brief Ensure that SMARTCARD frame data inversion setting is valid.
+ * @param __DATAINV__ SMARTCARD frame data inversion setting.
+ * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
+ */
+#define IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \
+ ((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE))
+
+/**
+ * @brief Ensure that SMARTCARD frame RX/TX pins swap setting is valid.
+ * @param __SWAP__ SMARTCARD frame RX/TX pins swap setting.
+ * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
+ */
+#define IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \
+ ((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_ENABLE))
+
+/**
+ * @brief Ensure that SMARTCARD frame overrun setting is valid.
+ * @param __OVERRUN__ SMARTCARD frame overrun setting.
+ * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
+ */
+#define IS_SMARTCARD_OVERRUN(__OVERRUN__) (((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \
+ ((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE))
+
+/**
+ * @brief Ensure that SMARTCARD DMA enabling or disabling on error setting is valid.
+ * @param __DMA__ SMARTCARD DMA enabling or disabling on error setting.
+ * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
+ */
+#define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \
+ ((__DMA__) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR))
+
+/**
+ * @brief Ensure that SMARTCARD frame MSB first setting is valid.
+ * @param __MSBFIRST__ SMARTCARD frame MSB first setting.
+ * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
+ */
+#define IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \
+ ((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE))
+
+/**
+ * @brief Ensure that SMARTCARD request parameter is valid.
+ * @param __PARAM__ SMARTCARD request parameter.
+ * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
+ */
+#define IS_SMARTCARD_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \
+ ((__PARAM__) == SMARTCARD_TXDATA_FLUSH_REQUEST))
+
+/**
+ * @}
+ */
+
+/* Include SMARTCARD HAL Extended module */
+#include "stm32f3xx_hal_smartcard_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SMARTCARD_Exported_Functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+
+/** @addtogroup SMARTCARD_Exported_Functions_Group1
+ * @{
+ */
+
+HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard);
+
+/**
+ * @}
+ */
+
+/* IO operation functions *****************************************************/
+/** @addtogroup SMARTCARD_Exported_Functions_Group2
+ * @{
+ */
+
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+
+void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard);
+
+/**
+ * @}
+ */
+
+/* Peripheral State and Error functions ***************************************/
+/** @addtogroup SMARTCARD_Exported_Functions_Group3
+ * @{
+ */
+
+HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard);
+uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_SMARTCARD_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_hal_smartcard_ex.h b/Inc/stm32f3xx_hal_smartcard_ex.h
new file mode 100644
index 0000000..3402769
--- /dev/null
+++ b/Inc/stm32f3xx_hal_smartcard_ex.h
@@ -0,0 +1,223 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_smartcard_ex.h
+ * @author MCD Application Team
+ * @brief Header file of SMARTCARD HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_SMARTCARD_EX_H
+#define __STM32F3xx_HAL_SMARTCARD_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SMARTCARDEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SMARTCARDEx_Private_Macros SMARTCARD Extended Private Macros
+ * @{
+ */
+
+/** @brief Report the SMARTCARD clock source.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @param __CLOCKSOURCE__ output variable.
+ * @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__.
+ */
+#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0U)
+#else
+#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK2: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
+ case RCC_USART2CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART2CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART2CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART2CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \
+ { \
+ case RCC_USART3CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART3CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART3CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART3CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0U)
+#endif
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SMARTCARDEx_Exported_Functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+/* IO operation methods *******************************************************/
+
+/** @addtogroup SMARTCARDEx_Exported_Functions_Group1
+ * @{
+ */
+
+/* Peripheral Control functions ***********************************************/
+void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength);
+void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue);
+HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_SMARTCARD_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_hal_smbus.h b/Inc/stm32f3xx_hal_smbus.h
new file mode 100644
index 0000000..4221ec2
--- /dev/null
+++ b/Inc/stm32f3xx_hal_smbus.h
@@ -0,0 +1,699 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_smbus.h
+ * @author MCD Application Team
+ * @brief Header file of SMBUS HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_SMBUS_H
+#define __STM32F3xx_HAL_SMBUS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SMBUS
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SMBUS_Exported_Types SMBUS Exported Types
+ * @{
+ */
+
+/** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition
+ * @brief SMBUS Configuration Structure definition
+ * @{
+ */
+typedef struct
+{
+ uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value.
+ This parameter calculated by referring to SMBUS initialization
+ section in Reference manual */
+ uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not.
+ This parameter can be a value of @ref SMBUS_Analog_Filter */
+
+ uint32_t OwnAddress1; /*!< Specifies the first device own address.
+ This parameter can be a 7-bit or 10-bit address. */
+
+ uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected.
+ This parameter can be a value of @ref SMBUS_addressing_mode */
+
+ uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
+ This parameter can be a value of @ref SMBUS_dual_addressing_mode */
+
+ uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
+ This parameter can be a 7-bit address. */
+
+ uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected
+ This parameter can be a value of @ref SMBUS_own_address2_masks. */
+
+ uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
+ This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */
+
+ uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
+ This parameter can be a value of @ref SMBUS_nostretch_mode */
+
+ uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected.
+ This parameter can be a value of @ref SMBUS_packet_error_check_mode */
+
+ uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected.
+ This parameter can be a value of @ref SMBUS_peripheral_mode */
+
+ uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value.
+ (Enable bits and different timeout values)
+ This parameter calculated by referring to SMBUS initialization
+ section in Reference manual */
+} SMBUS_InitTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HAL_state_definition HAL state definition
+ * @brief HAL State definition
+ * @{
+ */
+#define HAL_SMBUS_STATE_RESET (0x00000000U) /*!< SMBUS not yet initialized or disabled */
+#define HAL_SMBUS_STATE_READY (0x00000001U) /*!< SMBUS initialized and ready for use */
+#define HAL_SMBUS_STATE_BUSY (0x00000002U) /*!< SMBUS internal process is ongoing */
+#define HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */
+#define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */
+#define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */
+#define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */
+#define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */
+#define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */
+#define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition
+ * @brief SMBUS Error Code definition
+ * @{
+ */
+#define HAL_SMBUS_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_SMBUS_ERROR_BERR (0x00000001U) /*!< BERR error */
+#define HAL_SMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */
+#define HAL_SMBUS_ERROR_ACKF (0x00000004U) /*!< ACKF error */
+#define HAL_SMBUS_ERROR_OVR (0x00000008U) /*!< OVR error */
+#define HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U) /*!< Timeout error */
+#define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */
+#define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */
+#define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition
+ * @brief SMBUS handle Structure definition
+ * @{
+ */
+typedef struct
+{
+ I2C_TypeDef *Instance; /*!< SMBUS registers base address */
+
+ SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */
+
+ uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */
+
+ uint16_t XferSize; /*!< SMBUS transfer size */
+
+ __IO uint16_t XferCount; /*!< SMBUS transfer counter */
+
+ __IO uint32_t XferOptions; /*!< SMBUS transfer options */
+
+ __IO uint32_t PreviousState; /*!< SMBUS communication Previous state */
+
+ HAL_LockTypeDef Lock; /*!< SMBUS locking object */
+
+ __IO uint32_t State; /*!< SMBUS communication state */
+
+ __IO uint32_t ErrorCode; /*!< SMBUS Error code */
+
+} SMBUS_HandleTypeDef;
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants
+ * @{
+ */
+
+/** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter
+ * @{
+ */
+#define SMBUS_ANALOGFILTER_ENABLE (0x00000000U)
+#define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_addressing_mode SMBUS addressing mode
+ * @{
+ */
+#define SMBUS_ADDRESSINGMODE_7BIT (0x00000001U)
+#define SMBUS_ADDRESSINGMODE_10BIT (0x00000002U)
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode
+ * @{
+ */
+
+#define SMBUS_DUALADDRESS_DISABLE (0x00000000U)
+#define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_own_address2_masks SMBUS ownaddress2 masks
+ * @{
+ */
+
+#define SMBUS_OA2_NOMASK ((uint8_t)0x00U)
+#define SMBUS_OA2_MASK01 ((uint8_t)0x01U)
+#define SMBUS_OA2_MASK02 ((uint8_t)0x02U)
+#define SMBUS_OA2_MASK03 ((uint8_t)0x03U)
+#define SMBUS_OA2_MASK04 ((uint8_t)0x04U)
+#define SMBUS_OA2_MASK05 ((uint8_t)0x05U)
+#define SMBUS_OA2_MASK06 ((uint8_t)0x06U)
+#define SMBUS_OA2_MASK07 ((uint8_t)0x07U)
+/**
+ * @}
+ */
+
+
+/** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode
+ * @{
+ */
+#define SMBUS_GENERALCALL_DISABLE (0x00000000U)
+#define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode
+ * @{
+ */
+#define SMBUS_NOSTRETCH_DISABLE (0x00000000U)
+#define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode
+ * @{
+ */
+#define SMBUS_PEC_DISABLE (0x00000000U)
+#define SMBUS_PEC_ENABLE I2C_CR1_PECEN
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode
+ * @{
+ */
+#define SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN
+#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U)
+#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition
+ * @{
+ */
+
+#define SMBUS_SOFTEND_MODE (0x00000000U)
+#define SMBUS_RELOAD_MODE I2C_CR2_RELOAD
+#define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND
+#define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition
+ * @{
+ */
+
+#define SMBUS_NO_STARTSTOP (0x00000000U)
+#define SMBUS_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
+#define SMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
+#define SMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition
+ * @{
+ */
+
+/* List of XferOptions in usage of :
+ * 1- Restart condition when direction change
+ * 2- No Restart condition in other use cases
+ */
+#define SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE
+#define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
+#define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
+#define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
+#define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
+#define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
+
+/* List of XferOptions in usage of :
+ * 1- Restart condition in all use cases (direction change or not)
+ */
+#define SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU)
+#define SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U)
+#define SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U)
+#define SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U)
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition
+ * @brief SMBUS Interrupt definition
+ * Elements values convention: 0xXXXXXXXX
+ * - XXXXXXXX : Interrupt control mask
+ * @{
+ */
+#define SMBUS_IT_ERRI I2C_CR1_ERRIE
+#define SMBUS_IT_TCI I2C_CR1_TCIE
+#define SMBUS_IT_STOPI I2C_CR1_STOPIE
+#define SMBUS_IT_NACKI I2C_CR1_NACKIE
+#define SMBUS_IT_ADDRI I2C_CR1_ADDRIE
+#define SMBUS_IT_RXI I2C_CR1_RXIE
+#define SMBUS_IT_TXI I2C_CR1_TXIE
+#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)
+#define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)
+#define SMBUS_IT_ALERT (SMBUS_IT_ERRI)
+#define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_Flag_definition SMBUS Flag definition
+ * @brief Flag definition
+ * Elements values convention: 0xXXXXYYYY
+ * - XXXXXXXX : Flag mask
+ * @{
+ */
+
+#define SMBUS_FLAG_TXE I2C_ISR_TXE
+#define SMBUS_FLAG_TXIS I2C_ISR_TXIS
+#define SMBUS_FLAG_RXNE I2C_ISR_RXNE
+#define SMBUS_FLAG_ADDR I2C_ISR_ADDR
+#define SMBUS_FLAG_AF I2C_ISR_NACKF
+#define SMBUS_FLAG_STOPF I2C_ISR_STOPF
+#define SMBUS_FLAG_TC I2C_ISR_TC
+#define SMBUS_FLAG_TCR I2C_ISR_TCR
+#define SMBUS_FLAG_BERR I2C_ISR_BERR
+#define SMBUS_FLAG_ARLO I2C_ISR_ARLO
+#define SMBUS_FLAG_OVR I2C_ISR_OVR
+#define SMBUS_FLAG_PECERR I2C_ISR_PECERR
+#define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT
+#define SMBUS_FLAG_ALERT I2C_ISR_ALERT
+#define SMBUS_FLAG_BUSY I2C_ISR_BUSY
+#define SMBUS_FLAG_DIR I2C_ISR_DIR
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros ------------------------------------------------------------*/
+/** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros
+ * @{
+ */
+
+/** @brief Reset SMBUS handle state.
+ * @param __HANDLE__ specifies the SMBUS Handle.
+ * @retval None
+ */
+#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
+
+/** @brief Enable the specified SMBUS interrupts.
+ * @param __HANDLE__ specifies the SMBUS Handle.
+ * @param __INTERRUPT__ specifies the interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg @ref SMBUS_IT_ERRI Errors interrupt enable
+ * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable
+ * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
+ * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
+ * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
+ * @arg @ref SMBUS_IT_RXI RX interrupt enable
+ * @arg @ref SMBUS_IT_TXI TX interrupt enable
+ *
+ * @retval None
+ */
+#define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
+
+/** @brief Disable the specified SMBUS interrupts.
+ * @param __HANDLE__ specifies the SMBUS Handle.
+ * @param __INTERRUPT__ specifies the interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg @ref SMBUS_IT_ERRI Errors interrupt enable
+ * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable
+ * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
+ * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
+ * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
+ * @arg @ref SMBUS_IT_RXI RX interrupt enable
+ * @arg @ref SMBUS_IT_TXI TX interrupt enable
+ *
+ * @retval None
+ */
+#define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
+
+/** @brief Check whether the specified SMBUS interrupt source is enabled or not.
+ * @param __HANDLE__ specifies the SMBUS Handle.
+ * @param __INTERRUPT__ specifies the SMBUS interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg @ref SMBUS_IT_ERRI Errors interrupt enable
+ * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable
+ * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
+ * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
+ * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
+ * @arg @ref SMBUS_IT_RXI RX interrupt enable
+ * @arg @ref SMBUS_IT_TXI TX interrupt enable
+ *
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Check whether the specified SMBUS flag is set or not.
+ * @param __HANDLE__ specifies the SMBUS Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg @ref SMBUS_FLAG_TXE Transmit data register empty
+ * @arg @ref SMBUS_FLAG_TXIS Transmit interrupt status
+ * @arg @ref SMBUS_FLAG_RXNE Receive data register not empty
+ * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode)
+ * @arg @ref SMBUS_FLAG_AF NACK received flag
+ * @arg @ref SMBUS_FLAG_STOPF STOP detection flag
+ * @arg @ref SMBUS_FLAG_TC Transfer complete (master mode)
+ * @arg @ref SMBUS_FLAG_TCR Transfer complete reload
+ * @arg @ref SMBUS_FLAG_BERR Bus error
+ * @arg @ref SMBUS_FLAG_ARLO Arbitration lost
+ * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun
+ * @arg @ref SMBUS_FLAG_PECERR PEC error in reception
+ * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
+ * @arg @ref SMBUS_FLAG_ALERT SMBus alert
+ * @arg @ref SMBUS_FLAG_BUSY Bus busy
+ * @arg @ref SMBUS_FLAG_DIR Transfer direction (slave mode)
+ *
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define SMBUS_FLAG_MASK (0x0001FFFFU)
+#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
+
+/** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
+ * @param __HANDLE__ specifies the SMBUS Handle.
+ * @param __FLAG__ specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode)
+ * @arg @ref SMBUS_FLAG_AF NACK received flag
+ * @arg @ref SMBUS_FLAG_STOPF STOP detection flag
+ * @arg @ref SMBUS_FLAG_BERR Bus error
+ * @arg @ref SMBUS_FLAG_ARLO Arbitration lost
+ * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun
+ * @arg @ref SMBUS_FLAG_PECERR PEC error in reception
+ * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
+ * @arg @ref SMBUS_FLAG_ALERT SMBus alert
+ *
+ * @retval None
+ */
+#define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/** @brief Enable the specified SMBUS peripheral.
+ * @param __HANDLE__ specifies the SMBUS Handle.
+ * @retval None
+ */
+#define __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
+
+/** @brief Disable the specified SMBUS peripheral.
+ * @param __HANDLE__ specifies the SMBUS Handle.
+ * @retval None
+ */
+#define __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
+
+/** @brief Generate a Non-Acknowledge SMBUS peripheral in Slave mode.
+ * @param __HANDLE__ specifies the SMBUS Handle.
+ * @retval None
+ */
+#define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
+
+/**
+ * @}
+ */
+
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SMBUS_Private_Macro SMBUS Private Macros
+ * @{
+ */
+
+#define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
+ ((FILTER) == SMBUS_ANALOGFILTER_DISABLE))
+
+#define IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
+
+#define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \
+ ((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
+
+#define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \
+ ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))
+
+#define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \
+ ((MASK) == SMBUS_OA2_MASK01) || \
+ ((MASK) == SMBUS_OA2_MASK02) || \
+ ((MASK) == SMBUS_OA2_MASK03) || \
+ ((MASK) == SMBUS_OA2_MASK04) || \
+ ((MASK) == SMBUS_OA2_MASK05) || \
+ ((MASK) == SMBUS_OA2_MASK06) || \
+ ((MASK) == SMBUS_OA2_MASK07))
+
+#define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLE) || \
+ ((CALL) == SMBUS_GENERALCALL_ENABLE))
+
+#define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \
+ ((STRETCH) == SMBUS_NOSTRETCH_ENABLE))
+
+#define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \
+ ((PEC) == SMBUS_PEC_ENABLE))
+
+#define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \
+ ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \
+ ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
+
+#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \
+ ((MODE) == SMBUS_AUTOEND_MODE) || \
+ ((MODE) == SMBUS_SOFTEND_MODE) || \
+ ((MODE) == SMBUS_SENDPEC_MODE) || \
+ ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \
+ ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \
+ ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \
+ ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE )))
+
+
+#define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \
+ ((REQUEST) == SMBUS_GENERATE_START_READ) || \
+ ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \
+ ((REQUEST) == SMBUS_NO_STARTSTOP))
+
+
+#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_FIRST_FRAME) || \
+ ((REQUEST) == SMBUS_NEXT_FRAME) || \
+ ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
+ ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \
+ ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
+ ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC) || \
+ IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
+
+#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \
+ ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \
+ ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \
+ ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))
+
+#define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
+#define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
+
+#define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
+ (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
+
+#define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)
+#define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
+#define SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
+#define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
+#define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
+
+#define SMBUS_GET_ISR_REG(__HANDLE__) ((__HANDLE__)->Instance->ISR)
+#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
+
+#define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
+#define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions
+ * @{
+ */
+
+/** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter);
+HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter);
+
+/**
+ * @}
+ */
+
+/** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
+ * @{
+ */
+
+/* IO operation functions *****************************************************/
+/** @addtogroup Blocking_mode_Polling Blocking mode Polling
+ * @{
+ */
+/******* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt
+ * @{
+ */
+/******* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress);
+HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+
+HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus);
+/**
+ * @}
+ */
+
+/** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+/******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
+void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
+void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
+
+/**
+ * @}
+ */
+
+/** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @{
+ */
+
+/* Peripheral State and Errors functions **************************************************/
+uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
+uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup SMBUS_Private_Functions SMBUS Private Functions
+ * @{
+ */
+/* Private functions are defined in stm32f3xx_hal_smbus.c file */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F3xx_HAL_SMBUS_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_hal_spi.h b/Inc/stm32f3xx_hal_spi.h
new file mode 100644
index 0000000..a43b6ef
--- /dev/null
+++ b/Inc/stm32f3xx_hal_spi.h
@@ -0,0 +1,703 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_spi.h
+ * @author MCD Application Team
+ * @brief Header file of SPI HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_SPI_H
+#define __STM32F3xx_HAL_SPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SPI
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SPI_Exported_Types SPI Exported Types
+ * @{
+ */
+
+/**
+ * @brief SPI Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t Mode; /*!< Specifies the SPI operating mode.
+ This parameter can be a value of @ref SPI_Mode */
+
+ uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.
+ This parameter can be a value of @ref SPI_Direction */
+
+ uint32_t DataSize; /*!< Specifies the SPI data size.
+ This parameter can be a value of @ref SPI_Data_Size */
+
+ uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
+ This parameter can be a value of @ref SPI_Clock_Polarity */
+
+ uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
+ This parameter can be a value of @ref SPI_Clock_Phase */
+
+ uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
+ hardware (NSS pin) or by software using the SSI bit.
+ This parameter can be a value of @ref SPI_Slave_Select_management */
+
+ uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
+ used to configure the transmit and receive SCK clock.
+ This parameter can be a value of @ref SPI_BaudRate_Prescaler
+ @note The communication clock is derived from the master
+ clock. The slave clock does not need to be set. */
+
+ uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
+ This parameter can be a value of @ref SPI_MSB_LSB_transmission */
+
+ uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
+ This parameter can be a value of @ref SPI_TI_mode */
+
+ uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
+ This parameter can be a value of @ref SPI_CRC_Calculation */
+
+ uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
+ This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */
+
+ uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation.
+ CRC Length is only used with Data8 and Data16, not other data size
+ This parameter can be a value of @ref SPI_CRC_length */
+
+ uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not .
+ This parameter can be a value of @ref SPI_NSSP_Mode
+ This mode is activated by the NSSP bit in the SPIx_CR2 register and
+ it takes effect only if the SPI interface is configured as Motorola SPI
+ master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0,
+ CPOL setting is ignored).. */
+} SPI_InitTypeDef;
+
+/**
+ * @brief HAL SPI State structure definition
+ */
+typedef enum
+{
+ HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */
+ HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
+ HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
+ HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
+ HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
+ HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
+ HAL_SPI_STATE_ERROR = 0x06U, /*!< SPI error state */
+ HAL_SPI_STATE_ABORT = 0x07U /*!< SPI abort is ongoing */
+} HAL_SPI_StateTypeDef;
+
+/**
+ * @brief SPI handle Structure definition
+ */
+typedef struct __SPI_HandleTypeDef
+{
+ SPI_TypeDef *Instance; /*!< SPI registers base address */
+
+ SPI_InitTypeDef Init; /*!< SPI communication parameters */
+
+ uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
+
+ uint16_t TxXferSize; /*!< SPI Tx Transfer size */
+
+ __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */
+
+ uint16_t RxXferSize; /*!< SPI Rx Transfer size */
+
+ __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */
+
+ uint32_t CRCSize; /*!< SPI CRC size used for the transfer */
+
+ void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */
+
+ void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */
+
+ DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< Locking object */
+
+ __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */
+
+ __IO uint32_t ErrorCode; /*!< SPI Error code */
+
+} SPI_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SPI_Exported_Constants SPI Exported Constants
+ * @{
+ */
+
+/** @defgroup SPI_Error_Code SPI Error Code
+ * @{
+ */
+#define HAL_SPI_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_SPI_ERROR_MODF (0x00000001U) /*!< MODF error */
+#define HAL_SPI_ERROR_CRC (0x00000002U) /*!< CRC error */
+#define HAL_SPI_ERROR_OVR (0x00000004U) /*!< OVR error */
+#define HAL_SPI_ERROR_FRE (0x00000008U) /*!< FRE error */
+#define HAL_SPI_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
+#define HAL_SPI_ERROR_FLAG (0x00000020U) /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */
+#define HAL_SPI_ERROR_ABORT (0x00000040U) /*!< Error during SPI Abort procedure */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Mode SPI Mode
+ * @{
+ */
+#define SPI_MODE_SLAVE (0x00000000U)
+#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Direction SPI Direction Mode
+ * @{
+ */
+#define SPI_DIRECTION_2LINES (0x00000000U)
+#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
+#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Data_Size SPI Data Size
+ * @{
+ */
+#define SPI_DATASIZE_4BIT (0x00000300U)
+#define SPI_DATASIZE_5BIT (0x00000400U)
+#define SPI_DATASIZE_6BIT (0x00000500U)
+#define SPI_DATASIZE_7BIT (0x00000600U)
+#define SPI_DATASIZE_8BIT (0x00000700U)
+#define SPI_DATASIZE_9BIT (0x00000800U)
+#define SPI_DATASIZE_10BIT (0x00000900U)
+#define SPI_DATASIZE_11BIT (0x00000A00U)
+#define SPI_DATASIZE_12BIT (0x00000B00U)
+#define SPI_DATASIZE_13BIT (0x00000C00U)
+#define SPI_DATASIZE_14BIT (0x00000D00U)
+#define SPI_DATASIZE_15BIT (0x00000E00U)
+#define SPI_DATASIZE_16BIT (0x00000F00U)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
+ * @{
+ */
+#define SPI_POLARITY_LOW (0x00000000U)
+#define SPI_POLARITY_HIGH SPI_CR1_CPOL
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Clock_Phase SPI Clock Phase
+ * @{
+ */
+#define SPI_PHASE_1EDGE (0x00000000U)
+#define SPI_PHASE_2EDGE SPI_CR1_CPHA
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Slave_Select_management SPI Slave Select Management
+ * @{
+ */
+#define SPI_NSS_SOFT SPI_CR1_SSM
+#define SPI_NSS_HARD_INPUT (0x00000000U)
+#define SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode
+ * @{
+ */
+#define SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP
+#define SPI_NSS_PULSE_DISABLE (0x00000000U)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
+ * @{
+ */
+#define SPI_BAUDRATEPRESCALER_2 (0x00000000U)
+#define SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0)
+#define SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1)
+#define SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)
+#define SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2)
+#define SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)
+#define SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)
+#define SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
+ * @{
+ */
+#define SPI_FIRSTBIT_MSB (0x00000000U)
+#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
+/**
+ * @}
+ */
+
+/** @defgroup SPI_TI_mode SPI TI Mode
+ * @{
+ */
+#define SPI_TIMODE_DISABLE (0x00000000U)
+#define SPI_TIMODE_ENABLE SPI_CR2_FRF
+/**
+ * @}
+ */
+
+/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
+ * @{
+ */
+#define SPI_CRCCALCULATION_DISABLE (0x00000000U)
+#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
+/**
+ * @}
+ */
+
+/** @defgroup SPI_CRC_length SPI CRC Length
+ * @{
+ * This parameter can be one of the following values:
+ * SPI_CRC_LENGTH_DATASIZE: aligned with the data size
+ * SPI_CRC_LENGTH_8BIT : CRC 8bit
+ * SPI_CRC_LENGTH_16BIT : CRC 16bit
+ */
+#define SPI_CRC_LENGTH_DATASIZE (0x00000000U)
+#define SPI_CRC_LENGTH_8BIT (0x00000001U)
+#define SPI_CRC_LENGTH_16BIT (0x00000002U)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold
+ * @{
+ * This parameter can be one of the following values:
+ * SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF :
+ * RXNE event is generated if the FIFO
+ * level is greater or equal to 1/2(16-bits).
+ * SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO
+ * level is greater or equal to 1/4(8 bits). */
+#define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH
+#define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH
+#define SPI_RXFIFO_THRESHOLD_HF (0x00000000U)
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
+ * @{
+ */
+#define SPI_IT_TXE SPI_CR2_TXEIE
+#define SPI_IT_RXNE SPI_CR2_RXNEIE
+#define SPI_IT_ERR SPI_CR2_ERRIE
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Flags_definition SPI Flags Definition
+ * @{
+ */
+#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
+#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
+#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
+#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
+#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
+#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
+#define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
+#define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */
+#define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level
+ * @{
+ */
+#define SPI_FTLVL_EMPTY (0x00000000U)
+#define SPI_FTLVL_QUARTER_FULL (0x00000800U)
+#define SPI_FTLVL_HALF_FULL (0x00001000U)
+#define SPI_FTLVL_FULL (0x00001800U)
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level
+ * @{
+ */
+#define SPI_FRLVL_EMPTY (0x00000000U)
+#define SPI_FRLVL_QUARTER_FULL (0x00000200U)
+#define SPI_FRLVL_HALF_FULL (0x00000400U)
+#define SPI_FRLVL_FULL (0x00000600U)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup SPI_Exported_Macros SPI Exported Macros
+ * @{
+ */
+
+/** @brief Reset SPI handle state.
+ * @param __HANDLE__ specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
+
+/** @brief Enable the specified SPI interrupts.
+ * @param __HANDLE__ specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @param __INTERRUPT__ specifies the interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
+ * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg SPI_IT_ERR: Error interrupt enable
+ * @retval None
+ */
+#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
+
+/** @brief Disable the specified SPI interrupts.
+ * @param __HANDLE__ specifies the SPI handle.
+ * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
+ * @param __INTERRUPT__ specifies the interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
+ * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg SPI_IT_ERR: Error interrupt enable
+ * @retval None
+ */
+#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
+
+/** @brief Check whether the specified SPI interrupt source is enabled or not.
+ * @param __HANDLE__ specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @param __INTERRUPT__ specifies the SPI interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
+ * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg SPI_IT_ERR: Error interrupt enable
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Check whether the specified SPI flag is set or not.
+ * @param __HANDLE__ specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg SPI_FLAG_RXNE: Receive buffer not empty flag
+ * @arg SPI_FLAG_TXE: Transmit buffer empty flag
+ * @arg SPI_FLAG_CRCERR: CRC error flag
+ * @arg SPI_FLAG_MODF: Mode fault flag
+ * @arg SPI_FLAG_OVR: Overrun flag
+ * @arg SPI_FLAG_BSY: Busy flag
+ * @arg SPI_FLAG_FRE: Frame format error flag
+ * @arg SPI_FLAG_FTLVL: SPI fifo transmission level
+ * @arg SPI_FLAG_FRLVL: SPI fifo reception level
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the SPI CRCERR pending flag.
+ * @param __HANDLE__ specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
+
+/** @brief Clear the SPI MODF pending flag.
+ * @param __HANDLE__ specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg_modf = 0x00U; \
+ tmpreg_modf = (__HANDLE__)->Instance->SR; \
+ CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \
+ UNUSED(tmpreg_modf); \
+ } while(0U)
+
+/** @brief Clear the SPI OVR pending flag.
+ * @param __HANDLE__ specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg_ovr = 0x00U; \
+ tmpreg_ovr = (__HANDLE__)->Instance->DR; \
+ tmpreg_ovr = (__HANDLE__)->Instance->SR; \
+ UNUSED(tmpreg_ovr); \
+ } while(0U)
+
+/** @brief Clear the SPI FRE pending flag.
+ * @param __HANDLE__ specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg_fre = 0x00U; \
+ tmpreg_fre = (__HANDLE__)->Instance->SR; \
+ UNUSED(tmpreg_fre); \
+ }while(0U)
+
+/** @brief Enable the SPI peripheral.
+ * @param __HANDLE__ specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
+
+/** @brief Disable the SPI peripheral.
+ * @param __HANDLE__ specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SPI_Private_Macros SPI Private Macros
+ * @{
+ */
+
+/** @brief Set the SPI transmit-only mode.
+ * @param __HANDLE__ specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
+
+/** @brief Set the SPI receive-only mode.
+ * @param __HANDLE__ specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
+
+/** @brief Reset the CRC calculation of the SPI.
+ * @param __HANDLE__ specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
+ SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)
+
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
+ ((MODE) == SPI_MODE_MASTER))
+
+#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
+ ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
+ ((MODE) == SPI_DIRECTION_1LINE))
+
+#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
+
+#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
+ ((MODE) == SPI_DIRECTION_1LINE))
+
+#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_15BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_14BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_13BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_12BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_11BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_10BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_9BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_8BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_7BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_6BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_5BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_4BIT))
+
+#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
+ ((CPOL) == SPI_POLARITY_HIGH))
+
+#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
+ ((CPHA) == SPI_PHASE_2EDGE))
+
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
+ ((NSS) == SPI_NSS_HARD_INPUT) || \
+ ((NSS) == SPI_NSS_HARD_OUTPUT))
+
+#define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \
+ ((NSSP) == SPI_NSS_PULSE_DISABLE))
+
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
+
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
+ ((BIT) == SPI_FIRSTBIT_LSB))
+
+#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \
+ ((MODE) == SPI_TIMODE_ENABLE))
+
+#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
+ ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
+
+#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) ||\
+ ((LENGTH) == SPI_CRC_LENGTH_8BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_16BIT))
+
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1U) && ((POLYNOMIAL) <= 0xFFFFU) && (((POLYNOMIAL)&0x1U) != 0U))
+
+#define IS_SPI_DMA_HANDLE(HANDLE) ((HANDLE) != NULL)
+
+
+/**
+ * @}
+ */
+
+/* Include SPI HAL Extended module */
+#include "stm32f3xx_hal_spi_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SPI_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup SPI_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization/de-initialization functions ********************************/
+HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
+void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
+void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Exported_Functions_Group2
+ * @{
+ */
+/* I/O operation functions ***************************************************/
+HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
+
+void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral State and Error functions ***************************************/
+HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
+uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_SPI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_hal_spi_ex.h b/Inc/stm32f3xx_hal_spi_ex.h
new file mode 100644
index 0000000..25fcdee
--- /dev/null
+++ b/Inc/stm32f3xx_hal_spi_ex.h
@@ -0,0 +1,91 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_spi_ex.h
+ * @author MCD Application Team
+ * @brief Header file of SPI HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_SPI_EX_H
+#define __STM32F3xx_HAL_SPI_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SPIEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SPIEx_Exported_Functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+/* IO operation functions *****************************************************/
+/** @addtogroup SPIEx_Exported_Functions_Group1
+ * @{
+ */
+HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_SPI_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_hal_sram.h b/Inc/stm32f3xx_hal_sram.h
new file mode 100644
index 0000000..7d1e6f5
--- /dev/null
+++ b/Inc/stm32f3xx_hal_sram.h
@@ -0,0 +1,197 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_sram.h
+ * @author MCD Application Team
+ * @brief Header file of SRAM HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_SRAM_H
+#define __STM32F3xx_HAL_SRAM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+#include "stm32f3xx_ll_fmc.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SRAM
+ * @{
+ */
+
+/* Exported typedef ----------------------------------------------------------*/
+
+/** @defgroup SRAM_Exported_Types SRAM Exported Types
+ * @{
+ */
+/**
+ * @brief HAL SRAM State structures definition
+ */
+typedef enum
+{
+ HAL_SRAM_STATE_RESET = 0x00U, /*!< SRAM not yet initialized or disabled */
+ HAL_SRAM_STATE_READY = 0x01U, /*!< SRAM initialized and ready for use */
+ HAL_SRAM_STATE_BUSY = 0x02U, /*!< SRAM internal process is ongoing */
+ HAL_SRAM_STATE_ERROR = 0x03U, /*!< SRAM error state */
+ HAL_SRAM_STATE_PROTECTED = 0x04 /*!< SRAM peripheral NORSRAM device write protected */
+
+}HAL_SRAM_StateTypeDef;
+
+/**
+ * @brief SRAM handle Structure definition
+ */
+typedef struct
+{
+ FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
+
+ FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
+
+ FMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */
+
+ HAL_LockTypeDef Lock; /*!< SRAM locking object */
+
+ __IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */
+
+ DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
+
+}SRAM_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup SRAM_Exported_Macros SRAM Exported Macros
+ * @{
+ */
+
+/** @brief Reset SRAM handle state
+ * @param __HANDLE__ SRAM handle
+ * @retval None
+ */
+#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SRAM_Exported_Functions SRAM Exported Functions
+ * @{
+ */
+
+/** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization/de-initialization functions ********************************/
+HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
+HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
+void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
+void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
+
+void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
+void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
+
+/**
+ * @}
+ */
+
+/** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
+ * @{
+ */
+
+/* I/O operation functions ***************************************************/
+HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
+
+/**
+ * @}
+ */
+
+/** @addtogroup SRAM_Exported_Functions_Group3 Control functions
+ * @{
+ */
+
+/* SRAM Control functions ****************************************************/
+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
+
+/**
+ * @}
+ */
+
+/** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions
+ * @{
+ */
+
+/* SRAM Peripheral State functions ********************************************/
+HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_SRAM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_hal_tim.h b/Inc/stm32f3xx_hal_tim.h
new file mode 100644
index 0000000..6cb103b
--- /dev/null
+++ b/Inc/stm32f3xx_hal_tim.h
@@ -0,0 +1,1623 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_tim.h
+ * @author MCD Application Team
+ * @brief Header file of TIM HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_TIM_H
+#define __STM32F3xx_HAL_TIM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup TIM
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup TIM_Exported_Types TIM Exported Types
+ * @{
+ */
+/**
+ * @brief TIM Time base Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFU */
+
+ uint32_t CounterMode; /*!< Specifies the counter mode.
+ This parameter can be a value of @ref TIM_Counter_Mode */
+
+ uint32_t Period; /*!< Specifies the period value to be loaded into the active
+ Auto-Reload Register at the next update event.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
+ uint32_t ClockDivision; /*!< Specifies the clock division.
+ This parameter can be a value of @ref TIM_ClockDivision */
+
+ uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
+ reaches zero, an update event is generated and counting restarts
+ from the RCR value (N).
+ This means in PWM mode that (N+1U) corresponds to:
+ - the number of PWM periods in edge-aligned mode
+ - the number of half PWM period in center-aligned mode
+ GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+ Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
+ uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
+ This parameter can be a value of @ref TIM_AutoReloadPreload */
+} TIM_Base_InitTypeDef;
+
+/**
+ * @brief TIM Output Compare Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t OCMode; /*!< Specifies the TIM mode.
+ This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */
+
+ uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFU */
+
+ uint32_t OCPolarity; /*!< Specifies the output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+ uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint32_t OCFastMode; /*!< Specifies the Fast mode state.
+ This parameter can be a value of @ref TIM_Output_Fast_State
+ @note This parameter is valid only in PWM1 and PWM2 mode. */
+
+
+ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+ @note This parameter is valid only for TIM1 and TIM8. */
+} TIM_OC_InitTypeDef;
+
+/**
+ * @brief TIM One Pulse Mode Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t OCMode; /*!< Specifies the TIM mode.
+ This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */
+
+ uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFU */
+
+ uint32_t OCPolarity; /*!< Specifies the output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+ uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint32_t ICSelection; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+ uint32_t ICFilter; /*!< Specifies the input capture filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
+} TIM_OnePulse_InitTypeDef;
+
+
+/**
+ * @brief TIM Input Capture Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint32_t ICSelection; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+ uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+ uint32_t ICFilter; /*!< Specifies the input capture filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
+} TIM_IC_InitTypeDef;
+
+/**
+ * @brief TIM Encoder Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Encoder_Mode */
+
+ uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint32_t IC1Selection; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+ uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+ uint32_t IC1Filter; /*!< Specifies the input capture filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
+
+ uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint32_t IC2Selection; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+ uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+ uint32_t IC2Filter; /*!< Specifies the input capture filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
+} TIM_Encoder_InitTypeDef;
+
+
+/**
+ * @brief TIM Clock Configuration Handle Structure definition
+ */
+typedef struct
+{
+ uint32_t ClockSource; /*!< TIM clock sources
+ This parameter can be a value of @ref TIM_Clock_Source */
+ uint32_t ClockPolarity; /*!< TIM clock polarity
+ This parameter can be a value of @ref TIM_Clock_Polarity */
+ uint32_t ClockPrescaler; /*!< TIM clock prescaler
+ This parameter can be a value of @ref TIM_Clock_Prescaler */
+ uint32_t ClockFilter; /*!< TIM clock filter
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
+}TIM_ClockConfigTypeDef;
+
+/**
+ * @brief TIM Clear Input Configuration Handle Structure definition
+ */
+typedef struct
+{
+ uint32_t ClearInputState; /*!< TIM clear Input state
+ This parameter can be ENABLE or DISABLE */
+ uint32_t ClearInputSource; /*!< TIM clear Input sources
+ This parameter can be a value of @ref TIMEx_ClearInput_Source */
+ uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
+ This parameter can be a value of @ref TIM_ClearInput_Polarity */
+ uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
+ This parameter can be a value of @ref TIM_ClearInput_Prescaler */
+ uint32_t ClearInputFilter; /*!< TIM Clear Input filter
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
+}TIM_ClearInputConfigTypeDef;
+
+/**
+ * @brief TIM Slave configuration Structure definition
+ */
+typedef struct {
+ uint32_t SlaveMode; /*!< Slave mode selection
+ This parameter can be a value of @ref TIMEx_Slave_Mode */
+ uint32_t InputTrigger; /*!< Input Trigger source
+ This parameter can be a value of @ref TIM_Trigger_Selection */
+ uint32_t TriggerPolarity; /*!< Input Trigger polarity
+ This parameter can be a value of @ref TIM_Trigger_Polarity */
+ uint32_t TriggerPrescaler; /*!< Input trigger prescaler
+ This parameter can be a value of @ref TIM_Trigger_Prescaler */
+ uint32_t TriggerFilter; /*!< Input trigger filter
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
+
+}TIM_SlaveConfigTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
+ HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
+ HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
+ HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
+ HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
+}HAL_TIM_StateTypeDef;
+
+/**
+ * @brief HAL Active channel structures definition
+ */
+typedef enum
+{
+ HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */
+ HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */
+ HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */
+ HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */
+ HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */
+}HAL_TIM_ActiveChannel;
+
+/**
+ * @brief TIM Time Base Handle Structure definition
+ */
+typedef struct
+{
+ TIM_TypeDef *Instance; /*!< Register base address */
+ TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
+ HAL_TIM_ActiveChannel Channel; /*!< Active channel */
+ DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
+ This array is accessed by a @ref TIM_DMA_Handle_index */
+ HAL_LockTypeDef Lock; /*!< Locking object */
+ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
+}TIM_HandleTypeDef;
+
+/**
+ * @}
+ */
+/* End of exported types -----------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIM_Exported_Constants TIM Exported Constants
+ * @{
+ */
+
+/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
+ * @{
+ */
+#define TIM_INPUTCHANNELPOLARITY_RISING (0x00000000U) /*!< Polarity for TIx source */
+#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */
+#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
+ * @{
+ */
+#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
+#define TIM_ETRPOLARITY_NONINVERTED (0x0000U) /*!< Polarity for ETR source */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
+ * @{
+ */
+#define TIM_ETRPRESCALER_DIV1 (0x0000U) /*!< No prescaler is used */
+#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2U */
+#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4U */
+#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8U */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Counter_Mode TIM Counter Mode
+ * @{
+ */
+#define TIM_COUNTERMODE_UP (0x0000U)
+#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
+#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
+#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
+#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ClockDivision TIM Clock Division
+ * @{
+ */
+#define TIM_CLOCKDIVISION_DIV1 (0x0000U)
+#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
+#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
+ * @{
+ */
+#define TIM_AUTORELOAD_PRELOAD_DISABLE (0x0000U) /*!< TIMx_ARR register is not buffered */
+#define TIM_AUTORELOAD_PRELOAD_ENABLE (TIM_CR1_ARPE) /*!< TIMx_ARR register is buffered */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Fast_State TIM Output Fast State
+ * @{
+ */
+#define TIM_OCFAST_DISABLE (0x0000U)
+#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
+ * @{
+ */
+#define TIM_OCPOLARITY_HIGH (0x0000U)
+#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
+ * @{
+ */
+#define TIM_OCNPOLARITY_HIGH (0x0000U)
+#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
+ * @{
+ */
+#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
+#define TIM_OCIDLESTATE_RESET (0x0000U)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
+ * @{
+ */
+#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
+#define TIM_OCNIDLESTATE_RESET (0x0000U)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
+ * @{
+ */
+#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
+#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
+#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
+ * @{
+ */
+#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1U, 2U, 3 or 4 is selected to be
+ connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1U, 2U, 3 or 4 is selected to be
+ connected to IC2, IC1, IC4 or IC3, respectively */
+#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1U, 2U, 3 or 4 is selected to be connected to TRC */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
+ * @{
+ */
+#define TIM_ICPSC_DIV1 (0x0000U) /*!< Capture performed each time an edge is detected on the capture input */
+#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */
+#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */
+#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
+ * @{
+ */
+#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
+#define TIM_OPMODE_REPETITIVE (0x0000U)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
+ * @{
+ */
+#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
+#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
+#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Interrupt_definition TIM Interrupt Definition
+ * @{
+ */
+#define TIM_IT_UPDATE (TIM_DIER_UIE)
+#define TIM_IT_CC1 (TIM_DIER_CC1IE)
+#define TIM_IT_CC2 (TIM_DIER_CC2IE)
+#define TIM_IT_CC3 (TIM_DIER_CC3IE)
+#define TIM_IT_CC4 (TIM_DIER_CC4IE)
+#define TIM_IT_COM (TIM_DIER_COMIE)
+#define TIM_IT_TRIGGER (TIM_DIER_TIE)
+#define TIM_IT_BREAK (TIM_DIER_BIE)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Commutation_Source TIM Commutation Source
+ * @{
+ */
+#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
+#define TIM_COMMUTATION_SOFTWARE (0x0000U)
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_sources TIM DMA Sources
+ * @{
+ */
+#define TIM_DMA_UPDATE (TIM_DIER_UDE)
+#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
+#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
+#define TIM_DMA_CC3 (TIM_DIER_CC3DE)
+#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
+#define TIM_DMA_COM (TIM_DIER_COMDE)
+#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Flag_definition TIM Flag Definition
+ * @{
+ */
+#define TIM_FLAG_UPDATE (TIM_SR_UIF)
+#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
+#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
+#define TIM_FLAG_CC3 (TIM_SR_CC3IF)
+#define TIM_FLAG_CC4 (TIM_SR_CC4IF)
+#define TIM_FLAG_COM (TIM_SR_COMIF)
+#define TIM_FLAG_TRIGGER (TIM_SR_TIF)
+#define TIM_FLAG_BREAK (TIM_SR_BIF)
+#if defined(TIM_SR_B2IF)
+#define TIM_FLAG_BREAK2 (TIM_SR_B2IF)
+#endif
+#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
+#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
+#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
+#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Clock_Source TIM Clock Source
+ * @{
+ */
+#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
+#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
+#define TIM_CLOCKSOURCE_ITR0 (0x0000U)
+#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
+#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
+#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
+#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
+#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
+#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
+#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
+ * @{
+ */
+#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
+ * @{
+ */
+#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
+#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
+#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
+#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
+ * @{
+ */
+#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
+#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
+ * @{
+ */
+#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
+#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR Off State Selection for Run mode state
+ * @{
+ */
+#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
+#define TIM_OSSR_DISABLE (0x0000U)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI Off State Selection for Idle mode state
+ * @{
+ */
+#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
+#define TIM_OSSI_DISABLE (0x0000U)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Lock_level TIM Lock level
+ * @{
+ */
+#define TIM_LOCKLEVEL_OFF (0x0000U)
+#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
+#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
+#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable Disable
+ * @{
+ */
+#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
+#define TIM_BREAK_DISABLE (0x0000U)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
+ * @{
+ */
+#define TIM_BREAKPOLARITY_LOW (0x0000U)
+#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
+/**
+ * @}
+ */
+/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
+ * @{
+ */
+#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
+#define TIM_AUTOMATICOUTPUT_DISABLE (0x0000U)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
+ * @{
+ */
+#define TIM_TRGO_RESET (0x0000U)
+#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
+#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
+#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
+#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
+#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
+#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
+#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
+ * @{
+ */
+#define TIM_MASTERSLAVEMODE_ENABLE (0x0080U)
+#define TIM_MASTERSLAVEMODE_DISABLE (0x0000U)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
+ * @{
+ */
+#define TIM_TS_ITR0 (0x0000U)
+#define TIM_TS_ITR1 (0x0010U)
+#define TIM_TS_ITR2 (0x0020U)
+#define TIM_TS_ITR3 (0x0030U)
+#define TIM_TS_TI1F_ED (0x0040U)
+#define TIM_TS_TI1FP1 (0x0050U)
+#define TIM_TS_TI2FP2 (0x0060U)
+#define TIM_TS_ETRF (0x0070U)
+#define TIM_TS_NONE (0xFFFFU)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
+ * @{
+ */
+#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
+#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
+#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
+ * @{
+ */
+#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
+#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
+#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
+#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
+/**
+ * @}
+ */
+
+ /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
+ * @{
+ */
+#define TIM_TI1SELECTION_CH1 (0x0000U)
+#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
+ * @{
+ */
+#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000U)
+#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100U)
+#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200U)
+#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300U)
+#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400U)
+#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500U)
+#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600U)
+#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700U)
+#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800U)
+#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900U)
+#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00U)
+#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00U)
+#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00U)
+#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00U)
+#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00U)
+#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00U)
+#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000U)
+#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100U)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_Handle_index TIM DMA Handle Index
+ * @{
+ */
+#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0U) /*!< Index of the DMA handle used for Update DMA requests */
+#define TIM_DMA_ID_CC1 ((uint16_t) 0x1U) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
+#define TIM_DMA_ID_CC2 ((uint16_t) 0x2U) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
+#define TIM_DMA_ID_CC3 ((uint16_t) 0x3U) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
+#define TIM_DMA_ID_CC4 ((uint16_t) 0x4U) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
+#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5U) /*!< Index of the DMA handle used for Commutation DMA requests */
+#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6U) /*!< Index of the DMA handle used for Trigger DMA requests */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Channel_CC_State TIM Capture/Compare Channel State
+ * @{
+ */
+#define TIM_CCx_ENABLE (0x0001U)
+#define TIM_CCx_DISABLE (0x0000U)
+#define TIM_CCxN_ENABLE (0x0004U)
+#define TIM_CCxN_DISABLE (0x0000U)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* End of exported constants -------------------------------------------------*/
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup TIM_Exported_Macros TIM Exported Macros
+ * @{
+ */
+
+/** @brief Reset TIM handle state
+ * @param __HANDLE__ TIM handle.
+ * @retval None
+ */
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
+
+/**
+ * @brief Enable the TIM peripheral.
+ * @param __HANDLE__ TIM handle
+ * @retval None
+ */
+#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
+
+/**
+ * @brief Enable the TIM main Output.
+ * @param __HANDLE__ TIM handle
+ * @retval None
+ */
+#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
+
+/**
+ * @brief Disable the TIM peripheral.
+ * @param __HANDLE__ TIM handle
+ * @retval None
+ */
+#define __HAL_TIM_DISABLE(__HANDLE__) \
+ do { \
+ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
+ { \
+ if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
+ { \
+ (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
+ } \
+ } \
+ } while(0U)
+/* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN
+ channels have been disabled */
+/**
+ * @brief Disable the TIM main Output.
+ * @param __HANDLE__ TIM handle
+ * @retval None
+ * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
+ */
+#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
+ do { \
+ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
+ { \
+ if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
+ { \
+ (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
+ } \
+ } \
+ } while(0U)
+
+/* The Main Output Enable of a timer instance is disabled unconditionally */
+/**
+ * @brief Disable the TIM main Output.
+ * @param __HANDLE__ TIM handle
+ * @retval None
+ * @note The Main Output Enable of a timer instance is disabled uncondiotionally
+ */
+#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
+
+/**
+ * @brief Enables the specified TIM interrupt.
+ * @param __HANDLE__ specifies the TIM Handle.
+ * @param __INTERRUPT__ specifies the TIM interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg TIM_IT_UPDATE: Update interrupt
+ * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
+ * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
+ * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
+ * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
+ * @arg TIM_IT_COM: Commutation interrupt
+ * @arg TIM_IT_TRIGGER: Trigger interrupt
+ * @arg TIM_IT_BREAK: Break interrupt
+ * @retval None
+ */
+#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
+
+/**
+ * @brief Disables the specified TIM interrupt.
+ * @param __HANDLE__ specifies the TIM Handle.
+ * @param __INTERRUPT__ specifies the TIM interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg TIM_IT_UPDATE: Update interrupt
+ * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
+ * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
+ * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
+ * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
+ * @arg TIM_IT_COM: Commutation interrupt
+ * @arg TIM_IT_TRIGGER: Trigger interrupt
+ * @arg TIM_IT_BREAK: Break interrupt
+ * @retval None
+ */
+#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
+
+/**
+ * @brief Enables the specified DMA request.
+ * @param __HANDLE__ specifies the TIM Handle.
+ * @param __DMA__ specifies the TIM DMA request to enable.
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: Update DMA request
+ * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
+ * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
+ * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
+ * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
+ * @arg TIM_DMA_COM: Commutation DMA request
+ * @arg TIM_DMA_TRIGGER: Trigger DMA request
+ * @retval None
+ */
+#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
+
+/**
+ * @brief Disables the specified DMA request.
+ * @param __HANDLE__ specifies the TIM Handle.
+ * @param __DMA__ specifies the TIM DMA request to disable.
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: Update DMA request
+ * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
+ * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
+ * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
+ * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
+ * @arg TIM_DMA_COM: Commutation DMA request
+ * @arg TIM_DMA_TRIGGER: Trigger DMA request
+ * @retval None
+ */
+#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
+
+/**
+ * @brief Checks whether the specified TIM interrupt flag is set or not.
+ * @param __HANDLE__ specifies the TIM Handle.
+ * @param __FLAG__ specifies the TIM interrupt flag to check.
+ * This parameter can be one of the following values:
+ * @arg TIM_FLAG_UPDATE: Update interrupt flag
+ * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
+ * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
+ * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
+ * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
+ * @arg TIM_FLAG_COM: Commutation interrupt flag
+ * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
+ * @arg TIM_FLAG_BREAK: Break interrupt flag
+ * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
+ * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
+ * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
+ * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Clears the specified TIM interrupt flag.
+ * @param __HANDLE__ specifies the TIM Handle.
+ * @param __FLAG__ specifies the TIM interrupt flag to clear.
+ * This parameter can be one of the following values:
+ * @arg TIM_FLAG_UPDATE: Update interrupt flag
+ * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
+ * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
+ * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
+ * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
+ * @arg TIM_FLAG_COM: Commutation interrupt flag
+ * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
+ * @arg TIM_FLAG_BREAK: Break interrupt flag
+ * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
+ * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
+ * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
+ * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
+
+/**
+ * @brief Checks whether the specified TIM interrupt has occurred or not.
+ * @param __HANDLE__ TIM handle
+ * @param __INTERRUPT__ specifies the TIM interrupt source to check.
+ * @retval The state of TIM_IT (SET or RESET).
+ */
+#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/**
+ * @brief Clear the TIM interrupt pending bits
+ * @param __HANDLE__ TIM handle
+ * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
+ * @retval None
+ */
+#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
+
+/**
+ * @brief Indicates whether or not the TIM Counter is used as downcounter
+ * @param __HANDLE__ TIM handle.
+ * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
+ * @note This macro is particularly usefull to get the counting mode when the timer operates in Center-aligned mode or Encoder mode.
+ */
+#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
+
+/**
+ * @brief Sets the TIM active prescaler register value on update event.
+ * @param __HANDLE__ TIM handle.
+ * @param __PRESC__ specifies the active prescaler register new value.
+ * @retval None
+ */
+#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
+
+/**
+ * @brief Sets the TIM Counter Register value on runtime.
+ * @param __HANDLE__ TIM handle.
+ * @param __COUNTER__ specifies the Counter register new value.
+ * @retval None
+ */
+#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
+
+/**
+ * @brief Gets the TIM Counter Register value on runtime.
+ * @param __HANDLE__ TIM handle.
+ * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
+ */
+#define __HAL_TIM_GET_COUNTER(__HANDLE__) \
+ ((__HANDLE__)->Instance->CNT)
+
+/**
+ * @brief Sets the TIM Autoreload Register value on runtime without calling
+ * another time any Init function.
+ * @param __HANDLE__ TIM handle.
+ * @param __AUTORELOAD__ specifies the Counter register new value.
+ * @retval None
+ */
+#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
+ do{ \
+ (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
+ (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
+ } while(0U)
+
+/**
+ * @brief Gets the TIM Autoreload Register value on runtime
+ * @param __HANDLE__ TIM handle.
+ * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
+ */
+#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \
+ ((__HANDLE__)->Instance->ARR)
+
+/**
+ * @brief Sets the TIM Clock Division value on runtime without calling
+ * another time any Init function.
+ * @param __HANDLE__ TIM handle.
+ * @param __CKD__ specifies the clock division value.
+ * This parameter can be one of the following value:
+ * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
+ * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
+ * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
+ * @retval None
+ */
+#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
+ do{ \
+ (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
+ (__HANDLE__)->Instance->CR1 |= (__CKD__); \
+ (__HANDLE__)->Init.ClockDivision = (__CKD__); \
+ } while(0U)
+
+/**
+ * @brief Gets the TIM Clock Division value on runtime
+ * @param __HANDLE__ TIM handle.
+ * @retval The clock division can be one of the following values:
+ * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
+ * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
+ * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
+ */
+#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \
+ ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
+
+/**
+ * @brief Sets the TIM Input Capture prescaler on runtime without calling
+ * another time HAL_TIM_IC_ConfigChannel() function.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param __ICPSC__ specifies the Input Capture4 prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPSC_DIV1: no prescaler
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+ * @retval None
+ */
+#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
+ do{ \
+ TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
+ TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
+ } while(0U)
+
+/**
+ * @brief Gets the TIM Input Capture prescaler on runtime
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
+ * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
+ * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
+ * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
+ * @retval The input capture prescaler can be one of the following values:
+ * @arg TIM_ICPSC_DIV1: no prescaler
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+ */
+#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
+ (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
+
+/**
+ * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
+ * @param __HANDLE__ TIM handle.
+ * @note When the USR bit of the TIMx_CR1 register is set, only counter
+ * overflow/underflow generates an update interrupt or DMA request (if
+ * enabled)
+ * @retval None
+ */
+#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
+ ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
+
+/**
+ * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
+ * @param __HANDLE__ TIM handle.
+ * @note When the USR bit of the TIMx_CR1 register is reset, any of the
+ * following events generate an update interrupt or DMA request (if
+ * enabled):
+ * (+) Counter overflow/underflow
+ * (+) Setting the UG bit
+ * (+) Update generation through the slave mode controller
+ * @retval None
+ */
+#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
+ ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
+
+/**
+ * @brief Sets the TIM Capture x input polarity on runtime.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param __POLARITY__ Polarity for TIx source
+ * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
+ * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
+ * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
+ * @retval None
+ */
+#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
+ do{ \
+ TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
+ TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
+ }while(0U)
+
+/**
+ * @}
+ */
+/* End of exported macros ----------------------------------------------------*/
+
+/* Private Constants -----------------------------------------------------------*/
+/** @defgroup TIM_Private_Constants TIM Private Constants
+ * @{
+ */
+
+/* The counter of a timer instance is disabled only if all the CCx and CCxN
+ channels have been disabled */
+#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
+#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
+
+/**
+ * @}
+ */
+/* End of private constants --------------------------------------------------*/
+
+/* Private Macros -----------------------------------------------------------*/
+/** @defgroup TIM_Private_Macros TIM Private Macros
+ * @{
+ */
+
+#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \
+ ((MODE) == TIM_COUNTERMODE_DOWN) || \
+ ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \
+ ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \
+ ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
+
+#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \
+ ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
+ ((DIV) == TIM_CLOCKDIVISION_DIV4))
+
+#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
+ ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
+
+#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \
+ ((STATE) == TIM_OCFAST_ENABLE))
+
+#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \
+ ((POLARITY) == TIM_OCPOLARITY_LOW))
+
+#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \
+ ((POLARITY) == TIM_OCNPOLARITY_LOW))
+
+#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \
+ ((STATE) == TIM_OCIDLESTATE_RESET))
+
+#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \
+ ((STATE) == TIM_OCNIDLESTATE_RESET))
+
+
+#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \
+ ((POLARITY) == TIM_ICPOLARITY_FALLING) || \
+ ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
+
+#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \
+ ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
+ ((SELECTION) == TIM_ICSELECTION_TRC))
+
+#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
+ ((PRESCALER) == TIM_ICPSC_DIV2) || \
+ ((PRESCALER) == TIM_ICPSC_DIV4) || \
+ ((PRESCALER) == TIM_ICPSC_DIV8))
+
+#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \
+ ((MODE) == TIM_OPMODE_REPETITIVE))
+
+#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \
+ ((MODE) == TIM_ENCODERMODE_TI2) || \
+ ((MODE) == TIM_ENCODERMODE_TI12))
+
+#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U))
+
+
+#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
+
+#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \
+ ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
+ ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \
+ ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \
+ ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
+
+#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
+ ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
+ ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
+ ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
+
+#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xFU)
+
+#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
+ ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
+
+#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
+ ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
+ ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
+ ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
+
+#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xFU)
+
+#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
+ ((STATE) == TIM_OSSR_DISABLE))
+
+#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
+ ((STATE) == TIM_OSSI_DISABLE))
+
+#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
+ ((LEVEL) == TIM_LOCKLEVEL_1) || \
+ ((LEVEL) == TIM_LOCKLEVEL_2) || \
+ ((LEVEL) == TIM_LOCKLEVEL_3))
+
+#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \
+ ((STATE) == TIM_BREAK_DISABLE))
+
+#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
+ ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
+
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
+ ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
+
+#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \
+ ((SOURCE) == TIM_TRGO_ENABLE) || \
+ ((SOURCE) == TIM_TRGO_UPDATE) || \
+ ((SOURCE) == TIM_TRGO_OC1) || \
+ ((SOURCE) == TIM_TRGO_OC1REF) || \
+ ((SOURCE) == TIM_TRGO_OC2REF) || \
+ ((SOURCE) == TIM_TRGO_OC3REF) || \
+ ((SOURCE) == TIM_TRGO_OC4REF))
+
+#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
+ ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
+
+#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+ ((SELECTION) == TIM_TS_ITR1) || \
+ ((SELECTION) == TIM_TS_ITR2) || \
+ ((SELECTION) == TIM_TS_ITR3) || \
+ ((SELECTION) == TIM_TS_TI1F_ED) || \
+ ((SELECTION) == TIM_TS_TI1FP1) || \
+ ((SELECTION) == TIM_TS_TI2FP2) || \
+ ((SELECTION) == TIM_TS_ETRF))
+
+#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+ ((SELECTION) == TIM_TS_ITR1) || \
+ ((SELECTION) == TIM_TS_ITR2) || \
+ ((SELECTION) == TIM_TS_ITR3) || \
+ ((SELECTION) == TIM_TS_NONE))
+
+#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \
+ ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
+ ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \
+ ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \
+ ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
+
+#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
+ ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
+ ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
+ ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
+
+#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xFU)
+
+#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \
+ ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
+
+#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
+
+#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
+
+#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xFU)
+
+/** @brief Set TIM IC prescaler
+ * @param __HANDLE__ TIM handle
+ * @param __CHANNEL__ specifies TIM Channel
+ * @param __ICPSC__ specifies the prescaler value.
+ * @retval None
+ */
+#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
+ ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
+
+/** @brief Reset TIM IC prescaler
+ * @param __HANDLE__ TIM handle
+ * @param __CHANNEL__ specifies TIM Channel
+ * @retval None
+ */
+#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
+ ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
+
+/** @brief Set TIM IC polarity
+ * @param __HANDLE__ TIM handle
+ * @param __CHANNEL__ specifies TIM Channel
+ * @param __POLARITY__ specifies TIM Channel Polarity
+ * @retval None
+ */
+#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
+ ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
+
+/** @brief Reset TIM IC polarity
+ * @param __HANDLE__ TIM handle
+ * @param __CHANNEL__ specifies TIM Channel
+ * @retval None
+ */
+#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
+ ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
+/**
+ * @}
+ */
+/* End of private macros -----------------------------------------------------*/
+
+/* Include TIM HAL Extended module */
+#include "stm32f3xx_hal_tim_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIM_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group1
+ * @{
+ */
+/* Time Base functions ********************************************************/
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group2
+ * @{
+ */
+/* Timer Output Compare functions **********************************************/
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group3
+ * @{
+ */
+/* Timer PWM functions *********************************************************/
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group4
+ * @{
+ */
+/* Timer Input Capture functions ***********************************************/
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group5
+ * @{
+ */
+/* Timer One Pulse functions ***************************************************/
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group6
+ * @{
+ */
+/* Timer Encoder functions *****************************************************/
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig);
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
+ /* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group7
+ * @{
+ */
+/* Interrupt Handler functions **********************************************/
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group8
+ * @{
+ */
+/* Control functions *********************************************************/
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel);
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
+ uint32_t *BurstBuffer, uint32_t BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
+ uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
+ uint32_t *BurstBuffer, uint32_t BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
+ uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
+uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group9
+ * @{
+ */
+/* Callback in non blocking modes (Interrupt and DMA) *************************/
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group10
+ * @{
+ */
+/* Peripheral State functions **************************************************/
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* End of exported functions -------------------------------------------------*/
+
+/* Private Functions --------------------------------------------------------*/
+/** @addtogroup TIM_Private_Functions
+ * @{
+ */
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
+void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
+ uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
+void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
+void TIM_DMAError(DMA_HandleTypeDef *hdma);
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
+void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
+/**
+ * @}
+ */
+/* End of private functions --------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_TIM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_hal_tim_ex.h b/Inc/stm32f3xx_hal_tim_ex.h
new file mode 100644
index 0000000..178a460
--- /dev/null
+++ b/Inc/stm32f3xx_hal_tim_ex.h
@@ -0,0 +1,1243 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_tim_ex.h
+ * @author MCD Application Team
+ * @brief Header file of TIM HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_TIM_EX_H
+#define __STM32F3xx_HAL_TIM_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup TIMEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Types TIMEx Exported Types
+ * @{
+ */
+
+/**
+ * @brief TIM Hall sensor Configuration Structure definition
+ */
+
+typedef struct
+{
+
+ uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+ uint32_t IC1Filter; /*!< Specifies the input capture filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
+ uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFU */
+} TIM_HallSensor_InitTypeDef;
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief TIM Master configuration Structure definition
+ * @note STM32F373xC and STM32F378xx: timer instances provide a single TRGO
+ * output
+ */
+typedef struct {
+ uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
+ This parameter can be a value of @ref TIM_Master_Mode_Selection */
+ uint32_t MasterSlaveMode; /*!< Master/slave mode selection
+ This parameter can be a value of @ref TIM_Master_Slave_Mode */
+}TIM_MasterConfigTypeDef;
+
+/**
+ * @brief TIM Break and Dead time configuration Structure definition
+ * @note STM32F373xC and STM32F378xx: single break input with configurable polarity.
+ */
+typedef struct
+{
+ uint32_t OffStateRunMode; /*!< TIM off state in run mode
+ This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
+ uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
+ This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
+ uint32_t LockLevel; /*!< TIM Lock level
+ This parameter can be a value of @ref TIM_Lock_level */
+ uint32_t DeadTime; /*!< TIM dead Time
+ This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFFU */
+ uint32_t BreakState; /*!< TIM Break State
+ This parameter can be a value of @ref TIM_Break_Input_enable_disable */
+ uint32_t BreakPolarity; /*!< TIM Break input polarity
+ This parameter can be a value of @ref TIM_Break_Polarity */
+ uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
+ This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+} TIM_BreakDeadTimeConfigTypeDef;
+
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief TIM Break input(s) and Dead time configuration Structure definition
+ * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable
+ * filter and polarity.
+ */
+typedef struct
+{
+ uint32_t OffStateRunMode; /*!< TIM off state in run mode
+ This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
+ uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
+ This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
+ uint32_t LockLevel; /*!< TIM Lock level
+ This parameter can be a value of @ref TIM_Lock_level */
+ uint32_t DeadTime; /*!< TIM dead Time
+ This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFFU */
+ uint32_t BreakState; /*!< TIM Break State
+ This parameter can be a value of @ref TIM_Break_Input_enable_disable */
+ uint32_t BreakPolarity; /*!< TIM Break input polarity
+ This parameter can be a value of @ref TIM_Break_Polarity */
+ uint32_t BreakFilter; /*!< Specifies the brek input filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
+ uint32_t Break2State; /*!< TIM Break2 State
+ This parameter can be a value of @ref TIMEx_Break2_Input_enable_disable */
+ uint32_t Break2Polarity; /*!< TIM Break2 input polarity
+ This parameter can be a value of @ref TIMEx_Break2_Polarity */
+ uint32_t Break2Filter; /*!< TIM break2 input filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
+ uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
+ This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+} TIM_BreakDeadTimeConfigTypeDef;
+
+/**
+ * @brief TIM Master configuration Structure definition
+ * @note Advanced timers provide TRGO2 internal line which is redirected
+ * to the ADC
+ */
+typedef struct {
+ uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
+ This parameter can be a value of @ref TIM_Master_Mode_Selection */
+ uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection
+ This parameter can be a value of @ref TIMEx_Master_Mode_Selection_2 */
+ uint32_t MasterSlaveMode; /*!< Master/slave mode selection
+ This parameter can be a value of @ref TIM_Master_Slave_Mode */
+}TIM_MasterConfigTypeDef;
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Constants TIMEx Exported Constants
+ * @{
+ */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/** @defgroup TIMEx_Channel TIMEx Channel
+ * @{
+ */
+#define TIM_CHANNEL_1 (0x0000U)
+#define TIM_CHANNEL_2 (0x0004U)
+#define TIM_CHANNEL_3 (0x0008U)
+#define TIM_CHANNEL_4 (0x000CU)
+#define TIM_CHANNEL_ALL (0x0018U)
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Output_Compare_and_PWM_modes TIMEx Output Compare and PWM Modes
+ * @{
+ */
+#define TIM_OCMODE_TIMING (0x0000U)
+#define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0)
+#define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1)
+#define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
+#define TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
+#define TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M)
+#define TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
+#define TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2)
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_ClearInput_Source TIMEx Clear Input Source
+ * @{
+ */
+#define TIM_CLEARINPUTSOURCE_ETR (0x0001U)
+#define TIM_CLEARINPUTSOURCE_NONE (0x0000U)
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Slave_Mode TIMEx Slave Mode
+ * @{
+ */
+#define TIM_SLAVEMODE_DISABLE (0x0000U)
+#define TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2))
+#define TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0))
+#define TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1))
+#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0))
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Event_Source TIMEx Event Source
+ * @{
+ */
+#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */
+#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1U */
+#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2U */
+#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3U */
+#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4U */
+#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */
+#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */
+#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_DMA_Base_address TIMEx DMA BAse Address
+ * @{
+ */
+#define TIM_DMABASE_CR1 (0x00000000U)
+#define TIM_DMABASE_CR2 (0x00000001U)
+#define TIM_DMABASE_SMCR (0x00000002U)
+#define TIM_DMABASE_DIER (0x00000003U)
+#define TIM_DMABASE_SR (0x00000004U)
+#define TIM_DMABASE_EGR (0x00000005U)
+#define TIM_DMABASE_CCMR1 (0x00000006U)
+#define TIM_DMABASE_CCMR2 (0x00000007U)
+#define TIM_DMABASE_CCER (0x00000008U)
+#define TIM_DMABASE_CNT (0x00000009U)
+#define TIM_DMABASE_PSC (0x0000000AU)
+#define TIM_DMABASE_ARR (0x0000000BU)
+#define TIM_DMABASE_RCR (0x0000000CU)
+#define TIM_DMABASE_CCR1 (0x0000000DU)
+#define TIM_DMABASE_CCR2 (0x0000000EU)
+#define TIM_DMABASE_CCR3 (0x0000000FU)
+#define TIM_DMABASE_CCR4 (0x00000010U)
+#define TIM_DMABASE_BDTR (0x00000011U)
+#define TIM_DMABASE_DCR (0x00000012U)
+#define TIM_DMABASE_OR (0x00000013U)
+/**
+ * @}
+ */
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/** @defgroup TIMEx_Channel TIMEx Channel
+ * @{
+ */
+#define TIM_CHANNEL_1 (0x0000U)
+#define TIM_CHANNEL_2 (0x0004U)
+#define TIM_CHANNEL_3 (0x0008U)
+#define TIM_CHANNEL_4 (0x000CU)
+#define TIM_CHANNEL_5 (0x0010U)
+#define TIM_CHANNEL_6 (0x0014U)
+#define TIM_CHANNEL_ALL (0x003CU)
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Output_Compare_and_PWM_modes TIMEx Output Compare and PWM Modes
+ * @{
+ */
+#define TIM_OCMODE_TIMING (0x0000U)
+#define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0)
+#define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1)
+#define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
+#define TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
+#define TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
+#define TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
+#define TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2)
+
+#define TIM_OCMODE_RETRIGERRABLE_OPM1 ((uint32_t)TIM_CCMR1_OC1M_3)
+#define TIM_OCMODE_RETRIGERRABLE_OPM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)
+#define TIM_OCMODE_COMBINED_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)
+#define TIM_OCMODE_COMBINED_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
+#define TIM_OCMODE_ASSYMETRIC_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
+#define TIM_OCMODE_ASSYMETRIC_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_ClearInput_Source TIMEx Clear Input Source
+ * @{
+ */
+#define TIM_CLEARINPUTSOURCE_ETR (0x0001U)
+#define TIM_CLEARINPUTSOURCE_OCREFCLR (0x0002U)
+#define TIM_CLEARINPUTSOURCE_NONE (0x0000U)
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Break2_Input_enable_disable TIMEX Break input 2 Enable
+ * @{
+ */
+#define TIM_BREAK2_DISABLE (0x00000000U)
+#define TIM_BREAK2_ENABLE ((uint32_t)TIM_BDTR_BK2E)
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Break2_Polarity TIMEx Break Input 2 Polarity
+ * @{
+ */
+#define TIM_BREAK2POLARITY_LOW (0x00000000U)
+#define TIM_BREAK2POLARITY_HIGH ((uint32_t)TIM_BDTR_BK2P)
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Master_Mode_Selection_2 TIMEx Master Mode Selection 2 (TRGO2)
+ * @{
+ */
+#define TIM_TRGO2_RESET (0x00000000U)
+#define TIM_TRGO2_ENABLE ((uint32_t)(TIM_CR2_MMS2_0))
+#define TIM_TRGO2_UPDATE ((uint32_t)(TIM_CR2_MMS2_1))
+#define TIM_TRGO2_OC1 ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
+#define TIM_TRGO2_OC1REF ((uint32_t)(TIM_CR2_MMS2_2))
+#define TIM_TRGO2_OC2REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
+#define TIM_TRGO2_OC3REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1))
+#define TIM_TRGO2_OC4REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
+#define TIM_TRGO2_OC5REF ((uint32_t)(TIM_CR2_MMS2_3))
+#define TIM_TRGO2_OC6REF ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0))
+#define TIM_TRGO2_OC4REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1))
+#define TIM_TRGO2_OC6REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
+#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2))
+#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
+#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1))
+#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Slave_Mode TIMEx Slave mode
+ * @{
+ */
+#define TIM_SLAVEMODE_DISABLE (0x0000U)
+#define TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2))
+#define TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0))
+#define TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1))
+#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0))
+#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER ((uint32_t)(TIM_SMCR_SMS_3))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Event_Source TIMEx Event Source
+ * @{
+ */
+#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */
+#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1U */
+#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2U */
+#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3U */
+#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4U */
+#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */
+#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */
+#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */
+#define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_Base_address TIMEx DMA Base Address
+ * @{
+ */
+#define TIM_DMABASE_CR1 (0x00000000U)
+#define TIM_DMABASE_CR2 (0x00000001U)
+#define TIM_DMABASE_SMCR (0x00000002U)
+#define TIM_DMABASE_DIER (0x00000003U)
+#define TIM_DMABASE_SR (0x00000004U)
+#define TIM_DMABASE_EGR (0x00000005U)
+#define TIM_DMABASE_CCMR1 (0x00000006U)
+#define TIM_DMABASE_CCMR2 (0x00000007U)
+#define TIM_DMABASE_CCER (0x00000008U)
+#define TIM_DMABASE_CNT (0x00000009U)
+#define TIM_DMABASE_PSC (0x0000000AU)
+#define TIM_DMABASE_ARR (0x0000000BU)
+#define TIM_DMABASE_RCR (0x0000000CU)
+#define TIM_DMABASE_CCR1 (0x0000000DU)
+#define TIM_DMABASE_CCR2 (0x0000000EU)
+#define TIM_DMABASE_CCR3 (0x0000000FU)
+#define TIM_DMABASE_CCR4 (0x00000010U)
+#define TIM_DMABASE_BDTR (0x00000011U)
+#define TIM_DMABASE_DCR (0x00000012U)
+#define TIM_DMABASE_CCMR3 (0x00000015U)
+#define TIM_DMABASE_CCR5 (0x00000016U)
+#define TIM_DMABASE_CCR6 (0x00000017U)
+#define TIM_DMABASE_OR (0x00000018U)
+/**
+ * @}
+ */
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC) || \
+ defined(STM32F303x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/** @defgroup TIMEx_Remap TIMEx Remapping
+ * @{
+ */
+#define TIM_TIM1_ADC1_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
+#define TIM_TIM1_ADC1_AWD1 (0x00000001U) /*!< TIM1_ETR is connected to ADC1 AWD1 */
+#define TIM_TIM1_ADC1_AWD2 (0x00000002U) /*!< TIM1_ETR is connected to ADC1 AWD2 */
+#define TIM_TIM1_ADC1_AWD3 (0x00000003U) /*!< TIM1_ETR is connected to ADC1 AWD3 */
+#define TIM_TIM16_GPIO (0x00000000U) /*!< TIM16 TI1 is connected to GPIO */
+#define TIM_TIM16_RTC (0x00000001U) /*!< TIM16 TI1 is connected to RTC_clock */
+#define TIM_TIM16_HSE (0x00000002U) /*!< TIM16 TI1 is connected to HSE/32U */
+#define TIM_TIM16_MCO (0x00000003U) /*!< TIM16 TI1 is connected to MCO */
+/**
+ * @}
+ */
+#endif /* STM32F302xE || */
+ /* STM32F302xC || */
+ /* STM32F303x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
+
+
+#if defined(STM32F334x8)
+/** @defgroup TIMEx_Remap TIMEx Remapping 1
+ * @{
+ */
+#define TIM_TIM1_ADC1_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
+#define TIM_TIM1_ADC1_AWD1 (0x00000001U) /*!< TIM1_ETR is connected to ADC1 AWD1 */
+#define TIM_TIM1_ADC1_AWD2 (0x00000002U) /*!< TIM1_ETR is connected to ADC1 AWD2 */
+#define TIM_TIM1_ADC1_AWD3 (0x00000003U) /*!< TIM1_ETR is connected to ADC1 AWD3 */
+#define TIM_TIM16_GPIO (0x00000000U) /*!< TIM16 TI1 is connected to GPIO */
+#define TIM_TIM16_RTC (0x00000001U) /*!< TIM16 TI1 is connected to RTC_clock */
+#define TIM_TIM16_HSE (0x00000002U) /*!< TIM16 TI1 is connected to HSE/32U */
+#define TIM_TIM16_MCO (0x00000003U) /*!< TIM16 TI1 is connected to MCO */
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Remap2 TIMEx Remapping 2
+ * @{
+ */
+#define TIM_TIM1_ADC2_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
+#define TIM_TIM1_ADC2_AWD1 (0x00000004U) /*!< TIM1_ETR is connected to ADC2 AWD1 */
+#define TIM_TIM1_ADC2_AWD2 (0x00000008U) /*!< TIM1_ETR is connected to ADC2 AWD2 */
+#define TIM_TIM1_ADC2_AWD3 (0x0000000CU) /*!< TIM1_ETR is connected to ADC2 AWD3 */
+#define TIM_TIM16_NONE (0x00000000U) /*!< Non significant value for TIM16U */
+/**
+ * @}
+ */
+#endif /* STM32F334x8 */
+
+#if defined(STM32F303xC) || defined(STM32F358xx)
+/** @defgroup TIMEx_Remap TIMEx Remapping 1
+ * @{
+ */
+#define TIM_TIM1_ADC1_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
+#define TIM_TIM1_ADC1_AWD1 (0x00000001U) /*!< TIM1_ETR is connected to ADC1 AWD1 */
+#define TIM_TIM1_ADC1_AWD2 (0x00000002U) /*!< TIM1_ETR is connected to ADC1 AWD2 */
+#define TIM_TIM1_ADC1_AWD3 (0x00000003U) /*!< TIM1_ETR is connected to ADC1 AWD3 */
+#define TIM_TIM8_ADC2_NONE (0x00000000U) /*!< TIM8_ETR is not connected to any AWD (analog watchdog) */
+#define TIM_TIM8_ADC2_AWD1 (0x00000001U) /*!< TIM8_ETR is connected to ADC2 AWD1 */
+#define TIM_TIM8_ADC2_AWD2 (0x00000002U) /*!< TIM8_ETR is connected to ADC2 AWD2 */
+#define TIM_TIM8_ADC2_AWD3 (0x00000003U) /*!< TIM8_ETR is connected to ADC2 AWD3 */
+#define TIM_TIM16_GPIO (0x00000000U) /*!< TIM16 TI1 is connected to GPIO */
+#define TIM_TIM16_RTC (0x00000001U) /*!< TIM16 TI1 is connected to RTC_clock */
+#define TIM_TIM16_HSE (0x00000002U) /*!< TIM16 TI1 is connected to HSE/32U */
+#define TIM_TIM16_MCO (0x00000003U) /*!< TIM16 TI1 is connected to MCO */
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Remap2 TIMEx Remapping 2
+ * @{
+ */
+#define TIM_TIM1_ADC4_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
+#define TIM_TIM1_ADC4_AWD1 (0x00000004U) /*!< TIM1_ETR is connected to ADC4 AWD1 */
+#define TIM_TIM1_ADC4_AWD2 (0x00000008U) /*!< TIM1_ETR is connected to ADC4 AWD2 */
+#define TIM_TIM1_ADC4_AWD3 (0x0000000CU) /*!< TIM1_ETR is connected to ADC4 AWD3 */
+#define TIM_TIM8_ADC3_NONE (0x00000000U) /*!< TIM8_ETR is not connected to any AWD (analog watchdog) */
+#define TIM_TIM8_ADC3_AWD1 (0x00000004U) /*!< TIM8_ETR is connected to ADC3 AWD1 */
+#define TIM_TIM8_ADC3_AWD2 (0x00000008U) /*!< TIM8_ETR is connected to ADC3 AWD2 */
+#define TIM_TIM8_ADC3_AWD3 (0x0000000CU) /*!< TIM8_ETR is connected to ADC3 AWD3 */
+#define TIM_TIM16_NONE (0x00000000U) /*!< Non significant value for TIM16U */
+/**
+ * @}
+ */
+#endif /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)
+/** @defgroup TIMEx_Remap TIMEx Remapping 1
+ * @{
+ */
+#define TIM_TIM1_ADC1_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
+#define TIM_TIM1_ADC1_AWD1 (0x00000001U) /*!< TIM1_ETR is connected to ADC1 AWD1 */
+#define TIM_TIM1_ADC1_AWD2 (0x00000002U) /*!< TIM1_ETR is connected to ADC1 AWD2 */
+#define TIM_TIM1_ADC1_AWD3 (0x00000003U) /*!< TIM1_ETR is connected to ADC1 AWD3 */
+#define TIM_TIM8_ADC2_NONE (0x00000000U) /*!< TIM8_ETR is not connected to any AWD (analog watchdog) */
+#define TIM_TIM8_ADC2_AWD1 (0x00000001U) /*!< TIM8_ETR is connected to ADC2 AWD1 */
+#define TIM_TIM8_ADC2_AWD2 (0x00000002U) /*!< TIM8_ETR is connected to ADC2 AWD2 */
+#define TIM_TIM8_ADC2_AWD3 (0x00000003U) /*!< TIM8_ETR is connected to ADC2 AWD3 */
+#define TIM_TIM16_GPIO (0x00000000U) /*!< TIM16 TI1 is connected to GPIO */
+#define TIM_TIM16_RTC (0x00000001U) /*!< TIM16 TI1 is connected to RTC_clock */
+#define TIM_TIM16_HSE (0x00000002U) /*!< TIM16 TI1 is connected to HSE/32U */
+#define TIM_TIM16_MCO (0x00000003U) /*!< TIM16 TI1 is connected to MCO */
+#define TIM_TIM20_ADC3_NONE (0x00000000U) /*!< TIM20_ETR is not connected to any AWD (analog watchdog) */
+#define TIM_TIM20_ADC3_AWD1 (0x00000001U) /*!< TIM20_ETR is connected to ADC3 AWD1 */
+#define TIM_TIM20_ADC3_AWD2 (0x00000002U) /*!< TIM20_ETR is connected to ADC3 AWD2 */
+#define TIM_TIM20_ADC3_AWD3 (0x00000003U) /*!< TIM20_ETR is connected to ADC3 AWD3 */
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Remap2 TIMEx Remapping 2
+ * @{
+ */
+#define TIM_TIM1_ADC4_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
+#define TIM_TIM1_ADC4_AWD1 (0x00000004U) /*!< TIM1_ETR is connected to ADC4 AWD1 */
+#define TIM_TIM1_ADC4_AWD2 (0x00000008U) /*!< TIM1_ETR is connected to ADC4 AWD2 */
+#define TIM_TIM1_ADC4_AWD3 (0x0000000CU) /*!< TIM1_ETR is connected to ADC4 AWD3 */
+#define TIM_TIM8_ADC3_NONE (0x00000000U) /*!< TIM8_ETR is not connected to any AWD (analog watchdog) */
+#define TIM_TIM8_ADC3_AWD1 (0x00000004U) /*!< TIM8_ETR is connected to ADC3 AWD1 */
+#define TIM_TIM8_ADC3_AWD2 (0x00000008U) /*!< TIM8_ETR is connected to ADC3 AWD2 */
+#define TIM_TIM8_ADC3_AWD3 (0x0000000CU) /*!< TIM8_ETR is connected to ADC3 AWD3 */
+#define TIM_TIM16_NONE (0x00000000U) /*!< Non significant value for TIM16U */
+#define TIM_TIM20_ADC4_NONE (0x00000000U) /*!< TIM20_ETR is not connected to any AWD (analog watchdog) */
+#define TIM_TIM20_ADC4_AWD1 (0x00000004U) /*!< TIM20_ETR is connected to ADC4 AWD1 */
+#define TIM_TIM20_ADC4_AWD2 (0x00000008U) /*!< TIM20_ETR is connected to ADC4 AWD2 */
+#define TIM_TIM20_ADC4_AWD3 (0x0000000CU) /*!< TIM20_ETR is connected to ADC4 AWD3 */
+/**
+ * @}
+ */
+#endif /* STM32F303xE || STM32F398xx */
+
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/** @defgroup TIMEx_Remap TIMEx remapping
+ * @{
+ */
+#define TIM_TIM2_TIM8_TRGO (0x00000000U) /*!< TIM8 TRGOUT is connected to TIM2_ITR1 */
+#define TIM_TIM2_ETH_PTP (0x00000400U) /*!< PTP trigger output is connected to TIM2_ITR1 */
+#define TIM_TIM2_USBFS_SOF (0x00000800U) /*!< OTG FS SOF is connected to the TIM2_ITR1 input */
+#define TIM_TIM2_USBHS_SOF (0x00000C00U) /*!< OTG HS SOF is connected to the TIM2_ITR1 input */
+#define TIM_TIM14_GPIO (0x00000000U) /*!< TIM14 TI1 is connected to GPIO */
+#define TIM_TIM14_RTC (0x00000001U) /*!< TIM14 TI1 is connected to RTC_clock */
+#define TIM_TIM14_HSE (0x00000002U) /*!< TIM14 TI1 is connected to HSE/32U */
+#define TIM_TIM14_MCO (0x00000003U) /*!< TIM14 TI1 is connected to MCO */
+/**
+ * @}
+ */
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/** @defgroup TIMEx_Group_Channel5 Group Channel 5 and Channel 1U, 2 or 3
+ * @{
+ */
+#define TIM_GROUPCH5_NONE 0x00000000 /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
+#define TIM_GROUPCH5_OC1REFC (TIM_CCR5_GC5C1) /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
+#define TIM_GROUPCH5_OC2REFC (TIM_CCR5_GC5C2) /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
+#define TIM_GROUPCH5_OC3REFC (TIM_CCR5_GC5C3) /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
+/**
+ * @}
+ */
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+/**
+ * @}
+ */
+
+
+/* Private Macros -----------------------------------------------------------*/
+/** @defgroup TIM_Private_Macros TIM Private Macros
+ * @{
+ */
+#if defined(STM32F373xC) || defined(STM32F378xx)
+
+#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4) || \
+ ((CHANNEL) == TIM_CHANNEL_ALL))
+
+#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))
+
+#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))
+
+#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
+ ((MODE) == TIM_OCMODE_PWM2))
+
+#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
+ ((MODE) == TIM_OCMODE_ACTIVE) || \
+ ((MODE) == TIM_OCMODE_INACTIVE) || \
+ ((MODE) == TIM_OCMODE_TOGGLE) || \
+ ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
+ ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
+
+#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \
+ ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
+
+#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
+ ((MODE) == TIM_SLAVEMODE_RESET) || \
+ ((MODE) == TIM_SLAVEMODE_GATED) || \
+ ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
+ ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
+
+#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))
+
+#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \
+ ((BASE) == TIM_DMABASE_CR2) || \
+ ((BASE) == TIM_DMABASE_SMCR) || \
+ ((BASE) == TIM_DMABASE_DIER) || \
+ ((BASE) == TIM_DMABASE_SR) || \
+ ((BASE) == TIM_DMABASE_EGR) || \
+ ((BASE) == TIM_DMABASE_CCMR1) || \
+ ((BASE) == TIM_DMABASE_CCMR2) || \
+ ((BASE) == TIM_DMABASE_CCER) || \
+ ((BASE) == TIM_DMABASE_CNT) || \
+ ((BASE) == TIM_DMABASE_PSC) || \
+ ((BASE) == TIM_DMABASE_ARR) || \
+ ((BASE) == TIM_DMABASE_RCR) || \
+ ((BASE) == TIM_DMABASE_CCR1) || \
+ ((BASE) == TIM_DMABASE_CCR2) || \
+ ((BASE) == TIM_DMABASE_CCR3) || \
+ ((BASE) == TIM_DMABASE_CCR4) || \
+ ((BASE) == TIM_DMABASE_BDTR) || \
+ ((BASE) == TIM_DMABASE_DCR) || \
+ ((BASE) == TIM_DMABASE_OR))
+
+#endif /* STM32F373xC || STM32F378xx */
+
+
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+
+#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4) || \
+ ((CHANNEL) == TIM_CHANNEL_5) || \
+ ((CHANNEL) == TIM_CHANNEL_6) || \
+ ((CHANNEL) == TIM_CHANNEL_ALL))
+
+#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))
+
+#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))
+
+#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
+ ((MODE) == TIM_OCMODE_PWM2) || \
+ ((MODE) == TIM_OCMODE_COMBINED_PWM1) || \
+ ((MODE) == TIM_OCMODE_COMBINED_PWM2) || \
+ ((MODE) == TIM_OCMODE_ASSYMETRIC_PWM1) || \
+ ((MODE) == TIM_OCMODE_ASSYMETRIC_PWM2))
+
+#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
+ ((MODE) == TIM_OCMODE_ACTIVE) || \
+ ((MODE) == TIM_OCMODE_INACTIVE) || \
+ ((MODE) == TIM_OCMODE_TOGGLE) || \
+ ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
+ ((MODE) == TIM_OCMODE_FORCED_INACTIVE) || \
+ ((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
+ ((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM2))
+
+#define IS_TIM_CLEARINPUT_SOURCE(MODE) (((MODE) == TIM_CLEARINPUTSOURCE_ETR) || \
+ ((MODE) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \
+ ((MODE) == TIM_CLEARINPUTSOURCE_NONE))
+
+#define IS_TIM_BREAK_FILTER(BRKFILTER) ((BRKFILTER) <= 0xFU)
+
+#define IS_TIM_BREAK2_STATE(STATE) (((STATE) == TIM_BREAK2_ENABLE) || \
+ ((STATE) == TIM_BREAK2_DISABLE))
+
+#define IS_TIM_BREAK2_POLARITY(POLARITY) (((POLARITY) == TIM_BREAK2POLARITY_LOW) || \
+ ((POLARITY) == TIM_BREAK2POLARITY_HIGH))
+
+#define IS_TIM_TRGO2_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO2_RESET) || \
+ ((SOURCE) == TIM_TRGO2_ENABLE) || \
+ ((SOURCE) == TIM_TRGO2_UPDATE) || \
+ ((SOURCE) == TIM_TRGO2_OC1) || \
+ ((SOURCE) == TIM_TRGO2_OC1REF) || \
+ ((SOURCE) == TIM_TRGO2_OC2REF) || \
+ ((SOURCE) == TIM_TRGO2_OC3REF) || \
+ ((SOURCE) == TIM_TRGO2_OC3REF) || \
+ ((SOURCE) == TIM_TRGO2_OC4REF) || \
+ ((SOURCE) == TIM_TRGO2_OC5REF) || \
+ ((SOURCE) == TIM_TRGO2_OC6REF) || \
+ ((SOURCE) == TIM_TRGO2_OC4REF_RISINGFALLING) || \
+ ((SOURCE) == TIM_TRGO2_OC6REF_RISINGFALLING) || \
+ ((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \
+ ((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
+ ((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \
+ ((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
+
+#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
+ ((MODE) == TIM_SLAVEMODE_RESET) || \
+ ((MODE) == TIM_SLAVEMODE_GATED) || \
+ ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
+ ((MODE) == TIM_SLAVEMODE_EXTERNAL1) || \
+ ((MODE) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
+
+#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFE00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))
+
+#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \
+ ((BASE) == TIM_DMABASE_CR2) || \
+ ((BASE) == TIM_DMABASE_SMCR) || \
+ ((BASE) == TIM_DMABASE_DIER) || \
+ ((BASE) == TIM_DMABASE_SR) || \
+ ((BASE) == TIM_DMABASE_EGR) || \
+ ((BASE) == TIM_DMABASE_CCMR1) || \
+ ((BASE) == TIM_DMABASE_CCMR2) || \
+ ((BASE) == TIM_DMABASE_CCER) || \
+ ((BASE) == TIM_DMABASE_CNT) || \
+ ((BASE) == TIM_DMABASE_PSC) || \
+ ((BASE) == TIM_DMABASE_ARR) || \
+ ((BASE) == TIM_DMABASE_RCR) || \
+ ((BASE) == TIM_DMABASE_CCR1) || \
+ ((BASE) == TIM_DMABASE_CCR2) || \
+ ((BASE) == TIM_DMABASE_CCR3) || \
+ ((BASE) == TIM_DMABASE_CCR4) || \
+ ((BASE) == TIM_DMABASE_BDTR) || \
+ ((BASE) == TIM_DMABASE_CCMR3) || \
+ ((BASE) == TIM_DMABASE_CCR5) || \
+ ((BASE) == TIM_DMABASE_CCR6) || \
+ ((BASE) == TIM_DMABASE_OR))
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC) || \
+ defined(STM32F303x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+
+#define IS_TIM_REMAP(REMAP) (((REMAP) == TIM_TIM1_ADC1_NONE) ||\
+ ((REMAP) == TIM_TIM1_ADC1_AWD1) ||\
+ ((REMAP) == TIM_TIM1_ADC1_AWD2) ||\
+ ((REMAP) == TIM_TIM1_ADC1_AWD3) ||\
+ ((REMAP) == TIM_TIM16_GPIO) ||\
+ ((REMAP) == TIM_TIM16_RTC) ||\
+ ((REMAP) == TIM_TIM16_HSE) ||\
+ ((REMAP) == TIM_TIM16_MCO))
+
+#endif /* STM32F302xE || */
+ /* STM32F302xC || */
+ /* STM32F303x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
+
+#if defined(STM32F334x8)
+#define IS_TIM_REMAP(REMAP1) (((REMAP1) == TIM_TIM1_ADC1_NONE) ||\
+ ((REMAP1) == TIM_TIM1_ADC1_AWD1) ||\
+ ((REMAP1) == TIM_TIM1_ADC1_AWD2) ||\
+ ((REMAP1) == TIM_TIM1_ADC1_AWD3) ||\
+ ((REMAP1) == TIM_TIM16_GPIO) ||\
+ ((REMAP1) == TIM_TIM16_RTC) ||\
+ ((REMAP1) == TIM_TIM16_HSE) ||\
+ ((REMAP1) == TIM_TIM16_MCO))
+
+#define IS_TIM_REMAP2(REMAP2) (((REMAP2) == TIM_TIM1_ADC2_NONE) ||\
+ ((REMAP2) == TIM_TIM1_ADC2_AWD1) ||\
+ ((REMAP2) == TIM_TIM1_ADC2_AWD2) ||\
+ ((REMAP2) == TIM_TIM1_ADC2_AWD3) ||\
+ ((REMAP2) == TIM_TIM16_NONE))
+
+#endif /* STM32F334x8 */
+
+#if defined(STM32F303xC) || defined(STM32F358xx)
+
+#define IS_TIM_REMAP(REMAP1) (((REMAP1) == TIM_TIM1_ADC1_NONE) ||\
+ ((REMAP1) == TIM_TIM1_ADC1_AWD1) ||\
+ ((REMAP1) == TIM_TIM1_ADC1_AWD2) ||\
+ ((REMAP1) == TIM_TIM1_ADC1_AWD3) ||\
+ ((REMAP1) == TIM_TIM8_ADC2_NONE) ||\
+ ((REMAP1) == TIM_TIM8_ADC2_AWD1) ||\
+ ((REMAP1) == TIM_TIM8_ADC2_AWD2) ||\
+ ((REMAP1) == TIM_TIM8_ADC2_AWD3) ||\
+ ((REMAP1) == TIM_TIM16_GPIO) ||\
+ ((REMAP1) == TIM_TIM16_RTC) ||\
+ ((REMAP1) == TIM_TIM16_HSE) ||\
+ ((REMAP1) == TIM_TIM16_MCO))
+
+#define IS_TIM_REMAP2(REMAP2) (((REMAP2) == TIM_TIM1_ADC4_NONE) ||\
+ ((REMAP2) == TIM_TIM1_ADC4_AWD1) ||\
+ ((REMAP2) == TIM_TIM1_ADC4_AWD2) ||\
+ ((REMAP2) == TIM_TIM1_ADC4_AWD3) ||\
+ ((REMAP2) == TIM_TIM8_ADC3_NONE) ||\
+ ((REMAP2) == TIM_TIM8_ADC3_AWD1) ||\
+ ((REMAP2) == TIM_TIM8_ADC3_AWD2) ||\
+ ((REMAP2) == TIM_TIM8_ADC3_AWD3) ||\
+ ((REMAP2) == TIM_TIM16_NONE))
+
+#endif /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)
+
+#define IS_TIM_REMAP(REMAP1) (((REMAP1) == TIM_TIM1_ADC1_NONE) ||\
+ ((REMAP1) == TIM_TIM1_ADC1_AWD1) ||\
+ ((REMAP1) == TIM_TIM1_ADC1_AWD2) ||\
+ ((REMAP1) == TIM_TIM1_ADC1_AWD3) ||\
+ ((REMAP1) == TIM_TIM8_ADC2_NONE) ||\
+ ((REMAP1) == TIM_TIM8_ADC2_AWD1) ||\
+ ((REMAP1) == TIM_TIM8_ADC2_AWD2) ||\
+ ((REMAP1) == TIM_TIM8_ADC2_AWD3) ||\
+ ((REMAP1) == TIM_TIM16_GPIO) ||\
+ ((REMAP1) == TIM_TIM16_RTC) ||\
+ ((REMAP1) == TIM_TIM16_HSE) ||\
+ ((REMAP1) == TIM_TIM16_MCO) ||\
+ ((REMAP1) == TIM_TIM20_ADC3_NONE) ||\
+ ((REMAP1) == TIM_TIM20_ADC3_AWD1) ||\
+ ((REMAP1) == TIM_TIM20_ADC3_AWD2) ||\
+ ((REMAP1) == TIM_TIM20_ADC3_AWD3))
+
+#define IS_TIM_REMAP2(REMAP2) (((REMAP2) == TIM_TIM1_ADC4_NONE) ||\
+ ((REMAP2) == TIM_TIM1_ADC4_AWD1) ||\
+ ((REMAP2) == TIM_TIM1_ADC4_AWD2) ||\
+ ((REMAP2) == TIM_TIM1_ADC4_AWD3) ||\
+ ((REMAP2) == TIM_TIM8_ADC3_NONE) ||\
+ ((REMAP2) == TIM_TIM8_ADC3_AWD1) ||\
+ ((REMAP2) == TIM_TIM8_ADC3_AWD2) ||\
+ ((REMAP2) == TIM_TIM8_ADC3_AWD3) ||\
+ ((REMAP2) == TIM_TIM16_NONE) ||\
+ ((REMAP2) == TIM_TIM20_ADC4_NONE) ||\
+ ((REMAP2) == TIM_TIM20_ADC4_AWD1) ||\
+ ((REMAP2) == TIM_TIM20_ADC4_AWD2) ||\
+ ((REMAP2) == TIM_TIM20_ADC4_AWD3))
+
+#endif /* STM32F303xE || STM32F398xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+
+#define IS_TIM_REMAP(REMAP) (((REMAP) == TIM_TIM2_TIM8_TRGO) ||\
+ ((REMAP) == TIM_TIM2_ETH_PTP) ||\
+ ((REMAP) == TIM_TIM2_USBFS_SOF) ||\
+ ((REMAP) == TIM_TIM2_USBHS_SOF) ||\
+ ((REMAP) == TIM_TIM14_GPIO) ||\
+ ((REMAP) == TIM_TIM14_RTC) ||\
+ ((REMAP) == TIM_TIM14_HSE) ||\
+ ((REMAP) == TIM_TIM14_MCO))
+
+#endif /* STM32F373xC || STM32F378xx */
+
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+
+#define IS_TIM_GROUPCH5(OCREF) ((((OCREF) & 0x1FFFFFFFU) == 0x00000000U))
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#define IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFFU)
+
+/**
+ * @}
+ */
+/* End of private macros -----------------------------------------------------*/
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Macros TIMEx Exported Macros
+ * @{
+ */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Sets the TIM Capture Compare Register value on runtime without
+ * calling another time ConfigChannel function.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param __COMPARE__ specifies the Capture Compare register new value.
+ * @retval None
+ */
+#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
+(*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__))
+
+/**
+ * @brief Gets the TIM Capture Compare Register value on runtime
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channel associated with the capture compare register
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: get capture/compare 1 register value
+ * @arg TIM_CHANNEL_2: get capture/compare 2 register value
+ * @arg TIM_CHANNEL_3: get capture/compare 3 register value
+ * @arg TIM_CHANNEL_4: get capture/compare 4 register value
+ * @retval None
+ */
+#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
+ (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))
+
+/**
+ * @brief Sets the TIM Output compare preload.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval None
+ */
+#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
+ ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))
+
+/**
+ * @brief Resets the TIM Output compare preload.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval None
+ */
+#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\
+ ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE))
+
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Sets the TIM Capture Compare Register value on runtime without
+ * calling another time ConfigChannel function.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @param __COMPARE__ specifies the Capture Compare register new value.
+ * @retval None
+ */
+#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
+ ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
+
+/**
+ * @brief Gets the TIM Capture Compare Register value on runtime
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channel associated with the capture compare register
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: get capture/compare 1 register value
+ * @arg TIM_CHANNEL_2: get capture/compare 2 register value
+ * @arg TIM_CHANNEL_3: get capture/compare 3 register value
+ * @arg TIM_CHANNEL_4: get capture/compare 4 register value
+ * @arg TIM_CHANNEL_5: get capture/compare 5 register value
+ * @arg TIM_CHANNEL_6: get capture/compare 6 register value
+ * @retval None
+ */
+#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
+ ((__HANDLE__)->Instance->CCR6))
+
+/**
+ * @brief Sets the TIM Output compare preload.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @retval None
+ */
+#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\
+ ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))
+
+/**
+ * @brief Resets the TIM Output compare preload.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @retval None
+ */
+#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC5PE) :\
+ ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC6PE))
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIMEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group1
+ * @{
+ */
+/* Timer Hall Sensor functions **********************************************/
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
+
+void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
+
+ /* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group2
+ * @{
+ */
+/* Timer Complementary Output Compare functions *****************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group3
+ * @{
+ */
+/* Timer Complementary PWM functions ****************************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group4
+ * @{
+ */
+/* Timer Complementary One Pulse functions **********************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group5
+ * @{
+ */
+/* Extended Control functions ************************************************/
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig);
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F334x8)
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap1, uint32_t Remap2);
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC) || \
+ defined(STM32F303x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
+#endif /* STM32F302xE || */
+ /* STM32F302xC || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
+ /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group6
+ * @{
+ */
+/* Extended Callback *********************************************************/
+void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group7
+ * @{
+ */
+/* Extended Peripheral State functions **************************************/
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* End of exported functions -------------------------------------------------*/
+
+/* Private functions----------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
+ * @{
+ */
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+/* End of private functions --------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F3xx_HAL_TIM_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_hal_tsc.h b/Inc/stm32f3xx_hal_tsc.h
new file mode 100644
index 0000000..2649760
--- /dev/null
+++ b/Inc/stm32f3xx_hal_tsc.h
@@ -0,0 +1,724 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_tsc.h
+ * @author MCD Application Team
+ * @brief Header file of TSC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_TSC_H
+#define __STM32F3xx_HAL_TSC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup TSC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup TSC_Exported_Types TSC Exported Types
+ * @{
+ */
+
+/**
+ * @brief TSC state structure definition
+ */
+typedef enum
+{
+ HAL_TSC_STATE_RESET = 0x00U, /*!< TSC registers have their reset value */
+ HAL_TSC_STATE_READY = 0x01U, /*!< TSC registers are initialized or acquisition is completed with success */
+ HAL_TSC_STATE_BUSY = 0x02U, /*!< TSC initialization or acquisition is on-going */
+ HAL_TSC_STATE_ERROR = 0x03U /*!< Acquisition is completed with max count error */
+} HAL_TSC_StateTypeDef;
+
+/**
+ * @brief TSC group status structure definition
+ */
+typedef enum
+{
+ TSC_GROUP_ONGOING = 0x00U, /*!< Acquisition on group is on-going or not started */
+ TSC_GROUP_COMPLETED = 0x01U /*!< Acquisition on group is completed with success (no max count error) */
+} TSC_GroupStatusTypeDef;
+
+/**
+ * @brief TSC init structure definition
+ */
+typedef struct
+{
+ uint32_t CTPulseHighLength; /*!< Charge-transfer high pulse length
+ This parameter can be a value of @ref TSC_CTPulseHL_Config */
+ uint32_t CTPulseLowLength; /*!< Charge-transfer low pulse length
+ This parameter can be a value of @ref TSC_CTPulseLL_Config */
+ uint32_t SpreadSpectrum; /*!< Spread spectrum activation
+ This parameter can be a value of @ref TSC_CTPulseLL_Config */
+ uint32_t SpreadSpectrumDeviation; /*!< Spread spectrum deviation
+ This parameter must be a number between Min_Data = 0 and Max_Data = 127U */
+ uint32_t SpreadSpectrumPrescaler; /*!< Spread spectrum prescaler
+ This parameter can be a value of @ref TSC_SpreadSpec_Prescaler */
+ uint32_t PulseGeneratorPrescaler; /*!< Pulse generator prescaler
+ This parameter can be a value of @ref TSC_PulseGenerator_Prescaler */
+ uint32_t MaxCountValue; /*!< Max count value
+ This parameter can be a value of @ref TSC_MaxCount_Value */
+ uint32_t IODefaultMode; /*!< IO default mode
+ This parameter can be a value of @ref TSC_IO_Default_Mode */
+ uint32_t SynchroPinPolarity; /*!< Synchro pin polarity
+ This parameter can be a value of @ref TSC_Synchro_Pin_Polarity */
+ uint32_t AcquisitionMode; /*!< Acquisition mode
+ This parameter can be a value of @ref TSC_Acquisition_Mode */
+ uint32_t MaxCountInterrupt; /*!< Max count interrupt activation
+ This parameter can be set to ENABLE or DISABLE. */
+ uint32_t ChannelIOs; /*!< Channel IOs mask */
+ uint32_t ShieldIOs; /*!< Shield IOs mask */
+ uint32_t SamplingIOs; /*!< Sampling IOs mask */
+} TSC_InitTypeDef;
+
+/**
+ * @brief TSC IOs configuration structure definition
+ */
+typedef struct
+{
+ uint32_t ChannelIOs; /*!< Channel IOs mask */
+ uint32_t ShieldIOs; /*!< Shield IOs mask */
+ uint32_t SamplingIOs; /*!< Sampling IOs mask */
+} TSC_IOConfigTypeDef;
+
+/**
+ * @brief TSC handle Structure definition
+ */
+typedef struct
+{
+ TSC_TypeDef *Instance; /*!< Register base address */
+ TSC_InitTypeDef Init; /*!< Initialization parameters */
+ __IO HAL_TSC_StateTypeDef State; /*!< Peripheral state */
+ HAL_LockTypeDef Lock; /*!< Lock feature */
+} TSC_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TSC_Exported_Constants TSC Exported Constants
+ * @{
+ */
+
+/** @defgroup TSC_CTPulseHL_Config CTPulse High Length
+ * @{
+ */
+#define TSC_CTPH_1CYCLE ((uint32_t)( 0U << 28U))
+#define TSC_CTPH_2CYCLES ((uint32_t)( 1U << 28U))
+#define TSC_CTPH_3CYCLES ((uint32_t)( 2U << 28U))
+#define TSC_CTPH_4CYCLES ((uint32_t)( 3U << 28U))
+#define TSC_CTPH_5CYCLES ((uint32_t)( 4U << 28U))
+#define TSC_CTPH_6CYCLES ((uint32_t)( 5U << 28U))
+#define TSC_CTPH_7CYCLES ((uint32_t)( 6U << 28U))
+#define TSC_CTPH_8CYCLES ((uint32_t)( 7U << 28U))
+#define TSC_CTPH_9CYCLES ((uint32_t)( 8U << 28U))
+#define TSC_CTPH_10CYCLES ((uint32_t)( 9U << 28U))
+#define TSC_CTPH_11CYCLES ((uint32_t)(10U << 28U))
+#define TSC_CTPH_12CYCLES ((uint32_t)(11U << 28U))
+#define TSC_CTPH_13CYCLES ((uint32_t)(12U << 28U))
+#define TSC_CTPH_14CYCLES ((uint32_t)(13U << 28U))
+#define TSC_CTPH_15CYCLES ((uint32_t)(14U << 28U))
+#define TSC_CTPH_16CYCLES ((uint32_t)(15U << 28U))
+/**
+ * @}
+ */
+
+/** @defgroup TSC_CTPulseLL_Config CTPulse Low Length
+ * @{
+ */
+#define TSC_CTPL_1CYCLE ((uint32_t)( 0U << 24U))
+#define TSC_CTPL_2CYCLES ((uint32_t)( 1U << 24U))
+#define TSC_CTPL_3CYCLES ((uint32_t)( 2U << 24U))
+#define TSC_CTPL_4CYCLES ((uint32_t)( 3U << 24U))
+#define TSC_CTPL_5CYCLES ((uint32_t)( 4U << 24U))
+#define TSC_CTPL_6CYCLES ((uint32_t)( 5U << 24U))
+#define TSC_CTPL_7CYCLES ((uint32_t)( 6U << 24U))
+#define TSC_CTPL_8CYCLES ((uint32_t)( 7U << 24U))
+#define TSC_CTPL_9CYCLES ((uint32_t)( 8U << 24U))
+#define TSC_CTPL_10CYCLES ((uint32_t)( 9U << 24U))
+#define TSC_CTPL_11CYCLES ((uint32_t)(10U << 24U))
+#define TSC_CTPL_12CYCLES ((uint32_t)(11U << 24U))
+#define TSC_CTPL_13CYCLES ((uint32_t)(12U << 24U))
+#define TSC_CTPL_14CYCLES ((uint32_t)(13U << 24U))
+#define TSC_CTPL_15CYCLES ((uint32_t)(14U << 24U))
+#define TSC_CTPL_16CYCLES ((uint32_t)(15U << 24U))
+/**
+ * @}
+ */
+
+/** @defgroup TSC_SpreadSpec_Prescaler Spread Spectrum Prescaler
+ * @{
+ */
+#define TSC_SS_PRESC_DIV1 (0U)
+#define TSC_SS_PRESC_DIV2 (TSC_CR_SSPSC)
+/**
+ * @}
+ */
+
+/** @defgroup TSC_PulseGenerator_Prescaler Pulse Generator Prescaler
+ * @{
+ */
+#define TSC_PG_PRESC_DIV1 ((uint32_t)(0U << 12U))
+#define TSC_PG_PRESC_DIV2 ((uint32_t)(1U << 12U))
+#define TSC_PG_PRESC_DIV4 ((uint32_t)(2U << 12U))
+#define TSC_PG_PRESC_DIV8 ((uint32_t)(3U << 12U))
+#define TSC_PG_PRESC_DIV16 ((uint32_t)(4U << 12U))
+#define TSC_PG_PRESC_DIV32 ((uint32_t)(5U << 12U))
+#define TSC_PG_PRESC_DIV64 ((uint32_t)(6U << 12U))
+#define TSC_PG_PRESC_DIV128 ((uint32_t)(7U << 12U))
+/**
+ * @}
+ */
+
+/** @defgroup TSC_MaxCount_Value Max Count Value
+ * @{
+ */
+#define TSC_MCV_255 ((uint32_t)(0U << 5U))
+#define TSC_MCV_511 ((uint32_t)(1U << 5U))
+#define TSC_MCV_1023 ((uint32_t)(2U << 5U))
+#define TSC_MCV_2047 ((uint32_t)(3U << 5U))
+#define TSC_MCV_4095 ((uint32_t)(4U << 5U))
+#define TSC_MCV_8191 ((uint32_t)(5U << 5U))
+#define TSC_MCV_16383 ((uint32_t)(6U << 5U))
+/**
+ * @}
+ */
+
+/** @defgroup TSC_IO_Default_Mode IO Default Mode
+ * @{
+ */
+#define TSC_IODEF_OUT_PP_LOW (0U)
+#define TSC_IODEF_IN_FLOAT (TSC_CR_IODEF)
+/**
+ * @}
+ */
+
+/** @defgroup TSC_Synchro_Pin_Polarity Synchro Pin Polarity
+ * @{
+ */
+#define TSC_SYNC_POLARITY_FALLING (0U)
+#define TSC_SYNC_POLARITY_RISING (TSC_CR_SYNCPOL)
+/**
+ * @}
+ */
+
+/** @defgroup TSC_Acquisition_Mode Acquisition Mode
+ * @{
+ */
+#define TSC_ACQ_MODE_NORMAL (0U)
+#define TSC_ACQ_MODE_SYNCHRO (TSC_CR_AM)
+/**
+ * @}
+ */
+
+/** @defgroup TSC_IO_Mode IO Mode
+ * @{
+ */
+#define TSC_IOMODE_UNUSED (0U)
+#define TSC_IOMODE_CHANNEL (1U)
+#define TSC_IOMODE_SHIELD (2U)
+#define TSC_IOMODE_SAMPLING (3U)
+/**
+ * @}
+ */
+
+/** @defgroup TSC_interrupts_definition Interrupts definition
+ * @{
+ */
+#define TSC_IT_EOA ((uint32_t)TSC_IER_EOAIE)
+#define TSC_IT_MCE ((uint32_t)TSC_IER_MCEIE)
+/**
+ * @}
+ */
+
+/** @defgroup TSC_flags_definition Flags definition
+ * @{
+ */
+#define TSC_FLAG_EOA ((uint32_t)TSC_ISR_EOAF)
+#define TSC_FLAG_MCE ((uint32_t)TSC_ISR_MCEF)
+/**
+ * @}
+ */
+
+/** @defgroup TSC_Group_definition Group definition
+ * @{
+ */
+#define TSC_NB_OF_GROUPS (8U)
+
+#define TSC_GROUP1 (0x00000001U)
+#define TSC_GROUP2 (0x00000002U)
+#define TSC_GROUP3 (0x00000004U)
+#define TSC_GROUP4 (0x00000008U)
+#define TSC_GROUP5 (0x00000010U)
+#define TSC_GROUP6 (0x00000020U)
+#define TSC_GROUP7 (0x00000040U)
+#define TSC_GROUP8 (0x00000080U)
+#define TSC_ALL_GROUPS (0x000000FFU)
+
+#define TSC_GROUP1_IDX (0U)
+#define TSC_GROUP2_IDX (1U)
+#define TSC_GROUP3_IDX (2U)
+#define TSC_GROUP4_IDX (3U)
+#define TSC_GROUP5_IDX (4U)
+#define TSC_GROUP6_IDX (5U)
+#define TSC_GROUP7_IDX (6U)
+#define TSC_GROUP8_IDX (7U)
+
+#define TSC_GROUP1_IO1 (0x00000001U)
+#define TSC_GROUP1_IO2 (0x00000002U)
+#define TSC_GROUP1_IO3 (0x00000004U)
+#define TSC_GROUP1_IO4 (0x00000008U)
+#define TSC_GROUP1_ALL_IOS (0x0000000FU)
+
+#define TSC_GROUP2_IO1 (0x00000010U)
+#define TSC_GROUP2_IO2 (0x00000020U)
+#define TSC_GROUP2_IO3 (0x00000040U)
+#define TSC_GROUP2_IO4 (0x00000080U)
+#define TSC_GROUP2_ALL_IOS (0x000000F0U)
+
+#define TSC_GROUP3_IO1 (0x00000100U)
+#define TSC_GROUP3_IO2 (0x00000200U)
+#define TSC_GROUP3_IO3 (0x00000400U)
+#define TSC_GROUP3_IO4 (0x00000800U)
+#define TSC_GROUP3_ALL_IOS (0x00000F00U)
+
+#define TSC_GROUP4_IO1 (0x00001000U)
+#define TSC_GROUP4_IO2 (0x00002000U)
+#define TSC_GROUP4_IO3 (0x00004000U)
+#define TSC_GROUP4_IO4 (0x00008000U)
+#define TSC_GROUP4_ALL_IOS (0x0000F000U)
+
+#define TSC_GROUP5_IO1 (0x00010000U)
+#define TSC_GROUP5_IO2 (0x00020000U)
+#define TSC_GROUP5_IO3 (0x00040000U)
+#define TSC_GROUP5_IO4 (0x00080000U)
+#define TSC_GROUP5_ALL_IOS (0x000F0000U)
+
+#define TSC_GROUP6_IO1 (0x00100000U)
+#define TSC_GROUP6_IO2 (0x00200000U)
+#define TSC_GROUP6_IO3 (0x00400000U)
+#define TSC_GROUP6_IO4 (0x00800000U)
+#define TSC_GROUP6_ALL_IOS (0x00F00000U)
+
+#define TSC_GROUP7_IO1 (0x01000000U)
+#define TSC_GROUP7_IO2 (0x02000000U)
+#define TSC_GROUP7_IO3 (0x04000000U)
+#define TSC_GROUP7_IO4 (0x08000000U)
+#define TSC_GROUP7_ALL_IOS (0x0F000000U)
+
+#define TSC_GROUP8_IO1 (0x10000000U)
+#define TSC_GROUP8_IO2 (0x20000000U)
+#define TSC_GROUP8_IO3 (0x40000000U)
+#define TSC_GROUP8_IO4 (0x80000000U)
+#define TSC_GROUP8_ALL_IOS (0xF0000000U)
+
+#define TSC_ALL_GROUPS_ALL_IOS (0xFFFFFFFFU)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup TSC_Exported_Macros TSC Exported Macros
+ * @{
+ */
+
+/** @brief Reset TSC handle state.
+ * @param __HANDLE__ TSC handle
+ * @retval None
+ */
+#define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET)
+
+/**
+ * @brief Enable the TSC peripheral.
+ * @param __HANDLE__ TSC handle
+ * @retval None
+ */
+#define __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE)
+
+/**
+ * @brief Disable the TSC peripheral.
+ * @param __HANDLE__ TSC handle
+ * @retval None
+ */
+#define __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_TSCE))
+
+/**
+ * @brief Start acquisition.
+ * @param __HANDLE__ TSC handle
+ * @retval None
+ */
+#define __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START)
+
+/**
+ * @brief Stop acquisition.
+ * @param __HANDLE__ TSC handle
+ * @retval None
+ */
+#define __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_START))
+
+/**
+ * @brief Set IO default mode to output push-pull low.
+ * @param __HANDLE__ TSC handle
+ * @retval None
+ */
+#define __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_IODEF))
+
+/**
+ * @brief Set IO default mode to input floating.
+ * @param __HANDLE__ TSC handle
+ * @retval None
+ */
+#define __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF)
+
+/**
+ * @brief Set synchronization polarity to falling edge.
+ * @param __HANDLE__ TSC handle
+ * @retval None
+ */
+#define __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_SYNCPOL))
+
+/**
+ * @brief Set synchronization polarity to rising edge and high level.
+ * @param __HANDLE__ TSC handle
+ * @retval None
+ */
+#define __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL)
+
+/**
+ * @brief Enable TSC interrupt.
+ * @param __HANDLE__ TSC handle
+ * @param __INTERRUPT__ TSC interrupt
+ * @retval None
+ */
+#define __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
+
+/**
+ * @brief Disable TSC interrupt.
+ * @param __HANDLE__ TSC handle
+ * @param __INTERRUPT__ TSC interrupt
+ * @retval None
+ */
+#define __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (uint32_t)(~(__INTERRUPT__)))
+
+/** @brief Check whether the specified TSC interrupt source is enabled or not.
+ * @param __HANDLE__ TSC Handle
+ * @param __INTERRUPT__ TSC interrupt
+ * @retval SET or RESET
+ */
+#define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/**
+ * @brief Check whether the specified TSC flag is set or not.
+ * @param __HANDLE__ TSC handle
+ * @param __FLAG__ TSC flag
+ * @retval SET or RESET
+ */
+#define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+
+/**
+ * @brief Clear the TSC's pending flag.
+ * @param __HANDLE__ TSC handle
+ * @param __FLAG__ TSC flag
+ * @retval None
+ */
+#define __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/**
+ * @brief Enable schmitt trigger hysteresis on a group of IOs.
+ * @param __HANDLE__ TSC handle
+ * @param __GX_IOY_MASK__ IOs mask
+ * @retval None
+ */
+#define __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__))
+
+/**
+ * @brief Disable schmitt trigger hysteresis on a group of IOs.
+ * @param __HANDLE__ TSC handle
+ * @param __GX_IOY_MASK__ IOs mask
+ * @retval None
+ */
+#define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR &= (uint32_t)(~(__GX_IOY_MASK__)))
+
+/**
+ * @brief Open analog switch on a group of IOs.
+ * @param __HANDLE__ TSC handle
+ * @param __GX_IOY_MASK__ IOs mask
+ * @retval None
+ */
+#define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR &= (uint32_t)(~(__GX_IOY_MASK__)))
+
+/**
+ * @brief Close analog switch on a group of IOs.
+ * @param __HANDLE__ TSC handle
+ * @param __GX_IOY_MASK__ IOs mask
+ * @retval None
+ */
+#define __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__))
+
+/**
+ * @brief Enable a group of IOs in channel mode.
+ * @param __HANDLE__ TSC handle
+ * @param __GX_IOY_MASK__ IOs mask
+ * @retval None
+ */
+#define __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__))
+
+/**
+ * @brief Disable a group of channel IOs.
+ * @param __HANDLE__ TSC handle
+ * @param __GX_IOY_MASK__ IOs mask
+ * @retval None
+ */
+#define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR &= (uint32_t)(~(__GX_IOY_MASK__)))
+
+/**
+ * @brief Enable a group of IOs in sampling mode.
+ * @param __HANDLE__ TSC handle
+ * @param __GX_IOY_MASK__ IOs mask
+ * @retval None
+ */
+#define __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__))
+
+/**
+ * @brief Disable a group of sampling IOs.
+ * @param __HANDLE__ TSC handle
+ * @param __GX_IOY_MASK__ IOs mask
+ * @retval None
+ */
+#define __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (uint32_t)(~(__GX_IOY_MASK__)))
+
+/**
+ * @brief Enable acquisition groups.
+ * @param __HANDLE__ TSC handle
+ * @param __GX_MASK__ Groups mask
+ * @retval None
+ */
+#define __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__))
+
+/**
+ * @brief Disable acquisition groups.
+ * @param __HANDLE__ TSC handle
+ * @param __GX_MASK__ Groups mask
+ * @retval None
+ */
+#define __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (uint32_t)(~(__GX_MASK__)))
+
+/** @brief Gets acquisition group status.
+ * @param __HANDLE__ TSC Handle
+ * @param __GX_INDEX__ Group index
+ * @retval SET or RESET
+ */
+#define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \
+((((__HANDLE__)->Instance->IOGCSR & (uint32_t)((uint32_t)1U << ((__GX_INDEX__) + (uint32_t)16U))) == (uint32_t)((uint32_t)1U << ((__GX_INDEX__) + (uint32_t)16U))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING)
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @defgroup TSC_Private_Macros TSC Private Macros
+ * @{
+ */
+
+#define IS_TSC_CTPH(VAL) (((VAL) == TSC_CTPH_1CYCLE) || \
+ ((VAL) == TSC_CTPH_2CYCLES) || \
+ ((VAL) == TSC_CTPH_3CYCLES) || \
+ ((VAL) == TSC_CTPH_4CYCLES) || \
+ ((VAL) == TSC_CTPH_5CYCLES) || \
+ ((VAL) == TSC_CTPH_6CYCLES) || \
+ ((VAL) == TSC_CTPH_7CYCLES) || \
+ ((VAL) == TSC_CTPH_8CYCLES) || \
+ ((VAL) == TSC_CTPH_9CYCLES) || \
+ ((VAL) == TSC_CTPH_10CYCLES) || \
+ ((VAL) == TSC_CTPH_11CYCLES) || \
+ ((VAL) == TSC_CTPH_12CYCLES) || \
+ ((VAL) == TSC_CTPH_13CYCLES) || \
+ ((VAL) == TSC_CTPH_14CYCLES) || \
+ ((VAL) == TSC_CTPH_15CYCLES) || \
+ ((VAL) == TSC_CTPH_16CYCLES))
+
+#define IS_TSC_CTPL(VAL) (((VAL) == TSC_CTPL_1CYCLE) || \
+ ((VAL) == TSC_CTPL_2CYCLES) || \
+ ((VAL) == TSC_CTPL_3CYCLES) || \
+ ((VAL) == TSC_CTPL_4CYCLES) || \
+ ((VAL) == TSC_CTPL_5CYCLES) || \
+ ((VAL) == TSC_CTPL_6CYCLES) || \
+ ((VAL) == TSC_CTPL_7CYCLES) || \
+ ((VAL) == TSC_CTPL_8CYCLES) || \
+ ((VAL) == TSC_CTPL_9CYCLES) || \
+ ((VAL) == TSC_CTPL_10CYCLES) || \
+ ((VAL) == TSC_CTPL_11CYCLES) || \
+ ((VAL) == TSC_CTPL_12CYCLES) || \
+ ((VAL) == TSC_CTPL_13CYCLES) || \
+ ((VAL) == TSC_CTPL_14CYCLES) || \
+ ((VAL) == TSC_CTPL_15CYCLES) || \
+ ((VAL) == TSC_CTPL_16CYCLES))
+
+#define IS_TSC_SS(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE))
+
+#define IS_TSC_SSD(VAL) (((VAL) == 0U) || (((VAL) > 0U) && ((VAL) < 128U)))
+
+#define IS_TSC_SS_PRESC(VAL) (((VAL) == TSC_SS_PRESC_DIV1) || ((VAL) == TSC_SS_PRESC_DIV2))
+
+#define IS_TSC_PG_PRESC(VAL) (((VAL) == TSC_PG_PRESC_DIV1) || \
+ ((VAL) == TSC_PG_PRESC_DIV2) || \
+ ((VAL) == TSC_PG_PRESC_DIV4) || \
+ ((VAL) == TSC_PG_PRESC_DIV8) || \
+ ((VAL) == TSC_PG_PRESC_DIV16) || \
+ ((VAL) == TSC_PG_PRESC_DIV32) || \
+ ((VAL) == TSC_PG_PRESC_DIV64) || \
+ ((VAL) == TSC_PG_PRESC_DIV128))
+
+#define IS_TSC_MCV(VAL) (((VAL) == TSC_MCV_255) || \
+ ((VAL) == TSC_MCV_511) || \
+ ((VAL) == TSC_MCV_1023) || \
+ ((VAL) == TSC_MCV_2047) || \
+ ((VAL) == TSC_MCV_4095) || \
+ ((VAL) == TSC_MCV_8191) || \
+ ((VAL) == TSC_MCV_16383))
+
+#define IS_TSC_IODEF(VAL) (((VAL) == TSC_IODEF_OUT_PP_LOW) || ((VAL) == TSC_IODEF_IN_FLOAT))
+
+#define IS_TSC_SYNC_POL(VAL) (((VAL) == TSC_SYNC_POLARITY_FALLING) || ((VAL) == TSC_SYNC_POLARITY_RISING))
+
+#define IS_TSC_ACQ_MODE(VAL) (((VAL) == TSC_ACQ_MODE_NORMAL) || ((VAL) == TSC_ACQ_MODE_SYNCHRO))
+
+#define IS_TSC_IOMODE(VAL) (((VAL) == TSC_IOMODE_UNUSED) || \
+ ((VAL) == TSC_IOMODE_CHANNEL) || \
+ ((VAL) == TSC_IOMODE_SHIELD) || \
+ ((VAL) == TSC_IOMODE_SAMPLING))
+
+#define IS_TSC_MCE_IT(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE))
+
+#define IS_TSC_GROUP_INDEX(VAL) (((VAL) == 0U) || (((VAL) > 0U) && ((VAL) < TSC_NB_OF_GROUPS)))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TSC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup TSC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+ /* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc);
+HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc);
+void HAL_TSC_MspInit(TSC_HandleTypeDef* htsc);
+void HAL_TSC_MspDeInit(TSC_HandleTypeDef* htsc);
+/**
+ * @}
+ */
+
+/** @addtogroup TSC_Exported_Functions_Group2 Input and Output operation functions
+ * @{
+ */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef* htsc);
+HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef* htsc);
+HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef* htsc);
+HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef* htsc);
+HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef* htsc);
+TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef* htsc, uint32_t gx_index);
+uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef* htsc, uint32_t gx_index);
+/**
+ * @}
+ */
+
+/** @addtogroup TSC_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef* htsc, TSC_IOConfigTypeDef* config);
+HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef* htsc, uint32_t choice);
+/**
+ * @}
+ */
+
+/** @addtogroup TSC_Exported_Functions_Group4 Peripheral State and Errors functions
+ * @{
+ */
+/* Peripheral State and Error functions ***************************************/
+HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef* htsc);
+/**
+ * @}
+ */
+
+/** @addtogroup TSC_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+/******* TSC IRQHandler and Callbacks used in Interrupt mode */
+void HAL_TSC_IRQHandler(TSC_HandleTypeDef* htsc);
+void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef* htsc);
+void HAL_TSC_ErrorCallback(TSC_HandleTypeDef* htsc);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F3xx_TSC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_hal_uart.h b/Inc/stm32f3xx_hal_uart.h
new file mode 100644
index 0000000..c63fbb4
--- /dev/null
+++ b/Inc/stm32f3xx_hal_uart.h
@@ -0,0 +1,1446 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_uart.h
+ * @author MCD Application Team
+ * @brief Header file of UART HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_UART_H
+#define __STM32F3xx_HAL_UART_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup UART
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup UART_Exported_Types UART Exported Types
+ * @{
+ */
+
+/**
+ * @brief UART Init Structure definition
+ */
+typedef struct
+{
+ uint32_t BaudRate; /*!< This member configures the UART communication baud rate.
+ The baud rate register is computed using the following formula:
+ - If oversampling is 16 or in LIN mode,
+ Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate)))
+ - If oversampling is 8U,
+ Baud Rate Register[15:4] = ((2U * PCLKx) / ((huart->Init.BaudRate)))[15:4]
+ Baud Rate Register[3] = 0
+ Baud Rate Register[2:0] = (((2U * PCLKx) / ((huart->Init.BaudRate)))[3:0]) >> 1 */
+
+ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter can be a value of @ref UARTEx_Word_Length. */
+
+ uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
+ This parameter can be a value of @ref UART_Stop_Bits. */
+
+ uint32_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref UART_Parity
+ @note When parity is enabled, the computed parity is inserted
+ at the MSB position of the transmitted data (9th bit when
+ the word length is set to 9 data bits; 8th bit when the
+ word length is set to 8 data bits). */
+
+ uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref UART_Mode. */
+
+ uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled
+ or disabled.
+ This parameter can be a value of @ref UART_Hardware_Flow_Control. */
+
+ uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f_PCLK/8U).
+ This parameter can be a value of @ref UART_Over_Sampling. */
+
+ uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected.
+ Selecting the single sample method increases the receiver tolerance to clock
+ deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */
+}UART_InitTypeDef;
+
+/**
+ * @brief UART Advanced Features initalization structure definition
+ */
+typedef struct
+{
+ uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several
+ Advanced Features may be initialized at the same time .
+ This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type. */
+
+ uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted.
+ This parameter can be a value of @ref UART_Tx_Inv. */
+
+ uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted.
+ This parameter can be a value of @ref UART_Rx_Inv. */
+
+ uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic
+ vs negative/inverted logic).
+ This parameter can be a value of @ref UART_Data_Inv. */
+
+ uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped.
+ This parameter can be a value of @ref UART_Rx_Tx_Swap. */
+
+ uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled.
+ This parameter can be a value of @ref UART_Overrun_Disable. */
+
+ uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error.
+ This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */
+
+ uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled.
+ This parameter can be a value of @ref UART_AutoBaudRate_Enable */
+
+ uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled, specifies how the rate
+ detection is carried out.
+ This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */
+
+ uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line.
+ This parameter can be a value of @ref UART_MSB_First. */
+} UART_AdvFeatureInitTypeDef;
+
+/**
+ * @brief UART wake up from stop mode parameters
+ */
+typedef struct
+{
+ uint32_t WakeUpEvent; /*!< Specifies which event will activat the Wakeup from Stop mode flag (WUF).
+ This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection.
+ If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must
+ be filled up. */
+
+ uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long.
+ This parameter can be a value of @ref UART_WakeUp_Address_Length. */
+
+ uint8_t Address; /*!< UART/USART node address (7-bit long max). */
+} UART_WakeUpTypeDef;
+
+/**
+ * @brief HAL UART State structures definition
+ * @note HAL UART State value is a combination of 2 different substates: gState and RxState.
+ * - gState contains UART state information related to global Handle management
+ * and also information related to Tx operations.
+ * gState value coding follow below described bitmap :
+ * b7-b6 Error information
+ * 00 : No Error
+ * 01 : (Not Used)
+ * 10 : Timeout
+ * 11 : Error
+ * b5 IP initilisation status
+ * 0 : Reset (IP not initialized)
+ * 1 : Init done (IP not initialized. HAL UART Init function already called)
+ * b4-b3 (not used)
+ * xx : Should be set to 00
+ * b2 Intrinsic process state
+ * 0 : Ready
+ * 1 : Busy (IP busy with some configuration or internal operations)
+ * b1 (not used)
+ * x : Should be set to 0
+ * b0 Tx state
+ * 0 : Ready (no Tx operation ongoing)
+ * 1 : Busy (Tx operation ongoing)
+ * - RxState contains information related to Rx operations.
+ * RxState value coding follow below described bitmap :
+ * b7-b6 (not used)
+ * xx : Should be set to 00
+ * b5 IP initilisation status
+ * 0 : Reset (IP not initialized)
+ * 1 : Init done (IP not initialized)
+ * b4-b2 (not used)
+ * xxx : Should be set to 000
+ * b1 Rx state
+ * 0 : Ready (no Rx operation ongoing)
+ * 1 : Busy (Rx operation ongoing)
+ * b0 (not used)
+ * x : Should be set to 0.
+ */
+typedef enum
+{
+ HAL_UART_STATE_RESET = 0x00U, /*!< Peripheral is not initialized
+ Value is allowed for gState and RxState */
+ HAL_UART_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
+ Value is allowed for gState and RxState */
+ HAL_UART_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
+ Value is allowed for gState only */
+ HAL_UART_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
+ Value is allowed for gState only */
+ HAL_UART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
+ Value is allowed for RxState only */
+ HAL_UART_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
+ Not to be used for neither gState nor RxState.
+ Value is result of combination (Or) between gState and RxState values */
+ HAL_UART_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
+ Value is allowed for gState only */
+ HAL_UART_STATE_ERROR = 0xE0U /*!< Error
+ Value is allowed for gState only */
+}HAL_UART_StateTypeDef;
+
+/**
+ * @brief UART clock sources definition
+ */
+typedef enum
+{
+ UART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
+ UART_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */
+ UART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
+ UART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
+ UART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */
+ UART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */
+}UART_ClockSourceTypeDef;
+
+/**
+ * @brief UART handle Structure definition
+ */
+typedef struct
+{
+ USART_TypeDef *Instance; /*!< UART registers base address */
+
+ UART_InitTypeDef Init; /*!< UART communication parameters */
+
+ UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */
+
+ uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */
+
+ uint16_t TxXferSize; /*!< UART Tx Transfer size */
+
+ __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */
+
+ uint16_t RxXferSize; /*!< UART Rx Transfer size */
+
+ __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */
+
+ uint16_t Mask; /*!< UART Rx RDR register mask */
+
+ DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< Locking object */
+
+ __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management
+ and also related to Tx operations.
+ This parameter can be a value of @ref HAL_UART_StateTypeDef */
+
+ __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations.
+ This parameter can be a value of @ref HAL_UART_StateTypeDef */
+
+ __IO uint32_t ErrorCode; /*!< UART Error code */
+
+}UART_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UART_Exported_Constants UART Exported Constants
+ * @{
+ */
+
+/** @defgroup UART_Error UART Error
+ * @{
+ */
+#define HAL_UART_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_UART_ERROR_PE (0x00000001U) /*!< Parity error */
+#define HAL_UART_ERROR_NE (0x00000002U) /*!< Noise error */
+#define HAL_UART_ERROR_FE (0x00000004U) /*!< frame error */
+#define HAL_UART_ERROR_ORE (0x00000008U) /*!< Overrun error */
+#define HAL_UART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
+#define HAL_UART_ERROR_BUSY (0x00000020U) /*!< Busy Error */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Stop_Bits UART Number of Stop Bits
+ * @{
+ */
+#define UART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< UART frame with 0.5 stop bit */
+#define UART_STOPBITS_1 (0x00000000U) /*!< UART frame with 1 stop bit */
+#define UART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) /*!< UART frame with 1.5 stop bits */
+#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) /*!< UART frame with 2 stop bits */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Parity UART Parity
+ * @{
+ */
+#define UART_PARITY_NONE (0x00000000U) /*!< No parity */
+#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /*!< Even parity */
+#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< Odd parity */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
+ * @{
+ */
+#define UART_HWCONTROL_NONE (0x00000000U) /*!< No hardware control */
+#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE) /*!< Request To Send */
+#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE) /*!< Clear To Send */
+#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE)) /*!< Request and Clear To Send */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Mode UART Transfer Mode
+ * @{
+ */
+#define UART_MODE_RX ((uint32_t)USART_CR1_RE) /*!< RX mode */
+#define UART_MODE_TX ((uint32_t)USART_CR1_TE) /*!< TX mode */
+#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) /*!< RX and TX mode */
+/**
+ * @}
+ */
+
+/** @defgroup UART_State UART State
+ * @{
+ */
+#define UART_STATE_DISABLE (0x00000000U) /*!< UART disabled */
+#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE) /*!< UART enabled */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Over_Sampling UART Over Sampling
+ * @{
+ */
+#define UART_OVERSAMPLING_16 (0x00000000U) /*!< Oversampling by 16U */
+#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8) /*!< Oversampling by 8 */
+/**
+ * @}
+ */
+
+/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method
+ * @{
+ */
+#define UART_ONE_BIT_SAMPLE_DISABLE (0x00000000U) /*!< One-bit sampling disable */
+#define UART_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) /*!< One-bit sampling enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode
+ * @{
+ */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT (0x00000000U) /*!< Auto Baud rate detection on start bit */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0) /*!< Auto Baud rate detection on falling edge */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME ((uint32_t)USART_CR2_ABRMODE_1) /*!< Auto Baud rate detection on 0x7F frame detection */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME ((uint32_t)USART_CR2_ABRMODE) /*!< Auto Baud rate detection on 0x55 frame detection */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut
+ * @{
+ */
+#define UART_RECEIVER_TIMEOUT_DISABLE (0x00000000U) /*!< UART receiver timeout disable */
+#define UART_RECEIVER_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN) /*!< UART receiver timeout enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_LIN UART Local Interconnection Network mode
+ * @{
+ */
+#define UART_LIN_DISABLE (0x00000000U) /*!< Local Interconnect Network disable */
+#define UART_LIN_ENABLE ((uint32_t)USART_CR2_LINEN) /*!< Local Interconnect Network enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_LIN_Break_Detection UART LIN Break Detection
+ * @{
+ */
+#define UART_LINBREAKDETECTLENGTH_10B (0x00000000U) /*!< LIN 10-bit break detection length */
+#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL) /*!< LIN 11-bit break detection length */
+/**
+ * @}
+ */
+
+/** @defgroup UART_DMA_Tx UART DMA Tx
+ * @{
+ */
+#define UART_DMA_TX_DISABLE (0x00000000U) /*!< UART DMA TX disabled */
+#define UART_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT) /*!< UART DMA TX enabled */
+/**
+ * @}
+ */
+
+/** @defgroup UART_DMA_Rx UART DMA Rx
+ * @{
+ */
+#define UART_DMA_RX_DISABLE (0x00000000U) /*!< UART DMA RX disabled */
+#define UART_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR) /*!< UART DMA RX enabled */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection
+ * @{
+ */
+#define UART_HALF_DUPLEX_DISABLE (0x00000000U) /*!< UART half-duplex disabled */
+#define UART_HALF_DUPLEX_ENABLE ((uint32_t)USART_CR3_HDSEL) /*!< UART half-duplex enabled */
+/**
+ * @}
+ */
+
+/** @defgroup UART_WakeUp_Address_Length UART WakeUp Address Length
+ * @{
+ */
+#define UART_ADDRESS_DETECT_4B (0x00000000U) /*!< 4-bit long wake-up address */
+#define UART_ADDRESS_DETECT_7B ((uint32_t)USART_CR2_ADDM7) /*!< 7-bit long wake-up address */
+/**
+ * @}
+ */
+
+/** @defgroup UART_WakeUp_Methods UART WakeUp Methods
+ * @{
+ */
+#define UART_WAKEUPMETHOD_IDLELINE (0x00000000U) /*!< UART wake-up on idle line */
+#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE) /*!< UART wake-up on address mark */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Flags UART Status Flags
+ * Elements values convention: 0xXXXX
+ * - 0xXXXX : Flag mask in the ISR register
+ * @{
+ */
+#define UART_FLAG_REACK (0x00400000U) /*!< UART receive enable acknowledge flag */
+#define UART_FLAG_TEACK (0x00200000U) /*!< UART transmit enable acknowledge flag */
+#define UART_FLAG_WUF (0x00100000U) /*!< UART wake-up from stop mode flag */
+#define UART_FLAG_RWU (0x00080000U) /*!< UART receiver wake-up from mute mode flag */
+#define UART_FLAG_SBKF (0x00040000U) /*!< UART send break flag */
+#define UART_FLAG_CMF (0x00020000U) /*!< UART character match flag */
+#define UART_FLAG_BUSY (0x00010000U) /*!< UART busy flag */
+#define UART_FLAG_ABRF (0x00008000U) /*!< UART auto Baud rate flag */
+#define UART_FLAG_ABRE (0x00004000U) /*!< UART auto Baud rate error */
+#define UART_FLAG_EOBF (0x00001000U) /*!< UART end of block flag */
+#define UART_FLAG_RTOF (0x00000800U) /*!< UART receiver timeout flag */
+#define UART_FLAG_CTS (0x00000400U) /*!< UART clear to send flag */
+#define UART_FLAG_CTSIF (0x00000200U) /*!< UART clear to send interrupt flag */
+#define UART_FLAG_LBDF (0x00000100U) /*!< UART LIN break detection flag */
+#define UART_FLAG_TXE (0x00000080U) /*!< UART transmit data register empty */
+#define UART_FLAG_TC (0x00000040U) /*!< UART transmission complete */
+#define UART_FLAG_RXNE (0x00000020U) /*!< UART read data register not empty */
+#define UART_FLAG_IDLE (0x00000010U) /*!< UART idle flag */
+#define UART_FLAG_ORE (0x00000008U) /*!< UART overrun error */
+#define UART_FLAG_NE (0x00000004U) /*!< UART noise error */
+#define UART_FLAG_FE (0x00000002U) /*!< UART frame error */
+#define UART_FLAG_PE (0x00000001U) /*!< UART parity error */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Interrupt_definition UART Interrupts Definition
+ * Elements values convention: 000ZZZZZ0XXYYYYYb
+ * - YYYYY : Interrupt source position in the XX register (5bits)
+ * - XX : Interrupt source register (2bits)
+ * - 01: CR1 register
+ * - 10: CR2 register
+ * - 11: CR3 register
+ * - ZZZZZ : Flag position in the ISR register(5bits)
+ * @{
+ */
+#define UART_IT_PE (0x0028U) /*!< UART parity error interruption */
+#define UART_IT_TXE (0x0727U) /*!< UART transmit data register empty interruption */
+#define UART_IT_TC (0x0626U) /*!< UART transmission complete interruption */
+#define UART_IT_RXNE (0x0525U) /*!< UART read data register not empty interruption */
+#define UART_IT_IDLE (0x0424U) /*!< UART idle interruption */
+#define UART_IT_LBD (0x0846U) /*!< UART LIN break detection interruption */
+#define UART_IT_CTS (0x096AU) /*!< UART CTS interruption */
+#define UART_IT_CM (0x112EU) /*!< UART character match interruption */
+#define UART_IT_WUF (0x1476U) /*!< UART wake-up from stop mode interruption */
+#define UART_IT_ERR (0x0060U) /*!< UART error interruption */
+#define UART_IT_ORE (0x0300U) /*!< UART overrun error interruption */
+#define UART_IT_NE (0x0200U) /*!< UART noise error interruption */
+#define UART_IT_FE (0x0100U) /*!< UART frame error interruption */
+/**
+ * @}
+ */
+
+/** @defgroup UART_IT_CLEAR_Flags UART Interruption Clear Flags
+ * @{
+ */
+#define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
+#define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
+#define UART_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */
+#define UART_CLEAR_OREF USART_ICR_ORECF /*!< Overrun Error Clear Flag */
+#define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
+#define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
+#define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag */
+#define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */
+#define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< Receiver Time Out Clear Flag */
+#define UART_CLEAR_EOBF USART_ICR_EOBCF /*!< End Of Block Clear Flag */
+#define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */
+#define UART_CLEAR_WUF USART_ICR_WUCF /*!< Wake Up from stop mode Clear Flag */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Request_Parameters UART Request Parameters
+ * @{
+ */
+#define UART_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ) /*!< Auto-Baud Rate Request */
+#define UART_SENDBREAK_REQUEST ((uint32_t)USART_RQR_SBKRQ) /*!< Send Break Request */
+#define UART_MUTE_MODE_REQUEST ((uint32_t)USART_RQR_MMRQ) /*!< Mute Mode Request */
+#define UART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */
+#define UART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature Initialization Type
+ * @{
+ */
+#define UART_ADVFEATURE_NO_INIT (0x00000000U) /*!< No advanced feature initialization */
+#define UART_ADVFEATURE_TXINVERT_INIT (0x00000001U) /*!< TX pin active level inversion */
+#define UART_ADVFEATURE_RXINVERT_INIT (0x00000002U) /*!< RX pin active level inversion */
+#define UART_ADVFEATURE_DATAINVERT_INIT (0x00000004U) /*!< Binary data inversion */
+#define UART_ADVFEATURE_SWAP_INIT (0x00000008U) /*!< TX/RX pins swap */
+#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT (0x00000010U) /*!< RX overrun disable */
+#define UART_ADVFEATURE_DMADISABLEONERROR_INIT (0x00000020U) /*!< DMA disable on Reception Error */
+#define UART_ADVFEATURE_AUTOBAUDRATE_INIT (0x00000040U) /*!< Auto Baud rate detection initialization */
+#define UART_ADVFEATURE_MSBFIRST_INIT (0x00000080U) /*!< Most significant bit sent/received first */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion
+ * @{
+ */
+#define UART_ADVFEATURE_TXINV_DISABLE (0x00000000U) /*!< TX pin active level inversion disable */
+#define UART_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV) /*!< TX pin active level inversion enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion
+ * @{
+ */
+#define UART_ADVFEATURE_RXINV_DISABLE (0x00000000U) /*!< RX pin active level inversion disable */
+#define UART_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV) /*!< RX pin active level inversion enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion
+ * @{
+ */
+#define UART_ADVFEATURE_DATAINV_DISABLE (0x00000000U) /*!< Binary data inversion disable */
+#define UART_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV) /*!< Binary data inversion enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap
+ * @{
+ */
+#define UART_ADVFEATURE_SWAP_DISABLE (0x00000000U) /*!< TX/RX pins swap disable */
+#define UART_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP) /*!< TX/RX pins swap enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable
+ * @{
+ */
+#define UART_ADVFEATURE_OVERRUN_ENABLE (0x00000000U) /*!< RX overrun enable */
+#define UART_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS) /*!< RX overrun disable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable
+ * @{
+ */
+#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE (0x00000000U) /*!< RX Auto Baud rate detection enable */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE ((uint32_t)USART_CR2_ABREN) /*!< RX Auto Baud rate detection disable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error
+ * @{
+ */
+#define UART_ADVFEATURE_DMA_ENABLEONRXERROR (0x00000000U) /*!< DMA enable on Reception Error */
+#define UART_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE) /*!< DMA disable on Reception Error */
+/**
+ * @}
+ */
+
+/** @defgroup UART_MSB_First UART Advanced Feature MSB First
+ * @{
+ */
+#define UART_ADVFEATURE_MSBFIRST_DISABLE (0x00000000U) /*!< Most significant bit sent/received first disable */
+#define UART_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST) /*!< Most significant bit sent/received first enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Stop_Mode_Enable UART Advanced Feature Stop Mode Enable
+ * @{
+ */
+#define UART_ADVFEATURE_STOPMODE_DISABLE (0x00000000U) /*!< UART stop mode disable */
+#define UART_ADVFEATURE_STOPMODE_ENABLE ((uint32_t)USART_CR1_UESM) /*!< UART stop mode enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable
+ * @{
+ */
+#define UART_ADVFEATURE_MUTEMODE_DISABLE (0x00000000U) /*!< UART mute mode disable */
+#define UART_ADVFEATURE_MUTEMODE_ENABLE ((uint32_t)USART_CR1_MME) /*!< UART mute mode enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register
+ * @{
+ */
+#define UART_CR2_ADDRESS_LSB_POS ( 24U) /*!< UART address-matching LSB position in CR2 register */
+/**
+ * @}
+ */
+
+/** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection
+ * @{
+ */
+#define UART_WAKEUP_ON_ADDRESS (0x00000000U) /*!< UART wake-up on address */
+#define UART_WAKEUP_ON_STARTBIT ((uint32_t)USART_CR3_WUS_1) /*!< UART wake-up on start bit */
+#define UART_WAKEUP_ON_READDATA_NONEMPTY ((uint32_t)USART_CR3_WUS) /*!< UART wake-up on receive data register not empty */
+/**
+ * @}
+ */
+
+/** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity
+ * @{
+ */
+#define UART_DE_POLARITY_HIGH (0x00000000U) /*!< Driver enable signal is active high */
+#define UART_DE_POLARITY_LOW ((uint32_t)USART_CR3_DEP) /*!< Driver enable signal is active low */
+/**
+ * @}
+ */
+
+/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register
+ * @{
+ */
+#define UART_CR1_DEAT_ADDRESS_LSB_POS ( 21U) /*!< UART Driver Enable assertion time LSB position in CR1 register */
+/**
+ * @}
+ */
+
+/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register
+ * @{
+ */
+#define UART_CR1_DEDT_ADDRESS_LSB_POS ( 16U) /*!< UART Driver Enable de-assertion time LSB position in CR1 register */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask
+ * @{
+ */
+#define UART_IT_MASK (0x001FU) /*!< UART interruptions flags mask */
+/**
+ * @}
+ */
+
+/** @defgroup UART_TimeOut_Value UART polling-based communications time-out value
+ * @{
+ */
+#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFF /*!< UART polling-based communications time-out value */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup UART_Exported_Macros UART Exported Macros
+ * @{
+ */
+
+/** @brief Reset UART handle states.
+ * @param __HANDLE__ UART handle.
+ * @retval None
+ */
+#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->gState = HAL_UART_STATE_RESET; \
+ (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \
+ } while(0U)
+/** @brief Flush the UART Data registers.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \
+ do{ \
+ SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
+ SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
+ } while(0U)
+
+/** @brief Clear the specified UART pending flag.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag
+ * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag
+ * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag
+ * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag
+ * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag
+ * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag
+ * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag (not available on all devices)
+ * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag
+ * @arg @ref UART_CLEAR_RTOF Receiver Time Out Clear Flag
+ * @arg @ref UART_CLEAR_EOBF End Of Block Clear Flag (not available on all devices)
+ * @arg @ref UART_CLEAR_CMF Character Match Clear Flag
+ * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag (not available on all devices)
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/** @brief Clear the UART PE pending flag.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)
+
+/** @brief Clear the UART FE pending flag.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)
+
+/** @brief Clear the UART NE pending flag.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)
+
+/** @brief Clear the UART ORE pending flag.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)
+
+/** @brief Clear the UART IDLE pending flag.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)
+
+/** @brief Check whether the specified UART flag is set or not.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg @ref UART_FLAG_REACK Receive enable acknowledge flag
+ * @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag
+ * @arg @ref UART_FLAG_WUF Wake up from stop mode flag
+ * @arg @ref UART_FLAG_RWU Receiver wake up flag
+ * @arg @ref UART_FLAG_SBKF Send Break flag
+ * @arg @ref UART_FLAG_CMF Character match flag
+ * @arg @ref UART_FLAG_BUSY Busy flag
+ * @arg @ref UART_FLAG_ABRF Auto Baud rate detection flag
+ * @arg @ref UART_FLAG_ABRE Auto Baud rate detection error flag
+ * @arg @ref UART_FLAG_EOBF End of block flag
+ * @arg @ref UART_FLAG_RTOF Receiver timeout flag
+ * @arg @ref UART_FLAG_CTS CTS Change flag (not available for UART4 and UART5)
+ * @arg @ref UART_FLAG_LBDF LIN Break detection flag
+ * @arg @ref UART_FLAG_TXE Transmit data register empty flag
+ * @arg @ref UART_FLAG_TC Transmission Complete flag
+ * @arg @ref UART_FLAG_RXNE Receive data register not empty flag
+ * @arg @ref UART_FLAG_IDLE Idle Line detection flag
+ * @arg @ref UART_FLAG_ORE Overrun Error flag
+ * @arg @ref UART_FLAG_NE Noise Error flag
+ * @arg @ref UART_FLAG_FE Framing Error flag
+ * @arg @ref UART_FLAG_PE Parity Error flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
+
+/** @brief Enable the specified UART interrupt.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @param __INTERRUPT__ specifies the UART interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt
+ * @arg @ref UART_IT_CM Character match interrupt
+ * @arg @ref UART_IT_CTS CTS change interrupt
+ * @arg @ref UART_IT_LBD LIN Break detection interrupt
+ * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref UART_IT_TC Transmission complete interrupt
+ * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref UART_IT_IDLE Idle line detection interrupt
+ * @arg @ref UART_IT_PE Parity Error interrupt
+ * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
+ * @retval None
+ */
+#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
+ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))))
+
+
+/** @brief Disable the specified UART interrupt.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @param __INTERRUPT__ specifies the UART interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt
+ * @arg @ref UART_IT_CM Character match interrupt
+ * @arg @ref UART_IT_CTS CTS change interrupt
+ * @arg @ref UART_IT_LBD LIN Break detection interrupt
+ * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref UART_IT_TC Transmission complete interrupt
+ * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref UART_IT_IDLE Idle line detection interrupt
+ * @arg @ref UART_IT_PE Parity Error interrupt
+ * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
+ * @retval None
+ */
+#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
+ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))))
+
+/** @brief Check whether the specified UART interrupt has occurred or not.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @param __IT__ specifies the UART interrupt to check.
+ * This parameter can be one of the following values:
+ * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt
+ * @arg @ref UART_IT_CM Character match interrupt
+ * @arg @ref UART_IT_CTS CTS change interrupt (not available for UART4 and UART5)
+ * @arg @ref UART_IT_LBD LIN Break detection interrupt
+ * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref UART_IT_TC Transmission complete interrupt
+ * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref UART_IT_IDLE Idle line detection interrupt
+ * @arg @ref UART_IT_ORE Overrun Error interrupt
+ * @arg @ref UART_IT_NE Noise Error interrupt
+ * @arg @ref UART_IT_FE Framing Error interrupt
+ * @arg @ref UART_IT_PE Parity Error interrupt
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U)))
+
+/** @brief Check whether the specified UART interrupt source is enabled or not.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @param __IT__ specifies the UART interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt
+ * @arg @ref UART_IT_CM Character match interrupt
+ * @arg @ref UART_IT_CTS CTS change interrupt (not available for UART4 and UART5)
+ * @arg @ref UART_IT_LBD LIN Break detection interrupt
+ * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref UART_IT_TC Transmission complete interrupt
+ * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref UART_IT_IDLE Idle line detection interrupt
+ * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
+ * @arg @ref UART_IT_PE Parity Error interrupt
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2U)? \
+ (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__IT__)) & UART_IT_MASK)))
+
+/** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
+ * to clear the corresponding interrupt
+ * This parameter can be one of the following values:
+ * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag
+ * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag
+ * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag
+ * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag
+ * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag
+ * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag
+ * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag
+ * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag
+ * @arg @ref UART_CLEAR_RTOF Receiver Time Out Clear Flag
+ * @arg @ref UART_CLEAR_EOBF End Of Block Clear Flag
+ * @arg @ref UART_CLEAR_CMF Character Match Clear Flag
+ * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
+
+/** @brief Set a specific UART request flag.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @param __REQ__ specifies the request flag to set
+ * This parameter can be one of the following values:
+ * @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request
+ * @arg @ref UART_SENDBREAK_REQUEST Send Break Request
+ * @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request
+ * @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request
+ * @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request
+ * @retval None
+ */
+#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__))
+
+/** @brief Enable the UART one bit sample method.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+
+/** @brief Disable the UART one bit sample method.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
+
+/** @brief Enable UART.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+
+/** @brief Disable UART.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+
+/** @brief Enable CTS flow control.
+ * @note This macro allows to enable CTS hardware flow control for a given UART instance,
+ * without need to call HAL_UART_Init() function.
+ * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+ * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
+ * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+ * - UART instance should have already been initialised (through call of HAL_UART_Init() )
+ * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
+ * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \
+ do{ \
+ SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
+ (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \
+ } while(0U)
+
+/** @brief Disable CTS flow control.
+ * @note This macro allows to disable CTS hardware flow control for a given UART instance,
+ * without need to call HAL_UART_Init() function.
+ * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+ * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
+ * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+ * - UART instance should have already been initialised (through call of HAL_UART_Init() )
+ * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
+ * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \
+ do{ \
+ CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
+ (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \
+ } while(0U)
+
+/** @brief Enable RTS flow control.
+ * @note This macro allows to enable RTS hardware flow control for a given UART instance,
+ * without need to call HAL_UART_Init() function.
+ * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+ * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
+ * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+ * - UART instance should have already been initialised (through call of HAL_UART_Init() )
+ * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
+ * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \
+ do{ \
+ SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
+ (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \
+ } while(0U)
+
+/** @brief Disable RTS flow control.
+ * @note This macro allows to disable RTS hardware flow control for a given UART instance,
+ * without need to call HAL_UART_Init() function.
+ * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+ * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
+ * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+ * - UART instance should have already been initialised (through call of HAL_UART_Init() )
+ * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
+ * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \
+ do{ \
+ CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
+ (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \
+ } while(0U)
+
+/**
+ * @}
+ */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup UART_Private_Macros UART Private Macros
+ * @{
+ */
+/** @brief BRR division operation to set BRR register in 8-bit oversampling mode.
+ * @param __PCLK__ UART clock.
+ * @param __BAUD__ Baud rate set by the user.
+ * @retval Division result
+ */
+#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__) ((((__PCLK__)*2U) + ((__BAUD__)/2U)) / (__BAUD__))
+
+/** @brief BRR division operation to set BRR register in 16-bit oversampling mode.
+ * @param __PCLK__ UART clock.
+ * @param __BAUD__ Baud rate set by the user.
+ * @retval Division result
+ */
+#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__) (((__PCLK__) + ((__BAUD__)/2U)) / (__BAUD__))
+
+/** @brief Check UART Baud rate.
+ * @param __BAUDRATE__ Baudrate specified by the user.
+ * The maximum Baud Rate is derived from the maximum clock on F3 (i.e. 72 MHz)
+ * divided by the smallest oversampling used on the USART (i.e. 8)
+ * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)
+ */
+#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 9000001U)
+
+/** @brief Check UART assertion time.
+ * @param __TIME__ 5-bit value assertion time.
+ * @retval Test result (TRUE or FALSE).
+ */
+#define IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
+
+/** @brief Check UART deassertion time.
+ * @param __TIME__ 5-bit value deassertion time.
+ * @retval Test result (TRUE or FALSE).
+ */
+#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
+
+/**
+ * @brief Ensure that UART frame number of stop bits is valid.
+ * @param __STOPBITS__ UART frame number of stop bits.
+ * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
+ */
+#define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \
+ ((__STOPBITS__) == UART_STOPBITS_1) || \
+ ((__STOPBITS__) == UART_STOPBITS_1_5) || \
+ ((__STOPBITS__) == UART_STOPBITS_2))
+
+/**
+ * @brief Ensure that UART frame parity is valid.
+ * @param __PARITY__ UART frame parity.
+ * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
+ */
+#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \
+ ((__PARITY__) == UART_PARITY_EVEN) || \
+ ((__PARITY__) == UART_PARITY_ODD))
+
+/**
+ * @brief Ensure that UART hardware flow control is valid.
+ * @param __CONTROL__ UART hardware flow control.
+ * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid)
+ */
+#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\
+ (((__CONTROL__) == UART_HWCONTROL_NONE) || \
+ ((__CONTROL__) == UART_HWCONTROL_RTS) || \
+ ((__CONTROL__) == UART_HWCONTROL_CTS) || \
+ ((__CONTROL__) == UART_HWCONTROL_RTS_CTS))
+
+/**
+ * @brief Ensure that UART communication mode is valid.
+ * @param __MODE__ UART communication mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
+
+/**
+ * @brief Ensure that UART state is valid.
+ * @param __STATE__ UART state.
+ * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
+ */
+#define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \
+ ((__STATE__) == UART_STATE_ENABLE))
+
+/**
+ * @brief Ensure that UART oversampling is valid.
+ * @param __SAMPLING__ UART oversampling.
+ * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)
+ */
+#define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \
+ ((__SAMPLING__) == UART_OVERSAMPLING_8))
+
+/**
+ * @brief Ensure that UART frame sampling is valid.
+ * @param __ONEBIT__ UART frame sampling.
+ * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
+ */
+#define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \
+ ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE))
+
+/**
+ * @brief Ensure that Address Length detection parameter is valid.
+ * @param __ADDRESS__ UART Adress length value.
+ * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)
+ */
+#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
+ ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
+
+/**
+ * @brief Ensure that UART auto Baud rate detection mode is valid.
+ * @param __MODE__ UART auto Baud rate detection mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \
+ ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \
+ ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \
+ ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))
+
+/**
+ * @brief Ensure that UART receiver timeout setting is valid.
+ * @param __TIMEOUT__ UART receiver timeout setting.
+ * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
+ */
+#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \
+ ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))
+
+/**
+ * @brief Ensure that UART LIN state is valid.
+ * @param __LIN__ UART LIN state.
+ * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid)
+ */
+#define IS_UART_LIN(__LIN__) (((__LIN__) == UART_LIN_DISABLE) || \
+ ((__LIN__) == UART_LIN_ENABLE))
+
+/**
+ * @brief Ensure that UART LIN break detection length is valid.
+ * @param __LENGTH__ UART LIN break detection length.
+ * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+ */
+#define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \
+ ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B))
+
+/**
+ * @brief Ensure that UART DMA TX state is valid.
+ * @param __DMATX__ UART DMA TX state.
+ * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
+ */
+#define IS_UART_DMA_TX(__DMATX__) (((__DMATX__) == UART_DMA_TX_DISABLE) || \
+ ((__DMATX__) == UART_DMA_TX_ENABLE))
+
+/**
+ * @brief Ensure that UART DMA RX state is valid.
+ * @param __DMARX__ UART DMA RX state.
+ * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
+ */
+#define IS_UART_DMA_RX(__DMARX__) (((__DMARX__) == UART_DMA_RX_DISABLE) || \
+ ((__DMARX__) == UART_DMA_RX_ENABLE))
+
+/**
+ * @brief Ensure that UART half-duplex state is valid.
+ * @param __HDSEL__ UART half-duplex state.
+ * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid)
+ */
+#define IS_UART_HALF_DUPLEX(__HDSEL__) (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \
+ ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE))
+
+/**
+ * @brief Ensure that UART wake-up method is valid.
+ * @param __WAKEUP__ UART wake-up method .
+ * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid)
+ */
+#define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \
+ ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK))
+
+/**
+ * @brief Ensure that UART advanced features initialization is valid.
+ * @param __INIT__ UART advanced features initialization.
+ * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \
+ UART_ADVFEATURE_TXINVERT_INIT | \
+ UART_ADVFEATURE_RXINVERT_INIT | \
+ UART_ADVFEATURE_DATAINVERT_INIT | \
+ UART_ADVFEATURE_SWAP_INIT | \
+ UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \
+ UART_ADVFEATURE_DMADISABLEONERROR_INIT | \
+ UART_ADVFEATURE_AUTOBAUDRATE_INIT | \
+ UART_ADVFEATURE_MSBFIRST_INIT))
+
+/**
+ * @brief Ensure that UART frame TX inversion setting is valid.
+ * @param __TXINV__ UART frame TX inversion setting.
+ * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \
+ ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE))
+
+/**
+ * @brief Ensure that UART frame RX inversion setting is valid.
+ * @param __RXINV__ UART frame RX inversion setting.
+ * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \
+ ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE))
+
+/**
+ * @brief Ensure that UART frame data inversion setting is valid.
+ * @param __DATAINV__ UART frame data inversion setting.
+ * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \
+ ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE))
+
+/**
+ * @brief Ensure that UART frame RX/TX pins swap setting is valid.
+ * @param __SWAP__ UART frame RX/TX pins swap setting.
+ * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \
+ ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE))
+
+/**
+ * @brief Ensure that UART frame overrun setting is valid.
+ * @param __OVERRUN__ UART frame overrun setting.
+ * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
+ */
+#define IS_UART_OVERRUN(__OVERRUN__) (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \
+ ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE))
+
+/**
+ * @brief Ensure that UART auto Baud rate state is valid.
+ * @param __AUTOBAUDRATE__ UART auto Baud rate state.
+ * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
+ ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))
+
+/**
+ * @brief Ensure that UART DMA enabling or disabling on error setting is valid.
+ * @param __DMA__ UART DMA enabling or disabling on error setting.
+ * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \
+ ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))
+
+/**
+ * @brief Ensure that UART frame MSB first setting is valid.
+ * @param __MSBFIRST__ UART frame MSB first setting.
+ * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \
+ ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE))
+
+/**
+ * @brief Ensure that UART stop mode state is valid.
+ * @param __STOPMODE__ UART stop mode state.
+ * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \
+ ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE))
+
+/**
+ * @brief Ensure that UART mute mode state is valid.
+ * @param __MUTE__ UART mute mode state.
+ * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid)
+ */
+#define IS_UART_MUTE_MODE(__MUTE__) (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \
+ ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE))
+
+/**
+ * @brief Ensure that UART wake-up selection is valid.
+ * @param __WAKE__ UART wake-up selection.
+ * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid)
+ */
+#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \
+ ((__WAKE__) == UART_WAKEUP_ON_STARTBIT) || \
+ ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY))
+
+/**
+ * @brief Ensure that UART driver enable polarity is valid.
+ * @param __POLARITY__ UART driver enable polarity.
+ * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid)
+ */
+#define IS_UART_DE_POLARITY(__POLARITY__) (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \
+ ((__POLARITY__) == UART_DE_POLARITY_LOW))
+
+/**
+ * @brief Ensure that UART request parameter is valid.
+ * @param __PARAM__ UART request parameter.
+ * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
+ */
+#define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST) || \
+ ((__PARAM__) == UART_SENDBREAK_REQUEST) || \
+ ((__PARAM__) == UART_MUTE_MODE_REQUEST) || \
+ ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \
+ ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST))
+
+/**
+ * @}
+ */
+
+/* Include UART HAL Extended module */
+#include "stm32f3xx_hal_uart_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UART_Exported_Functions UART Exported Functions
+ * @{
+ */
+
+/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
+HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart);
+void HAL_UART_MspInit(UART_HandleTypeDef *huart);
+void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
+
+/**
+ * @}
+ */
+
+/** @addtogroup UART_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart);
+
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
+void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
+void HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart);
+void HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart);
+void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart);
+
+/**
+ * @}
+ */
+
+/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+
+/* Peripheral Control functions ************************************************/
+HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart);
+void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
+
+/**
+ * @}
+ */
+
+/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions
+ * @{
+ */
+
+/* Peripheral State and Errors functions **************************************************/
+HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
+uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions -----------------------------------------------------------*/
+/** @addtogroup UART_Private_Functions UART Private Functions
+ * @{
+ */
+HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
+void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
+HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
+void UART_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_UART_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Inc/stm32f3xx_hal_uart_ex.h b/Inc/stm32f3xx_hal_uart_ex.h
new file mode 100644
index 0000000..18e4518
--- /dev/null
+++ b/Inc/stm32f3xx_hal_uart_ex.h
@@ -0,0 +1,475 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_uart_ex.h
+ * @author MCD Application Team
+ * @brief Header file of UART HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_UART_EX_H
+#define __STM32F3xx_HAL_UART_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup UARTEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants
+ * @{
+ */
+
+/** @defgroup UARTEx_Word_Length UARTEx Word Length
+ * @{
+ */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define UART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long UART frame */
+#define UART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long UART frame */
+#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long UART frame */
+#else
+#define UART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long UART frame */
+#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M) /*!< 9-bit long UART frame */
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UARTEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup UARTEx_Exported_Functions_Group1
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime);
+
+/**
+ * @}
+ */
+
+/* IO operation functions *****************************************************/
+
+/** @addtogroup UARTEx_Exported_Functions_Group3
+ * @{
+ */
+
+/* Peripheral Control functions **********************************************/
+HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
+HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
+void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup UARTEx_Private_Macros UARTEx Private Macros
+ * @{
+ */
+
+/** @brief Report the UART clock source.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @param __CLOCKSOURCE__ output variable.
+ * @retval UART clocking source, written in __CLOCKSOURCE__.
+ */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK2: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
+ case RCC_USART2CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART2CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART2CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART2CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \
+ { \
+ case RCC_USART3CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART3CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART3CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART3CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == UART4) \
+ { \
+ switch(__HAL_RCC_GET_UART4_SOURCE()) \
+ { \
+ case RCC_UART4CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_UART4CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_UART4CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_UART4CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if ((__HANDLE__)->Instance == UART5) \
+ { \
+ switch(__HAL_RCC_GET_UART5_SOURCE()) \
+ { \
+ case RCC_UART5CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_UART5CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_UART5CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_UART5CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0U)
+#elif defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0U)
+#else
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK2: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
+ case RCC_USART2CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART2CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART2CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART2CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \
+ { \
+ case RCC_USART3CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART3CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART3CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART3CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0U)
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+
+/** @brief Compute the UART mask to apply to retrieve the received data
+ * according to the word length and to the parity bits activation.
+ * @note If PCE = 1, the parity bit is not included in the data extracted
+ * by the reception API().
+ * This masking operation is not carried out in the case of
+ * DMA transfers.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.
+ */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define UART_MASK_COMPUTATION(__HANDLE__) \
+ do { \
+ if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x01FFU ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x00FFU ; \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x00FFU ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x007FU ; \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x007FU ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x003FU ; \
+ } \
+ } \
+} while(0U)
+#else
+#define UART_MASK_COMPUTATION(__HANDLE__) \
+ do { \
+ if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x01FFU ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x00FFU ; \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x00FFU ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x007FU ; \
+ } \
+ } \
+} while(0U)
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+/**
+ * @brief Ensure that UART frame length is valid.
+ * @param __LENGTH__ UART frame length.
+ * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+ */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \
+ ((__LENGTH__) == UART_WORDLENGTH_8B) || \
+ ((__LENGTH__) == UART_WORDLENGTH_9B))
+#else
+#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_8B) || \
+ ((__LENGTH__) == UART_WORDLENGTH_9B))
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_UART_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Inc/stm32f3xx_hal_usart.h b/Inc/stm32f3xx_hal_usart.h
new file mode 100644
index 0000000..104fad2
--- /dev/null
+++ b/Inc/stm32f3xx_hal_usart.h
@@ -0,0 +1,710 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_usart.h
+ * @author MCD Application Team
+ * @brief Header file of USART HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_USART_H
+#define __STM32F3xx_HAL_USART_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup USART
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup USART_Exported_Types USART Exported Types
+ * @{
+ */
+
+/**
+ * @brief USART Init Structure definition
+ */
+typedef struct
+{
+ uint32_t BaudRate; /*!< This member configures the Usart communication baud rate.
+ The baud rate is computed using the following formula:
+ Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate))). */
+
+ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter can be a value of @ref USARTEx_Word_Length. */
+
+ uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
+ This parameter can be a value of @ref USART_Stop_Bits. */
+
+ uint32_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref USART_Parity
+ @note When parity is enabled, the computed parity is inserted
+ at the MSB position of the transmitted data (9th bit when
+ the word length is set to 9 data bits; 8th bit when the
+ word length is set to 8 data bits). */
+
+ uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref USART_Mode. */
+
+ uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
+ This parameter can be a value of @ref USART_Clock_Polarity. */
+
+ uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.
+ This parameter can be a value of @ref USART_Clock_Phase. */
+
+ uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
+ data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+ This parameter can be a value of @ref USART_Last_Bit. */
+}USART_InitTypeDef;
+
+/**
+ * @brief HAL USART State structures definition
+ */
+typedef enum
+{
+ HAL_USART_STATE_RESET = 0x00U, /*!< Peripheral is not initialized */
+ HAL_USART_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
+ HAL_USART_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
+ HAL_USART_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */
+ HAL_USART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
+ HAL_USART_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission Reception process is ongoing */
+ HAL_USART_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
+ HAL_USART_STATE_ERROR = 0x04U /*!< Error */
+}HAL_USART_StateTypeDef;
+
+/**
+ * @brief USART clock sources definitions
+ */
+typedef enum
+{
+ USART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
+ USART_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */
+ USART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
+ USART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
+ USART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */
+ USART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */
+}USART_ClockSourceTypeDef;
+
+
+/**
+ * @brief USART handle Structure definition
+ */
+typedef struct
+{
+ USART_TypeDef *Instance; /*!< USART registers base address */
+
+ USART_InitTypeDef Init; /*!< USART communication parameters */
+
+ uint8_t *pTxBuffPtr; /*!< Pointer to USART Tx transfer Buffer */
+
+ uint16_t TxXferSize; /*!< USART Tx Transfer size */
+
+ __IO uint16_t TxXferCount; /*!< USART Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /*!< Pointer to USART Rx transfer Buffer */
+
+ uint16_t RxXferSize; /*!< USART Rx Transfer size */
+
+ __IO uint16_t RxXferCount; /*!< USART Rx Transfer Counter */
+
+ uint16_t Mask; /*!< USART Rx RDR register mask */
+
+ DMA_HandleTypeDef *hdmatx; /*!< USART Tx DMA Handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< USART Rx DMA Handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< Locking object */
+
+ __IO HAL_USART_StateTypeDef State; /*!< USART communication state */
+
+ __IO uint32_t ErrorCode; /*!< USART Error code */
+
+}USART_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup USART_Exported_Constants USART Exported Constants
+ * @{
+ */
+
+/** @defgroup USART_Error USART Error
+ * @{
+ */
+#define HAL_USART_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_USART_ERROR_PE (0x00000001U) /*!< Parity error */
+#define HAL_USART_ERROR_NE (0x00000002U) /*!< Noise error */
+#define HAL_USART_ERROR_FE (0x00000004U) /*!< frame error */
+#define HAL_USART_ERROR_ORE (0x00000008U) /*!< Overrun error */
+#define HAL_USART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
+/**
+ * @}
+ */
+
+/** @defgroup USART_Stop_Bits USART Number of Stop Bits
+ * @{
+ */
+#define USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0) /*!< USART frame with 0.5 stop bit */
+#define USART_STOPBITS_1 (0x00000000U) /*!< USART frame with 1 stop bit */
+#define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) /*!< USART frame with 1.5 stop bits */
+#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) /*!< USART frame with 2 stop bits */
+/**
+ * @}
+ */
+
+/** @defgroup USART_Parity USART Parity
+ * @{
+ */
+#define USART_PARITY_NONE (0x00000000U) /*!< No parity */
+#define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /*!< Even parity */
+#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< Odd parity */
+/**
+ * @}
+ */
+
+/** @defgroup USART_Mode USART Mode
+ * @{
+ */
+#define USART_MODE_RX ((uint32_t)USART_CR1_RE) /*!< RX mode */
+#define USART_MODE_TX ((uint32_t)USART_CR1_TE) /*!< TX mode */
+#define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) /*!< RX and TX mode */
+/**
+ * @}
+ */
+
+/** @defgroup USART_Clock USART Clock
+ * @{
+ */
+#define USART_CLOCK_DISABLE (0x00000000U) /*!< USART clock disable */
+#define USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN) /*!< USART clock enable */
+/**
+ * @}
+ */
+
+/** @defgroup USART_Clock_Polarity USART Clock Polarity
+ * @{
+ */
+#define USART_POLARITY_LOW (0x00000000U) /*!< USART Clock signal is steady Low */
+#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL) /*!< USART Clock signal is steady High */
+/**
+ * @}
+ */
+
+/** @defgroup USART_Clock_Phase USART Clock Phase
+ * @{
+ */
+#define USART_PHASE_1EDGE (0x00000000U) /*!< USART frame phase on first clock transition */
+#define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA) /*!< USART frame phase on second clock transition */
+/**
+ * @}
+ */
+
+/** @defgroup USART_Last_Bit USART Last Bit
+ * @{
+ */
+#define USART_LASTBIT_DISABLE (0x00000000U) /*!< USART frame last data bit clock pulse not output to SCLK pin */
+#define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL) /*!< USART frame last data bit clock pulse output to SCLK pin */
+/**
+ * @}
+ */
+
+/** @defgroup USART_Request_Parameters USART Request Parameters
+ * @{
+ */
+#define USART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */
+#define USART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */
+/**
+ * @}
+ */
+
+/** @defgroup USART_Flags USART Flags
+ * Elements values convention: 0xXXXX
+ * - 0xXXXX : Flag mask in the ISR register
+ * @{
+ */
+#define USART_FLAG_REACK (0x00400000U) /*!< USART receive enable acknowledge flag */
+#define USART_FLAG_TEACK (0x00200000U) /*!< USART transmit enable acknowledge flag */
+#define USART_FLAG_BUSY (0x00010000U) /*!< USART busy flag */
+#define USART_FLAG_CTS (0x00000400U) /*!< USART clear to send flag */
+#define USART_FLAG_CTSIF (0x00000200U) /*!< USART clear to send interrupt flag */
+#define USART_FLAG_LBDF (0x00000100U) /*!< USART LIN break detection flag */
+#define USART_FLAG_TXE (0x00000080U) /*!< USART transmit data register empty */
+#define USART_FLAG_TC (0x00000040U) /*!< USART transmission complete */
+#define USART_FLAG_RXNE (0x00000020U) /*!< USART read data register not empty */
+#define USART_FLAG_IDLE (0x00000010U) /*!< USART idle flag */
+#define USART_FLAG_ORE (0x00000008U) /*!< USART overrun error */
+#define USART_FLAG_NE (0x00000004U) /*!< USART noise error */
+#define USART_FLAG_FE (0x00000002U) /*!< USART frame error */
+#define USART_FLAG_PE (0x00000001U) /*!< USART parity error */
+/**
+ * @}
+ */
+
+/** @defgroup USART_Interrupt_definition USART Interrupts Definition
+ * Elements values convention: 0000ZZZZ0XXYYYYYb
+ * - YYYYY : Interrupt source position in the XX register (5bits)
+ * - XX : Interrupt source register (2bits)
+ * - 01: CR1 register
+ * - 10: CR2 register
+ * - 11: CR3 register
+ * - ZZZZ : Flag position in the ISR register(4bits)
+ * @{
+ */
+
+#define USART_IT_PE ((uint16_t)0x0028U) /*!< USART parity error interruption */
+#define USART_IT_TXE ((uint16_t)0x0727U) /*!< USART transmit data register empty interruption */
+#define USART_IT_TC ((uint16_t)0x0626U) /*!< USART transmission complete interruption */
+#define USART_IT_RXNE ((uint16_t)0x0525U) /*!< USART read data register not empty interruption */
+#define USART_IT_IDLE ((uint16_t)0x0424U) /*!< USART idle interruption */
+#define USART_IT_ERR ((uint16_t)0x0060U) /*!< USART error interruption */
+#define USART_IT_ORE ((uint16_t)0x0300U) /*!< USART overrun error interruption */
+#define USART_IT_NE ((uint16_t)0x0200U) /*!< USART noise error interruption */
+#define USART_IT_FE ((uint16_t)0x0100U) /*!< USART frame error interruption */
+/**
+ * @}
+ */
+
+/** @defgroup USART_IT_CLEAR_Flags USART Interruption Clear Flags
+ * @{
+ */
+#define USART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
+#define USART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
+#define USART_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */
+#define USART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
+#define USART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
+#define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
+#define USART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */
+/**
+ * @}
+ */
+
+/** @defgroup USART_Interruption_Mask USART Interruption Flags Mask
+ * @{
+ */
+#define USART_IT_MASK ((uint16_t)0x001FU) /*!< USART interruptions flags mask */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup USART_Exported_Macros USART Exported Macros
+ * @{
+ */
+
+/** @brief Reset USART handle state.
+ * @param __HANDLE__ USART handle.
+ * @retval None
+ */
+#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
+
+/** @brief Flush the USART Data registers.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_FLUSH_DRREGISTER(__HANDLE__) \
+ do{ \
+ SET_BIT((__HANDLE__)->Instance->RQR, USART_RXDATA_FLUSH_REQUEST); \
+ SET_BIT((__HANDLE__)->Instance->RQR, USART_TXDATA_FLUSH_REQUEST); \
+ } while(0U)
+
+/** @brief Check whether the specified USART flag is set or not.
+ * @param __HANDLE__ specifies the USART Handle
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg @ref USART_FLAG_REACK Receive enable acknowledge flag
+ * @arg @ref USART_FLAG_TEACK Transmit enable acknowledge flag
+ * @arg @ref USART_FLAG_BUSY Busy flag
+ * @arg @ref USART_FLAG_CTS CTS Change flag
+ * @arg @ref USART_FLAG_TXE Transmit data register empty flag
+ * @arg @ref USART_FLAG_TC Transmission Complete flag
+ * @arg @ref USART_FLAG_RXNE Receive data register not empty flag
+ * @arg @ref USART_FLAG_IDLE Idle Line detection flag
+ * @arg @ref USART_FLAG_ORE OverRun Error flag
+ * @arg @ref USART_FLAG_NE Noise Error flag
+ * @arg @ref USART_FLAG_FE Framing Error flag
+ * @arg @ref USART_FLAG_PE Parity Error flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the specified USART pending flag.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg @ref USART_CLEAR_PEF
+ * @arg @ref USART_CLEAR_FEF
+ * @arg @ref USART_CLEAR_NEF
+ * @arg @ref USART_CLEAR_OREF
+ * @arg @ref USART_CLEAR_IDLEF
+ * @arg @ref USART_CLEAR_TCF
+ * @arg @ref USART_CLEAR_CTSF
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/** @brief Clear the USART PE pending flag.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF)
+
+/** @brief Clear the USART FE pending flag.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF)
+
+/** @brief Clear the USART NE pending flag.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF)
+
+/** @brief Clear the USART ORE pending flag.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF)
+
+/** @brief Clear the USART IDLE pending flag.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF)
+
+/** @brief Enable the specified USART interrupt.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @param __INTERRUPT__ specifies the USART interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref USART_IT_TC Transmission complete interrupt
+ * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref USART_IT_IDLE Idle line detection interrupt
+ * @arg @ref USART_IT_PE Parity Error interrupt
+ * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
+ * @retval None
+ */
+#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & 0xFFU) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+ ((((__INTERRUPT__) & 0xFFU) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))))
+
+/** @brief Disable the specified USART interrupt.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @param __INTERRUPT__ specifies the USART interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref USART_IT_TC Transmission complete interrupt
+ * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref USART_IT_IDLE Idle line detection interrupt
+ * @arg @ref USART_IT_PE Parity Error interrupt
+ * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
+ * @retval None
+ */
+#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & 0xFFU) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+ ((((__INTERRUPT__) & 0xFFU) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))))
+
+
+/** @brief Check whether the specified USART interrupt has occurred or not.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @param __IT__ specifies the USART interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref USART_IT_TC Transmission complete interrupt
+ * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref USART_IT_IDLE Idle line detection interrupt
+ * @arg @ref USART_IT_ORE OverRun Error interrupt
+ * @arg @ref USART_IT_NE Noise Error interrupt
+ * @arg @ref USART_IT_FE Framing Error interrupt
+ * @arg @ref USART_IT_PE Parity Error interrupt
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_USART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U)))
+
+/** @brief Check whether the specified USART interrupt source is enabled or not.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @param __IT__ specifies the USART interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref USART_IT_TC Transmission complete interrupt
+ * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref USART_IT_IDLE Idle line detection interrupt
+ * @arg @ref USART_IT_ORE OverRun Error interrupt
+ * @arg @ref USART_IT_NE Noise Error interrupt
+ * @arg @ref USART_IT_FE Framing Error interrupt
+ * @arg @ref USART_IT_PE Parity Error interrupt
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2U)? \
+ (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (1U << \
+ (((uint16_t)(__IT__)) & USART_IT_MASK)))
+
+
+/** @brief Clear the specified USART ISR flag, in setting the proper ICR register flag.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
+ * to clear the corresponding interrupt.
+ * This parameter can be one of the following values:
+ * @arg @ref USART_CLEAR_PEF Parity Error Clear Flag
+ * @arg @ref USART_CLEAR_FEF Framing Error Clear Flag
+ * @arg @ref USART_CLEAR_NEF Noise detected Clear Flag
+ * @arg @ref USART_CLEAR_OREF OverRun Error Clear Flag
+ * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag
+ * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag
+ * @arg @ref USART_CLEAR_CTSF CTS Interrupt Clear Flag
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
+
+/** @brief Set a specific USART request flag.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @param __REQ__ specifies the request flag to set.
+ * This parameter can be one of the following values:
+ * @arg @ref USART_RXDATA_FLUSH_REQUEST Receive Data flush Request
+ * @arg @ref USART_TXDATA_FLUSH_REQUEST Transmit data flush Request
+ *
+ * @retval None
+ */
+#define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (__REQ__))
+
+/** @brief Enable the USART one bit sample method.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+
+/** @brief Disable the USART one bit sample method.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
+
+/** @brief Enable USART.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+
+/** @brief Disable USART.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+
+/**
+ * @}
+ */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup USART_Private_Macros USART Private Macros
+ * @{
+ */
+
+/** @brief Check USART Baud rate.
+ * @param __BAUDRATE__ Baudrate specified by the user.
+ * The maximum Baud Rate is derived from the maximum clock on F3 (i.e. 72 MHz)
+ * divided by the smallest oversampling used on the USART (i.e. 8).
+ * @retval Test result (TRUE or FALSE).
+ */
+#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 9000001U)
+
+/**
+ * @brief Ensure that USART frame number of stop bits is valid.
+ * @param __STOPBITS__ USART frame number of stop bits.
+ * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
+ */
+#define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_0_5) || \
+ ((__STOPBITS__) == USART_STOPBITS_1) || \
+ ((__STOPBITS__) == USART_STOPBITS_1_5) || \
+ ((__STOPBITS__) == USART_STOPBITS_2))
+
+/**
+ * @brief Ensure that USART frame parity is valid.
+ * @param __PARITY__ USART frame parity.
+ * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
+ */
+#define IS_USART_PARITY(__PARITY__) (((__PARITY__) == USART_PARITY_NONE) || \
+ ((__PARITY__) == USART_PARITY_EVEN) || \
+ ((__PARITY__) == USART_PARITY_ODD))
+
+/**
+ * @brief Ensure that USART communication mode is valid.
+ * @param __MODE__ USART communication mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
+
+/**
+ * @brief Ensure that USART clock state is valid.
+ * @param __CLOCK__ USART clock state.
+ * @retval SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid)
+ */
+#define IS_USART_CLOCK(__CLOCK__) (((__CLOCK__) == USART_CLOCK_DISABLE) || \
+ ((__CLOCK__) == USART_CLOCK_ENABLE))
+
+/**
+ * @brief Ensure that USART frame polarity is valid.
+ * @param __CPOL__ USART frame polarity.
+ * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
+ */
+#define IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))
+
+/**
+ * @brief Ensure that USART frame phase is valid.
+ * @param __CPHA__ USART frame phase.
+ * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
+ */
+#define IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))
+
+/**
+ * @brief Ensure that USART frame last bit clock pulse setting is valid.
+ * @param __LASTBIT__ USART frame last bit clock pulse setting.
+ * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
+ */
+#define IS_USART_LASTBIT(__LASTBIT__) (((__LASTBIT__) == USART_LASTBIT_DISABLE) || \
+ ((__LASTBIT__) == USART_LASTBIT_ENABLE))
+
+/**
+ * @brief Ensure that USART request parameter is valid.
+ * @param __PARAM__ USART request parameter.
+ * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
+ */
+#define IS_USART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \
+ ((__PARAM__) == USART_TXDATA_FLUSH_REQUEST))
+
+/**
+ * @}
+ */
+
+/* Include USART HAL Extended module */
+#include "stm32f3xx_hal_usart_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup USART_Exported_Functions USART Exported Functions
+ * @{
+ */
+
+/** @addtogroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
+void HAL_USART_MspInit(USART_HandleTypeDef *husart);
+void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart);
+
+void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
+void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
+void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart);
+
+/**
+ * @}
+ */
+
+/* Peripheral Control functions ***********************************************/
+
+/** @addtogroup USART_Exported_Functions_Group3 Peripheral State and Error functions
+ * @{
+ */
+
+/* Peripheral State and Error functions ***************************************/
+HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
+uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_USART_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Inc/stm32f3xx_hal_usart_ex.h b/Inc/stm32f3xx_hal_usart_ex.h
new file mode 100644
index 0000000..11c50b1
--- /dev/null
+++ b/Inc/stm32f3xx_hal_usart_ex.h
@@ -0,0 +1,322 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_usart_ex.h
+ * @author MCD Application Team
+ * @brief Header file of USART HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_USART_EX_H
+#define __STM32F3xx_HAL_USART_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup USARTEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup USARTEx_Exported_Constants USARTEx Exported Constants
+ * @{
+ */
+
+/** @defgroup USARTEx_Word_Length USARTEx Word Length
+ * @{
+ */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F334x8) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long USART frame */
+#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */
+#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long USART frame */
+#else
+#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */
+#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M) /*!< 9-bit long USART frame */
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F334x8 || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup USARTEx_Private_Macros USARTEx Private Macros
+ * @{
+ */
+
+/** @brief Report the USART clock source.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @param __CLOCKSOURCE__ output variable.
+ * @retval the USART clocking source, written in __CLOCKSOURCE__.
+ */
+#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0U)
+#else
+#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK2: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
+ case RCC_USART2CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART2CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART2CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART2CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \
+ { \
+ case RCC_USART3CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART3CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART3CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART3CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0U)
+#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+/** @brief Compute the USART mask to apply to retrieve the received data
+ * according to the word length and to the parity bits activation.
+ * @note If PCE = 1, the parity bit is not included in the data extracted
+ * by the reception API().
+ * This masking operation is not carried out in the case of
+ * DMA transfers.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @retval None, the mask to apply to USART RDR register is stored in (__HANDLE__)->Mask field.
+ */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F334x8) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define USART_MASK_COMPUTATION(__HANDLE__) \
+ do { \
+ if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x01FFU ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x00FFU ; \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x00FFU ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x007FU ; \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x007FU ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x003FU ; \
+ } \
+ } \
+} while(0U)
+#else
+#define USART_MASK_COMPUTATION(__HANDLE__) \
+ do { \
+ if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x01FFU ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x00FFU ; \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x00FFU ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x007FU ; \
+ } \
+ } \
+} while(0U)
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F334x8 || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+
+/**
+ * @brief Ensure that USART frame length is valid.
+ * @param __LENGTH__ USART frame length.
+ * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+ */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F334x8) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_7B) || \
+ ((__LENGTH__) == USART_WORDLENGTH_8B) || \
+ ((__LENGTH__) == USART_WORDLENGTH_9B))
+#else
+#define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_8B) || \
+ ((__LENGTH__) == USART_WORDLENGTH_9B))
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F334x8 || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_USART_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Inc/stm32f3xx_hal_wwdg.h b/Inc/stm32f3xx_hal_wwdg.h
new file mode 100644
index 0000000..e77336d
--- /dev/null
+++ b/Inc/stm32f3xx_hal_wwdg.h
@@ -0,0 +1,283 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_wwdg.h
+ * @author MCD Application Team
+ * @brief Header file of WWDG HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_WWDG_H
+#define __STM32F3xx_HAL_WWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup WWDG
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup WWDG_Exported_Types WWDG Exported Types
+ * @{
+ */
+
+/**
+ * @brief WWDG Init structure definition
+ */
+typedef struct
+{
+ uint32_t Prescaler; /*!< Specifies the prescaler value of the WWDG.
+ This parameter can be a value of @ref WWDG_Prescaler */
+
+ uint32_t Window; /*!< Specifies the WWDG window value to be compared to the downcounter.
+ This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7FU */
+
+ uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value.
+ This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7FU */
+
+ uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interupt is enable or not.
+ This parameter can be a value of @ref WWDG_EWI_Mode */
+
+}WWDG_InitTypeDef;
+
+/**
+ * @brief WWDG handle Structure definition
+ */
+typedef struct
+{
+ WWDG_TypeDef *Instance; /*!< Register base address */
+
+ WWDG_InitTypeDef Init; /*!< WWDG required parameters */
+
+}WWDG_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup WWDG_Exported_Constants WWDG Exported Constants
+ * @{
+ */
+
+/** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition
+ * @{
+ */
+#define WWDG_IT_EWI WWDG_CFR_EWI /*!< Early wakeup interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Flag_definition WWDG Flag definition
+ * @brief WWDG Flag definition
+ * @{
+ */
+#define WWDG_FLAG_EWIF WWDG_SR_EWIF /*!< Early wakeup interrupt flag */
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Prescaler WWDG Prescaler
+ * @{
+ */
+#define WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096U)/1U */
+#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096U)/2U */
+#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096U)/4U */
+#define WWDG_PRESCALER_8 WWDG_CFR_WDGTB /*!< WWDG counter clock = (PCLK1/4096U)/8U */
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_EWI_Mode WWDG Early Wakeup Interrupt Mode
+ * @{
+ */
+#define WWDG_EWI_DISABLE 0x00000000u /*!< EWI Disable */
+#define WWDG_EWI_ENABLE WWDG_CFR_EWI /*!< EWI Enable */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @defgroup WWDG_Private_Macros WWDG Private Macros
+ * @{
+ */
+#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \
+ ((__PRESCALER__) == WWDG_PRESCALER_2) || \
+ ((__PRESCALER__) == WWDG_PRESCALER_4) || \
+ ((__PRESCALER__) == WWDG_PRESCALER_8))
+
+#define IS_WWDG_WINDOW(__WINDOW__) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))
+
+#define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))
+
+#define IS_WWDG_EWI_MODE(__MODE__) (((__MODE__) == WWDG_EWI_ENABLE) || \
+ ((__MODE__) == WWDG_EWI_DISABLE))
+/**
+ * @}
+ */
+
+
+/* Exported macros ------------------------------------------------------------*/
+
+/** @defgroup WWDG_Exported_Macros WWDG Exported Macros
+ * @{
+ */
+
+/**
+ * @brief Enable the WWDG peripheral.
+ * @param __HANDLE__ WWDG handle
+ * @retval None
+ */
+#define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
+
+/**
+ * @brief Enable the WWDG early wakeup interrupt.
+ * @param __HANDLE__ WWDG handle
+ * @param __INTERRUPT__ specifies the interrupt to enable.
+ * This parameter can be one of the following values:
+ * @arg WWDG_IT_EWI: Early wakeup interrupt
+ * @note Once enabled this interrupt cannot be disabled except by a system reset.
+ * @retval None
+ */
+#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
+
+/**
+ * @brief Check whether the selected WWDG interrupt has occurred or not.
+ * @param __HANDLE__ WWDG handle
+ * @param __INTERRUPT__ specifies the it to check.
+ * This parameter can be one of the following values:
+ * @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT
+ * @retval The new state of WWDG_FLAG (SET or RESET).
+ */
+#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
+
+/** @brief Clear the WWDG interrupt pending bits.
+ * bits to clear the selected interrupt pending bits.
+ * @param __HANDLE__ WWDG handle
+ * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
+ * This parameter can be one of the following values:
+ * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
+ */
+#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified WWDG flag is set or not.
+ * @param __HANDLE__ WWDG handle
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
+ * @retval The new state of WWDG_FLAG (SET or RESET).
+ */
+#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Clear the WWDG's pending flags.
+ * @param __HANDLE__ WWDG handle
+ * @param __FLAG__ specifies the flag to clear.
+ * This parameter can be one of the following values:
+ * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
+ * @retval None
+ */
+#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
+
+/** @brief Check whether the specified WWDG interrupt source is enabled or not.
+ * @param __HANDLE__ WWDG Handle.
+ * @param __INTERRUPT__ specifies the WWDG interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg WWDG_IT_EWI: Early Wakeup Interrupt
+ * @retval state of __INTERRUPT__ (TRUE or FALSE).
+ */
+#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup WWDG_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup WWDG_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
+void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
+/**
+ * @}
+ */
+
+/** @addtogroup WWDG_Exported_Functions_Group2
+ * @{
+ */
+/* I/O operation functions ******************************************************/
+HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg);
+void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
+void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_WWDG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_ll_adc.h b/Inc/stm32f3xx_ll_adc.h
new file mode 100644
index 0000000..dbf5612
--- /dev/null
+++ b/Inc/stm32f3xx_ll_adc.h
@@ -0,0 +1,10833 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_adc.h
+ * @author MCD Application Team
+ * @brief Header file of ADC LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_LL_ADC_H
+#define __STM32F3xx_LL_ADC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx.h"
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+/* Note: Devices of STM32F3 serie embed 1 out of 2 different ADC IP. */
+/* - STM32F30x, STM32F31x, STM32F32x, STM32F33x, STM32F35x, STM32F39x: */
+/* ADC IP 5Msamples/sec, from 1 to 4 ADC instances and other specific */
+/* features (refer to reference manual). */
+/* - STM32F37x: */
+/* ADC IP 1Msamples/sec, 1 ADC instance */
+/* This file contains the drivers of these ADC IP, located in 2 area */
+/* delimited by compilation switches. */
+
+#if defined(ADC5_V1_1)
+
+#if defined (ADC1) || defined (ADC2) || defined (ADC3) || defined (ADC4)
+
+/** @defgroup ADC_LL ADC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup ADC_LL_Private_Constants ADC Private Constants
+ * @{
+ */
+
+/* Internal mask for ADC group regular sequencer: */
+/* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
+/* - sequencer register offset */
+/* - sequencer rank bits position into the selected register */
+
+/* Internal register offset for ADC group regular sequencer configuration */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_SQR1_REGOFFSET ((uint32_t)0x00000000U)
+#define ADC_SQR2_REGOFFSET ((uint32_t)0x00000100U)
+#define ADC_SQR3_REGOFFSET ((uint32_t)0x00000200U)
+#define ADC_SQR4_REGOFFSET ((uint32_t)0x00000300U)
+
+#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
+#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
+
+/* Definition of ADC group regular sequencer bits information to be inserted */
+/* into ADC group regular sequencer ranks literals definition. */
+#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ1) */
+#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ((uint32_t)12U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ2) */
+#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS ((uint32_t)18U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ3) */
+#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ4) */
+#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ5) */
+#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ6) */
+#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ((uint32_t)12U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */
+#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ((uint32_t)18U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */
+#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */
+#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ10) */
+#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ11) */
+#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS ((uint32_t)12U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ12) */
+#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ((uint32_t)18U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ13) */
+#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ14) */
+#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ15) */
+#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ16) */
+
+
+
+/* Internal mask for ADC group injected sequencer: */
+/* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
+/* - data register offset */
+/* - sequencer rank bits position into the selected register */
+
+/* Internal register offset for ADC group injected data register */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_JDR1_REGOFFSET ((uint32_t)0x00000000U)
+#define ADC_JDR2_REGOFFSET ((uint32_t)0x00000100U)
+#define ADC_JDR3_REGOFFSET ((uint32_t)0x00000200U)
+#define ADC_JDR4_REGOFFSET ((uint32_t)0x00000300U)
+
+#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
+#define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
+
+/* Definition of ADC group injected sequencer bits information to be inserted */
+/* into ADC group injected sequencer ranks literals definition. */
+#define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS ((uint32_t) 8U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ1) */
+#define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS ((uint32_t)14U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ2) */
+#define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ3) */
+#define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS ((uint32_t)26U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ4) */
+
+
+
+/* Internal mask for ADC group regular trigger: */
+/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
+/* - regular trigger source */
+/* - regular trigger edge */
+#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
+
+/* Mask containing trigger source masks for each of possible */
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
+#define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0U)) | \
+ ((ADC_CFGR_EXTSEL) << (4U * 1U)) | \
+ ((ADC_CFGR_EXTSEL) << (4U * 2U)) | \
+ ((ADC_CFGR_EXTSEL) << (4U * 3U)) )
+
+/* Mask containing trigger edge masks for each of possible */
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
+#define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0U)) | \
+ ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1U)) | \
+ ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2U)) | \
+ ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3U)) )
+
+/* Definition of ADC group regular trigger bits information. */
+#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_CFGR_EXTSEL) */
+#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_CFGR_EXTEN) */
+
+
+
+/* Internal definitions for ADC group regular trigger sources: */
+/* To differentiate into literal LL_ADC_REG_TRIG_x the trigger sources */
+/* depending on ADC instances ADC1, ADC2, ADC3, ADC4 (if ADC instance is */
+/* available on the selected device). */
+
+#if defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F303xE) || defined(STM32F398xx)
+/* Internal mask offset for ADC group injected trigger sources */
+/* available only on specific ADC instances. */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_REG_TRIG_EXT_INST_ADC12 ((uint32_t)0x00000001U) /* Marker for differentiation of ADC group regular external trigger available only on ADC instance: ADC1, ADC2 */
+#define ADC_REG_TRIG_EXT_INST_ADC34 ((uint32_t)0x00000002U) /* Marker for differentiation of ADC group regular external trigger available only on ADC instance: ADC3, ADC4 */
+#endif
+
+/* Internal mask for ADC group injected trigger: */
+/* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */
+/* - injected trigger source */
+/* - injected trigger edge */
+#define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
+
+/* Mask containing trigger source masks for each of possible */
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
+#define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0U)) | \
+ ((ADC_JSQR_JEXTSEL) << (4U * 1U)) | \
+ ((ADC_JSQR_JEXTSEL) << (4U * 2U)) | \
+ ((ADC_JSQR_JEXTSEL) << (4U * 3U)) )
+
+/* Mask containing trigger edge masks for each of possible */
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
+#define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0U)) | \
+ ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 1U)) | \
+ ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 2U)) | \
+ ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 3U)) )
+
+/* Definition of ADC group injected trigger bits information. */
+#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS ((uint32_t) 2U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JEXTSEL) */
+#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JEXTEN) */
+
+
+
+/* Internal definitions for ADC group injected trigger sources: */
+/* To differentiate into literal LL_ADC_INJ_TRIG_x the trigger sources */
+/* depending on ADC instances ADC1, ADC2, ADC3, ADC4 (if ADC instance is */
+/* available on the selected device). */
+
+#if defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F303xE) || defined(STM32F398xx)
+/* Internal mask offset for ADC group injected trigger sources */
+/* available only on specific ADC instances. */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_INJ_TRIG_EXT_INST_ADC12 ((uint32_t)0x00000001U) /* Marker for differentiation of ADC group injected external trigger available only on ADC instance: ADC1, ADC2 */
+#define ADC_INJ_TRIG_EXT_INST_ADC34 ((uint32_t)0x00000002U) /* Marker for differentiation of ADC group injected external trigger available only on ADC instance: ADC3, ADC4 */
+#endif
+
+
+
+
+/* Internal mask for ADC channel: */
+/* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
+/* - channel identifier defined by number */
+/* - channel identifier defined by bitfield */
+/* - channel differentiation between external channels (connected to */
+/* GPIO pins) and internal channels (connected to internal paths) */
+/* - channel sampling time defined by SMPRx register offset */
+/* and SMPx bits positions into SMPRx register */
+#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH)
+#define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)
+#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ((uint32_t)26U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
+#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
+/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
+#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
+
+/* Channel differentiation between external and internal channels */
+#define ADC_CHANNEL_ID_INTERNAL_CH ((uint32_t)0x80000000U) /* Marker of internal channel */
+#define ADC_CHANNEL_ID_INTERNAL_CH_2 ((uint32_t)0x00080000U) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
+#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
+
+/* Internal register offset for ADC channel sampling time configuration */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_SMPR1_REGOFFSET ((uint32_t)0x00000000U)
+#define ADC_SMPR2_REGOFFSET ((uint32_t)0x02000000U)
+#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
+
+#define ADC_CHANNEL_SMPx_BITOFFSET_MASK ((uint32_t)0x01F00000U)
+#define ADC_CHANNEL_SMPx_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
+
+/* Definition of channels ID number information to be inserted into */
+/* channels literals definition. */
+#define ADC_CHANNEL_0_NUMBER ((uint32_t)0x00000000U)
+#define ADC_CHANNEL_1_NUMBER ( ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_2_NUMBER ( ADC_CFGR_AWD1CH_1 )
+#define ADC_CHANNEL_3_NUMBER ( ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_4_NUMBER ( ADC_CFGR_AWD1CH_2 )
+#define ADC_CHANNEL_5_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_6_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )
+#define ADC_CHANNEL_7_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_8_NUMBER ( ADC_CFGR_AWD1CH_3 )
+#define ADC_CHANNEL_9_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_10_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 )
+#define ADC_CHANNEL_11_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_12_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 )
+#define ADC_CHANNEL_13_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_14_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )
+#define ADC_CHANNEL_15_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4 )
+#define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1 )
+
+/* Definition of channels ID bitfield information to be inserted into */
+/* channels literals definition. */
+#define ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)
+#define ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)
+#define ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)
+#define ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3)
+#define ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4)
+#define ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5)
+#define ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6)
+#define ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7)
+#define ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8)
+#define ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9)
+#define ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10)
+#define ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11)
+#define ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12)
+#define ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13)
+#define ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14)
+#define ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15)
+#define ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16)
+#define ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17)
+#define ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18)
+
+/* Definition of channels sampling time information to be inserted into */
+/* channels literals definition. */
+#define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP0) */
+#define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP1) */
+#define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP2) */
+#define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP3) */
+#define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP4) */
+#define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP5) */
+#define ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP6) */
+#define ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP7) */
+#define ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP8) */
+#define ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP9) */
+#define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP10) */
+#define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP11) */
+#define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP12) */
+#define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP13) */
+#define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP14) */
+#define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP15) */
+#define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP16) */
+#define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP17) */
+#define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP18) */
+
+
+/* Internal mask for ADC mode single or differential ended: */
+/* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL */
+/* the relevant bits for: */
+/* (concatenation of multiple bits used in different registers) */
+/* - ADC calibration: calibration start, calibration factor get or set */
+/* - ADC channels: set each ADC channel ending mode */
+#define ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF)
+#define ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)
+#define ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
+#define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_5) /* Bit chosen to perform of shift when single mode is selected, shift value out of channels bits range. */
+
+
+/* Internal mask for ADC analog watchdog: */
+/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
+/* (concatenation of multiple bits used in different analog watchdogs, */
+/* (feature of several watchdogs not available on all STM32 families)). */
+/* - analog watchdog 1: monitored channel defined by number, */
+/* selection of ADC group (ADC groups regular and-or injected). */
+/* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */
+/* selection on groups. */
+
+/* Internal register offset for ADC analog watchdog channel configuration */
+#define ADC_AWD_CR1_REGOFFSET ((uint32_t)0x00000000U)
+#define ADC_AWD_CR2_REGOFFSET ((uint32_t)0x00100000U)
+#define ADC_AWD_CR3_REGOFFSET ((uint32_t)0x00200000U)
+
+/* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
+/* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
+#define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
+#define ADC_AWD_CR12_REGOFFSETGAP_VAL ((uint32_t)0x00000024U)
+
+#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
+
+#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
+#define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
+#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
+
+/* Internal register offset for ADC analog watchdog threshold configuration */
+#define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
+#define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
+#define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)
+#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
+
+
+/* Internal mask for ADC offset: */
+/* Internal register offset for ADC offset number configuration */
+#define ADC_OFR1_REGOFFSET ((uint32_t)0x00000000U)
+#define ADC_OFR2_REGOFFSET ((uint32_t)0x00000001U)
+#define ADC_OFR3_REGOFFSET ((uint32_t)0x00000002U)
+#define ADC_OFR4_REGOFFSET ((uint32_t)0x00000003U)
+#define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
+
+
+/* ADC registers bits positions */
+#define ADC_CFGR_RES_BITOFFSET_POS ((uint32_t) 3U) /* Value equivalent to POSITION_VAL(ADC_CFGR_RES) */
+#define ADC_CFGR_AWD1SGL_BITOFFSET_POS ((uint32_t)22U) /* Value equivalent to POSITION_VAL(ADC_CFGR_AWD1SGL) */
+#define ADC_CFGR_AWD1EN_BITOFFSET_POS ((uint32_t)23U) /* Value equivalent to POSITION_VAL(ADC_CFGR_AWD1EN) */
+#define ADC_CFGR_JAWD1EN_BITOFFSET_POS ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_CFGR_JAWD1EN) */
+#define ADC_TR1_HT1_BITOFFSET_POS ((uint32_t)16U) /* Value equivalent to POSITION_VAL(ADC_TR1_HT1) */
+
+
+/* ADC registers bits groups */
+#define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
+
+
+/* ADC internal channels related definitions */
+/* Internal voltage reference VrefInt */
+#define VREFINT_CAL_ADDR ((uint16_t*) ((uint32_t)0x1FFFF7BAU)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
+#define VREFINT_CAL_VREF ((uint32_t) 3300U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
+/* Temperature sensor */
+#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) ((uint32_t)0x1FFFF7B8U)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32F3, temperature sensor ADC raw data acquired at temperature 25 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
+#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) ((uint32_t)0x1FFFF7C2U)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32F3, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
+#define TEMPSENSOR_CAL1_TEMP (( int32_t) 25) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
+#define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
+#define TEMPSENSOR_CAL_VREFANALOG ((uint32_t) 3300U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
+
+
+/**
+ * @}
+ */
+
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup ADC_LL_Private_Macros ADC Private Macros
+ * @{
+ */
+
+/**
+ * @brief Driver macro reserved for internal use: isolate bits with the
+ * selected mask and shift them to the register LSB
+ * (shift mask on register position bit 0).
+ * @param __BITS__ Bits in register 32 bits
+ * @param __MASK__ Mask in register 32 bits
+ * @retval Bits in register 32 bits
+ */
+#define __ADC_MASK_SHIFT(__BITS__, __MASK__) \
+ (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
+
+/**
+ * @brief Driver macro reserved for internal use: set a pointer to
+ * a register from a register basis from which an offset
+ * is applied.
+ * @param __REG__ Register basis from which the offset is applied.
+ * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
+ * @retval Pointer to register address
+ */
+#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
+ ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
+
+/**
+ * @}
+ */
+
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief Structure definition of some features of ADC common parameters
+ * and multimode
+ * (all ADC instances belonging to the same ADC common instance).
+ * @note The setting of these parameters by function @ref LL_ADC_CommonInit()
+ * is conditioned to ADC instances state (all ADC instances
+ * sharing the same ADC common instance):
+ * All ADC instances sharing the same ADC common instance must be
+ * disabled.
+ */
+typedef struct
+{
+ uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
+ This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
+ @note On this STM32 serie, if ADC group injected is used, some
+ clock ratio constraints between ADC clock and AHB clock
+ must be respected. Refer to reference manual.
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+ uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
+ This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */
+
+ uint32_t MultiDMATransfer; /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA.
+ This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */
+
+ uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases.
+ This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+} LL_ADC_CommonInitTypeDef;
+
+/**
+ * @brief Structure definition of some features of ADC instance.
+ * @note These parameters have an impact on ADC scope: ADC instance.
+ * Affects both group regular and group injected (availability
+ * of ADC group injected depends on STM32 families).
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Instance .
+ * @note The setting of these parameters by function @ref LL_ADC_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 families. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ */
+typedef struct
+{
+ uint32_t Resolution; /*!< Set ADC resolution.
+ This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
+
+ uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
+ This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
+
+ uint32_t LowPowerMode; /*!< Set ADC low power mode.
+ This parameter can be a value of @ref ADC_LL_EC_LP_MODE
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */
+
+} LL_ADC_InitTypeDef;
+
+/**
+ * @brief Structure definition of some features of ADC group regular.
+ * @note These parameters have an impact on ADC scope: ADC group regular.
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+ * (functions with prefix "REG").
+ * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 families. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ */
+typedef struct
+{
+ uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
+ This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
+ @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge
+ (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
+ In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge().
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
+
+ uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
+ This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
+
+ uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
+ This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
+ @note This parameter has an effect only if group regular sequencer is enabled
+ (scan length of 2 ranks or more).
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
+
+ uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
+ This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
+ Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
+
+ uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
+ This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
+
+ uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun:
+ data preserved or overwritten.
+ This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */
+
+} LL_ADC_REG_InitTypeDef;
+
+/**
+ * @brief Structure definition of some features of ADC group injected.
+ * @note These parameters have an impact on ADC scope: ADC group injected.
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+ * (functions with prefix "INJ").
+ * @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 families. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ */
+typedef struct
+{
+ uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
+ This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
+ @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge
+ (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
+ In case of need to modify trigger edge, use function @ref LL_ADC_INJ_SetTriggerEdge().
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
+
+ uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
+ This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */
+
+ uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
+ This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
+ @note This parameter has an effect only if group injected sequencer is enabled
+ (scan length of 2 ranks or more).
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */
+
+ uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
+ This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
+ Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
+
+} LL_ADC_INJ_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
+ * @{
+ */
+
+/** @defgroup ADC_LL_EC_FLAG ADC flags
+ * @brief Flags defines which can be used with LL_ADC_ReadReg function
+ * @{
+ */
+#define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */
+#define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary conversion */
+#define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence conversions */
+#define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */
+#define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */
+#define LL_ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC flag ADC group injected end of unitary conversion */
+#define LL_ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC flag ADC group injected end of sequence conversions */
+#define LL_ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC flag ADC group injected contexts queue overflow */
+#define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */
+#define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */
+#define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */
+#if defined(ADC_MULTIMODE_SUPPORT)
+#define LL_ADC_FLAG_ADRDY_MST ADC_CSR_ADRDY_MST /*!< ADC flag ADC multimode master instance ready */
+#define LL_ADC_FLAG_ADRDY_SLV ADC_CSR_ADRDY_SLV /*!< ADC flag ADC multimode slave instance ready */
+#define LL_ADC_FLAG_EOC_MST ADC_CSR_EOC_MST /*!< ADC flag ADC multimode master group regular end of unitary conversion */
+#define LL_ADC_FLAG_EOC_SLV ADC_CSR_EOC_SLV /*!< ADC flag ADC multimode slave group regular end of unitary conversion */
+#define LL_ADC_FLAG_EOS_MST ADC_CSR_EOS_MST /*!< ADC flag ADC multimode master group regular end of sequence conversions */
+#define LL_ADC_FLAG_EOS_SLV ADC_CSR_EOS_SLV /*!< ADC flag ADC multimode slave group regular end of sequence conversions */
+#define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR_MST /*!< ADC flag ADC multimode master group regular overrun */
+#define LL_ADC_FLAG_OVR_SLV ADC_CSR_OVR_SLV /*!< ADC flag ADC multimode slave group regular overrun */
+#define LL_ADC_FLAG_EOSMP_MST ADC_CSR_EOSMP_MST /*!< ADC flag ADC multimode master group regular end of sampling phase */
+#define LL_ADC_FLAG_EOSMP_SLV ADC_CSR_EOSMP_SLV /*!< ADC flag ADC multimode slave group regular end of sampling phase */
+#define LL_ADC_FLAG_JEOC_MST ADC_CSR_JEOC_MST /*!< ADC flag ADC multimode master group injected end of unitary conversion */
+#define LL_ADC_FLAG_JEOC_SLV ADC_CSR_JEOC_SLV /*!< ADC flag ADC multimode slave group injected end of unitary conversion */
+#define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOS_MST /*!< ADC flag ADC multimode master group injected end of sequence conversions */
+#define LL_ADC_FLAG_JEOS_SLV ADC_CSR_JEOS_SLV /*!< ADC flag ADC multimode slave group injected end of sequence conversions */
+#define LL_ADC_FLAG_JQOVF_MST ADC_CSR_JQOVF_MST /*!< ADC flag ADC multimode master group injected contexts queue overflow */
+#define LL_ADC_FLAG_JQOVF_SLV ADC_CSR_JQOVF_SLV /*!< ADC flag ADC multimode slave group injected contexts queue overflow */
+#define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1_MST /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */
+#define LL_ADC_FLAG_AWD1_SLV ADC_CSR_AWD1_SLV /*!< ADC flag ADC multimode slave analog watchdog 1 of the ADC slave */
+#define LL_ADC_FLAG_AWD2_MST ADC_CSR_AWD2_MST /*!< ADC flag ADC multimode master analog watchdog 2 of the ADC master */
+#define LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV /*!< ADC flag ADC multimode slave analog watchdog 2 of the ADC slave */
+#define LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST /*!< ADC flag ADC multimode master analog watchdog 3 of the ADC master */
+#define LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV /*!< ADC flag ADC multimode slave analog watchdog 3 of the ADC slave */
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
+ * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
+ * @{
+ */
+#define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */
+#define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion */
+#define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence conversions */
+#define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */
+#define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling phase */
+#define LL_ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC interruption ADC group injected end of unitary conversion */
+#define LL_ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC interruption ADC group injected end of sequence conversions */
+#define LL_ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC interruption ADC group injected contexts queue overflow */
+#define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */
+#define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */
+#define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
+ * @{
+ */
+/* List of ADC registers intended to be used (most commonly) with */
+/* DMA transfer. */
+/* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
+#define LL_ADC_DMA_REG_REGULAR_DATA ((uint32_t)0x00000000U) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
+#if defined(ADC_MULTIMODE_SUPPORT)
+#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI ((uint32_t)0x00000001U) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
+ * @{
+ */
+#define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock without prescaler */
+#define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1 ) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
+#define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
+#define LL_ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000U) /*!< ADC asynchronous clock without prescaler */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
+ * @{
+ */
+/* Note: Other measurement paths to internal channels may be available */
+/* (connections to other peripherals). */
+/* If they are not listed below, they do not require any specific */
+/* path enable. In this case, Access to measurement path is done */
+/* only by selecting the corresponding ADC internal channel. */
+#define LL_ADC_PATH_INTERNAL_NONE ((uint32_t)0x00000000U)/*!< ADC measurement pathes all disabled */
+#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */
+#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel temperature sensor */
+#define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /*!< ADC measurement path to internal channel Vbat */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
+ * @{
+ */
+#define LL_ADC_RESOLUTION_12B ((uint32_t)0x00000000U) /*!< ADC resolution 12 bits */
+#define LL_ADC_RESOLUTION_10B ( ADC_CFGR_RES_0) /*!< ADC resolution 10 bits */
+#define LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_1 ) /*!< ADC resolution 8 bits */
+#define LL_ADC_RESOLUTION_6B (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) /*!< ADC resolution 6 bits */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
+ * @{
+ */
+#define LL_ADC_DATA_ALIGN_RIGHT ((uint32_t)0x00000000U)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
+#define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode
+ * @{
+ */
+#define LL_ADC_LP_MODE_NONE ((uint32_t)0x00000000U) /*!< No ADC low power mode activated */
+#define LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY) /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_OFFSET_NB ADC instance - Offset number
+ * @{
+ */
+#define LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
+#define LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
+#define LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
+#define LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_OFFSET_STATE ADC instance - Offset state
+ * @{
+ */
+#define LL_ADC_OFFSET_DISABLE ((uint32_t)0x00000000U)/*!< ADC offset disabled (among ADC selected offset number 1, 2, 3 or 4) */
+#define LL_ADC_OFFSET_ENABLE (ADC_OFR1_OFFSET1_EN) /*!< ADC offset enabled (among ADC selected offset number 1, 2, 3 or 4) */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
+ * @{
+ */
+#define LL_ADC_GROUP_REGULAR ((uint32_t)0x00000001U) /*!< ADC group regular (available on all STM32 devices) */
+#define LL_ADC_GROUP_INJECTED ((uint32_t)0x00000002U) /*!< ADC group injected (not available on all STM32 devices)*/
+#define LL_ADC_GROUP_REGULAR_INJECTED ((uint32_t)0x00000003U) /*!< ADC both groups regular and injected */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
+ * @{
+ */
+#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
+#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
+#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
+#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
+#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
+#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
+#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
+#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
+#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
+#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
+#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
+#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
+#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
+#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
+#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
+#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
+#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
+#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
+#define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
+#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32F3, ADC channel available only on all ADC instances, but only one ADC instance is allowed to be connected to VrefInt at the same time. */
+#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32F3, ADC channel available only on ADC instance: ADC1. */
+#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On STM32F3, ADC channel available only on ADC instance: ADC1. */
+#if defined(OPAMP1_CSR_OPAMP1EN)
+#define LL_ADC_CHANNEL_VOPAMP1 (LL_ADC_CHANNEL_15 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP1 output. On STM32F3, ADC channel available only on ADC instance: ADC1. */
+#endif
+#if defined(OPAMP2_CSR_OPAMP2EN)
+#define LL_ADC_CHANNEL_VOPAMP2 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP2 output. On STM32F3, ADC channel available only on ADC instance: ADC2. */
+#endif
+#if defined(OPAMP3_CSR_OPAMP3EN)
+#define LL_ADC_CHANNEL_VOPAMP3 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP3 output. On STM32F3, ADC channel available only on ADC instance: ADC3. */
+#endif
+#if defined(OPAMP4_CSR_OPAMP4EN)
+#define LL_ADC_CHANNEL_VOPAMP4 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP4 output. On STM32F3, ADC channel available only on ADC instance: ADC4. */
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
+ * @{
+ */
+#define LL_ADC_REG_TRIG_SOFTWARE ((uint32_t)0x00000000U) /*!< ADC group regular conversion trigger internal: SW start. */
+#if defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F303xE) || defined(STM32F398xx)
+/* ADC group regular external triggers for ADC instances: ADC1, ADC2 (for */
+/* ADC instances ADCx available on the selected device) */
+/* Note: Literal without suffix "ADCxy" means that external trigger */
+/* is available on all ADC instances. */
+/* Note: For devices STM32F303xE, STM32F398xx: some triggers require to set */
+/* register SYSCFG_CFGR4. Refer to reference manual. */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH1_ADC12 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH2_ADC12 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_CH2_ADC12 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO_ADC12 (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM4_CH4_ADC12 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11_ADC12 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC12 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO_ADC12 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC12 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM3_CH4_ADC12 (ADC_CFGR_EXTSEL | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#if defined(STM32F303xE) || defined(STM32F398xx)
+#define LL_ADC_REG_TRIG_EXT_TIM20_TRG0_ADC12 (LL_ADC_REG_TRIG_EXT_TIM1_CH3) /*!< ADC group regular conversion trigger from external IP: TIM20 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM20_TRG02_ADC12 (LL_ADC_REG_TRIG_EXT_TIM2_CH2_ADC12) /*!< ADC group regular conversion trigger from external IP: TIM20 TRGO2. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM20_CH1_ADC12 (LL_ADC_REG_TRIG_EXT_TIM4_CH4_ADC12) /*!< ADC group regular conversion trigger from external IP: TIM20 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM20_CH2_ADC12 (LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC12) /*!< ADC group regular conversion trigger from external IP: TIM20 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM20_CH3_ADC12 (LL_ADC_REG_TRIG_EXT_TIM3_CH4_ADC12) /*!< ADC group regular conversion trigger from external IP: TIM20 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#endif /* STM32F303xE || STM32F398xx */
+
+/* ADC group regular external triggers for ADC instances: ADC3, ADC4 (for */
+/* ADC instances ADCx available on the selected device) */
+/* Note: Literal without suffix "ADCxy" means that external trigger */
+/* is available on all ADC instances. */
+/* Note: For devices STM32F303xE, STM32F398xx: some triggers require to set */
+/* register SYSCFG_CFGR4. Refer to reference manual. */
+#define LL_ADC_REG_TRIG_EXT_TIM3_CH1_ADC34 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_CH3_ADC34 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM8_CH1_ADC34 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO__ADC34 (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_EXTI_LINE2_ADC34 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 2. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM4_CH1_ADC34 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO__ADC34 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO__ADC34 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM7_TRGO_ADC34 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM7 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_CH1_ADC34 (ADC_CFGR_EXTSEL | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 CCx. Trigger edge set to rising edge (default setting). */
+#if defined(STM32F303xE) || defined(STM32F398xx)
+#define LL_ADC_REG_TRIG_EXT_TIM20_TRG0_ADC34 (LL_ADC_REG_TRIG_EXT_EXTI_LINE2_ADC34) /*!< ADC group regular conversion trigger from external IP: TIM20 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM20_TRG02_ADC34 (LL_ADC_REG_TRIG_EXT_TIM4_CH1_ADC34) /*!< ADC group regular conversion trigger from external IP: TIM20 TRGO2. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM20_CH1_ADC34 (LL_ADC_REG_TRIG_EXT_TIM2_CH1_ADC34) /*!< ADC group regular conversion trigger from external IP: TIM20 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#endif /* STM32F303xE || STM32F398xx */
+
+#elif defined(STM32F303x8) || defined(STM32F328xx)
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+
+#elif defined(STM32F334x8)
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG1 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: HRTIM TRG1. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG3 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: HRTIM TRG3. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+
+#elif defined(STM32F302xC) || defined(STM32F302xE)
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+
+#elif defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
+ * @{
+ */
+#define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */
+#define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */
+#define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
+* @{
+*/
+#define LL_ADC_REG_CONV_SINGLE ((uint32_t)0x00000000U) /*!< ADC conversions are performed in single mode: one conversion per trigger */
+#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
+ * @{
+ */
+#define LL_ADC_REG_DMA_TRANSFER_NONE ((uint32_t)0x00000000U) /*!< ADC conversions are not transferred by DMA */
+#define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
+#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
+* @{
+*/
+#define LL_ADC_REG_OVR_DATA_PRESERVED ((uint32_t)0x00000000U)/*!< ADC group regular behavior in case of overrun: data preserved */
+#define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD) /*!< ADC group regular behavior in case of overrun: data overwritten */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
+ * @{
+ */
+#define LL_ADC_REG_SEQ_SCAN_DISABLE ((uint32_t)0x00000000U) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
+ * @{
+ */
+#define LL_ADC_REG_SEQ_DISCONT_DISABLE ((uint32_t)0x00000000U) /*!< ADC group regular sequencer discontinuous mode disable */
+#define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
+#define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
+ * @{
+ */
+#define LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */
+#define LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */
+#define LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */
+#define LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */
+#define LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */
+#define LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */
+#define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */
+#define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */
+#define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */
+#define LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */
+#define LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */
+#define LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */
+#define LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */
+#define LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
+#define LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
+#define LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
+ * @{
+ */
+#define LL_ADC_INJ_TRIG_SOFTWARE ((uint32_t)0x00000000U) /*!< ADC group injected conversion trigger internal: SW start.. Trigger edge set to rising edge (default setting). */
+#if defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F303xE) || defined(STM32F398xx)
+/* ADC group injected external triggers for ADC instances: ADC1, ADC2 (for */
+/* ADC instances ADCx available on the selected device) */
+/* Note: Literal without suffix "ADCxy" means that external trigger */
+/* is available on all ADC instances. */
+/* Note: For devices STM32F303xE, STM32F398xx: some triggers require to set */
+/* register SYSCFG_CFGR4. Refer to reference manual. */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO_ADC12 (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1_ADC12 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4_ADC12 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO_ADC12 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15_ADC12 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC12 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG02. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 TRG02. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH3_ADC12 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH1_ADC12 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO_ADC12 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM6 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM15 TRG0. Trigger edge set to rising edge (default setting). */
+#if defined(STM32F303xE) || defined(STM32F398xx)
+#define LL_ADC_INJ_TRIG_EXT_TIM20_TRGO_ADC12 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1_ADC12) /*!< ADC group injected conversion trigger from external IP: TIM20 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2_ADC12 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15_ADC12) /*!< ADC group injected conversion trigger from external IP: TIM20 TRG02. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM20_CH4_ADC12 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1_ADC12) /*!< ADC group injected conversion trigger from external IP: TIM20 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#endif /* STM32F303xE || STM32F398xx */
+
+/* ADC group injected external triggers for ADC instances: ADC3, ADC4 (for */
+/* ADC instances ADCx available on the selected device) */
+/* Note: Literal without suffix "ADCxy" means that external trigger */
+/* is available on all ADC instances. */
+/* Note: External triggers JEXT2 and JEXT5 are the same (TIM4_CH3 event). */
+/* JEXT2 is the main trigger, JEXT5 is kept as spare trigger for */
+/* future devices. */
+/* Note: For devices STM32F303xE, STM32F398xx: some triggers require to set */
+/* register SYSCFG_CFGR4. Refer to reference manual. */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM4_CH3_ADC34 (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_CH2_ADC34 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4__ADC34 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM4_CH4_ADC34 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO__ADC34 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG02. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 TRG02. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_CH3_ADC34 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO__ADC34 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM7_TRGO_ADC34 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM7 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM15 TRG0. Trigger edge set to rising edge (default setting). */
+#if defined(STM32F303xE) || defined(STM32F398xx)
+#define LL_ADC_INJ_TRIG_EXT_TIM20_TRG_ADC34 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM20 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM20_TRG2_ADC34 (LL_ADC_INJ_TRIG_EXT_TIM1_CH3_ADC34) /*!< ADC group injected conversion trigger from external IP: TIM20 TRG02. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM20_CH2 (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM20 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#endif /* STM32F303xE || STM32F398xx */
+
+#elif defined(STM32F303x8) || defined(STM32F328xx)
+#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG02. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 TRG02. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM6 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM15 TRG0. Trigger edge set to rising edge (default setting). */
+
+#elif defined(STM32F334x8)
+#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG02. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: HRTIM TRG2. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: HRTIM TRG4. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM6 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM15 TRG0. Trigger edge set to rising edge (default setting). */
+
+#elif defined(STM32F302xC) || defined(STM32F302xE)
+#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG02. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM6 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM15 TRG0. Trigger edge set to rising edge (default setting). */
+
+#elif defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG02. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM6 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM15 TRG0. Trigger edge set to rising edge (default setting). */
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
+ * @{
+ */
+#define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */
+#define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 ) /*!< ADC group injected conversion trigger polarity set to falling edge */
+#define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
+* @{
+*/
+#define LL_ADC_INJ_TRIG_INDEPENDENT ((uint32_t)0x00000000U)/*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
+#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE ADC group injected - Context queue mode
+ * @{
+ */
+#define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE ((uint32_t)0x00000000U)/* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */
+#define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
+ * @{
+ */
+#define LL_ADC_INJ_SEQ_SCAN_DISABLE ((uint32_t)0x00000000U) /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
+#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
+#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
+#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
+ * @{
+ */
+#define LL_ADC_INJ_SEQ_DISCONT_DISABLE ((uint32_t)0x00000000U)/*!< ADC group injected sequencer discontinuous mode disable */
+#define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
+ * @{
+ */
+#define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 */
+#define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 2 */
+#define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 3 */
+#define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 4 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
+ * @{
+ */
+#define LL_ADC_SAMPLINGTIME_1CYCLE_5 (0x00000000U) /*!< Sampling time 1.5 ADC clock cycle */
+#define LL_ADC_SAMPLINGTIME_2CYCLES_5 ( ADC_SMPR2_SMP10_0) /*!< Sampling time 2.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_4CYCLES_5 ( ADC_SMPR2_SMP10_1 ) /*!< Sampling time 4.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_7CYCLES_5 ( ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 7.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_19CYCLES_5 (ADC_SMPR2_SMP10_2 ) /*!< Sampling time 19.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_61CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0) /*!< Sampling time 61.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_181CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 ) /*!< Sampling time 181.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_601CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 601.5 ADC clock cycles */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending
+ * @{
+ */
+#define LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */
+#define LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */
+#define LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to both single ended and differential (literal used only to set calibration factors) */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
+ * @{
+ */
+#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
+#define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
+#define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
+ * @{
+ */
+#define LL_ADC_AWD_DISABLE ((uint32_t)0x00000000U) /*!< ADC analog watchdog monitoring disabled */
+#define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
+#define LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
+#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
+#define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
+#define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
+#define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */
+#define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */
+#define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only */
+#define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda */
+#if defined(OPAMP1_CSR_OPAMP1EN)
+#define LL_ADC_AWD_CH_VOPAMP1_REG ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only */
+#define LL_ADC_AWD_CH_VOPAMP1_INJ ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only */
+#define LL_ADC_AWD_CH_VOPAMP1_REG_INJ ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected */
+#endif
+#if defined(OPAMP2_CSR_OPAMP2EN)
+#define LL_ADC_AWD_CH_VOPAMP2_REG ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only */
+#define LL_ADC_AWD_CH_VOPAMP2_INJ ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only */
+#define LL_ADC_AWD_CH_VOPAMP2_REG_INJ ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected */
+#endif
+#if defined(OPAMP3_CSR_OPAMP3EN)
+#define LL_ADC_AWD_CH_VOPAMP3_REG ((LL_ADC_CHANNEL_VOPAMP3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group regular only */
+#define LL_ADC_AWD_CH_VOPAMP3_INJ ((LL_ADC_CHANNEL_VOPAMP3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group injected only */
+#define LL_ADC_AWD_CH_VOPAMP3_REG_INJ ((LL_ADC_CHANNEL_VOPAMP3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by either group regular or injected */
+#endif
+#if defined(OPAMP4_CSR_OPAMP4EN)
+#define LL_ADC_AWD_CH_VOPAMP4_REG ((LL_ADC_CHANNEL_VOPAMP4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group regular only */
+#define LL_ADC_AWD_CH_VOPAMP4_INJ ((LL_ADC_CHANNEL_VOPAMP4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group injected only */
+#define LL_ADC_AWD_CH_VOPAMP4_REG_INJ ((LL_ADC_CHANNEL_VOPAMP4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by either group regular or injected */
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
+ * @{
+ */
+#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_TR1_HT1 ) /*!< ADC analog watchdog threshold high */
+#define LL_ADC_AWD_THRESHOLD_LOW ( ADC_TR1_LT1) /*!< ADC analog watchdog threshold low */
+#define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_TR1_HT1 | ADC_TR1_LT1) /*!< ADC analog watchdog both thresholds high and low concatenated into the same data */
+/**
+ * @}
+ */
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
+ * @{
+ */
+#define LL_ADC_MULTI_INDEPENDENT ((uint32_t)0x00000000U) /*!< ADC dual mode disabled (ADC independent mode) */
+#define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: group regular simultaneous */
+#define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved */
+#define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected simultaneous */
+#define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
+#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
+#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
+#define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer
+ * @{
+ */
+#define LL_ADC_MULTI_REG_DMA_EACH_ADC ((uint32_t)0x00000000U) /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */
+#define LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B ( ADC_CCR_MDMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 12 and 10 bits */
+#define LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B ( ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 8 and 6 bits */
+#define LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 12 and 10 bits */
+#define LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 8 and 6 bits */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
+ * @{
+ */
+#define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE ((uint32_t)0x00000000U) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */
+#define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES ( ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES ( ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES ( ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave
+ * @{
+ */
+#define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */
+#define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV ) /*!< In multimode, selection among several ADC instances: ADC slave */
+#define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */
+/**
+ * @}
+ */
+
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+
+/** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
+ * @note Only ADC IP HW delays are defined in ADC LL driver driver,
+ * not timeout values.
+ * For details on delays values, refer to descriptions in source code
+ * above each literal definition.
+ * @{
+ */
+
+/* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
+/* not timeout values. */
+/* Timeout values for ADC operations are dependent to device clock */
+/* configuration (system clock versus ADC clock), */
+/* and therefore must be defined in user application. */
+/* Indications for estimation of ADC timeout delays, for this */
+/* STM32 serie: */
+/* - ADC calibration time: maximum delay is 112/fADC. */
+/* (refer to device datasheet, parameter "tCAL") */
+/* - ADC enable time: maximum delay is 1 conversion cycle. */
+/* (refer to device datasheet, parameter "tSTAB") */
+/* - ADC disable time: maximum delay should be a few ADC clock cycles */
+/* - ADC stop conversion time: maximum delay should be a few ADC clock */
+/* cycles */
+/* - ADC conversion time: duration depending on ADC clock and ADC */
+/* configuration. */
+/* (refer to device reference manual, section "Timing") */
+
+/* Delay for ADC stabilization time (ADC voltage regulator start-up time) */
+/* Delay set to maximum value (refer to device datasheet, */
+/* parameter "tADCVREG_STUP"). */
+/* Unit: us */
+#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ((uint32_t) 10U) /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */
+
+/* Delay for internal voltage reference stabilization time. */
+/* Delay set to maximum value (refer to device datasheet, */
+/* parameter "tstart_vrefint"). */
+/* Unit: us */
+#define LL_ADC_DELAY_VREFINT_STAB_US ((uint32_t) 12U) /*!< Delay for internal voltage reference stabilization time */
+
+/* Delay for temperature sensor stabilization time. */
+/* Literal set to maximum value (refer to device datasheet, */
+/* parameter "tSTART"). */
+/* Unit: us */
+#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ((uint32_t) 120U) /*!< Delay for temperature sensor stabilization time */
+
+/* Delay required between ADC end of calibration and ADC enable. */
+/* Note: On this STM32 serie, a minimum number of ADC clock cycles */
+/* are required between ADC end of calibration and ADC enable. */
+/* Wait time can be computed in user application by waiting for the */
+/* equivalent number of CPU cycles, by taking into account */
+/* ratio of CPU clock versus ADC clock prescalers. */
+/* Unit: ADC clock cycles. */
+#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ((uint32_t) 4U) /*!< Delay required between ADC end of calibration and ADC enable */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
+ * @{
+ */
+
+/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in ADC register
+ * @param __INSTANCE__ ADC Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in ADC register
+ * @param __INSTANCE__ ADC Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
+ * @{
+ */
+
+/**
+ * @brief Helper macro to get ADC channel number in decimal format
+ * from literals LL_ADC_CHANNEL_x.
+ * @note Example:
+ * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
+ * will return decimal number "4".
+ * @note The input can be a value from functions where a channel
+ * number is returned, either defined with number
+ * or with bitfield (only one bit must be set).
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
+ *
+ * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
+ * (5) On STM32F3, ADC channel available only on all ADC instances, but
+ * only one ADC instance is allowed to be connected to VrefInt at the same time.
+ * @retval Value between Min_Data=0 and Max_Data=18
+ */
+#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
+ ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0U) \
+ ? ( \
+ ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
+ ) \
+ : \
+ ( \
+ POSITION_VAL((__CHANNEL__)) \
+ ) \
+ )
+
+/**
+ * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
+ * from number in decimal format.
+ * @note Example:
+ * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
+ * will return a data equivalent to "LL_ADC_CHANNEL_4".
+ * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
+ *
+ * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
+ * (5) On STM32F3, ADC channel available only on all ADC instances, but
+ * only one ADC instance is allowed to be connected to VrefInt at the same time.\n
+ * (1, 2, 3, 4, 5) For ADC channel read back from ADC register,
+ * comparison with internal channel parameter to be done
+ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+ */
+#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
+ (((__DECIMAL_NB__) <= 9U) \
+ ? ( \
+ ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
+ (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
+ (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
+ ) \
+ : \
+ ( \
+ ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
+ (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
+ (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
+ ) \
+ )
+
+/**
+ * @brief Helper macro to determine whether the selected channel
+ * corresponds to literal definitions of driver.
+ * @note The different literal definitions of ADC channels are:
+ * - ADC internal channel:
+ * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
+ * - ADC external channel (channel connected to a GPIO pin):
+ * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
+ * @note The channel parameter must be a value defined from literal
+ * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+ * LL_ADC_CHANNEL_TEMPSENSOR, ...),
+ * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
+ * must not be a value from functions where a channel number is
+ * returned from ADC registers,
+ * because internal and external channels share the same channel
+ * number in ADC registers. The differentiation is made only with
+ * parameters definitions of driver.
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
+ *
+ * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
+ * (5) On STM32F3, ADC channel available only on all ADC instances, but
+ * only one ADC instance is allowed to be connected to VrefInt at the same time.
+ * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
+ * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
+ */
+#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
+ (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)
+
+/**
+ * @brief Helper macro to convert a channel defined from parameter
+ * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+ * LL_ADC_CHANNEL_TEMPSENSOR, ...),
+ * to its equivalent parameter definition of a ADC external channel
+ * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
+ * @note The channel parameter can be, additionally to a value
+ * defined from parameter definition of a ADC internal channel
+ * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
+ * a value defined from parameter definition of
+ * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
+ * or a value from functions where a channel number is returned
+ * from ADC registers.
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
+ *
+ * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
+ * (5) On STM32F3, ADC channel available only on all ADC instances, but
+ * only one ADC instance is allowed to be connected to VrefInt at the same time.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ */
+#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
+ ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
+
+/**
+ * @brief Helper macro to determine whether the internal channel
+ * selected is available on the ADC instance selected.
+ * @note The channel parameter must be a value defined from parameter
+ * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+ * LL_ADC_CHANNEL_TEMPSENSOR, ...),
+ * must not be a value defined from parameter definition of
+ * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
+ * or a value from functions where a channel number is
+ * returned from ADC registers,
+ * because internal and external channels share the same channel
+ * number in ADC registers. The differentiation is made only with
+ * parameters definitions of driver.
+ * @param __ADC_INSTANCE__ ADC instance
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
+ *
+ * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
+ * (5) On STM32F3, ADC channel available only on all ADC instances, but
+ * only one ADC instance is allowed to be connected to VrefInt at the same time.
+ * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
+ * Value "1" if the internal channel selected is available on the ADC instance selected.
+ */
+#if defined (ADC1) && defined (ADC2) && defined (ADC3) && defined (ADC4)
+#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
+ (((__ADC_INSTANCE__) == ADC1) \
+ ? ( \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) \
+ ) \
+ : \
+ ((__ADC_INSTANCE__) == ADC2) \
+ ? ( \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) \
+ ) \
+ : \
+ ((__ADC_INSTANCE__) == ADC3) \
+ ? ( \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3) \
+ ) \
+ : \
+ ((__ADC_INSTANCE__) == ADC4) \
+ ? ( \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP4) \
+ ) \
+ : \
+ (0U) \
+ )
+#elif defined (ADC1) && defined (ADC2)
+#if defined(OPAMP1_CSR_OPAMP1EN) && defined(OPAMP2_CSR_OPAMP2EN)
+#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
+ (((__ADC_INSTANCE__) == ADC1) \
+ ? ( \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) \
+ ) \
+ : \
+ ((__ADC_INSTANCE__) == ADC2) \
+ ? ( \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) \
+ ) \
+ : \
+ (0U) \
+ )
+#elif defined(OPAMP2_CSR_OPAMP2EN)
+#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
+ (((__ADC_INSTANCE__) == ADC1) \
+ ? ( \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \
+ ) \
+ : \
+ ((__ADC_INSTANCE__) == ADC2) \
+ ? ( \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) \
+ ) \
+ : \
+ (0U) \
+ )
+#else
+#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
+ (((__ADC_INSTANCE__) == ADC1) \
+ ? ( \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) \
+ ) \
+ : \
+ ((__ADC_INSTANCE__) == ADC2) \
+ ? ( \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \
+ ) \
+ : \
+ (0U) \
+ )
+#endif
+#elif defined (ADC1)
+#if defined(OPAMP1_CSR_OPAMP1EN)
+#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
+ ( \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) \
+ )
+#else
+#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
+ ( \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \
+ )
+#endif
+#endif
+
+/**
+ * @brief Helper macro to define ADC analog watchdog parameter:
+ * define a single channel to monitor with analog watchdog
+ * from sequencer channel and groups definition.
+ * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
+ * Example:
+ * LL_ADC_SetAnalogWDMonitChannels(
+ * ADC1, LL_ADC_AWD1,
+ * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
+ *
+ * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
+ * (5) On STM32F3, ADC channel available only on all ADC instances, but
+ * only one ADC instance is allowed to be connected to VrefInt at the same time.\n
+ * (1, 2, 3, 4, 5) For ADC channel read back from ADC register,
+ * comparison with internal channel parameter to be done
+ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+ * @param __GROUP__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_GROUP_REGULAR
+ * @arg @ref LL_ADC_GROUP_INJECTED
+ * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_AWD_DISABLE
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)(5)
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(5)
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (5)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP1_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG (0)(2)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP2_INJ (0)(2)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG_INJ (2)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP3_REG (0)(3)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP3_INJ (0)(3)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP3_REG_INJ (3)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG (0)(4)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP4_INJ (0)(4)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG_INJ (4)
+ *
+ * (0) On STM32F3, parameter available only on analog watchdog number: AWD1.\n
+ * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
+ * (5) On STM32F3, ADC channel available only on all ADC instances, but
+ * only one ADC instance is allowed to be connected to VrefInt at the same time.
+ */
+#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
+ (((__GROUP__) == LL_ADC_GROUP_REGULAR) \
+ ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
+ : \
+ ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
+ ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) \
+ : \
+ (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
+ )
+
+/**
+ * @brief Helper macro to set the value of ADC analog watchdog threshold high
+ * or low in function of ADC resolution, when ADC resolution is
+ * different of 12 bits.
+ * @note To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()
+ * or @ref LL_ADC_SetAnalogWDThresholds().
+ * Example, with a ADC resolution of 8 bits, to set the value of
+ * analog watchdog threshold high (on 8 bits):
+ * LL_ADC_SetAnalogWDThresholds
+ * (< ADCx param >,
+ * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
+ * );
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
+ ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
+
+/**
+ * @brief Helper macro to get the value of ADC analog watchdog threshold high
+ * or low in function of ADC resolution, when ADC resolution is
+ * different of 12 bits.
+ * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
+ * Example, with a ADC resolution of 8 bits, to get the value of
+ * analog watchdog threshold high (on 8 bits):
+ * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
+ * (LL_ADC_RESOLUTION_8B,
+ * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
+ * );
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
+ ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
+
+/**
+ * @brief Helper macro to get the ADC analog watchdog threshold high
+ * or low from raw value containing both thresholds concatenated.
+ * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
+ * Example, to get analog watchdog threshold high from the register raw value:
+ * __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>);
+ * @param __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
+ * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
+ * @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+#define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \
+ (((__AWD_THRESHOLDS__) >> POSITION_VAL((__AWD_THRESHOLD_TYPE__))) & LL_ADC_AWD_THRESHOLD_LOW)
+
+/**
+ * @brief Helper macro to set the ADC calibration value with both single ended
+ * and differential modes calibration factors concatenated.
+ * @note To be used with function @ref LL_ADC_SetCalibrationFactor().
+ * Example, to set calibration factors single ended to 0x55
+ * and differential ended to 0x2A:
+ * LL_ADC_SetCalibrationFactor(
+ * ADC1,
+ * __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))
+ * @param __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and Max_Data=0x7F
+ * @param __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F
+ * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+ */
+#define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) \
+ (((__CALIB_FACTOR_DIFFERENTIAL__) << POSITION_VAL(ADC_CALFACT_CALFACT_D)) | (__CALIB_FACTOR_SINGLE_ENDED__))
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Helper macro to get the ADC multimode conversion data of ADC master
+ * or ADC slave from raw value with both ADC conversion data concatenated.
+ * @note This macro is intended to be used when multimode transfer by DMA
+ * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
+ * In this case the transferred data need to processed with this macro
+ * to separate the conversion data of ADC master and ADC slave.
+ * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_MULTI_MASTER
+ * @arg @ref LL_ADC_MULTI_SLAVE
+ * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+#define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
+ (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
+#endif
+
+/**
+ * @brief Helper macro to select the ADC common instance
+ * to which is belonging the selected ADC instance.
+ * @note ADC common register instance can be used for:
+ * - Set parameters common to several ADC instances
+ * - Multimode (for devices with several ADC instances)
+ * Refer to functions having argument "ADCxy_COMMON" as parameter.
+ * @param __ADCx__ ADC instance
+ * @retval ADC common register instance
+ */
+#if defined(ADC3) && defined(ADC4)
+#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
+ ((((__ADCx__) == ADC1) || ((__ADCx__) == ADC2)) \
+ ? ( \
+ (ADC12_COMMON) \
+ ) \
+ : \
+ ( \
+ (ADC34_COMMON) \
+ ) \
+ )
+#elif defined(ADC1) && defined(ADC2)
+#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
+ (ADC12_COMMON)
+#else
+#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
+ (ADC1_COMMON)
+#endif
+
+/**
+ * @brief Helper macro to check if all ADC instances sharing the same
+ * ADC common instance are disabled.
+ * @note This check is required by functions with setting conditioned to
+ * ADC state:
+ * All ADC instances of the ADC common group must be disabled.
+ * Refer to functions having argument "ADCxy_COMMON" as parameter.
+ * @note On devices with only 1 ADC common instance, parameter of this macro
+ * is useless and can be ignored (parameter kept for compatibility
+ * with devices featuring several ADC common instances).
+ * @param __ADCXY_COMMON__ ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval Value "0" if all ADC instances sharing the same ADC common instance
+ * are disabled.
+ * Value "1" if at least one ADC instance sharing the same ADC common instance
+ * is enabled.
+ */
+#if defined(ADC3) && defined(ADC4)
+#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
+ (((__ADCXY_COMMON__) == ADC12_COMMON) \
+ ? ( \
+ (LL_ADC_IsEnabled(ADC1) | \
+ LL_ADC_IsEnabled(ADC2) ) \
+ ) \
+ : \
+ ( \
+ (LL_ADC_IsEnabled(ADC3) | \
+ LL_ADC_IsEnabled(ADC4) ) \
+ ) \
+ )
+#elif defined(ADC1) && defined(ADC2)
+#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
+ (LL_ADC_IsEnabled(ADC1) | \
+ LL_ADC_IsEnabled(ADC2) )
+#else
+#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
+ LL_ADC_IsEnabled(ADC1)
+#endif
+
+/**
+ * @brief Helper macro to define the ADC conversion data full-scale digital
+ * value corresponding to the selected ADC resolution.
+ * @note ADC conversion data full-scale corresponds to voltage range
+ * determined by analog voltage references Vref+ and Vref-
+ * (refer to reference manual).
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+ */
+#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
+ (((uint32_t)0xFFFU) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U)))
+
+/**
+ * @brief Helper macro to convert the ADC conversion data from
+ * a resolution to another resolution.
+ * @param __DATA__ ADC conversion data to be converted
+ * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
+ * This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
+ * This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ * @retval ADC conversion data to the requested resolution
+ */
+#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
+ __ADC_RESOLUTION_CURRENT__,\
+ __ADC_RESOLUTION_TARGET__) \
+ (((__DATA__) \
+ << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U))) \
+ >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U)) \
+ )
+
+/**
+ * @brief Helper macro to calculate the voltage (unit: mVolt)
+ * corresponding to a ADC conversion data (unit: digital value).
+ * @note Analog reference voltage (Vref+) must be either known from
+ * user board environment or can be calculated using ADC measurement
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+ * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
+ * (unit: digital value).
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+ */
+#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
+ __ADC_DATA__,\
+ __ADC_RESOLUTION__) \
+ ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
+ / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
+ )
+
+/**
+ * @brief Helper macro to calculate analog reference voltage (Vref+)
+ * (unit: mVolt) from ADC conversion data of internal voltage
+ * reference VrefInt.
+ * @note Computation is using VrefInt calibration value
+ * stored in system memory for each device during production.
+ * @note This voltage depends on user board environment: voltage level
+ * connected to pin Vref+.
+ * On devices with small package, the pin Vref+ is not present
+ * and internally bonded to pin Vdda.
+ * @note On this STM32 serie, calibration data of internal voltage reference
+ * VrefInt corresponds to a resolution of 12 bits,
+ * this is the recommended ADC resolution to convert voltage of
+ * internal voltage reference VrefInt.
+ * Otherwise, this macro performs the processing to scale
+ * ADC conversion data to 12 bits.
+ * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
+ * of internal voltage reference VrefInt (unit: digital value).
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ * @retval Analog reference voltage (unit: mV)
+ */
+#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
+ __ADC_RESOLUTION__) \
+ (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
+ / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
+ (__ADC_RESOLUTION__), \
+ LL_ADC_RESOLUTION_12B) \
+ )
+
+/**
+ * @brief Helper macro to calculate the temperature (unit: degree Celsius)
+ * from ADC conversion data of internal temperature sensor.
+ * @note Computation is using temperature sensor calibration values
+ * stored in system memory for each device during production.
+ * @note Calculation formula:
+ * Temperature = ((TS_ADC_DATA - TS_CAL1)
+ * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
+ * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
+ * with TS_ADC_DATA = temperature sensor raw data measured by ADC
+ * Avg_Slope = (TS_CAL2 - TS_CAL1)
+ * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
+ * TS_CAL1 = equivalent TS_ADC_DATA at temperature
+ * TEMP_DEGC_CAL1 (calibrated in factory)
+ * TS_CAL2 = equivalent TS_ADC_DATA at temperature
+ * TEMP_DEGC_CAL2 (calibrated in factory)
+ * Caution: Calculation relevancy under reserve that calibration
+ * parameters are correct (address and data).
+ * To calculate temperature using temperature sensor
+ * datasheet typical values (generic values less, therefore
+ * less accurate than calibrated values),
+ * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
+ * @note As calculation input, the analog reference voltage (Vref+) must be
+ * defined as it impacts the ADC LSB equivalent voltage.
+ * @note Analog reference voltage (Vref+) must be either known from
+ * user board environment or can be calculated using ADC measurement
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * @note On this STM32 serie, calibration data of temperature sensor
+ * corresponds to a resolution of 12 bits,
+ * this is the recommended ADC resolution to convert voltage of
+ * temperature sensor.
+ * Otherwise, this macro performs the processing to scale
+ * ADC conversion data to 12 bits.
+ * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+ * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
+ * temperature sensor (unit: digital value).
+ * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
+ * sensor voltage has been measured.
+ * This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ * @retval Temperature (unit: degree Celsius)
+ */
+#define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
+ __TEMPSENSOR_ADC_DATA__,\
+ __ADC_RESOLUTION__) \
+ (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
+ (__ADC_RESOLUTION__), \
+ LL_ADC_RESOLUTION_12B) \
+ * (__VREFANALOG_VOLTAGE__)) \
+ / TEMPSENSOR_CAL_VREFANALOG) \
+ - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
+ ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
+ ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
+ ) + TEMPSENSOR_CAL1_TEMP \
+ )
+
+/**
+ * @brief Helper macro to calculate the temperature (unit: degree Celsius)
+ * from ADC conversion data of internal temperature sensor.
+ * @note Computation is using temperature sensor typical values
+ * (refer to device datasheet).
+ * @note Calculation formula:
+ * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
+ * / Avg_Slope + CALx_TEMP
+ * with TS_ADC_DATA = temperature sensor raw data measured by ADC
+ * (unit: digital value)
+ * Avg_Slope = temperature sensor slope
+ * (unit: uV/Degree Celsius)
+ * TS_TYP_CALx_VOLT = temperature sensor digital value at
+ * temperature CALx_TEMP (unit: mV)
+ * Caution: Calculation relevancy under reserve the temperature sensor
+ * of the current device has characteristics in line with
+ * datasheet typical values.
+ * If temperature sensor calibration values are available on
+ * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
+ * temperature calculation will be more accurate using
+ * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
+ * @note As calculation input, the analog reference voltage (Vref+) must be
+ * defined as it impacts the ADC LSB equivalent voltage.
+ * @note Analog reference voltage (Vref+) must be either known from
+ * user board environment or can be calculated using ADC measurement
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * @note ADC measurement data must correspond to a resolution of 12bits
+ * (full scale digital value 4095). If not the case, the data must be
+ * preliminarily rescaled to an equivalent resolution of 12 bits.
+ * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
+ * On STM32F3, refer to device datasheet parameter "Avg_Slope".
+ * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
+ * On STM32F3, refer to device datasheet parameter "V25" (corresponding to TS_CAL1).
+ * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
+ * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
+ * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
+ * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
+ * This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ * @retval Temperature (unit: degree Celsius)
+ */
+#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
+ __TEMPSENSOR_TYP_CALX_V__,\
+ __TEMPSENSOR_CALX_TEMP__,\
+ __VREFANALOG_VOLTAGE__,\
+ __TEMPSENSOR_ADC_DATA__,\
+ __ADC_RESOLUTION__) \
+ ((( ( \
+ (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
+ * 1000) \
+ - \
+ (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
+ / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
+ * 1000) \
+ ) \
+ ) / (__TEMPSENSOR_TYP_AVGSLOPE__) \
+ ) + (__TEMPSENSOR_CALX_TEMP__) \
+ )
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
+ * @{
+ */
+
+/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
+ * @{
+ */
+/* Note: LL ADC functions to set DMA transfer are located into sections of */
+/* configuration of ADC instance, groups and multimode (if available): */
+/* @ref LL_ADC_REG_SetDMATransfer(), ... */
+
+/**
+ * @brief Function to help to configure DMA transfer from ADC: retrieve the
+ * ADC register address from ADC instance and a list of ADC registers
+ * intended to be used (most commonly) with DMA transfer.
+ * @note These ADC registers are data registers:
+ * when ADC conversion data is available in ADC data registers,
+ * ADC generates a DMA transfer request.
+ * @note This macro is intended to be used with LL DMA driver, refer to
+ * function "LL_DMA_ConfigAddresses()".
+ * Example:
+ * LL_DMA_ConfigAddresses(DMA1,
+ * LL_DMA_CHANNEL_1,
+ * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
+ * (uint32_t)&< array or variable >,
+ * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
+ * @note For devices with several ADC: in multimode, some devices
+ * use a different data register outside of ADC instance scope
+ * (common data register). This macro manages this register difference,
+ * only ADC instance has to be set as parameter.
+ * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n
+ * CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n
+ * CDR RDATA_SLV LL_ADC_DMA_GetRegAddr
+ * @param ADCx ADC instance
+ * @param Register This parameter can be one of the following values:
+ * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
+ * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
+ *
+ * (1) Available on devices with several ADC instances.
+ * @retval ADC register address
+ */
+#if defined(ADC_MULTIMODE_SUPPORT)
+__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
+{
+ register uint32_t data_reg_addr = 0U;
+
+ if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
+ {
+ /* Retrieve address of register DR */
+ data_reg_addr = (uint32_t)&(ADCx->DR);
+ }
+ else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
+ {
+ /* Retrieve address of register CDR */
+ data_reg_addr = (uint32_t)&((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
+ }
+
+ return data_reg_addr;
+}
+#else
+__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
+{
+ /* Retrieve address of register DR */
+ return (uint32_t)&(ADCx->DR);
+}
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
+ * @{
+ */
+
+/**
+ * @brief Set parameter common to several ADC: Clock source and prescaler.
+ * @note On this STM32 serie, if ADC group injected is used, some
+ * clock ratio constraints between ADC clock and AHB clock
+ * must be respected.
+ * Refer to reference manual.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * All ADC instances of the ADC common group must be disabled.
+ * This check can be done with function @ref LL_ADC_IsEnabled() for each
+ * ADC instance or by using helper macro helper macro
+ * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
+ * @rmtoll CCR CKMODE LL_ADC_SetCommonClock\n
+ * CCR PRESC LL_ADC_SetCommonClock
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param CommonClock This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
+ * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
+ * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
+{
+ MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE, CommonClock);
+}
+
+/**
+ * @brief Get parameter common to several ADC: Clock source and prescaler.
+ * @rmtoll CCR CKMODE LL_ADC_GetCommonClock\n
+ * CCR PRESC LL_ADC_GetCommonClock
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
+ * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
+ * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE));
+}
+
+/**
+ * @brief Set parameter common to several ADC: measurement path to internal
+ * channels (VrefInt, temperature sensor, ...).
+ * @note One or several values can be selected.
+ * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+ * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+ * @note Stabilization time of measurement path to internal channel:
+ * After enabling internal paths, before starting ADC conversion,
+ * a delay is required for internal voltage reference and
+ * temperature sensor stabilization time.
+ * Refer to device datasheet.
+ * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
+ * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
+ * @note ADC internal channel sampling time constraint:
+ * For ADC conversion of internal channels,
+ * a sampling time minimum value is required.
+ * Refer to device datasheet.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * All ADC instances of the ADC common group must be disabled.
+ * This check can be done with function @ref LL_ADC_IsEnabled() for each
+ * ADC instance or by using helper macro helper macro
+ * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
+ * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n
+ * CCR TSEN LL_ADC_SetCommonPathInternalCh\n
+ * CCR VBATEN LL_ADC_SetCommonPathInternalCh
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param PathInternal This parameter can be a combination of the following values:
+ * @arg @ref LL_ADC_PATH_INTERNAL_NONE
+ * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+ * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+ * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
+{
+ MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);
+}
+
+/**
+ * @brief Get parameter common to several ADC: measurement path to internal
+ * channels (VrefInt, temperature sensor, ...).
+ * @note One or several values can be selected.
+ * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+ * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+ * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n
+ * CCR TSEN LL_ADC_GetCommonPathInternalCh\n
+ * CCR VBATEN LL_ADC_GetCommonPathInternalCh
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval Returned value can be a combination of the following values:
+ * @arg @ref LL_ADC_PATH_INTERNAL_NONE
+ * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+ * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+ * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
+ * @{
+ */
+
+/**
+ * @brief Set ADC calibration factor in the mode single-ended
+ * or differential (for devices with differential mode available).
+ * @note This function is intended to set calibration parameters
+ * without having to perform a new calibration using
+ * @ref LL_ADC_StartCalibration().
+ * @note For devices with differential mode available:
+ * Calibration of offset is specific to each of
+ * single-ended and differential modes
+ * (calibration factor must be specified for each of these
+ * differential modes, if used afterwards and if the application
+ * requires their calibration).
+ * @note In case of setting calibration factors of both modes single ended
+ * and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED):
+ * both calibration factors must be concatenated.
+ * To perform this processing, use helper macro
+ * @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be enabled, without calibration on going, without conversion
+ * on going on group regular.
+ * @rmtoll CALFACT CALFACT_S LL_ADC_SetCalibrationFactor\n
+ * CALFACT CALFACT_D LL_ADC_SetCalibrationFactor
+ * @param ADCx ADC instance
+ * @param SingleDiff This parameter can be one of the following values:
+ * @arg @ref LL_ADC_SINGLE_ENDED
+ * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
+ * @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED
+ * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)
+{
+ MODIFY_REG(ADCx->CALFACT,
+ SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
+ CalibrationFactor << POSITION_VAL(SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK));
+}
+
+/**
+ * @brief Get ADC calibration factor in the mode single-ended
+ * or differential (for devices with differential mode available).
+ * @note Calibration factors are set by hardware after performing
+ * a calibration run using function @ref LL_ADC_StartCalibration().
+ * @note For devices with differential mode available:
+ * Calibration of offset is specific to each of
+ * single-ended and differential modes
+ * @rmtoll CALFACT CALFACT_S LL_ADC_GetCalibrationFactor\n
+ * CALFACT CALFACT_D LL_ADC_GetCalibrationFactor
+ * @param ADCx ADC instance
+ * @param SingleDiff This parameter can be one of the following values:
+ * @arg @ref LL_ADC_SINGLE_ENDED
+ * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
+ * @retval Value between Min_Data=0x00 and Max_Data=0x7F
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff)
+{
+ /* Retrieve bits with position in register depending on parameter */
+ /* "SingleDiff". */
+ /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */
+ /* containing other bits reserved for other purpose. */
+ return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> POSITION_VAL(SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK));
+}
+
+/**
+ * @brief Set ADC resolution.
+ * Refer to reference manual for alignments formats
+ * dependencies to ADC resolutions.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll CFGR RES LL_ADC_SetResolution
+ * @param ADCx ADC instance
+ * @param Resolution This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
+{
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
+}
+
+/**
+ * @brief Get ADC resolution.
+ * Refer to reference manual for alignments formats
+ * dependencies to ADC resolutions.
+ * @rmtoll CFGR RES LL_ADC_GetResolution
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
+}
+
+/**
+ * @brief Set ADC conversion data alignment.
+ * @note Refer to reference manual for alignments formats
+ * dependencies to ADC resolutions.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll CFGR ALIGN LL_ADC_SetDataAlignment
+ * @param ADCx ADC instance
+ * @param DataAlignment This parameter can be one of the following values:
+ * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
+ * @arg @ref LL_ADC_DATA_ALIGN_LEFT
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
+{
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_ALIGN, DataAlignment);
+}
+
+/**
+ * @brief Get ADC conversion data alignment.
+ * @note Refer to reference manual for alignments formats
+ * dependencies to ADC resolutions.
+ * @rmtoll CFGR ALIGN LL_ADC_GetDataAlignment
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
+ * @arg @ref LL_ADC_DATA_ALIGN_LEFT
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_ALIGN));
+}
+
+/**
+ * @brief Set ADC low power mode.
+ * @note Description of ADC low power modes:
+ * - ADC low power mode "auto wait": Dynamic low power mode,
+ * ADC conversions occurrences are limited to the minimum necessary
+ * in order to reduce power consumption.
+ * New ADC conversion starts only when the previous
+ * unitary conversion data (for ADC group regular)
+ * or previous sequence conversions data (for ADC group injected)
+ * has been retrieved by user software.
+ * In the meantime, ADC remains idle: does not performs any
+ * other conversion.
+ * This mode allows to automatically adapt the ADC conversions
+ * triggers to the speed of the software that reads the data.
+ * Moreover, this avoids risk of overrun for low frequency
+ * applications.
+ * How to use this low power mode:
+ * - Do not use with interruption or DMA since these modes
+ * have to clear immediately the EOC flag to free the
+ * IRQ vector sequencer.
+ * - Do use with polling: 1. Start conversion,
+ * 2. Later on, when conversion data is needed: poll for end of
+ * conversion to ensure that conversion is completed and
+ * retrieve ADC conversion data. This will trig another
+ * ADC conversion start.
+ * - ADC low power mode "auto power-off" (feature available on
+ * this device if parameter LL_ADC_LP_MODE_AUTOOFF is available):
+ * the ADC automatically powers-off after a conversion and
+ * automatically wakes up when a new conversion is triggered
+ * (with startup time between trigger and start of sampling).
+ * This feature can be combined with low power mode "auto wait".
+ * @note With ADC low power mode "auto wait", the ADC conversion data read
+ * is corresponding to previous ADC conversion start, independently
+ * of delay during which ADC was idle.
+ * Therefore, the ADC conversion data may be outdated: does not
+ * correspond to the current voltage level on the selected
+ * ADC channel.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll CFGR AUTDLY LL_ADC_SetLowPowerMode
+ * @param ADCx ADC instance
+ * @param LowPowerMode This parameter can be one of the following values:
+ * @arg @ref LL_ADC_LP_MODE_NONE
+ * @arg @ref LL_ADC_LP_AUTOWAIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
+{
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode);
+}
+
+/**
+ * @brief Get ADC low power mode:
+ * @note Description of ADC low power modes:
+ * - ADC low power mode "auto wait": Dynamic low power mode,
+ * ADC conversions occurrences are limited to the minimum necessary
+ * in order to reduce power consumption.
+ * New ADC conversion starts only when the previous
+ * unitary conversion data (for ADC group regular)
+ * or previous sequence conversions data (for ADC group injected)
+ * has been retrieved by user software.
+ * In the meantime, ADC remains idle: does not performs any
+ * other conversion.
+ * This mode allows to automatically adapt the ADC conversions
+ * triggers to the speed of the software that reads the data.
+ * Moreover, this avoids risk of overrun for low frequency
+ * applications.
+ * How to use this low power mode:
+ * - Do not use with interruption or DMA since these modes
+ * have to clear immediately the EOC flag to free the
+ * IRQ vector sequencer.
+ * - Do use with polling: 1. Start conversion,
+ * 2. Later on, when conversion data is needed: poll for end of
+ * conversion to ensure that conversion is completed and
+ * retrieve ADC conversion data. This will trig another
+ * ADC conversion start.
+ * - ADC low power mode "auto power-off" (feature available on
+ * this device if parameter LL_ADC_LP_MODE_AUTOOFF is available):
+ * the ADC automatically powers-off after a conversion and
+ * automatically wakes up when a new conversion is triggered
+ * (with startup time between trigger and start of sampling).
+ * This feature can be combined with low power mode "auto wait".
+ * @note With ADC low power mode "auto wait", the ADC conversion data read
+ * is corresponding to previous ADC conversion start, independently
+ * of delay during which ADC was idle.
+ * Therefore, the ADC conversion data may be outdated: does not
+ * correspond to the current voltage level on the selected
+ * ADC channel.
+ * @rmtoll CFGR AUTDLY LL_ADC_GetLowPowerMode
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_LP_MODE_NONE
+ * @arg @ref LL_ADC_LP_AUTOWAIT
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY));
+}
+
+/**
+ * @brief Set ADC selected offset number 1, 2, 3 or 4.
+ * @note This function set the 2 items of offset configuration:
+ * - ADC channel to which the offset programmed will be applied
+ * (independently of channel mapped on ADC group regular
+ * or group injected)
+ * - Offset level (offset to be subtracted from the raw
+ * converted data).
+ * @note Caution: Offset format is dependent to ADC resolution:
+ * offset has to be left-aligned on bit 11, the LSB (right bits)
+ * are set to 0.
+ * @note This function enables the offset, by default. It can be forced
+ * to disable state using function LL_ADC_SetOffsetState().
+ * @note If a channel is mapped on several offsets numbers, only the offset
+ * with the lowest value is considered for the subtraction.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll OFR1 OFFSET1_CH LL_ADC_SetOffset\n
+ * OFR1 OFFSET1 LL_ADC_SetOffset\n
+ * OFR1 OFFSET1_EN LL_ADC_SetOffset\n
+ * OFR2 OFFSET2_CH LL_ADC_SetOffset\n
+ * OFR2 OFFSET2 LL_ADC_SetOffset\n
+ * OFR2 OFFSET2_EN LL_ADC_SetOffset\n
+ * OFR3 OFFSET3_CH LL_ADC_SetOffset\n
+ * OFR3 OFFSET3 LL_ADC_SetOffset\n
+ * OFR3 OFFSET3_EN LL_ADC_SetOffset\n
+ * OFR4 OFFSET4_CH LL_ADC_SetOffset\n
+ * OFR4 OFFSET4 LL_ADC_SetOffset\n
+ * OFR4 OFFSET4_EN LL_ADC_SetOffset
+ * @param ADCx ADC instance
+ * @param Offsety This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_1
+ * @arg @ref LL_ADC_OFFSET_2
+ * @arg @ref LL_ADC_OFFSET_3
+ * @arg @ref LL_ADC_OFFSET_4
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
+ *
+ * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
+ * (5) On STM32F3, ADC channel available only on all ADC instances, but
+ * only one ADC instance is allowed to be connected to VrefInt at the same time.
+ * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
+{
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+
+ MODIFY_REG(*preg,
+ ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
+ ADC_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
+}
+
+/**
+ * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
+ * Channel to which the offset programmed will be applied
+ * (independently of channel mapped on ADC group regular
+ * or group injected)
+ * @note Usage of the returned channel number:
+ * - To reinject this channel into another function LL_ADC_xxx:
+ * the returned channel number is only partly formatted on definition
+ * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+ * with parts of literals LL_ADC_CHANNEL_x or using
+ * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * Then the selected literal LL_ADC_CHANNEL_x can be used
+ * as parameter for another function.
+ * - To get the channel number in decimal format:
+ * process the returned value with the helper macro
+ * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * @rmtoll OFR1 OFFSET1_CH LL_ADC_GetOffsetChannel\n
+ * OFR2 OFFSET2_CH LL_ADC_GetOffsetChannel\n
+ * OFR3 OFFSET3_CH LL_ADC_GetOffsetChannel\n
+ * OFR4 OFFSET4_CH LL_ADC_GetOffsetChannel
+ * @param ADCx ADC instance
+ * @param Offsety This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_1
+ * @arg @ref LL_ADC_OFFSET_2
+ * @arg @ref LL_ADC_OFFSET_3
+ * @arg @ref LL_ADC_OFFSET_4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
+ *
+ * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
+ * (5) On STM32F3, ADC channel available only on all ADC instances, but
+ * only one ADC instance is allowed to be connected to VrefInt at the same time.\n
+ * (1, 2, 3, 4, 5) For ADC channel read back from ADC register,
+ * comparison with internal channel parameter to be done
+ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety)
+{
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+
+ return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
+}
+
+/**
+ * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
+ * Offset level (offset to be subtracted from the raw
+ * converted data).
+ * @note Caution: Offset format is dependent to ADC resolution:
+ * offset has to be left-aligned on bit 11, the LSB (right bits)
+ * are set to 0.
+ * @rmtoll OFR1 OFFSET1 LL_ADC_GetOffsetLevel\n
+ * OFR2 OFFSET2 LL_ADC_GetOffsetLevel\n
+ * OFR3 OFFSET3 LL_ADC_GetOffsetLevel\n
+ * OFR4 OFFSET4 LL_ADC_GetOffsetLevel
+ * @param ADCx ADC instance
+ * @param Offsety This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_1
+ * @arg @ref LL_ADC_OFFSET_2
+ * @arg @ref LL_ADC_OFFSET_3
+ * @arg @ref LL_ADC_OFFSET_4
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety)
+{
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+
+ return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1);
+}
+
+/**
+ * @brief Set for the ADC selected offset number 1, 2, 3 or 4:
+ * force offset state disable or enable
+ * without modifying offset channel or offset value.
+ * @note This function should be needed only in case of offset to be
+ * enabled-disabled dynamically, and should not be needed in other cases:
+ * function LL_ADC_SetOffset() automatically enables the offset.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll OFR1 OFFSET1_EN LL_ADC_SetOffsetState\n
+ * OFR2 OFFSET2_EN LL_ADC_SetOffsetState\n
+ * OFR3 OFFSET3_EN LL_ADC_SetOffsetState\n
+ * OFR4 OFFSET4_EN LL_ADC_SetOffsetState
+ * @param ADCx ADC instance
+ * @param Offsety This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_1
+ * @arg @ref LL_ADC_OFFSET_2
+ * @arg @ref LL_ADC_OFFSET_3
+ * @arg @ref LL_ADC_OFFSET_4
+ * @param OffsetState This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_DISABLE
+ * @arg @ref LL_ADC_OFFSET_ENABLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
+{
+ register __IO uint32_t *preg = (__IO uint32_t *)((uint32_t)
+ ((uint32_t)(&ADCx->OFR1) + (Offsety*4U)));
+
+ MODIFY_REG(*preg,
+ ADC_OFR1_OFFSET1_EN,
+ OffsetState);
+}
+
+/**
+ * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
+ * offset state disabled or enabled.
+ * @rmtoll OFR1 OFFSET1_EN LL_ADC_GetOffsetState\n
+ * OFR2 OFFSET2_EN LL_ADC_GetOffsetState\n
+ * OFR3 OFFSET3_EN LL_ADC_GetOffsetState\n
+ * OFR4 OFFSET4_EN LL_ADC_GetOffsetState
+ * @param ADCx ADC instance
+ * @param Offsety This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_1
+ * @arg @ref LL_ADC_OFFSET_2
+ * @arg @ref LL_ADC_OFFSET_3
+ * @arg @ref LL_ADC_OFFSET_4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_DISABLE
+ * @arg @ref LL_ADC_OFFSET_ENABLE
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety)
+{
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+
+ return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_EN);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
+ * @{
+ */
+
+/**
+ * @brief Set ADC group regular conversion trigger source:
+ * internal (SW start) or from external IP (timer event,
+ * external interrupt line).
+ * @note On this STM32 serie, setting trigger source to external trigger
+ * also set trigger polarity to rising edge
+ * (default setting for compatibility with some ADC on other
+ * STM32 families having this setting set by HW default value).
+ * In case of need to modify trigger edge, use
+ * function @ref LL_ADC_REG_SetTriggerEdge().
+ * @note Availability of parameters of trigger sources from timer
+ * depends on timers availability on the selected device.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @rmtoll CFGR EXTSEL LL_ADC_REG_SetTriggerSource\n
+ * CFGR EXTEN LL_ADC_REG_SetTriggerSource
+ * @param ADCx ADC instance
+ * @param TriggerSource This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (3)(4)(5)(6)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (3)(4)(5)(6)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO (3)(4)(5)(6)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO__ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH1_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO (3)(4)(5)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO__ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4 (3)(4)(5)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO (1)(2)(3)(5)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH1_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 (3) (5)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO (3)(4)(5)(6)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (3)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (1)(2)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM7_TRGO_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO__ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (1)(2)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO (5)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRG0_ADC12 (1) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRG02_ADC12 (1) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH1_ADC12 (1) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH2_ADC12 (1) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH3_ADC12 (1) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRG0_ADC3 (1) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRG02_ADC34 (1) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH1_ADC34 (1) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1 (4)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3 (4)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE2_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (3)(4)(5)(6)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11_ADC12 (1)(2) (7)
+
+ * (1) On STM32F3, parameter not available on all devices: among others, on STM32F303xE, STM32F398xx.\n
+ * (2) On STM32F3, parameter not available on all devices: among others, on STM32F303xC, STM32F358xx.\n
+ * (3) On STM32F3, parameter not available on all devices: among others, on STM32F303x8, STM32F328xx.\n
+ * (4) On STM32F3, parameter not available on all devices: among others, on STM32F334x8.\n
+ * (5) On STM32F3, parameter not available on all devices: among others, on STM32F302xC, STM32F302xE.\n
+ * (6) On STM32F3, parameter not available on all devices: among others, on STM32F301x8, STM32F302x8, STM32F318xx.\n
+ * (7) On STM32F3, parameter not available on all ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n
+ * (8) On STM32F3, parameter not available on all ADC instances: ADC3, ADC4 (for ADC instances ADCx available on the selected device).
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
+{
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource);
+}
+
+/**
+ * @brief Get ADC group regular conversion trigger source:
+ * internal (SW start) or from external IP (timer event,
+ * external interrupt line).
+ * @note To determine whether group regular trigger source is
+ * internal (SW start) or external, without detail
+ * of which peripheral is selected as external trigger,
+ * (equivalent to
+ * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
+ * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
+ * @note Availability of parameters of trigger sources from timer
+ * depends on timers availability on the selected device.
+ * @rmtoll CFGR EXTSEL LL_ADC_REG_GetTriggerSource\n
+ * CFGR EXTEN LL_ADC_REG_GetTriggerSource
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (3)(4)(5)(6)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (3)(4)(5)(6)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO (3)(4)(5)(6)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO__ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH1_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO (3)(4)(5)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO__ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4 (3)(4)(5)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO (1)(2)(3)(5)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH1_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 (3) (5)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO (3)(4)(5)(6)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (3)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (1)(2)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM7_TRGO_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO__ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (1)(2)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO (5)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRG0_ADC12 (1) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRG02_ADC12 (1) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH1_ADC12 (1) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH2_ADC12 (1) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH3_ADC12 (1) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRG0_ADC3 (1) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRG02_ADC34 (1) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH1_ADC34 (1) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1 (4)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3 (4)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE2_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (3)(4)(5)(6)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11_ADC12 (1)(2) (7)
+
+ * (1) On STM32F3, parameter not available on all devices: among others, on STM32F303xE, STM32F398xx.\n
+ * (2) On STM32F3, parameter not available on all devices: among others, on STM32F303xC, STM32F358xx.\n
+ * (3) On STM32F3, parameter not available on all devices: among others, on STM32F303x8, STM32F328xx.\n
+ * (4) On STM32F3, parameter not available on all devices: among others, on STM32F334x8.\n
+ * (5) On STM32F3, parameter not available on all devices: among others, on STM32F302xC, STM32F302xE.\n
+ * (6) On STM32F3, parameter not available on all devices: among others, on STM32F301x8, STM32F302x8, STM32F318xx.\n
+ * (7) On STM32F3, parameter not available on all ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n
+ * (8) On STM32F3, parameter not available on all ADC instances: ADC3, ADC4 (for ADC instances ADCx available on the selected device).
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
+{
+ register uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN);
+
+ /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
+ /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */
+ register uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U));
+
+ /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */
+ /* to match with triggers literals definition. */
+ return ((TriggerSource
+ & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR_EXTSEL)
+ | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR_EXTEN)
+ );
+}
+
+/**
+ * @brief Get ADC group regular conversion trigger source internal (SW start)
+ or external.
+ * @note In case of group regular trigger source set to external trigger,
+ * to determine which peripheral is selected as external trigger,
+ * use function @ref LL_ADC_REG_GetTriggerSource().
+ * @rmtoll CFGR EXTEN LL_ADC_REG_IsTriggerSourceSWStart
+ * @param ADCx ADC instance
+ * @retval Value "0" if trigger source external trigger
+ * Value "1" if trigger source SW start.
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN));
+}
+
+/**
+ * @brief Set ADC group regular conversion trigger polarity.
+ * @note Applicable only for trigger source set to external trigger.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @rmtoll CFGR EXTEN LL_ADC_REG_SetTriggerEdge
+ * @param ADCx ADC instance
+ * @param ExternalTriggerEdge This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
+ * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
+ * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
+{
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge);
+}
+
+/**
+ * @brief Get ADC group regular conversion trigger polarity.
+ * @note Applicable only for trigger source set to external trigger.
+ * @rmtoll CFGR EXTEN LL_ADC_REG_GetTriggerEdge
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
+ * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
+ * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN));
+}
+
+
+/**
+ * @brief Set ADC group regular sequencer length and scan direction.
+ * @note Description of ADC group regular sequencer features:
+ * - For devices with sequencer fully configurable
+ * (function "LL_ADC_REG_SetSequencerRanks()" available):
+ * sequencer length and each rank affectation to a channel
+ * are configurable.
+ * This function performs configuration of:
+ * - Sequence length: Number of ranks in the scan sequence.
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from rank 1 to rank n).
+ * Sequencer ranks are selected using
+ * function "LL_ADC_REG_SetSequencerRanks()".
+ * - For devices with sequencer not fully configurable
+ * (function "LL_ADC_REG_SetSequencerChannels()" available):
+ * sequencer length and each rank affectation to a channel
+ * are defined by channel number.
+ * This function performs configuration of:
+ * - Sequence length: Number of ranks in the scan sequence is
+ * defined by number of channels set in the sequence,
+ * rank of each channel is fixed by channel HW number.
+ * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from lowest channel number to
+ * highest channel number).
+ * Sequencer ranks are selected using
+ * function "LL_ADC_REG_SetSequencerChannels()".
+ * @note Sequencer disabled is equivalent to sequencer of 1 rank:
+ * ADC conversion on only 1 channel.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
+ * @param ADCx ADC instance
+ * @param SequencerNbRanks This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
+{
+ MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
+}
+
+/**
+ * @brief Get ADC group regular sequencer length and scan direction.
+ * @note Description of ADC group regular sequencer features:
+ * - For devices with sequencer fully configurable
+ * (function "LL_ADC_REG_SetSequencerRanks()" available):
+ * sequencer length and each rank affectation to a channel
+ * are configurable.
+ * This function retrieves:
+ * - Sequence length: Number of ranks in the scan sequence.
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from rank 1 to rank n).
+ * Sequencer ranks are selected using
+ * function "LL_ADC_REG_SetSequencerRanks()".
+ * - For devices with sequencer not fully configurable
+ * (function "LL_ADC_REG_SetSequencerChannels()" available):
+ * sequencer length and each rank affectation to a channel
+ * are defined by channel number.
+ * This function retrieves:
+ * - Sequence length: Number of ranks in the scan sequence is
+ * defined by number of channels set in the sequence,
+ * rank of each channel is fixed by channel HW number.
+ * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from lowest channel number to
+ * highest channel number).
+ * Sequencer ranks are selected using
+ * function "LL_ADC_REG_SetSequencerChannels()".
+ * @note Sequencer disabled is equivalent to sequencer of 1 rank:
+ * ADC conversion on only 1 channel.
+ * @rmtoll SQR1 L LL_ADC_REG_GetSequencerLength
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
+}
+
+/**
+ * @brief Set ADC group regular sequencer discontinuous mode:
+ * sequence subdivided and scan conversions interrupted every selected
+ * number of ranks.
+ * @note It is not possible to enable both ADC group regular
+ * continuous mode and sequencer discontinuous mode.
+ * @note It is not possible to enable both ADC auto-injected mode
+ * and ADC group regular sequencer discontinuous mode.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @rmtoll CFGR DISCEN LL_ADC_REG_SetSequencerDiscont\n
+ * CFGR DISCNUM LL_ADC_REG_SetSequencerDiscont
+ * @param ADCx ADC instance
+ * @param SeqDiscont This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
+{
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont);
+}
+
+/**
+ * @brief Get ADC group regular sequencer discontinuous mode:
+ * sequence subdivided and scan conversions interrupted every selected
+ * number of ranks.
+ * @rmtoll CFGR DISCEN LL_ADC_REG_GetSequencerDiscont\n
+ * CFGR DISCNUM LL_ADC_REG_GetSequencerDiscont
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM));
+}
+
+/**
+ * @brief Set ADC group regular sequence: channel on the selected
+ * scan sequence rank.
+ * @note This function performs configuration of:
+ * - Channels ordering into each rank of scan sequence:
+ * whatever channel can be placed into whatever rank.
+ * @note On this STM32 serie, ADC group regular sequencer is
+ * fully configurable: sequencer length and each rank
+ * affectation to a channel are configurable.
+ * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
+ * @note Depending on devices and packages, some channels may not be available.
+ * Refer to device datasheet for channels availability.
+ * @note On this STM32 serie, to measure internal channels (VrefInt,
+ * TempSensor, ...), measurement paths to internal channels must be
+ * enabled separately.
+ * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @rmtoll SQR1 SQ1 LL_ADC_REG_SetSequencerRanks\n
+ * SQR1 SQ2 LL_ADC_REG_SetSequencerRanks\n
+ * SQR1 SQ3 LL_ADC_REG_SetSequencerRanks\n
+ * SQR1 SQ4 LL_ADC_REG_SetSequencerRanks\n
+ * SQR2 SQ5 LL_ADC_REG_SetSequencerRanks\n
+ * SQR2 SQ6 LL_ADC_REG_SetSequencerRanks\n
+ * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n
+ * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n
+ * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n
+ * SQR3 SQ10 LL_ADC_REG_SetSequencerRanks\n
+ * SQR3 SQ11 LL_ADC_REG_SetSequencerRanks\n
+ * SQR3 SQ12 LL_ADC_REG_SetSequencerRanks\n
+ * SQR3 SQ13 LL_ADC_REG_SetSequencerRanks\n
+ * SQR3 SQ14 LL_ADC_REG_SetSequencerRanks\n
+ * SQR4 SQ15 LL_ADC_REG_SetSequencerRanks\n
+ * SQR4 SQ16 LL_ADC_REG_SetSequencerRanks
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_RANK_1
+ * @arg @ref LL_ADC_REG_RANK_2
+ * @arg @ref LL_ADC_REG_RANK_3
+ * @arg @ref LL_ADC_REG_RANK_4
+ * @arg @ref LL_ADC_REG_RANK_5
+ * @arg @ref LL_ADC_REG_RANK_6
+ * @arg @ref LL_ADC_REG_RANK_7
+ * @arg @ref LL_ADC_REG_RANK_8
+ * @arg @ref LL_ADC_REG_RANK_9
+ * @arg @ref LL_ADC_REG_RANK_10
+ * @arg @ref LL_ADC_REG_RANK_11
+ * @arg @ref LL_ADC_REG_RANK_12
+ * @arg @ref LL_ADC_REG_RANK_13
+ * @arg @ref LL_ADC_REG_RANK_14
+ * @arg @ref LL_ADC_REG_RANK_15
+ * @arg @ref LL_ADC_REG_RANK_16
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
+ *
+ * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
+ * (5) On STM32F3, ADC channel available only on all ADC instances, but
+ * only one ADC instance is allowed to be connected to VrefInt at the same time.
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
+{
+ /* Set bits with content of parameter "Channel" with bits position */
+ /* in register and register position depending on parameter "Rank". */
+ /* Parameters "Rank" and "Channel" are used with masks because containing */
+ /* other bits reserved for other purpose. */
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
+
+ MODIFY_REG(*preg,
+ ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
+ (Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_REG_RANK_ID_SQRX_MASK)));
+}
+
+/**
+ * @brief Get ADC group regular sequence: channel on the selected
+ * scan sequence rank.
+ * @note On this STM32 serie, ADC group regular sequencer is
+ * fully configurable: sequencer length and each rank
+ * affectation to a channel are configurable.
+ * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
+ * @note Depending on devices and packages, some channels may not be available.
+ * Refer to device datasheet for channels availability.
+ * @note Usage of the returned channel number:
+ * - To reinject this channel into another function LL_ADC_xxx:
+ * the returned channel number is only partly formatted on definition
+ * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+ * with parts of literals LL_ADC_CHANNEL_x or using
+ * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * Then the selected literal LL_ADC_CHANNEL_x can be used
+ * as parameter for another function.
+ * - To get the channel number in decimal format:
+ * process the returned value with the helper macro
+ * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * @rmtoll SQR1 SQ1 LL_ADC_REG_GetSequencerRanks\n
+ * SQR1 SQ2 LL_ADC_REG_GetSequencerRanks\n
+ * SQR1 SQ3 LL_ADC_REG_GetSequencerRanks\n
+ * SQR1 SQ4 LL_ADC_REG_GetSequencerRanks\n
+ * SQR2 SQ5 LL_ADC_REG_GetSequencerRanks\n
+ * SQR2 SQ6 LL_ADC_REG_GetSequencerRanks\n
+ * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n
+ * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n
+ * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n
+ * SQR3 SQ10 LL_ADC_REG_GetSequencerRanks\n
+ * SQR3 SQ11 LL_ADC_REG_GetSequencerRanks\n
+ * SQR3 SQ12 LL_ADC_REG_GetSequencerRanks\n
+ * SQR3 SQ13 LL_ADC_REG_GetSequencerRanks\n
+ * SQR3 SQ14 LL_ADC_REG_GetSequencerRanks\n
+ * SQR4 SQ15 LL_ADC_REG_GetSequencerRanks\n
+ * SQR4 SQ16 LL_ADC_REG_GetSequencerRanks
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_RANK_1
+ * @arg @ref LL_ADC_REG_RANK_2
+ * @arg @ref LL_ADC_REG_RANK_3
+ * @arg @ref LL_ADC_REG_RANK_4
+ * @arg @ref LL_ADC_REG_RANK_5
+ * @arg @ref LL_ADC_REG_RANK_6
+ * @arg @ref LL_ADC_REG_RANK_7
+ * @arg @ref LL_ADC_REG_RANK_8
+ * @arg @ref LL_ADC_REG_RANK_9
+ * @arg @ref LL_ADC_REG_RANK_10
+ * @arg @ref LL_ADC_REG_RANK_11
+ * @arg @ref LL_ADC_REG_RANK_12
+ * @arg @ref LL_ADC_REG_RANK_13
+ * @arg @ref LL_ADC_REG_RANK_14
+ * @arg @ref LL_ADC_REG_RANK_15
+ * @arg @ref LL_ADC_REG_RANK_16
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
+ *
+ * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
+ * (5) On STM32F3, ADC channel available only on all ADC instances, but
+ * only one ADC instance is allowed to be connected to VrefInt at the same time.\n
+ * (1, 2, 3, 4, 5) For ADC channel read back from ADC register,
+ * comparison with internal channel parameter to be done
+ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
+
+ return (uint32_t) (READ_BIT(*preg,
+ ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
+ << (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_REG_RANK_ID_SQRX_MASK))
+ );
+}
+
+/**
+ * @brief Set ADC continuous conversion mode on ADC group regular.
+ * @note Description of ADC continuous conversion mode:
+ * - single mode: one conversion per trigger
+ * - continuous mode: after the first trigger, following
+ * conversions launched successively automatically.
+ * @note It is not possible to enable both ADC group regular
+ * continuous mode and sequencer discontinuous mode.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @rmtoll CFGR CONT LL_ADC_REG_SetContinuousMode
+ * @param ADCx ADC instance
+ * @param Continuous This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_CONV_SINGLE
+ * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
+{
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous);
+}
+
+/**
+ * @brief Get ADC continuous conversion mode on ADC group regular.
+ * @note Description of ADC continuous conversion mode:
+ * - single mode: one conversion per trigger
+ * - continuous mode: after the first trigger, following
+ * conversions launched successively automatically.
+ * @rmtoll CFGR CONT LL_ADC_REG_GetContinuousMode
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_CONV_SINGLE
+ * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT));
+}
+
+/**
+ * @brief Set ADC group regular conversion data transfer: no transfer or
+ * transfer by DMA, and DMA requests mode.
+ * @note If transfer by DMA selected, specifies the DMA requests
+ * mode:
+ * - Limited mode (One shot mode): DMA transfer requests are stopped
+ * when number of DMA data transfers (number of
+ * ADC conversions) is reached.
+ * This ADC mode is intended to be used with DMA mode non-circular.
+ * - Unlimited mode: DMA transfer requests are unlimited,
+ * whatever number of DMA data transfers (number of
+ * ADC conversions).
+ * This ADC mode is intended to be used with DMA mode circular.
+ * @note If ADC DMA requests mode is set to unlimited and DMA is set to
+ * mode non-circular:
+ * when DMA transfers size will be reached, DMA will stop transfers of
+ * ADC conversions data ADC will raise an overrun error
+ * (overrun flag and interruption if enabled).
+ * @note For devices with several ADC instances: ADC multimode DMA
+ * settings are available using function @ref LL_ADC_SetMultiDMATransfer().
+ * @note To configure DMA source address (peripheral address),
+ * use function @ref LL_ADC_DMA_GetRegAddr().
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll CFGR DMAEN LL_ADC_REG_SetDMATransfer\n
+ * CFGR DMACFG LL_ADC_REG_SetDMATransfer
+ * @param ADCx ADC instance
+ * @param DMATransfer This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
+ * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
+ * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
+{
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG, DMATransfer);
+}
+
+/**
+ * @brief Get ADC group regular conversion data transfer: no transfer or
+ * transfer by DMA, and DMA requests mode.
+ * @note If transfer by DMA selected, specifies the DMA requests
+ * mode:
+ * - Limited mode (One shot mode): DMA transfer requests are stopped
+ * when number of DMA data transfers (number of
+ * ADC conversions) is reached.
+ * This ADC mode is intended to be used with DMA mode non-circular.
+ * - Unlimited mode: DMA transfer requests are unlimited,
+ * whatever number of DMA data transfers (number of
+ * ADC conversions).
+ * This ADC mode is intended to be used with DMA mode circular.
+ * @note If ADC DMA requests mode is set to unlimited and DMA is set to
+ * mode non-circular:
+ * when DMA transfers size will be reached, DMA will stop transfers of
+ * ADC conversions data ADC will raise an overrun error
+ * (overrun flag and interruption if enabled).
+ * @note For devices with several ADC instances: ADC multimode DMA
+ * settings are available using function @ref LL_ADC_GetMultiDMATransfer().
+ * @note To configure DMA source address (peripheral address),
+ * use function @ref LL_ADC_DMA_GetRegAddr().
+ * @rmtoll CFGR DMAEN LL_ADC_REG_GetDMATransfer\n
+ * CFGR DMACFG LL_ADC_REG_GetDMATransfer
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
+ * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
+ * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG));
+}
+
+/**
+ * @brief Set ADC group regular behavior in case of overrun:
+ * data preserved or overwritten.
+ * @note Compatibility with devices without feature overrun:
+ * other devices without this feature have a behavior
+ * equivalent to data overwritten.
+ * The default setting of overrun is data preserved.
+ * Therefore, for compatibility with all devices, parameter
+ * overrun should be set to data overwritten.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @rmtoll CFGR OVRMOD LL_ADC_REG_SetOverrun
+ * @param ADCx ADC instance
+ * @param Overrun This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
+ * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
+{
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun);
+}
+
+/**
+ * @brief Get ADC group regular behavior in case of overrun:
+ * data preserved or overwritten.
+ * @rmtoll CFGR OVRMOD LL_ADC_REG_GetOverrun
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
+ * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
+ * @{
+ */
+
+/**
+ * @brief Set ADC group injected conversion trigger source:
+ * internal (SW start) or from external IP (timer event,
+ * external interrupt line).
+ * @note On this STM32 serie, setting trigger source to external trigger
+ * also set trigger polarity to rising edge
+ * (default setting for compatibility with some ADC on other
+ * STM32 families having this setting set by HW default value).
+ * In case of need to modify trigger edge, use
+ * function @ref LL_ADC_INJ_SetTriggerEdge().
+ * @note Caution to ADC group injected contexts queue: On this STM32 serie,
+ * using successively several times this function will appear has
+ * having no effect.
+ * This is due to ADC group injected contexts queue (this feature
+ * cannot be disabled on this STM32 serie).
+ * To set several features of ADC group injected, use
+ * function @ref LL_ADC_INJ_ConfigQueueContext().
+ * @note Availability of parameters of trigger sources from timer
+ * depends on timers availability on the selected device.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must not be disabled. Can be enabled with or without conversion
+ * on going on either groups regular or injected.
+ * @rmtoll JSQR JEXTSEL LL_ADC_INJ_SetTriggerSource\n
+ * JSQR JEXTEN LL_ADC_INJ_SetTriggerSource
+ * @param ADCx ADC instance
+ * @param TriggerSource This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (3)(4)(5)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO__ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (3)(4)(5)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (1)(2)(3)(4)(5)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (3)(4)(5)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (3)(4)(5)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (3)(4)(5)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4_ADC12 (1)(2)(3)(4)(5) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (3) (5)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO__ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (3)(4)(5)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (1)(2)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (1)(2)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4__ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO_ADC12 (1) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2_ADC12 (1) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4_ADC12 (1) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRG_ADC34 (1) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRG2_ADC34 (1) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2_ADC34 (1) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 (4)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 (4)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (3)(4)(5)(6)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15_ADC12 (1)(2) (7)
+ *
+ * (1) On STM32F3, parameter not available on all devices: among others, on STM32F303xE, STM32F398xx.\n
+ * (2) On STM32F3, parameter not available on all devices: among others, on STM32F303xC, STM32F358xx.\n
+ * (3) On STM32F3, parameter not available on all devices: among others, on STM32F303x8, STM32F328xx.\n
+ * (4) On STM32F3, parameter not available on all devices: among others, on STM32F334x8.\n
+ * (5) On STM32F3, parameter not available on all devices: among others, on STM32F302xC, STM32F302xE.\n
+ * (6) On STM32F3, parameter not available on all devices: among others, on STM32F301x8, STM32F302x8, STM32F318xx.\n
+ * (7) On STM32F3, parameter not available on all ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n
+ * (8) On STM32F3, parameter not available on all ADC instances: ADC3, ADC4 (for ADC instances ADCx available on the selected device).
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
+{
+ MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource);
+}
+
+/**
+ * @brief Get ADC group injected conversion trigger source:
+ * internal (SW start) or from external IP (timer event,
+ * external interrupt line).
+ * @note To determine whether group injected trigger source is
+ * internal (SW start) or external, without detail
+ * of which peripheral is selected as external trigger,
+ * (equivalent to
+ * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
+ * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
+ * @note Availability of parameters of trigger sources from timer
+ * depends on timers availability on the selected device.
+ * @rmtoll JSQR JEXTSEL LL_ADC_INJ_GetTriggerSource\n
+ * JSQR JEXTEN LL_ADC_INJ_GetTriggerSource
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (3)(4)(5)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO__ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (3)(4)(5)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (1)(2)(3)(4)(5)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (3)(4)(5)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (3)(4)(5)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (3)(4)(5)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4_ADC12 (1)(2)(3)(4)(5) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (3) (5)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO__ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (3)(4)(5)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (1)(2)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (1)(2)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4__ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO_ADC12 (1) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2_ADC12 (1) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4_ADC12 (1) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRG_ADC34 (1) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRG2_ADC34 (1) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2_ADC34 (1) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 (4)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 (4)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (3)(4)(5)(6)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15_ADC12 (1)(2) (7)
+ *
+ * (1) On STM32F3, parameter not available on all devices: among others, on STM32F303xE, STM32F398xx.\n
+ * (2) On STM32F3, parameter not available on all devices: among others, on STM32F303xC, STM32F358xx.\n
+ * (3) On STM32F3, parameter not available on all devices: among others, on STM32F303x8, STM32F328xx.\n
+ * (4) On STM32F3, parameter not available on all devices: among others, on STM32F334x8.\n
+ * (5) On STM32F3, parameter not available on all devices: among others, on STM32F302xC, STM32F302xE.\n
+ * (6) On STM32F3, parameter not available on all devices: among others, on STM32F301x8, STM32F302x8, STM32F318xx.\n
+ * (7) On STM32F3, parameter not available on all ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n
+ * (8) On STM32F3, parameter not available on all ADC instances: ADC3, ADC4 (for ADC instances ADCx available on the selected device).
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
+{
+ register uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
+
+ /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
+ /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */
+ register uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2U));
+
+ /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */
+ /* to match with triggers literals definition. */
+ return ((TriggerSource
+ & (ADC_INJ_TRIG_SOURCE_MASK >> ShiftJexten) & ADC_JSQR_JEXTSEL)
+ | ((ADC_INJ_TRIG_EDGE_MASK >> ShiftJexten) & ADC_JSQR_JEXTEN)
+ );
+}
+
+/**
+ * @brief Get ADC group injected conversion trigger source internal (SW start)
+ or external
+ * @note In case of group injected trigger source set to external trigger,
+ * to determine which peripheral is selected as external trigger,
+ * use function @ref LL_ADC_INJ_GetTriggerSource.
+ * @rmtoll JSQR JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart
+ * @param ADCx ADC instance
+ * @retval Value "0" if trigger source external trigger
+ * Value "1" if trigger source SW start.
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN));
+}
+
+/**
+ * @brief Set ADC group injected conversion trigger polarity.
+ * Applicable only for trigger source set to external trigger.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must not be disabled. Can be enabled with or without conversion
+ * on going on either groups regular or injected.
+ * @rmtoll JSQR JEXTEN LL_ADC_INJ_SetTriggerEdge
+ * @param ADCx ADC instance
+ * @param ExternalTriggerEdge This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
+{
+ MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);
+}
+
+/**
+ * @brief Get ADC group injected conversion trigger polarity.
+ * Applicable only for trigger source set to external trigger.
+ * @rmtoll JSQR JEXTEN LL_ADC_INJ_GetTriggerEdge
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));
+}
+
+/**
+ * @brief Set ADC group injected sequencer length and scan direction.
+ * @note This function performs configuration of:
+ * - Sequence length: Number of ranks in the scan sequence.
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from rank 1 to rank n).
+ * @note Sequencer disabled is equivalent to sequencer of 1 rank:
+ * ADC conversion on only 1 channel.
+ * @note Caution to ADC group injected contexts queue: On this STM32 serie,
+ * using successively several times this function will appear has
+ * having no effect.
+ * This is due to ADC group injected contexts queue (this feature
+ * cannot be disabled on this STM32 serie).
+ * To set several features of ADC group injected, use
+ * function @ref LL_ADC_INJ_ConfigQueueContext().
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must not be disabled. Can be enabled with or without conversion
+ * on going on either groups regular or injected.
+ * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
+ * @param ADCx ADC instance
+ * @param SequencerNbRanks This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
+{
+ MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
+}
+
+/**
+ * @brief Get ADC group injected sequencer length and scan direction.
+ * @note This function retrieves:
+ * - Sequence length: Number of ranks in the scan sequence.
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from rank 1 to rank n).
+ * @note Sequencer disabled is equivalent to sequencer of 1 rank:
+ * ADC conversion on only 1 channel.
+ * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
+}
+
+/**
+ * @brief Set ADC group injected sequencer discontinuous mode:
+ * sequence subdivided and scan conversions interrupted every selected
+ * number of ranks.
+ * @note It is not possible to enable both ADC group injected
+ * auto-injected mode and sequencer discontinuous mode.
+ * @rmtoll CFGR JDISCEN LL_ADC_INJ_SetSequencerDiscont
+ * @param ADCx ADC instance
+ * @param SeqDiscont This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
+ * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
+{
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont);
+}
+
+/**
+ * @brief Get ADC group injected sequencer discontinuous mode:
+ * sequence subdivided and scan conversions interrupted every selected
+ * number of ranks.
+ * @rmtoll CFGR JDISCEN LL_ADC_INJ_GetSequencerDiscont
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
+ * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN));
+}
+
+/**
+ * @brief Set ADC group injected sequence: channel on the selected
+ * sequence rank.
+ * @note Depending on devices and packages, some channels may not be available.
+ * Refer to device datasheet for channels availability.
+ * @note On this STM32 serie, to measure internal channels (VrefInt,
+ * TempSensor, ...), measurement paths to internal channels must be
+ * enabled separately.
+ * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+ * @note Caution to ADC group injected contexts queue: On this STM32 serie,
+ * using successively several times this function will appear has
+ * having no effect.
+ * This is due to ADC group injected contexts queue (this feature
+ * cannot be disabled on this STM32 serie).
+ * To set several features of ADC group injected, use
+ * function @ref LL_ADC_INJ_ConfigQueueContext().
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must not be disabled. Can be enabled with or without conversion
+ * on going on either groups regular or injected.
+ * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
+ * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
+ * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
+ * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
+ *
+ * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
+ * (5) On STM32F3, ADC channel available only on all ADC instances, but
+ * only one ADC instance is allowed to be connected to VrefInt at the same time.
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
+{
+ /* Set bits with content of parameter "Channel" with bits position */
+ /* in register depending on parameter "Rank". */
+ /* Parameters "Rank" and "Channel" are used with masks because containing */
+ /* other bits reserved for other purpose. */
+ MODIFY_REG(ADCx->JSQR,
+ ADC_CHANNEL_ID_NUMBER_MASK >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_INJ_RANK_ID_JSQR_MASK)),
+ (Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_INJ_RANK_ID_JSQR_MASK)));
+}
+
+/**
+ * @brief Get ADC group injected sequence: channel on the selected
+ * sequence rank.
+ * @note Depending on devices and packages, some channels may not be available.
+ * Refer to device datasheet for channels availability.
+ * @note Usage of the returned channel number:
+ * - To reinject this channel into another function LL_ADC_xxx:
+ * the returned channel number is only partly formatted on definition
+ * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+ * with parts of literals LL_ADC_CHANNEL_x or using
+ * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * Then the selected literal LL_ADC_CHANNEL_x can be used
+ * as parameter for another function.
+ * - To get the channel number in decimal format:
+ * process the returned value with the helper macro
+ * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * @rmtoll JSQR JSQ1 LL_ADC_INJ_GetSequencerRanks\n
+ * JSQR JSQ2 LL_ADC_INJ_GetSequencerRanks\n
+ * JSQR JSQ3 LL_ADC_INJ_GetSequencerRanks\n
+ * JSQR JSQ4 LL_ADC_INJ_GetSequencerRanks
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
+ *
+ * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
+ * (5) On STM32F3, ADC channel available only on all ADC instances, but
+ * only one ADC instance is allowed to be connected to VrefInt at the same time.\n
+ * (1, 2, 3, 4, 5) For ADC channel read back from ADC register,
+ * comparison with internal channel parameter to be done
+ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ return (uint32_t)(READ_BIT(ADCx->JSQR,
+ ADC_CHANNEL_ID_NUMBER_MASK >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_INJ_RANK_ID_JSQR_MASK)))
+ << (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
+ );
+}
+
+/**
+ * @brief Set ADC group injected conversion trigger:
+ * independent or from ADC group regular.
+ * @note This mode can be used to extend number of data registers
+ * updated after one ADC conversion trigger and with data
+ * permanently kept (not erased by successive conversions of scan of
+ * ADC sequencer ranks), up to 5 data registers:
+ * 1 data register on ADC group regular, 4 data registers
+ * on ADC group injected.
+ * @note If ADC group injected injected trigger source is set to an
+ * external trigger, this feature must be must be set to
+ * independent trigger.
+ * ADC group injected automatic trigger is compliant only with
+ * group injected trigger source set to SW start, without any
+ * further action on ADC group injected conversion start or stop:
+ * in this case, ADC group injected is controlled only
+ * from ADC group regular.
+ * @note It is not possible to enable both ADC group injected
+ * auto-injected mode and sequencer discontinuous mode.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll CFGR JAUTO LL_ADC_INJ_SetTrigAuto
+ * @param ADCx ADC instance
+ * @param TrigAuto This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
+ * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
+{
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, TrigAuto);
+}
+
+/**
+ * @brief Get ADC group injected conversion trigger:
+ * independent or from ADC group regular.
+ * @rmtoll CFGR JAUTO LL_ADC_INJ_GetTrigAuto
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
+ * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO));
+}
+
+/**
+ * @brief Set ADC group injected contexts queue mode.
+ * @note A context is a setting of group injected sequencer:
+ * - group injected trigger
+ * - sequencer length
+ * - sequencer ranks
+ * If contexts queue is disabled:
+ * - only 1 sequence can be configured
+ * and is active perpetually.
+ * If contexts queue is enabled:
+ * - up to 2 contexts can be queued
+ * and are checked in and out as a FIFO stack (first-in, first-out).
+ * - If a new context is set when queues is full, error is triggered
+ * by interruption "Injected Queue Overflow".
+ * - Two behaviors are possible when all contexts have been processed:
+ * the contexts queue can maintain the last context active perpetually
+ * or can be empty and injected group triggers are disabled.
+ * - Triggers can be only external (not internal SW start)
+ * - Caution: The sequence must be fully configured in one time
+ * (one write of register JSQR makes a check-in of a new context
+ * into the queue).
+ * Therefore functions to set separately injected trigger and
+ * sequencer channels cannot be used, register JSQR must be set
+ * using function @ref LL_ADC_INJ_ConfigQueueContext().
+ * @note This parameter can be modified only when no conversion is on going
+ * on either groups regular or injected.
+ * @note A modification of the context mode (bit JQDIS) causes the contexts
+ * queue to be flushed and the register JSQR is cleared.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll CFGR JQM LL_ADC_INJ_SetQueueMode
+ * @param ADCx ADC instance
+ * @param QueueMode This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
+ * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMode)
+{
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM, QueueMode);
+}
+
+/**
+ * @brief Get ADC group injected context queue mode.
+ * @rmtoll CFGR JQM LL_ADC_INJ_GetQueueMode
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
+ * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM));
+}
+
+/**
+ * @brief Set one context on ADC group injected that will be checked in
+ * contexts queue.
+ * @note A context is a setting of group injected sequencer:
+ * - group injected trigger
+ * - sequencer length
+ * - sequencer ranks
+ * This function is intended to be used when contexts queue is enabled,
+ * because the sequence must be fully configured in one time
+ * (functions to set separately injected trigger and sequencer channels
+ * cannot be used):
+ * Refer to function @ref LL_ADC_INJ_SetQueueMode().
+ * @note In the contexts queue, only the active context can be read.
+ * The parameters of this function can be read using functions:
+ * @arg @ref LL_ADC_INJ_GetTriggerSource()
+ * @arg @ref LL_ADC_INJ_GetTriggerEdge()
+ * @arg @ref LL_ADC_INJ_GetSequencerRanks()
+ * @note On this STM32 serie, to measure internal channels (VrefInt,
+ * TempSensor, ...), measurement paths to internal channels must be
+ * enabled separately.
+ * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must not be disabled. Can be enabled with or without conversion
+ * on going on either groups regular or injected.
+ * @rmtoll JSQR JEXTSEL LL_ADC_INJ_ConfigQueueContext\n
+ * JSQR JEXTEN LL_ADC_INJ_ConfigQueueContext\n
+ * JSQR JL LL_ADC_INJ_ConfigQueueContext\n
+ * JSQR JSQ1 LL_ADC_INJ_ConfigQueueContext\n
+ * JSQR JSQ2 LL_ADC_INJ_ConfigQueueContext\n
+ * JSQR JSQ3 LL_ADC_INJ_ConfigQueueContext\n
+ * JSQR JSQ4 LL_ADC_INJ_ConfigQueueContext
+ * @param ADCx ADC instance
+ * @param TriggerSource This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (3)(4)(5)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO__ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (3)(4)(5)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (1)(2)(3)(4)(5)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (3)(4)(5)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (3)(4)(5)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (3)(4)(5)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4_ADC12 (1)(2)(3)(4)(5) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (3) (5)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO__ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (3)(4)(5)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (1)(2)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (1)(2)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4__ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO_ADC12 (1) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2_ADC12 (1) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4_ADC12 (1) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRG_ADC34 (1) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRG2_ADC34 (1) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2_ADC34 (1) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 (4)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 (4)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (3)(4)(5)(6)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15_ADC12 (1)(2) (7)
+ *
+ * (1) On STM32F3, parameter not available on all devices: among others, on STM32F303xE, STM32F398xx.\n
+ * (2) On STM32F3, parameter not available on all devices: among others, on STM32F303xC, STM32F358xx.\n
+ * (3) On STM32F3, parameter not available on all devices: among others, on STM32F303x8, STM32F328xx.\n
+ * (4) On STM32F3, parameter not available on all devices: among others, on STM32F334x8.\n
+ * (5) On STM32F3, parameter not available on all devices: among others, on STM32F302xC, STM32F302xE.\n
+ * (6) On STM32F3, parameter not available on all devices: among others, on STM32F301x8, STM32F302x8, STM32F318xx.\n
+ * (7) On STM32F3, parameter not available on all ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n
+ * (8) On STM32F3, parameter not available on all ADC instances: ADC3, ADC4 (for ADC instances ADCx available on the selected device).
+ * @param ExternalTriggerEdge This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
+ *
+ * Note: This parameter is discarded in case of SW start:
+ * parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE".
+ * @param SequencerNbRanks This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
+ * @param Rank1_Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
+ *
+ * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
+ * (5) On STM32F3, ADC channel available only on all ADC instances, but
+ * only one ADC instance is allowed to be connected to VrefInt at the same time.
+ * @param Rank2_Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
+ *
+ * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
+ * (5) On STM32F3, ADC channel available only on all ADC instances, but
+ * only one ADC instance is allowed to be connected to VrefInt at the same time.
+ * @param Rank3_Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
+ *
+ * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
+ * (5) On STM32F3, ADC channel available only on all ADC instances, but
+ * only one ADC instance is allowed to be connected to VrefInt at the same time.
+ * @param Rank4_Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
+ *
+ * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
+ * (5) On STM32F3, ADC channel available only on all ADC instances, but
+ * only one ADC instance is allowed to be connected to VrefInt at the same time.
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx,
+ uint32_t TriggerSource,
+ uint32_t ExternalTriggerEdge,
+ uint32_t SequencerNbRanks,
+ uint32_t Rank1_Channel,
+ uint32_t Rank2_Channel,
+ uint32_t Rank3_Channel,
+ uint32_t Rank4_Channel)
+{
+ /* Set bits with content of parameter "Rankx_Channel" with bits position */
+ /* in register depending on literal "LL_ADC_INJ_RANK_x". */
+ /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks */
+ /* because containing other bits reserved for other purpose. */
+ /* If parameter "TriggerSource" is set to SW start, then parameter */
+ /* "ExternalTriggerEdge" is discarded. */
+ MODIFY_REG(ADCx->JSQR ,
+ ADC_JSQR_JEXTSEL |
+ ADC_JSQR_JEXTEN |
+ ADC_JSQR_JSQ4 |
+ ADC_JSQR_JSQ3 |
+ ADC_JSQR_JSQ2 |
+ ADC_JSQR_JSQ1 |
+ ADC_JSQR_JL ,
+ TriggerSource |
+ (ExternalTriggerEdge * ((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE))) |
+ ((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK))) |
+ ((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK))) |
+ ((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK))) |
+ ((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK))) |
+ SequencerNbRanks
+ );
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
+ * @{
+ */
+
+/**
+ * @brief Set sampling time of the selected ADC channel
+ * Unit: ADC clock cycles.
+ * @note On this device, sampling time is on channel scope: independently
+ * of channel mapped on ADC group regular or injected.
+ * @note In case of internal channel (VrefInt, TempSensor, ...) to be
+ * converted:
+ * sampling time constraints must be respected (sampling time can be
+ * adjusted in function of ADC clock frequency and sampling time
+ * setting).
+ * Refer to device datasheet for timings values (parameters TS_vrefint,
+ * TS_temp, ...).
+ * @note Conversion time is the addition of sampling time and processing time.
+ * On this STM32 serie, ADC processing time is:
+ * - 12.5 ADC clock cycles at ADC resolution 12 bits
+ * - 10.5 ADC clock cycles at ADC resolution 10 bits
+ * - 8.5 ADC clock cycles at ADC resolution 8 bits
+ * - 6.5 ADC clock cycles at ADC resolution 6 bits
+ * @note In case of ADC conversion of internal channel (VrefInt,
+ * temperature sensor, ...), a sampling time minimum value
+ * is required.
+ * Refer to device datasheet.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll SMPR1 SMP0 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP1 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP2 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP3 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP4 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP5 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP6 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP7 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP8 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP9 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP10 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP11 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP12 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP13 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP14 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP15 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP16 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP17 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP18 LL_ADC_SetChannelSamplingTime
+ * @param ADCx ADC instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
+ *
+ * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
+ * (5) On STM32F3, ADC channel available only on all ADC instances, but
+ * only one ADC instance is allowed to be connected to VrefInt at the same time.
+ * @param SamplingTime This parameter can be one of the following values:
+ * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_4CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_61CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_181CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_601CYCLES_5
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
+{
+ /* Set bits with content of parameter "SamplingTime" with bits position */
+ /* in register and register position depending on parameter "Channel". */
+ /* Parameter "Channel" is used with masks because containing */
+ /* other bits reserved for other purpose. */
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
+
+ MODIFY_REG(*preg,
+ ADC_SMPR1_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK),
+ SamplingTime << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Get sampling time of the selected ADC channel
+ * Unit: ADC clock cycles.
+ * @note On this device, sampling time is on channel scope: independently
+ * of channel mapped on ADC group regular or injected.
+ * @note Conversion time is the addition of sampling time and processing time.
+ * On this STM32 serie, ADC processing time is:
+ * - 12.5 ADC clock cycles at ADC resolution 12 bits
+ * - 10.5 ADC clock cycles at ADC resolution 10 bits
+ * - 8.5 ADC clock cycles at ADC resolution 8 bits
+ * - 6.5 ADC clock cycles at ADC resolution 6 bits
+ * @rmtoll SMPR1 SMP0 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP1 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP2 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP3 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP4 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP5 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP6 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP7 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP8 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP9 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP10 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP11 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP12 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP13 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP14 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP15 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP16 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP17 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP18 LL_ADC_GetChannelSamplingTime
+ * @param ADCx ADC instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
+ *
+ * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
+ * (5) On STM32F3, ADC channel available only on all ADC instances, but
+ * only one ADC instance is allowed to be connected to VrefInt at the same time.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_4CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_61CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_181CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_601CYCLES_5
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
+{
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
+
+ return (uint32_t)(READ_BIT(*preg,
+ ADC_SMPR1_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK))
+ >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)
+ );
+}
+
+/**
+ * @brief Set mode single-ended or differential input of the selected
+ * ADC channel.
+ * @note Channel ending is on channel scope: independently of channel mapped
+ * on ADC group regular or injected.
+ * In differential mode: Differential measurement is carried out
+ * between the selected channel 'i' (positive input) and
+ * channel 'i+1' (negative input). Only channel 'i' has to be
+ * configured, channel 'i+1' is configured automatically.
+ * @note Refer to Reference Manual to ensure the selected channel is
+ * available in differential mode.
+ * For example, internal channels (VrefInt, TempSensor, ...) are
+ * not available in differential mode.
+ * @note When configuring a channel 'i' in differential mode,
+ * the channel 'i+1' is not usable separately.
+ * @note On STM32F3, channels 16, 17, 18 of ADC1,
+ * channels 17, 18 of ADC2, ADC3, ADC4 (if available)
+ * are internally fixed to single-ended inputs configuration.
+ * @note For ADC channels configured in differential mode, both inputs
+ * should be biased at (Vref+)/2 +/-200mV.
+ * (Vref+ is the analog voltage reference)
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be ADC disabled.
+ * @note One or several values can be selected.
+ * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
+ * @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSamplingTime
+ * @param ADCx ADC instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16 (1)
+ *
+ * (1) On STM32F3, parameter available only on ADC instance: ADC1.
+ * @param SingleDiff This parameter can be a combination of the following values:
+ * @arg @ref LL_ADC_SINGLE_ENDED
+ * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
+{
+ /* Bits of channels in single or differential mode are set only for */
+ /* differential mode (for single mode, mask of bits allowed to be set is */
+ /* shifted out of range of bits of channels in single or differential mode. */
+ MODIFY_REG(ADCx->DIFSEL,
+ Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
+ (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL << (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
+}
+
+/**
+ * @brief Get mode single-ended or differential input of the selected
+ * ADC channel.
+ * @note When configuring a channel 'i' in differential mode,
+ * the channel 'i+1' is not usable separately.
+ * Therefore, to ensure a channel is configured in single-ended mode,
+ * the configuration of channel itself and the channel 'i-1' must be
+ * read back (to ensure that the selected channel channel has not been
+ * configured in differential mode by the previous channel).
+ * @note Refer to Reference Manual to ensure the selected channel is
+ * available in differential mode.
+ * For example, internal channels (VrefInt, TempSensor, ...) are
+ * not available in differential mode.
+ * @note When configuring a channel 'i' in differential mode,
+ * the channel 'i+1' is not usable separately.
+ * @note On STM32F3, channels 16, 17, 18 of ADC1,
+ * channels 17, 18 of ADC2, ADC3, ADC4 (if available)
+ * are internally fixed to single-ended inputs configuration.
+ * @note One or several values can be selected. In this case, the value
+ * returned is null if all channels are in single ended-mode.
+ * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
+ * @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSamplingTime
+ * @param ADCx ADC instance
+ * @param Channel This parameter can be a combination of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16 (1)
+ *
+ * (1) On STM32F3, parameter available only on ADC instance: ADC1.
+ * @retval 0: channel in single-ended mode, else: channel in differential mode
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel)
+{
+ return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
+ * @{
+ */
+
+/**
+ * @brief Set ADC analog watchdog monitored channels:
+ * a single channel, multiple channels or all channels,
+ * on ADC groups regular and-or injected.
+ * @note Once monitored channels are selected, analog watchdog
+ * is enabled.
+ * @note In case of need to define a single channel to monitor
+ * with analog watchdog from sequencer channel definition,
+ * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
+ * @note On this STM32 serie, there are 2 kinds of analog watchdog
+ * instance:
+ * - AWD standard (instance AWD1):
+ * - channels monitored: can monitor 1 channel or all channels.
+ * - groups monitored: ADC groups regular and-or injected.
+ * - resolution: resolution is not limited (corresponds to
+ * ADC resolution configured).
+ * - AWD flexible (instances AWD2, AWD3):
+ * - channels monitored: flexible on channels monitored, selection is
+ * channel wise, from from 1 to all channels.
+ * Specificity of this analog watchdog: Multiple channels can
+ * be selected. For example:
+ * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
+ * - groups monitored: not selection possible (monitoring on both
+ * groups regular and injected).
+ * Channels selected are monitored on groups regular and injected:
+ * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
+ * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
+ * - resolution: resolution is limited to 8 bits: if ADC resolution is
+ * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
+ * the 2 LSB are ignored.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll CFGR AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
+ * CFGR AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
+ * CFGR AWD1EN LL_ADC_SetAnalogWDMonitChannels\n
+ * CFGR JAWD1EN LL_ADC_SetAnalogWDMonitChannels\n
+ * AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels\n
+ * AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels
+ * @param ADCx ADC instance
+ * @param AWDy This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD1
+ * @arg @ref LL_ADC_AWD2
+ * @arg @ref LL_ADC_AWD3
+ * @param AWDChannelGroup This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD_DISABLE
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)(5)
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(5)
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (5)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP1_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG (0)(2)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP2_INJ (0)(2)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG_INJ (2)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP3_REG (0)(3)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP3_INJ (0)(3)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP3_REG_INJ (3)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG (0)(4)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP4_INJ (0)(4)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG_INJ (4)
+ *
+ * (0) On STM32F3, parameter available only on analog watchdog number: AWD1.\n
+ * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
+ * (5) On STM32F3, ADC channel available only on all ADC instances, but
+ * only one ADC instance is allowed to be connected to VrefInt at the same time.
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
+{
+ /* Set bits with content of parameter "AWDChannelGroup" with bits position */
+ /* in register and register position depending on parameter "AWDy". */
+ /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */
+ /* containing other bits reserved for other purpose. */
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, __ADC_MASK_SHIFT(AWDy, ADC_AWD_CRX_REGOFFSET_MASK)
+ + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
+
+ MODIFY_REG(*preg,
+ (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
+ AWDChannelGroup & AWDy);
+}
+
+/**
+ * @brief Get ADC analog watchdog monitored channel.
+ * @note Usage of the returned channel number:
+ * - To reinject this channel into another function LL_ADC_xxx:
+ * the returned channel number is only partly formatted on definition
+ * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+ * with parts of literals LL_ADC_CHANNEL_x or using
+ * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * Then the selected literal LL_ADC_CHANNEL_x can be used
+ * as parameter for another function.
+ * - To get the channel number in decimal format:
+ * process the returned value with the helper macro
+ * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * Applicable only when the analog watchdog is set to monitor
+ * one channel.
+ * @note On this STM32 serie, there are 2 kinds of analog watchdog
+ * instance:
+ * - AWD standard (instance AWD1):
+ * - channels monitored: can monitor 1 channel or all channels.
+ * - groups monitored: ADC groups regular and-or injected.
+ * - resolution: resolution is not limited (corresponds to
+ * ADC resolution configured).
+ * - AWD flexible (instances AWD2, AWD3):
+ * - channels monitored: flexible on channels monitored, selection is
+ * channel wise, from from 1 to all channels.
+ * Specificity of this analog watchdog: Multiple channels can
+ * be selected. For example:
+ * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
+ * - groups monitored: not selection possible (monitoring on both
+ * groups regular and injected).
+ * Channels selected are monitored on groups regular and injected:
+ * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
+ * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
+ * - resolution: resolution is limited to 8 bits: if ADC resolution is
+ * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
+ * the 2 LSB are ignored.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll CFGR AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
+ * CFGR AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
+ * CFGR AWD1EN LL_ADC_GetAnalogWDMonitChannels\n
+ * CFGR JAWD1EN LL_ADC_GetAnalogWDMonitChannels\n
+ * AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels\n
+ * AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels
+ * @param ADCx ADC instance
+ * @param AWDy This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD1
+ * @arg @ref LL_ADC_AWD2 (1)
+ * @arg @ref LL_ADC_AWD3 (1)
+ *
+ * (1) On this AWD number, monitored channel can be retrieved
+ * if only 1 channel is programmed (or none or all channels).
+ * This function cannot retrieve monitored channel if
+ * multiple channels are programmed simultaneously
+ * by bitfield.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_AWD_DISABLE
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
+ *
+ * (0) On STM32F3, parameter available only on analog watchdog number: AWD1.
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy)
+{
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, __ADC_MASK_SHIFT(AWDy, ADC_AWD_CRX_REGOFFSET_MASK)
+ + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
+
+ /* Variable "AWDy" used to retrieve appropriate bitfield corresponding to */
+ /* ADC_AWD_CR1_CHANNEL_MASK or ADC_AWD_CR23_CHANNEL_MASK. */
+ register uint32_t AWD123ChannelGroup = READ_BIT(*preg, (AWDy | ADC_AWD_CR_ALL_CHANNEL_MASK));
+
+ /* Set variable of AWD1 monitored channel according to AWD1 features */
+ /* and ADC channel definition: */
+ /* - channel ID with number */
+ /* - channel ID with bitfield */
+ /* - AWD1 single or all channels */
+ /* - AWD1 enable or disable (also used to discard AWD1 bitfield in case of */
+ /* AWD2 or AWD3 selected). */
+ register uint32_t AWD1ChannelSingle = ((AWD123ChannelGroup & ADC_CFGR_AWD1SGL) >> ADC_CFGR_AWD1SGL_BITOFFSET_POS);
+
+ register uint32_t AWD1ChannelGroup = ( ( AWD123ChannelGroup
+ | ((ADC_CHANNEL_0_BITFIELD << ((AWD123ChannelGroup & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)) * AWD1ChannelSingle)
+ | (ADC_CHANNEL_ID_BITFIELD_MASK * (~AWD1ChannelSingle & ((uint32_t)0x00000001U)))
+ )
+ * (((AWD123ChannelGroup & ADC_CFGR_JAWD1EN) >> ADC_CFGR_JAWD1EN_BITOFFSET_POS) | ((AWD123ChannelGroup & ADC_CFGR_AWD1EN) >> ADC_CFGR_AWD1EN_BITOFFSET_POS))
+ );
+
+ /* Set variable of AWD2 and AWD3 monitored channel according to AWD2-3 */
+ /* features and ADC channel definition: */
+ /* - channel ID with number */
+ /* - channel ID with bitfield */
+ /* - AWD2-3 single or all channels (shift value 32 (0x1 shift 5) used to */
+ /* shift AWD1 equivalent single-all channels out of register) */
+ /* - AWD2-3 enable or disable */
+ /* Note: Use modulo 3 to avoid a shift value too long. On AWD2 and AWD3, */
+ /* channel can be read back if only 1 channel monitoring */
+ /* is activated, therefore the channel monitoring value channel "3" */
+ /* is not not supported by this function, there is no risk of */
+ /* conflict. */
+ register uint32_t AWD23Enabled = ((((uint32_t)0x00000001U) >> (AWD123ChannelGroup % 3U)) << 6U); /* Value "0" if AWD2-3 is enabled, value "32" if AWD2-3 is disabled */
+
+ register uint32_t AWD23ChannelGroup = ((( AWD123ChannelGroup
+ | ((uint32_t)POSITION_VAL(AWD123ChannelGroup) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
+ | ((ADC_CFGR_AWD1SGL) >> ((((uint32_t)0x00000001U) >> (ADC_AWD_CR23_CHANNEL_MASK - AWD123ChannelGroup)) << 5U))
+ | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN)
+ ) >> AWD23Enabled
+ ) >> (((AWDy & ADC_CFGR_AWD1SGL) >> ADC_CFGR_AWD1SGL_BITOFFSET_POS) << 5U));
+
+ return (AWD1ChannelGroup | AWD23ChannelGroup);
+}
+
+/**
+ * @brief Set ADC analog watchdog thresholds value of both thresholds
+ * high and low.
+ * @note If value of only one threshold high or low must be set,
+ * use function @ref LL_ADC_SetAnalogWDThresholds().
+ * @note In case of ADC resolution different of 12 bits,
+ * analog watchdog thresholds data require a specific shift.
+ * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
+ * @note On this STM32 serie, there are 2 kinds of analog watchdog
+ * instance:
+ * - AWD standard (instance AWD1):
+ * - channels monitored: can monitor 1 channel or all channels.
+ * - groups monitored: ADC groups regular and-or injected.
+ * - resolution: resolution is not limited (corresponds to
+ * ADC resolution configured).
+ * - AWD flexible (instances AWD2, AWD3):
+ * - channels monitored: flexible on channels monitored, selection is
+ * channel wise, from from 1 to all channels.
+ * Specificity of this analog watchdog: Multiple channels can
+ * be selected. For example:
+ * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
+ * - groups monitored: not selection possible (monitoring on both
+ * groups regular and injected).
+ * Channels selected are monitored on groups regular and injected:
+ * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
+ * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
+ * - resolution: resolution is limited to 8 bits: if ADC resolution is
+ * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
+ * the 2 LSB are ignored.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll TR1 HT1 LL_ADC_ConfigAnalogWDThresholds\n
+ * TR2 HT2 LL_ADC_ConfigAnalogWDThresholds\n
+ * TR3 HT3 LL_ADC_ConfigAnalogWDThresholds\n
+ * TR1 LT1 LL_ADC_ConfigAnalogWDThresholds\n
+ * TR2 LT2 LL_ADC_ConfigAnalogWDThresholds\n
+ * TR3 LT3 LL_ADC_ConfigAnalogWDThresholds
+ * @param ADCx ADC instance
+ * @param AWDy This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD1
+ * @arg @ref LL_ADC_AWD2
+ * @arg @ref LL_ADC_AWD3
+ * @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue, uint32_t AWDThresholdLowValue)
+{
+ /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */
+ /* position in register and register position depending on parameter */
+ /* "AWDy". */
+ /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
+ /* containing other bits reserved for other purpose. */
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK));
+
+ MODIFY_REG(*preg,
+ ADC_TR1_HT1 | ADC_TR1_LT1,
+ (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue);
+}
+
+/**
+ * @brief Set ADC analog watchdog threshold value of threshold
+ * high or low.
+ * @note If values of both thresholds high or low must be set,
+ * use function @ref LL_ADC_ConfigAnalogWDThresholds().
+ * @note In case of ADC resolution different of 12 bits,
+ * analog watchdog thresholds data require a specific shift.
+ * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
+ * @note On this STM32 serie, there are 2 kinds of analog watchdog
+ * instance:
+ * - AWD standard (instance AWD1):
+ * - channels monitored: can monitor 1 channel or all channels.
+ * - groups monitored: ADC groups regular and-or injected.
+ * - resolution: resolution is not limited (corresponds to
+ * ADC resolution configured).
+ * - AWD flexible (instances AWD2, AWD3):
+ * - channels monitored: flexible on channels monitored, selection is
+ * channel wise, from from 1 to all channels.
+ * Specificity of this analog watchdog: Multiple channels can
+ * be selected. For example:
+ * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
+ * - groups monitored: not selection possible (monitoring on both
+ * groups regular and injected).
+ * Channels selected are monitored on groups regular and injected:
+ * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
+ * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
+ * - resolution: resolution is limited to 8 bits: if ADC resolution is
+ * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
+ * the 2 LSB are ignored.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll TR1 HT1 LL_ADC_SetAnalogWDThresholds\n
+ * TR2 HT2 LL_ADC_SetAnalogWDThresholds\n
+ * TR3 HT3 LL_ADC_SetAnalogWDThresholds\n
+ * TR1 LT1 LL_ADC_SetAnalogWDThresholds\n
+ * TR2 LT2 LL_ADC_SetAnalogWDThresholds\n
+ * TR3 LT3 LL_ADC_SetAnalogWDThresholds
+ * @param ADCx ADC instance
+ * @param AWDy This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD1
+ * @arg @ref LL_ADC_AWD2
+ * @arg @ref LL_ADC_AWD3
+ * @param AWDThresholdsHighLow This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
+ * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
+ * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
+{
+ /* Set bits with content of parameter "AWDThresholdValue" with bits */
+ /* position in register and register position depending on parameters */
+ /* "AWDThresholdsHighLow" and "AWDy". */
+ /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
+ /* containing other bits reserved for other purpose. */
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK));
+
+ MODIFY_REG(*preg,
+ AWDThresholdsHighLow,
+ AWDThresholdValue << POSITION_VAL(AWDThresholdsHighLow));
+}
+
+/**
+ * @brief Get ADC analog watchdog threshold value of threshold high,
+ * threshold low or raw data with ADC thresholds high and low
+ * concatenated.
+ * @note If raw data with ADC thresholds high and low is retrieved,
+ * the data of each threshold high or low can be isolated
+ * using helper macro:
+ * @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
+ * @note In case of ADC resolution different of 12 bits,
+ * analog watchdog thresholds data require a specific shift.
+ * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
+ * @rmtoll TR1 HT1 LL_ADC_GetAnalogWDThresholds\n
+ * TR2 HT2 LL_ADC_GetAnalogWDThresholds\n
+ * TR3 HT3 LL_ADC_GetAnalogWDThresholds\n
+ * TR1 LT1 LL_ADC_GetAnalogWDThresholds\n
+ * TR2 LT2 LL_ADC_GetAnalogWDThresholds\n
+ * TR3 LT3 LL_ADC_GetAnalogWDThresholds
+ * @param ADCx ADC instance
+ * @param AWDy This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD1
+ * @arg @ref LL_ADC_AWD2
+ * @arg @ref LL_ADC_AWD3
+ * @param AWDThresholdsHighLow This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
+ * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
+ * @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+*/
+__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
+{
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK));
+
+ return (uint32_t)(READ_BIT(*preg,
+ (AWDThresholdsHighLow | ADC_TR1_LT1))
+ >> POSITION_VAL(AWDThresholdsHighLow)
+ );
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode
+ * @{
+ */
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Set ADC multimode configuration to operate in independent mode
+ * or multimode (for devices with several ADC instances).
+ * @note If multimode configuration: the selected ADC instance is
+ * either master or slave depending on hardware.
+ * Refer to reference manual.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * All ADC instances of the ADC common group must be disabled.
+ * This check can be done with function @ref LL_ADC_IsEnabled() for each
+ * ADC instance or by using helper macro
+ * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
+ * @rmtoll CCR DUAL LL_ADC_SetMultimode
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param Multimode This parameter can be one of the following values:
+ * @arg @ref LL_ADC_MULTI_INDEPENDENT
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
+ * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
+ * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
+{
+ MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode);
+}
+
+/**
+ * @brief Get ADC multimode configuration to operate in independent mode
+ * or multimode (for devices with several ADC instances).
+ * @note If multimode configuration: the selected ADC instance is
+ * either master or slave depending on hardware.
+ * Refer to reference manual.
+ * @rmtoll CCR DUAL LL_ADC_GetMultimode
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_MULTI_INDEPENDENT
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
+ * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
+ * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
+}
+
+/**
+ * @brief Set ADC multimode conversion data transfer: no transfer
+ * or transfer by DMA.
+ * @note If ADC multimode transfer by DMA is not selected:
+ * each ADC uses its own DMA channel, with its individual
+ * DMA transfer settings.
+ * If ADC multimode transfer by DMA is selected:
+ * One DMA channel is used for both ADC (DMA of ADC master)
+ * Specifies the DMA requests mode:
+ * - Limited mode (One shot mode): DMA transfer requests are stopped
+ * when number of DMA data transfers (number of
+ * ADC conversions) is reached.
+ * This ADC mode is intended to be used with DMA mode non-circular.
+ * - Unlimited mode: DMA transfer requests are unlimited,
+ * whatever number of DMA data transfers (number of
+ * ADC conversions).
+ * This ADC mode is intended to be used with DMA mode circular.
+ * @note If ADC DMA requests mode is set to unlimited and DMA is set to
+ * mode non-circular:
+ * when DMA transfers size will be reached, DMA will stop transfers of
+ * ADC conversions data ADC will raise an overrun error
+ * (overrun flag and interruption if enabled).
+ * @note How to retrieve multimode conversion data:
+ * Whatever multimode transfer by DMA setting: using function
+ * @ref LL_ADC_REG_ReadMultiConversionData32().
+ * If ADC multimode transfer by DMA is selected: conversion data
+ * is a raw data with ADC master and slave concatenated.
+ * A macro is available to get the conversion data of
+ * ADC master or ADC slave: see helper macro
+ * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * All ADC instances of the ADC common group must be disabled
+ * or enabled without conversion on going on group regular.
+ * @rmtoll CCR MDMA LL_ADC_SetMultiDMATransfer\n
+ * CCR DMACFG LL_ADC_SetMultiDMATransfer
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param MultiDMATransfer This parameter can be one of the following values:
+ * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
+ * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
+ * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
+ * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
+ * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
+{
+ MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG, MultiDMATransfer);
+}
+
+/**
+ * @brief Get ADC multimode conversion data transfer: no transfer
+ * or transfer by DMA.
+ * @note If ADC multimode transfer by DMA is not selected:
+ * each ADC uses its own DMA channel, with its individual
+ * DMA transfer settings.
+ * If ADC multimode transfer by DMA is selected:
+ * One DMA channel is used for both ADC (DMA of ADC master)
+ * Specifies the DMA requests mode:
+ * - Limited mode (One shot mode): DMA transfer requests are stopped
+ * when number of DMA data transfers (number of
+ * ADC conversions) is reached.
+ * This ADC mode is intended to be used with DMA mode non-circular.
+ * - Unlimited mode: DMA transfer requests are unlimited,
+ * whatever number of DMA data transfers (number of
+ * ADC conversions).
+ * This ADC mode is intended to be used with DMA mode circular.
+ * @note If ADC DMA requests mode is set to unlimited and DMA is set to
+ * mode non-circular:
+ * when DMA transfers size will be reached, DMA will stop transfers of
+ * ADC conversions data ADC will raise an overrun error
+ * (overrun flag and interruption if enabled).
+ * @note How to retrieve multimode conversion data:
+ * Whatever multimode transfer by DMA setting: using function
+ * @ref LL_ADC_REG_ReadMultiConversionData32().
+ * If ADC multimode transfer by DMA is selected: conversion data
+ * is a raw data with ADC master and slave concatenated.
+ * A macro is available to get the conversion data of
+ * ADC master or ADC slave: see helper macro
+ * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
+ * @rmtoll CCR MDMA LL_ADC_GetMultiDMATransfer\n
+ * CCR DMACFG LL_ADC_GetMultiDMATransfer
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
+ * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
+ * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
+ * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
+ * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG));
+}
+
+/**
+ * @brief Set ADC multimode delay between 2 sampling phases.
+ * @note The sampling delay range depends on ADC resolution:
+ * - ADC resolution 12 bits can have maximum delay of 12 cycles.
+ * - ADC resolution 10 bits can have maximum delay of 10 cycles.
+ * - ADC resolution 8 bits can have maximum delay of 8 cycles.
+ * - ADC resolution 6 bits can have maximum delay of 6 cycles.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * All ADC instances of the ADC common group must be disabled.
+ * This check can be done with function @ref LL_ADC_IsEnabled() for each
+ * ADC instance or by using helper macro helper macro
+ * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
+ * @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param MultiTwoSamplingDelay This parameter can be one of the following values:
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1)
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1)
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2)
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2)
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
+ *
+ * (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
+ * (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
+ * (3) Parameter available only if ADC resolution is 12 bits.
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
+{
+ MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
+}
+
+/**
+ * @brief Get ADC multimode delay between 2 sampling phases.
+ * @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1)
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1)
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2)
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2)
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
+ *
+ * (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
+ * (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
+ * (3) Parameter available only if ADC resolution is 12 bits.
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @}
+ */
+/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
+ * @{
+ */
+
+/**
+ * @brief Enable ADC instance internal voltage regulator.
+ * @note On this STM32 serie, after ADC internal voltage regulator enable,
+ * a delay for ADC internal voltage regulator stabilization
+ * is required before performing a ADC calibration or ADC enable.
+ * Refer to device datasheet, parameter tADCVREG_STUP.
+ * Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be ADC disabled.
+ * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
+{
+ /* 1. Set the intermediate state before moving the ADC voltage regulator */
+ /* to state enable. */
+ CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN_1 | ADC_CR_ADVREGEN_0));
+ /* 2. Set the final state of ADC voltage regulator enable */
+ /* (ADVREGEN bits set to 0x01). */
+ /* Note: Write register with some additional bits forced to state reset */
+ /* instead of modifying only the selected bit for this function, */
+ /* to not interfere with bits with HW property "rs". */
+ MODIFY_REG(ADCx->CR,
+ ADC_CR_BITS_PROPERTY_RS,
+ ADC_CR_ADVREGEN_0);
+}
+
+/**
+ * @brief Disable ADC internal voltage regulator.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be ADC disabled.
+ * @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
+}
+
+/**
+ * @brief Get the selected ADC instance internal voltage regulator state.
+ * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
+ * @param ADCx ADC instance
+ * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->CR, (ADC_CR_ADVREGEN_1 | ADC_CR_ADVREGEN_0)) == (ADC_CR_ADVREGEN_0));
+}
+
+/**
+ * @brief Enable the selected ADC instance.
+ * @note On this STM32 serie, after ADC enable, a delay for
+ * ADC internal analog stabilization is required before performing a
+ * ADC conversion start.
+ * Refer to device datasheet, parameter tSTAB.
+ * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+ * is enabled and when conversion clock is active.
+ * (not only core clock: this ADC has a dual clock domain)
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be ADC disabled and ADC internal voltage regulator enabled.
+ * @rmtoll CR ADEN LL_ADC_Enable
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
+{
+ /* Note: Write register with some additional bits forced to state reset */
+ /* instead of modifying only the selected bit for this function, */
+ /* to not interfere with bits with HW property "rs". */
+ MODIFY_REG(ADCx->CR,
+ ADC_CR_BITS_PROPERTY_RS,
+ ADC_CR_ADEN);
+}
+
+/**
+ * @brief Disable the selected ADC instance.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be not disabled. Must be enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll CR ADDIS LL_ADC_Disable
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
+{
+ /* Note: Write register with some additional bits forced to state reset */
+ /* instead of modifying only the selected bit for this function, */
+ /* to not interfere with bits with HW property "rs". */
+ MODIFY_REG(ADCx->CR,
+ ADC_CR_BITS_PROPERTY_RS,
+ ADC_CR_ADDIS);
+}
+
+/**
+ * @brief Get the selected ADC instance enable state.
+ * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+ * is enabled and when conversion clock is active.
+ * (not only core clock: this ADC has a dual clock domain)
+ * @rmtoll CR ADEN LL_ADC_IsEnabled
+ * @param ADCx ADC instance
+ * @retval 0: ADC is disabled, 1: ADC is enabled.
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN));
+}
+
+/**
+ * @brief Get the selected ADC instance disable state.
+ * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing
+ * @param ADCx ADC instance
+ * @retval 0: no ADC disable command on going.
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS));
+}
+
+/**
+ * @brief Start ADC calibration in the mode single-ended
+ * or differential (for devices with differential mode available).
+ * @note On this STM32 serie, a minimum number of ADC clock cycles
+ * are required between ADC end of calibration and ADC enable.
+ * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
+ * @note For devices with differential mode available:
+ * Calibration of offset is specific to each of
+ * single-ended and differential modes
+ * (calibration run must be performed for each of these
+ * differential modes, if used afterwards and if the application
+ * requires their calibration).
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be ADC disabled.
+ * @rmtoll CR ADCAL LL_ADC_StartCalibration\n
+ * CR ADCALDIF LL_ADC_StartCalibration
+ * @param ADCx ADC instance
+ * @param SingleDiff This parameter can be one of the following values:
+ * @arg @ref LL_ADC_SINGLE_ENDED
+ * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t SingleDiff)
+{
+ /* Note: Write register with some additional bits forced to state reset */
+ /* instead of modifying only the selected bit for this function, */
+ /* to not interfere with bits with HW property "rs". */
+ MODIFY_REG(ADCx->CR,
+ ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS,
+ ADC_CR_ADCAL | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK));
+}
+
+/**
+ * @brief Get ADC calibration state.
+ * @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing
+ * @param ADCx ADC instance
+ * @retval 0: calibration complete, 1: calibration in progress.
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
+ * @{
+ */
+
+/**
+ * @brief Start ADC group regular conversion.
+ * @note On this STM32 serie, this function is relevant for both
+ * internal trigger (SW start) and external trigger:
+ * - If ADC trigger has been set to software start, ADC conversion
+ * starts immediately.
+ * - If ADC trigger has been set to external trigger, ADC conversion
+ * will start at next trigger event (on the selected trigger edge)
+ * following the ADC start conversion command.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be enabled without conversion on going on group regular,
+ * without conversion stop command on going on group regular,
+ * without ADC disable command on going.
+ * @rmtoll CR ADSTART LL_ADC_REG_StartConversion
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
+{
+ /* Note: Write register with some additional bits forced to state reset */
+ /* instead of modifying only the selected bit for this function, */
+ /* to not interfere with bits with HW property "rs". */
+ MODIFY_REG(ADCx->CR,
+ ADC_CR_BITS_PROPERTY_RS,
+ ADC_CR_ADSTART);
+}
+
+/**
+ * @brief Stop ADC group regular conversion.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be enabled with conversion on going on group regular,
+ * without ADC disable command on going.
+ * @rmtoll CR ADSTP LL_ADC_REG_StopConversion
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
+{
+ /* Note: Write register with some additional bits forced to state reset */
+ /* instead of modifying only the selected bit for this function, */
+ /* to not interfere with bits with HW property "rs". */
+ MODIFY_REG(ADCx->CR,
+ ADC_CR_BITS_PROPERTY_RS,
+ ADC_CR_ADSTP);
+}
+
+/**
+ * @brief Get ADC group regular conversion state.
+ * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
+ * @param ADCx ADC instance
+ * @retval 0: no conversion is on going on ADC group regular.
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART));
+}
+
+/**
+ * @brief Get ADC group regular command of conversion stop state
+ * @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing
+ * @param ADCx ADC instance
+ * @retval 0: no command of conversion stop is on going on ADC group regular.
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP));
+}
+
+/**
+ * @brief Get ADC group regular conversion data, range fit for
+ * all ADC configurations: all ADC resolutions and
+ * all oversampling increased data width (for devices
+ * with feature oversampling).
+ * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
+ * @param ADCx ADC instance
+ * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+}
+
+/**
+ * @brief Get ADC group regular conversion data, range fit for
+ * ADC resolution 12 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_REG_ReadConversionData32.
+ * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
+ * @param ADCx ADC instance
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
+{
+ return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+}
+
+/**
+ * @brief Get ADC group regular conversion data, range fit for
+ * ADC resolution 10 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_REG_ReadConversionData32.
+ * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10
+ * @param ADCx ADC instance
+ * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
+ */
+__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
+{
+ return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+}
+
+/**
+ * @brief Get ADC group regular conversion data, range fit for
+ * ADC resolution 8 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_REG_ReadConversionData32.
+ * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8
+ * @param ADCx ADC instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
+{
+ return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+}
+
+/**
+ * @brief Get ADC group regular conversion data, range fit for
+ * ADC resolution 6 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_REG_ReadConversionData32.
+ * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData6
+ * @param ADCx ADC instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x3F
+ */
+__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
+{
+ return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+}
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Get ADC multimode conversion data of ADC master, ADC slave
+ * or raw data with ADC master and slave concatenated.
+ * @note If raw data with ADC master and slave concatenated is retrieved,
+ * a macro is available to get the conversion data of
+ * ADC master or ADC slave: see helper macro
+ * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
+ * (however this macro is mainly intended for multimode
+ * transfer by DMA, because this function can do the same
+ * by getting multimode conversion data of ADC master or ADC slave
+ * separately).
+ * @rmtoll CDR RDATA_MST LL_ADC_REG_ReadMultiConversionData32\n
+ * CDR RDATA_SLV LL_ADC_REG_ReadMultiConversionData32
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param ConversionData This parameter can be one of the following values:
+ * @arg @ref LL_ADC_MULTI_MASTER
+ * @arg @ref LL_ADC_MULTI_SLAVE
+ * @arg @ref LL_ADC_MULTI_MASTER_SLAVE
+ * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)
+{
+ return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,
+ ConversionData)
+ >> POSITION_VAL(ConversionData)
+ );
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
+ * @{
+ */
+
+/**
+ * @brief Start ADC group injected conversion.
+ * @note On this STM32 serie, this function is relevant for both
+ * internal trigger (SW start) and external trigger:
+ * - If ADC trigger has been set to software start, ADC conversion
+ * starts immediately.
+ * - If ADC trigger has been set to external trigger, ADC conversion
+ * will start at next trigger event (on the selected trigger edge)
+ * following the ADC start conversion command.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be enabled without conversion on going on group injected,
+ * without conversion stop command on going on group injected,
+ * without ADC disable command on going.
+ * @rmtoll CR JADSTART LL_ADC_INJ_StartConversion
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)
+{
+ /* Note: Write register with some additional bits forced to state reset */
+ /* instead of modifying only the selected bit for this function, */
+ /* to not interfere with bits with HW property "rs". */
+ MODIFY_REG(ADCx->CR,
+ ADC_CR_BITS_PROPERTY_RS,
+ ADC_CR_JADSTART);
+}
+
+/**
+ * @brief Stop ADC group injected conversion.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be enabled with conversion on going on group injected,
+ * without ADC disable command on going.
+ * @rmtoll CR JADSTP LL_ADC_INJ_StopConversion
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)
+{
+ /* Note: Write register with some additional bits forced to state reset */
+ /* instead of modifying only the selected bit for this function, */
+ /* to not interfere with bits with HW property "rs". */
+ MODIFY_REG(ADCx->CR,
+ ADC_CR_BITS_PROPERTY_RS,
+ ADC_CR_JADSTP);
+}
+
+/**
+ * @brief Get ADC group injected conversion state.
+ * @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing
+ * @param ADCx ADC instance
+ * @retval 0: no conversion is on going on ADC group injected.
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART));
+}
+
+/**
+ * @brief Get ADC group injected command of conversion stop state
+ * @rmtoll CR JADSTP LL_ADC_INJ_IsStopConversionOngoing
+ * @param ADCx ADC instance
+ * @retval 0: no command of conversion stop is on going on ADC group injected.
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP));
+}
+
+/**
+ * @brief Get ADC group regular conversion data, range fit for
+ * all ADC configurations: all ADC resolutions and
+ * all oversampling increased data width (for devices
+ * with feature oversampling).
+ * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n
+ * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n
+ * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n
+ * JDR4 JDATA LL_ADC_INJ_ReadConversionData32
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
+
+ return (uint32_t)(READ_BIT(*preg,
+ ADC_JDR1_JDATA)
+ );
+}
+
+/**
+ * @brief Get ADC group injected conversion data, range fit for
+ * ADC resolution 12 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+ * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n
+ * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n
+ * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n
+ * JDR4 JDATA LL_ADC_INJ_ReadConversionData12
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
+
+ return (uint16_t)(READ_BIT(*preg,
+ ADC_JDR1_JDATA)
+ );
+}
+
+/**
+ * @brief Get ADC group injected conversion data, range fit for
+ * ADC resolution 10 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+ * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n
+ * JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n
+ * JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n
+ * JDR4 JDATA LL_ADC_INJ_ReadConversionData10
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
+ */
+__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
+
+ return (uint16_t)(READ_BIT(*preg,
+ ADC_JDR1_JDATA)
+ );
+}
+
+/**
+ * @brief Get ADC group injected conversion data, range fit for
+ * ADC resolution 8 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+ * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n
+ * JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n
+ * JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n
+ * JDR4 JDATA LL_ADC_INJ_ReadConversionData8
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
+
+ return (uint8_t)(READ_BIT(*preg,
+ ADC_JDR1_JDATA)
+ );
+}
+
+/**
+ * @brief Get ADC group injected conversion data, range fit for
+ * ADC resolution 6 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+ * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData6\n
+ * JDR2 JDATA LL_ADC_INJ_ReadConversionData6\n
+ * JDR3 JDATA LL_ADC_INJ_ReadConversionData6\n
+ * JDR4 JDATA LL_ADC_INJ_ReadConversionData6
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Value between Min_Data=0x00 and Max_Data=0x3F
+ */
+__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
+
+ return (uint8_t)(READ_BIT(*preg,
+ ADC_JDR1_JDATA)
+ );
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
+ * @{
+ */
+
+/**
+ * @brief Get flag ADC ready.
+ * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+ * is enabled and when conversion clock is active.
+ * (not only core clock: this ADC has a dual clock domain)
+ * @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY));
+}
+
+/**
+ * @brief Get flag ADC group regular end of unitary conversion.
+ * @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC));
+}
+
+/**
+ * @brief Get flag ADC group regular end of sequence conversions.
+ * @rmtoll ISR EOS LL_ADC_IsActiveFlag_EOS
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS));
+}
+
+/**
+ * @brief Get flag ADC group regular overrun.
+ * @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR));
+}
+
+/**
+ * @brief Get flag ADC group regular end of sampling phase.
+ * @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP));
+}
+
+/**
+ * @brief Get flag ADC group injected end of unitary conversion.
+ * @rmtoll ISR JEOC LL_ADC_IsActiveFlag_JEOC
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC));
+}
+
+/**
+ * @brief Get flag ADC group injected end of sequence conversions.
+ * @rmtoll ISR JEOS LL_ADC_IsActiveFlag_JEOS
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS));
+}
+
+/**
+ * @brief Get flag ADC group injected contexts queue overflow.
+ * @rmtoll ISR JQOVF LL_ADC_IsActiveFlag_JQOVF
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF));
+}
+
+/**
+ * @brief Get flag ADC analog watchdog 1 flag
+ * @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
+}
+
+/**
+ * @brief Get flag ADC analog watchdog 2.
+ * @rmtoll ISR AWD2 LL_ADC_IsActiveFlag_AWD2
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2));
+}
+
+/**
+ * @brief Get flag ADC analog watchdog 3.
+ * @rmtoll ISR AWD3 LL_ADC_IsActiveFlag_AWD3
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3));
+}
+
+/**
+ * @brief Clear flag ADC ready.
+ * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+ * is enabled and when conversion clock is active.
+ * (not only core clock: this ADC has a dual clock domain)
+ * @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
+}
+
+/**
+ * @brief Clear flag ADC group regular end of unitary conversion.
+ * @rmtoll ISR EOC LL_ADC_ClearFlag_EOC
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
+}
+
+/**
+ * @brief Clear flag ADC group regular end of sequence conversions.
+ * @rmtoll ISR EOS LL_ADC_ClearFlag_EOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
+}
+
+/**
+ * @brief Clear flag ADC group regular overrun.
+ * @rmtoll ISR OVR LL_ADC_ClearFlag_OVR
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
+}
+
+/**
+ * @brief Clear flag ADC group regular end of sampling phase.
+ * @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
+}
+
+/**
+ * @brief Clear flag ADC group injected end of unitary conversion.
+ * @rmtoll ISR JEOC LL_ADC_ClearFlag_JEOC
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC);
+}
+
+/**
+ * @brief Clear flag ADC group injected end of sequence conversions.
+ * @rmtoll ISR JEOS LL_ADC_ClearFlag_JEOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS);
+}
+
+/**
+ * @brief Clear flag ADC group injected contexts queue overflow.
+ * @rmtoll ISR JQOVF LL_ADC_ClearFlag_JQOVF
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JQOVF);
+}
+
+/**
+ * @brief Clear flag ADC analog watchdog 1.
+ * @rmtoll ISR AWD1 LL_ADC_ClearFlag_AWD1
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
+}
+
+/**
+ * @brief Clear flag ADC analog watchdog 2.
+ * @rmtoll ISR AWD2 LL_ADC_ClearFlag_AWD2
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);
+}
+
+/**
+ * @brief Clear flag ADC analog watchdog 3.
+ * @rmtoll ISR AWD3 LL_ADC_ClearFlag_AWD3
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
+}
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Get flag multimode ADC ready of the ADC master.
+ * @rmtoll CSR ADRDY_MST LL_ADC_IsActiveFlag_MST_ADRDY
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST));
+}
+
+/**
+ * @brief Get flag multimode ADC ready of the ADC slave.
+ * @rmtoll CSR ADRDY_SLV LL_ADC_IsActiveFlag_SLV_ADRDY
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV));
+}
+
+/**
+ * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC master.
+ * @rmtoll CSR EOC_MST LL_ADC_IsActiveFlag_MST_EOC
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV));
+}
+
+/**
+ * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC slave.
+ * @rmtoll CSR EOC_SLV LL_ADC_IsActiveFlag_SLV_EOC
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV));
+}
+
+/**
+ * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC master.
+ * @rmtoll CSR EOS_MST LL_ADC_IsActiveFlag_MST_EOS
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST));
+}
+
+/**
+ * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC slave.
+ * @rmtoll CSR EOS_SLV LL_ADC_IsActiveFlag_SLV_EOS
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV));
+}
+
+/**
+ * @brief Get flag multimode ADC group regular overrun of the ADC master.
+ * @rmtoll CSR OVR_MST LL_ADC_IsActiveFlag_MST_OVR
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST));
+}
+
+/**
+ * @brief Get flag multimode ADC group regular overrun of the ADC slave.
+ * @rmtoll CSR OVR_SLV LL_ADC_IsActiveFlag_SLV_OVR
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV));
+}
+
+/**
+ * @brief Get flag multimode ADC group regular end of sampling of the ADC master.
+ * @rmtoll CSR EOSMP_MST LL_ADC_IsActiveFlag_MST_EOSMP
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST));
+}
+
+/**
+ * @brief Get flag multimode ADC group regular end of sampling of the ADC slave.
+ * @rmtoll CSR EOSMP_SLV LL_ADC_IsActiveFlag_SLV_EOSMP
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV));
+}
+
+/**
+ * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC master.
+ * @rmtoll CSR JEOC_MST LL_ADC_IsActiveFlag_MST_JEOC
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST));
+}
+
+/**
+ * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC slave.
+ * @rmtoll CSR JEOC_SLV LL_ADC_IsActiveFlag_SLV_JEOC
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV));
+}
+
+/**
+ * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master.
+ * @rmtoll CSR JEOS_MST LL_ADC_IsActiveFlag_MST_JEOS
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST));
+}
+
+/**
+ * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave.
+ * @rmtoll CSR JEOS_SLV LL_ADC_IsActiveFlag_SLV_JEOS
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV));
+}
+
+/**
+ * @brief Get flag multimode ADC group injected context queue overflow of the ADC master.
+ * @rmtoll CSR JQOVF_MST LL_ADC_IsActiveFlag_MST_JQOVF
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST));
+}
+
+/**
+ * @brief Get flag multimode ADC group injected context queue overflow of the ADC slave.
+ * @rmtoll CSR JQOVF_SLV LL_ADC_IsActiveFlag_SLV_JQOVF
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV));
+}
+
+/**
+ * @brief Get flag multimode ADC analog watchdog 1 of the ADC master.
+ * @rmtoll CSR AWD1_MST LL_ADC_IsActiveFlag_MST_AWD1
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST));
+}
+
+/**
+ * @brief Get flag multimode analog watchdog 1 of the ADC slave.
+ * @rmtoll CSR AWD1_SLV LL_ADC_IsActiveFlag_SLV_AWD1
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV));
+}
+
+/**
+ * @brief Get flag multimode ADC analog watchdog 2 of the ADC master.
+ * @rmtoll CSR AWD2_MST LL_ADC_IsActiveFlag_MST_AWD2
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST));
+}
+
+/**
+ * @brief Get flag multimode ADC analog watchdog 2 of the ADC slave.
+ * @rmtoll CSR AWD2_SLV LL_ADC_IsActiveFlag_SLV_AWD2
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV));
+}
+
+/**
+ * @brief Get flag multimode ADC analog watchdog 3 of the ADC master.
+ * @rmtoll CSR AWD3_MST LL_ADC_IsActiveFlag_MST_AWD3
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST));
+}
+
+/**
+ * @brief Get flag multimode ADC analog watchdog 3 of the ADC slave.
+ * @rmtoll CSR AWD3_SLV LL_ADC_IsActiveFlag_SLV_AWD3
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV));
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_IT_Management ADC IT management
+ * @{
+ */
+
+/**
+ * @brief Enable ADC ready.
+ * @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
+}
+
+/**
+ * @brief Enable interruption ADC group regular end of unitary conversion.
+ * @rmtoll IER EOCIE LL_ADC_EnableIT_EOC
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
+}
+
+/**
+ * @brief Enable interruption ADC group regular end of sequence conversions.
+ * @rmtoll IER EOSIE LL_ADC_EnableIT_EOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
+}
+
+/**
+ * @brief Enable ADC group regular interruption overrun.
+ * @rmtoll IER OVRIE LL_ADC_EnableIT_OVR
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
+}
+
+/**
+ * @brief Enable interruption ADC group regular end of sampling.
+ * @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
+}
+
+/**
+ * @brief Enable interruption ADC group injected end of unitary conversion.
+ * @rmtoll IER JEOCIE LL_ADC_EnableIT_JEOC
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->IER, LL_ADC_IT_JEOC);
+}
+
+/**
+ * @brief Enable interruption ADC group injected end of sequence conversions.
+ * @rmtoll IER JEOSIE LL_ADC_EnableIT_JEOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->IER, LL_ADC_IT_JEOS);
+}
+
+/**
+ * @brief Enable interruption ADC group injected context queue overflow.
+ * @rmtoll IER JQOVFIE LL_ADC_EnableIT_JQOVF
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
+}
+
+/**
+ * @brief Enable interruption ADC analog watchdog 1.
+ * @rmtoll IER AWD1IE LL_ADC_EnableIT_AWD1
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
+}
+
+/**
+ * @brief Enable interruption ADC analog watchdog 2.
+ * @rmtoll IER AWD2IE LL_ADC_EnableIT_AWD2
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);
+}
+
+/**
+ * @brief Enable interruption ADC analog watchdog 3.
+ * @rmtoll IER AWD3IE LL_ADC_EnableIT_AWD3
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
+}
+
+/**
+ * @brief Disable interruption ADC ready.
+ * @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
+}
+
+/**
+ * @brief Disable interruption ADC group regular end of unitary conversion.
+ * @rmtoll IER EOCIE LL_ADC_DisableIT_EOC
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
+}
+
+/**
+ * @brief Disable interruption ADC group regular end of sequence conversions.
+ * @rmtoll IER EOSIE LL_ADC_DisableIT_EOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
+}
+
+/**
+ * @brief Disable interruption ADC group regular overrun.
+ * @rmtoll IER OVRIE LL_ADC_DisableIT_OVR
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
+}
+
+/**
+ * @brief Disable interruption ADC group regular end of sampling.
+ * @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
+}
+
+/**
+ * @brief Disable interruption ADC group regular end of unitary conversion.
+ * @rmtoll IER JEOCIE LL_ADC_DisableIT_JEOC
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC);
+}
+
+/**
+ * @brief Disable interruption ADC group injected end of sequence conversions.
+ * @rmtoll IER JEOSIE LL_ADC_DisableIT_JEOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS);
+}
+
+/**
+ * @brief Disable interruption ADC group injected context queue overflow.
+ * @rmtoll IER JQOVFIE LL_ADC_DisableIT_JQOVF
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
+}
+
+/**
+ * @brief Disable interruption ADC analog watchdog 1.
+ * @rmtoll IER AWD1IE LL_ADC_DisableIT_AWD1
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
+}
+
+/**
+ * @brief Disable interruption ADC analog watchdog 2.
+ * @rmtoll IER AWD2IE LL_ADC_DisableIT_AWD2
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);
+}
+
+/**
+ * @brief Disable interruption ADC analog watchdog 3.
+ * @rmtoll IER AWD3IE LL_ADC_DisableIT_AWD3
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
+}
+
+/**
+ * @brief Get state of interruption ADC ready
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY));
+}
+
+/**
+ * @brief Get state of interruption ADC group regular end of unitary conversion
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC));
+}
+
+/**
+ * @brief Get state of interruption ADC group regular end of sequence conversions
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER EOSIE LL_ADC_IsEnabledIT_EOS
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS));
+}
+
+/**
+ * @brief Get state of interruption ADC group regular overrun
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR));
+}
+
+/**
+ * @brief Get state of interruption ADC group regular end of sampling
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP));
+}
+
+/**
+ * @brief Get state of interruption ADC group injected end of unitary conversion
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER JEOCIE LL_ADC_IsEnabledIT_JEOC
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC));
+}
+
+/**
+ * @brief Get state of interruption ADC group injected end of sequence conversions
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER JEOSIE LL_ADC_IsEnabledIT_JEOS
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS));
+}
+
+/**
+ * @brief Get state of interruption ADC group injected context queue overflow interrupt state
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER JQOVFIE LL_ADC_IsEnabledIT_JQOVF
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF));
+}
+
+/**
+ * @brief Get state of interruption ADC analog watchdog 1
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER AWD1IE LL_ADC_IsEnabledIT_AWD1
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1));
+}
+
+/**
+ * @brief Get state of interruption Get ADC analog watchdog 2
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER AWD2IE LL_ADC_IsEnabledIT_AWD2
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2));
+}
+
+/**
+ * @brief Get state of interruption Get ADC analog watchdog 3
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER AWD3IE LL_ADC_IsEnabledIT_AWD3
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3));
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization of some features of ADC common parameters and multimode */
+ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
+ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
+void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
+
+/* De-initialization of ADC instance, ADC group regular and ADC group injected */
+/* (availability of ADC group injected depends on STM32 families) */
+ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
+
+/* Initialization of some features of ADC instance */
+ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
+void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
+
+/* Initialization of some features of ADC instance and ADC group regular */
+ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
+void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
+
+/* Initialization of some features of ADC instance and ADC group injected */
+ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
+void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* ADC1 || ADC2 || ADC3 || ADC4 */
+
+
+#endif /* STM32F301x8 || STM32F302x8 || STM32F302xC || STM32F302xE || STM32F303x8 || STM32F303xC || STM32F303xE || STM32F318xx || STM32F328xx || STM32F334x8 || STM32F358xx || STM32F398xx */
+
+#if defined (ADC1_V2_5)
+
+#if defined (ADC1)
+
+/** @defgroup ADC_LL ADC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup ADC_LL_Private_Constants ADC Private Constants
+ * @{
+ */
+
+/* Internal mask for ADC group regular sequencer: */
+/* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
+/* - sequencer register offset */
+/* - sequencer rank bits position into the selected register */
+
+/* Internal register offset for ADC group regular sequencer configuration */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_SQR1_REGOFFSET ((uint32_t)0x00000000U)
+#define ADC_SQR2_REGOFFSET ((uint32_t)0x00000100U)
+#define ADC_SQR3_REGOFFSET ((uint32_t)0x00000200U)
+#define ADC_SQR4_REGOFFSET ((uint32_t)0x00000300U)
+
+#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
+#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
+
+/* Definition of ADC group regular sequencer bits information to be inserted */
+/* into ADC group regular sequencer ranks literals definition. */
+#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1) */
+#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2) */
+#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3) */
+#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4) */
+#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5) */
+#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS ((uint32_t)25U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6) */
+#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */
+#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */
+#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */
+#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10) */
+#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11) */
+#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS ((uint32_t)25U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12) */
+#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13) */
+#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14) */
+#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */
+#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */
+
+
+
+/* Internal mask for ADC group injected sequencer: */
+/* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
+/* - data register offset */
+/* - offset register offset */
+/* - sequencer rank bits position into the selected register */
+
+/* Internal register offset for ADC group injected data register */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_JDR1_REGOFFSET ((uint32_t)0x00000000U)
+#define ADC_JDR2_REGOFFSET ((uint32_t)0x00000100U)
+#define ADC_JDR3_REGOFFSET ((uint32_t)0x00000200U)
+#define ADC_JDR4_REGOFFSET ((uint32_t)0x00000300U)
+
+/* Internal register offset for ADC group injected offset configuration */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_JOFR1_REGOFFSET ((uint32_t)0x00000000U)
+#define ADC_JOFR2_REGOFFSET ((uint32_t)0x00001000U)
+#define ADC_JOFR3_REGOFFSET ((uint32_t)0x00002000U)
+#define ADC_JOFR4_REGOFFSET ((uint32_t)0x00003000U)
+
+#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
+#define ADC_INJ_JOFRX_REGOFFSET_MASK (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET)
+#define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
+
+/* Definition of ADC group injected sequencer bits information to be inserted */
+/* into ADC group injected sequencer ranks literals definition. */
+#define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ1) */
+#define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ2) */
+#define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ3) */
+#define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ4) */
+
+
+
+/* Internal mask for ADC channel: */
+/* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
+/* - channel identifier defined by number */
+/* - channel differentiation between external channels (connected to */
+/* GPIO pins) and internal channels (connected to internal paths) */
+/* - channel sampling time defined by SMPRx register offset */
+/* and SMPx bits positions into SMPRx register */
+#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CR1_AWDCH)
+#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ((uint32_t) 0U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
+#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
+/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
+#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 ((uint32_t)0x0000001FU) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
+
+/* Channel differentiation between external and internal channels */
+#define ADC_CHANNEL_ID_INTERNAL_CH ((uint32_t)0x80000000U) /* Marker of internal channel */
+#define ADC_CHANNEL_ID_INTERNAL_CH_2 ((uint32_t)0x40000000U) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
+#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
+
+/* Internal register offset for ADC channel sampling time configuration */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_SMPR1_REGOFFSET ((uint32_t)0x00000000U)
+#define ADC_SMPR2_REGOFFSET ((uint32_t)0x02000000U)
+#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
+
+#define ADC_CHANNEL_SMPx_BITOFFSET_MASK ((uint32_t)0x01F00000U)
+#define ADC_CHANNEL_SMPx_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
+
+/* Definition of channels ID number information to be inserted into */
+/* channels literals definition. */
+#define ADC_CHANNEL_0_NUMBER ((uint32_t)0x00000000U)
+#define ADC_CHANNEL_1_NUMBER ( ADC_CR1_AWDCH_0)
+#define ADC_CHANNEL_2_NUMBER ( ADC_CR1_AWDCH_1 )
+#define ADC_CHANNEL_3_NUMBER ( ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
+#define ADC_CHANNEL_4_NUMBER ( ADC_CR1_AWDCH_2 )
+#define ADC_CHANNEL_5_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)
+#define ADC_CHANNEL_6_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )
+#define ADC_CHANNEL_7_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
+#define ADC_CHANNEL_8_NUMBER ( ADC_CR1_AWDCH_3 )
+#define ADC_CHANNEL_9_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0)
+#define ADC_CHANNEL_10_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 )
+#define ADC_CHANNEL_11_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
+#define ADC_CHANNEL_12_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 )
+#define ADC_CHANNEL_13_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)
+#define ADC_CHANNEL_14_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )
+#define ADC_CHANNEL_15_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
+#define ADC_CHANNEL_16_NUMBER (ADC_CR1_AWDCH_4 )
+#define ADC_CHANNEL_17_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0)
+
+/* Definition of channels sampling time information to be inserted into */
+/* channels literals definition. */
+#define ADC_CHANNEL_0_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP0) */
+#define ADC_CHANNEL_1_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP1) */
+#define ADC_CHANNEL_2_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP2) */
+#define ADC_CHANNEL_3_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP3) */
+#define ADC_CHANNEL_4_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP4) */
+#define ADC_CHANNEL_5_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP5) */
+#define ADC_CHANNEL_6_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP6) */
+#define ADC_CHANNEL_7_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP7) */
+#define ADC_CHANNEL_8_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP8) */
+#define ADC_CHANNEL_9_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP9) */
+#define ADC_CHANNEL_10_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP10) */
+#define ADC_CHANNEL_11_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP11) */
+#define ADC_CHANNEL_12_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP12) */
+#define ADC_CHANNEL_13_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP13) */
+#define ADC_CHANNEL_14_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP14) */
+#define ADC_CHANNEL_15_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP15) */
+#define ADC_CHANNEL_16_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP16) */
+#define ADC_CHANNEL_17_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */
+
+
+/* Internal mask for ADC analog watchdog: */
+/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
+/* (concatenation of multiple bits used in different analog watchdogs, */
+/* (feature of several watchdogs not available on all STM32 families)). */
+/* - analog watchdog 1: monitored channel defined by number, */
+/* selection of ADC group (ADC groups regular and-or injected). */
+
+/* Internal register offset for ADC analog watchdog channel configuration */
+#define ADC_AWD_CR1_REGOFFSET ((uint32_t)0x00000000U)
+
+#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET)
+
+#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CR1_AWDCH | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
+#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK)
+
+/* Internal register offset for ADC analog watchdog threshold configuration */
+#define ADC_AWD_TR1_HIGH_REGOFFSET ((uint32_t)0x00000000U)
+#define ADC_AWD_TR1_LOW_REGOFFSET ((uint32_t)0x00000001U)
+#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET)
+
+
+/* ADC registers bits positions */
+#define ADC_CR1_DUALMOD_BITOFFSET_POS ((uint32_t)16U) /* Value equivalent to POSITION_VAL(ADC_CR1_DUALMOD) */
+
+
+/* ADC internal channels related definitions */
+/* Internal voltage reference VrefInt */
+#define VREFINT_CAL_ADDR ((uint16_t*) ((uint32_t)0x1FFFF7BAU)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
+#define VREFINT_CAL_VREF ((uint32_t) 3300U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
+/* Temperature sensor */
+#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) ((uint32_t)0x1FFFF7B8U)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32F37x, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
+#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) ((uint32_t)0x1FFFF7C2U)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32F37x, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
+#define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
+#define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
+#define TEMPSENSOR_CAL_VREFANALOG ((uint32_t) 3300U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
+
+
+/**
+ * @}
+ */
+
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup ADC_LL_Private_Macros ADC Private Macros
+ * @{
+ */
+
+/**
+ * @brief Driver macro reserved for internal use: isolate bits with the
+ * selected mask and shift them to the register LSB
+ * (shift mask on register position bit 0).
+ * @param __BITS__ Bits in register 32 bits
+ * @param __MASK__ Mask in register 32 bits
+ * @retval Bits in register 32 bits
+ */
+#define __ADC_MASK_SHIFT(__BITS__, __MASK__) \
+ (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
+
+/**
+ * @brief Driver macro reserved for internal use: set a pointer to
+ * a register from a register basis from which an offset
+ * is applied.
+ * @param __REG__ Register basis from which the offset is applied.
+ * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
+ * @retval Pointer to register address
+ */
+#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
+ ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
+
+/**
+ * @}
+ */
+
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief Structure definition of some features of ADC instance.
+ * @note These parameters have an impact on ADC scope: ADC instance.
+ * Affects both group regular and group injected (availability
+ * of ADC group injected depends on STM32 families).
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Instance .
+ * @note The setting of these parameters by function @ref LL_ADC_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 families. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ */
+typedef struct
+{
+ uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
+ This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
+
+ uint32_t SequencersScanMode; /*!< Set ADC scan selection.
+ This parameter can be a value of @ref ADC_LL_EC_SCAN_SELECTION
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_SetSequencersScanMode(). */
+
+} LL_ADC_InitTypeDef;
+
+/**
+ * @brief Structure definition of some features of ADC group regular.
+ * @note These parameters have an impact on ADC scope: ADC group regular.
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+ * (functions with prefix "REG").
+ * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 families. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ */
+typedef struct
+{
+ uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or external from timer or external interrupt.
+ This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
+ @note On this STM32 serie, external trigger is set with trigger polarity: rising edge
+ (only trigger polarity available on this STM32 serie).
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
+
+ uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
+ This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
+ @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
+
+ uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
+ This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
+ @note This parameter has an effect only if group regular sequencer is enabled
+ (scan length of 2 ranks or more).
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
+
+ uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
+ This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
+ Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
+
+ uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
+ This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
+
+} LL_ADC_REG_InitTypeDef;
+
+/**
+ * @brief Structure definition of some features of ADC group injected.
+ * @note These parameters have an impact on ADC scope: ADC group injected.
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+ * (functions with prefix "INJ").
+ * @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 families. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ */
+typedef struct
+{
+ uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or external from timer or external interrupt.
+ This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
+ @note On this STM32 serie, external trigger is set with trigger polarity: rising edge
+ (only trigger polarity available on this STM32 serie).
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
+
+ uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
+ This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
+ @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */
+
+ uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
+ This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
+ @note This parameter has an effect only if group injected sequencer is enabled
+ (scan length of 2 ranks or more).
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */
+
+ uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
+ This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
+ Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
+
+} LL_ADC_INJ_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
+ * @{
+ */
+
+/** @defgroup ADC_LL_EC_FLAG ADC flags
+ * @brief Flags defines which can be used with LL_ADC_ReadReg function
+ * @{
+ */
+#define LL_ADC_FLAG_STRT ADC_SR_STRT /*!< ADC flag ADC group regular conversion start */
+#define LL_ADC_FLAG_EOS ADC_SR_EOC /*!< ADC flag ADC group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) */
+#define LL_ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC flag ADC group injected conversion start */
+#define LL_ADC_FLAG_JEOS ADC_SR_JEOC /*!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
+#define LL_ADC_FLAG_AWD1 ADC_SR_AWD /*!< ADC flag ADC analog watchdog 1 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
+ * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
+ * @{
+ */
+#define LL_ADC_IT_EOS ADC_CR1_EOCIE /*!< ADC interruption ADC group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) */
+#define LL_ADC_IT_JEOS ADC_CR1_JEOCIE /*!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
+#define LL_ADC_IT_AWD1 ADC_CR1_AWDIE /*!< ADC interruption ADC analog watchdog 1 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
+ * @{
+ */
+/* List of ADC registers intended to be used (most commonly) with */
+/* DMA transfer. */
+/* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
+#define LL_ADC_DMA_REG_REGULAR_DATA ((uint32_t)0x00000000U) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
+ * @{
+ */
+/* Note: Other measurement paths to internal channels may be available */
+/* (connections to other peripherals). */
+/* If they are not listed below, they do not require any specific */
+/* path enable. In this case, Access to measurement path is done */
+/* only by selecting the corresponding ADC internal channel. */
+#define LL_ADC_PATH_INTERNAL_NONE ((uint32_t)0x00000000U)/*!< ADC measurement pathes all disabled */
+#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CR2_TSVREFE) /*!< ADC measurement path to internal channel VrefInt */
+#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CR2_TSVREFE) /*!< ADC measurement path to internal channel temperature sensor */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
+ * @{
+ */
+#define LL_ADC_RESOLUTION_12B ((uint32_t)0x00000000U) /*!< ADC resolution 12 bits */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
+ * @{
+ */
+#define LL_ADC_DATA_ALIGN_RIGHT ((uint32_t)0x00000000U)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
+#define LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_SCAN_SELECTION ADC instance - Scan selection
+ * @{
+ */
+#define LL_ADC_SEQ_SCAN_DISABLE ((uint32_t)0x00000000U) /*!< ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of both groups regular and injected sequencers (sequence length, ...) is discarded: equivalent to length of 1 rank.*/
+#define LL_ADC_SEQ_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN) /*!< ADC conversions are performed in sequence conversions mode, according to configuration of both groups regular and injected sequencers (sequence length, ...). */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
+ * @{
+ */
+#define LL_ADC_GROUP_REGULAR ((uint32_t)0x00000001U) /*!< ADC group regular (available on all STM32 devices) */
+#define LL_ADC_GROUP_INJECTED ((uint32_t)0x00000002U) /*!< ADC group injected (not available on all STM32 devices)*/
+#define LL_ADC_GROUP_REGULAR_INJECTED ((uint32_t)0x00000003U) /*!< ADC both groups regular and injected */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
+ * @{
+ */
+#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
+#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
+#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
+#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
+#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
+#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
+#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
+#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
+#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
+#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
+#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
+#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
+#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
+#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
+#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
+#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
+#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
+#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
+#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32F37x, ADC channel available only on ADC instance: ADC1. */
+#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
+ * @{
+ */
+#define LL_ADC_REG_TRIG_SOFTWARE (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger internal (SW start) */
+#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger external from TIM2 CC2. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CR2_EXTSEL_2) /*!< ADC group regular conversion trigger external from TIM3 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM4_CH2 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger external from TIM4 CC4. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM19_TRGO ((uint32_t)0x00000000U) /*!< ADC group regular conversion trigger external from TIM19 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM19_CH3 (ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger external from TIM19 CC3. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM19_CH4 (ADC_CR2_EXTSEL_1) /*!< ADC group regular conversion trigger external from TIM19 CC4. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1) /*!< ADC group regular conversion trigger external interrupt line 11. Trigger edge set to rising edge (default setting). */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
+ * @{
+ */
+#define LL_ADC_REG_TRIG_EXT_RISING ((uint32_t)0x00000000U) /*!< ADC group regular conversion trigger polarity set to rising edge */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
+* @{
+*/
+#define LL_ADC_REG_CONV_SINGLE ((uint32_t)0x00000000U)/*!< ADC conversions are performed in single mode: one conversion per trigger */
+#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CR2_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer
+ * @{
+ */
+#define LL_ADC_REG_DMA_TRANSFER_NONE ((uint32_t)0x00000000U) /*!< ADC conversions are not transferred by DMA */
+#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CR2_DMA) /*!< ADC conversions are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
+ * @{
+ */
+#define LL_ADC_REG_SEQ_SCAN_DISABLE ((uint32_t)0x00000000U) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
+ * @{
+ */
+#define LL_ADC_REG_SEQ_DISCONT_DISABLE ((uint32_t)0x00000000U) /*!< ADC group regular sequencer discontinuous mode disable */
+#define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
+#define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_RANKS ADC group regular - Sequencer ranks
+ * @{
+ */
+#define LL_ADC_REG_RANK_1 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */
+#define LL_ADC_REG_RANK_2 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */
+#define LL_ADC_REG_RANK_3 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */
+#define LL_ADC_REG_RANK_4 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */
+#define LL_ADC_REG_RANK_5 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */
+#define LL_ADC_REG_RANK_6 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */
+#define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */
+#define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */
+#define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */
+#define LL_ADC_REG_RANK_10 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */
+#define LL_ADC_REG_RANK_11 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */
+#define LL_ADC_REG_RANK_12 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */
+#define LL_ADC_REG_RANK_13 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */
+#define LL_ADC_REG_RANK_14 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
+#define LL_ADC_REG_RANK_15 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
+#define LL_ADC_REG_RANK_16 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
+ * @{
+ */
+#define LL_ADC_INJ_TRIG_SOFTWARE (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger internal (SW start) */
+#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_CR2_JEXTSEL_1) /*!< ADC group injected conversion trigger external from TIM2 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger external from TIM2 CC1. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_CR2_JEXTSEL_2) /*!< ADC group injected conversion trigger external from TIM3 CC4. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger external from TIM4 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM19_CH1 ((uint32_t)0x00000000U) /*!< ADC group injected conversion trigger external from TIM19 CC1. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM19_CH2 (ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger external from TIM19 CC2. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1) /*!< ADC group injected conversion trigger external interrupt line 15. Trigger edge set to rising edge (default setting). */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
+ * @{
+ */
+#define LL_ADC_INJ_TRIG_EXT_RISING ((uint32_t)0x00000000U) /*!< ADC group injected conversion trigger polarity set to rising edge */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
+* @{
+*/
+#define LL_ADC_INJ_TRIG_INDEPENDENT ((uint32_t)0x00000000U)/*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
+#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CR1_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
+/**
+ * @}
+ */
+
+
+/** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
+ * @{
+ */
+#define LL_ADC_INJ_SEQ_SCAN_DISABLE ((uint32_t)0x00000000U) /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
+#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
+#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
+#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
+ * @{
+ */
+#define LL_ADC_INJ_SEQ_DISCONT_DISABLE ((uint32_t)0x00000000U)/*!< ADC group injected sequencer discontinuous mode disable */
+#define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CR1_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_RANKS ADC group injected - Sequencer ranks
+ * @{
+ */
+#define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 */
+#define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 2 */
+#define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 3 */
+#define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 4 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_SAMPLINGTIME Channel - Sampling time
+ * @{
+ */
+#define LL_ADC_SAMPLINGTIME_1CYCLE_5 ((uint32_t)0x00000000U) /*!< Sampling time 1.5 ADC clock cycle */
+#define LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR2_SMP0_0) /*!< Sampling time 7.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_13CYCLES_5 (ADC_SMPR2_SMP0_1) /*!< Sampling time 13.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_28CYCLES_5 (ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0) /*!< Sampling time 28.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_41CYCLES_5 (ADC_SMPR2_SMP0_2) /*!< Sampling time 41.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_55CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0) /*!< Sampling time 55.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_71CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1) /*!< Sampling time 71.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_239CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0) /*!< Sampling time 239.5 ADC clock cycles */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
+ * @{
+ */
+#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
+ * @{
+ */
+#define LL_ADC_AWD_DISABLE ((uint32_t)0x00000000U) /*!< ADC analog watchdog monitoring disabled */
+#define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
+#define LL_ADC_AWD_ALL_CHANNELS_INJ ( ADC_CR1_JAWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
+#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ ( ADC_CR1_JAWDEN | ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
+#define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
+#define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
+#define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */
+#define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
+ * @{
+ */
+#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD_TR1_HIGH_REGOFFSET) /*!< ADC analog watchdog threshold high */
+#define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD_TR1_LOW_REGOFFSET) /*!< ADC analog watchdog threshold low */
+/**
+ * @}
+ */
+
+
+/** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
+ * @note Only ADC IP HW delays are defined in ADC LL driver driver,
+ * not timeout values.
+ * For details on delays values, refer to descriptions in source code
+ * above each literal definition.
+ * @{
+ */
+
+/* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
+/* not timeout values. */
+/* Timeout values for ADC operations are dependent to device clock */
+/* configuration (system clock versus ADC clock), */
+/* and therefore must be defined in user application. */
+/* Indications for estimation of ADC timeout delays, for this */
+/* STM32 serie: */
+/* - ADC enable time: maximum delay is 1us */
+/* (refer to device datasheet, parameter "tSTAB") */
+/* - ADC conversion time: duration depending on ADC clock and ADC */
+/* configuration. */
+/* (refer to device reference manual, section "Timing") */
+
+/* Delay for temperature sensor stabilization time. */
+/* Literal set to maximum value (refer to device datasheet, */
+/* parameter "tSTART"). */
+/* Unit: us */
+#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ((uint32_t) 10U) /*!< Delay for internal voltage reference stabilization time */
+
+/* Delay required between ADC disable and ADC calibration start. */
+/* Note: On this STM32 serie, before starting a calibration, */
+/* ADC must be disabled. */
+/* A minimum number of ADC clock cycles are required */
+/* between ADC disable state and calibration start. */
+/* Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES. */
+/* Wait time can be computed in user application by waiting for the */
+/* equivalent number of CPU cycles, by taking into account */
+/* ratio of CPU clock versus ADC clock prescalers. */
+/* Unit: ADC clock cycles. */
+#define LL_ADC_DELAY_DISABLE_CALIB_ADC_CYCLES ((uint32_t) 2U) /*!< Delay required between ADC disable and ADC calibration start */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
+ * @{
+ */
+
+/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in ADC register
+ * @param __INSTANCE__ ADC Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in ADC register
+ * @param __INSTANCE__ ADC Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
+ * @{
+ */
+
+/**
+ * @brief Helper macro to get ADC channel number in decimal format
+ * from literals LL_ADC_CHANNEL_x.
+ * @note Example:
+ * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
+ * will return decimal number "4".
+ * @note The input can be a value from functions where a channel
+ * number is returned, either defined with number
+ * or with bitfield (only one bit must be set).
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ *
+ * (1) On STM32F37x, parameter available only on ADC instance: ADC1.
+ * @retval Value between Min_Data=0 and Max_Data=18
+ */
+#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
+ (((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
+
+/**
+ * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
+ * from number in decimal format.
+ * @note Example:
+ * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
+ * will return a data equivalent to "LL_ADC_CHANNEL_4".
+ * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ *
+ * (1) On STM32F37x, parameter available only on ADC instance: ADC1.\n
+ * (1) For ADC channel read back from ADC register,
+ * comparison with internal channel parameter to be done
+ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+ */
+#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
+ (((__DECIMAL_NB__) <= 9U) \
+ ? ( \
+ ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
+ (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
+ ) \
+ : \
+ ( \
+ ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
+ (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
+ ) \
+ )
+
+/**
+ * @brief Helper macro to determine whether the selected channel
+ * corresponds to literal definitions of driver.
+ * @note The different literal definitions of ADC channels are:
+ * - ADC internal channel:
+ * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
+ * - ADC external channel (channel connected to a GPIO pin):
+ * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
+ * @note The channel parameter must be a value defined from literal
+ * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+ * LL_ADC_CHANNEL_TEMPSENSOR, ...),
+ * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
+ * must not be a value from functions where a channel number is
+ * returned from ADC registers,
+ * because internal and external channels share the same channel
+ * number in ADC registers. The differentiation is made only with
+ * parameters definitions of driver.
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ *
+ * (1) On STM32F37x, parameter available only on ADC instance: ADC1.
+ * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin)
+ * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel
+ */
+#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
+ (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)
+
+/**
+ * @brief Helper macro to convert a channel defined from parameter
+ * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+ * LL_ADC_CHANNEL_TEMPSENSOR, ...),
+ * to its equivalent parameter definition of a ADC external channel
+ * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
+ * @note The channel parameter can be, additionally to a value
+ * defined from parameter definition of a ADC internal channel
+ * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
+ * a value defined from parameter definition of
+ * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
+ * or a value from functions where a channel number is returned
+ * from ADC registers.
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ *
+ * (1) On STM32F37x, parameter available only on ADC instance: ADC1.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ */
+#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
+ ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
+
+/**
+ * @brief Helper macro to determine whether the internal channel
+ * selected is available on the ADC instance selected.
+ * @note The channel parameter must be a value defined from parameter
+ * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+ * LL_ADC_CHANNEL_TEMPSENSOR, ...),
+ * must not be a value defined from parameter definition of
+ * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
+ * or a value from functions where a channel number is
+ * returned from ADC registers,
+ * because internal and external channels share the same channel
+ * number in ADC registers. The differentiation is made only with
+ * parameters definitions of driver.
+ * @param __ADC_INSTANCE__ ADC instance
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ *
+ * (1) On STM32F37x, parameter available only on ADC instance: ADC1.
+ * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
+ * Value "1" if the internal channel selected is available on the ADC instance selected.
+ */
+#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
+ (((__ADC_INSTANCE__) == ADC1) \
+ ? ( \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) \
+ ) \
+ : \
+ (0U) \
+ )
+
+/**
+ * @brief Helper macro to define ADC analog watchdog parameter:
+ * define a single channel to monitor with analog watchdog
+ * from sequencer channel and groups definition.
+ * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
+ * Example:
+ * LL_ADC_SetAnalogWDMonitChannels(
+ * ADC1, LL_ADC_AWD1,
+ * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ *
+ * (1) On STM32F37x, parameter available only on ADC instance: ADC1.\n
+ * (1) For ADC channel read back from ADC register,
+ * comparison with internal channel parameter to be done
+ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+ * @param __GROUP__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_GROUP_REGULAR
+ * @arg @ref LL_ADC_GROUP_INJECTED
+ * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_AWD_DISABLE
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1)
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
+ *
+ * (1) On STM32F37x, parameter available only on ADC instance: ADC1.
+ */
+#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
+ (((__GROUP__) == LL_ADC_GROUP_REGULAR) \
+ ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \
+ : \
+ ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
+ ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) \
+ : \
+ (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \
+ )
+
+/**
+ * @brief Helper macro to set the value of ADC analog watchdog threshold high
+ * or low in function of ADC resolution, when ADC resolution is
+ * different of 12 bits.
+ * @note To be used with function @ref LL_ADC_SetAnalogWDThresholds().
+ * Example, with a ADC resolution of 8 bits, to set the value of
+ * analog watchdog threshold high (on 8 bits):
+ * LL_ADC_SetAnalogWDThresholds
+ * (< ADCx param >,
+ * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
+ * );
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+/* Note: On this STM32 serie, ADC is fixed to resolution 12 bits. */
+/* This macro has been kept anyway for compatibility with other */
+/* STM32 families featuring different ADC resolutions. */
+#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
+ ((__AWD_THRESHOLD__) << (0U))
+
+/**
+ * @brief Helper macro to get the value of ADC analog watchdog threshold high
+ * or low in function of ADC resolution, when ADC resolution is
+ * different of 12 bits.
+ * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
+ * Example, with a ADC resolution of 8 bits, to get the value of
+ * analog watchdog threshold high (on 8 bits):
+ * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
+ * (LL_ADC_RESOLUTION_8B,
+ * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
+ * );
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+/* Note: On this STM32 serie, ADC is fixed to resolution 12 bits. */
+/* This macro has been kept anyway for compatibility with other */
+/* STM32 families featuring different ADC resolutions. */
+#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
+ (__AWD_THRESHOLD_12_BITS__)
+
+/**
+ * @brief Helper macro to select the ADC common instance
+ * to which is belonging the selected ADC instance.
+ * @note ADC common register instance can be used for:
+ * - Set parameters common to several ADC instances
+ * - Multimode (for devices with several ADC instances)
+ * Refer to functions having argument "ADCxy_COMMON" as parameter.
+ * @note On STM32F37x, there is no common ADC instance.
+ * However, ADC instance ADC1 has a role of common ADC instance
+ * (equivalence with other STM32 families featuring several
+ * ADC instances).
+ * @param __ADCx__ ADC instance
+ * @retval ADC common register instance
+ */
+#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
+ (ADC1_COMMON)
+
+/**
+ * @brief Helper macro to check if all ADC instances sharing the same
+ * ADC common instance are disabled.
+ * @note This check is required by functions with setting conditioned to
+ * ADC state:
+ * All ADC instances of the ADC common group must be disabled.
+ * Refer to functions having argument "ADCxy_COMMON" as parameter.
+ * @note On devices with only 1 ADC common instance, parameter of this macro
+ * is useless and can be ignored (parameter kept for compatibility
+ * with devices featuring several ADC common instances).
+ * @note On STM32F37x, there is no common ADC instance.
+ * However, ADC instance ADC1 has a role of common ADC instance
+ * (equivalence with other STM32 families featuring several
+ * ADC instances).
+ * @param __ADCXY_COMMON__ ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval Value "0" All ADC instances sharing the same ADC common instance
+ * are disabled.
+ * Value "1" At least one ADC instance sharing the same ADC common instance
+ * is enabled
+ */
+#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
+ LL_ADC_IsEnabled(ADC1)
+
+/**
+ * @brief Helper macro to define the ADC conversion data full-scale digital
+ * value corresponding to the selected ADC resolution.
+ * @note ADC conversion data full-scale corresponds to voltage range
+ * determined by analog voltage references Vref+ and Vref-
+ * (refer to reference manual).
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+ */
+#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
+ ((uint32_t)0xFFFU)
+
+/**
+ * @brief Helper macro to convert the ADC conversion data from
+ * a resolution to another resolution.
+ * @note On STM32F37x, the only ADC resolution available is 12 bits.
+ * This macro has been kept for compatibility purpose over other
+ * STM32 families.
+ * @param __DATA__ ADC conversion data to be converted
+ * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
+ * This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
+ * This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @retval ADC conversion data to the requested resolution
+ */
+#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
+ __ADC_RESOLUTION_CURRENT__,\
+ __ADC_RESOLUTION_TARGET__) \
+ (((__DATA__) \
+ << ((__ADC_RESOLUTION_CURRENT__) >> (0U))) \
+ >> ((__ADC_RESOLUTION_TARGET__) >> (0U)) \
+ )
+
+/**
+ * @brief Helper macro to calculate the voltage (unit: mVolt)
+ * corresponding to a ADC conversion data (unit: digital value).
+ * @note Analog reference voltage (Vref+) must be either known from
+ * user board environment or can be calculated using ADC measurement
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+ * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
+ * (unit: digital value).
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+ */
+#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
+ __ADC_DATA__,\
+ __ADC_RESOLUTION__) \
+ ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
+ / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
+ )
+
+
+/**
+ * @brief Helper macro to calculate analog reference voltage (Vref+)
+ * (unit: mVolt) from ADC conversion data of internal voltage
+ * reference VrefInt.
+ * @note Computation is using VrefInt calibration value
+ * stored in system memory for each device during production.
+ * @note This voltage depends on user board environment: voltage level
+ * connected to pin Vref+.
+ * On devices with small package, the pin Vref+ is not present
+ * and internally bonded to pin Vdda.
+ * @note On this STM32 serie, calibration data of internal voltage reference
+ * VrefInt corresponds to a resolution of 12 bits,
+ * this is the recommended ADC resolution to convert voltage of
+ * internal voltage reference VrefInt.
+ * On STM32F37x, the only ADC resolution available is 12 bits.
+ * The parameter of ADC resolution is kept for compatibility purpose
+ * over other STM32 families.
+ * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
+ * of internal voltage reference VrefInt (unit: digital value).
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @retval Analog reference voltage (unit: mV)
+ */
+#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
+ __ADC_RESOLUTION__) \
+ (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
+ / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
+ (__ADC_RESOLUTION__), \
+ LL_ADC_RESOLUTION_12B) \
+ )
+
+/**
+ * @brief Helper macro to calculate the temperature (unit: degree Celsius)
+ * from ADC conversion data of internal temperature sensor.
+ * @note Computation is using temperature sensor calibration values
+ * stored in system memory for each device during production.
+ * @note Calculation formula:
+ * Temperature = ((TS_ADC_DATA - TS_CAL1)
+ * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
+ * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
+ * with TS_ADC_DATA = temperature sensor raw data measured by ADC
+ * Avg_Slope = (TS_CAL2 - TS_CAL1)
+ * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
+ * TS_CAL1 = equivalent TS_ADC_DATA at temperature
+ * TEMP_DEGC_CAL1 (calibrated in factory)
+ * TS_CAL2 = equivalent TS_ADC_DATA at temperature
+ * TEMP_DEGC_CAL2 (calibrated in factory)
+ * Caution: Calculation relevancy under reserve that calibration
+ * parameters are correct (address and data).
+ * To calculate temperature using temperature sensor
+ * datasheet typical values (generic values less, therefore
+ * less accurate than calibrated values),
+ * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
+ * @note As calculation input, the analog reference voltage (Vref+) must be
+ * defined as it impacts the ADC LSB equivalent voltage.
+ * @note Analog reference voltage (Vref+) must be either known from
+ * user board environment or can be calculated using ADC measurement
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * @note On this STM32 serie, calibration data of temperature sensor
+ * corresponds to a resolution of 12 bits,
+ * this is the recommended ADC resolution to convert voltage of
+ * temperature sensor.
+ * On STM32F37x, the only ADC resolution available is 12 bits.
+ * The parameter of ADC resolution is kept for compatibility purpose
+ * over other STM32 families.
+ * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+ * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
+ * temperature sensor (unit: digital value).
+ * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
+ * sensor voltage has been measured.
+ * This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @retval Temperature (unit: degree Celsius)
+ */
+#define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
+ __TEMPSENSOR_ADC_DATA__,\
+ __ADC_RESOLUTION__) \
+ (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
+ (__ADC_RESOLUTION__), \
+ LL_ADC_RESOLUTION_12B) \
+ * (__VREFANALOG_VOLTAGE__)) \
+ / TEMPSENSOR_CAL_VREFANALOG) \
+ - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
+ ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
+ ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
+ ) + TEMPSENSOR_CAL1_TEMP \
+ )
+
+/**
+ * @brief Helper macro to calculate the temperature (unit: degree Celsius)
+ * from ADC conversion data of internal temperature sensor.
+ * @note Computation is using temperature sensor typical values
+ * (refer to device datasheet).
+ * @note Calculation formula:
+ * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
+ * / Avg_Slope + CALx_TEMP
+ * with TS_ADC_DATA = temperature sensor raw data measured by ADC
+ * (unit: digital value)
+ * Avg_Slope = temperature sensor slope
+ * (unit: uV/Degree Celsius)
+ * TS_TYP_CALx_VOLT = temperature sensor digital value at
+ * temperature CALx_TEMP (unit: mV)
+ * Caution: Calculation relevancy under reserve the temperature sensor
+ * of the current device has characteristics in line with
+ * datasheet typical values.
+ * If temperature sensor calibration values are available on
+ * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
+ * temperature calculation will be more accurate using
+ * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
+ * @note As calculation input, the analog reference voltage (Vref+) must be
+ * defined as it impacts the ADC LSB equivalent voltage.
+ * @note Analog reference voltage (Vref+) must be either known from
+ * user board environment or can be calculated using ADC measurement
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * @note ADC measurement data must correspond to a resolution of 12bits
+ * (full scale digital value 4095). If not the case, the data must be
+ * preliminarily rescaled to an equivalent resolution of 12 bits.
+ * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
+ * On STM32F37x, refer to device datasheet parameter "Avg_Slope".
+ * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
+ * On STM32F37x, refer to device datasheet parameter "V25".
+ * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
+ * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
+ * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
+ * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
+ * This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @retval Temperature (unit: degree Celsius)
+ */
+#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
+ __TEMPSENSOR_TYP_CALX_V__,\
+ __TEMPSENSOR_CALX_TEMP__,\
+ __VREFANALOG_VOLTAGE__,\
+ __TEMPSENSOR_ADC_DATA__,\
+ __ADC_RESOLUTION__) \
+ ((( ( \
+ (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
+ * 1000) \
+ - \
+ (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
+ / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
+ * 1000) \
+ ) \
+ ) / (__TEMPSENSOR_TYP_AVGSLOPE__) \
+ ) + (__TEMPSENSOR_CALX_TEMP__) \
+ )
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
+ * @{
+ */
+
+/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
+ * @{
+ */
+/* Note: LL ADC functions to set DMA transfer are located into sections of */
+/* configuration of ADC instance, groups and multimode (if available): */
+/* @ref LL_ADC_REG_SetDMATransfer(), ... */
+
+/**
+ * @brief Function to help to configure DMA transfer from ADC: retrieve the
+ * ADC register address from ADC instance and a list of ADC registers
+ * intended to be used (most commonly) with DMA transfer.
+ * @note These ADC registers are data registers:
+ * when ADC conversion data is available in ADC data registers,
+ * ADC generates a DMA transfer request.
+ * @note This macro is intended to be used with LL DMA driver, refer to
+ * function "LL_DMA_ConfigAddresses()".
+ * Example:
+ * LL_DMA_ConfigAddresses(DMA1,
+ * LL_DMA_CHANNEL_1,
+ * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
+ * (uint32_t)&< array or variable >,
+ * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
+ * @note For devices with several ADC: in multimode, some devices
+ * use a different data register outside of ADC instance scope
+ * (common data register). This macro manages this register difference,
+ * only ADC instance has to be set as parameter.
+ * @rmtoll DR DATA LL_ADC_DMA_GetRegAddr
+ * @param ADCx ADC instance
+ * @param Register This parameter can be one of the following values:
+ * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
+ * @retval ADC register address
+ */
+__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
+{
+ /* Retrieve address of register DR */
+ return (uint32_t)&(ADCx->DR);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
+ * @{
+ */
+
+/**
+ * @brief Set parameter common to several ADC: measurement path to internal
+ * channels (VrefInt, temperature sensor, ...).
+ * @note One or several values can be selected.
+ * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+ * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+ * @note Stabilization time of measurement path to internal channel:
+ * After enabling internal paths, before starting ADC conversion,
+ * a delay is required for internal voltage reference and
+ * temperature sensor stabilization time.
+ * Refer to device datasheet.
+ * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
+ * @note ADC internal channel sampling time constraint:
+ * For ADC conversion of internal channels,
+ * a sampling time minimum value is required.
+ * Refer to device datasheet.
+ * @rmtoll CR2 TSVREFE LL_ADC_SetCommonPathInternalCh
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param PathInternal This parameter can be a combination of the following values:
+ * @arg @ref LL_ADC_PATH_INTERNAL_NONE
+ * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+ * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
+{
+ MODIFY_REG(ADCxy_COMMON->CR2, (ADC_CR2_TSVREFE), PathInternal);
+}
+
+/**
+ * @brief Get parameter common to several ADC: measurement path to internal
+ * channels (VrefInt, temperature sensor, ...).
+ * @note One or several values can be selected.
+ * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+ * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+ * @rmtoll CR2 TSVREFE LL_ADC_GetCommonPathInternalCh
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval Returned value can be a combination of the following values:
+ * @arg @ref LL_ADC_PATH_INTERNAL_NONE
+ * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+ * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (uint32_t)(READ_BIT(ADCxy_COMMON->CR2, ADC_CR2_TSVREFE));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
+ * @{
+ */
+
+/**
+ * @brief Set ADC conversion data alignment.
+ * @note Refer to reference manual for alignments formats
+ * dependencies to ADC resolutions.
+ * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment
+ * @param ADCx ADC instance
+ * @param DataAlignment This parameter can be one of the following values:
+ * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
+ * @arg @ref LL_ADC_DATA_ALIGN_LEFT
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
+{
+ MODIFY_REG(ADCx->CR2, ADC_CR2_ALIGN, DataAlignment);
+}
+
+/**
+ * @brief Get ADC conversion data alignment.
+ * @note Refer to reference manual for alignments formats
+ * dependencies to ADC resolutions.
+ * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
+ * @arg @ref LL_ADC_DATA_ALIGN_LEFT
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_ALIGN));
+}
+
+/**
+ * @brief Set ADC sequencers scan mode, for all ADC groups
+ * (group regular, group injected).
+ * @note According to sequencers scan mode :
+ * - If disabled: ADC conversion is performed in unitary conversion
+ * mode (one channel converted, that defined in rank 1).
+ * Configuration of sequencers of all ADC groups
+ * (sequencer scan length, ...) is discarded: equivalent to
+ * scan length of 1 rank.
+ * - If enabled: ADC conversions are performed in sequence conversions
+ * mode, according to configuration of sequencers of
+ * each ADC group (sequencer scan length, ...).
+ * Refer to function @ref LL_ADC_REG_SetSequencerLength()
+ * and to function @ref LL_ADC_INJ_SetSequencerLength().
+ * @rmtoll CR1 SCAN LL_ADC_SetSequencersScanMode
+ * @param ADCx ADC instance
+ * @param ScanMode This parameter can be one of the following values:
+ * @arg @ref LL_ADC_SEQ_SCAN_DISABLE
+ * @arg @ref LL_ADC_SEQ_SCAN_ENABLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetSequencersScanMode(ADC_TypeDef *ADCx, uint32_t ScanMode)
+{
+ MODIFY_REG(ADCx->CR1, ADC_CR1_SCAN, ScanMode);
+}
+
+/**
+ * @brief Get ADC sequencers scan mode, for all ADC groups
+ * (group regular, group injected).
+ * @note According to sequencers scan mode :
+ * - If disabled: ADC conversion is performed in unitary conversion
+ * mode (one channel converted, that defined in rank 1).
+ * Configuration of sequencers of all ADC groups
+ * (sequencer scan length, ...) is discarded: equivalent to
+ * scan length of 1 rank.
+ * - If enabled: ADC conversions are performed in sequence conversions
+ * mode, according to configuration of sequencers of
+ * each ADC group (sequencer scan length, ...).
+ * Refer to function @ref LL_ADC_REG_SetSequencerLength()
+ * and to function @ref LL_ADC_INJ_SetSequencerLength().
+ * @rmtoll CR1 SCAN LL_ADC_GetSequencersScanMode
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_SEQ_SCAN_DISABLE
+ * @arg @ref LL_ADC_SEQ_SCAN_ENABLE
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_SCAN));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
+ * @{
+ */
+
+/**
+ * @brief Set ADC group regular conversion trigger source:
+ * internal (SW start) or external from timer or external interrupt.
+ * @note On this STM32 serie, external trigger is set with trigger polarity:
+ * rising edge (only trigger polarity available on this STM32 serie).
+ * @note Availability of parameters of trigger sources from timer
+ * depends on timers availability on the selected device.
+ * @rmtoll CR2 EXTSEL LL_ADC_REG_SetTriggerSource
+ * @param ADCx ADC instance
+ * @param TriggerSource This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH2
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM19_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM19_CH3
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM19_CH4
+ * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
+{
+/* Note: On this STM32 serie, ADC group regular external trigger edge */
+/* is used to perform a ADC conversion start. */
+/* This function does not set external trigger edge. */
+/* This feature is set using function */
+/* @ref LL_ADC_REG_StartConversionExtTrig(). */
+ MODIFY_REG(ADCx->CR2, ADC_CR2_EXTSEL, (TriggerSource & ADC_CR2_EXTSEL));
+}
+
+/**
+ * @brief Get ADC group regular conversion trigger source:
+ * internal (SW start) or external from timer or external interrupt.
+ * @note To determine whether group regular trigger source is
+ * internal (SW start) or external, without detail
+ * of which peripheral is selected as external trigger,
+ * (equivalent to
+ * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
+ * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
+ * @note Availability of parameters of trigger sources from timer
+ * depends on timers availability on the selected device.
+ * @rmtoll CR2 EXTSEL LL_ADC_REG_GetTriggerSource
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH2
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM19_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM19_CH3
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM19_CH4
+ * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL));
+}
+
+/**
+ * @brief Get ADC group regular conversion trigger source internal (SW start)
+ or external.
+ * @note In case of group regular trigger source set to external trigger,
+ * to determine which peripheral is selected as external trigger,
+ * use function @ref LL_ADC_REG_GetTriggerSource().
+ * @rmtoll CR2 EXTSEL LL_ADC_REG_IsTriggerSourceSWStart
+ * @param ADCx ADC instance
+ * @retval Value "0" trigger source external trigger
+ * Value "1" trigger source SW start.
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL) == (LL_ADC_REG_TRIG_SOFTWARE));
+}
+
+
+/**
+ * @brief Set ADC group regular sequencer length and scan direction.
+ * @note Description of ADC group regular sequencer features:
+ * - For devices with sequencer fully configurable
+ * (function "LL_ADC_REG_SetSequencerRanks()" available):
+ * sequencer length and each rank affectation to a channel
+ * are configurable.
+ * This function performs configuration of:
+ * - Sequence length: Number of ranks in the scan sequence.
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from rank 1 to rank n).
+ * Sequencer ranks are selected using
+ * function "LL_ADC_REG_SetSequencerRanks()".
+ * - For devices with sequencer not fully configurable
+ * (function "LL_ADC_REG_SetSequencerChannels()" available):
+ * sequencer length and each rank affectation to a channel
+ * are defined by channel number.
+ * This function performs configuration of:
+ * - Sequence length: Number of ranks in the scan sequence is
+ * defined by number of channels set in the sequence,
+ * rank of each channel is fixed by channel HW number.
+ * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from lowest channel number to
+ * highest channel number).
+ * Sequencer ranks are selected using
+ * function "LL_ADC_REG_SetSequencerChannels()".
+ * @note On this STM32 serie, group regular sequencer configuration
+ * is conditioned to ADC instance sequencer mode.
+ * If ADC instance sequencer mode is disabled, sequencers of
+ * all groups (group regular, group injected) can be configured
+ * but their execution is disabled (limited to rank 1).
+ * Refer to function @ref LL_ADC_SetSequencersScanMode().
+ * @note Sequencer disabled is equivalent to sequencer of 1 rank:
+ * ADC conversion on only 1 channel.
+ * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
+ * @param ADCx ADC instance
+ * @param SequencerNbRanks This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
+{
+ MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
+}
+
+/**
+ * @brief Get ADC group regular sequencer length and scan direction.
+ * @note Description of ADC group regular sequencer features:
+ * - For devices with sequencer fully configurable
+ * (function "LL_ADC_REG_SetSequencerRanks()" available):
+ * sequencer length and each rank affectation to a channel
+ * are configurable.
+ * This function retrieves:
+ * - Sequence length: Number of ranks in the scan sequence.
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from rank 1 to rank n).
+ * Sequencer ranks are selected using
+ * function "LL_ADC_REG_SetSequencerRanks()".
+ * - For devices with sequencer not fully configurable
+ * (function "LL_ADC_REG_SetSequencerChannels()" available):
+ * sequencer length and each rank affectation to a channel
+ * are defined by channel number.
+ * This function retrieves:
+ * - Sequence length: Number of ranks in the scan sequence is
+ * defined by number of channels set in the sequence,
+ * rank of each channel is fixed by channel HW number.
+ * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from lowest channel number to
+ * highest channel number).
+ * Sequencer ranks are selected using
+ * function "LL_ADC_REG_SetSequencerChannels()".
+ * @note On this STM32 serie, group regular sequencer configuration
+ * is conditioned to ADC instance sequencer mode.
+ * If ADC instance sequencer mode is disabled, sequencers of
+ * all groups (group regular, group injected) can be configured
+ * but their execution is disabled (limited to rank 1).
+ * Refer to function @ref LL_ADC_SetSequencersScanMode().
+ * @note Sequencer disabled is equivalent to sequencer of 1 rank:
+ * ADC conversion on only 1 channel.
+ * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
+}
+
+/**
+ * @brief Set ADC group regular sequencer discontinuous mode:
+ * sequence subdivided and scan conversions interrupted every selected
+ * number of ranks.
+ * @note It is not possible to enable both ADC group regular
+ * continuous mode and sequencer discontinuous mode.
+ * @note It is not possible to enable both ADC auto-injected mode
+ * and ADC group regular sequencer discontinuous mode.
+ * @rmtoll CR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n
+ * CR1 DISCNUM LL_ADC_REG_SetSequencerDiscont
+ * @param ADCx ADC instance
+ * @param SeqDiscont This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
+{
+ MODIFY_REG(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM, SeqDiscont);
+}
+
+/**
+ * @brief Get ADC group regular sequencer discontinuous mode:
+ * sequence subdivided and scan conversions interrupted every selected
+ * number of ranks.
+ * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n
+ * CR1 DISCNUM LL_ADC_REG_GetSequencerDiscont
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM));
+}
+
+/**
+ * @brief Set ADC group regular sequence: channel on the selected
+ * scan sequence rank.
+ * @note This function performs configuration of:
+ * - Channels ordering into each rank of scan sequence:
+ * whatever channel can be placed into whatever rank.
+ * @note On this STM32 serie, ADC group regular sequencer is
+ * fully configurable: sequencer length and each rank
+ * affectation to a channel are configurable.
+ * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
+ * @note Depending on devices and packages, some channels may not be available.
+ * Refer to device datasheet for channels availability.
+ * @note On this STM32 serie, to measure internal channels (VrefInt,
+ * TempSensor, ...), measurement paths to internal channels must be
+ * enabled separately.
+ * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+ * @rmtoll SQR3 SQ1 LL_ADC_REG_SetSequencerRanks\n
+ * SQR3 SQ2 LL_ADC_REG_SetSequencerRanks\n
+ * SQR3 SQ3 LL_ADC_REG_SetSequencerRanks\n
+ * SQR3 SQ4 LL_ADC_REG_SetSequencerRanks\n
+ * SQR3 SQ5 LL_ADC_REG_SetSequencerRanks\n
+ * SQR3 SQ6 LL_ADC_REG_SetSequencerRanks\n
+ * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n
+ * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n
+ * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n
+ * SQR2 SQ10 LL_ADC_REG_SetSequencerRanks\n
+ * SQR2 SQ11 LL_ADC_REG_SetSequencerRanks\n
+ * SQR2 SQ12 LL_ADC_REG_SetSequencerRanks\n
+ * SQR1 SQ13 LL_ADC_REG_SetSequencerRanks\n
+ * SQR1 SQ14 LL_ADC_REG_SetSequencerRanks\n
+ * SQR1 SQ15 LL_ADC_REG_SetSequencerRanks\n
+ * SQR1 SQ16 LL_ADC_REG_SetSequencerRanks
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_RANK_1
+ * @arg @ref LL_ADC_REG_RANK_2
+ * @arg @ref LL_ADC_REG_RANK_3
+ * @arg @ref LL_ADC_REG_RANK_4
+ * @arg @ref LL_ADC_REG_RANK_5
+ * @arg @ref LL_ADC_REG_RANK_6
+ * @arg @ref LL_ADC_REG_RANK_7
+ * @arg @ref LL_ADC_REG_RANK_8
+ * @arg @ref LL_ADC_REG_RANK_9
+ * @arg @ref LL_ADC_REG_RANK_10
+ * @arg @ref LL_ADC_REG_RANK_11
+ * @arg @ref LL_ADC_REG_RANK_12
+ * @arg @ref LL_ADC_REG_RANK_13
+ * @arg @ref LL_ADC_REG_RANK_14
+ * @arg @ref LL_ADC_REG_RANK_15
+ * @arg @ref LL_ADC_REG_RANK_16
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ *
+ * (1) On STM32F37x, parameter available only on ADC instance: ADC1.
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
+{
+ /* Set bits with content of parameter "Channel" with bits position */
+ /* in register and register position depending on parameter "Rank". */
+ /* Parameters "Rank" and "Channel" are used with masks because containing */
+ /* other bits reserved for other purpose. */
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
+
+ MODIFY_REG(*preg,
+ ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
+ (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
+}
+
+/**
+ * @brief Get ADC group regular sequence: channel on the selected
+ * scan sequence rank.
+ * @note On this STM32 serie, ADC group regular sequencer is
+ * fully configurable: sequencer length and each rank
+ * affectation to a channel are configurable.
+ * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
+ * @note Depending on devices and packages, some channels may not be available.
+ * Refer to device datasheet for channels availability.
+ * @note Usage of the returned channel number:
+ * - To reinject this channel into another function LL_ADC_xxx:
+ * the returned channel number is only partly formatted on definition
+ * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+ * with parts of literals LL_ADC_CHANNEL_x or using
+ * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * Then the selected literal LL_ADC_CHANNEL_x can be used
+ * as parameter for another function.
+ * - To get the channel number in decimal format:
+ * process the returned value with the helper macro
+ * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * @rmtoll SQR3 SQ1 LL_ADC_REG_GetSequencerRanks\n
+ * SQR3 SQ2 LL_ADC_REG_GetSequencerRanks\n
+ * SQR3 SQ3 LL_ADC_REG_GetSequencerRanks\n
+ * SQR3 SQ4 LL_ADC_REG_GetSequencerRanks\n
+ * SQR3 SQ5 LL_ADC_REG_GetSequencerRanks\n
+ * SQR3 SQ6 LL_ADC_REG_GetSequencerRanks\n
+ * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n
+ * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n
+ * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n
+ * SQR2 SQ10 LL_ADC_REG_GetSequencerRanks\n
+ * SQR2 SQ11 LL_ADC_REG_GetSequencerRanks\n
+ * SQR2 SQ12 LL_ADC_REG_GetSequencerRanks\n
+ * SQR1 SQ13 LL_ADC_REG_GetSequencerRanks\n
+ * SQR1 SQ14 LL_ADC_REG_GetSequencerRanks\n
+ * SQR1 SQ15 LL_ADC_REG_GetSequencerRanks\n
+ * SQR1 SQ16 LL_ADC_REG_GetSequencerRanks
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_RANK_1
+ * @arg @ref LL_ADC_REG_RANK_2
+ * @arg @ref LL_ADC_REG_RANK_3
+ * @arg @ref LL_ADC_REG_RANK_4
+ * @arg @ref LL_ADC_REG_RANK_5
+ * @arg @ref LL_ADC_REG_RANK_6
+ * @arg @ref LL_ADC_REG_RANK_7
+ * @arg @ref LL_ADC_REG_RANK_8
+ * @arg @ref LL_ADC_REG_RANK_9
+ * @arg @ref LL_ADC_REG_RANK_10
+ * @arg @ref LL_ADC_REG_RANK_11
+ * @arg @ref LL_ADC_REG_RANK_12
+ * @arg @ref LL_ADC_REG_RANK_13
+ * @arg @ref LL_ADC_REG_RANK_14
+ * @arg @ref LL_ADC_REG_RANK_15
+ * @arg @ref LL_ADC_REG_RANK_16
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ *
+ * (1) On STM32F37x, parameter available only on ADC instance: ADC1.\n
+ * (1) For ADC channel read back from ADC register,
+ * comparison with internal channel parameter to be done
+ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
+
+ return (uint32_t) (READ_BIT(*preg,
+ ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
+ >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)
+ );
+}
+
+/**
+ * @brief Set ADC continuous conversion mode on ADC group regular.
+ * @note Description of ADC continuous conversion mode:
+ * - single mode: one conversion per trigger
+ * - continuous mode: after the first trigger, following
+ * conversions launched successively automatically.
+ * @note It is not possible to enable both ADC group regular
+ * continuous mode and sequencer discontinuous mode.
+ * @rmtoll CR2 CONT LL_ADC_REG_SetContinuousMode
+ * @param ADCx ADC instance
+ * @param Continuous This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_CONV_SINGLE
+ * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
+{
+ MODIFY_REG(ADCx->CR2, ADC_CR2_CONT, Continuous);
+}
+
+/**
+ * @brief Get ADC continuous conversion mode on ADC group regular.
+ * @note Description of ADC continuous conversion mode:
+ * - single mode: one conversion per trigger
+ * - continuous mode: after the first trigger, following
+ * conversions launched successively automatically.
+ * @rmtoll CR2 CONT LL_ADC_REG_GetContinuousMode
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_CONV_SINGLE
+ * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_CONT));
+}
+
+/**
+ * @brief Set ADC group regular conversion data transfer: no transfer or
+ * transfer by DMA, and DMA requests mode.
+ * @note If transfer by DMA selected, specifies the DMA requests
+ * mode:
+ * - Limited mode (One shot mode): DMA transfer requests are stopped
+ * when number of DMA data transfers (number of
+ * ADC conversions) is reached.
+ * This ADC mode is intended to be used with DMA mode non-circular.
+ * - Unlimited mode: DMA transfer requests are unlimited,
+ * whatever number of DMA data transfers (number of
+ * ADC conversions).
+ * This ADC mode is intended to be used with DMA mode circular.
+ * @note If ADC DMA requests mode is set to unlimited and DMA is set to
+ * mode non-circular:
+ * when DMA transfers size will be reached, DMA will stop transfers of
+ * ADC conversions data ADC will raise an overrun error
+ * (overrun flag and interruption if enabled).
+ * @note To configure DMA source address (peripheral address),
+ * use function @ref LL_ADC_DMA_GetRegAddr().
+ * @rmtoll CR2 DMA LL_ADC_REG_SetDMATransfer
+ * @param ADCx ADC instance
+ * @param DMATransfer This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
+ * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
+{
+ MODIFY_REG(ADCx->CR2, ADC_CR2_DMA, DMATransfer);
+}
+
+/**
+ * @brief Get ADC group regular conversion data transfer: no transfer or
+ * transfer by DMA, and DMA requests mode.
+ * @note If transfer by DMA selected, specifies the DMA requests
+ * mode:
+ * - Limited mode (One shot mode): DMA transfer requests are stopped
+ * when number of DMA data transfers (number of
+ * ADC conversions) is reached.
+ * This ADC mode is intended to be used with DMA mode non-circular.
+ * - Unlimited mode: DMA transfer requests are unlimited,
+ * whatever number of DMA data transfers (number of
+ * ADC conversions).
+ * This ADC mode is intended to be used with DMA mode circular.
+ * @note If ADC DMA requests mode is set to unlimited and DMA is set to
+ * mode non-circular:
+ * when DMA transfers size will be reached, DMA will stop transfers of
+ * ADC conversions data ADC will raise an overrun error
+ * (overrun flag and interruption if enabled).
+ * @note To configure DMA source address (peripheral address),
+ * use function @ref LL_ADC_DMA_GetRegAddr().
+ * @rmtoll CR2 DMA LL_ADC_REG_GetDMATransfer
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
+ * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_DMA));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
+ * @{
+ */
+
+/**
+ * @brief Set ADC group injected conversion trigger source:
+ * internal (SW start) or external from timer or external interrupt.
+ * @note On this STM32 serie, external trigger is set with trigger polarity:
+ * rising edge (only trigger polarity available on this STM32 serie).
+ * @note Availability of parameters of trigger sources from timer
+ * depends on timers availability on the selected device.
+ * @rmtoll CR2 JEXTSEL LL_ADC_INJ_SetTriggerSource
+ * @param ADCx ADC instance
+ * @param TriggerSource This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM19_CH1
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM19_CH2
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
+{
+/* Note: On this STM32 serie, ADC group injected external trigger edge */
+/* is used to perform a ADC conversion start. */
+/* This function does not set external trigger edge. */
+/* This feature is set using function */
+/* @ref LL_ADC_INJ_StartConversionExtTrig(). */
+ MODIFY_REG(ADCx->CR2, ADC_CR2_JEXTSEL, (TriggerSource & ADC_CR2_JEXTSEL));
+}
+
+/**
+ * @brief Get ADC group injected conversion trigger source:
+ * internal (SW start) or external from timer or external interrupt.
+ * @note To determine whether group injected trigger source is
+ * internal (SW start) or external, without detail
+ * of which peripheral is selected as external trigger,
+ * (equivalent to
+ * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
+ * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
+ * @note Availability of parameters of trigger sources from timer
+ * depends on timers availability on the selected device.
+ * @rmtoll CR2 JEXTSEL LL_ADC_INJ_GetTriggerSource
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM19_CH1
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM19_CH2
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL));
+}
+
+/**
+ * @brief Get ADC group injected conversion trigger source internal (SW start)
+ or external
+ * @note In case of group injected trigger source set to external trigger,
+ * to determine which peripheral is selected as external trigger,
+ * use function @ref LL_ADC_INJ_GetTriggerSource.
+ * @rmtoll CR2 JEXTSEL LL_ADC_INJ_IsTriggerSourceSWStart
+ * @param ADCx ADC instance
+ * @retval Value "0" trigger source external trigger
+ * Value "1" trigger source SW start.
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL) == LL_ADC_INJ_TRIG_SOFTWARE);
+}
+
+/**
+ * @brief Set ADC group injected sequencer length and scan direction.
+ * @note This function performs configuration of:
+ * - Sequence length: Number of ranks in the scan sequence.
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from rank 1 to rank n).
+ * @note On this STM32 serie, group injected sequencer configuration
+ * is conditioned to ADC instance sequencer mode.
+ * If ADC instance sequencer mode is disabled, sequencers of
+ * all groups (group regular, group injected) can be configured
+ * but their execution is disabled (limited to rank 1).
+ * Refer to function @ref LL_ADC_SetSequencersScanMode().
+ * @note Sequencer disabled is equivalent to sequencer of 1 rank:
+ * ADC conversion on only 1 channel.
+ * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
+ * @param ADCx ADC instance
+ * @param SequencerNbRanks This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
+{
+ MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
+}
+
+/**
+ * @brief Get ADC group injected sequencer length and scan direction.
+ * @note This function retrieves:
+ * - Sequence length: Number of ranks in the scan sequence.
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from rank 1 to rank n).
+ * @note On this STM32 serie, group injected sequencer configuration
+ * is conditioned to ADC instance sequencer mode.
+ * If ADC instance sequencer mode is disabled, sequencers of
+ * all groups (group regular, group injected) can be configured
+ * but their execution is disabled (limited to rank 1).
+ * Refer to function @ref LL_ADC_SetSequencersScanMode().
+ * @note Sequencer disabled is equivalent to sequencer of 1 rank:
+ * ADC conversion on only 1 channel.
+ * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
+}
+
+/**
+ * @brief Set ADC group injected sequencer discontinuous mode:
+ * sequence subdivided and scan conversions interrupted every selected
+ * number of ranks.
+ * @note It is not possible to enable both ADC group injected
+ * auto-injected mode and sequencer discontinuous mode.
+ * @rmtoll CR1 DISCEN LL_ADC_INJ_SetSequencerDiscont
+ * @param ADCx ADC instance
+ * @param SeqDiscont This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
+ * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
+{
+ MODIFY_REG(ADCx->CR1, ADC_CR1_JDISCEN, SeqDiscont);
+}
+
+/**
+ * @brief Get ADC group injected sequencer discontinuous mode:
+ * sequence subdivided and scan conversions interrupted every selected
+ * number of ranks.
+ * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
+ * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JDISCEN));
+}
+
+/**
+ * @brief Set ADC group injected sequence: channel on the selected
+ * sequence rank.
+ * @note Depending on devices and packages, some channels may not be available.
+ * Refer to device datasheet for channels availability.
+ * @note On this STM32 serie, to measure internal channels (VrefInt,
+ * TempSensor, ...), measurement paths to internal channels must be
+ * enabled separately.
+ * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+ * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
+ * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
+ * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
+ * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ *
+ * (1) On STM32F37x, parameter available only on ADC instance: ADC1.
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
+{
+ /* Set bits with content of parameter "Channel" with bits position */
+ /* in register depending on parameter "Rank". */
+ /* Parameters "Rank" and "Channel" are used with masks because containing */
+ /* other bits reserved for other purpose. */
+ MODIFY_REG(ADCx->JSQR,
+ ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),
+ (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));
+}
+
+/**
+ * @brief Get ADC group injected sequence: channel on the selected
+ * sequence rank.
+ * @note Depending on devices and packages, some channels may not be available.
+ * Refer to device datasheet for channels availability.
+ * @note Usage of the returned channel number:
+ * - To reinject this channel into another function LL_ADC_xxx:
+ * the returned channel number is only partly formatted on definition
+ * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+ * with parts of literals LL_ADC_CHANNEL_x or using
+ * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * Then the selected literal LL_ADC_CHANNEL_x can be used
+ * as parameter for another function.
+ * - To get the channel number in decimal format:
+ * process the returned value with the helper macro
+ * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
+ * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
+ * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
+ * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ *
+ * (1) On STM32F37x, parameter available only on ADC instance: ADC1.\n
+ * (1) For ADC channel read back from ADC register,
+ * comparison with internal channel parameter to be done
+ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ return (uint32_t)(READ_BIT(ADCx->JSQR,
+ ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
+ >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)
+ );
+}
+
+/**
+ * @brief Set ADC group injected conversion trigger:
+ * independent or from ADC group regular.
+ * @note This mode can be used to extend number of data registers
+ * updated after one ADC conversion trigger and with data
+ * permanently kept (not erased by successive conversions of scan of
+ * ADC sequencer ranks), up to 5 data registers:
+ * 1 data register on ADC group regular, 4 data registers
+ * on ADC group injected.
+ * @note If ADC group injected injected trigger source is set to an
+ * external trigger, this feature must be must be set to
+ * independent trigger.
+ * ADC group injected automatic trigger is compliant only with
+ * group injected trigger source set to SW start, without any
+ * further action on ADC group injected conversion start or stop:
+ * in this case, ADC group injected is controlled only
+ * from ADC group regular.
+ * @note It is not possible to enable both ADC group injected
+ * auto-injected mode and sequencer discontinuous mode.
+ * @rmtoll CR1 JAUTO LL_ADC_INJ_SetTrigAuto
+ * @param ADCx ADC instance
+ * @param TrigAuto This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
+ * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
+{
+ MODIFY_REG(ADCx->CR1, ADC_CR1_JAUTO, TrigAuto);
+}
+
+/**
+ * @brief Get ADC group injected conversion trigger:
+ * independent or from ADC group regular.
+ * @rmtoll CR1 JAUTO LL_ADC_INJ_GetTrigAuto
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
+ * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JAUTO));
+}
+
+/**
+ * @brief Set ADC group injected offset.
+ * @note It sets:
+ * - ADC group injected rank to which the offset programmed
+ * will be applied
+ * - Offset level (offset to be subtracted from the raw
+ * converted data).
+ * Caution: Offset format is dependent to ADC resolution:
+ * offset has to be left-aligned on bit 11, the LSB (right bits)
+ * are set to 0.
+ * @note Offset cannot be enabled or disabled.
+ * To emulate offset disabled, set an offset value equal to 0.
+ * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_SetOffset\n
+ * JOFR2 JOFFSET2 LL_ADC_INJ_SetOffset\n
+ * JOFR3 JOFFSET3 LL_ADC_INJ_SetOffset\n
+ * JOFR4 JOFFSET4 LL_ADC_INJ_SetOffset
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel)
+{
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
+
+ MODIFY_REG(*preg,
+ ADC_JOFR1_JOFFSET1,
+ OffsetLevel);
+}
+
+/**
+ * @brief Get ADC group injected offset.
+ * @note It gives offset level (offset to be subtracted from the raw converted data).
+ * Caution: Offset format is dependent to ADC resolution:
+ * offset has to be left-aligned on bit 11, the LSB (right bits)
+ * are set to 0.
+ * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_GetOffset\n
+ * JOFR2 JOFFSET2 LL_ADC_INJ_GetOffset\n
+ * JOFR3 JOFFSET3 LL_ADC_INJ_GetOffset\n
+ * JOFR4 JOFFSET4 LL_ADC_INJ_GetOffset
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
+
+ return (uint32_t)(READ_BIT(*preg,
+ ADC_JOFR1_JOFFSET1)
+ );
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
+ * @{
+ */
+
+/**
+ * @brief Set sampling time of the selected ADC channel
+ * Unit: ADC clock cycles.
+ * @note On this device, sampling time is on channel scope: independently
+ * of channel mapped on ADC group regular or injected.
+ * @note In case of internal channel (VrefInt, TempSensor, ...) to be
+ * converted:
+ * sampling time constraints must be respected (sampling time can be
+ * adjusted in function of ADC clock frequency and sampling time
+ * setting).
+ * Refer to device datasheet for timings values (parameters TS_vrefint,
+ * TS_temp, ...).
+ * @note Conversion time is the addition of sampling time and processing time.
+ * Refer to reference manual for ADC processing time of
+ * this STM32 serie.
+ * @note In case of ADC conversion of internal channel (VrefInt,
+ * temperature sensor, ...), a sampling time minimum value
+ * is required.
+ * Refer to device datasheet.
+ * @rmtoll SMPR1 SMP17 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP16 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP15 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP14 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP13 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP12 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP11 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP10 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP9 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP8 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP7 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP6 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP5 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP4 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP3 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP2 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP1 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP0 LL_ADC_SetChannelSamplingTime
+ * @param ADCx ADC instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ *
+ * (1) On STM32F37x, parameter available only on ADC instance: ADC1.
+ * @param SamplingTime This parameter can be one of the following values:
+ * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_13CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_41CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_55CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_71CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_239CYCLES_5
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
+{
+ /* Set bits with content of parameter "SamplingTime" with bits position */
+ /* in register and register position depending on parameter "Channel". */
+ /* Parameter "Channel" is used with masks because containing */
+ /* other bits reserved for other purpose. */
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
+
+ MODIFY_REG(*preg,
+ ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK),
+ SamplingTime << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Get sampling time of the selected ADC channel
+ * Unit: ADC clock cycles.
+ * @note On this device, sampling time is on channel scope: independently
+ * of channel mapped on ADC group regular or injected.
+ * @note Conversion time is the addition of sampling time and processing time.
+ * Refer to reference manual for ADC processing time of
+ * this STM32 serie.
+ * @rmtoll SMPR1 SMP17 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP16 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP15 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP14 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP13 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP12 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP11 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP10 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP9 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP8 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP7 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP6 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP5 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP4 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP3 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP2 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP1 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP0 LL_ADC_GetChannelSamplingTime
+ * @param ADCx ADC instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ *
+ * (1) On STM32F37x, parameter available only on ADC instance: ADC1.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_13CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_41CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_55CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_71CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_239CYCLES_5
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
+{
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
+
+ return (uint32_t)(READ_BIT(*preg,
+ ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK))
+ >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)
+ );
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
+ * @{
+ */
+
+/**
+ * @brief Set ADC analog watchdog monitored channels:
+ * a single channel or all channels,
+ * on ADC groups regular and-or injected.
+ * @note Once monitored channels are selected, analog watchdog
+ * is enabled.
+ * @note In case of need to define a single channel to monitor
+ * with analog watchdog from sequencer channel definition,
+ * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
+ * @note On this STM32 serie, there is only 1 kind of analog watchdog
+ * instance:
+ * - AWD standard (instance AWD1):
+ * - channels monitored: can monitor 1 channel or all channels.
+ * - groups monitored: ADC groups regular and-or injected.
+ * - resolution: resolution is not limited (corresponds to
+ * ADC resolution configured).
+ * @rmtoll CR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
+ * CR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
+ * CR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels
+ * @param ADCx ADC instance
+ * @param AWDChannelGroup This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD_DISABLE
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1)
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
+ *
+ * (1) On STM32F37x, parameter available only on ADC instance: ADC1.
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup)
+{
+ MODIFY_REG(ADCx->CR1,
+ (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH),
+ AWDChannelGroup);
+}
+
+/**
+ * @brief Get ADC analog watchdog monitored channel.
+ * @note Usage of the returned channel number:
+ * - To reinject this channel into another function LL_ADC_xxx:
+ * the returned channel number is only partly formatted on definition
+ * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+ * with parts of literals LL_ADC_CHANNEL_x or using
+ * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * Then the selected literal LL_ADC_CHANNEL_x can be used
+ * as parameter for another function.
+ * - To get the channel number in decimal format:
+ * process the returned value with the helper macro
+ * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * Applicable only when the analog watchdog is set to monitor
+ * one channel.
+ * @note On this STM32 serie, there is only 1 kind of analog watchdog
+ * instance:
+ * - AWD standard (instance AWD1):
+ * - channels monitored: can monitor 1 channel or all channels.
+ * - groups monitored: ADC groups regular and-or injected.
+ * - resolution: resolution is not limited (corresponds to
+ * ADC resolution configured).
+ * @rmtoll CR1 AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
+ * CR1 AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
+ * CR1 AWD1EN LL_ADC_GetAnalogWDMonitChannels
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_AWD_DISABLE
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH)));
+}
+
+/**
+ * @brief Set ADC analog watchdog threshold value of threshold
+ * high or low.
+ * @note On this STM32 serie, there is only 1 kind of analog watchdog
+ * instance:
+ * - AWD standard (instance AWD1):
+ * - channels monitored: can monitor 1 channel or all channels.
+ * - groups monitored: ADC groups regular and-or injected.
+ * - resolution: resolution is not limited (corresponds to
+ * ADC resolution configured).
+ * @rmtoll HTR HT LL_ADC_SetAnalogWDThresholds\n
+ * LTR LT LL_ADC_SetAnalogWDThresholds
+ * @param ADCx ADC instance
+ * @param AWDThresholdsHighLow This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
+ * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
+ * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
+{
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
+
+ MODIFY_REG(*preg,
+ ADC_HTR_HT,
+ AWDThresholdValue);
+}
+
+/**
+ * @brief Get ADC analog watchdog threshold value of threshold high or
+ * threshold low.
+ * @note In case of ADC resolution different of 12 bits,
+ * analog watchdog thresholds data require a specific shift.
+ * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
+ * @rmtoll HTR HT LL_ADC_GetAnalogWDThresholds\n
+ * LTR LT LL_ADC_GetAnalogWDThresholds
+ * @param ADCx ADC instance
+ * @param AWDThresholdsHighLow This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
+ * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+*/
+__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)
+{
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
+
+ return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
+ * @{
+ */
+
+/**
+ * @brief Enable the selected ADC instance.
+ * @note On this STM32 serie, after ADC enable, a delay for
+ * ADC internal analog stabilization is required before performing a
+ * ADC conversion start.
+ * Refer to device datasheet, parameter tSTAB.
+ * @rmtoll CR2 ADON LL_ADC_Enable
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->CR2, ADC_CR2_ADON);
+}
+
+/**
+ * @brief Disable the selected ADC instance.
+ * @rmtoll CR2 ADON LL_ADC_Disable
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->CR2, ADC_CR2_ADON);
+}
+
+/**
+ * @brief Get the selected ADC instance enable state.
+ * @rmtoll CR2 ADON LL_ADC_IsEnabled
+ * @param ADCx ADC instance
+ * @retval 0: ADC is disabled, 1: ADC is enabled.
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->CR2, ADC_CR2_ADON) == (ADC_CR2_ADON));
+}
+
+/**
+ * @brief Start ADC calibration in the mode single-ended
+ * or differential (for devices with differential mode available).
+ * @note On this STM32 serie, before starting a calibration,
+ * ADC must be disabled.
+ * A minimum number of ADC clock cycles are required
+ * between ADC disable state and calibration start.
+ * Refer to literal @ref LL_ADC_DELAY_DISABLE_CALIB_ADC_CYCLES.
+ * @note On this STM32 serie, hardware prerequisite before starting a calibration:
+ the ADC must have been in power-on state for at least
+ two ADC clock cycles.
+ * @rmtoll CR2 CAL LL_ADC_StartCalibration
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->CR2, ADC_CR2_CAL);
+}
+
+/**
+ * @brief Get ADC calibration state.
+ * @rmtoll CR2 CAL LL_ADC_IsCalibrationOnGoing
+ * @param ADCx ADC instance
+ * @retval 0: calibration complete, 1: calibration in progress.
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->CR2, ADC_CR2_CAL) == (ADC_CR2_CAL));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
+ * @{
+ */
+
+/**
+ * @brief Start ADC group regular conversion.
+ * @note On this STM32 serie, this function is relevant for both
+ * internal trigger (SW start) and external trigger:
+ * - If ADC trigger has been set to software start, ADC conversion
+ * starts immediately.
+ * - If ADC trigger has been set to external trigger, ADC conversion
+ * will start at next trigger event (on the selected trigger edge)
+ * following the ADC start conversion command.
+ * @rmtoll CR2 EXTTRIG LL_ADC_REG_StartConversion
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
+{
+ /* Note: Set bit ADC_CR2_SWSTART for case of trigger source set to */
+ /* SW start. In case of external trigger selected, this bit */
+ /* has no effect. */
+ SET_BIT(ADCx->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
+}
+
+/**
+ * @brief Stop ADC group regular conversion from external trigger.
+ * @note No more ADC conversion will start at next trigger event
+ * following the ADC stop conversion command.
+ * If a conversion is on-going, it will be completed.
+ * @note On this STM32 serie, there is no specific command
+ * to stop a conversion on-going or to stop ADC converting
+ * in continuous mode. These actions can be performed
+ * using function @ref LL_ADC_Disable().
+ * @rmtoll CR2 EXTSEL LL_ADC_REG_StopConversionExtTrig
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->CR2, ADC_CR2_EXTSEL);
+}
+
+/**
+ * @brief Get ADC group regular conversion data, range fit for
+ * all ADC configurations: all ADC resolutions and
+ * all oversampling increased data width (for devices
+ * with feature oversampling).
+ * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
+ * @param ADCx ADC instance
+ * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
+{
+ return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
+}
+
+/**
+ * @brief Get ADC group regular conversion data, range fit for
+ * ADC resolution 12 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_REG_ReadConversionData32.
+ * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
+ * @param ADCx ADC instance
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
+{
+ return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
+ * @{
+ */
+
+/**
+ * @brief Start ADC group injected conversion.
+ * @note On this STM32 serie, this function is relevant for both
+ * internal trigger (SW start) and external trigger:
+ * - If ADC trigger has been set to software start, ADC conversion
+ * starts immediately.
+ * - If ADC trigger has been set to external trigger, ADC conversion
+ * will start at next trigger event (on the selected trigger edge)
+ * following the ADC start conversion command.
+ * @rmtoll CR2 JEXTTRIG LL_ADC_REG_StartConversion
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)
+{
+ /* Note: Set bit ADC_CR2_JSWSTART for case of trigger source set to */
+ /* SW start. In case of external trigger selected, this bit */
+ /* has no effect. */
+ SET_BIT(ADCx->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG));
+}
+
+/**
+ * @brief Stop ADC group injected conversion from external trigger.
+ * @note No more ADC conversion will start at next trigger event
+ * following the ADC stop conversion command.
+ * If a conversion is on-going, it will be completed.
+ * @note On this STM32 serie, there is no specific command
+ * to stop a conversion on-going or to stop ADC converting
+ * in continuous mode. These actions can be performed
+ * using function @ref LL_ADC_Disable().
+ * @rmtoll CR2 JEXTSEL LL_ADC_INJ_StopConversionExtTrig
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->CR2, ADC_CR2_JEXTSEL);
+}
+
+/**
+ * @brief Get ADC group regular conversion data, range fit for
+ * all ADC configurations: all ADC resolutions and
+ * all oversampling increased data width (for devices
+ * with feature oversampling).
+ * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n
+ * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n
+ * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n
+ * JDR4 JDATA LL_ADC_INJ_ReadConversionData32
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
+
+ return (uint32_t)(READ_BIT(*preg,
+ ADC_JDR1_JDATA)
+ );
+}
+
+/**
+ * @brief Get ADC group injected conversion data, range fit for
+ * ADC resolution 12 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+ * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n
+ * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n
+ * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n
+ * JDR4 JDATA LL_ADC_INJ_ReadConversionData12
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
+
+ return (uint16_t)(READ_BIT(*preg,
+ ADC_JDR1_JDATA)
+ );
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
+ * @{
+ */
+
+/**
+ * @brief Get flag ADC group regular end of sequence conversions.
+ * @rmtoll SR EOC LL_ADC_IsActiveFlag_EOS
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
+{
+ /* Note: on this STM32 serie, there is no flag ADC group regular */
+ /* end of unitary conversion. */
+ /* Flag noted as "EOC" is corresponding to flag "EOS" */
+ /* in other STM32 families). */
+ return (READ_BIT(ADCx->SR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS));
+}
+
+
+/**
+ * @brief Get flag ADC group injected end of sequence conversions.
+ * @rmtoll SR JEOC LL_ADC_IsActiveFlag_JEOS
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
+{
+ /* Note: on this STM32 serie, there is no flag ADC group injected */
+ /* end of unitary conversion. */
+ /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
+ /* in other STM32 families). */
+ return (READ_BIT(ADCx->SR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS));
+}
+
+/**
+ * @brief Get flag ADC analog watchdog 1 flag
+ * @rmtoll SR AWD LL_ADC_IsActiveFlag_AWD1
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
+}
+
+/**
+ * @brief Clear flag ADC group regular end of sequence conversions.
+ * @rmtoll SR EOC LL_ADC_ClearFlag_EOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
+{
+ /* Note: on this STM32 serie, there is no flag ADC group regular */
+ /* end of unitary conversion. */
+ /* Flag noted as "EOC" is corresponding to flag "EOS" */
+ /* in other STM32 families). */
+ WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_EOS);
+}
+
+
+/**
+ * @brief Clear flag ADC group injected end of sequence conversions.
+ * @rmtoll SR JEOC LL_ADC_ClearFlag_JEOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
+{
+ /* Note: on this STM32 serie, there is no flag ADC group injected */
+ /* end of unitary conversion. */
+ /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
+ /* in other STM32 families). */
+ WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_JEOS);
+}
+
+/**
+ * @brief Clear flag ADC analog watchdog 1.
+ * @rmtoll SR AWD LL_ADC_ClearFlag_AWD1
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_AWD1);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_IT_Management ADC IT management
+ * @{
+ */
+
+/**
+ * @brief Enable interruption ADC group regular end of sequence conversions.
+ * @rmtoll CR1 EOCIE LL_ADC_EnableIT_EOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
+{
+ /* Note: on this STM32 serie, there is no flag ADC group regular */
+ /* end of unitary conversion. */
+ /* Flag noted as "EOC" is corresponding to flag "EOS" */
+ /* in other STM32 families). */
+ SET_BIT(ADCx->CR1, ADC_CR1_EOCIE);
+}
+
+
+/**
+ * @brief Enable interruption ADC group injected end of sequence conversions.
+ * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
+{
+ /* Note: on this STM32 serie, there is no flag ADC group injected */
+ /* end of unitary conversion. */
+ /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
+ /* in other STM32 families). */
+ SET_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
+}
+
+/**
+ * @brief Enable interruption ADC analog watchdog 1.
+ * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
+}
+
+/**
+ * @brief Disable interruption ADC group regular end of sequence conversions.
+ * @rmtoll CR1 EOCIE LL_ADC_DisableIT_EOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
+{
+ /* Note: on this STM32 serie, there is no flag ADC group regular */
+ /* end of unitary conversion. */
+ /* Flag noted as "EOC" is corresponding to flag "EOS" */
+ /* in other STM32 families). */
+ CLEAR_BIT(ADCx->CR1, ADC_CR1_EOCIE);
+}
+
+
+/**
+ * @brief Disable interruption ADC group injected end of sequence conversions.
+ * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
+{
+ /* Note: on this STM32 serie, there is no flag ADC group injected */
+ /* end of unitary conversion. */
+ /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
+ /* in other STM32 families). */
+ CLEAR_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
+}
+
+/**
+ * @brief Disable interruption ADC analog watchdog 1.
+ * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
+}
+
+/**
+ * @brief Get state of interruption ADC group regular end of sequence conversions
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll CR1 EOCIE LL_ADC_IsEnabledIT_EOS
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
+{
+ /* Note: on this STM32 serie, there is no flag ADC group regular */
+ /* end of unitary conversion. */
+ /* Flag noted as "EOC" is corresponding to flag "EOS" */
+ /* in other STM32 families). */
+ return (READ_BIT(ADCx->CR1, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS));
+}
+
+
+/**
+ * @brief Get state of interruption ADC group injected end of sequence conversions
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
+{
+ /* Note: on this STM32 serie, there is no flag ADC group injected */
+ /* end of unitary conversion. */
+ /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
+ /* in other STM32 families). */
+ return (READ_BIT(ADCx->CR1, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS));
+}
+
+/**
+ * @brief Get state of interruption ADC analog watchdog 1
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->CR1, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1));
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization of some features of ADC common parameters and multimode */
+/* Note: On STM32F37x ADC, there is no ADC common initialization */
+/* function. */
+ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
+
+/* De-initialization of ADC instance, ADC group regular and ADC group injected */
+/* (availability of ADC group injected depends on STM32 families) */
+ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
+
+/* Initialization of some features of ADC instance */
+ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
+void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
+
+/* Initialization of some features of ADC instance and ADC group regular */
+ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
+void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
+
+/* Initialization of some features of ADC instance and ADC group injected */
+ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
+void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* ADC1 */
+
+
+#endif /* STM32F373xC || STM32F378xx */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_LL_ADC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_ll_bus.h b/Inc/stm32f3xx_ll_bus.h
new file mode 100644
index 0000000..f3e5849
--- /dev/null
+++ b/Inc/stm32f3xx_ll_bus.h
@@ -0,0 +1,1079 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_bus.h
+ * @author MCD Application Team
+ * @brief Header file of BUS LL module.
+
+ @verbatim
+ ##### RCC Limitations #####
+ ==============================================================================
+ [..]
+ A delay between an RCC peripheral clock enable and the effective peripheral
+ enabling should be taken into account in order to manage the peripheral read/write
+ from/to registers.
+ (+) This delay depends on the peripheral mapping.
+ (++) AHB & APB peripherals, 1 dummy read is necessary
+
+ [..]
+ Workarounds:
+ (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
+ inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_LL_BUS_H
+#define __STM32F3xx_LL_BUS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx.h"
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined(RCC)
+
+/** @defgroup BUS_LL BUS
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
+ * @{
+ */
+
+/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
+ * @{
+ */
+#define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
+#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN
+#if defined(DMA2)
+#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN
+#endif /*DMA2*/
+#define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN
+#define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN
+#if defined(FMC_Bank1)
+#define LL_AHB1_GRP1_PERIPH_FMC RCC_AHBENR_FMCEN
+#endif /*FMC_Bank1*/
+#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
+#if defined(GPIOH)
+#define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHBENR_GPIOHEN
+#endif /*GPIOH*/
+#define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHBENR_GPIOAEN
+#define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHBENR_GPIOBEN
+#define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHBENR_GPIOCEN
+#define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHBENR_GPIODEN
+#if defined(GPIOE)
+#define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHBENR_GPIOEEN
+#endif /*GPIOE*/
+#define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHBENR_GPIOFEN
+#if defined(GPIOG)
+#define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHBENR_GPIOGEN
+#endif /*GPIOH*/
+#define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN
+#if defined(RCC_AHBENR_ADC1EN)
+#define LL_AHB1_GRP1_PERIPH_ADC1 RCC_AHBENR_ADC1EN
+#endif /*RCC_AHBENR_ADC1EN*/
+#if defined(ADC1_2_COMMON)
+#define LL_AHB1_GRP1_PERIPH_ADC12 RCC_AHBENR_ADC12EN
+#endif /*ADC1_2_COMMON*/
+#if defined(ADC3_4_COMMON)
+#define LL_AHB1_GRP1_PERIPH_ADC34 RCC_AHBENR_ADC34EN
+#endif /*ADC3_4_COMMON*/
+/**
+ * @}
+ */
+
+/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
+ * @{
+ */
+#define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
+#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
+#if defined(TIM3)
+#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN
+#endif /*TIM3*/
+#if defined(TIM4)
+#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN
+#endif /*TIM4*/
+#if defined(TIM5)
+#define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN
+#endif /*TIM5*/
+#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN
+#if defined(TIM7)
+#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN
+#endif /*TIM7*/
+#if defined(TIM12)
+#define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN
+#endif /*TIM12*/
+#if defined(TIM13)
+#define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN
+#endif /*TIM13*/
+#if defined(TIM14)
+#define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN
+#endif /*TIM14*/
+#if defined(TIM18)
+#define LL_APB1_GRP1_PERIPH_TIM18 RCC_APB1ENR_TIM18EN
+#endif /*TIM18*/
+#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN
+#if defined(SPI2)
+#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN
+#endif /*SPI2*/
+#if defined(SPI3)
+#define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN
+#endif /*SPI3*/
+#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
+#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN
+#if defined(UART4)
+#define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN
+#endif /*UART4*/
+#if defined(UART5)
+#define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN
+#endif /*UART5*/
+#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN
+#if defined(I2C2)
+#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
+#endif /*I2C2*/
+#if defined(USB)
+#define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN
+#endif /*USB*/
+#if defined(CAN)
+#define LL_APB1_GRP1_PERIPH_CAN RCC_APB1ENR_CANEN
+#endif /*CAN*/
+#if defined(DAC2)
+#define LL_APB1_GRP1_PERIPH_DAC2 RCC_APB1ENR_DAC2EN
+#endif /*DAC2*/
+#define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
+#define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DAC1EN
+#if defined(CEC)
+#define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN
+#endif /*CEC*/
+#if defined(I2C3)
+#define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN
+#endif /*I2C3*/
+/**
+ * @}
+ */
+
+/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
+ * @{
+ */
+#define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
+#define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
+#if defined(RCC_APB2ENR_ADC1EN)
+#define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
+#endif /*RCC_APB2ENR_ADC1EN*/
+#if defined(TIM1)
+#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
+#endif /*TIM1*/
+#if defined(SPI1)
+#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
+#endif /*SPI1*/
+#if defined(TIM8)
+#define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
+#endif /*TIM8*/
+#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
+#if defined(SPI4)
+#define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN
+#endif /*SPI4*/
+#define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
+#define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
+#define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
+#if defined(TIM19)
+#define LL_APB2_GRP1_PERIPH_TIM19 RCC_APB2ENR_TIM19EN
+#endif /*TIM19*/
+#if defined(TIM20)
+#define LL_APB2_GRP1_PERIPH_TIM20 RCC_APB2ENR_TIM20EN
+#endif /*TIM20*/
+#if defined(HRTIM1)
+#define LL_APB2_GRP1_PERIPH_HRTIM1 RCC_APB2ENR_HRTIM1EN
+#endif /*HRTIM1*/
+#if defined(SDADC1)
+#define LL_APB2_GRP1_PERIPH_SDADC1 RCC_APB2ENR_SDADC1EN
+#endif /*SDADC1*/
+#if defined(SDADC2)
+#define LL_APB2_GRP1_PERIPH_SDADC2 RCC_APB2ENR_SDADC2EN
+#endif /*SDADC2*/
+#if defined(SDADC3)
+#define LL_APB2_GRP1_PERIPH_SDADC3 RCC_APB2ENR_SDADC3EN
+#endif /*SDADC3*/
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
+ * @{
+ */
+
+/** @defgroup BUS_LL_EF_AHB1 AHB1
+ * @{
+ */
+
+/**
+ * @brief Enable AHB1 peripherals clock.
+ * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR DMA2EN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR SRAMEN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR FLITFEN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR FMCEN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR GPIOHEN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR GPIOAEN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR GPIOBEN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR GPIOCEN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR GPIODEN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR GPIOEEN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR GPIOFEN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR GPIOGEN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR TSCEN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR ADC1EN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR ADC12EN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR ADC34EN LL_AHB1_GRP1_EnableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FMC (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ADC1 (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ADC34 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->AHBENR, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->AHBENR, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Check if AHB1 peripheral clock is enabled or not
+ * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR SRAMEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR FMCEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR ADC1EN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR ADC12EN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR ADC34EN LL_AHB1_GRP1_IsEnabledClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FMC (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ADC1 (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ADC34 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval State of Periphs (1 or 0).
+*/
+__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+ return (READ_BIT(RCC->AHBENR, Periphs) == Periphs);
+}
+
+/**
+ * @brief Disable AHB1 peripherals clock.
+ * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR DMA2EN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR SRAMEN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR FLITFEN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR FMCEN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR GPIOHEN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR GPIOAEN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR GPIOBEN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR GPIOCEN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR GPIODEN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR GPIOEEN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR GPIOFEN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR GPIOGEN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR TSCEN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR ADC1EN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR ADC12EN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR ADC34EN LL_AHB1_GRP1_DisableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FMC (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ADC1 (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ADC34 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->AHBENR, Periphs);
+}
+
+/**
+ * @brief Force AHB1 peripherals reset.
+ * @rmtoll AHBRSTR FMCRST LL_AHB1_GRP1_ForceReset\n
+ * AHBRSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n
+ * AHBRSTR GPIOARST LL_AHB1_GRP1_ForceReset\n
+ * AHBRSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n
+ * AHBRSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n
+ * AHBRSTR GPIODRST LL_AHB1_GRP1_ForceReset\n
+ * AHBRSTR GPIOERST LL_AHB1_GRP1_ForceReset\n
+ * AHBRSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n
+ * AHBRSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n
+ * AHBRSTR TSCRST LL_AHB1_GRP1_ForceReset\n
+ * AHBRSTR ADC1RST LL_AHB1_GRP1_ForceReset\n
+ * AHBRSTR ADC12RST LL_AHB1_GRP1_ForceReset\n
+ * AHBRSTR ADC34RST LL_AHB1_GRP1_ForceReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FMC (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ADC1 (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ADC34 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
+{
+ SET_BIT(RCC->AHBRSTR, Periphs);
+}
+
+/**
+ * @brief Release AHB1 peripherals reset.
+ * @rmtoll AHBRSTR FMCRST LL_AHB1_GRP1_ReleaseReset\n
+ * AHBRSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n
+ * AHBRSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n
+ * AHBRSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n
+ * AHBRSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n
+ * AHBRSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n
+ * AHBRSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n
+ * AHBRSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n
+ * AHBRSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n
+ * AHBRSTR TSCRST LL_AHB1_GRP1_ReleaseReset\n
+ * AHBRSTR ADC1RST LL_AHB1_GRP1_ReleaseReset\n
+ * AHBRSTR ADC12RST LL_AHB1_GRP1_ReleaseReset\n
+ * AHBRSTR ADC34RST LL_AHB1_GRP1_ReleaseReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FMC (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ADC1 (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ADC34 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->AHBRSTR, Periphs);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup BUS_LL_EF_APB1 APB1
+ * @{
+ */
+
+/**
+ * @brief Enable APB1 peripherals clock.
+ * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR TIM18EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR CANEN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR DAC2EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR DAC1EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM18 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART3
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_DAC2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_PWR
+ * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+ * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->APB1ENR, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Check if APB1 peripheral clock is enabled or not
+ * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR TIM18EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR CANEN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR DAC2EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR DAC1EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM18 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART3
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_DAC2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_PWR
+ * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+ * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval State of Periphs (1 or 0).
+*/
+__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+ return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
+}
+
+/**
+ * @brief Disable APB1 peripherals clock.
+ * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR TIM18EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR CANEN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR DAC2EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR DAC1EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM18 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART3
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_DAC2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_PWR
+ * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+ * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->APB1ENR, Periphs);
+}
+
+/**
+ * @brief Force APB1 peripherals reset.
+ * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR TIM18RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR CANRST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR DAC2RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR DAC1RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP1_PERIPH_ALL
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM18 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART3
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_DAC2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_PWR
+ * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+ * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
+{
+ SET_BIT(RCC->APB1RSTR, Periphs);
+}
+
+/**
+ * @brief Release APB1 peripherals reset.
+ * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR TIM18RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR CANRST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR DAC2RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR DAC1RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP1_PERIPH_ALL
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM18 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART3
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_DAC2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_PWR
+ * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+ * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->APB1RSTR, Periphs);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup BUS_LL_EF_APB2 APB2
+ * @{
+ */
+
+/**
+ * @brief Enable APB2 peripherals clock.
+ * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR TIM19EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR TIM20EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR HRTIM1EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR SDADC1EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR SDADC2EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR SDADC3EN LL_APB2_GRP1_EnableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM19 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SDADC1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SDADC2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SDADC3 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->APB2ENR, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Check if APB2 peripheral clock is enabled or not
+ * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR TIM19EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR TIM20EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR HRTIM1EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR SDADC1EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR SDADC2EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR SDADC3EN LL_APB2_GRP1_IsEnabledClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM19 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SDADC1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SDADC2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SDADC3 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval State of Periphs (1 or 0).
+*/
+__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+ return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
+}
+
+/**
+ * @brief Disable APB2 peripherals clock.
+ * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR TIM19EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR TIM20EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR HRTIM1EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR SDADC1EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR SDADC2EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR SDADC3EN LL_APB2_GRP1_DisableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM19 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SDADC1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SDADC2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SDADC3 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->APB2ENR, Periphs);
+}
+
+/**
+ * @brief Force APB2 peripherals reset.
+ * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR ADC1RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM19RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM20RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR HRTIM1RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR SDADC1RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR SDADC2RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR SDADC3RST LL_APB2_GRP1_ForceReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_ALL
+ * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM19 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SDADC1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SDADC2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SDADC3 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
+{
+ SET_BIT(RCC->APB2RSTR, Periphs);
+}
+
+/**
+ * @brief Release APB2 peripherals reset.
+ * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR ADC1RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR TIM19RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR TIM20RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR HRTIM1RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR SDADC1RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR SDADC2RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR SDADC3RST LL_APB2_GRP1_ReleaseReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_ALL
+ * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM19 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SDADC1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SDADC2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SDADC3 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->APB2RSTR, Periphs);
+}
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(RCC) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_LL_BUS_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_ll_comp.h b/Inc/stm32f3xx_ll_comp.h
new file mode 100644
index 0000000..02312e4
--- /dev/null
+++ b/Inc/stm32f3xx_ll_comp.h
@@ -0,0 +1,2277 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_comp.h
+ * @author MCD Application Team
+ * @brief Header file of COMP LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_LL_COMP_H
+#define __STM32F3xx_LL_COMP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx.h"
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+/* Note: Devices of STM32F3 serie embed 1 out of 2 different comparator IP. */
+/* - STM32F30x, STM32F31x, STM32F32x, STM32F33x, STM32F35x, STM32F39x: */
+/* COMP IP from 3 to 7 instances and other specific features */
+/* (comparator output blanking, ...) (refer to reference manual). */
+/* - STM32F37x: */
+/* COMP IP with 2 instances */
+/* This file contains the drivers of these COMP IP, located in 2 area */
+/* delimited by compilation switches. */
+
+#if defined(COMP_V1_3_0_0)
+
+#if defined (COMP1) || defined (COMP2) || defined (COMP3) || defined (COMP4) || defined (COMP5) || defined (COMP6) || defined (COMP7)
+
+/** @defgroup COMP_LL COMP
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup COMP_LL_Private_Constants COMP Private Constants
+ * @{
+ */
+
+/* COMP registers bits positions */
+#define LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS ((uint32_t)30U) /* Value equivalent to POSITION_VAL(COMPxOUT) */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup COMP_LL_ES_INIT COMP Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief Structure definition of some features of COMP instance.
+ */
+typedef struct
+{
+ uint32_t PowerMode; /*!< Set comparator operating mode to adjust power and speed.
+ This parameter can be a value of @ref COMP_LL_EC_POWERMODE
+
+ This feature can be modified afterwards using unitary function @ref LL_COMP_SetPowerMode(). */
+
+ uint32_t InputPlus; /*!< Set comparator input plus (non-inverting input).
+ This parameter can be a value of @ref COMP_LL_EC_INPUT_PLUS
+
+ This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputPlus(). */
+
+ uint32_t InputMinus; /*!< Set comparator input minus (inverting input).
+ This parameter can be a value of @ref COMP_LL_EC_INPUT_MINUS
+
+ This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputMinus(). */
+
+ uint32_t InputHysteresis; /*!< Set comparator hysteresis mode of the input minus.
+ This parameter can be a value of @ref COMP_LL_EC_INPUT_HYSTERESIS
+
+ This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputHysteresis(). */
+
+ uint32_t OutputSelection; /*!< Set comparator output selection.
+ This parameter can be a value of @ref COMP_LL_EC_OUTPUT_SELECTION
+
+ This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputSelection(). */
+
+ uint32_t OutputPolarity; /*!< Set comparator output polarity.
+ This parameter can be a value of @ref COMP_LL_EC_OUTPUT_POLARITY
+
+ This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputPolarity(). */
+
+ uint32_t OutputBlankingSource; /*!< Set comparator blanking source.
+ This parameter can be a value of @ref COMP_LL_EC_OUTPUT_BLANKING_SOURCE
+
+ This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputBlankingSource(). */
+
+} LL_COMP_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup COMP_LL_Exported_Constants COMP Exported Constants
+ * @{
+ */
+
+/** @defgroup COMP_LL_EC_COMMON_WINDOWMODE Comparator common modes - Window mode
+ * @{
+ */
+#define LL_COMP_WINDOWMODE_DISABLE ((uint32_t)0x00000000U) /*!< Window mode disable: Comparators 1 and 2 are independent */
+#if defined(COMP2_CSR_COMP2WNDWEN)
+#define LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP2_CSR_COMP2WNDWEN) /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */
+#endif
+#if defined(COMP4_CSR_COMP4WNDWEN)
+#define LL_COMP_WINDOWMODE_COMP3_INPUT_PLUS_COMMON (COMP4_CSR_COMP4WNDWEN) /*!< Window mode enable: Comparators instances pair COMP3 and COMP4 have their input plus connected together. The common input is COMP3 input plus (COMP4 input plus is no more accessible). */
+#endif
+#if defined(COMP6_CSR_COMP6WNDWEN)
+#define LL_COMP_WINDOWMODE_COMP5_INPUT_PLUS_COMMON (COMP6_CSR_COMP6WNDWEN) /*!< Window mode enable: Comparators instances pair COMP5 and COMP6 have their input plus connected together. The common input is COMP5 input plus (COMP6 input plus is no more accessible). */
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EC_POWERMODE Comparator modes - Power mode
+ * @{
+ */
+#define LL_COMP_POWERMODE_HIGHSPEED ((uint32_t)0x00000000U) /*!< COMP power mode to high speed */
+#if defined(COMP_CSR_COMPxMODE)
+#define LL_COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_COMPxMODE_0) /*!< COMP power mode to medium speed */
+#define LL_COMP_POWERMODE_LOWPOWER (COMP_CSR_COMPxMODE_1) /*!< COMP power mode to low power */
+#define LL_COMP_POWERMODE_ULTRALOWPOWER (COMP_CSR_COMPxMODE_1 | COMP_CSR_COMPxMODE_0) /*!< COMP power mode to ultra-low power */
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EC_INPUT_PLUS Comparator inputs - Input plus (input non-inverting) selection
+ * @{
+ */
+#if !defined(COMP_CSR_COMPxNONINSEL)
+#define LL_COMP_INPUT_PLUS_IO1 ((uint32_t)0x00000000U) /*!< Comparator input plus connected to IO1 (pin PA1 for COMP1, PA3 for COMP2 (except STM32F334xx: PA7), PB14 for COMP3, PB0 for COMP4, PD12 for COMP5, PD11 for COMP6, PA0 for COMP7) (COMP instance availability depends on the selected device) */
+#define LL_COMP_INPUT_PLUS_IO2 ((uint32_t)0x00000000U) /*!< Comparator input plus connected to IO2: Same as IO1 */
+#else
+#define LL_COMP_INPUT_PLUS_IO1 ((uint32_t)0x00000000U) /*!< Comparator input plus connected to IO1 (pin PA7 for COMP2, PB14 for COMP3, PB0 for COMP4, PD12 for COMP5, PD11 for COMP6, PA0 for COMP7) (COMP instance availability depends on the selected device) */
+#define LL_COMP_INPUT_PLUS_IO2 (COMP_CSR_COMPxNONINSEL) /*!< Comparator input plus connected to IO2 (pin PA3 for COMP2, PD14 for COMP3, PE7 for COMP4, PB13 for COMP5, PB11 for COMP6, PC1 for COMP7) (COMP instance availability depends on the selected device) */
+#endif
+#if defined(STM32F302xC) || defined(STM32F302xE) || defined(STM32F303xC) || defined(STM32F303xE) || defined(STM32F358xx) || defined(STM32F398xx)
+#define LL_COMP_INPUT_PLUS_DAC1_CH1_COMP1 (COMP_CSR_COMPxSW1) /*!< Comparator input plus connected to DAC1 channel 1 (DAC_OUT1), through dedicated switch (Note: this switch is solely intended to redirect signals onto high impedance input, such as COMP1 input plus (highly resistive switch)) (specific to COMP instance: COMP1) */
+
+/* Note: Comparator input plus specific to COMP instances, defined with */
+/* generic naming not taking into account COMP instance constraints. */
+/* Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_INPUT_PLUS_DAC1_CH1 LL_COMP_INPUT_PLUS_DAC1_CH1_COMP1 /*!< Comparator input plus connected to DAC1 channel 1 (DAC_OUT1), through dedicated switch. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+
+#elif defined(STM32F301x8) || defined(STM32F318xx) || defined(STM32F302x8)
+#define LL_COMP_INPUT_PLUS_DAC1_CH1_COMP2 (COMP_CSR_COMPxSW1) /*!< Comparator input plus connected to DAC1 channel 1 (DAC_OUT1), through dedicated switch (Note: this switch is solely intended to redirect signals onto high impedance input, such as COMP2 input plus (highly resistive switch)) (specific to COMP instance: COMP2) */
+
+/* Note: Comparator input plus specific to COMP instances, defined with */
+/* generic naming not taking into account COMP instance constraints. */
+/* Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_INPUT_PLUS_DAC1_CH1 LL_COMP_INPUT_PLUS_DAC1_CH1_COMP2 /*!< Comparator input plus connected to DAC1 channel 1 (DAC_OUT1), through dedicated switch. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EC_INPUT_MINUS Comparator inputs - Input minus (input inverting) selection
+ * @{
+ */
+#define LL_COMP_INPUT_MINUS_1_4VREFINT ((uint32_t)0x00000000U) /*!< Comparator input minus connected to 1/4 VrefInt */
+#define LL_COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_COMPxINSEL_0) /*!< Comparator input minus connected to 1/2 VrefInt */
+#define LL_COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_COMPxINSEL_1 ) /*!< Comparator input minus connected to 3/4 VrefInt */
+#define LL_COMP_INPUT_MINUS_VREFINT ( COMP_CSR_COMPxINSEL_1 | COMP_CSR_COMPxINSEL_0) /*!< Comparator input minus connected to VrefInt */
+#define LL_COMP_INPUT_MINUS_DAC1_CH1 (COMP_CSR_COMPxINSEL_2 ) /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1) */
+#if defined(STM32F301x8) || defined(STM32F318xx) || defined(STM32F302x8) || defined(STM32F302xC) || defined(STM32F302xE)
+/* This device has no comparator input minus DAC1_CH2 */
+#else
+#define LL_COMP_INPUT_MINUS_DAC1_CH2 (COMP_CSR_COMPxINSEL_2 | COMP_CSR_COMPxINSEL_0) /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2) */
+#endif
+#if defined(STM32F301x8) || defined(STM32F318xx) || defined(STM32F334x8)
+#define LL_COMP_INPUT_MINUS_IO1 (COMP_CSR_COMPxINSEL_2 | COMP_CSR_COMPxINSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PA2 for COMP2) */
+#else
+#define LL_COMP_INPUT_MINUS_IO1 (COMP_CSR_COMPxINSEL_2 | COMP_CSR_COMPxINSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PA0 for COMP1, pin PA2 for COMP2, PD15 for COMP3, PE8 for COMP4, PD13 for COMP5, PD10 for COMP6, PC0 for COMP7 (COMP instance availability depends on the selected device)) */
+#endif
+#define LL_COMP_INPUT_MINUS_IO2 (COMP_CSR_COMPxINSEL_2 | COMP_CSR_COMPxINSEL_1 | COMP_CSR_COMPxINSEL_0) /*!< Comparator input minus connected to IO2 (PB12 for COMP3, PB2 for COMP4, PB10 for COMP5, PB15 for COMP6 (COMP instance availability depends on the selected device)) */
+#if defined(STM32F301x8) || defined(STM32F318xx) || defined(STM32F334x8) || defined(STM32F302x8) || defined(STM32F303x8) || defined(STM32F328xx)
+/* This device has no comparator input minus IO3 */
+#else
+#define LL_COMP_INPUT_MINUS_IO3 (COMP_CSR_COMPxINSEL_2 | COMP_CSR_COMPxINSEL_0) /*!< Comparator input minus connected to IO3 (pin PA5 for COMP1/2/3/4/5/6/7 (COMP instance availability depends on the selected device)) */
+#endif
+#define LL_COMP_INPUT_MINUS_IO4 (COMP_CSR_COMPxINSEL_2 ) /*!< Comparator input minus connected to IO4 (pin PA4 for COMP1/2/3/4/5/6/7 (COMP instance availability depends on the selected device)) */
+#if defined(STM32F303x8) || defined(STM32F328xx) || defined(STM32F334x8)
+#define LL_COMP_INPUT_MINUS_DAC2_CH1 (COMP_CSR_COMPxINSEL_3 ) /*!< Comparator input minus connected to DAC2 channel 1 (DAC2_OUT1) */
+#else
+/* This device has no comparator input minus DAC2_CH1 */
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EC_INPUT_HYSTERESIS Comparator input - Hysteresis
+ * @{
+ */
+#define LL_COMP_HYSTERESIS_NONE ((uint32_t)0x00000000U) /*!< No hysteresis */
+#if defined(COMP_CSR_COMPxHYST)
+#define LL_COMP_HYSTERESIS_LOW ( COMP_CSR_COMPxHYST_0) /*!< Hysteresis level low (available only on devices: STM32F303xB/C, STM32F358xC) */
+#define LL_COMP_HYSTERESIS_MEDIUM (COMP_CSR_COMPxHYST_1 ) /*!< Hysteresis level medium (available only on devices: STM32F303xB/C, STM32F358xC) */
+#define LL_COMP_HYSTERESIS_HIGH (COMP_CSR_COMPxHYST_1 | COMP_CSR_COMPxHYST_0) /*!< Hysteresis level high (available only on devices: STM32F303xB/C, STM32F358xC) */
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EC_OUTPUT_SELECTION Comparator output - Output selection
+ * @{
+ */
+#define LL_COMP_OUTPUT_NONE ((uint32_t)0x00000000) /*!< COMP output is not connected to other peripherals (except GPIO and EXTI that are always connected to COMP output) (specific to COMP instance: COMP2) */
+#if defined(COMP_CSR_COMPxOUT)
+/* Note: Output redirection common to all COMP instances, all STM32F3 serie */
+/* devices. */
+#define LL_COMP_OUTPUT_TIM1_BKIN (COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM1 break input (BKIN) */
+#define LL_COMP_OUTPUT_TIM1_BKIN2 (COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM1 break input 2 (BKIN2) */
+
+#if defined(STM32F301x8) || defined(STM32F318xx)
+/* Note: Output redirection specific to COMP instance: COMP2 */
+#define LL_COMP_OUTPUT_TIM1_IC1_COMP2 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM1 input capture 1 (specific to COMP instance: COMP2) */
+#define LL_COMP_OUTPUT_TIM2_IC4_COMP2 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM1 input capture 4 (specific to COMP instance: COMP2) */
+#define LL_COMP_OUTPUT_TIM1_OCCLR_COMP2 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM1 OCREF clear (specific to COMP instance: COMP2) */
+#define LL_COMP_OUTPUT_TIM2_OCCLR_COMP2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM2 OCREF clear (specific to COMP instance: COMP2) */
+/* Note: Output redirection specific to COMP instance: COMP4 */
+#define LL_COMP_OUTPUT_TIM15_IC2_COMP4 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM15 input capture 1 (specific to COMP instance: COMP4) */
+#define LL_COMP_OUTPUT_TIM15_OCCLR_COMP4 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM15 OCREF clear (specific to COMP instance: COMP4) */
+/* Note: Output redirection specific to COMP instance: COMP6 */
+#define LL_COMP_OUTPUT_TIM2_IC2_COMP6 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM2 input capture 2 (specific to COMP instance: COMP6) */
+#define LL_COMP_OUTPUT_TIM2_OCCLR_COMP6 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM2 OCREF clear (specific to COMP instance: COMP6) */
+#define LL_COMP_OUTPUT_TIM16_IC1_COMP6 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM16 input capture 1 (specific to COMP instance: COMP6) */
+#define LL_COMP_OUTPUT_TIM16_OCCLR_COMP6 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM16 OCREF clear (specific to COMP instance: COMP6) */
+
+/* Note: Output redirection specific to COMP instances, defined with */
+/* generic naming not taking into account COMP instance constraints. */
+/* Refer to literal definitions above for COMP instance constraints. */
+/* Note: Some output redirections cannot have a generic naming, */
+/* due to literal value different depending on COMP instance. */
+/* (For exemple: LL_COMP_OUTPUT_TIM2_OCCLR_COMP2 and */
+/* LL_COMP_OUTPUT_TIM2_OCCLR_COMP6). */
+#define LL_COMP_OUTPUT_TIM1_IC1 LL_COMP_OUTPUT_TIM1_IC1_COMP2 /*!< COMP output connected to TIM1 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM1_OCCLR LL_COMP_OUTPUT_TIM1_OCCLR_COMP2 /*!< COMP output connected to TIM1 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM2_IC2 LL_COMP_OUTPUT_TIM2_IC2_COMP6 /*!< COMP output connected to TIM2 input capture 2. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM2_IC4 LL_COMP_OUTPUT_TIM2_IC4_COMP2 /*!< COMP output connected to TIM2 input capture 4. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM15_IC2 LL_COMP_OUTPUT_TIM15_IC2_COMP4 /*!< COMP output connected to TIM15 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM15_OCCLR LL_COMP_OUTPUT_TIM15_OCCLR_COMP4 /*!< COMP output connected to TIM15 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM16_IC1 LL_COMP_OUTPUT_TIM16_IC1_COMP6 /*!< COMP output connected to TIM16 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM16_OCCLR LL_COMP_OUTPUT_TIM16_OCCLR_COMP6 /*!< COMP output connected to TIM16 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+/* Note: Output redirection specific to COMP instances, defined with */
+/* partially generic naming grouping COMP instance constraints. */
+/* Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3 LL_COMP_OUTPUT_TIM2_OCCLR_COMP2 /*!< COMP output connected to TIM2 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+
+#elif defined(STM32F303x8) || defined(STM32F328xx) || defined(STM32F334x8)|| defined(STM32F302x8)
+/* Note: Output redirection specific to COMP instance: COMP2, COMP4 */
+#define LL_COMP_OUTPUT_TIM3_OCCLR_COMP2_4 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM3 OCREF clear (specific to COMP instance: COMP2, COMP4) */
+/* Note: Output redirection specific to COMP instance: COMP2 */
+#define LL_COMP_OUTPUT_TIM1_IC1_COMP2 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM1 input capture 1 (specific to COMP instance: COMP2) */
+#define LL_COMP_OUTPUT_TIM2_IC4_COMP2 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM1 input capture 4 (specific to COMP instance: COMP2) */
+#define LL_COMP_OUTPUT_TIM1_OCCLR_COMP2 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM1 OCREF clear (specific to COMP instance: COMP2) */
+#define LL_COMP_OUTPUT_TIM2_OCCLR_COMP2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM2 OCREF clear (specific to COMP instance: COMP2) */
+#define LL_COMP_OUTPUT_TIM3_IC1_COMP2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM3 input capture 1 (specific to COMP instance: COMP2) */
+/* Note: Output redirection specific to COMP instance: COMP4 */
+#define LL_COMP_OUTPUT_TIM3_IC3_COMP4 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM3 input capture 3 (specific to COMP instance: COMP4) */
+#define LL_COMP_OUTPUT_TIM15_IC2_COMP4 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM15 input capture 1 (specific to COMP instance: COMP4) */
+#define LL_COMP_OUTPUT_TIM15_OCCLR_COMP4 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM15 OCREF clear (specific to COMP instance: COMP4) */
+/* Note: Output redirection specific to COMP instance: COMP6 */
+#define LL_COMP_OUTPUT_TIM2_IC2_COMP6 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM2 input capture 2 (specific to COMP instance: COMP6) */
+#define LL_COMP_OUTPUT_TIM2_OCCLR_COMP6 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM2 OCREF clear (specific to COMP instance: COMP6) */
+#define LL_COMP_OUTPUT_TIM16_IC1_COMP6 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM16 input capture 1 (specific to COMP instance: COMP6) */
+#define LL_COMP_OUTPUT_TIM16_OCCLR_COMP6 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM16 OCREF clear (specific to COMP instance: COMP6) */
+
+/* Note: Output redirection specific to COMP instances, defined with */
+/* generic naming not taking into account COMP instance constraints. */
+/* Refer to literal definitions above for COMP instance constraints. */
+/* Note: Some output redirections cannot have a generic naming, */
+/* due to literal value different depending on COMP instance. */
+/* (For exemple: LL_COMP_OUTPUT_TIM2_OCCLR_COMP2 and */
+/* LL_COMP_OUTPUT_TIM2_OCCLR_COMP6). */
+#define LL_COMP_OUTPUT_TIM1_IC1 LL_COMP_OUTPUT_TIM1_IC1_COMP2 /*!< COMP output connected to TIM1 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM1_OCCLR LL_COMP_OUTPUT_TIM1_OCCLR_COMP2 /*!< COMP output connected to TIM1 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM2_IC2 LL_COMP_OUTPUT_TIM2_IC2_COMP6 /*!< COMP output connected to TIM2 input capture 2. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM2_IC4 LL_COMP_OUTPUT_TIM2_IC4_COMP2 /*!< COMP output connected to TIM2 input capture 4. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM3_IC1 LL_COMP_OUTPUT_TIM3_IC1_COMP2 /*!< COMP output connected to TIM3 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM3_IC3 LL_COMP_OUTPUT_TIM3_IC3_COMP4 /*!< COMP output connected to TIM3 input capture 3. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM3_OCCLR LL_COMP_OUTPUT_TIM3_OCCLR_COMP2_4 /*!< COMP output connected to TIM3 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM15_IC2 LL_COMP_OUTPUT_TIM15_IC2_COMP4 /*!< COMP output connected to TIM15 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM15_OCCLR LL_COMP_OUTPUT_TIM15_OCCLR_COMP4 /*!< COMP output connected to TIM15 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM16_IC1 LL_COMP_OUTPUT_TIM16_IC1_COMP6 /*!< COMP output connected to TIM16 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM16_OCCLR LL_COMP_OUTPUT_TIM16_OCCLR_COMP6 /*!< COMP output connected to TIM16 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+/* Note: Output redirection specific to COMP instances, defined with */
+/* partially generic naming grouping COMP instance constraints. */
+/* Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3 LL_COMP_OUTPUT_TIM2_OCCLR_COMP2 /*!< COMP output connected to TIM2 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+
+#elif defined(STM32F302xC) || defined(STM32F302xE)
+/* Note: Output redirection specific to COMP instance: COMP1, COMP2, COMP4 */
+#define LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM3 OCREF clear (specific to COMP instance: COMP2, COMP4) */
+/* Note: Output redirection specific to COMP instance: COMP1, COMP2 */
+#define LL_COMP_OUTPUT_TIM1_IC1_COMP1_2 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM1 input capture 1 (specific to COMP instance: COMP2) */
+#define LL_COMP_OUTPUT_TIM2_IC4_COMP1_2 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM2 input capture 4 (specific to COMP instance: COMP2) */
+#define LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM1 OCREF clear (specific to COMP instance: COMP2) */
+#define LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM2 OCREF clear (specific to COMP instance: COMP2) */
+#define LL_COMP_OUTPUT_TIM3_IC1_COMP1_2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM3 input capture 1 (specific to COMP instance: COMP2) */
+/* Note: Output redirection specific to COMP instance: COMP4 */
+#define LL_COMP_OUTPUT_TIM3_IC3_COMP4 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM3 input capture 3 (specific to COMP instance: COMP4) */
+#define LL_COMP_OUTPUT_TIM4_IC2_COMP4 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM4 input capture 2 (specific to COMP instance: COMP4) */
+#define LL_COMP_OUTPUT_TIM15_IC2_COMP4 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM15 input capture 1 (specific to COMP instance: COMP4) */
+#define LL_COMP_OUTPUT_TIM15_OCCLR_COMP4 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM15 OCREF clear (specific to COMP instance: COMP4) */
+/* Note: Output redirection specific to COMP instance: COMP6 */
+#define LL_COMP_OUTPUT_TIM2_IC2_COMP6 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM2 input capture 2 (specific to COMP instance: COMP6) */
+#define LL_COMP_OUTPUT_TIM2_OCCLR_COMP6 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM2 OCREF clear (specific to COMP instance: COMP6) */
+#define LL_COMP_OUTPUT_TIM4_IC4_COMP6 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM4 input capture 4 (specific to COMP instance: COMP6) */
+#define LL_COMP_OUTPUT_TIM16_IC1_COMP6 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM16 input capture 1 (specific to COMP instance: COMP6) */
+#define LL_COMP_OUTPUT_TIM16_OCCLR_COMP6 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM16 OCREF clear (specific to COMP instance: COMP6) */
+
+/* Note: Output redirection specific to COMP instances, defined with */
+/* generic naming not taking into account COMP instance constraints. */
+/* Refer to literal definitions above for COMP instance constraints. */
+/* Note: Some output redirections cannot have a generic naming, */
+/* due to literal value different depending on COMP instance. */
+/* (For exemple: LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2 and */
+/* LL_COMP_OUTPUT_TIM2_OCCLR_COMP6). */
+#define LL_COMP_OUTPUT_TIM1_IC1 LL_COMP_OUTPUT_TIM1_IC1_COMP1_2 /*!< COMP output connected to TIM1 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM1_OCCLR LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2 /*!< COMP output connected to TIM1 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM2_IC2 LL_COMP_OUTPUT_TIM2_IC2_COMP6 /*!< COMP output connected to TIM2 input capture 2. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM2_IC4 LL_COMP_OUTPUT_TIM2_IC4_COMP1_2 /*!< COMP output connected to TIM2 input capture 4. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM3_IC1 LL_COMP_OUTPUT_TIM3_IC1_COMP1_2 /*!< COMP output connected to TIM3 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM3_IC3 LL_COMP_OUTPUT_TIM3_IC3_COMP4 /*!< COMP output connected to TIM3 input capture 3. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM3_OCCLR LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4 /*!< COMP output connected to TIM3 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM4_IC2 LL_COMP_OUTPUT_TIM4_IC2_COMP4 /*!< COMP output connected to TIM4 input capture 2. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM4_IC4 LL_COMP_OUTPUT_TIM4_IC4_COMP6 /*!< COMP output connected to TIM4 input capture 4. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM15_IC2 LL_COMP_OUTPUT_TIM15_IC2_COMP4 /*!< COMP output connected to TIM15 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM15_OCCLR LL_COMP_OUTPUT_TIM15_OCCLR_COMP4 /*!< COMP output connected to TIM15 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM16_IC1 LL_COMP_OUTPUT_TIM16_IC1_COMP6 /*!< COMP output connected to TIM16 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM16_OCCLR LL_COMP_OUTPUT_TIM16_OCCLR_COMP6 /*!< COMP output connected to TIM16 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+/* Note: Output redirection specific to COMP instances, defined with */
+/* partially generic naming grouping COMP instance constraints. */
+/* Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3 LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2 /*!< COMP output connected to TIM2 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+
+#elif defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F303xE) || defined(STM32F398xx)
+/* Note: Output redirection common to all COMP instances */
+#define LL_COMP_OUTPUT_TIM8_BKIN (COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM8 break input (BKIN) */
+#define LL_COMP_OUTPUT_TIM8_BKIN2 (COMP_CSR_COMPxOUTSEL_2) /*!< COMP output connected to TIM8 break input 2 (BKIN2) */
+#define LL_COMP_OUTPUT_TIM1_TIM8_BKIN2 (COMP_CSR_COMPxOUTSEL_2| COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM1 break input 2 and TIM8 break input 2 (BKIN2) */
+#if defined(STM32F303xE) || defined(STM32F398xx)
+#define LL_COMP_OUTPUT_TIM20_BKIN (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_2) /*!< COMP output connected to TIM8 break input (BKIN) */
+#define LL_COMP_OUTPUT_TIM20_BKIN2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM8 break input 2 (BKIN2) */
+#define LL_COMP_OUTPUT_TIM1_TIM8_TIM20_BKIN2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_2| COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM1 break input 2, TIM8 break input 2 and TIM20 break input 2 (BKIN2) */
+#endif
+/* Note: Output redirection specific to COMP instance: COMP1, COMP2, COMP3, COMP7 */
+#define LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2_3_7 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM1 OCREF clear (specific to COMP instance: COMP1, COMP2, COMP3, COMP7) */
+/* Note: Output redirection specific to COMP instance: COMP1, COMP2, COMP3 */
+#define LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM2 OCREF clear (specific to COMP instance: COMP1, COMP2, COMP3) */
+/* Note: Output redirection specific to COMP instance: COMP1, COMP2, COMP4, COMP5 */
+#define LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4_5 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM3 OCREF clear (specific to COMP instance: COMP1, COMP2, COMP4, COMP5) */
+/* Note: Output redirection specific to COMP instance: COMP4, COMP5, COMP6, COMP7 */
+#define LL_COMP_OUTPUT_TIM8_OCCLR_COMP4_5_6_7 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM8 OCREF clear (specific to COMP instance: COMP4, COMP5, COMP6, COMP7) */
+/* Note: Output redirection specific to COMP instance: COMP1, COMP2 */
+#define LL_COMP_OUTPUT_TIM1_IC1_COMP1_2 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM1 input capture 1 (specific to COMP instance: COMP2) */
+#define LL_COMP_OUTPUT_TIM2_IC4_COMP1_2 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM2 input capture 4 (specific to COMP instance: COMP2) */
+#define LL_COMP_OUTPUT_TIM3_IC1_COMP1_2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM3 input capture 1 (specific to COMP instance: COMP2) */
+#if defined(STM32F303xE) || defined(STM32F398xx)
+#define LL_COMP_OUTPUT_TIM20_OCCLR_COMP2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM20 OCREF clear (specific to COMP instance: COMP2) */
+#endif
+/* Note: Output redirection specific to COMP instance: COMP3 */
+#define LL_COMP_OUTPUT_TIM3_IC2_COMP3 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM3 input capture 2 (specific to COMP instance: COMP3) */
+#define LL_COMP_OUTPUT_TIM4_IC1_COMP3 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM4 input capture 1 (specific to COMP instance: COMP3) */
+#define LL_COMP_OUTPUT_TIM15_IC1_COMP3 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM15 input capture 1 (specific to COMP instance: COMP3) */
+#define LL_COMP_OUTPUT_TIM15_BKIN_COMP3 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM15 break input (BKIN) */
+/* Note: Output redirection specific to COMP instance: COMP4 */
+#define LL_COMP_OUTPUT_TIM3_IC3_COMP4 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM3 input capture 3 (specific to COMP instance: COMP4) */
+#define LL_COMP_OUTPUT_TIM4_IC2_COMP4 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM4 input capture 2 (specific to COMP instance: COMP4) */
+#define LL_COMP_OUTPUT_TIM15_IC2_COMP4 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM15 input capture 1 (specific to COMP instance: COMP4) */
+#define LL_COMP_OUTPUT_TIM15_OCCLR_COMP4 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM15 OCREF clear (specific to COMP instance: COMP4) */
+/* Note: Output redirection specific to COMP instance: COMP5 */
+#define LL_COMP_OUTPUT_TIM2_IC1_COMP5 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM2 input capture 1 (specific to COMP instance: COMP5) */
+#define LL_COMP_OUTPUT_TIM4_IC3_COMP5 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM4 input capture 3 (specific to COMP instance: COMP5) */
+#define LL_COMP_OUTPUT_TIM17_IC1_COMP5 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM17 input capture 1 (specific to COMP instance: COMP5) */
+#define LL_COMP_OUTPUT_TIM16_BKIN_COMP5 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM16 break input (BKIN) */
+/* Note: Output redirection specific to COMP instance: COMP6 */
+#define LL_COMP_OUTPUT_TIM2_IC2_COMP6 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM2 input capture 2 (specific to COMP instance: COMP6) */
+#define LL_COMP_OUTPUT_TIM2_OCCLR_COMP6 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM2 OCREF clear (specific to COMP instance: COMP6) */
+#define LL_COMP_OUTPUT_TIM4_IC4_COMP6 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM4 input capture 4 (specific to COMP instance: COMP6) */
+#define LL_COMP_OUTPUT_TIM16_IC1_COMP6 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM16 input capture 1 (specific to COMP instance: COMP6) */
+#define LL_COMP_OUTPUT_TIM16_OCCLR_COMP6 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM16 OCREF clear (specific to COMP instance: COMP6) */
+/* Note: Output redirection specific to COMP instance: COMP7 */
+#define LL_COMP_OUTPUT_TIM1_IC2_COMP7 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM2 input capture 1 (specific to COMP instance: COMP7) */
+#define LL_COMP_OUTPUT_TIM2_IC3_COMP7 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM4 input capture 3 (specific to COMP instance: COMP7) */
+#define LL_COMP_OUTPUT_TIM17_OCCLR_COMP7 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM17 OCREF clear (specific to COMP instance: COMP7) */
+#define LL_COMP_OUTPUT_TIM17_BKIN_COMP7 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM17 break input (BKIN) */
+
+/* Note: Output redirection specific to COMP instances, defined with */
+/* generic naming not taking into account COMP instance constraints. */
+/* Refer to literal definitions above for COMP instance constraints. */
+/* Note: Some output redirections cannot have a generic naming, */
+/* due to literal value different depending on COMP instance. */
+/* (For exemple: LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3 and */
+/* LL_COMP_OUTPUT_TIM2_OCCLR_COMP6). */
+#define LL_COMP_OUTPUT_TIM1_IC1 LL_COMP_OUTPUT_TIM1_IC1_COMP1_2 /*!< COMP output connected to TIM1 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM1_IC2 LL_COMP_OUTPUT_TIM1_IC2_COMP7 /*!< COMP output connected to TIM2 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM1_OCCLR LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2_3_7 /*!< COMP output connected to TIM1 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM2_IC1 LL_COMP_OUTPUT_TIM2_IC1_COMP5 /*!< COMP output connected to TIM2 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM2_IC2 LL_COMP_OUTPUT_TIM2_IC2_COMP6 /*!< COMP output connected to TIM2 input capture 2. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM2_IC3 LL_COMP_OUTPUT_TIM2_IC3_COMP7 /*!< COMP output connected to TIM4 input capture 3. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM2_IC4 LL_COMP_OUTPUT_TIM2_IC4_COMP1_2 /*!< COMP output connected to TIM2 input capture 4. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM3_IC1 LL_COMP_OUTPUT_TIM3_IC1_COMP1_2 /*!< COMP output connected to TIM3 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM3_IC2 LL_COMP_OUTPUT_TIM3_IC2_COMP3 /*!< COMP output connected to TIM3 input capture 2. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM3_IC3 LL_COMP_OUTPUT_TIM3_IC3_COMP4 /*!< COMP output connected to TIM3 input capture 3. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM3_OCCLR LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4_5 /*!< COMP output connected to TIM3 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM4_IC1 LL_COMP_OUTPUT_TIM4_IC1_COMP3 /*!< COMP output connected to TIM4 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM4_IC2 LL_COMP_OUTPUT_TIM4_IC2_COMP4 /*!< COMP output connected to TIM4 input capture 2. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM4_IC3 LL_COMP_OUTPUT_TIM4_IC3_COMP5 /*!< COMP output connected to TIM4 input capture 3. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM4_IC4 LL_COMP_OUTPUT_TIM4_IC4_COMP6 /*!< COMP output connected to TIM4 input capture 4. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM8_OCCLR LL_COMP_OUTPUT_TIM8_OCCLR_COMP4_5_6_7 /*!< COMP output connected to TIM8 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM15_IC1 LL_COMP_OUTPUT_TIM15_IC1_COMP3 /*!< COMP output connected to TIM15 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM15_IC2 LL_COMP_OUTPUT_TIM15_IC2_COMP4 /*!< COMP output connected to TIM15 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM15_BKIN LL_COMP_OUTPUT_TIM15_BKIN_COMP3 /*!< COMP output connected to TIM15 break input (BKIN). Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM15_OCCLR LL_COMP_OUTPUT_TIM15_OCCLR_COMP4 /*!< COMP output connected to TIM15 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM16_IC1 LL_COMP_OUTPUT_TIM16_IC1_COMP6 /*!< COMP output connected to TIM16 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM16_BKIN LL_COMP_OUTPUT_TIM16_BKIN_COMP5 /*!< COMP output connected to TIM16 break input (BKIN). Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM16_OCCLR LL_COMP_OUTPUT_TIM16_OCCLR_COMP6 /*!< COMP output connected to TIM16 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM17_IC1 LL_COMP_OUTPUT_TIM17_IC1_COMP5 /*!< COMP output connected to TIM17 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM17_BKIN LL_COMP_OUTPUT_TIM17_BKIN_COMP7 /*!< COMP output connected to TIM17 break input (BKIN). Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM17_OCCLR LL_COMP_OUTPUT_TIM17_OCCLR_COMP7 /*!< COMP output connected to TIM17 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#if defined(STM32F303xE) || defined(STM32F398xx)
+#define LL_COMP_OUTPUT_TIM20_OCCLR LL_COMP_OUTPUT_TIM20_OCCLR_COMP2 /*!< COMP output connected to TIM20 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#endif
+
+#endif
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EC_OUTPUT_POLARITY Comparator output - Output polarity
+ * @{
+ */
+#define LL_COMP_OUTPUTPOL_NONINVERTED ((uint32_t)0x00000000U) /*!< COMP output polarity is not inverted: comparator output is high when the plus (non-inverting) input is at a higher voltage than the minus (inverting) input */
+#define LL_COMP_OUTPUTPOL_INVERTED (COMP_CSR_COMPxPOL) /*!< COMP output polarity is inverted: comparator output is low when the plus (non-inverting) input is at a lower voltage than the minus (inverting) input */
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EC_OUTPUT_BLANKING_SOURCE Comparator output - Blanking source
+ * @{
+ */
+#define LL_COMP_BLANKINGSRC_NONE ((uint32_t)0x00000000U) /*!<Comparator output without blanking */
+#if defined(COMP_CSR_COMPxBLANKING)
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+/* Note: Output blanking source specific to COMP instance: COMP2 */
+#define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2 (COMP_CSR_COMPxBLANKING_0) /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP2) */
+#define LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2 (COMP_CSR_COMPxBLANKING_1) /*!< Comparator output blanking source TIM2 OC3 (specific to COMP instance: COMP2) */
+#define LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2 (COMP_CSR_COMPxBLANKING_1 | COMP_CSR_COMPxBLANKING_0) /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP2) */
+/* Note: Output blanking source specific to COMP instance: COMP4 */
+#define LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4 (COMP_CSR_COMPxBLANKING_0) /*!< Comparator output blanking source TIM3 OC4 (specific to COMP instance: COMP4) */
+#define LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4 (COMP_CSR_COMPxBLANKING_0 | COMP_CSR_COMPxBLANKING_1) /*!< Comparator output blanking source TIM15 OC1 (specific to COMP instance: COMP4) */
+/* Note: Output blanking source specific to COMP instance: COMP6 */
+#define LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6 (COMP_CSR_COMPxBLANKING_0 | COMP_CSR_COMPxBLANKING_1) /*!< Comparator output blanking source TIM2 OC4 (specific to COMP instance: COMP6) */
+#define LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6 (COMP_CSR_COMPxBLANKING_0) /*!< Comparator output blanking source TIM15 OC2 (specific to COMP instance: COMP6) */
+
+/* Note: Output blanking source specific to COMP instances, defined with */
+/* generic naming not taking into account COMP instance constraints. */
+/* Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_BLANKINGSRC_TIM1_OC5 LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2 /*!< Comparator output blanking source TIM1 OC5. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_BLANKINGSRC_TIM2_OC3 LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2 /*!< Comparator output blanking source TIM2 OC3. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_BLANKINGSRC_TIM2_OC4 LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6 /*!< Comparator output blanking source TIM2 OC4. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_BLANKINGSRC_TIM3_OC3 LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2 /*!< Comparator output blanking source TIM3 OC3. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_BLANKINGSRC_TIM3_OC4 LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4 /*!< Comparator output blanking source TIM3 OC4. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_BLANKINGSRC_TIM15_OC1 LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4 /*!< Comparator output blanking source TIM15 OC1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_BLANKINGSRC_TIM15_OC2 LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6 /*!< Comparator output blanking source TIM15 OC2. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+
+#elif defined(STM32F302xE) || defined(STM32F302xC)
+/* Note: Output blanking source specific to COMP instance: COMP1, COMP2 */
+#define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1_2 (COMP_CSR_COMPxBLANKING_0) /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP1, COMP2) */
+#define LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1_2 (COMP_CSR_COMPxBLANKING_1) /*!< Comparator output blanking source TIM2 OC3 (specific to COMP instance: COMP1, COMP2) */
+#define LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1_2 (COMP_CSR_COMPxBLANKING_1 | COMP_CSR_COMPxBLANKING_0) /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP1, COMP2) */
+/* Note: Output blanking source specific to COMP instance: COMP4 */
+#define LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4 (COMP_CSR_COMPxBLANKING_0) /*!< Comparator output blanking source TIM3 OC4 (specific to COMP instance: COMP4) */
+#define LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4 (COMP_CSR_COMPxBLANKING_0 | COMP_CSR_COMPxBLANKING_1) /*!< Comparator output blanking source TIM15 OC1 (specific to COMP instance: COMP4) */
+/* Note: Output blanking source specific to COMP instance: COMP6 */
+#define LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6 (COMP_CSR_COMPxBLANKING_0 | COMP_CSR_COMPxBLANKING_1) /*!< Comparator output blanking source TIM2 OC4 (specific to COMP instance: COMP6) */
+#define LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6 (COMP_CSR_COMPxBLANKING_0) /*!< Comparator output blanking source TIM15 OC2 (specific to COMP instance: COMP6) */
+
+/* Note: Output blanking source specific to COMP instances, defined with */
+/* generic naming not taking into account COMP instance constraints. */
+/* Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_BLANKINGSRC_TIM1_OC5 LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1_2 /*!< Comparator output blanking source TIM1 OC5. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_BLANKINGSRC_TIM2_OC3 LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1_2 /*!< Comparator output blanking source TIM2 OC3. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_BLANKINGSRC_TIM2_OC4 LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6 /*!< Comparator output blanking source TIM2 OC4. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_BLANKINGSRC_TIM3_OC3 LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1_2 /*!< Comparator output blanking source TIM3 OC3. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_BLANKINGSRC_TIM3_OC4 LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4 /*!< Comparator output blanking source TIM3 OC4. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_BLANKINGSRC_TIM15_OC1 LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4 /*!< Comparator output blanking source TIM15 OC1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_BLANKINGSRC_TIM15_OC2 LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6 /*!< Comparator output blanking source TIM15 OC2. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+
+#elif defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
+/* Note: Output blanking source specific to COMP instance: COMP1, COMP2, COMP7 */
+#define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1_2_7 (COMP_CSR_COMPxBLANKING_0) /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP1, COMP2, COMP7) */
+/* Note: Output blanking source specific to COMP instance: COMP1, COMP2 */
+#define LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1_2 (COMP_CSR_COMPxBLANKING_1) /*!< Comparator output blanking source TIM2 OC3 (specific to COMP instance: COMP1, COMP2) */
+#define LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1_2 (COMP_CSR_COMPxBLANKING_1 | COMP_CSR_COMPxBLANKING_0) /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP1, COMP2) */
+/* Note: Output blanking source specific to COMP instance: COMP3, COMP6 */
+#define LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3_6 (COMP_CSR_COMPxBLANKING_1 | COMP_CSR_COMPxBLANKING_0) /*!< Comparator output blanking source TIM2 OC4 (specific to COMP instance: COMP3, COMP6) */
+/* Note: Output blanking source specific to COMP instance: COMP4, COMP5, COMP6, COMP7 */
+#define LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4_5_6_7 (COMP_CSR_COMPxBLANKING_1) /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP4, COMP5, COMP6, COMP7) */
+/* Note: Output blanling source specific to COMP instance: COMP6, COMP7 */
+#define LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6_7 (COMP_CSR_COMPxBLANKING_2) /*!< Comparator output blanking source TIM15 OC2 (specific to COMP instance: COMP6, COMP7) */
+/* Note: Output blanking source specific to COMP instance: COMP4 */
+#define LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4 (COMP_CSR_COMPxBLANKING_0) /*!< Comparator output blanking source TIM3 OC4 (specific to COMP instance: COMP4) */
+#define LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4 (COMP_CSR_COMPxBLANKING_1 | COMP_CSR_COMPxBLANKING_0) /*!< Comparator output blanking source TIM15 OC1 (specific to COMP instance: COMP4) */
+
+/* Note: Output blanking source specific to COMP instances, defined with */
+/* generic naming not taking into account COMP instance constraints. */
+/* Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_BLANKINGSRC_TIM1_OC5 LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1_2_7 /*!< Comparator output blanking source TIM1 OC5. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_BLANKINGSRC_TIM2_OC3 LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1_2 /*!< Comparator output blanking source TIM2 OC3. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_BLANKINGSRC_TIM2_OC4 LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3_6 /*!< Comparator output blanking source TIM2 OC4. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_BLANKINGSRC_TIM3_OC3 LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1_2 /*!< Comparator output blanking source TIM3 OC3. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_BLANKINGSRC_TIM3_OC4 LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4 /*!< Comparator output blanking source TIM3 OC4. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_BLANKINGSRC_TIM8_OC5 LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4_5_6_7 /*!< Comparator output blanking source TIM8 OC5. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_BLANKINGSRC_TIM15_OC1 LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4 /*!< Comparator output blanking source TIM15 OC1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_BLANKINGSRC_TIM15_OC2 LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6_7 /*!< Comparator output blanking source TIM15 OC2. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+
+#endif
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EC_OUTPUT_LEVEL Comparator output - Output level
+ * @{
+ */
+#define LL_COMP_OUTPUT_LEVEL_LOW ((uint32_t)0x00000000U) /*!< Comparator output level low (if the polarity is not inverted, otherwise to be complemented) */
+#define LL_COMP_OUTPUT_LEVEL_HIGH ((uint32_t)0x00000001U) /*!< Comparator output level high (if the polarity is not inverted, otherwise to be complemented) */
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EC_HW_DELAYS Definitions of COMP hardware constraints delays
+ * @note Only COMP IP HW delays are defined in COMP LL driver driver,
+ * not timeout values.
+ * For details on delays values, refer to descriptions in source code
+ * above each literal definition.
+ * @{
+ */
+
+/* Delay for comparator startup time. */
+/* Note: Delay required to reach propagation delay specification. */
+/* Literal set to maximum value (refer to device datasheet, */
+/* parameter "tSTART"). */
+/* Unit: us */
+#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+#define LL_COMP_DELAY_STARTUP_US ((uint32_t) 60U) /*!< Delay for COMP startup time */
+#else
+#define LL_COMP_DELAY_STARTUP_US ((uint32_t) 10U) /*!< Delay for COMP startup time */
+#endif
+
+/* Delay for comparator voltage scaler stabilization time. */
+/* Note: Voltage scaler is used when selecting comparator input */
+/* based on VrefInt: VrefInt or subdivision of VrefInt. */
+/* Literal set to maximum value (refer to device datasheet, */
+/* parameter "tS_SC"). */
+/* Unit: us */
+#define LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US ((uint32_t) 200U) /*!< Delay for COMP voltage scaler stabilization time */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup COMP_LL_Exported_Macros COMP Exported Macros
+ * @{
+ */
+/** @defgroup COMP_LL_EM_WRITE_READ Common write and read registers macro
+ * @{
+ */
+
+/**
+ * @brief Write a value in COMP register
+ * @param __INSTANCE__ comparator instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_COMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in COMP register
+ * @param __INSTANCE__ comparator instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_COMP_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EM_HELPER_MACRO COMP helper macro
+ * @{
+ */
+
+/**
+ * @brief Helper macro to select the COMP common instance
+ * to which is belonging the selected COMP instance.
+ * @note COMP common register instance can be used to
+ * set parameters common to several COMP instances.
+ * Refer to functions having argument "COMPxy_COMMON" as parameter.
+ * @param __COMPx__ COMP instance
+ * @retval COMP common instance or value "0" if there is no COMP common instance.
+ */
+#if defined(COMP1) && defined(COMP2) && defined(COMP3) && defined(COMP4) && defined(COMP5) && defined(COMP6) && defined(COMP7)
+/* Note: On STM32F3 serie devices with 7 comparator instances, */
+/* COMP instance COMP7 has no other comparator instance to work */
+/* in pair with: window mode is not available for COMP7. */
+#define __LL_COMP_COMMON_INSTANCE(__COMPx__) \
+ ((((__COMPx__) == COMP1) || ((__COMPx__) == COMP2)) \
+ ? ( \
+ (COMP12_COMMON) \
+ ) \
+ : \
+ ((((__COMPx__) == COMP3) || ((__COMPx__) == COMP4)) \
+ ? ( \
+ (COMP34_COMMON) \
+ ) \
+ : \
+ ((((__COMPx__) == COMP5) || ((__COMPx__) == COMP6)) \
+ ? ( \
+ (COMP56_COMMON) \
+ ) \
+ : \
+ ( \
+ ((uint32_t)0U) \
+ ) \
+ ) \
+ ) \
+ )
+#elif defined(COMP1) && defined(COMP2) && defined(COMP4) && defined(COMP6)
+#define __LL_COMP_COMMON_INSTANCE(__COMPx__) \
+ ((((__COMPx__) == COMP1) || ((__COMPx__) == COMP2)) \
+ ? ( \
+ (COMP12_COMMON) \
+ ) \
+ : \
+ ( \
+ ((uint32_t)0U) \
+ ) \
+ )
+#elif defined(COMP2) && defined(COMP4) && defined(COMP6)
+/* Note: On STM32F3 serie devices with 3 comparator instances (COMP2, 4, 6) */
+/* COMP instances have no other comparator instance to work */
+/* in pair with: window mode is not available for all COMP instances. */
+#define __LL_COMP_COMMON_INSTANCE(__COMPx__) \
+ ((uint32_t)0U)
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup COMP_LL_Exported_Functions COMP Exported Functions
+ * @{
+ */
+
+/** @defgroup COMP_LL_EF_Configuration_comparator_common Configuration of COMP hierarchical scope: common to several COMP instances
+ * @{
+ */
+
+/**
+ * @brief Set window mode of a pair of comparators instances
+ * (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).
+ * @rmtoll CSR COMPxWNDWEN LL_COMP_SetCommonWindowMode
+ * @param COMPxy_COMMON Comparator common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() )
+ * @param WindowMode This parameter can be one of the following values:
+ * @arg @ref LL_COMP_WINDOWMODE_DISABLE
+ * @arg @ref LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (1)
+ * @arg @ref LL_COMP_WINDOWMODE_COMP3_INPUT_PLUS_COMMON (2)
+ * @arg @ref LL_COMP_WINDOWMODE_COMP5_INPUT_PLUS_COMMON (2)
+ *
+ * (1) Parameter available on devices: STM32F302xB/C, STM32F303xB/C, STM32F358xC
+ * (2) Parameter available on devices: STM32F303xB/C, STM32F358xC
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_SetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowMode)
+{
+#if defined(COMP_CSR_COMPxWNDWEN)
+ MODIFY_REG(COMPxy_COMMON->CSR, COMP_CSR_COMPxWNDWEN, WindowMode);
+#else
+ /* Device without pair of comparator working in window mode */
+ /* No update of comparator register (corresponds to setting */
+ /* "LL_COMP_WINDOWMODE_DISABLE"). */
+#endif
+}
+
+/**
+ * @brief Get window mode of a pair of comparators instances
+ * (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).
+ * @rmtoll CSR COMPxWNDWEN LL_COMP_GetCommonWindowMode
+ * @param COMPxy_COMMON Comparator common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() )
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_COMP_WINDOWMODE_DISABLE
+ * @arg @ref LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (1)
+ * @arg @ref LL_COMP_WINDOWMODE_COMP3_INPUT_PLUS_COMMON (2)
+ * @arg @ref LL_COMP_WINDOWMODE_COMP5_INPUT_PLUS_COMMON (2)
+ *
+ * (1) Parameter available on devices: STM32F302xB/C, STM32F303xB/C, STM32F358xC
+ * (2) Parameter available on devices: STM32F303xB/C, STM32F358xC
+ */
+__STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON)
+{
+#if defined(COMP_CSR_COMPxWNDWEN)
+ return (uint32_t)(READ_BIT(COMPxy_COMMON->CSR, COMP_CSR_COMPxWNDWEN));
+#else
+ /* Device without pair of comparator working in window mode */
+ return (LL_COMP_WINDOWMODE_DISABLE);
+#endif
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EF_Configuration_comparator_modes Configuration of comparator modes
+ * @{
+ */
+
+/**
+ * @brief Set comparator instance operating mode to adjust power and speed.
+ * @rmtoll CSR COMPxMODE LL_COMP_SetPowerMode
+ * @param COMPx Comparator instance
+ * @param PowerMode This parameter can be one of the following values:
+ * @arg @ref LL_COMP_POWERMODE_HIGHSPEED
+ * @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED (1)
+ * @arg @ref LL_COMP_POWERMODE_LOWPOWER (1)
+ * @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER (1)
+ *
+ * (1) Parameter available only on devices: STM32F302xB/C, STM32F303xB/C, STM32F358xC
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_SetPowerMode(COMP_TypeDef *COMPx, uint32_t PowerMode)
+{
+#if defined(COMP_CSR_COMPxMODE)
+ MODIFY_REG(COMPx->CSR, COMP_CSR_COMPxMODE, PowerMode);
+#else
+ /* Device without comparator power mode configurable */
+ /* No update of comparator register (corresponds to setting */
+ /* "LL_COMP_POWERMODE_HIGHSPEED"). */
+#endif
+}
+
+/**
+ * @brief Get comparator instance operating mode to adjust power and speed.
+ * @rmtoll CSR COMPxMODE LL_COMP_GetPowerMode
+ * @param COMPx Comparator instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_COMP_POWERMODE_HIGHSPEED
+ * @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED (1)
+ * @arg @ref LL_COMP_POWERMODE_LOWPOWER (1)
+ * @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER (1)
+ *
+ * (1) Parameter available only on devices: STM32F302xB/C, STM32F303xB/C, STM32F358xC
+ */
+__STATIC_INLINE uint32_t LL_COMP_GetPowerMode(COMP_TypeDef *COMPx)
+{
+#if defined(COMP_CSR_COMPxMODE)
+ return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_COMPxMODE));
+#else
+ /* Device without comparator power mode configurable */
+ return (LL_COMP_POWERMODE_HIGHSPEED);
+#endif
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EF_Configuration_comparator_inputs Configuration of comparator inputs
+ * @{
+ */
+
+/**
+ * @brief Set comparator inputs minus (inverting) and plus (non-inverting).
+ * @note In case of comparator input selected to be connected to IO:
+ * GPIO pins are specific to each comparator instance.
+ * Refer to description of parameters or to reference manual.
+ * @note On this STM32 serie, a voltage scaler is used
+ * when COMP input is based on VrefInt (VrefInt or subdivision
+ * of VrefInt):
+ * Voltage scaler requires a delay for voltage stabilization.
+ * Refer to device datasheet, parameter "tS_SC".
+ * @rmtoll CSR INMSEL LL_COMP_ConfigInputs\n
+ * CSR NONINSEL LL_COMP_ConfigInputs
+ * @param COMPx Comparator instance
+ * @param InputMinus This parameter can be one of the following values:
+ * @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1
+ * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2 (3)
+ * @arg @ref LL_COMP_INPUT_MINUS_DAC2_CH1 (2)
+ * @arg @ref LL_COMP_INPUT_MINUS_IO1
+ * @arg @ref LL_COMP_INPUT_MINUS_IO2
+ * @arg @ref LL_COMP_INPUT_MINUS_IO3 (1)
+ * @arg @ref LL_COMP_INPUT_MINUS_IO4
+ * (1) Parameter available on all devices except STM32F301x6/8, STM32F318x8, STM32F302x6/8, STM32F303x6/8, STM32F328xx, STM32F334xx.\n
+ * (2) Parameter available only on devices STM32F303x6/8, STM32F328x8, STM32F334xx.\n
+ * (3) Parameter available on all devices except STM32F301x6/8, STM32F318x8, STM32F302xx.\n
+ * @param InputPlus This parameter can be one of the following values:
+ * @arg @ref LL_COMP_INPUT_PLUS_IO1
+ * @arg @ref LL_COMP_INPUT_PLUS_IO2 (1)
+ * @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1_COMP1 (2)
+ * @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1_COMP2 (3)
+ *
+ * (1) Parameter available only on devices STM32F302xB/C, STM32F303xB/C, STM32F358xC.\n
+ * (2) Parameter available on devices: STM32F302xB/C, STM32F302xD/E, STM32F303xB/C/D/E, STM32F358xC, STM32F398xE.\n
+ * (3) Parameter available on devices: STM32F301x6/8, STM32F318xx, STM32F302x6/8.
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_ConfigInputs(COMP_TypeDef *COMPx, uint32_t InputMinus, uint32_t InputPlus)
+{
+#if defined(COMP_CSR_COMPxNONINSEL) && defined(COMP_CSR_COMPxSW1)
+ MODIFY_REG(COMPx->CSR,
+ COMP_CSR_COMPxINSEL | COMP_CSR_COMPxNONINSEL | COMP_CSR_COMPxSW1,
+ InputMinus | InputPlus);
+#elif defined(COMP_CSR_COMPxNONINSEL)
+ MODIFY_REG(COMPx->CSR,
+ COMP_CSR_COMPxINSEL | COMP_CSR_COMPxNONINSEL,
+ InputMinus | InputPlus);
+#elif defined(COMP_CSR_COMPxSW1)
+ MODIFY_REG(COMPx->CSR,
+ COMP_CSR_COMPxINSEL | COMP_CSR_COMPxSW1,
+ InputMinus | InputPlus);
+#else
+ /* Device without comparator input plus configurable */
+ /* No update of comparator register (corresponds to setting */
+ /* "LL_COMP_INPUT_PLUS_IO1" or "LL_COMP_INPUT_PLUS_IO2" compared to */
+ /* other STM32F3 devices, depending on comparator instance */
+ /* (refer to reference manual)). */
+ MODIFY_REG(COMPx->CSR,
+ COMP_CSR_COMPxINSEL,
+ InputMinus);
+#endif
+}
+
+/**
+ * @brief Set comparator input plus (non-inverting).
+ * @note In case of comparator input selected to be connected to IO:
+ * GPIO pins are specific to each comparator instance.
+ * Refer to description of parameters or to reference manual.
+ * @rmtoll CSR NONINSEL LL_COMP_SetInputPlus
+ * @param COMPx Comparator instance
+ * @param InputPlus This parameter can be one of the following values:
+ * @arg @ref LL_COMP_INPUT_PLUS_IO1
+ * @arg @ref LL_COMP_INPUT_PLUS_IO2 (1)
+ * @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1_COMP1 (2)
+ * @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1_COMP2 (3)
+ *
+ * (1) Parameter available only on devices STM32F302xB/C, STM32F303xB/C, STM32F358xC.\n
+ * (2) Parameter available on devices: STM32F302xB/C, STM32F302xD/E, STM32F303xB/C/D/E, STM32F358xC, STM32F398xE.\n
+ * (3) Parameter available on devices: STM32F301x6/8, STM32F318xx, STM32F302x6/8.
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_SetInputPlus(COMP_TypeDef *COMPx, uint32_t InputPlus)
+{
+#if defined(COMP_CSR_COMPxNONINSEL) && defined(COMP_CSR_COMPxSW1)
+ MODIFY_REG(COMPx->CSR, (COMP_CSR_COMPxNONINSEL | COMP_CSR_COMPxSW1), InputPlus);
+#elif defined(COMP_CSR_COMPxNONINSEL)
+ MODIFY_REG(COMPx->CSR, COMP_CSR_COMPxNONINSEL, InputPlus);
+#elif defined(COMP_CSR_COMPxSW1)
+ MODIFY_REG(COMPx->CSR, COMP_CSR_COMPxSW1, InputPlus);
+#else
+ /* Device without comparator input plus configurable */
+ /* No update of comparator register (corresponds to setting */
+ /* "LL_COMP_INPUT_PLUS_IO1" or "LL_COMP_INPUT_PLUS_IO2" compared to */
+ /* other STM32F3 devices, depending on comparator instance */
+ /* (refer to reference manual)). */
+#endif
+}
+
+/**
+ * @brief Get comparator input plus (non-inverting).
+ * @note In case of comparator input selected to be connected to IO:
+ * GPIO pins are specific to each comparator instance.
+ * Refer to description of parameters or to reference manual.
+ * @rmtoll CSR NONINSEL LL_COMP_GetInputPlus
+ * @param COMPx Comparator instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_COMP_INPUT_PLUS_IO1
+ * @arg @ref LL_COMP_INPUT_PLUS_IO2 (1)
+ * @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1_COMP1 (2)
+ * @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1_COMP2 (3)
+ *
+ * (1) Parameter available only on devices STM32F302xB/C, STM32F303xB/C, STM32F358xC.\n
+ * (2) Parameter available on devices: STM32F302xB/C, STM32F302xD/E, STM32F303xB/C/D/E, STM32F358xC, STM32F398xE.\n
+ * (3) Parameter available on devices: STM32F301x6/8, STM32F318xx, STM32F302x6/8.
+ */
+__STATIC_INLINE uint32_t LL_COMP_GetInputPlus(COMP_TypeDef *COMPx)
+{
+#if defined(COMP_CSR_COMPxNONINSEL) && defined(COMP_CSR_COMPxSW1)
+ return (uint32_t)(READ_BIT(COMPx->CSR, (COMP_CSR_COMPxNONINSEL | COMP_CSR_COMPxSW1)));
+#elif defined(COMP_CSR_COMPxNONINSEL)
+ return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_COMPxNONINSEL));
+#elif defined(COMP_CSR_COMPxSW1)
+ return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_COMPxSW1));
+#else
+ /* Device without comparator input plus configurable */
+ /* No update of comparator register (corresponds to setting */
+ /* "LL_COMP_INPUT_PLUS_IO1" or "LL_COMP_INPUT_PLUS_IO2" compared to */
+ /* other STM32F3 devices, depending on comparator instance */
+ /* (refer to reference manual)). */
+ return (LL_COMP_INPUT_PLUS_IO1);
+#endif
+}
+
+/**
+ * @brief Set comparator input minus (inverting).
+ * @note In case of comparator input selected to be connected to IO:
+ * GPIO pins are specific to each comparator instance.
+ * Refer to description of parameters or to reference manual.
+ * @note On this STM32 serie, a voltage scaler is used
+ * when COMP input is based on VrefInt (VrefInt or subdivision
+ * of VrefInt):
+ * Voltage scaler requires a delay for voltage stabilization.
+ * Refer to device datasheet, parameter "tS_SC".
+ * @rmtoll CSR INMSEL LL_COMP_SetInputMinus
+ * @param COMPx Comparator instance
+ * @param InputMinus This parameter can be one of the following values:
+ * @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1
+ * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2 (3)
+ * @arg @ref LL_COMP_INPUT_MINUS_DAC2_CH1 (2)
+ * @arg @ref LL_COMP_INPUT_MINUS_IO1
+ * @arg @ref LL_COMP_INPUT_MINUS_IO2
+ * @arg @ref LL_COMP_INPUT_MINUS_IO3 (1)
+ * @arg @ref LL_COMP_INPUT_MINUS_IO4
+ * (1) Parameter available on all devices except STM32F301x6/8, STM32F318x8, STM32F302x6/8, STM32F303x6/8, STM32F328xx, STM32F334xx.\n
+ * (2) Parameter available only on devices STM32F303x6/8, STM32F328x8, STM32F334xx.\n
+ * (3) Parameter available on all devices except STM32F301x6/8, STM32F318x8, STM32F302xx.\n
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_SetInputMinus(COMP_TypeDef *COMPx, uint32_t InputMinus)
+{
+ MODIFY_REG(COMPx->CSR, COMP_CSR_COMPxINSEL, InputMinus);
+}
+
+/**
+ * @brief Get comparator input minus (inverting).
+ * @note In case of comparator input selected to be connected to IO:
+ * GPIO pins are specific to each comparator instance.
+ * Refer to description of parameters or to reference manual.
+ * @rmtoll CSR INMSEL LL_COMP_GetInputMinus
+ * @param COMPx Comparator instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1
+ * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2 (3)
+ * @arg @ref LL_COMP_INPUT_MINUS_DAC2_CH1 (2)
+ * @arg @ref LL_COMP_INPUT_MINUS_IO1
+ * @arg @ref LL_COMP_INPUT_MINUS_IO2
+ * @arg @ref LL_COMP_INPUT_MINUS_IO3 (1)
+ * @arg @ref LL_COMP_INPUT_MINUS_IO4
+ * (1) Parameter available on all devices except STM32F301x6/8, STM32F318x8, STM32F302x6/8, STM32F303x6/8, STM32F328xx, STM32F334xx.\n
+ * (2) Parameter available only on devices STM32F303x6/8, STM32F328x8, STM32F334xx.\n
+ * (3) Parameter available on all devices except STM32F301x6/8, STM32F318x8, STM32F302xx.\n
+ */
+__STATIC_INLINE uint32_t LL_COMP_GetInputMinus(COMP_TypeDef *COMPx)
+{
+ return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_COMPxINSEL));
+}
+
+/**
+ * @brief Set comparator instance hysteresis mode of the input minus (inverting input).
+ * @rmtoll CSR COMPxHYST LL_COMP_SetInputHysteresis
+ * @param COMPx Comparator instance
+ * @param InputHysteresis This parameter can be one of the following values:
+ * @arg @ref LL_COMP_HYSTERESIS_NONE
+ * @arg @ref LL_COMP_HYSTERESIS_LOW (1)
+ * @arg @ref LL_COMP_HYSTERESIS_MEDIUM (1)
+ * @arg @ref LL_COMP_HYSTERESIS_HIGH (1)
+ *
+ * (1) Parameter available only on devices: STM32F302xB/C, STM32F303xB/C, STM32F358xC
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_SetInputHysteresis(COMP_TypeDef *COMPx, uint32_t InputHysteresis)
+{
+#if defined(COMP_CSR_COMPxHYST)
+ MODIFY_REG(COMPx->CSR, COMP_CSR_COMPxHYST, InputHysteresis);
+#else
+ /* Device without comparator input hysteresis */
+ /* No update of comparator register (corresponds to setting */
+ /* "LL_COMP_HYSTERESIS_NONE"). */
+#endif
+}
+
+/**
+ * @brief Get comparator instance hysteresis mode of the minus (inverting) input.
+ * @rmtoll CSR COMPxHYST LL_COMP_GetInputHysteresis
+ * @param COMPx Comparator instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_COMP_HYSTERESIS_NONE
+ * @arg @ref LL_COMP_HYSTERESIS_LOW (1)
+ * @arg @ref LL_COMP_HYSTERESIS_MEDIUM (1)
+ * @arg @ref LL_COMP_HYSTERESIS_HIGH (1)
+ *
+ * (1) Parameter available only on devices: STM32F302xB/C, STM32F303xB/C, STM32F358xC
+ */
+__STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis(COMP_TypeDef *COMPx)
+{
+#if defined(COMP_CSR_COMPxHYST)
+ return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_COMPxHYST));
+#else
+ /* Device without comparator input hysteresis */
+ return (LL_COMP_HYSTERESIS_NONE);
+#endif
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EF_Configuration_comparator_output Configuration of comparator output
+ * @{
+ */
+
+/**
+ * @brief Set comparator output selection.
+ * @note Availability of parameters of output selection to timer
+ * depends on timers availability on the selected device.
+ * @rmtoll CSR COMPxOUTSEL LL_COMP_SetOutputSelection
+ * @param COMPx Comparator instance
+ * @param OutputSelection This parameter can be one of the following values:
+ * @arg @ref LL_COMP_OUTPUT_NONE
+ * @arg @ref LL_COMP_OUTPUT_TIM1_BKIN
+ * @arg @ref LL_COMP_OUTPUT_TIM1_BKIN2
+ * @arg @ref LL_COMP_OUTPUT_TIM1_TIM8_BKIN2
+ * @arg @ref LL_COMP_OUTPUT_TIM8_BKIN (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM8_BKIN2 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM1_TIM8_BKIN2 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM20_BKIN (5)
+ * @arg @ref LL_COMP_OUTPUT_TIM20_BKIN2 (5)
+ * @arg @ref LL_COMP_OUTPUT_TIM1_TIM8_TIM20_BKIN2 (5)
+ * @arg @ref LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2_3_7 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4_5 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM8_OCCLR_COMP4_5_6_7 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM3_OCCLR_COMP2_4 (6)
+ * @arg @ref LL_COMP_OUTPUT_TIM1_IC1_COMP2 (2)
+ * @arg @ref LL_COMP_OUTPUT_TIM2_IC4_COMP2 (2)
+ * @arg @ref LL_COMP_OUTPUT_TIM3_IC1_COMP2 (1)
+ * @arg @ref LL_COMP_OUTPUT_TIM1_IC1_COMP1_2 (3)
+ * @arg @ref LL_COMP_OUTPUT_TIM2_IC4_COMP1_2 (3)
+ * @arg @ref LL_COMP_OUTPUT_TIM3_IC1_COMP1_2 (3)
+ * @arg @ref LL_COMP_OUTPUT_TIM20_OCCLR_COMP2 (5)
+ * @arg @ref LL_COMP_OUTPUT_TIM3_IC2_COMP3 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM4_IC1_COMP3 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM15_IC1_COMP3 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM15_BKIN
+ * @arg @ref LL_COMP_OUTPUT_TIM3_IC3_COMP4 (1)
+ * @arg @ref LL_COMP_OUTPUT_TIM4_IC2_COMP4
+ * @arg @ref LL_COMP_OUTPUT_TIM15_IC2_COMP4
+ * @arg @ref LL_COMP_OUTPUT_TIM15_OCCLR_COMP4
+ * @arg @ref LL_COMP_OUTPUT_TIM2_IC1_COMP5 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM4_IC3_COMP5 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM17_IC1_COMP5 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM16_BKIN
+ * @arg @ref LL_COMP_OUTPUT_TIM2_IC2_COMP6
+ * @arg @ref LL_COMP_OUTPUT_TIM2_OCCLR_COMP6
+ * @arg @ref LL_COMP_OUTPUT_TIM4_IC4_COMP6
+ * @arg @ref LL_COMP_OUTPUT_TIM16_IC1_COMP6
+ * @arg @ref LL_COMP_OUTPUT_TIM16_OCCLR_COMP6
+ * @arg @ref LL_COMP_OUTPUT_TIM1_IC2_COMP7 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM2_IC3_COMP7 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM17_OCCLR_COMP7 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM17_BKIN (4)
+ *
+ * (1) Parameter available on devices: STM32F302x8, STM32F318xx, STM32F303x8, STM32F328xx, STM32F334x8, STM32F302xC, STM32F302xE, STM32F303xC, STM32F358xx, STM32F303xE, STM32F398xx.\n
+ * (2) Parameter available on devices: STM32F301x8, STM32F302x8, STM32F318xx, STM32F303x8, STM32F328xx, STM32F334x8.\n
+ * (3) Parameter available on devices: STM32F302xC, STM32F302xE, STM32F303xC, STM32F358xx, STM32F303xE, STM32F398xx.\n
+ * (4) Parameter available on devices: STM32F303xC, STM32F358xx, STM32F303xE, STM32F398xx.\n
+ * (5) Parameter available on devices: STM32F303xE, STM32F398xx.\n
+ * (6) Parameter available on devices: STM32F303x8, STM32F328xx, STM32F334x8.
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_SetOutputSelection(COMP_TypeDef *COMPx, uint32_t OutputSelection)
+{
+ MODIFY_REG(COMPx->CSR, COMP_CSR_COMPxOUTSEL, OutputSelection);
+}
+
+/**
+ * @brief Get comparator output selection.
+ * @note Availability of parameters of output selection to timer
+ * depends on timers availability on the selected device.
+ * @rmtoll CSR COMPxOUTSEL LL_COMP_GetOutputSelection
+ * @param COMPx Comparator instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_COMP_OUTPUT_NONE
+ * @arg @ref LL_COMP_OUTPUT_TIM1_BKIN
+ * @arg @ref LL_COMP_OUTPUT_TIM1_BKIN2
+ * @arg @ref LL_COMP_OUTPUT_TIM1_TIM8_BKIN2
+ * @arg @ref LL_COMP_OUTPUT_TIM8_BKIN (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM8_BKIN2 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM1_TIM8_BKIN2 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM20_BKIN (5)
+ * @arg @ref LL_COMP_OUTPUT_TIM20_BKIN2 (5)
+ * @arg @ref LL_COMP_OUTPUT_TIM1_TIM8_TIM20_BKIN2 (5)
+ * @arg @ref LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2_3_7 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4_5 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM8_OCCLR_COMP4_5_6_7 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM3_OCCLR_COMP2_4 (6)
+ * @arg @ref LL_COMP_OUTPUT_TIM1_IC1_COMP2 (2)
+ * @arg @ref LL_COMP_OUTPUT_TIM2_IC4_COMP2 (2)
+ * @arg @ref LL_COMP_OUTPUT_TIM3_IC1_COMP2 (1)
+ * @arg @ref LL_COMP_OUTPUT_TIM1_IC1_COMP1_2 (3)
+ * @arg @ref LL_COMP_OUTPUT_TIM2_IC4_COMP1_2 (3)
+ * @arg @ref LL_COMP_OUTPUT_TIM3_IC1_COMP1_2 (3)
+ * @arg @ref LL_COMP_OUTPUT_TIM20_OCCLR_COMP2 (5)
+ * @arg @ref LL_COMP_OUTPUT_TIM3_IC2_COMP3 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM4_IC1_COMP3 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM15_IC1_COMP3 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM15_BKIN
+ * @arg @ref LL_COMP_OUTPUT_TIM3_IC3_COMP4 (1)
+ * @arg @ref LL_COMP_OUTPUT_TIM4_IC2_COMP4
+ * @arg @ref LL_COMP_OUTPUT_TIM15_IC2_COMP4
+ * @arg @ref LL_COMP_OUTPUT_TIM15_OCCLR_COMP4
+ * @arg @ref LL_COMP_OUTPUT_TIM2_IC1_COMP5 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM4_IC3_COMP5 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM17_IC1_COMP5 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM16_BKIN
+ * @arg @ref LL_COMP_OUTPUT_TIM2_IC2_COMP6
+ * @arg @ref LL_COMP_OUTPUT_TIM2_OCCLR_COMP6
+ * @arg @ref LL_COMP_OUTPUT_TIM4_IC4_COMP6
+ * @arg @ref LL_COMP_OUTPUT_TIM16_IC1_COMP6
+ * @arg @ref LL_COMP_OUTPUT_TIM16_OCCLR_COMP6
+ * @arg @ref LL_COMP_OUTPUT_TIM1_IC2_COMP7 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM2_IC3_COMP7 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM17_OCCLR_COMP7 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM17_BKIN (4)
+ *
+ * (1) Parameter available on devices: STM32F302x8, STM32F318xx, STM32F303x8, STM32F328xx, STM32F334x8, STM32F302xC, STM32F302xE, STM32F303xC, STM32F358xx, STM32F303xE, STM32F398xx.\n
+ * (2) Parameter available on devices: STM32F301x8, STM32F302x8, STM32F318xx, STM32F303x8, STM32F328xx, STM32F334x8.\n
+ * (3) Parameter available on devices: STM32F302xC, STM32F302xE, STM32F303xC, STM32F358xx, STM32F303xE, STM32F398xx.\n
+ * (4) Parameter available on devices: STM32F303xC, STM32F358xx, STM32F303xE, STM32F398xx.\n
+ * (5) Parameter available on devices: STM32F303xE, STM32F398xx.\n
+ * (6) Parameter available on devices: STM32F303x8, STM32F328xx, STM32F334x8.
+ */
+__STATIC_INLINE uint32_t LL_COMP_GetOutputSelection(COMP_TypeDef *COMPx)
+{
+ return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_COMPxOUTSEL));
+}
+
+/**
+ * @brief Set comparator instance output polarity.
+ * @rmtoll CSR COMPxPOL LL_COMP_SetOutputPolarity
+ * @param COMPx Comparator instance
+ * @param OutputPolarity This parameter can be one of the following values:
+ * @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED
+ * @arg @ref LL_COMP_OUTPUTPOL_INVERTED
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_SetOutputPolarity(COMP_TypeDef *COMPx, uint32_t OutputPolarity)
+{
+ MODIFY_REG(COMPx->CSR, COMP_CSR_COMPxPOL, OutputPolarity);
+}
+
+/**
+ * @brief Get comparator instance output polarity.
+ * @rmtoll CSR COMPxPOL LL_COMP_GetOutputPolarity
+ * @param COMPx Comparator instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED
+ * @arg @ref LL_COMP_OUTPUTPOL_INVERTED
+ */
+__STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(COMP_TypeDef *COMPx)
+{
+ return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_COMPxPOL));
+}
+
+/**
+ * @brief Set comparator instance blanking source.
+ * @note Blanking source may be specific to each comparator instance.
+ * Refer to description of parameters or to reference manual.
+ * @note Availability of parameters of blanking source from timer
+ * depends on timers availability on the selected device.
+ * @rmtoll CSR COMPxBLANKING LL_COMP_SetOutputBlankingSource
+ * @param COMPx Comparator instance
+ * @param BlankingSource This parameter can be one of the following values:
+ * @arg @ref LL_COMP_BLANKINGSRC_NONE
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2 (1)
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2 (1)
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2 (1)
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1_2 (2)(3)
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1_2 (2)(3)
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1_2 (2)(3)
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6 (2)
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6 (1)(2)
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1_2_7 (3)
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3_6 (3)
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4_5_6_7 (3)
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6_7 (3)
+ *
+ * (1) Parameter available on devices: STM32F301x8, STM32F302x8, STM32F318xx, STM32F303x8, STM32F334x8, STM32F328xx.\n
+ * (2) Parameter available on devices: STM32F302xE, STM32F302xC.\n
+ * (3) Parameter available on devices: STM32F303xE, STM32F398xx, STM32F303xC, STM32F358xx.
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_SetOutputBlankingSource(COMP_TypeDef *COMPx, uint32_t BlankingSource)
+{
+ MODIFY_REG(COMPx->CSR, COMP_CSR_COMPxBLANKING, BlankingSource);
+}
+
+/**
+ * @brief Get comparator instance blanking source.
+ * @note Availability of parameters of blanking source from timer
+ * depends on timers availability on the selected device.
+ * @note Blanking source may be specific to each comparator instance.
+ * Refer to description of parameters or to reference manual.
+ * @rmtoll CSR COMPxBLANKING LL_COMP_GetOutputBlankingSource
+ * @param COMPx Comparator instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_COMP_BLANKINGSRC_NONE
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2 (1)
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2 (1)
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2 (1)
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1_2 (2)(3)
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1_2 (2)(3)
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1_2 (2)(3)
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6 (2)
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6 (1)(2)
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1_2_7 (3)
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3_6 (3)
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4_5_6_7 (3)
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6_7 (3)
+ *
+ * (1) Parameter available on devices: STM32F301x8, STM32F302x8, STM32F318xx, STM32F303x8, STM32F334x8, STM32F328xx.\n
+ * (2) Parameter available on devices: STM32F302xE, STM32F302xC.\n
+ * (3) Parameter available on devices: STM32F303xE, STM32F398xx, STM32F303xC, STM32F358xx.
+ */
+__STATIC_INLINE uint32_t LL_COMP_GetOutputBlankingSource(COMP_TypeDef *COMPx)
+{
+ return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_COMPxBLANKING));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EF_Operation Operation on comparator instance
+ * @{
+ */
+
+/**
+ * @brief Enable comparator instance.
+ * @note After enable from off state, comparator requires a delay
+ * to reach reach propagation delay specification.
+ * Refer to device datasheet, parameter "tSTART".
+ * @rmtoll CSR COMPxEN LL_COMP_Enable
+ * @param COMPx Comparator instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_Enable(COMP_TypeDef *COMPx)
+{
+ SET_BIT(COMPx->CSR, COMP_CSR_COMPxEN);
+}
+
+/**
+ * @brief Disable comparator instance.
+ * @rmtoll CSR COMPxEN LL_COMP_Disable
+ * @param COMPx Comparator instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_Disable(COMP_TypeDef *COMPx)
+{
+ CLEAR_BIT(COMPx->CSR, COMP_CSR_COMPxEN);
+}
+
+/**
+ * @brief Get comparator enable state
+ * (0: COMP is disabled, 1: COMP is enabled)
+ * @rmtoll CSR COMPxEN LL_COMP_IsEnabled
+ * @param COMPx Comparator instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_COMP_IsEnabled(COMP_TypeDef *COMPx)
+{
+ return (READ_BIT(COMPx->CSR, COMP_CSR_COMPxEN) == (COMP_CSR_COMPxEN));
+}
+
+/**
+ * @brief Lock comparator instance.
+ * @note Once locked, comparator configuration can be accessed in read-only.
+ * @note The only way to unlock the comparator is a device hardware reset.
+ * @rmtoll CSR COMPxLOCK LL_COMP_Lock
+ * @param COMPx Comparator instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_Lock(COMP_TypeDef *COMPx)
+{
+ SET_BIT(COMPx->CSR, COMP_CSR_COMPxLOCK);
+}
+
+/**
+ * @brief Get comparator lock state
+ * (0: COMP is unlocked, 1: COMP is locked).
+ * @note Once locked, comparator configuration can be accessed in read-only.
+ * @note The only way to unlock the comparator is a device hardware reset.
+ * @rmtoll CSR COMPxLOCK LL_COMP_IsLocked
+ * @param COMPx Comparator instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_COMP_IsLocked(COMP_TypeDef *COMPx)
+{
+ return (READ_BIT(COMPx->CSR, COMP_CSR_COMPxLOCK) == (COMP_CSR_COMPxLOCK));
+}
+
+/**
+ * @brief Read comparator instance output level.
+ * @note The comparator output level depends on the selected polarity
+ * (Refer to function @ref LL_COMP_SetOutputPolarity()).
+ * If the comparator polarity is not inverted:
+ * - Comparator output is low when the input plus
+ * is at a lower voltage than the input minus
+ * - Comparator output is high when the input plus
+ * is at a higher voltage than the input minus
+ * If the comparator polarity is inverted:
+ * - Comparator output is high when the input plus
+ * is at a lower voltage than the input minus
+ * - Comparator output is low when the input plus
+ * is at a higher voltage than the input minus
+ * @rmtoll CSR COMPxOUT LL_COMP_ReadOutputLevel
+ * @param COMPx Comparator instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_COMP_OUTPUT_LEVEL_LOW
+ * @arg @ref LL_COMP_OUTPUT_LEVEL_HIGH
+ */
+__STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(COMP_TypeDef *COMPx)
+{
+ return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_COMPxOUT)
+ >> LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup COMP_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx);
+ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct);
+void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* COMP1 || COMP2 || COMP3 || COMP4 || COMP5 || COMP6 || COMP7 */
+
+
+#endif /* STM32F301x8 || STM32F302x8 || STM32F302xC || STM32F302xE || STM32F303x8 || STM32F303xC || STM32F303xE || STM32F318xx || STM32F328xx || STM32F334x8 || STM32F358xx || STM32F398xx */
+
+#if defined (COMP_V1_1_0_0)
+
+#if defined (COMP1) || defined (COMP2)
+
+/** @defgroup COMP_LL COMP
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup COMP_LL_Private_Constants COMP Private Constants
+ * @{
+ */
+
+/* Differentiation between COMP instances */
+/* Note: Value not corresponding to a register offset since both */
+/* COMP instances are sharing the same register) . */
+#define COMPX_BASE COMP_BASE
+#define COMPX (COMP1 - COMP2)
+
+/* COMP registers bits positions */
+#define LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS ((uint32_t)14U) /* Value equivalent to POSITION_VAL(COMP_CSR_COMP1OUT) */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup COMP_LL_Private_Macros COMP Private Macros
+ * @{
+ */
+
+/**
+ * @brief Driver macro reserved for internal use: if COMP instance selected
+ * is odd (COMP1, COMP3, ...), return value '1', else return '0'.
+ * @param __COMP_INSTANCE__ COMP instance
+ * @retval If COMP instance is odd, value '1'. Else, value '0'.
+*/
+#define __COMP_IS_INSTANCE_ODD(__COMP_INSTANCE__) \
+ ((~(((uint32_t)(__COMP_INSTANCE__) - COMP_BASE) >> 1U)) & 0x00000001)
+
+/**
+ * @brief Driver macro reserved for internal use: if COMP instance selected
+ * is even (COMP2, COMP4, ...), return value '1', else return '0'.
+ * @param __COMP_INSTANCE__ COMP instance
+ * @retval If COMP instance is even, value '1'. Else, value '0'.
+*/
+#define __COMP_IS_INSTANCE_EVEN(__COMP_INSTANCE__) \
+ (((uint32_t)(__COMP_INSTANCE__) - COMP_BASE) >> 1U)
+
+/**
+ * @brief Driver macro reserved for internal use: from COMP instance
+ * selected, set offset of bits into COMP register.
+ * @note Since both COMP instances are sharing the same register
+ * with 2 area of bits with an offset of 16 bits, this function
+ * returns value "0" if COMP1 is selected and "16" if COMP2 is
+ * selected.
+ * @param __COMP_INSTANCE__ COMP instance
+ * @retval Bits offset in register 32 bits
+*/
+#define __COMP_BITOFFSET_INSTANCE(__COMP_INSTANCE__) \
+ (((uint32_t)(__COMP_INSTANCE__) - COMP_BASE) << 3U)
+
+/**
+ * @}
+ */
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup COMP_LL_ES_INIT COMP Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief Structure definition of some features of COMP instance.
+ */
+typedef struct
+{
+ uint32_t PowerMode; /*!< Set comparator operating mode to adjust power and speed.
+ This parameter can be a value of @ref COMP_LL_EC_POWERMODE
+
+ This feature can be modified afterwards using unitary function @ref LL_COMP_SetPowerMode(). */
+
+ uint32_t InputPlus; /*!< Set comparator input plus (non-inverting input).
+ This parameter can be a value of @ref COMP_LL_EC_INPUT_PLUS
+
+ This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputPlus(). */
+
+ uint32_t InputMinus; /*!< Set comparator input minus (inverting input).
+ This parameter can be a value of @ref COMP_LL_EC_INPUT_MINUS
+
+ This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputMinus(). */
+
+ uint32_t InputHysteresis; /*!< Set comparator hysteresis mode of the input minus.
+ This parameter can be a value of @ref COMP_LL_EC_INPUT_HYSTERESIS
+
+ This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputHysteresis(). */
+
+ uint32_t OutputSelection; /*!< Set comparator output selection.
+ This parameter can be a value of @ref COMP_LL_EC_OUTPUT_SELECTION
+
+ This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputSelection(). */
+
+ uint32_t OutputPolarity; /*!< Set comparator output polarity.
+ This parameter can be a value of @ref COMP_LL_EC_OUTPUT_POLARITY
+
+ This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputPolarity(). */
+
+} LL_COMP_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup COMP_LL_Exported_Constants COMP Exported Constants
+ * @{
+ */
+
+/** @defgroup COMP_LL_EC_COMMON_WINDOWMODE Comparator common modes - Window mode
+ * @{
+ */
+#define LL_COMP_WINDOWMODE_DISABLE ((uint32_t)0x00000000U) /*!< Window mode disable: Comparators 1 and 2 are independent */
+#define LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WNDWEN) /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EC_POWERMODE Comparator modes - Power mode
+ * @{
+ */
+#define LL_COMP_POWERMODE_HIGHSPEED ((uint32_t)0x00000000U) /*!< COMP power mode to high speed */
+#define LL_COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_COMP1MODE_0) /*!< COMP power mode to medium speed */
+#define LL_COMP_POWERMODE_LOWPOWER (COMP_CSR_COMP1MODE_1) /*!< COMP power mode to low power */
+#define LL_COMP_POWERMODE_ULTRALOWPOWER (COMP_CSR_COMP1MODE_1 | COMP_CSR_COMP1MODE_0) /*!< COMP power mode to ultra-low power */
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EC_INPUT_PLUS Comparator inputs - Input plus (input non-inverting) selection
+ * @{
+ */
+#define LL_COMP_INPUT_PLUS_IO1 ((uint32_t)0x00000000U) /*!< Comparator input plus connected to IO1 (pin PA1 for COMP1, pin PA3 for COMP2) */
+#define LL_COMP_INPUT_PLUS_DAC1_CH1 (COMP_CSR_COMP1SW1) /*!< Comparator input plus connected to DAC1 channel 1 (DAC_OUT1), through dedicated switch (Note: this switch is solely intended to redirect signals onto high impedance input, such as COMP1 input plus (highly resistive switch)) (specific to COMP instance: COMP1) */
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EC_INPUT_MINUS Comparator inputs - Input minus (input inverting) selection
+ * @{
+ */
+#define LL_COMP_INPUT_MINUS_1_4VREFINT ((uint32_t)0x00000000U) /*!< Comparator input minus connected to 1/4 VrefInt */
+#define LL_COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_COMP1INSEL_0) /*!< Comparator input minus connected to 1/2 VrefInt */
+#define LL_COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_COMP1INSEL_1 ) /*!< Comparator input minus connected to 3/4 VrefInt */
+#define LL_COMP_INPUT_MINUS_VREFINT ( COMP_CSR_COMP1INSEL_1 | COMP_CSR_COMP1INSEL_0) /*!< Comparator input minus connected to VrefInt */
+#define LL_COMP_INPUT_MINUS_DAC1_CH1 (COMP_CSR_COMP1INSEL_2 ) /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1) */
+#define LL_COMP_INPUT_MINUS_DAC1_CH2 (COMP_CSR_COMP1INSEL_2 | COMP_CSR_COMP1INSEL_0) /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2) */
+#define LL_COMP_INPUT_MINUS_IO1 (COMP_CSR_COMP1INSEL_2 | COMP_CSR_COMP1INSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PA0 for COMP1, pin PA2 for COMP2) */
+#define LL_COMP_INPUT_MINUS_IO2 (COMP_CSR_COMP1INSEL_2 | COMP_CSR_COMP1INSEL_1 | COMP_CSR_COMP1INSEL_0) /*!< Comparator input minus connected to IO2 (pin PA6 for COMP1 & COMP2) */
+#define LL_COMP_INPUT_MINUS_IO3 (COMP_CSR_COMP1INSEL_2 | COMP_CSR_COMP1INSEL_0) /*!< Comparator input minus connected to IO3 (pin PA5 for COMP1 & COMP2) */
+#define LL_COMP_INPUT_MINUS_IO4 (COMP_CSR_COMP1INSEL_2 ) /*!< Comparator input minus connected to IO4 (pin PA4 for COMP1 & COMP2) */
+#define LL_COMP_INPUT_MINUS_DAC2_CH1 (COMP_CSR_COMP1INSEL_2 | COMP_CSR_COMP1INSEL_1 | COMP_CSR_COMP1INSEL_0) /*!< Comparator input minus connected to DAC2 channel 1 (DAC2_OUT1) */
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EC_INPUT_HYSTERESIS Comparator input - Hysteresis
+ * @{
+ */
+#define LL_COMP_HYSTERESIS_NONE ((uint32_t)0x00000000U) /*!< No hysteresis */
+#define LL_COMP_HYSTERESIS_LOW ( COMP_CSR_COMP1HYST_0) /*!< Hysteresis level low */
+#define LL_COMP_HYSTERESIS_MEDIUM (COMP_CSR_COMP1HYST_1 ) /*!< Hysteresis level medium */
+#define LL_COMP_HYSTERESIS_HIGH (COMP_CSR_COMP1HYST_1 | COMP_CSR_COMP1HYST_0) /*!< Hysteresis level high */
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EC_OUTPUT_SELECTION Comparator output - Output selection
+ * @{
+ */
+/* Note: Output redirection is common for COMP1 and COMP2 */
+#define LL_COMP_OUTPUT_NONE ((uint32_t)0x00000000U) /*!< COMP output is not connected to other peripherals (except GPIO and EXTI that are always connected to COMP output) */
+#define LL_COMP_OUTPUT_TIM2_IC4 (COMP_CSR_COMP1OUTSEL_2) /*!< COMP output connected to TIM2 input capture 4 */
+#define LL_COMP_OUTPUT_TIM2_OCCLR (COMP_CSR_COMP1OUTSEL_2 | COMP_CSR_COMP1OUTSEL_0) /*!< COMP output connected to TIM2 OCREF clear */
+
+/* Note: Output redirection specific to COMP instance: COMP1 */
+#define LL_COMP_OUTPUT_TIM15_BKIN_COMP1 (COMP_CSR_COMP1OUTSEL_0) /*!< COMP output connected to TIM15 break input (BKIN) (specific to COMP instance: COMP1) */
+#define LL_COMP_OUTPUT_TIM3_IC1_COMP1 (COMP_CSR_COMP1OUTSEL_1) /*!< COMP output connected to TIM3 input capture 1 (specific to COMP instance: COMP1) */
+#define LL_COMP_OUTPUT_TIM3_OCCLR_COMP1 (COMP_CSR_COMP1OUTSEL_1 | COMP_CSR_COMP1OUTSEL_0) /*!< COMP output connected to TIM3 OCREF clear (specific to COMP instance: COMP1) */
+#define LL_COMP_OUTPUT_TIM5_IC4_COMP1 (COMP_CSR_COMP1OUTSEL_2 | COMP_CSR_COMP1OUTSEL_1) /*!< COMP output connected to TIM5 input capture 4 (specific to COMP instance: COMP1) */
+#define LL_COMP_OUTPUT_TIM5_OCCLR_COMP1 (COMP_CSR_COMP1OUTSEL_2 | COMP_CSR_COMP1OUTSEL_1 | COMP_CSR_COMP1OUTSEL_0) /*!< COMP output connected to TIM5 OCREF clear (specific to COMP instance: COMP1) */
+
+/* Note: Output redirection specific to COMP instance: COMP2 */
+#define LL_COMP_OUTPUT_TIM16_BKIN_COMP2 (COMP_CSR_COMP1OUTSEL_0) /*!< COMP output connected to TIM16 break input (BKIN) (specific to COMP instance: COMP2) */
+#define LL_COMP_OUTPUT_TIM4_IC1_COMP2 (COMP_CSR_COMP1OUTSEL_1) /*!< COMP output connected to TIM4 input capture 1 (specific to COMP instance: COMP2) */
+#define LL_COMP_OUTPUT_TIM4_OCCLR_COMP2 (COMP_CSR_COMP1OUTSEL_1 | COMP_CSR_COMP1OUTSEL_0) /*!< COMP output connected to TIM4 OCREF clear (specific to COMP instance: COMP2) */
+#define LL_COMP_OUTPUT_TIM3_IC1_COMP2 (COMP_CSR_COMP1OUTSEL_2 | COMP_CSR_COMP1OUTSEL_1) /*!< COMP output connected to TIM3 input capture 1 (specific to COMP instance: COMP2) */
+#define LL_COMP_OUTPUT_TIM3_OCCLR_COMP2 (COMP_CSR_COMP1OUTSEL_2 | COMP_CSR_COMP1OUTSEL_1 | COMP_CSR_COMP1OUTSEL_0) /*!< COMP output connected to TIM3 OCREF clear (specific to COMP instance: COMP2) */
+
+/* Note: Output redirection specific to COMP instances, defined with */
+/* generic naming not taking into account COMP instance constraints. */
+/* Refer to literal definitions above for COMP instance constraints. */
+/* Note: Some output redirections cannot have a generic naming, */
+/* due to literal value different depending on COMP instance. */
+/* (For exemple: LL_COMP_OUTPUT_TIM3_IC1_COMP1 and */
+/* LL_COMP_OUTPUT_TIM3_IC1_COMP2). */
+#define LL_COMP_OUTPUT_TIM15_BKIN LL_COMP_OUTPUT_TIM15_BKIN_COMP1 /*!< COMP output connected to TIM15 break input (BKIN). Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM16_BKIN LL_COMP_OUTPUT_TIM16_BKIN_COMP2 /*!< COMP output connected to TIM16 break input (BKIN). Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM4_IC1 LL_COMP_OUTPUT_TIM4_IC1_COMP2 /*!< COMP output connected to TIM4 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM4_OCCLR LL_COMP_OUTPUT_TIM4_OCCLR_COMP2 /*!< COMP output connected to TIM4 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM5_IC4 LL_COMP_OUTPUT_TIM5_IC1_COMP1 /*!< COMP output connected to TIM5 input capture 4. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM5_OCCLR LL_COMP_OUTPUT_TIM5_OCCLR_COMP1 /*!< COMP output connected to TIM5 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EC_OUTPUT_POLARITY Comparator output - Output polarity
+ * @{
+ */
+#define LL_COMP_OUTPUTPOL_NONINVERTED ((uint32_t)0x00000000U) /*!< COMP output polarity is not inverted: comparator output is high when the plus (non-inverting) input is at a higher voltage than the minus (inverting) input */
+#define LL_COMP_OUTPUTPOL_INVERTED (COMP_CSR_COMP1POL) /*!< COMP output polarity is inverted: comparator output is low when the plus (non-inverting) input is at a lower voltage than the minus (inverting) input */
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EC_OUTPUT_LEVEL Comparator output - Output level
+ * @{
+ */
+#define LL_COMP_OUTPUT_LEVEL_LOW ((uint32_t)0x00000000U) /*!< Comparator output level low (if the polarity is not inverted, otherwise to be complemented) */
+#define LL_COMP_OUTPUT_LEVEL_HIGH ((uint32_t)0x00000001U) /*!< Comparator output level high (if the polarity is not inverted, otherwise to be complemented) */
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EC_HW_DELAYS Definitions of COMP hardware constraints delays
+ * @note Only COMP IP HW delays are defined in COMP LL driver driver,
+ * not timeout values.
+ * For details on delays values, refer to descriptions in source code
+ * above each literal definition.
+ * @{
+ */
+
+/* Delay for comparator startup time. */
+/* Note: Delay required to reach propagation delay specification. */
+/* Literal set to maximum value (refer to device datasheet, */
+/* parameter "tSTART"). */
+/* Unit: us */
+#define LL_COMP_DELAY_STARTUP_US ((uint32_t) 60U) /*!< Delay for COMP startup time */
+
+/* Delay for comparator voltage scaler stabilization time */
+/* (voltage from VrefInt, delay based on VrefInt startup time). */
+/* Literal set to maximum value (refer to device datasheet, */
+/* parameter "tS_SC"). */
+/* Unit: us */
+#define LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US ((uint32_t) 200U) /*!< Delay for COMP voltage scaler stabilization time */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup COMP_LL_Exported_Macros COMP Exported Macros
+ * @{
+ */
+/** @defgroup COMP_LL_EM_WRITE_READ Common write and read registers macro
+ * @{
+ */
+
+/**
+ * @brief Write a value in COMP register
+ * @param __INSTANCE__ comparator instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_COMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in COMP register
+ * @param __INSTANCE__ comparator instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_COMP_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EM_HELPER_MACRO COMP helper macro
+ * @{
+ */
+
+/**
+ * @brief Helper macro to select the COMP common instance
+ * to which is belonging the selected COMP instance.
+ * @note COMP common register instance can be used to
+ * set parameters common to several COMP instances.
+ * Refer to functions having argument "COMPxy_COMMON" as parameter.
+ * @param __COMPx__ COMP instance
+ * @retval COMP common instance or value "0" if there is no COMP common instance.
+ */
+#define __LL_COMP_COMMON_INSTANCE(__COMPx__) \
+ (COMP12_COMMON)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup COMP_LL_Exported_Functions COMP Exported Functions
+ * @{
+ */
+
+/** @defgroup COMP_LL_EF_Configuration_comparator_common Configuration of COMP hierarchical scope: common to several COMP instances
+ * @{
+ */
+
+/**
+ * @brief Set window mode of a pair of comparators instances
+ * (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).
+ * @rmtoll CSR WNDWEN LL_COMP_SetCommonWindowMode
+ * @param COMPxy_COMMON Comparator common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() )
+ * @param WindowMode This parameter can be one of the following values:
+ * @arg @ref LL_COMP_WINDOWMODE_DISABLE
+ * @arg @ref LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_SetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowMode)
+{
+ MODIFY_REG(COMPxy_COMMON->CSR, COMP_CSR_WNDWEN, WindowMode);
+}
+
+/**
+ * @brief Get window mode of a pair of comparators instances
+ * (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).
+ * @rmtoll CSR WNDWEN LL_COMP_GetCommonWindowMode
+ * @param COMPxy_COMMON Comparator common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() )
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_COMP_WINDOWMODE_DISABLE
+ * @arg @ref LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
+ */
+__STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON)
+{
+ return (uint32_t)(READ_BIT(COMPxy_COMMON->CSR, COMP_CSR_WNDWEN));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EF_Configuration_comparator_modes Configuration of comparator modes
+ * @{
+ */
+
+/**
+ * @brief Set comparator instance operating mode to adjust power and speed.
+ * @rmtoll CSR COMP1MODE LL_COMP_SetPowerMode\n
+ * COMP2MODE LL_COMP_SetPowerMode
+ * @param COMPx Comparator instance
+ * @param PowerMode This parameter can be one of the following values:
+ * @arg @ref LL_COMP_POWERMODE_HIGHSPEED
+ * @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED
+ * @arg @ref LL_COMP_POWERMODE_LOWPOWER
+ * @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_SetPowerMode(COMP_TypeDef *COMPx, uint32_t PowerMode)
+{
+ MODIFY_REG(COMP->CSR,
+ COMP_CSR_COMP1MODE << __COMP_BITOFFSET_INSTANCE(COMPx),
+ PowerMode << __COMP_BITOFFSET_INSTANCE(COMPx));
+}
+
+/**
+ * @brief Get comparator instance operating mode to adjust power and speed.
+ * @rmtoll CSR COMP1MODE LL_COMP_GetPowerMode\n
+ * COMP2MODE LL_COMP_GetPowerMode
+ * @param COMPx Comparator instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_COMP_POWERMODE_HIGHSPEED
+ * @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED
+ * @arg @ref LL_COMP_POWERMODE_LOWPOWER
+ * @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER
+ */
+__STATIC_INLINE uint32_t LL_COMP_GetPowerMode(COMP_TypeDef *COMPx)
+{
+ return (uint32_t)(READ_BIT(COMP->CSR,
+ COMP_CSR_COMP1MODE << __COMP_BITOFFSET_INSTANCE(COMPx))
+ >> __COMP_BITOFFSET_INSTANCE(COMPx)
+ );
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EF_Configuration_comparator_inputs Configuration of comparator inputs
+ * @{
+ */
+
+/**
+ * @brief Set comparator inputs minus (inverting) and plus (non-inverting).
+ * @note In case of comparator input selected to be connected to IO:
+ * GPIO pins are specific to each comparator instance.
+ * Refer to description of parameters or to reference manual.
+ * @rmtoll CSR COMP1INSEL LL_COMP_ConfigInputs\n
+ * CSR COMP2INSEL LL_COMP_ConfigInputs\n
+ * CSR COMP1SW1 LL_COMP_ConfigInputs
+ * @param COMPx Comparator instance
+ * @param InputMinus This parameter can be one of the following values:
+ * @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1
+ * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2
+ * @arg @ref LL_COMP_INPUT_MINUS_IO1
+ * @arg @ref LL_COMP_INPUT_MINUS_IO2
+ * @arg @ref LL_COMP_INPUT_MINUS_IO3
+ * @arg @ref LL_COMP_INPUT_MINUS_IO4
+ * @arg @ref LL_COMP_INPUT_MINUS_DAC2_CH1
+ * @param InputPlus This parameter can be one of the following values:
+ * @arg @ref LL_COMP_INPUT_PLUS_IO1
+ * @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1 (1)
+ *
+ * (1) Parameter available only on COMP instance: COMP1.
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_ConfigInputs(COMP_TypeDef *COMPx, uint32_t InputMinus, uint32_t InputPlus)
+{
+ /* Note: Connection switch is applicable only to COMP instance COMP1, */
+ /* therefore if COMP2 is selected the equivalent bit is */
+ /* kept unmodified. */
+ MODIFY_REG(COMP->CSR,
+ (COMP_CSR_COMP1INSEL | (COMP_CSR_COMP1SW1 * __COMP_IS_INSTANCE_ODD(COMPx))) << __COMP_BITOFFSET_INSTANCE(COMPx),
+ (InputMinus | InputPlus) << __COMP_BITOFFSET_INSTANCE(COMPx));
+}
+
+/**
+ * @brief Set comparator input plus (non-inverting).
+ * @note In case of comparator input selected to be connected to IO:
+ * GPIO pins are specific to each comparator instance.
+ * Refer to description of parameters or to reference manual.
+ * @rmtoll CSR COMP1INSEL LL_COMP_SetInputPlus\n
+ * CSR COMP2INSEL LL_COMP_SetInputPlus
+ * @param COMPx Comparator instance
+ * @param InputPlus This parameter can be one of the following values:
+ * @arg @ref LL_COMP_INPUT_PLUS_IO1
+ * @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1 (1)
+ *
+ * (1) Parameter available only on COMP instance: COMP1.
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_SetInputPlus(COMP_TypeDef *COMPx, uint32_t InputPlus)
+{
+ /* Note: Connection switch is applicable only to COMP instance COMP1, */
+ /* therefore if COMP2 is selected the equivalent bit is */
+ /* kept unmodified. */
+ MODIFY_REG(COMP->CSR,
+ (COMP_CSR_COMP1SW1 * __COMP_IS_INSTANCE_ODD(COMPx)) << __COMP_BITOFFSET_INSTANCE(COMPx),
+ InputPlus << __COMP_BITOFFSET_INSTANCE(COMPx));
+}
+
+/**
+ * @brief Get comparator input plus (non-inverting).
+ * @note In case of comparator input selected to be connected to IO:
+ * GPIO pins are specific to each comparator instance.
+ * Refer to description of parameters or to reference manual.
+ * @rmtoll CSR COMP1INSEL LL_COMP_GetInputPlus\n
+ * CSR COMP2INSEL LL_COMP_GetInputPlus
+ * @param COMPx Comparator instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_COMP_INPUT_PLUS_IO1
+ * @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1 (1)
+ *
+ * (1) Parameter available only on COMP instance: COMP1.
+ */
+__STATIC_INLINE uint32_t LL_COMP_GetInputPlus(COMP_TypeDef *COMPx)
+{
+ /* Note: Connection switch is applicable only to COMP instance COMP1, */
+ /* therefore is COMP2 is selected the returned value will be null. */
+ return (uint32_t)(READ_BIT(COMP->CSR,
+ COMP_CSR_COMP1SW1 << __COMP_BITOFFSET_INSTANCE(COMPx))
+ >> __COMP_BITOFFSET_INSTANCE(COMPx)
+ );
+}
+
+/**
+ * @brief Set comparator input minus (inverting).
+ * @note In case of comparator input selected to be connected to IO:
+ * GPIO pins are specific to each comparator instance.
+ * Refer to description of parameters or to reference manual.
+ * @rmtoll CSR COMP1SW1 LL_COMP_SetInputMinus
+ * @param COMPx Comparator instance
+ * @param InputMinus This parameter can be one of the following values:
+ * @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1
+ * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2
+ * @arg @ref LL_COMP_INPUT_MINUS_IO1
+ * @arg @ref LL_COMP_INPUT_MINUS_IO2
+ * @arg @ref LL_COMP_INPUT_MINUS_IO3
+ * @arg @ref LL_COMP_INPUT_MINUS_IO4
+ * @arg @ref LL_COMP_INPUT_MINUS_DAC2_CH1
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_SetInputMinus(COMP_TypeDef *COMPx, uint32_t InputMinus)
+{
+ MODIFY_REG(COMP->CSR,
+ COMP_CSR_COMP1INSEL << __COMP_BITOFFSET_INSTANCE(COMPx),
+ InputMinus << __COMP_BITOFFSET_INSTANCE(COMPx));
+}
+
+/**
+ * @brief Get comparator input minus (inverting).
+ * @note In case of comparator input selected to be connected to IO:
+ * GPIO pins are specific to each comparator instance.
+ * Refer to description of parameters or to reference manual.
+ * @rmtoll CSR COMP1SW1 LL_COMP_GetInputMinus
+ * @param COMPx Comparator instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1
+ * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2
+ * @arg @ref LL_COMP_INPUT_MINUS_IO1
+ * @arg @ref LL_COMP_INPUT_MINUS_IO2
+ * @arg @ref LL_COMP_INPUT_MINUS_IO3
+ * @arg @ref LL_COMP_INPUT_MINUS_IO4
+ * @arg @ref LL_COMP_INPUT_MINUS_DAC2_CH1
+ */
+__STATIC_INLINE uint32_t LL_COMP_GetInputMinus(COMP_TypeDef *COMPx)
+{
+ return (uint32_t)(READ_BIT(COMP->CSR,
+ COMP_CSR_COMP1INSEL << __COMP_BITOFFSET_INSTANCE(COMPx))
+ >> __COMP_BITOFFSET_INSTANCE(COMPx)
+ );
+}
+
+/**
+ * @brief Set comparator instance hysteresis mode of the input minus (inverting input).
+ * @rmtoll CSR COMP1HYST LL_COMP_SetInputHysteresis\n
+ * COMP2HYST LL_COMP_SetInputHysteresis
+ * @param COMPx Comparator instance
+ * @param InputHysteresis This parameter can be one of the following values:
+ * @arg @ref LL_COMP_HYSTERESIS_NONE
+ * @arg @ref LL_COMP_HYSTERESIS_LOW
+ * @arg @ref LL_COMP_HYSTERESIS_MEDIUM
+ * @arg @ref LL_COMP_HYSTERESIS_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_SetInputHysteresis(COMP_TypeDef *COMPx, uint32_t InputHysteresis)
+{
+ MODIFY_REG(COMP->CSR,
+ COMP_CSR_COMP1HYST << __COMP_BITOFFSET_INSTANCE(COMPx),
+ InputHysteresis << __COMP_BITOFFSET_INSTANCE(COMPx));
+}
+
+/**
+ * @brief Get comparator instance hysteresis mode of the minus (inverting) input.
+ * @rmtoll CSR COMP1HYST LL_COMP_GetInputHysteresis\n
+ * COMP2HYST LL_COMP_GetInputHysteresis
+ * @param COMPx Comparator instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_COMP_HYSTERESIS_NONE
+ * @arg @ref LL_COMP_HYSTERESIS_LOW
+ * @arg @ref LL_COMP_HYSTERESIS_MEDIUM
+ * @arg @ref LL_COMP_HYSTERESIS_HIGH
+ */
+__STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis(COMP_TypeDef *COMPx)
+{
+ return (uint32_t)(READ_BIT(COMP->CSR,
+ COMP_CSR_COMP1HYST << __COMP_BITOFFSET_INSTANCE(COMPx))
+ >> __COMP_BITOFFSET_INSTANCE(COMPx)
+ );
+
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EF_Configuration_comparator_output Configuration of comparator output
+ * @{
+ */
+
+/**
+ * @brief Set comparator output selection.
+ * @note Availability of parameters of output selection to timer
+ * depends on timers availability on the selected device.
+ * @rmtoll CSR COMP1OUTSEL LL_COMP_SetOutputSelection\n
+ * COMP2OUTSEL LL_COMP_SetOutputSelection
+ * @param COMPx Comparator instance
+ * @param OutputSelection This parameter can be one of the following values:
+ * @arg @ref LL_COMP_OUTPUT_NONE
+ * @arg @ref LL_COMP_OUTPUT_TIM16_BKIN (1)
+ * @arg @ref LL_COMP_OUTPUT_TIM4_IC1 (1)
+ * @arg @ref LL_COMP_OUTPUT_TIM4_OCCLR (1)
+ * @arg @ref LL_COMP_OUTPUT_TIM2_IC4 (1)
+ * @arg @ref LL_COMP_OUTPUT_TIM2_OCCLR (1)
+ * @arg @ref LL_COMP_OUTPUT_TIM3_IC1 (1)
+ * @arg @ref LL_COMP_OUTPUT_TIM3_OCCLR (1)
+ *
+ * (1) Parameter availability depending on timer availability
+ * on the selected device.
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_SetOutputSelection(COMP_TypeDef *COMPx, uint32_t OutputSelection)
+{
+ MODIFY_REG(COMP->CSR,
+ COMP_CSR_COMP1OUTSEL << __COMP_BITOFFSET_INSTANCE(COMPx),
+ OutputSelection << __COMP_BITOFFSET_INSTANCE(COMPx));
+}
+
+/**
+ * @brief Get comparator output selection.
+ * @note Availability of parameters of output selection to timer
+ * depends on timers availability on the selected device.
+ * @rmtoll CSR COMP1OUTSEL LL_COMP_GetOutputSelection\n
+ * COMP2OUTSEL LL_COMP_GetOutputSelection
+ * @param COMPx Comparator instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_COMP_OUTPUT_NONE
+ * @arg @ref LL_COMP_OUTPUT_TIM16_BKIN (1)
+ * @arg @ref LL_COMP_OUTPUT_TIM4_IC1 (1)
+ * @arg @ref LL_COMP_OUTPUT_TIM4_OCCLR (1)
+ * @arg @ref LL_COMP_OUTPUT_TIM2_IC4 (1)
+ * @arg @ref LL_COMP_OUTPUT_TIM2_OCCLR (1)
+ * @arg @ref LL_COMP_OUTPUT_TIM3_IC1 (1)
+ * @arg @ref LL_COMP_OUTPUT_TIM3_OCCLR (1)
+ *
+ * (1) Parameter availability depending on timer availability
+ * on the selected device.
+ */
+__STATIC_INLINE uint32_t LL_COMP_GetOutputSelection(COMP_TypeDef *COMPx)
+{
+ return (uint32_t)(READ_BIT(COMP->CSR,
+ COMP_CSR_COMP1OUTSEL << __COMP_BITOFFSET_INSTANCE(COMPx))
+ >> __COMP_BITOFFSET_INSTANCE(COMPx)
+ );
+}
+
+/**
+ * @brief Set comparator instance output polarity.
+ * @rmtoll CSR COMP1POL LL_COMP_SetOutputPolarity\n
+ * COMP2POL LL_COMP_SetOutputPolarity
+ * @param COMPx Comparator instance
+ * @param OutputPolarity This parameter can be one of the following values:
+ * @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED
+ * @arg @ref LL_COMP_OUTPUTPOL_INVERTED
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_SetOutputPolarity(COMP_TypeDef *COMPx, uint32_t OutputPolarity)
+{
+ MODIFY_REG(COMP->CSR,
+ COMP_CSR_COMP1POL << __COMP_BITOFFSET_INSTANCE(COMPx),
+ OutputPolarity << __COMP_BITOFFSET_INSTANCE(COMPx));
+}
+
+/**
+ * @brief Get comparator instance output polarity.
+ * @rmtoll CSR COMP1POL LL_COMP_GetOutputPolarity\n
+ * COMP2POL LL_COMP_GetOutputPolarity
+ * @param COMPx Comparator instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED
+ * @arg @ref LL_COMP_OUTPUTPOL_INVERTED
+ */
+__STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(COMP_TypeDef *COMPx)
+{
+ return (uint32_t)(READ_BIT(COMP->CSR,
+ COMP_CSR_COMP1POL << __COMP_BITOFFSET_INSTANCE(COMPx))
+ >> __COMP_BITOFFSET_INSTANCE(COMPx)
+ );
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EF_Operation Operation on comparator instance
+ * @{
+ */
+
+/**
+ * @brief Enable comparator instance.
+ * @note After enable from off state, comparator requires a delay
+ * to reach reach propagation delay specification.
+ * Refer to device datasheet, parameter "tSTART".
+ * @rmtoll CSR COMP1EN LL_COMP_Enable\n
+ * COMP2EN LL_COMP_Enable
+ * @param COMPx Comparator instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_Enable(COMP_TypeDef *COMPx)
+{
+ SET_BIT(COMP->CSR, COMP_CSR_COMP1EN << __COMP_BITOFFSET_INSTANCE(COMPx));
+}
+
+/**
+ * @brief Disable comparator instance.
+ * @rmtoll CSR COMP1EN LL_COMP_Disable\n
+ * COMP2EN LL_COMP_Disable
+ * @param COMPx Comparator instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_Disable(COMP_TypeDef *COMPx)
+{
+ CLEAR_BIT(COMP->CSR, COMP_CSR_COMP1EN << __COMP_BITOFFSET_INSTANCE(COMPx));
+}
+
+/**
+ * @brief Get comparator enable state
+ * (0: COMP is disabled, 1: COMP is enabled)
+ * @rmtoll CSR COMP1EN LL_COMP_IsEnabled\n
+ * COMP2EN LL_COMP_IsEnabled
+ * @param COMPx Comparator instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_COMP_IsEnabled(COMP_TypeDef *COMPx)
+{
+ return (READ_BIT(COMP->CSR, COMP_CSR_COMP1EN << __COMP_BITOFFSET_INSTANCE(COMPx)) == COMP_CSR_COMP1EN <<
+ __COMP_BITOFFSET_INSTANCE(COMPx));
+}
+
+/**
+ * @brief Lock comparator instance.
+ * @note Once locked, comparator configuration can be accessed in read-only.
+ * @note The only way to unlock the comparator is a device hardware reset.
+ * @rmtoll CSR COMP1LOCK LL_COMP_Lock\n
+ * COMP2LOCK LL_COMP_Lock
+ * @param COMPx Comparator instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_Lock(COMP_TypeDef *COMPx)
+{
+ SET_BIT(COMP->CSR, COMP_CSR_COMP1LOCK << __COMP_BITOFFSET_INSTANCE(COMPx));
+}
+
+/**
+ * @brief Get comparator lock state
+ * (0: COMP is unlocked, 1: COMP is locked).
+ * @note Once locked, comparator configuration can be accessed in read-only.
+ * @note The only way to unlock the comparator is a device hardware reset.
+ * @rmtoll CSR COMP1LOCK LL_COMP_IsLocked\n
+ * COMP2LOCK LL_COMP_IsLocked
+ * @param COMPx Comparator instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_COMP_IsLocked(COMP_TypeDef *COMPx)
+{
+ return (READ_BIT(COMP->CSR, COMP_CSR_COMP1LOCK << __COMP_BITOFFSET_INSTANCE(COMPx)) == COMP_CSR_COMP1LOCK <<
+ __COMP_BITOFFSET_INSTANCE(COMPx));
+}
+
+/**
+ * @brief Read comparator instance output level.
+ * @note The comparator output level depends on the selected polarity
+ * (Refer to function @ref LL_COMP_SetOutputPolarity()).
+ * If the comparator polarity is not inverted:
+ * - Comparator output is low when the input plus
+ * is at a lower voltage than the input minus
+ * - Comparator output is high when the input plus
+ * is at a higher voltage than the input minus
+ * If the comparator polarity is inverted:
+ * - Comparator output is high when the input plus
+ * is at a lower voltage than the input minus
+ * - Comparator output is low when the input plus
+ * is at a higher voltage than the input minus
+ * @rmtoll CSR COMP1OUT LL_COMP_ReadOutputLevel\n
+ * COMP2OUT LL_COMP_ReadOutputLevel
+ * @param COMPx Comparator instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_COMP_OUTPUT_LEVEL_LOW
+ * @arg @ref LL_COMP_OUTPUT_LEVEL_HIGH
+ */
+__STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(COMP_TypeDef *COMPx)
+{
+ return (uint32_t)(READ_BIT(COMP->CSR,
+ COMP_CSR_COMP1OUT << __COMP_BITOFFSET_INSTANCE(COMPx))
+ >> (__COMP_BITOFFSET_INSTANCE(COMPx) + LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS)
+ );
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup COMP_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx);
+ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct);
+void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* COMP1 || COMP2 */
+
+
+#endif /* STM32F373xC || STM32F378xx */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_LL_COMP_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_ll_cortex.h b/Inc/stm32f3xx_ll_cortex.h
new file mode 100644
index 0000000..750930b
--- /dev/null
+++ b/Inc/stm32f3xx_ll_cortex.h
@@ -0,0 +1,656 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_cortex.h
+ * @author MCD Application Team
+ * @brief Header file of CORTEX LL module.
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The LL CORTEX driver contains a set of generic APIs that can be
+ used by user:
+ (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
+ functions
+ (+) Low power mode configuration (SCB register of Cortex-MCU)
+ (+) MPU API to configure and enable regions
+ (MPU services provided only on some devices)
+ (+) API to access to MCU info (CPUID register)
+ (+) API to enable fault handler (SHCSR accesses)
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_LL_CORTEX_H
+#define __STM32F3xx_LL_CORTEX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx.h"
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+/** @defgroup CORTEX_LL CORTEX
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
+ * @{
+ */
+
+/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
+ * @{
+ */
+#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/
+#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
+ * @{
+ */
+#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
+#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
+#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
+/**
+ * @}
+ */
+
+#if __MPU_PRESENT
+
+/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
+ * @{
+ */
+#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */
+#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
+#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
+#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_REGION MPU Region Number
+ * @{
+ */
+#define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */
+#define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */
+#define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */
+#define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */
+#define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */
+#define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */
+#define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */
+#define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
+ * @{
+ */
+#define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
+ * @{
+ */
+#define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
+#define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
+#define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
+#define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
+#define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
+#define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
+ * @{
+ */
+#define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
+#define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
+#define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
+#define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
+ * @{
+ */
+#define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */
+#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
+ * @{
+ */
+#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
+#define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
+ * @{
+ */
+#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
+#define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
+ * @{
+ */
+#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
+#define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */
+/**
+ * @}
+ */
+#endif /* __MPU_PRESENT */
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
+ * @{
+ */
+
+/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
+ * @{
+ */
+
+/**
+ * @brief This function checks if the Systick counter flag is active or not.
+ * @note It can be used in timeout function on application side.
+ * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
+{
+ return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
+}
+
+/**
+ * @brief Configures the SysTick clock source
+ * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
+ * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
+{
+ if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
+ {
+ SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
+ }
+ else
+ {
+ CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
+ }
+}
+
+/**
+ * @brief Get the SysTick clock source
+ * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
+ * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
+ */
+__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
+{
+ return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
+}
+
+/**
+ * @brief Enable SysTick exception request
+ * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
+{
+ SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+ * @brief Disable SysTick exception request
+ * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSTICK_DisableIT(void)
+{
+ CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+ * @brief Checks if the SYSTICK interrupt is enabled or disabled.
+ * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
+{
+ return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
+ * @{
+ */
+
+/**
+ * @brief Processor uses sleep as its low power mode
+ * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPM_EnableSleep(void)
+{
+ /* Clear SLEEPDEEP bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+}
+
+/**
+ * @brief Processor uses deep sleep as its low power mode
+ * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
+{
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+}
+
+/**
+ * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
+ * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
+ * empty main application.
+ * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
+{
+ /* Set SLEEPONEXIT bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+/**
+ * @brief Do not sleep when returning to Thread mode.
+ * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
+{
+ /* Clear SLEEPONEXIT bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+/**
+ * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
+ * processor.
+ * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
+{
+ /* Set SEVEONPEND bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+/**
+ * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
+ * excluded
+ * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
+{
+ /* Clear SEVEONPEND bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EF_HANDLER HANDLER
+ * @{
+ */
+
+/**
+ * @brief Enable a fault in System handler control register (SHCSR)
+ * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
+ * @param Fault This parameter can be a combination of the following values:
+ * @arg @ref LL_HANDLER_FAULT_USG
+ * @arg @ref LL_HANDLER_FAULT_BUS
+ * @arg @ref LL_HANDLER_FAULT_MEM
+ * @retval None
+ */
+__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
+{
+ /* Enable the system handler fault */
+ SET_BIT(SCB->SHCSR, Fault);
+}
+
+/**
+ * @brief Disable a fault in System handler control register (SHCSR)
+ * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
+ * @param Fault This parameter can be a combination of the following values:
+ * @arg @ref LL_HANDLER_FAULT_USG
+ * @arg @ref LL_HANDLER_FAULT_BUS
+ * @arg @ref LL_HANDLER_FAULT_MEM
+ * @retval None
+ */
+__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
+{
+ /* Disable the system handler fault */
+ CLEAR_BIT(SCB->SHCSR, Fault);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
+ * @{
+ */
+
+/**
+ * @brief Get Implementer code
+ * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
+ * @retval Value should be equal to 0x41 for ARM
+ */
+__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
+{
+ return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
+}
+
+/**
+ * @brief Get Variant number (The r value in the rnpn product revision identifier)
+ * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
+ * @retval Value between 0 and 255 (0x0: revision 0)
+ */
+__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
+{
+ return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
+}
+
+/**
+ * @brief Get Constant number
+ * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
+ * @retval Value should be equal to 0xF for Cortex-M4 devices
+ */
+__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
+{
+ return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
+}
+
+/**
+ * @brief Get Part number
+ * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
+ * @retval Value should be equal to 0xC24 for Cortex-M4
+ */
+__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
+{
+ return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
+}
+
+/**
+ * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
+ * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
+ * @retval Value between 0 and 255 (0x1: patch 1)
+ */
+__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
+{
+ return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
+}
+
+/**
+ * @}
+ */
+
+#if __MPU_PRESENT
+/** @defgroup CORTEX_LL_EF_MPU MPU
+ * @{
+ */
+
+/**
+ * @brief Enable MPU with input options
+ * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
+ * @param Options This parameter can be one of the following values:
+ * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
+ * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
+ * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
+ * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
+{
+ /* Enable the MPU*/
+ WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
+ /* Ensure MPU settings take effects */
+ __DSB();
+ /* Sequence instruction fetches using update settings */
+ __ISB();
+}
+
+/**
+ * @brief Disable MPU
+ * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_Disable(void)
+{
+ /* Make sure outstanding transfers are done */
+ __DMB();
+ /* Disable MPU*/
+ WRITE_REG(MPU->CTRL, 0U);
+}
+
+/**
+ * @brief Check if MPU is enabled or not
+ * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
+{
+ return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
+}
+
+/**
+ * @brief Enable a MPU region
+ * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
+{
+ /* Set Region number */
+ WRITE_REG(MPU->RNR, Region);
+ /* Enable the MPU region */
+ SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
+/**
+ * @brief Configure and enable a region
+ * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
+ * MPU_RBAR REGION LL_MPU_ConfigRegion\n
+ * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
+ * MPU_RASR XN LL_MPU_ConfigRegion\n
+ * MPU_RASR AP LL_MPU_ConfigRegion\n
+ * MPU_RASR S LL_MPU_ConfigRegion\n
+ * MPU_RASR C LL_MPU_ConfigRegion\n
+ * MPU_RASR B LL_MPU_ConfigRegion\n
+ * MPU_RASR SIZE LL_MPU_ConfigRegion
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @param Address Value of region base address
+ * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
+ * @param Attributes This parameter can be a combination of the following values:
+ * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
+ * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
+ * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
+ * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
+ * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
+ * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
+ * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
+ * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
+ * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
+ * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
+ * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
+ * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
+ * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
+{
+ /* Set Region number */
+ WRITE_REG(MPU->RNR, Region);
+ /* Set base address */
+ WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
+ /* Configure MPU */
+ WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
+}
+
+/**
+ * @brief Disable a region
+ * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
+ * MPU_RASR ENABLE LL_MPU_DisableRegion
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
+{
+ /* Set Region number */
+ WRITE_REG(MPU->RNR, Region);
+ /* Disable the MPU region */
+ CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
+/**
+ * @}
+ */
+
+#endif /* __MPU_PRESENT */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_LL_CORTEX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_ll_crc.h b/Inc/stm32f3xx_ll_crc.h
new file mode 100644
index 0000000..b07d93a
--- /dev/null
+++ b/Inc/stm32f3xx_ll_crc.h
@@ -0,0 +1,477 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_crc.h
+ * @author MCD Application Team
+ * @brief Header file of CRC LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_LL_CRC_H
+#define __STM32F3xx_LL_CRC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx.h"
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined(CRC)
+
+/** @defgroup CRC_LL CRC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRC_LL_Exported_Constants CRC Exported Constants
+ * @{
+ */
+
+/** @defgroup CRC_LL_EC_POLYLENGTH Polynomial length
+ * @{
+ */
+#define LL_CRC_POLYLENGTH_32B 0x00000000U /*!< 32 bits Polynomial size */
+#define LL_CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0 /*!< 16 bits Polynomial size */
+#define LL_CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1 /*!< 8 bits Polynomial size */
+#define LL_CRC_POLYLENGTH_7B (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0) /*!< 7 bits Polynomial size */
+/**
+ * @}
+ */
+
+/** @defgroup CRC_LL_EC_INDATA_REVERSE Input Data Reverse
+ * @{
+ */
+#define LL_CRC_INDATA_REVERSE_NONE 0x00000000U /*!< Input Data bit order not affected */
+#define LL_CRC_INDATA_REVERSE_BYTE CRC_CR_REV_IN_0 /*!< Input Data bit reversal done by byte */
+#define LL_CRC_INDATA_REVERSE_HALFWORD CRC_CR_REV_IN_1 /*!< Input Data bit reversal done by half-word */
+#define LL_CRC_INDATA_REVERSE_WORD (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0) /*!< Input Data bit reversal done by word */
+/**
+ * @}
+ */
+
+/** @defgroup CRC_LL_EC_OUTDATA_REVERSE Output Data Reverse
+ * @{
+ */
+#define LL_CRC_OUTDATA_REVERSE_NONE 0x00000000U /*!< Output Data bit order not affected */
+#define LL_CRC_OUTDATA_REVERSE_BIT CRC_CR_REV_OUT /*!< Output Data bit reversal done by bit */
+/**
+ * @}
+ */
+
+/** @defgroup CRC_LL_EC_Default_Polynomial_Value Default CRC generating polynomial value
+ * @brief Normal representation of this polynomial value is
+ * X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 .
+ * @{
+ */
+#define LL_CRC_DEFAULT_CRC32_POLY 0x04C11DB7U /*!< Default CRC generating polynomial value */
+/**
+ * @}
+ */
+
+/** @defgroup CRC_LL_EC_Default_InitValue Default CRC computation initialization value
+ * @{
+ */
+#define LL_CRC_DEFAULT_CRC_INITVALUE 0xFFFFFFFFU /*!< Default CRC computation initialization value */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup CRC_LL_Exported_Macros CRC Exported Macros
+ * @{
+ */
+
+/** @defgroup CRC_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in CRC register
+ * @param __INSTANCE__ CRC Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in CRC register
+ * @param __INSTANCE__ CRC Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CRC_LL_Exported_Functions CRC Exported Functions
+ * @{
+ */
+
+/** @defgroup CRC_LL_EF_Configuration CRC Configuration functions
+ * @{
+ */
+
+/**
+ * @brief Reset the CRC calculation unit.
+ * @note If Programmable Initial CRC value feature
+ * is available, also set the Data Register to the value stored in the
+ * CRC_INIT register, otherwise, reset Data Register to its default value.
+ * @rmtoll CR RESET LL_CRC_ResetCRCCalculationUnit
+ * @param CRCx CRC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *CRCx)
+{
+ SET_BIT(CRCx->CR, CRC_CR_RESET);
+}
+
+/**
+ * @brief Configure size of the polynomial.
+ * @rmtoll CR POLYSIZE LL_CRC_SetPolynomialSize
+ * @param CRCx CRC Instance
+ * @param PolySize This parameter can be one of the following values:
+ * @arg @ref LL_CRC_POLYLENGTH_32B
+ * @arg @ref LL_CRC_POLYLENGTH_16B
+ * @arg @ref LL_CRC_POLYLENGTH_8B
+ * @arg @ref LL_CRC_POLYLENGTH_7B
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRC_SetPolynomialSize(CRC_TypeDef *CRCx, uint32_t PolySize)
+{
+ MODIFY_REG(CRCx->CR, CRC_CR_POLYSIZE, PolySize);
+}
+
+/**
+ * @brief Return size of the polynomial.
+ * @rmtoll CR POLYSIZE LL_CRC_GetPolynomialSize
+ * @param CRCx CRC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_CRC_POLYLENGTH_32B
+ * @arg @ref LL_CRC_POLYLENGTH_16B
+ * @arg @ref LL_CRC_POLYLENGTH_8B
+ * @arg @ref LL_CRC_POLYLENGTH_7B
+ */
+__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(CRC_TypeDef *CRCx)
+{
+ return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_POLYSIZE));
+}
+
+/**
+ * @brief Configure the reversal of the bit order of the input data
+ * @rmtoll CR REV_IN LL_CRC_SetInputDataReverseMode
+ * @param CRCx CRC Instance
+ * @param ReverseMode This parameter can be one of the following values:
+ * @arg @ref LL_CRC_INDATA_REVERSE_NONE
+ * @arg @ref LL_CRC_INDATA_REVERSE_BYTE
+ * @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
+ * @arg @ref LL_CRC_INDATA_REVERSE_WORD
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRC_SetInputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode)
+{
+ MODIFY_REG(CRCx->CR, CRC_CR_REV_IN, ReverseMode);
+}
+
+/**
+ * @brief Return type of reversal for input data bit order
+ * @rmtoll CR REV_IN LL_CRC_GetInputDataReverseMode
+ * @param CRCx CRC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_CRC_INDATA_REVERSE_NONE
+ * @arg @ref LL_CRC_INDATA_REVERSE_BYTE
+ * @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
+ * @arg @ref LL_CRC_INDATA_REVERSE_WORD
+ */
+__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(CRC_TypeDef *CRCx)
+{
+ return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_IN));
+}
+
+/**
+ * @brief Configure the reversal of the bit order of the Output data
+ * @rmtoll CR REV_OUT LL_CRC_SetOutputDataReverseMode
+ * @param CRCx CRC Instance
+ * @param ReverseMode This parameter can be one of the following values:
+ * @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
+ * @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRC_SetOutputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode)
+{
+ MODIFY_REG(CRCx->CR, CRC_CR_REV_OUT, ReverseMode);
+}
+
+/**
+ * @brief Configure the reversal of the bit order of the Output data
+ * @rmtoll CR REV_OUT LL_CRC_GetOutputDataReverseMode
+ * @param CRCx CRC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
+ * @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
+ */
+__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(CRC_TypeDef *CRCx)
+{
+ return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_OUT));
+}
+
+/**
+ * @brief Initialize the Programmable initial CRC value.
+ * @note If the CRC size is less than 32 bits, the least significant bits
+ * are used to write the correct value
+ * @note LL_CRC_DEFAULT_CRC_INITVALUE could be used as value for InitCrc parameter.
+ * @rmtoll INIT INIT LL_CRC_SetInitialData
+ * @param CRCx CRC Instance
+ * @param InitCrc Value to be programmed in Programmable initial CRC value register
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRC_SetInitialData(CRC_TypeDef *CRCx, uint32_t InitCrc)
+{
+ WRITE_REG(CRCx->INIT, InitCrc);
+}
+
+/**
+ * @brief Return current Initial CRC value.
+ * @note If the CRC size is less than 32 bits, the least significant bits
+ * are used to read the correct value
+ * @rmtoll INIT INIT LL_CRC_GetInitialData
+ * @param CRCx CRC Instance
+ * @retval Value programmed in Programmable initial CRC value register
+ */
+__STATIC_INLINE uint32_t LL_CRC_GetInitialData(CRC_TypeDef *CRCx)
+{
+ return (uint32_t)(READ_REG(CRCx->INIT));
+}
+
+/**
+ * @brief Initialize the Programmable polynomial value
+ * (coefficients of the polynomial to be used for CRC calculation).
+ * @note LL_CRC_DEFAULT_CRC32_POLY could be used as value for PolynomCoef parameter.
+ * @note Please check Reference Manual and existing Errata Sheets,
+ * regarding possible limitations for Polynomial values usage.
+ * For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
+ * @rmtoll POL POL LL_CRC_SetPolynomialCoef
+ * @param CRCx CRC Instance
+ * @param PolynomCoef Value to be programmed in Programmable Polynomial value register
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRC_SetPolynomialCoef(CRC_TypeDef *CRCx, uint32_t PolynomCoef)
+{
+ WRITE_REG(CRCx->POL, PolynomCoef);
+}
+
+/**
+ * @brief Return current Programmable polynomial value
+ * @note Please check Reference Manual and existing Errata Sheets,
+ * regarding possible limitations for Polynomial values usage.
+ * For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
+ * @rmtoll POL POL LL_CRC_GetPolynomialCoef
+ * @param CRCx CRC Instance
+ * @retval Value programmed in Programmable Polynomial value register
+ */
+__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(CRC_TypeDef *CRCx)
+{
+ return (uint32_t)(READ_REG(CRCx->POL));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_LL_EF_Data_Management Data_Management
+ * @{
+ */
+
+/**
+ * @brief Write given 32-bit data to the CRC calculator
+ * @rmtoll DR DR LL_CRC_FeedData32
+ * @param CRCx CRC Instance
+ * @param InData value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData)
+{
+ WRITE_REG(CRCx->DR, InData);
+}
+
+/**
+ * @brief Write given 16-bit data to the CRC calculator
+ * @rmtoll DR DR LL_CRC_FeedData16
+ * @param CRCx CRC Instance
+ * @param InData 16 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRC_FeedData16(CRC_TypeDef *CRCx, uint16_t InData)
+{
+ *(uint16_t __IO *)(&CRCx->DR) = (uint16_t) InData;
+}
+
+/**
+ * @brief Write given 8-bit data to the CRC calculator
+ * @rmtoll DR DR LL_CRC_FeedData8
+ * @param CRCx CRC Instance
+ * @param InData 8 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRC_FeedData8(CRC_TypeDef *CRCx, uint8_t InData)
+{
+ *(uint8_t __IO *)(&CRCx->DR) = (uint8_t) InData;
+}
+
+/**
+ * @brief Return current CRC calculation result. 32 bits value is returned.
+ * @rmtoll DR DR LL_CRC_ReadData32
+ * @param CRCx CRC Instance
+ * @retval Current CRC calculation result as stored in CRC_DR register (32 bits).
+ */
+__STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx)
+{
+ return (uint32_t)(READ_REG(CRCx->DR));
+}
+
+/**
+ * @brief Return current CRC calculation result. 16 bits value is returned.
+ * @note This function is expected to be used in a 16 bits CRC polynomial size context.
+ * @rmtoll DR DR LL_CRC_ReadData16
+ * @param CRCx CRC Instance
+ * @retval Current CRC calculation result as stored in CRC_DR register (16 bits).
+ */
+__STATIC_INLINE uint16_t LL_CRC_ReadData16(CRC_TypeDef *CRCx)
+{
+ return (uint16_t)READ_REG(CRCx->DR);
+}
+
+/**
+ * @brief Return current CRC calculation result. 8 bits value is returned.
+ * @note This function is expected to be used in a 8 bits CRC polynomial size context.
+ * @rmtoll DR DR LL_CRC_ReadData8
+ * @param CRCx CRC Instance
+ * @retval Current CRC calculation result as stored in CRC_DR register (8 bits).
+ */
+__STATIC_INLINE uint8_t LL_CRC_ReadData8(CRC_TypeDef *CRCx)
+{
+ return (uint8_t)READ_REG(CRCx->DR);
+}
+
+/**
+ * @brief Return current CRC calculation result. 7 bits value is returned.
+ * @note This function is expected to be used in a 7 bits CRC polynomial size context.
+ * @rmtoll DR DR LL_CRC_ReadData7
+ * @param CRCx CRC Instance
+ * @retval Current CRC calculation result as stored in CRC_DR register (7 bits).
+ */
+__STATIC_INLINE uint8_t LL_CRC_ReadData7(CRC_TypeDef *CRCx)
+{
+ return (uint8_t)(READ_REG(CRCx->DR) & 0x7FU);
+}
+
+/**
+ * @brief Return data stored in the Independent Data(IDR) register.
+ * @note This register can be used as a temporary storage location for one byte.
+ * @rmtoll IDR IDR LL_CRC_Read_IDR
+ * @param CRCx CRC Instance
+ * @retval Value stored in CRC_IDR register (General-purpose 8-bit data register).
+ */
+__STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx)
+{
+ return (uint32_t)(READ_REG(CRCx->IDR));
+}
+
+/**
+ * @brief Store data in the Independent Data(IDR) register.
+ * @note This register can be used as a temporary storage location for one byte.
+ * @rmtoll IDR IDR LL_CRC_Write_IDR
+ * @param CRCx CRC Instance
+ * @param InData value to be stored in CRC_IDR register (8-bit) between between Min_Data=0 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData)
+{
+ *((uint8_t __IO *)(&CRCx->IDR)) = (uint8_t) InData;
+}
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup CRC_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(CRC) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_LL_CRC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_ll_dac.h b/Inc/stm32f3xx_ll_dac.h
new file mode 100644
index 0000000..cf8bdcb
--- /dev/null
+++ b/Inc/stm32f3xx_ll_dac.h
@@ -0,0 +1,1526 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_dac.h
+ * @author MCD Application Team
+ * @brief Header file of DAC LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_LL_DAC_H
+#define __STM32F3xx_LL_DAC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx.h"
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined (DAC1) || defined (DAC2)
+
+/** @defgroup DAC_LL DAC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup DAC_LL_Private_Constants DAC Private Constants
+ * @{
+ */
+
+/* Internal masks for DAC channels definition */
+/* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
+/* - channel bits position into register CR */
+/* - channel bits position into register SWTRIG */
+/* - channel register offset of data holding register DHRx */
+/* - channel register offset of data output register DORx */
+#define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
+#define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
+#define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
+
+#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
+#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
+#else
+#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1)
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+#define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */
+#define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
+#define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
+#define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
+#define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
+#endif /* DAC_CHANNEL2_SUPPORT */
+#define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U
+#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U
+#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U
+#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
+
+#define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */
+#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
+#else
+#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET)
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+/* DAC registers bits positions */
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS 16U /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */
+#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS 20U /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */
+#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS 8U /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+/* Miscellaneous data */
+#define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
+
+/**
+ * @}
+ */
+
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DAC_LL_Private_Macros DAC Private Macros
+ * @{
+ */
+
+/**
+ * @brief Driver macro reserved for internal use: isolate bits with the
+ * selected mask and shift them to the register LSB
+ * (shift mask on register position bit 0).
+ * @param __BITS__ Bits in register 32 bits
+ * @param __MASK__ Mask in register 32 bits
+ * @retval Bits in register 32 bits
+*/
+#define __DAC_MASK_SHIFT(__BITS__, __MASK__) \
+ (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
+
+/**
+ * @brief Driver macro reserved for internal use: set a pointer to
+ * a register from a register basis from which an offset
+ * is applied.
+ * @param __REG__ Register basis from which the offset is applied.
+ * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
+ * @retval Pointer to register address
+*/
+#define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
+ ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
+
+/**
+ * @}
+ */
+
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief Structure definition of some features of DAC instance.
+ */
+typedef struct
+{
+ uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line).
+ This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
+
+ This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */
+
+ uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
+ This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
+
+ This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
+
+ uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
+ If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
+ If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
+ @note If waveform automatic generation mode is disabled, this parameter is discarded.
+
+ This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */
+
+ uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
+ This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
+
+ This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
+
+} LL_DAC_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
+ * @{
+ */
+
+/** @defgroup DAC_LL_EC_GET_FLAG DAC flags
+ * @brief Flags defines which can be used with LL_DAC_ReadReg function
+ * @{
+ */
+/* DAC channel 1 flags */
+#define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
+
+#if defined(DAC_CHANNEL2_SUPPORT)
+/* DAC channel 2 flags */
+#define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */
+#endif /* DAC_CHANNEL2_SUPPORT */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_IT DAC interruptions
+ * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
+ * @{
+ */
+#define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
+#endif /* DAC_CHANNEL2_SUPPORT */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_CHANNEL DAC channels
+ * @{
+ */
+#define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
+#endif /* DAC_CHANNEL2_SUPPORT */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
+ * @{
+ */
+#define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */
+#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
+#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. Trigger remap: by default, default trigger. If needed to restore trigger, use @ref LL_SYSCFG_DAC1_TRIG1_REMAP_TIM3_TRGO for TIM3 selection. */
+#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM8_TRGO (LL_DAC_TRIG_EXT_TIM3_TRGO) /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. Trigger remap: use @ref LL_SYSCFG_DAC1_TRIG1_REMAP_TIM8_TRGO for TIM8 selection. */
+#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
+
+#elif defined(STM32F303x8) || defined(STM32F328xx)
+#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
+#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
+
+#elif defined(STM32F302xE) || defined(STM32F302xC) || defined(STM32F302x8)
+#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 ) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
+#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
+
+#elif defined(STM32F301x8) || defined(STM32F318xx)
+#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
+#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
+
+#elif defined(STM32F373xC) || defined(STM32F378xx)
+#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM18_TRGO (LL_DAC_TRIG_EXT_TIM5_TRGO) /*!< DAC channel conversion trigger from external IP: TIM18 TRGO. */
+#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
+
+#elif defined(STM32F334x8)
+#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. Trigger remap: by default, default trigger. If needed to restore trigger, use @ref LL_SYSCFG_DAC1_TRIG1_REMAP_TIM3_TRGO for TIM3 selection. */
+#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM15 TRGO. Trigger remap: by default, default trigger. If needed to restore trigger, use @ref LL_SYSCFG_DAC1_TRIG3_REMAP_TIM15_TRGO for TIM15 selection. */
+#define LL_DAC_TRIGGER_HRTIM1_DACTRG1 (LL_DAC_TRIG_EXT_TIM15_TRGO) /*!< DAC channel conversion trigger from external IP: HRTIM1 DACTRG1. Available only on DAC instance: DAC1. Trigger remap: use @ref LL_SYSCFG_DAC1_TRIG3_REMAP_HRTIM1_DAC1_TRIG1 for HRTIM1 TRIG1 selection. */
+#define LL_DAC_TRIGGER_HRTIM1_DACTRG2 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: HRTIM1 DACTRG2. Available only on DAC instance: DAC2. Trigger remap: use @ref LL_SYSCFG_DAC1_TRIG5_REMAP_HRTIM1_DAC1_TRIG2 for HRTIM1 TRIG2 selection. */
+#define LL_DAC_TRIGGER_HRTIM1_DACTRG3 (LL_DAC_TRIGGER_HRTIM1_DACTRG2) /*!< DAC channel conversion trigger from external IP: HRTIM1 DACTRG3. */
+#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
+
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
+ * @{
+ */
+#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /*!< DAC channel wave auto generation mode disabled. */
+#define LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
+#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
+ * @{
+ */
+#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
+ * @{
+ */
+#define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
+ * @{
+ */
+#define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
+#define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
+
+#if defined(DAC_CR_OUTEN1) || defined(DAC_CR_OUTEN2)
+#define LL_DAC_OUTPUT_SWITCH_DISABLE (LL_DAC_OUTPUT_BUFFER_ENABLE) /*!< Feature specific to STM32F303x6/8 and STM32F328: On DAC1 channel 2, output buffer is replaced by a switch to connect DAC channel output to pin PA5. On DAC2 channel 1, output buffer is replaced by a switch to connect DAC channel output to pin PA6. Selection of switch disabled: DAC channel output not connected to GPIO. */
+#define LL_DAC_OUTPUT_SWITCH_ENABLE (LL_DAC_OUTPUT_BUFFER_DISABLE) /*!< Feature specific to STM32F303x6/8 and STM32F328: On DAC1 channel 2, output buffer is replaced by a switch to connect DAC channel output to pin PA5. On DAC2 channel 1, output buffer is replaced by a switch to connect DAC channel output to pin PA6. */
+#endif
+/**
+ * @}
+ */
+
+
+/** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
+ * @{
+ */
+#define LL_DAC_RESOLUTION_12B 0x00000000U /*!< DAC channel resolution 12 bits */
+#define LL_DAC_RESOLUTION_8B 0x00000002U /*!< DAC channel resolution 8 bits */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
+ * @{
+ */
+/* List of DAC registers intended to be used (most commonly) with */
+/* DMA transfer. */
+/* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
+#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits right aligned */
+#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits left aligned */
+#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_MASK /*!< DAC channel data holding register 8 bits right aligned */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
+ * @note Only DAC IP HW delays are defined in DAC LL driver driver,
+ * not timeout values.
+ * For details on delays values, refer to descriptions in source code
+ * above each literal definition.
+ * @{
+ */
+
+/* Delay for DAC channel voltage settling time from DAC channel startup */
+/* (transition from disable to enable). */
+/* Note: DAC channel startup time depends on board application environment: */
+/* impedance connected to DAC channel output. */
+/* The delay below is specified under conditions: */
+/* - voltage maximum transition (lowest to highest value) */
+/* - until voltage reaches final value +-1LSB */
+/* - DAC channel output buffer enabled */
+/* - load impedance of 5kOhm (min), 50pF (max) */
+/* Literal set to maximum value (refer to device datasheet, */
+/* parameter "tWAKEUP"). */
+/* Unit: us */
+#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15U /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
+
+/* Delay for DAC channel voltage settling time. */
+/* Note: DAC channel startup time depends on board application environment: */
+/* impedance connected to DAC channel output. */
+/* The delay below is specified under conditions: */
+/* - voltage maximum transition (lowest to highest value) */
+/* - until voltage reaches final value +-1LSB */
+/* - DAC channel output buffer enabled */
+/* - load impedance of 5kOhm min, 50pF max */
+/* Literal set to maximum value (refer to device datasheet, */
+/* parameter "tSETTLING"). */
+/* Unit: us */
+#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12U /*!< Delay for DAC channel voltage settling time */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
+ * @{
+ */
+
+/** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in DAC register
+ * @param __INSTANCE__ DAC Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in DAC register
+ * @param __INSTANCE__ DAC Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
+ * @{
+ */
+
+/**
+ * @brief Helper macro to get DAC channel number in decimal format
+ * from literals LL_DAC_CHANNEL_x.
+ * Example:
+ * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
+ * will return decimal number "1".
+ * @note The input can be a value from functions where a channel
+ * number is returned.
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval 1...2 (value "2" depending on DAC channel 2 availability)
+ */
+#define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
+ ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
+
+/**
+ * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
+ * from number in decimal format.
+ * Example:
+ * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
+ * will return a data equivalent to "LL_DAC_CHANNEL_1".
+ * @note If the input parameter does not correspond to a DAC channel,
+ * this macro returns value '0'.
+ * @param __DECIMAL_NB__ 1...2 (value "2" depending on DAC channel 2 availability)
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ */
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
+ (((__DECIMAL_NB__) == 1U) \
+ ? ( \
+ LL_DAC_CHANNEL_1 \
+ ) \
+ : \
+ (((__DECIMAL_NB__) == 2U) \
+ ? ( \
+ LL_DAC_CHANNEL_2 \
+ ) \
+ : \
+ ( \
+ 0 \
+ ) \
+ ) \
+ )
+#else
+#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
+ (((__DECIMAL_NB__) == 1U) \
+ ? ( \
+ LL_DAC_CHANNEL_1 \
+ ) \
+ : \
+ ( \
+ 0 \
+ ) \
+ )
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+/**
+ * @brief Helper macro to define the DAC conversion data full-scale digital
+ * value corresponding to the selected DAC resolution.
+ * @note DAC conversion data full-scale corresponds to voltage range
+ * determined by analog voltage references Vref+ and Vref-
+ * (refer to reference manual).
+ * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_DAC_RESOLUTION_12B
+ * @arg @ref LL_DAC_RESOLUTION_8B
+ * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+ */
+#define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
+ ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U))
+
+/**
+ * @brief Helper macro to calculate the DAC conversion data (unit: digital
+ * value) corresponding to a voltage (unit: mVolt).
+ * @note This helper macro is intended to provide input data in voltage
+ * rather than digital value,
+ * to be used with LL DAC functions such as
+ * @ref LL_DAC_ConvertData12RightAligned().
+ * @note Analog reference voltage (Vref+) must be either known from
+ * user board environment or can be calculated using ADC measurement
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+ * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
+ * (unit: mVolt).
+ * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_DAC_RESOLUTION_12B
+ * @arg @ref LL_DAC_RESOLUTION_8B
+ * @retval DAC conversion data (unit: digital value)
+ */
+#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
+ __DAC_VOLTAGE__,\
+ __DAC_RESOLUTION__) \
+ ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
+ / (__VREFANALOG_VOLTAGE__) \
+ )
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
+ * @{
+ */
+/** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
+ * @{
+ */
+
+/**
+ * @brief Set the conversion trigger source for the selected DAC channel.
+ * @note For conversion trigger source to be effective, DAC trigger
+ * must be enabled using function @ref LL_DAC_EnableTrigger().
+ * @note To set conversion trigger source, DAC channel must be disabled.
+ * Otherwise, the setting is discarded.
+ * @note Availability of parameters of trigger sources from timer
+ * depends on timers availability on the selected device.
+ * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
+ * CR TSEL2 LL_DAC_SetTriggerSource
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @param TriggerSource This parameter can be one of the following values:
+ * @arg @ref LL_DAC_TRIG_SOFTWARE
+ * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO (1)
+ * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO (1)
+ * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO (1)
+ * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO (1)
+ * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO (1)
+ * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO (1)
+ * @arg @ref LL_DAC_TRIG_EXT_TIM18_TRGO (1)
+ * @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG1 (1)
+ * @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG2 (1)(2)
+ * @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG3 (1) (3)
+ * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
+ *
+ * (1) On STM32F3, parameter not available on all devices
+ * (2) On STM32F3, parameter not available on all DAC instances: DAC1 (for DAC instances DACx available on the selected device).\n
+ * (3) On STM32F3, parameter not available on all DAC instances: DAC2 (for DAC instances DACx available on the selected device).
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
+{
+ MODIFY_REG(DACx->CR,
+ DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+ TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Get the conversion trigger source for the selected DAC channel.
+ * @note For conversion trigger source to be effective, DAC trigger
+ * must be enabled using function @ref LL_DAC_EnableTrigger().
+ * @note Availability of parameters of trigger sources from timer
+ * depends on timers availability on the selected device.
+ * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
+ * CR TSEL2 LL_DAC_GetTriggerSource
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DAC_TRIG_SOFTWARE
+ * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO (1)
+ * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO (1)
+ * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO (1)
+ * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO (1)
+ * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO (1)
+ * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO (1)
+ * @arg @ref LL_DAC_TRIG_EXT_TIM18_TRGO (1)
+ * @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG1 (1)
+ * @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG2 (1)(2)
+ * @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG3 (1) (3)
+ * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
+ *
+ * (1) On STM32F3, parameter not available on all devices
+ * (2) On STM32F3, parameter not available on all DAC instances: DAC1 (for DAC instances DACx available on the selected device).\n
+ * (3) On STM32F3, parameter not available on all DAC instances: DAC2 (for DAC instances DACx available on the selected device).
+ */
+__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ );
+}
+
+/**
+ * @brief Set the waveform automatic generation mode
+ * for the selected DAC channel.
+ * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
+ * CR WAVE2 LL_DAC_SetWaveAutoGeneration
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @param WaveAutoGeneration This parameter can be one of the following values:
+ * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
+ * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
+ * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
+{
+ MODIFY_REG(DACx->CR,
+ DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+ WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Get the waveform automatic generation mode
+ * for the selected DAC channel.
+ * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
+ * CR WAVE2 LL_DAC_GetWaveAutoGeneration
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
+ * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
+ * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
+ */
+__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ );
+}
+
+/**
+ * @brief Set the noise waveform generation for the selected DAC channel:
+ * Noise mode and parameters LFSR (linear feedback shift register).
+ * @note For wave generation to be effective, DAC channel
+ * wave generation mode must be enabled using
+ * function @ref LL_DAC_SetWaveAutoGeneration().
+ * @note This setting can be set when the selected DAC channel is disabled
+ * (otherwise, the setting operation is ignored).
+ * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
+ * CR MAMP2 LL_DAC_SetWaveNoiseLFSR
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @param NoiseLFSRMask This parameter can be one of the following values:
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
+{
+ MODIFY_REG(DACx->CR,
+ DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+ NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Set the noise waveform generation for the selected DAC channel:
+ * Noise mode and parameters LFSR (linear feedback shift register).
+ * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
+ * CR MAMP2 LL_DAC_GetWaveNoiseLFSR
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
+ */
+__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ );
+}
+
+/**
+ * @brief Set the triangle waveform generation for the selected DAC channel:
+ * triangle mode and amplitude.
+ * @note For wave generation to be effective, DAC channel
+ * wave generation mode must be enabled using
+ * function @ref LL_DAC_SetWaveAutoGeneration().
+ * @note This setting can be set when the selected DAC channel is disabled
+ * (otherwise, the setting operation is ignored).
+ * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
+ * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @param TriangleAmplitude This parameter can be one of the following values:
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
+{
+ MODIFY_REG(DACx->CR,
+ DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+ TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Set the triangle waveform generation for the selected DAC channel:
+ * triangle mode and amplitude.
+ * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
+ * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
+ */
+__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ );
+}
+
+/**
+ * @brief Set the output buffer for the selected DAC channel.
+ * @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n
+ * CR BOFF2 LL_DAC_SetOutputBuffer
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @param OutputBuffer This parameter can be one of the following values:
+ * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
+ * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
+ * @arg @ref LL_DAC_OUTPUT_SWITCH_DISABLE (1)
+ * @arg @ref LL_DAC_OUTPUT_SWITCH_ENABLE (1)
+ *
+ * (1) Feature specific to STM32F303x6/8 and STM32F328:
+ * On DAC1 channel 2, output buffer is replaced by a switch
+ * to connect DAC channel output to pin PA5.
+ * On DAC2 channel 1, output buffer is replaced by a switch
+ * to connect DAC channel output to pin PA6.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
+{
+ MODIFY_REG(DACx->CR,
+ DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+ OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Get the output buffer state for the selected DAC channel.
+ * @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n
+ * CR BOFF2 LL_DAC_GetOutputBuffer
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
+ * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
+ * @arg @ref LL_DAC_OUTPUT_SWITCH_DISABLE (1)
+ * @arg @ref LL_DAC_OUTPUT_SWITCH_ENABLE (1)
+ *
+ * (1) Feature specific to STM32F303x6/8 and STM32F328:
+ * On DAC1 channel 2, output buffer is replaced by a switch
+ * to connect DAC channel output to pin PA5.
+ * On DAC2 channel 1, output buffer is replaced by a switch
+ * to connect DAC channel output to pin PA6.
+ */
+__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ );
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EF_DMA_Management DMA Management
+ * @{
+ */
+
+/**
+ * @brief Enable DAC DMA transfer request of the selected channel.
+ * @note To configure DMA source address (peripheral address),
+ * use function @ref LL_DAC_DMA_GetRegAddr().
+ * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
+ * CR DMAEN2 LL_DAC_EnableDMAReq
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ SET_BIT(DACx->CR,
+ DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Disable DAC DMA transfer request of the selected channel.
+ * @note To configure DMA source address (peripheral address),
+ * use function @ref LL_DAC_DMA_GetRegAddr().
+ * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
+ * CR DMAEN2 LL_DAC_DisableDMAReq
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ CLEAR_BIT(DACx->CR,
+ DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Get DAC DMA transfer request state of the selected channel.
+ * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
+ * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
+ * CR DMAEN2 LL_DAC_IsDMAReqEnabled
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ return (READ_BIT(DACx->CR,
+ DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
+}
+
+/**
+ * @brief Function to help to configure DMA transfer to DAC: retrieve the
+ * DAC register address from DAC instance and a list of DAC registers
+ * intended to be used (most commonly) with DMA transfer.
+ * @note These DAC registers are data holding registers:
+ * when DAC conversion is requested, DAC generates a DMA transfer
+ * request to have data available in DAC data holding registers.
+ * @note This macro is intended to be used with LL DMA driver, refer to
+ * function "LL_DMA_ConfigAddresses()".
+ * Example:
+ * LL_DMA_ConfigAddresses(DMA1,
+ * LL_DMA_CHANNEL_1,
+ * (uint32_t)&< array or variable >,
+ * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
+ * LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
+ * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
+ * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
+ * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
+ * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
+ * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
+ * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @param Register This parameter can be one of the following values:
+ * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
+ * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
+ * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
+ * @retval DAC register address
+ */
+__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
+{
+ /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
+ /* DAC channel selected. */
+ return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, Register))));
+}
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EF_Operation Operation on DAC channels
+ * @{
+ */
+
+/**
+ * @brief Enable DAC selected channel.
+ * @rmtoll CR EN1 LL_DAC_Enable\n
+ * CR EN2 LL_DAC_Enable
+ * @note After enable from off state, DAC channel requires a delay
+ * for output voltage to reach accuracy +/- 1 LSB.
+ * Refer to device datasheet, parameter "tWAKEUP".
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ SET_BIT(DACx->CR,
+ DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Disable DAC selected channel.
+ * @rmtoll CR EN1 LL_DAC_Disable\n
+ * CR EN2 LL_DAC_Disable
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ CLEAR_BIT(DACx->CR,
+ DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Get DAC enable state of the selected channel.
+ * (0: DAC channel is disabled, 1: DAC channel is enabled)
+ * @rmtoll CR EN1 LL_DAC_IsEnabled\n
+ * CR EN2 LL_DAC_IsEnabled
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ return (READ_BIT(DACx->CR,
+ DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
+}
+
+/**
+ * @brief Enable DAC trigger of the selected channel.
+ * @note - If DAC trigger is disabled, DAC conversion is performed
+ * automatically once the data holding register is updated,
+ * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
+ * @ref LL_DAC_ConvertData12RightAligned(), ...
+ * - If DAC trigger is enabled, DAC conversion is performed
+ * only when a hardware of software trigger event is occurring.
+ * Select trigger source using
+ * function @ref LL_DAC_SetTriggerSource().
+ * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
+ * CR TEN2 LL_DAC_EnableTrigger
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ SET_BIT(DACx->CR,
+ DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Disable DAC trigger of the selected channel.
+ * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
+ * CR TEN2 LL_DAC_DisableTrigger
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ CLEAR_BIT(DACx->CR,
+ DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Get DAC trigger state of the selected channel.
+ * (0: DAC trigger is disabled, 1: DAC trigger is enabled)
+ * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
+ * CR TEN2 LL_DAC_IsTriggerEnabled
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ return (READ_BIT(DACx->CR,
+ DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
+}
+
+/**
+ * @brief Trig DAC conversion by software for the selected DAC channel.
+ * @note Preliminarily, DAC trigger must be set to software trigger
+ * using function @ref LL_DAC_SetTriggerSource()
+ * with parameter "LL_DAC_TRIGGER_SOFTWARE".
+ * and DAC trigger must be enabled using
+ * function @ref LL_DAC_EnableTrigger().
+ * @note For devices featuring DAC with 2 channels: this function
+ * can perform a SW start of both DAC channels simultaneously.
+ * Two channels can be selected as parameter.
+ * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
+ * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
+ * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can a combination of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ SET_BIT(DACx->SWTRIGR,
+ (DAC_Channel & DAC_SWTR_CHX_MASK));
+}
+
+/**
+ * @brief Set the data to be loaded in the data holding register
+ * in format 12 bits left alignment (LSB aligned on bit 0),
+ * for the selected DAC channel.
+ * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
+ * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
+{
+ register __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12RX_REGOFFSET_MASK));
+
+ MODIFY_REG(*preg,
+ DAC_DHR12R1_DACC1DHR,
+ Data);
+}
+
+/**
+ * @brief Set the data to be loaded in the data holding register
+ * in format 12 bits left alignment (MSB aligned on bit 15),
+ * for the selected DAC channel.
+ * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
+ * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
+{
+ register __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12LX_REGOFFSET_MASK));
+
+ MODIFY_REG(*preg,
+ DAC_DHR12L1_DACC1DHR,
+ Data);
+}
+
+/**
+ * @brief Set the data to be loaded in the data holding register
+ * in format 8 bits left alignment (LSB aligned on bit 0),
+ * for the selected DAC channel.
+ * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
+ * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
+{
+ register __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR8RX_REGOFFSET_MASK));
+
+ MODIFY_REG(*preg,
+ DAC_DHR8R1_DACC1DHR,
+ Data);
+}
+
+#if defined(DAC_CHANNEL2_SUPPORT)
+/**
+ * @brief Set the data to be loaded in the data holding register
+ * in format 12 bits left alignment (LSB aligned on bit 0),
+ * for both DAC channels.
+ * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
+ * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
+ * @param DACx DAC instance
+ * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
+{
+ MODIFY_REG(DACx->DHR12RD,
+ (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
+ ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
+}
+
+/**
+ * @brief Set the data to be loaded in the data holding register
+ * in format 12 bits left alignment (MSB aligned on bit 15),
+ * for both DAC channels.
+ * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
+ * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
+ * @param DACx DAC instance
+ * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
+{
+ /* Note: Data of DAC channel 2 shift value subtracted of 4 because */
+ /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
+ /* the 4 LSB must be taken into account for the shift value. */
+ MODIFY_REG(DACx->DHR12LD,
+ (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
+ ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
+}
+
+/**
+ * @brief Set the data to be loaded in the data holding register
+ * in format 8 bits left alignment (LSB aligned on bit 0),
+ * for both DAC channels.
+ * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
+ * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
+ * @param DACx DAC instance
+ * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
+ * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
+{
+ MODIFY_REG(DACx->DHR8RD,
+ (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
+ ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
+}
+
+#endif /* DAC_CHANNEL2_SUPPORT */
+/**
+ * @brief Retrieve output data currently generated for the selected DAC channel.
+ * @note Whatever alignment and resolution settings
+ * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
+ * @ref LL_DAC_ConvertData12RightAligned(), ...),
+ * output data format is 12 bits right aligned (LSB aligned on bit 0).
+ * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
+ * DOR2 DACC2DOR LL_DAC_RetrieveOutputData
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ register __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DORX_REGOFFSET_MASK));
+
+ return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
+ * @{
+ */
+/**
+ * @brief Get DAC underrun flag for DAC channel 1
+ * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
+ * @param DACx DAC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
+{
+ return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1));
+}
+
+#if defined(DAC_CHANNEL2_SUPPORT)
+/**
+ * @brief Get DAC underrun flag for DAC channel 2
+ * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
+ * @param DACx DAC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
+{
+ return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2));
+}
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+/**
+ * @brief Clear DAC underrun flag for DAC channel 1
+ * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
+ * @param DACx DAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
+{
+ WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
+}
+
+#if defined(DAC_CHANNEL2_SUPPORT)
+/**
+ * @brief Clear DAC underrun flag for DAC channel 2
+ * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
+ * @param DACx DAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
+{
+ WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
+}
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EF_IT_Management IT management
+ * @{
+ */
+
+/**
+ * @brief Enable DMA underrun interrupt for DAC channel 1
+ * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
+ * @param DACx DAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
+{
+ SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
+}
+
+#if defined(DAC_CHANNEL2_SUPPORT)
+/**
+ * @brief Enable DMA underrun interrupt for DAC channel 2
+ * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
+ * @param DACx DAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
+{
+ SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
+}
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+/**
+ * @brief Disable DMA underrun interrupt for DAC channel 1
+ * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
+ * @param DACx DAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
+{
+ CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
+}
+
+#if defined(DAC_CHANNEL2_SUPPORT)
+/**
+ * @brief Disable DMA underrun interrupt for DAC channel 2
+ * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
+ * @param DACx DAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
+{
+ CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
+}
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+/**
+ * @brief Get DMA underrun interrupt for DAC channel 1
+ * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
+ * @param DACx DAC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
+{
+ return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1));
+}
+
+#if defined(DAC_CHANNEL2_SUPPORT)
+/**
+ * @brief Get DMA underrun interrupt for DAC channel 2
+ * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
+ * @param DACx DAC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
+{
+ return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2));
+}
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx);
+ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct);
+void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* DAC1 || DAC2 */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_LL_DAC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_ll_dma.h b/Inc/stm32f3xx_ll_dma.h
new file mode 100644
index 0000000..1a8cae9
--- /dev/null
+++ b/Inc/stm32f3xx_ll_dma.h
@@ -0,0 +1,2012 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_dma.h
+ * @author MCD Application Team
+ * @brief Header file of DMA LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_LL_DMA_H
+#define __STM32F3xx_LL_DMA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx.h"
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined (DMA1) || defined (DMA2)
+
+/** @defgroup DMA_LL DMA
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup DMA_LL_Private_Variables DMA Private Variables
+ * @{
+ */
+/* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
+static const uint8_t CHANNEL_OFFSET_TAB[] =
+{
+ (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
+ (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
+ (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
+ (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
+ (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
+ (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
+ (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
+};
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA_LL_Private_Macros DMA Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
+ * @{
+ */
+typedef struct
+{
+ uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
+ or as Source base address in case of memory to memory transfer direction.
+
+ This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
+
+ uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
+ or as Destination base address in case of memory to memory transfer direction.
+
+ This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
+
+ uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
+ from memory to memory or from peripheral to memory.
+ This parameter can be a value of @ref DMA_LL_EC_DIRECTION
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
+
+ uint32_t Mode; /*!< Specifies the normal or circular operation mode.
+ This parameter can be a value of @ref DMA_LL_EC_MODE
+ @note: The circular buffer mode cannot be used if the memory to memory
+ data transfer direction is configured on the selected Channel
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
+
+ uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
+ is incremented or not.
+ This parameter can be a value of @ref DMA_LL_EC_PERIPH
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
+
+ uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
+ is incremented or not.
+ This parameter can be a value of @ref DMA_LL_EC_MEMORY
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
+
+ uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
+ in case of memory to memory transfer direction.
+ This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
+
+ uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
+ in case of memory to memory transfer direction.
+ This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
+
+ uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
+ The data unit is equal to the source buffer configuration set in PeripheralSize
+ or MemorySize parameters depending in the transfer direction.
+ This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
+
+ uint32_t Priority; /*!< Specifies the channel priority level.
+ This parameter can be a value of @ref DMA_LL_EC_PRIORITY
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
+
+} LL_DMA_InitTypeDef;
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
+ * @{
+ */
+/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
+ * @brief Flags defines which can be used with LL_DMA_WriteReg function
+ * @{
+ */
+#define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */
+#define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */
+#define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */
+#define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */
+#define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */
+#define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */
+#define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */
+#define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */
+#define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */
+#define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */
+#define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */
+#define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */
+#define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */
+#define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */
+#define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */
+#define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */
+#define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */
+#define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */
+#define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */
+#define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */
+#define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_DMA_ReadReg function
+ * @{
+ */
+#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */
+#define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */
+#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */
+#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */
+#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */
+#define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */
+#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */
+#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */
+#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */
+#define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */
+#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */
+#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */
+#define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */
+#define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */
+#define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */
+#define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */
+#define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */
+#define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */
+#define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */
+#define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */
+#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */
+#define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */
+#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */
+#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */
+#define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */
+#define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */
+#define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */
+#define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
+ * @{
+ */
+#define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */
+#define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */
+#define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_CHANNEL CHANNEL
+ * @{
+ */
+#define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */
+#define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */
+#define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */
+#define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */
+#define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */
+#define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */
+#define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */
+#if defined(USE_FULL_LL_DRIVER)
+#define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
+#endif /*USE_FULL_LL_DRIVER*/
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
+ * @{
+ */
+#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
+#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */
+#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_MODE Transfer mode
+ * @{
+ */
+#define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
+#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
+ * @{
+ */
+#define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */
+#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_MEMORY Memory increment mode
+ * @{
+ */
+#define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */
+#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
+ * @{
+ */
+#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
+#define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
+#define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
+ * @{
+ */
+#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
+#define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
+#define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
+ * @{
+ */
+#define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
+#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
+#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
+#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
+ * @{
+ */
+
+/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
+ * @{
+ */
+/**
+ * @brief Write a value in DMA register
+ * @param __INSTANCE__ DMA Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in DMA register
+ * @param __INSTANCE__ DMA Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
+ * @{
+ */
+/**
+ * @brief Convert DMAx_Channely into DMAx
+ * @param __CHANNEL_INSTANCE__ DMAx_Channely
+ * @retval DMAx
+ */
+#if defined(DMA2)
+#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
+(((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
+#else
+#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
+#endif
+
+/**
+ * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
+ * @param __CHANNEL_INSTANCE__ DMAx_Channely
+ * @retval LL_DMA_CHANNEL_y
+ */
+#if defined (DMA2)
+#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
+#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
+(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
+ LL_DMA_CHANNEL_7)
+#else
+#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
+(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
+ LL_DMA_CHANNEL_7)
+#endif
+#else
+#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
+(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
+ LL_DMA_CHANNEL_7)
+#endif
+
+/**
+ * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
+ * @param __DMA_INSTANCE__ DMAx
+ * @param __CHANNEL__ LL_DMA_CHANNEL_y
+ * @retval DMAx_Channely
+ */
+#if defined (DMA2)
+#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
+#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
+((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
+ DMA2_Channel7)
+#else
+#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
+((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
+ DMA1_Channel7)
+#endif
+#else
+#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
+((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
+ DMA1_Channel7)
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
+ * @{
+ */
+
+/** @defgroup DMA_LL_EF_Configuration Configuration
+ * @{
+ */
+/**
+ * @brief Enable DMA channel.
+ * @rmtoll CCR EN LL_DMA_EnableChannel
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
+}
+
+/**
+ * @brief Disable DMA channel.
+ * @rmtoll CCR EN LL_DMA_DisableChannel
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
+}
+
+/**
+ * @brief Check if DMA channel is enabled or disabled.
+ * @rmtoll CCR EN LL_DMA_IsEnabledChannel
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_EN) == (DMA_CCR_EN));
+}
+
+/**
+ * @brief Configure all parameters link to DMA transfer.
+ * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
+ * CCR MEM2MEM LL_DMA_ConfigTransfer\n
+ * CCR CIRC LL_DMA_ConfigTransfer\n
+ * CCR PINC LL_DMA_ConfigTransfer\n
+ * CCR MINC LL_DMA_ConfigTransfer\n
+ * CCR PSIZE LL_DMA_ConfigTransfer\n
+ * CCR MSIZE LL_DMA_ConfigTransfer\n
+ * CCR PL LL_DMA_ConfigTransfer
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param Configuration This parameter must be a combination of all the following values:
+ * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+ * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
+ * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
+ * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
+ * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
+ * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
+ * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
+{
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
+ Configuration);
+}
+
+/**
+ * @brief Set Data transfer direction (read from peripheral or from memory).
+ * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
+ * CCR MEM2MEM LL_DMA_SetDataTransferDirection
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param Direction This parameter can be one of the following values:
+ * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+ * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+ * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
+{
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
+}
+
+/**
+ * @brief Get Data transfer direction (read from peripheral or from memory).
+ * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
+ * CCR MEM2MEM LL_DMA_GetDataTransferDirection
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+ * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+ * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_DIR | DMA_CCR_MEM2MEM));
+}
+
+/**
+ * @brief Set DMA mode circular or normal.
+ * @note The circular buffer mode cannot be used if the memory-to-memory
+ * data transfer is configured on the selected Channel.
+ * @rmtoll CCR CIRC LL_DMA_SetMode
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_DMA_MODE_NORMAL
+ * @arg @ref LL_DMA_MODE_CIRCULAR
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
+{
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
+ Mode);
+}
+
+/**
+ * @brief Get DMA mode circular or normal.
+ * @rmtoll CCR CIRC LL_DMA_GetMode
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_MODE_NORMAL
+ * @arg @ref LL_DMA_MODE_CIRCULAR
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_CIRC));
+}
+
+/**
+ * @brief Set Peripheral increment mode.
+ * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
+ * @arg @ref LL_DMA_PERIPH_INCREMENT
+ * @arg @ref LL_DMA_PERIPH_NOINCREMENT
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
+{
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
+ PeriphOrM2MSrcIncMode);
+}
+
+/**
+ * @brief Get Peripheral increment mode.
+ * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_PERIPH_INCREMENT
+ * @arg @ref LL_DMA_PERIPH_NOINCREMENT
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_PINC));
+}
+
+/**
+ * @brief Set Memory increment mode.
+ * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
+ * @arg @ref LL_DMA_MEMORY_INCREMENT
+ * @arg @ref LL_DMA_MEMORY_NOINCREMENT
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
+{
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
+ MemoryOrM2MDstIncMode);
+}
+
+/**
+ * @brief Get Memory increment mode.
+ * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_MEMORY_INCREMENT
+ * @arg @ref LL_DMA_MEMORY_NOINCREMENT
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_MINC));
+}
+
+/**
+ * @brief Set Peripheral size.
+ * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
+ * @arg @ref LL_DMA_PDATAALIGN_BYTE
+ * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
+ * @arg @ref LL_DMA_PDATAALIGN_WORD
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
+{
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
+ PeriphOrM2MSrcDataSize);
+}
+
+/**
+ * @brief Get Peripheral size.
+ * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_PDATAALIGN_BYTE
+ * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
+ * @arg @ref LL_DMA_PDATAALIGN_WORD
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_PSIZE));
+}
+
+/**
+ * @brief Set Memory size.
+ * @rmtoll CCR MSIZE LL_DMA_SetMemorySize
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
+ * @arg @ref LL_DMA_MDATAALIGN_BYTE
+ * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
+ * @arg @ref LL_DMA_MDATAALIGN_WORD
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
+{
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
+ MemoryOrM2MDstDataSize);
+}
+
+/**
+ * @brief Get Memory size.
+ * @rmtoll CCR MSIZE LL_DMA_GetMemorySize
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_MDATAALIGN_BYTE
+ * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
+ * @arg @ref LL_DMA_MDATAALIGN_WORD
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_MSIZE));
+}
+
+/**
+ * @brief Set Channel priority level.
+ * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param Priority This parameter can be one of the following values:
+ * @arg @ref LL_DMA_PRIORITY_LOW
+ * @arg @ref LL_DMA_PRIORITY_MEDIUM
+ * @arg @ref LL_DMA_PRIORITY_HIGH
+ * @arg @ref LL_DMA_PRIORITY_VERYHIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
+{
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
+ Priority);
+}
+
+/**
+ * @brief Get Channel priority level.
+ * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_PRIORITY_LOW
+ * @arg @ref LL_DMA_PRIORITY_MEDIUM
+ * @arg @ref LL_DMA_PRIORITY_HIGH
+ * @arg @ref LL_DMA_PRIORITY_VERYHIGH
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_PL));
+}
+
+/**
+ * @brief Set Number of data to transfer.
+ * @note This action has no effect if
+ * channel is enabled.
+ * @rmtoll CNDTR NDT LL_DMA_SetDataLength
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
+{
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
+ DMA_CNDTR_NDT, NbData);
+}
+
+/**
+ * @brief Get Number of data to transfer.
+ * @note Once the channel is enabled, the return value indicate the
+ * remaining bytes to be transmitted.
+ * @rmtoll CNDTR NDT LL_DMA_GetDataLength
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
+ DMA_CNDTR_NDT));
+}
+
+/**
+ * @brief Configure the Source and Destination addresses.
+ * @note This API must not be called when the DMA channel is enabled.
+ * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr).
+ * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
+ * CMAR MA LL_DMA_ConfigAddresses
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ * @param Direction This parameter can be one of the following values:
+ * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+ * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+ * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
+ uint32_t DstAddress, uint32_t Direction)
+{
+ /* Direction Memory to Periph */
+ if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
+ {
+ WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress);
+ WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress);
+ }
+ /* Direction Periph to Memory and Memory to Memory */
+ else
+ {
+ WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress);
+ WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress);
+ }
+}
+
+/**
+ * @brief Set the Memory address.
+ * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+ * @note This API must not be called when the DMA channel is enabled.
+ * @rmtoll CMAR MA LL_DMA_SetMemoryAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
+{
+ WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
+}
+
+/**
+ * @brief Set the Peripheral address.
+ * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+ * @note This API must not be called when the DMA channel is enabled.
+ * @rmtoll CPAR PA LL_DMA_SetPeriphAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
+{
+ WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress);
+}
+
+/**
+ * @brief Get Memory address.
+ * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+ * @rmtoll CMAR MA LL_DMA_GetMemoryAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
+}
+
+/**
+ * @brief Get Peripheral address.
+ * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+ * @rmtoll CPAR PA LL_DMA_GetPeriphAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
+}
+
+/**
+ * @brief Set the Memory to Memory Source address.
+ * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+ * @note This API must not be called when the DMA channel is enabled.
+ * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
+{
+ WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress);
+}
+
+/**
+ * @brief Set the Memory to Memory Destination address.
+ * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+ * @note This API must not be called when the DMA channel is enabled.
+ * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
+{
+ WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
+}
+
+/**
+ * @brief Get the Memory to Memory Source address.
+ * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+ * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
+}
+
+/**
+ * @brief Get the Memory to Memory Destination address.
+ * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+ * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+
+/**
+ * @brief Get Channel 1 global interrupt flag.
+ * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1));
+}
+
+/**
+ * @brief Get Channel 2 global interrupt flag.
+ * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2));
+}
+
+/**
+ * @brief Get Channel 3 global interrupt flag.
+ * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3));
+}
+
+/**
+ * @brief Get Channel 4 global interrupt flag.
+ * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4));
+}
+
+/**
+ * @brief Get Channel 5 global interrupt flag.
+ * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5));
+}
+
+/**
+ * @brief Get Channel 6 global interrupt flag.
+ * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6));
+}
+
+/**
+ * @brief Get Channel 7 global interrupt flag.
+ * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7));
+}
+
+/**
+ * @brief Get Channel 1 transfer complete flag.
+ * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1));
+}
+
+/**
+ * @brief Get Channel 2 transfer complete flag.
+ * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2));
+}
+
+/**
+ * @brief Get Channel 3 transfer complete flag.
+ * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3));
+}
+
+/**
+ * @brief Get Channel 4 transfer complete flag.
+ * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4));
+}
+
+/**
+ * @brief Get Channel 5 transfer complete flag.
+ * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5));
+}
+
+/**
+ * @brief Get Channel 6 transfer complete flag.
+ * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6));
+}
+
+/**
+ * @brief Get Channel 7 transfer complete flag.
+ * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7));
+}
+
+/**
+ * @brief Get Channel 1 half transfer flag.
+ * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1));
+}
+
+/**
+ * @brief Get Channel 2 half transfer flag.
+ * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2));
+}
+
+/**
+ * @brief Get Channel 3 half transfer flag.
+ * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3));
+}
+
+/**
+ * @brief Get Channel 4 half transfer flag.
+ * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4));
+}
+
+/**
+ * @brief Get Channel 5 half transfer flag.
+ * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5));
+}
+
+/**
+ * @brief Get Channel 6 half transfer flag.
+ * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6));
+}
+
+/**
+ * @brief Get Channel 7 half transfer flag.
+ * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7));
+}
+
+/**
+ * @brief Get Channel 1 transfer error flag.
+ * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1));
+}
+
+/**
+ * @brief Get Channel 2 transfer error flag.
+ * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2));
+}
+
+/**
+ * @brief Get Channel 3 transfer error flag.
+ * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3));
+}
+
+/**
+ * @brief Get Channel 4 transfer error flag.
+ * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4));
+}
+
+/**
+ * @brief Get Channel 5 transfer error flag.
+ * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5));
+}
+
+/**
+ * @brief Get Channel 6 transfer error flag.
+ * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6));
+}
+
+/**
+ * @brief Get Channel 7 transfer error flag.
+ * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7));
+}
+
+/**
+ * @brief Clear Channel 1 global interrupt flag.
+ * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
+}
+
+/**
+ * @brief Clear Channel 2 global interrupt flag.
+ * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
+}
+
+/**
+ * @brief Clear Channel 3 global interrupt flag.
+ * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
+}
+
+/**
+ * @brief Clear Channel 4 global interrupt flag.
+ * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
+}
+
+/**
+ * @brief Clear Channel 5 global interrupt flag.
+ * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
+}
+
+/**
+ * @brief Clear Channel 6 global interrupt flag.
+ * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
+}
+
+/**
+ * @brief Clear Channel 7 global interrupt flag.
+ * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
+}
+
+/**
+ * @brief Clear Channel 1 transfer complete flag.
+ * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
+}
+
+/**
+ * @brief Clear Channel 2 transfer complete flag.
+ * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
+}
+
+/**
+ * @brief Clear Channel 3 transfer complete flag.
+ * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
+}
+
+/**
+ * @brief Clear Channel 4 transfer complete flag.
+ * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
+}
+
+/**
+ * @brief Clear Channel 5 transfer complete flag.
+ * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
+}
+
+/**
+ * @brief Clear Channel 6 transfer complete flag.
+ * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
+}
+
+/**
+ * @brief Clear Channel 7 transfer complete flag.
+ * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
+}
+
+/**
+ * @brief Clear Channel 1 half transfer flag.
+ * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
+}
+
+/**
+ * @brief Clear Channel 2 half transfer flag.
+ * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
+}
+
+/**
+ * @brief Clear Channel 3 half transfer flag.
+ * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
+}
+
+/**
+ * @brief Clear Channel 4 half transfer flag.
+ * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
+}
+
+/**
+ * @brief Clear Channel 5 half transfer flag.
+ * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
+}
+
+/**
+ * @brief Clear Channel 6 half transfer flag.
+ * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
+}
+
+/**
+ * @brief Clear Channel 7 half transfer flag.
+ * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
+}
+
+/**
+ * @brief Clear Channel 1 transfer error flag.
+ * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
+}
+
+/**
+ * @brief Clear Channel 2 transfer error flag.
+ * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
+}
+
+/**
+ * @brief Clear Channel 3 transfer error flag.
+ * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
+}
+
+/**
+ * @brief Clear Channel 4 transfer error flag.
+ * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
+}
+
+/**
+ * @brief Clear Channel 5 transfer error flag.
+ * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
+}
+
+/**
+ * @brief Clear Channel 6 transfer error flag.
+ * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
+}
+
+/**
+ * @brief Clear Channel 7 transfer error flag.
+ * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EF_IT_Management IT_Management
+ * @{
+ */
+/**
+ * @brief Enable Transfer complete interrupt.
+ * @rmtoll CCR TCIE LL_DMA_EnableIT_TC
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
+}
+
+/**
+ * @brief Enable Half transfer interrupt.
+ * @rmtoll CCR HTIE LL_DMA_EnableIT_HT
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
+}
+
+/**
+ * @brief Enable Transfer error interrupt.
+ * @rmtoll CCR TEIE LL_DMA_EnableIT_TE
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
+}
+
+/**
+ * @brief Disable Transfer complete interrupt.
+ * @rmtoll CCR TCIE LL_DMA_DisableIT_TC
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
+}
+
+/**
+ * @brief Disable Half transfer interrupt.
+ * @rmtoll CCR HTIE LL_DMA_DisableIT_HT
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
+}
+
+/**
+ * @brief Disable Transfer error interrupt.
+ * @rmtoll CCR TEIE LL_DMA_DisableIT_TE
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
+}
+
+/**
+ * @brief Check if Transfer complete Interrupt is enabled.
+ * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_TCIE) == (DMA_CCR_TCIE));
+}
+
+/**
+ * @brief Check if Half transfer Interrupt is enabled.
+ * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_HTIE) == (DMA_CCR_HTIE));
+}
+
+/**
+ * @brief Check if Transfer error Interrupt is enabled.
+ * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_TEIE) == (DMA_CCR_TEIE));
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
+uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
+void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* DMA1 || DMA2 */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_LL_DMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_ll_exti.h b/Inc/stm32f3xx_ll_exti.h
new file mode 100644
index 0000000..4aebae7
--- /dev/null
+++ b/Inc/stm32f3xx_ll_exti.h
@@ -0,0 +1,1399 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_exti.h
+ * @author MCD Application Team
+ * @brief Header file of EXTI LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_LL_EXTI_H
+#define __STM32F3xx_LL_EXTI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx.h"
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined (EXTI)
+
+/** @defgroup EXTI_LL EXTI
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private Macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure
+ * @{
+ */
+typedef struct
+{
+
+ uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31
+ This parameter can be any combination of @ref EXTI_LL_EC_LINE */
+#if defined(EXTI_32_63_SUPPORT)
+
+ uint32_t Line_32_63; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 32 to 63
+ This parameter can be any combination of @ref EXTI_LL_EC_LINE */
+#endif
+
+ FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines.
+ This parameter can be set either to ENABLE or DISABLE */
+
+ uint8_t Mode; /*!< Specifies the mode for the EXTI lines.
+ This parameter can be a value of @ref EXTI_LL_EC_MODE. */
+
+ uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
+ This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */
+} LL_EXTI_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants
+ * @{
+ */
+
+/** @defgroup EXTI_LL_EC_LINE LINE
+ * @{
+ */
+#define LL_EXTI_LINE_0 EXTI_IMR_IM0 /*!< Extended line 0 */
+#define LL_EXTI_LINE_1 EXTI_IMR_IM1 /*!< Extended line 1 */
+#define LL_EXTI_LINE_2 EXTI_IMR_IM2 /*!< Extended line 2 */
+#define LL_EXTI_LINE_3 EXTI_IMR_IM3 /*!< Extended line 3 */
+#define LL_EXTI_LINE_4 EXTI_IMR_IM4 /*!< Extended line 4 */
+#define LL_EXTI_LINE_5 EXTI_IMR_IM5 /*!< Extended line 5 */
+#define LL_EXTI_LINE_6 EXTI_IMR_IM6 /*!< Extended line 6 */
+#define LL_EXTI_LINE_7 EXTI_IMR_IM7 /*!< Extended line 7 */
+#define LL_EXTI_LINE_8 EXTI_IMR_IM8 /*!< Extended line 8 */
+#define LL_EXTI_LINE_9 EXTI_IMR_IM9 /*!< Extended line 9 */
+#define LL_EXTI_LINE_10 EXTI_IMR_IM10 /*!< Extended line 10 */
+#define LL_EXTI_LINE_11 EXTI_IMR_IM11 /*!< Extended line 11 */
+#define LL_EXTI_LINE_12 EXTI_IMR_IM12 /*!< Extended line 12 */
+#define LL_EXTI_LINE_13 EXTI_IMR_IM13 /*!< Extended line 13 */
+#define LL_EXTI_LINE_14 EXTI_IMR_IM14 /*!< Extended line 14 */
+#define LL_EXTI_LINE_15 EXTI_IMR_IM15 /*!< Extended line 15 */
+#if defined(EXTI_IMR_IM16)
+#define LL_EXTI_LINE_16 EXTI_IMR_IM16 /*!< Extended line 16 */
+#endif
+#define LL_EXTI_LINE_17 EXTI_IMR_IM17 /*!< Extended line 17 */
+#if defined(EXTI_IMR_IM18)
+#define LL_EXTI_LINE_18 EXTI_IMR_IM18 /*!< Extended line 18 */
+#endif
+#define LL_EXTI_LINE_19 EXTI_IMR_IM19 /*!< Extended line 19 */
+#if defined(EXTI_IMR_IM20)
+#define LL_EXTI_LINE_20 EXTI_IMR_IM20 /*!< Extended line 20 */
+#endif
+#if defined(EXTI_IMR_IM21)
+#define LL_EXTI_LINE_21 EXTI_IMR_IM21 /*!< Extended line 21 */
+#endif
+#if defined(EXTI_IMR_IM22)
+#define LL_EXTI_LINE_22 EXTI_IMR_IM22 /*!< Extended line 22 */
+#endif
+#define LL_EXTI_LINE_23 EXTI_IMR_IM23 /*!< Extended line 23 */
+#if defined(EXTI_IMR_IM24)
+#define LL_EXTI_LINE_24 EXTI_IMR_IM24 /*!< Extended line 24 */
+#endif
+#if defined(EXTI_IMR_IM25)
+#define LL_EXTI_LINE_25 EXTI_IMR_IM25 /*!< Extended line 25 */
+#endif
+#if defined(EXTI_IMR_IM26)
+#define LL_EXTI_LINE_26 EXTI_IMR_IM26 /*!< Extended line 26 */
+#endif
+#if defined(EXTI_IMR_IM27)
+#define LL_EXTI_LINE_27 EXTI_IMR_IM27 /*!< Extended line 27 */
+#endif
+#if defined(EXTI_IMR_IM28)
+#define LL_EXTI_LINE_28 EXTI_IMR_IM28 /*!< Extended line 28 */
+#endif
+#if defined(EXTI_IMR_IM29)
+#define LL_EXTI_LINE_29 EXTI_IMR_IM29 /*!< Extended line 29 */
+#endif
+#if defined(EXTI_IMR_IM30)
+#define LL_EXTI_LINE_30 EXTI_IMR_IM30 /*!< Extended line 30 */
+#endif
+#if defined(EXTI_IMR_IM31)
+#define LL_EXTI_LINE_31 EXTI_IMR_IM31 /*!< Extended line 31 */
+#endif
+#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR_IM /*!< All Extended line not reserved*/
+
+#if defined(EXTI_32_63_SUPPORT)
+#define LL_EXTI_LINE_32 EXTI_IMR2_IM32 /*!< Extended line 32 */
+#if defined(EXTI_IMR2_IM33)
+#define LL_EXTI_LINE_33 EXTI_IMR2_IM33 /*!< Extended line 33 */
+#endif
+#if defined(EXTI_IMR2_IM34)
+#define LL_EXTI_LINE_34 EXTI_IMR2_IM34 /*!< Extended line 34 */
+#endif
+#if defined(EXTI_IMR2_IM35)
+#define LL_EXTI_LINE_35 EXTI_IMR2_IM35 /*!< Extended line 35 */
+#endif
+#if defined(EXTI_IMR2_IM36)
+#define LL_EXTI_LINE_36 EXTI_IMR2_IM36 /*!< Extended line 36 */
+#endif
+#if defined(EXTI_IMR2_IM37)
+#define LL_EXTI_LINE_37 EXTI_IMR2_IM37 /*!< Extended line 37 */
+#endif
+#if defined(EXTI_IMR2_IM38)
+#define LL_EXTI_LINE_38 EXTI_IMR2_IM38 /*!< Extended line 38 */
+#endif
+#if defined(EXTI_IMR2_IM39)
+#define LL_EXTI_LINE_39 EXTI_IMR2_IM39 /*!< Extended line 39 */
+#endif
+#if defined(EXTI_IMR2_IM40)
+#define LL_EXTI_LINE_40 EXTI_IMR2_IM40 /*!< Extended line 40 */
+#endif
+#define LL_EXTI_LINE_ALL_32_63 EXTI_IMR2_IM /*!< All Extended line not reserved*/
+
+#endif
+
+#define LL_EXTI_LINE_ALL (0xFFFFFFFFU) /*!< All Extended line */
+
+#if defined(USE_FULL_LL_DRIVER)
+#define LL_EXTI_LINE_NONE (0x00000000U) /*!< None Extended line */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/**
+ * @}
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/** @defgroup EXTI_LL_EC_MODE Mode
+ * @{
+ */
+#define LL_EXTI_MODE_IT ((uint8_t)0x00U) /*!< Interrupt Mode */
+#define LL_EXTI_MODE_EVENT ((uint8_t)0x01U) /*!< Event Mode */
+#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U) /*!< Interrupt & Event Mode */
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger
+ * @{
+ */
+#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */
+#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */
+#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */
+#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */
+
+/**
+ * @}
+ */
+
+
+#endif /*USE_FULL_LL_DRIVER*/
+
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros
+ * @{
+ */
+
+/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in EXTI register
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in EXTI register
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions
+ * @{
+ */
+/** @defgroup EXTI_LL_EF_IT_Management IT_Management
+ * @{
+ */
+
+/**
+ * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31
+ * @note The reset value for the direct or internal lines (see RM)
+ * is set to 1 in order to enable the interrupt by default.
+ * Bits are set automatically at Power on.
+ * @rmtoll IMR IMx LL_EXTI_EnableIT_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_23
+ * @arg @ref LL_EXTI_LINE_24
+ * @arg @ref LL_EXTI_LINE_25
+ * @arg @ref LL_EXTI_LINE_26
+ * @arg @ref LL_EXTI_LINE_27
+ * @arg @ref LL_EXTI_LINE_28
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->IMR, ExtiLine);
+}
+#if defined(EXTI_32_63_SUPPORT)
+/**
+ * @brief Enable ExtiLine Interrupt request for Lines in range 32 to 63
+ * @note The reset value for the direct lines (lines from 32 to 34, line
+ * 39) is set to 1 in order to enable the interrupt by default.
+ * Bits are set automatically at Power on.
+ * @rmtoll IMR2 IMx LL_EXTI_EnableIT_32_63
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_32
+ * @arg @ref LL_EXTI_LINE_33
+ * @arg @ref LL_EXTI_LINE_34
+ * @arg @ref LL_EXTI_LINE_35
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @arg @ref LL_EXTI_LINE_39
+ * @arg @ref LL_EXTI_LINE_ALL_32_63
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->IMR2, ExtiLine);
+}
+#endif
+
+/**
+ * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31
+ * @note The reset value for the direct or internal lines (see RM)
+ * is set to 1 in order to enable the interrupt by default.
+ * Bits are set automatically at Power on.
+ * @rmtoll IMR IMx LL_EXTI_DisableIT_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_23
+ * @arg @ref LL_EXTI_LINE_24
+ * @arg @ref LL_EXTI_LINE_25
+ * @arg @ref LL_EXTI_LINE_26
+ * @arg @ref LL_EXTI_LINE_27
+ * @arg @ref LL_EXTI_LINE_28
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
+{
+ CLEAR_BIT(EXTI->IMR, ExtiLine);
+}
+
+#if defined(EXTI_32_63_SUPPORT)
+/**
+ * @brief Disable ExtiLine Interrupt request for Lines in range 32 to 63
+ * @note The reset value for the direct lines (lines from 32 to 34, line
+ * 39) is set to 1 in order to enable the interrupt by default.
+ * Bits are set automatically at Power on.
+ * @rmtoll IMR2 IMx LL_EXTI_DisableIT_32_63
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_32
+ * @arg @ref LL_EXTI_LINE_33
+ * @arg @ref LL_EXTI_LINE_34
+ * @arg @ref LL_EXTI_LINE_35
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @arg @ref LL_EXTI_LINE_39
+ * @arg @ref LL_EXTI_LINE_ALL_32_63
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine)
+{
+ CLEAR_BIT(EXTI->IMR2, ExtiLine);
+}
+#endif
+
+/**
+ * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31
+ * @note The reset value for the direct or internal lines (see RM)
+ * is set to 1 in order to enable the interrupt by default.
+ * Bits are set automatically at Power on.
+ * @rmtoll IMR IMx LL_EXTI_IsEnabledIT_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_23
+ * @arg @ref LL_EXTI_LINE_24
+ * @arg @ref LL_EXTI_LINE_25
+ * @arg @ref LL_EXTI_LINE_26
+ * @arg @ref LL_EXTI_LINE_27
+ * @arg @ref LL_EXTI_LINE_28
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
+{
+ return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine));
+}
+
+#if defined(EXTI_32_63_SUPPORT)
+/**
+ * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63
+ * @note The reset value for the direct lines (lines from 32 to 34, line
+ * 39) is set to 1 in order to enable the interrupt by default.
+ * Bits are set automatically at Power on.
+ * @rmtoll IMR2 IMx LL_EXTI_IsEnabledIT_32_63
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_32
+ * @arg @ref LL_EXTI_LINE_33
+ * @arg @ref LL_EXTI_LINE_34
+ * @arg @ref LL_EXTI_LINE_35
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @arg @ref LL_EXTI_LINE_39
+ * @arg @ref LL_EXTI_LINE_ALL_32_63
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine)
+{
+ return (READ_BIT(EXTI->IMR2, ExtiLine) == (ExtiLine));
+}
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_LL_EF_Event_Management Event_Management
+ * @{
+ */
+
+/**
+ * @brief Enable ExtiLine Event request for Lines in range 0 to 31
+ * @rmtoll EMR EMx LL_EXTI_EnableEvent_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_23
+ * @arg @ref LL_EXTI_LINE_24
+ * @arg @ref LL_EXTI_LINE_25
+ * @arg @ref LL_EXTI_LINE_26
+ * @arg @ref LL_EXTI_LINE_27
+ * @arg @ref LL_EXTI_LINE_28
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->EMR, ExtiLine);
+
+}
+
+#if defined(EXTI_32_63_SUPPORT)
+/**
+ * @brief Enable ExtiLine Event request for Lines in range 32 to 63
+ * @rmtoll EMR2 EMx LL_EXTI_EnableEvent_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_32
+ * @arg @ref LL_EXTI_LINE_33
+ * @arg @ref LL_EXTI_LINE_34
+ * @arg @ref LL_EXTI_LINE_35
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @arg @ref LL_EXTI_LINE_39
+ * @arg @ref LL_EXTI_LINE_ALL_32_63
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->EMR2, ExtiLine);
+}
+#endif
+
+/**
+ * @brief Disable ExtiLine Event request for Lines in range 0 to 31
+ * @rmtoll EMR EMx LL_EXTI_DisableEvent_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_23
+ * @arg @ref LL_EXTI_LINE_24
+ * @arg @ref LL_EXTI_LINE_25
+ * @arg @ref LL_EXTI_LINE_26
+ * @arg @ref LL_EXTI_LINE_27
+ * @arg @ref LL_EXTI_LINE_28
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
+{
+ CLEAR_BIT(EXTI->EMR, ExtiLine);
+}
+
+#if defined(EXTI_32_63_SUPPORT)
+/**
+ * @brief Disable ExtiLine Event request for Lines in range 32 to 63
+ * @rmtoll EMR2 EMx LL_EXTI_DisableEvent_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_32
+ * @arg @ref LL_EXTI_LINE_33
+ * @arg @ref LL_EXTI_LINE_34
+ * @arg @ref LL_EXTI_LINE_35
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @arg @ref LL_EXTI_LINE_39
+ * @arg @ref LL_EXTI_LINE_ALL_32_63
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine)
+{
+ CLEAR_BIT(EXTI->EMR2, ExtiLine);
+}
+#endif
+
+/**
+ * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31
+ * @rmtoll EMR EMx LL_EXTI_IsEnabledEvent_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_23
+ * @arg @ref LL_EXTI_LINE_24
+ * @arg @ref LL_EXTI_LINE_25
+ * @arg @ref LL_EXTI_LINE_26
+ * @arg @ref LL_EXTI_LINE_27
+ * @arg @ref LL_EXTI_LINE_28
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
+{
+ return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine));
+
+}
+
+#if defined(EXTI_32_63_SUPPORT)
+/**
+ * @brief Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63
+ * @rmtoll EMR2 EMx LL_EXTI_IsEnabledEvent_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_32
+ * @arg @ref LL_EXTI_LINE_33
+ * @arg @ref LL_EXTI_LINE_34
+ * @arg @ref LL_EXTI_LINE_35
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @arg @ref LL_EXTI_LINE_39
+ * @arg @ref LL_EXTI_LINE_ALL_32_63
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine)
+{
+ return (READ_BIT(EXTI->EMR2, ExtiLine) == (ExtiLine));
+}
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management
+ * @{
+ */
+
+/**
+ * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
+ * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ * generated on these lines. If a rising edge on a configurable interrupt
+ * line occurs during a write operation in the EXTI_RTSR register, the
+ * pending bit is not set.
+ * Rising and falling edge triggers can be set for
+ * the same interrupt line. In this case, both generate a trigger
+ * condition.
+ * @rmtoll RTSR RTx LL_EXTI_EnableRisingTrig_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->RTSR, ExtiLine);
+
+}
+
+#if defined(EXTI_32_63_SUPPORT)
+/**
+ * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63
+ * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ * generated on these lines. If a rising edge on a configurable interrupt
+ * line occurs during a write operation in the EXTI_RTSR register, the
+ * pending bit is not set.Rising and falling edge triggers can be set for
+ * the same interrupt line. In this case, both generate a trigger
+ * condition.
+ * @rmtoll RTSR2 RTx LL_EXTI_EnableRisingTrig_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_35
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->RTSR2, ExtiLine);
+}
+#endif
+
+/**
+ * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
+ * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ * generated on these lines. If a rising edge on a configurable interrupt
+ * line occurs during a write operation in the EXTI_RTSR register, the
+ * pending bit is not set.
+ * Rising and falling edge triggers can be set for
+ * the same interrupt line. In this case, both generate a trigger
+ * condition.
+ * @rmtoll RTSR RTx LL_EXTI_DisableRisingTrig_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
+{
+ CLEAR_BIT(EXTI->RTSR, ExtiLine);
+
+}
+
+#if defined(EXTI_32_63_SUPPORT)
+/**
+ * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63
+ * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ * generated on these lines. If a rising edge on a configurable interrupt
+ * line occurs during a write operation in the EXTI_RTSR register, the
+ * pending bit is not set.
+ * Rising and falling edge triggers can be set for
+ * the same interrupt line. In this case, both generate a trigger
+ * condition.
+ * @rmtoll RTSR2 RTx LL_EXTI_DisableRisingTrig_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_35
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine)
+{
+ CLEAR_BIT(EXTI->RTSR2, ExtiLine);
+}
+#endif
+
+/**
+ * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31
+ * @rmtoll RTSR RTx LL_EXTI_IsEnabledRisingTrig_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)
+{
+ return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine));
+}
+
+#if defined(EXTI_32_63_SUPPORT)
+/**
+ * @brief Check if rising edge trigger is enabled for Lines in range 32 to 63
+ * @rmtoll RTSR2 RTx LL_EXTI_IsEnabledRisingTrig_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_35
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63(uint32_t ExtiLine)
+{
+ return (READ_BIT(EXTI->RTSR2, ExtiLine) == (ExtiLine));
+}
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management
+ * @{
+ */
+
+/**
+ * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
+ * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ * generated on these lines. If a falling edge on a configurable interrupt
+ * line occurs during a write operation in the EXTI_FTSR register, the
+ * pending bit is not set.
+ * Rising and falling edge triggers can be set for
+ * the same interrupt line. In this case, both generate a trigger
+ * condition.
+ * @rmtoll FTSR FTx LL_EXTI_EnableFallingTrig_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->FTSR, ExtiLine);
+}
+
+#if defined(EXTI_32_63_SUPPORT)
+/**
+ * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63
+ * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ * generated on these lines. If a Falling edge on a configurable interrupt
+ * line occurs during a write operation in the EXTI_FTSR register, the
+ * pending bit is not set.
+ * Rising and falling edge triggers can be set for
+ * the same interrupt line. In this case, both generate a trigger
+ * condition.
+ * @rmtoll FTSR2 FTx LL_EXTI_EnableFallingTrig_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_35
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->FTSR2, ExtiLine);
+}
+#endif
+
+/**
+ * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
+ * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ * generated on these lines. If a Falling edge on a configurable interrupt
+ * line occurs during a write operation in the EXTI_FTSR register, the
+ * pending bit is not set.
+ * Rising and falling edge triggers can be set for the same interrupt line.
+ * In this case, both generate a trigger condition.
+ * @rmtoll FTSR FTx LL_EXTI_DisableFallingTrig_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)
+{
+ CLEAR_BIT(EXTI->FTSR, ExtiLine);
+}
+
+#if defined(EXTI_32_63_SUPPORT)
+/**
+ * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63
+ * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ * generated on these lines. If a Falling edge on a configurable interrupt
+ * line occurs during a write operation in the EXTI_FTSR register, the
+ * pending bit is not set.
+ * Rising and falling edge triggers can be set for the same interrupt line.
+ * In this case, both generate a trigger condition.
+ * @rmtoll FTSR2 FTx LL_EXTI_DisableFallingTrig_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_35
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine)
+{
+ CLEAR_BIT(EXTI->FTSR2, ExtiLine);
+}
+#endif
+
+/**
+ * @brief Check if falling edge trigger is enabled for Lines in range 0 to 31
+ * @rmtoll FTSR FTx LL_EXTI_IsEnabledFallingTrig_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine)
+{
+ return (READ_BIT(EXTI->FTSR, ExtiLine) == (ExtiLine));
+}
+
+#if defined(EXTI_32_63_SUPPORT)
+/**
+ * @brief Check if falling edge trigger is enabled for Lines in range 32 to 63
+ * @rmtoll FTSR2 FTx LL_EXTI_IsEnabledFallingTrig_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_35
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63(uint32_t ExtiLine)
+{
+ return (READ_BIT(EXTI->FTSR2, ExtiLine) == (ExtiLine));
+}
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management
+ * @{
+ */
+
+/**
+ * @brief Generate a software Interrupt Event for Lines in range 0 to 31
+ * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to
+ * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR
+ * resulting in an interrupt request generation.
+ * This bit is cleared by clearing the corresponding bit in the EXTI_PR
+ * register (by writing a 1 into the bit)
+ * @rmtoll SWIER SWIx LL_EXTI_GenerateSWI_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->SWIER, ExtiLine);
+}
+
+#if defined(EXTI_32_63_SUPPORT)
+/**
+ * @brief Generate a software Interrupt Event for Lines in range 32 to 63
+ * @note If the interrupt is enabled on this line inthe EXTI_IMR2, writing a 1 to
+ * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR2
+ * resulting in an interrupt request generation.
+ * This bit is cleared by clearing the corresponding bit in the EXTI_PR2
+ * register (by writing a 1 into the bit)
+ * @rmtoll SWIER2 SWIx LL_EXTI_GenerateSWI_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_35
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_GenerateSWI_32_63(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->SWIER2, ExtiLine);
+}
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management
+ * @{
+ */
+
+/**
+ * @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31
+ * @note This bit is set when the selected edge event arrives on the interrupt
+ * line. This bit is cleared by writing a 1 to the bit.
+ * @rmtoll PR PIFx LL_EXTI_IsActiveFlag_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)
+{
+ return (READ_BIT(EXTI->PR, ExtiLine) == (ExtiLine));
+}
+
+#if defined(EXTI_32_63_SUPPORT)
+/**
+ * @brief Check if the ExtLine Flag is set or not for Lines in range 32 to 63
+ * @note This bit is set when the selected edge event arrives on the interrupt
+ * line. This bit is cleared by writing a 1 to the bit.
+ * @rmtoll PR2 PIFx LL_EXTI_IsActiveFlag_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_35
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine)
+{
+ return (READ_BIT(EXTI->PR2, ExtiLine) == (ExtiLine));
+}
+#endif
+
+/**
+ * @brief Read ExtLine Combination Flag for Lines in range 0 to 31
+ * @note This bit is set when the selected edge event arrives on the interrupt
+ * line. This bit is cleared by writing a 1 to the bit.
+ * @rmtoll PR PIFx LL_EXTI_ReadFlag_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval @note This bit is set when the selected edge event arrives on the interrupt
+ */
+__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine)
+{
+ return (uint32_t)(READ_BIT(EXTI->PR, ExtiLine));
+}
+
+#if defined(EXTI_32_63_SUPPORT)
+
+/**
+ * @brief Read ExtLine Combination Flag for Lines in range 32 to 63
+ * @note This bit is set when the selected edge event arrives on the interrupt
+ * line. This bit is cleared by writing a 1 to the bit.
+ * @rmtoll PR2 PIFx LL_EXTI_ReadFlag_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_35
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @retval @note This bit is set when the selected edge event arrives on the interrupt
+ */
+__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_32_63(uint32_t ExtiLine)
+{
+ return (uint32_t)(READ_BIT(EXTI->PR2, ExtiLine));
+}
+#endif
+
+/**
+ * @brief Clear ExtLine Flags for Lines in range 0 to 31
+ * @note This bit is set when the selected edge event arrives on the interrupt
+ * line. This bit is cleared by writing a 1 to the bit.
+ * @rmtoll PR PIFx LL_EXTI_ClearFlag_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine)
+{
+ WRITE_REG(EXTI->PR, ExtiLine);
+}
+
+#if defined(EXTI_32_63_SUPPORT)
+/**
+ * @brief Clear ExtLine Flags for Lines in range 32 to 63
+ * @note This bit is set when the selected edge event arrives on the interrupt
+ * line. This bit is cleared by writing a 1 to the bit.
+ * @rmtoll PR2 PIFx LL_EXTI_ClearFlag_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_35
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_ClearFlag_32_63(uint32_t ExtiLine)
+{
+ WRITE_REG(EXTI->PR2, ExtiLine);
+}
+#endif
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);
+uint32_t LL_EXTI_DeInit(void);
+void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);
+
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* EXTI */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_LL_EXTI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_ll_fmc.h b/Inc/stm32f3xx_ll_fmc.h
new file mode 100644
index 0000000..37e45d5
--- /dev/null
+++ b/Inc/stm32f3xx_ll_fmc.h
@@ -0,0 +1,1082 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_fmc.h
+ * @author MCD Application Team
+ * @brief Header file of FMC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_LL_FMC_H
+#define __STM32F3xx_LL_FMC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+#if defined(FMC_BANK1)
+
+/** @addtogroup FMC_LL
+ * @{
+ */
+
+/** @addtogroup FMC_LL_Private_Macros
+ * @{
+ */
+
+#define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \
+ ((__BANK__) == FMC_NORSRAM_BANK2) || \
+ ((__BANK__) == FMC_NORSRAM_BANK3) || \
+ ((__BANK__) == FMC_NORSRAM_BANK4))
+
+#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
+ ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
+
+#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \
+ ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \
+ ((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
+
+#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \
+ ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
+ ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
+
+#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \
+ ((__BURST__) == FMC_WRITE_BURST_ENABLE))
+
+#define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
+ ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
+
+#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \
+ ((__MODE__) == FMC_ACCESS_MODE_B) || \
+ ((__MODE__) == FMC_ACCESS_MODE_C) || \
+ ((__MODE__) == FMC_ACCESS_MODE_D))
+
+#define IS_FMC_NAND_BANK(__BANK__) (((__BANK__) == FMC_NAND_BANK2) || \
+ ((__BANK__) == FMC_NAND_BANK3))
+
+#define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
+ ((__FEATURE__) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
+
+#define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
+ ((__WIDTH__) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
+
+#define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \
+ ((__STATE__) == FMC_NAND_ECC_ENABLE))
+
+#define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
+ ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
+ ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
+ ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
+ ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
+ ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
+
+/** @defgroup FMC_TCLR_Setup_Time FMC_TCLR_Setup_Time
+ * @{
+ */
+#define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_TAR_Setup_Time FMC_TAR_Setup_Time
+ * @{
+ */
+#define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Setup_Time FMC_Setup_Time
+ * @{
+ */
+#define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 255)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Wait_Setup_Time FMC_Wait_Setup_Time
+ * @{
+ */
+#define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 255)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Hold_Setup_Time FMC_Hold_Setup_Time
+ * @{
+ */
+#define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 255)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_HiZ_Setup_Time FMC_HiZ_Setup_Time
+ * @{
+ */
+#define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 255)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_NORSRAM_Device_Instance FMC NOR/SRAM Device Instance
+ * @{
+ */
+
+#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance FMC NOR/SRAM EXTENDED Device Instance
+ * @{
+ */
+
+#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_NAND_Device_Instance FMC NAND Device Instance
+ * @{
+ */
+#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_PCCARD_Device_Instance FMC PCCARD Device Instance
+ * @{
+ */
+#define IS_FMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_PCCARD_DEVICE)
+
+/**
+ * @}
+ */
+#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \
+ ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
+
+#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
+ ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
+
+#define IS_FMC_WRAP_MODE(__MODE__) (((__MODE__) == FMC_WRAP_MODE_DISABLE) || \
+ ((__MODE__) == FMC_WRAP_MODE_ENABLE))
+
+#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \
+ ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
+
+#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \
+ ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
+
+#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \
+ ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
+
+#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \
+ ((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
+
+#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
+ ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
+
+#define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1) && ((__DIV__) <= 16))
+
+/** @defgroup FMC_Data_Latency FMC Data Latency
+ * @{
+ */
+#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Address_Setup_Time FMC Address Setup Time
+ * @{
+ */
+#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Address_Hold_Time FMC Address Hold Time
+ * @{
+ */
+#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Data_Setup_Time FMC Data Setup Time
+ * @{
+ */
+#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Bus_Turn_around_Duration FMC Bus Turn around Duration
+ * @{
+ */
+#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported typedef ----------------------------------------------------------*/
+
+/** @defgroup FMC_NORSRAM_Exported_typedef FMC Low Layer Exported Types
+ * @{
+ */
+
+#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
+#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
+#define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
+#define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
+
+#define FMC_NORSRAM_DEVICE FMC_Bank1
+#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
+#define FMC_NAND_DEVICE FMC_Bank2_3
+#define FMC_PCCARD_DEVICE FMC_Bank4
+
+/**
+ * @brief FMC_NORSRAM Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
+ This parameter can be a value of @ref FMC_NORSRAM_Bank */
+
+ uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
+ multiplexed on the data bus or not.
+ This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
+
+ uint32_t MemoryType; /*!< Specifies the type of external memory attached to
+ the corresponding memory device.
+ This parameter can be a value of @ref FMC_Memory_Type */
+
+ uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
+ This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
+
+ uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
+ valid only with synchronous burst Flash memories.
+ This parameter can be a value of @ref FMC_Burst_Access_Mode */
+
+ uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
+ the Flash memory in burst mode.
+ This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
+
+ uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
+ memory, valid only when accessing Flash memories in burst mode.
+ This parameter can be a value of @ref FMC_Wrap_Mode */
+
+ uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
+ clock cycle before the wait state or during the wait state,
+ valid only when accessing memories in burst mode.
+ This parameter can be a value of @ref FMC_Wait_Timing */
+
+ uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
+ This parameter can be a value of @ref FMC_Write_Operation */
+
+ uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
+ signal, valid for Flash memory access in burst mode.
+ This parameter can be a value of @ref FMC_Wait_Signal */
+
+ uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
+ This parameter can be a value of @ref FMC_Extended_Mode */
+
+ uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
+ valid only with asynchronous Flash memories.
+ This parameter can be a value of @ref FMC_AsynchronousWait */
+
+ uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
+ This parameter can be a value of @ref FMC_Write_Burst */
+
+ uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
+ This parameter is only enabled through the FMC_BCR1 register, and don't care
+ through FMC_BCR2..4 registers.
+ This parameter can be a value of @ref FMC_Continous_Clock */
+
+}FMC_NORSRAM_InitTypeDef;
+
+/**
+ * @brief FMC_NORSRAM Timing parameters structure definition
+ */
+typedef struct
+{
+ uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
+ the duration of the address setup time.
+ This parameter can be a value between Min_Data = 0 and Max_Data = 15.
+ @note This parameter is not used with synchronous NOR Flash memories. */
+
+ uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
+ the duration of the address hold time.
+ This parameter can be a value between Min_Data = 1 and Max_Data = 15.
+ @note This parameter is not used with synchronous NOR Flash memories. */
+
+ uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
+ the duration of the data setup time.
+ This parameter can be a value between Min_Data = 1 and Max_Data = 255.
+ @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
+ NOR Flash memories. */
+
+ uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
+ the duration of the bus turnaround.
+ This parameter can be a value between Min_Data = 0 and Max_Data = 15.
+ @note This parameter is only used for multiplexed NOR Flash memories. */
+
+ uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
+ HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
+ @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
+ accesses. */
+
+ uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
+ to the memory before getting the first data.
+ The parameter value depends on the memory type as shown below:
+ - It must be set to 0 in case of a CRAM
+ - It is don't care in asynchronous NOR, SRAM or ROM accesses
+ - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
+ with synchronous burst mode enable */
+
+ uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
+ This parameter can be a value of @ref FMC_Access_Mode */
+
+}FMC_NORSRAM_TimingTypeDef;
+
+/**
+ * @brief FMC_NAND Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
+ This parameter can be a value of @ref FMC_NAND_Bank */
+
+ uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
+ This parameter can be any value of @ref FMC_Wait_feature */
+
+ uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
+ This parameter can be any value of @ref FMC_NAND_Data_Width */
+
+ uint32_t EccComputation; /*!< Enables or disables the ECC computation.
+ This parameter can be any value of @ref FMC_ECC */
+
+ uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
+ This parameter can be any value of @ref FMC_ECC_Page_Size */
+
+ uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between CLE low and RE low.
+ This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
+
+ uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between ALE low and RE low.
+ This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+
+}FMC_NAND_InitTypeDef;
+
+/**
+ * @brief FMC_NAND_PCC Timing parameters structure definition
+ */
+typedef struct
+{
+ uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
+ the command assertion for NAND-Flash read or write access
+ to common/Attribute or I/O memory space (depending on
+ the memory space timing to be configured).
+ This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
+
+ uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
+ command for NAND-Flash read or write access to
+ common/Attribute or I/O memory space (depending on the
+ memory space timing to be configured).
+ This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+
+ uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
+ (and data for write access) after the command de-assertion
+ for NAND-Flash read or write access to common/Attribute
+ or I/O memory space (depending on the memory space timing
+ to be configured).
+ This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+
+ uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
+ data bus is kept in HiZ after the start of a NAND-Flash
+ write access to common/Attribute or I/O memory space (depending
+ on the memory space timing to be configured).
+ This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+
+}FMC_NAND_PCC_TimingTypeDef;
+
+/**
+ * @brief FMC_NAND Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
+ This parameter can be any value of @ref FMC_Wait_feature */
+
+ uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between CLE low and RE low.
+ This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
+
+ uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between ALE low and RE low.
+ This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+
+}FMC_PCCARD_InitTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup FMC_Exported_Constants FMC Low Layer Exported Constants
+ * @{
+ */
+
+/** @defgroup FMC_NORSRAM_Exported_constants FMC NOR/SRAM Exported constants
+ * @{
+ */
+
+/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
+ * @{
+ */
+#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
+#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
+#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
+#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
+ * @{
+ */
+
+#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
+#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)FMC_BCRx_MUXEN)
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Memory_Type FMC Memory Type
+ * @{
+ */
+
+#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
+#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)FMC_BCRx_MTYP_0)
+#define FMC_MEMORY_TYPE_NOR ((uint32_t)FMC_BCRx_MTYP_1)
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_NORSRAM_Data_Width FMC NOR/SRAM Data Width
+ * @{
+ */
+
+#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
+#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)FMC_BCRx_MWID_0)
+#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)FMC_BCRx_MWID_1)
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
+ * @{
+ */
+
+#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)FMC_BCRx_FACCEN)
+#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
+ * @{
+ */
+
+#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
+#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)FMC_BCRx_BURSTEN)
+
+/**
+ * @}
+ */
+
+
+/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
+ * @{
+ */
+
+#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
+#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)FMC_BCRx_WAITPOL)
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Wrap_Mode FMC Wrap Mode
+ * @{
+ */
+
+#define FMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
+#define FMC_WRAP_MODE_ENABLE ((uint32_t)FMC_BCRx_WRAPMOD)
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Wait_Timing FMC Wait Timing
+ * @{
+ */
+
+#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
+#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)FMC_BCRx_WAITCFG)
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Write_Operation FMC Write Operation
+ * @{
+ */
+
+#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
+#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)FMC_BCRx_WREN)
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Wait_Signal FMC Wait Signal
+ * @{
+ */
+
+#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
+#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)FMC_BCRx_WAITEN)
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Extended_Mode FMC Extended Mode
+ * @{
+ */
+
+#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
+#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)FMC_BCRx_EXTMOD)
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
+ * @{
+ */
+
+#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
+#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)FMC_BCRx_ASYNCWAIT)
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Write_Burst FMC Write Burst
+ * @{
+ */
+
+#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
+#define FMC_WRITE_BURST_ENABLE ((uint32_t)FMC_BCRx_CBURSTRW)
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Continous_Clock FMC Continous Clock
+ * @{
+ */
+#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
+#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)FMC_BCR1_CCLKEN)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Access_Mode FMC Access Mode
+ * @{
+ */
+
+#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000)
+#define FMC_ACCESS_MODE_B ((uint32_t)FMC_BTRx_ACCMOD_0)
+#define FMC_ACCESS_MODE_C ((uint32_t)FMC_BTRx_ACCMOD_1)
+#define FMC_ACCESS_MODE_D ((uint32_t)(FMC_BTRx_ACCMOD_0 | FMC_BTRx_ACCMOD_1))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_NAND_Controller FMC NAND and PCCARD Controller
+ * @{
+ */
+
+/** @defgroup FMC_NAND_Bank FMC NAND Bank
+ * @{
+ */
+#define FMC_NAND_BANK2 ((uint32_t)0x00000010)
+#define FMC_NAND_BANK3 ((uint32_t)0x00000100)
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Wait_feature FMC Wait feature
+ * @{
+ */
+#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
+#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)FMC_PCRx_PWAITEN)
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
+ * @{
+ */
+#define FMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000)
+#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)FMC_PCRx_PTYP)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
+ * @{
+ */
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)FMC_PCRx_PWID_0)
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_ECC FMC NAND ECC
+ * @{
+ */
+#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
+#define FMC_NAND_ECC_ENABLE ((uint32_t)FMC_PCRx_ECCEN)
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
+ * @{
+ */
+#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
+#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)FMC_PCRx_ECCPS_0)
+#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)FMC_PCRx_ECCPS_1)
+#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)FMC_PCRx_ECCPS_0|FMC_PCRx_ECCPS_1)
+#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)FMC_PCRx_ECCPS_2)
+#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)FMC_PCRx_ECCPS_0|FMC_PCRx_ECCPS_2)
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Interrupt_definition FMC Interrupt definition
+ * @brief FMC Interrupt definition
+ * @{
+ */
+#define FMC_IT_RISING_EDGE ((uint32_t)FMC_SRx_IREN)
+#define FMC_IT_LEVEL ((uint32_t)FMC_SRx_ILEN)
+#define FMC_IT_FALLING_EDGE ((uint32_t)FMC_SRx_IFEN)
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Flag_definition FMC Flag definition
+ * @brief FMC Flag definition
+ * @{
+ */
+#define FMC_FLAG_RISING_EDGE ((uint32_t)FMC_SRx_IRS)
+#define FMC_FLAG_LEVEL ((uint32_t)FMC_SRx_ILS)
+#define FMC_FLAG_FALLING_EDGE ((uint32_t)FMC_SRx_IFS)
+#define FMC_FLAG_FEMPT ((uint32_t)FMC_SRx_FEMPT)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup FMC_Exported_Macros FMC Low Layer Exported Macros
+ * @{
+ */
+
+/** @defgroup FMC_NOR_Macros FMC NOR/SRAM Exported Macros
+ * @brief macros to handle NOR device enable/disable and read/write operations
+ * @{
+ */
+
+/**
+ * @brief Enable the NORSRAM device access.
+ * @param __INSTANCE__ FMC_NORSRAM Instance
+ * @param __BANK__ FMC_NORSRAM Bank
+ * @retval none
+ */
+#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) SET_BIT((__INSTANCE__)->BTCR[(__BANK__)], FMC_BCRx_MBKEN)
+
+/**
+ * @brief Disable the NORSRAM device access.
+ * @param __INSTANCE__ FMC_NORSRAM Instance
+ * @param __BANK__ FMC_NORSRAM Bank
+ * @retval none
+ */
+#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->BTCR[(__BANK__)], FMC_BCRx_MBKEN)
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_NAND_Macros FMC NAND Macros
+ * @brief macros to handle NAND device enable/disable
+ * @{
+ */
+
+/**
+ * @brief Enable the NAND device access.
+ * @param __INSTANCE__ FMC_NAND Instance
+ * @param __BANK__ FMC_NAND Bank
+ * @retval None
+ */
+#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? SET_BIT((__INSTANCE__)->PCR2, FMC_PCRx_PBKEN): \
+ SET_BIT((__INSTANCE__)->PCR3, FMC_PCRx_PBKEN))
+
+/**
+ * @brief Disable the NAND device access.
+ * @param __INSTANCE__ FMC_NAND Instance
+ * @param __BANK__ FMC_NAND Bank
+ * @retval None
+ */
+#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->PCR2, FMC_PCRx_PBKEN): \
+ CLEAR_BIT((__INSTANCE__)->PCR3, FMC_PCRx_PBKEN))
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_PCCARD_Macros FMC PCCARD Macros
+ * @brief macros to handle PCCARD read/write operations
+ * @{
+ */
+
+/**
+ * @brief Enable the PCCARD device access.
+ * @param __INSTANCE__ FMC_PCCARD Instance
+ * @retval None
+ */
+#define __FMC_PCCARD_ENABLE(__INSTANCE__) SET_BIT((__INSTANCE__)->PCR4, FMC_PCRx_PBKEN)
+
+/**
+ * @brief Disable the PCCARD device access.
+ * @param __INSTANCE__ FMC_PCCARD Instance
+ * @retval None
+ */
+#define __FMC_PCCARD_DISABLE(__INSTANCE__) CLEAR_BIT((__INSTANCE__)->PCR4, FMC_PCRx_PBKEN)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Interrupt FMC Interrupt
+ * @brief macros to handle FMC interrupts
+ * @{
+ */
+
+/**
+ * @brief Enable the NAND device interrupt.
+ * @param __INSTANCE__ FMC_NAND Instance
+ * @param __BANK__ FMC_NAND Bank
+ * @param __INTERRUPT__ FMC_NAND interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FMC_IT_RISING_EDGE Interrupt rising edge.
+ * @arg FMC_IT_LEVEL Interrupt level.
+ * @arg FMC_IT_FALLING_EDGE Interrupt falling edge.
+ * @retval None
+ */
+#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? SET_BIT((__INSTANCE__)->SR2, (__INTERRUPT__)): \
+ SET_BIT((__INSTANCE__)->SR3, (__INTERRUPT__)))
+
+/**
+ * @brief Disable the NAND device interrupt.
+ * @param __INSTANCE__ FMC_NAND Instance
+ * @param __BANK__ FMC_NAND Bank
+ * @param __INTERRUPT__ FMC_NAND interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FMC_IT_RISING_EDGE Interrupt rising edge.
+ * @arg FMC_IT_LEVEL Interrupt level.
+ * @arg FMC_IT_FALLING_EDGE Interrupt falling edge.
+ * @retval None
+ */
+#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->SR2, (__INTERRUPT__)): \
+ CLEAR_BIT((__INSTANCE__)->SR3, (__INTERRUPT__)))
+
+/**
+ * @brief Get flag status of the NAND device.
+ * @param __INSTANCE__ FMC_NAND Instance
+ * @param __BANK__ FMC_NAND Bank
+ * @param __FLAG__ FMC_NAND flag
+ * This parameter can be any combination of the following values:
+ * @arg FMC_FLAG_RISING_EDGE Interrupt rising edge flag.
+ * @arg FMC_FLAG_LEVEL Interrupt level edge flag.
+ * @arg FMC_FLAG_FALLING_EDGE Interrupt falling edge flag.
+ * @arg FMC_FLAG_FEMPT FIFO empty flag.
+ * @retval The state of FLAG (SET or RESET).
+ */
+#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
+ (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
+
+/**
+ * @brief Clear flag status of the NAND device.
+ * @param __INSTANCE__ FMC_NAND Instance
+ * @param __BANK__ FMC_NAND Bank
+ * @param __FLAG__ FMC_NAND flag
+ * This parameter can be any combination of the following values:
+ * @arg FMC_FLAG_RISING_EDGE Interrupt rising edge flag.
+ * @arg FMC_FLAG_LEVEL Interrupt level edge flag.
+ * @arg FMC_FLAG_FALLING_EDGE Interrupt falling edge flag.
+ * @arg FMC_FLAG_FEMPT FIFO empty flag.
+ * @retval None
+ */
+#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->SR2, (__FLAG__)): \
+ CLEAR_BIT((__INSTANCE__)->SR3, (__FLAG__)))
+
+/**
+ * @brief Enable the PCCARD device interrupt.
+ * @param __INSTANCE__ FMC_PCCARD Instance
+ * @param __INTERRUPT__ FMC_PCCARD interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FMC_IT_RISING_EDGE Interrupt rising edge.
+ * @arg FMC_IT_LEVEL Interrupt level.
+ * @arg FMC_IT_FALLING_EDGE Interrupt falling edge.
+ * @retval None
+ */
+#define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) SET_BIT((__INSTANCE__)->SR4, (__INTERRUPT__))
+
+/**
+ * @brief Disable the PCCARD device interrupt.
+ * @param __INSTANCE__ FMC_PCCARD Instance
+ * @param __INTERRUPT__ FMC_PCCARD interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FMC_IT_RISING_EDGE Interrupt rising edge.
+ * @arg FMC_IT_LEVEL Interrupt level.
+ * @arg FMC_IT_FALLING_EDGE Interrupt falling edge.
+ * @retval None
+ */
+#define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) CLEAR_BIT((__INSTANCE__)->SR4, (__INTERRUPT__))
+
+/**
+ * @brief Get flag status of the PCCARD device.
+ * @param __INSTANCE__ FMC_PCCARD Instance
+ * @param __FLAG__ FMC_PCCARD flag
+ * This parameter can be any combination of the following values:
+ * @arg FMC_FLAG_RISING_EDGE Interrupt rising edge flag.
+ * @arg FMC_FLAG_LEVEL Interrupt level edge flag.
+ * @arg FMC_FLAG_FALLING_EDGE Interrupt falling edge flag.
+ * @arg FMC_FLAG_FEMPT FIFO empty flag.
+ * @retval The state of FLAG (SET or RESET).
+ */
+#define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Clear flag status of the PCCARD device.
+ * @param __INSTANCE__ FMC_PCCARD Instance
+ * @param __FLAG__ FMC_PCCARD flag
+ * This parameter can be any combination of the following values:
+ * @arg FMC_FLAG_RISING_EDGE Interrupt rising edge flag.
+ * @arg FMC_FLAG_LEVEL Interrupt level edge flag.
+ * @arg FMC_FLAG_FALLING_EDGE Interrupt falling edge flag.
+ * @arg FMC_FLAG_FEMPT FIFO empty flag.
+ * @retval None
+ */
+#define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) CLEAR_BIT((__INSTANCE__)->SR4, (__FLAG__))
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup FMC_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup FMC_NORSRAM
+ * @{
+ */
+
+/** @addtogroup FMC_NORSRAM_Group1
+ * @{
+ */
+
+/* FMC_NORSRAM Controller functions ******************************************/
+/* Initialization/de-initialization functions */
+HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init);
+HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
+HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
+
+/**
+ * @}
+ */
+
+/** @addtogroup FMC_NORSRAM_Group2
+ * @{
+ */
+
+/* FMC_NORSRAM Control functions */
+HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup FMC_NAND
+ * @{
+ */
+
+/* FMC_NAND Controller functions **********************************************/
+/* Initialization/de-initialization functions */
+/** @addtogroup FMC_NAND_Exported_Functions_Group1
+ * @{
+ */
+
+HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
+HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
+
+/**
+ * @}
+ */
+
+/* FMC_NAND Control functions */
+/** @addtogroup FMC_NAND_Exported_Functions_Group2
+ * @{
+ */
+
+HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup FMC_PCCARD
+ * @{
+ */
+
+/* FMC_PCCARD Controller functions ********************************************/
+/* Initialization/de-initialization functions */
+/** @addtogroup FMC_PCCARD_Exported_Functions_Group1
+ * @{
+ */
+
+HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init);
+HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
+HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
+HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
+HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* FMC_BANK1 */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_LL_FMC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Inc/stm32f3xx_ll_gpio.h b/Inc/stm32f3xx_ll_gpio.h
new file mode 100644
index 0000000..ae7edcc
--- /dev/null
+++ b/Inc/stm32f3xx_ll_gpio.h
@@ -0,0 +1,995 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_gpio.h
+ * @author MCD Application Team
+ * @brief Header file of GPIO LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_LL_GPIO_H
+#define __STM32F3xx_LL_GPIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx.h"
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH)
+
+/** @defgroup GPIO_LL GPIO
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
+ * @{
+ */
+
+/**
+ * @brief LL GPIO Init Structure definition
+ */
+typedef struct
+{
+ uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
+ This parameter can be any value of @ref GPIO_LL_EC_PIN */
+
+ uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
+ This parameter can be a value of @ref GPIO_LL_EC_MODE.
+
+ GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/
+
+ uint32_t Speed; /*!< Specifies the speed for the selected pins.
+ This parameter can be a value of @ref GPIO_LL_EC_SPEED.
+
+ GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/
+
+ uint32_t OutputType; /*!< Specifies the operating output type for the selected pins.
+ This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.
+
+ GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/
+
+ uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
+ This parameter can be a value of @ref GPIO_LL_EC_PULL.
+
+ GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/
+
+ uint32_t Alternate; /*!< Specifies the Peripheral to be connected to the selected pins.
+ This parameter can be a value of @ref GPIO_LL_EC_AF.
+
+ GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/
+} LL_GPIO_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
+ * @{
+ */
+
+/** @defgroup GPIO_LL_EC_PIN PIN
+ * @{
+ */
+#define LL_GPIO_PIN_0 GPIO_BSRR_BS_0 /*!< Select pin 0 */
+#define LL_GPIO_PIN_1 GPIO_BSRR_BS_1 /*!< Select pin 1 */
+#define LL_GPIO_PIN_2 GPIO_BSRR_BS_2 /*!< Select pin 2 */
+#define LL_GPIO_PIN_3 GPIO_BSRR_BS_3 /*!< Select pin 3 */
+#define LL_GPIO_PIN_4 GPIO_BSRR_BS_4 /*!< Select pin 4 */
+#define LL_GPIO_PIN_5 GPIO_BSRR_BS_5 /*!< Select pin 5 */
+#define LL_GPIO_PIN_6 GPIO_BSRR_BS_6 /*!< Select pin 6 */
+#define LL_GPIO_PIN_7 GPIO_BSRR_BS_7 /*!< Select pin 7 */
+#define LL_GPIO_PIN_8 GPIO_BSRR_BS_8 /*!< Select pin 8 */
+#define LL_GPIO_PIN_9 GPIO_BSRR_BS_9 /*!< Select pin 9 */
+#define LL_GPIO_PIN_10 GPIO_BSRR_BS_10 /*!< Select pin 10 */
+#define LL_GPIO_PIN_11 GPIO_BSRR_BS_11 /*!< Select pin 11 */
+#define LL_GPIO_PIN_12 GPIO_BSRR_BS_12 /*!< Select pin 12 */
+#define LL_GPIO_PIN_13 GPIO_BSRR_BS_13 /*!< Select pin 13 */
+#define LL_GPIO_PIN_14 GPIO_BSRR_BS_14 /*!< Select pin 14 */
+#define LL_GPIO_PIN_15 GPIO_BSRR_BS_15 /*!< Select pin 15 */
+#define LL_GPIO_PIN_ALL (GPIO_BSRR_BS_0 | GPIO_BSRR_BS_1 | GPIO_BSRR_BS_2 | \
+ GPIO_BSRR_BS_3 | GPIO_BSRR_BS_4 | GPIO_BSRR_BS_5 | \
+ GPIO_BSRR_BS_6 | GPIO_BSRR_BS_7 | GPIO_BSRR_BS_8 | \
+ GPIO_BSRR_BS_9 | GPIO_BSRR_BS_10 | GPIO_BSRR_BS_11 | \
+ GPIO_BSRR_BS_12 | GPIO_BSRR_BS_13 | GPIO_BSRR_BS_14 | \
+ GPIO_BSRR_BS_15) /*!< Select all pins */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_LL_EC_MODE Mode
+ * @{
+ */
+#define LL_GPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */
+#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODER0_0 /*!< Select output mode */
+#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODER0_1 /*!< Select alternate function mode */
+#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODER0 /*!< Select analog mode */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_LL_EC_OUTPUT Output Type
+ * @{
+ */
+#define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U) /*!< Select push-pull as output type */
+#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT_0 /*!< Select open-drain as output type */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_LL_EC_SPEED Output Speed
+ * @{
+ */
+#define LL_GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Select I/O low output speed */
+#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDER_OSPEEDR0_0 /*!< Select I/O medium output speed */
+#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDER_OSPEEDR0 /*!< Select I/O high output speed */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
+ * @{
+ */
+#define LL_GPIO_PULL_NO (0x00000000U) /*!< Select I/O no pull */
+#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPDR0_0 /*!< Select I/O pull up */
+#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPDR0_1 /*!< Select I/O pull down */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_LL_EC_AF Alternate Function
+ * @{
+ */
+#define LL_GPIO_AF_0 (0x0000000U) /*!< Select alternate function 0 */
+#define LL_GPIO_AF_1 (0x0000001U) /*!< Select alternate function 1 */
+#define LL_GPIO_AF_2 (0x0000002U) /*!< Select alternate function 2 */
+#define LL_GPIO_AF_3 (0x0000003U) /*!< Select alternate function 3 */
+#define LL_GPIO_AF_4 (0x0000004U) /*!< Select alternate function 4 */
+#define LL_GPIO_AF_5 (0x0000005U) /*!< Select alternate function 5 */
+#define LL_GPIO_AF_6 (0x0000006U) /*!< Select alternate function 6 */
+#define LL_GPIO_AF_7 (0x0000007U) /*!< Select alternate function 7 */
+#define LL_GPIO_AF_8 (0x0000008U) /*!< Select alternate function 8 */
+#define LL_GPIO_AF_9 (0x0000009U) /*!< Select alternate function 9 */
+#define LL_GPIO_AF_10 (0x000000AU) /*!< Select alternate function 10 */
+#define LL_GPIO_AF_11 (0x000000BU) /*!< Select alternate function 11 */
+#define LL_GPIO_AF_12 (0x000000CU) /*!< Select alternate function 12 */
+#define LL_GPIO_AF_13 (0x000000DU) /*!< Select alternate function 13 */
+#define LL_GPIO_AF_14 (0x000000EU) /*!< Select alternate function 14 */
+#define LL_GPIO_AF_15 (0x000000FU) /*!< Select alternate function 15 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
+ * @{
+ */
+
+/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in GPIO register
+ * @param __INSTANCE__ GPIO Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in GPIO register
+ * @param __INSTANCE__ GPIO Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
+ * @{
+ */
+
+/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
+ * @{
+ */
+
+/**
+ * @brief Configure gpio mode for a dedicated pin on dedicated port.
+ * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll MODER MODEy LL_GPIO_SetPinMode
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_MODE_INPUT
+ * @arg @ref LL_GPIO_MODE_OUTPUT
+ * @arg @ref LL_GPIO_MODE_ALTERNATE
+ * @arg @ref LL_GPIO_MODE_ANALOG
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
+{
+ MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U)));
+}
+
+/**
+ * @brief Return gpio mode for a dedicated pin on dedicated port.
+ * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll MODER MODEy LL_GPIO_GetPinMode
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_GPIO_MODE_INPUT
+ * @arg @ref LL_GPIO_MODE_OUTPUT
+ * @arg @ref LL_GPIO_MODE_ALTERNATE
+ * @arg @ref LL_GPIO_MODE_ANALOG
+ */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+ return (uint32_t)(READ_BIT(GPIOx->MODER,
+ (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
+}
+
+/**
+ * @brief Configure gpio output type for several pins on dedicated port.
+ * @note Output type as to be set when gpio pin is in output or
+ * alternate modes. Possible type are Push-pull or Open-drain.
+ * @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @param OutputType This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_OUTPUT_PUSHPULL
+ * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
+{
+ MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
+}
+
+/**
+ * @brief Return gpio output type for several pins on dedicated port.
+ * @note Output type as to be set when gpio pin is in output or
+ * alternate modes. Possible type are Push-pull or Open-drain.
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_GPIO_OUTPUT_PUSHPULL
+ * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
+ */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+ return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin));
+}
+
+/**
+ * @brief Configure gpio speed for a dedicated pin on dedicated port.
+ * @note I/O speed can be Low, Medium, Fast or High speed.
+ * @note Warning: only one pin can be passed as parameter.
+ * @note Refer to datasheet for frequency specifications and the power
+ * supply and load conditions for each speed.
+ * @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @param Speed This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_SPEED_FREQ_LOW
+ * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
+ * @arg @ref LL_GPIO_SPEED_FREQ_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed)
+{
+ MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U)),
+ (Speed << (POSITION_VAL(Pin) * 2U)));
+}
+
+/**
+ * @brief Return gpio speed for a dedicated pin on dedicated port.
+ * @note I/O speed can be Low, Medium, Fast or High speed.
+ * @note Warning: only one pin can be passed as parameter.
+ * @note Refer to datasheet for frequency specifications and the power
+ * supply and load conditions for each speed.
+ * @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_GPIO_SPEED_FREQ_LOW
+ * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
+ * @arg @ref LL_GPIO_SPEED_FREQ_HIGH
+ */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+ return (uint32_t)(READ_BIT(GPIOx->OSPEEDR,
+ (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
+}
+
+/**
+ * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @param Pull This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PULL_NO
+ * @arg @ref LL_GPIO_PULL_UP
+ * @arg @ref LL_GPIO_PULL_DOWN
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
+{
+ MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U)));
+}
+
+/**
+ * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_GPIO_PULL_NO
+ * @arg @ref LL_GPIO_PULL_UP
+ * @arg @ref LL_GPIO_PULL_DOWN
+ */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+ return (uint32_t)(READ_BIT(GPIOx->PUPDR,
+ (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
+}
+
+/**
+ * @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
+ * @note Possible values are from AF0 to AF15 depending on target.
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @param Alternate This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_AF_0
+ * @arg @ref LL_GPIO_AF_1
+ * @arg @ref LL_GPIO_AF_2
+ * @arg @ref LL_GPIO_AF_3
+ * @arg @ref LL_GPIO_AF_4
+ * @arg @ref LL_GPIO_AF_5
+ * @arg @ref LL_GPIO_AF_6
+ * @arg @ref LL_GPIO_AF_7
+ * @arg @ref LL_GPIO_AF_8
+ * @arg @ref LL_GPIO_AF_9
+ * @arg @ref LL_GPIO_AF_10
+ * @arg @ref LL_GPIO_AF_11
+ * @arg @ref LL_GPIO_AF_12
+ * @arg @ref LL_GPIO_AF_13
+ * @arg @ref LL_GPIO_AF_14
+ * @arg @ref LL_GPIO_AF_15
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
+{
+ MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFRL0 << (POSITION_VAL(Pin) * 4U)),
+ (Alternate << (POSITION_VAL(Pin) * 4U)));
+}
+
+/**
+ * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
+ * @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_GPIO_AF_0
+ * @arg @ref LL_GPIO_AF_1
+ * @arg @ref LL_GPIO_AF_2
+ * @arg @ref LL_GPIO_AF_3
+ * @arg @ref LL_GPIO_AF_4
+ * @arg @ref LL_GPIO_AF_5
+ * @arg @ref LL_GPIO_AF_6
+ * @arg @ref LL_GPIO_AF_7
+ * @arg @ref LL_GPIO_AF_8
+ * @arg @ref LL_GPIO_AF_9
+ * @arg @ref LL_GPIO_AF_10
+ * @arg @ref LL_GPIO_AF_11
+ * @arg @ref LL_GPIO_AF_12
+ * @arg @ref LL_GPIO_AF_13
+ * @arg @ref LL_GPIO_AF_14
+ * @arg @ref LL_GPIO_AF_15
+ */
+__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+ return (uint32_t)(READ_BIT(GPIOx->AFR[0],
+ (GPIO_AFRL_AFRL0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
+}
+
+/**
+ * @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
+ * @note Possible values are from AF0 to AF15 depending on target.
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @param Alternate This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_AF_0
+ * @arg @ref LL_GPIO_AF_1
+ * @arg @ref LL_GPIO_AF_2
+ * @arg @ref LL_GPIO_AF_3
+ * @arg @ref LL_GPIO_AF_4
+ * @arg @ref LL_GPIO_AF_5
+ * @arg @ref LL_GPIO_AF_6
+ * @arg @ref LL_GPIO_AF_7
+ * @arg @ref LL_GPIO_AF_8
+ * @arg @ref LL_GPIO_AF_9
+ * @arg @ref LL_GPIO_AF_10
+ * @arg @ref LL_GPIO_AF_11
+ * @arg @ref LL_GPIO_AF_12
+ * @arg @ref LL_GPIO_AF_13
+ * @arg @ref LL_GPIO_AF_14
+ * @arg @ref LL_GPIO_AF_15
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
+{
+ MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFRH0 << (POSITION_VAL(Pin >> 8U) * 4U)),
+ (Alternate << (POSITION_VAL(Pin >> 8U) * 4U)));
+}
+
+/**
+ * @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
+ * @note Possible values are from AF0 to AF15 depending on target.
+ * @rmtoll AFRH AFSELy LL_GPIO_GetAFPin_8_15
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_GPIO_AF_0
+ * @arg @ref LL_GPIO_AF_1
+ * @arg @ref LL_GPIO_AF_2
+ * @arg @ref LL_GPIO_AF_3
+ * @arg @ref LL_GPIO_AF_4
+ * @arg @ref LL_GPIO_AF_5
+ * @arg @ref LL_GPIO_AF_6
+ * @arg @ref LL_GPIO_AF_7
+ * @arg @ref LL_GPIO_AF_8
+ * @arg @ref LL_GPIO_AF_9
+ * @arg @ref LL_GPIO_AF_10
+ * @arg @ref LL_GPIO_AF_11
+ * @arg @ref LL_GPIO_AF_12
+ * @arg @ref LL_GPIO_AF_13
+ * @arg @ref LL_GPIO_AF_14
+ * @arg @ref LL_GPIO_AF_15
+ */
+__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+ return (uint32_t)(READ_BIT(GPIOx->AFR[1],
+ (GPIO_AFRH_AFRH0 << (POSITION_VAL(Pin >> 8U) * 4U))) >> (POSITION_VAL(Pin >> 8U) * 4U));
+}
+
+
+/**
+ * @brief Lock configuration of several pins for a dedicated port.
+ * @note When the lock sequence has been applied on a port bit, the
+ * value of this port bit can no longer be modified until the
+ * next reset.
+ * @note Each lock bit freezes a specific configuration register
+ * (control and alternate function registers).
+ * @rmtoll LCKR LCKK LL_GPIO_LockPin
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ __IO uint32_t temp;
+ WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
+ WRITE_REG(GPIOx->LCKR, PinMask);
+ WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
+ temp = READ_REG(GPIOx->LCKR);
+ (void) temp;
+}
+
+/**
+ * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.
+ * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ return (READ_BIT(GPIOx->LCKR, PinMask) == (PinMask));
+}
+
+/**
+ * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0.
+ * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked
+ * @param GPIOx GPIO Port
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)
+{
+ return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_LL_EF_Data_Access Data Access
+ * @{
+ */
+
+/**
+ * @brief Return full input data register value for a dedicated port.
+ * @rmtoll IDR IDy LL_GPIO_ReadInputPort
+ * @param GPIOx GPIO Port
+ * @retval Input data register value of port
+ */
+__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
+{
+ return (uint32_t)(READ_REG(GPIOx->IDR));
+}
+
+/**
+ * @brief Return if input data level for several pins of dedicated port is high or low.
+ * @rmtoll IDR IDy LL_GPIO_IsInputPinSet
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ return (READ_BIT(GPIOx->IDR, PinMask) == (PinMask));
+}
+
+/**
+ * @brief Write output data register for the port.
+ * @rmtoll ODR ODy LL_GPIO_WriteOutputPort
+ * @param GPIOx GPIO Port
+ * @param PortValue Level value for each pin of the port
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)
+{
+ WRITE_REG(GPIOx->ODR, PortValue);
+}
+
+/**
+ * @brief Return full output data register value for a dedicated port.
+ * @rmtoll ODR ODy LL_GPIO_ReadOutputPort
+ * @param GPIOx GPIO Port
+ * @retval Output data register value of port
+ */
+__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)
+{
+ return (uint32_t)(READ_REG(GPIOx->ODR));
+}
+
+/**
+ * @brief Return if input data level for several pins of dedicated port is high or low.
+ * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ return (READ_BIT(GPIOx->ODR, PinMask) == (PinMask));
+}
+
+/**
+ * @brief Set several pins to high level on dedicated gpio port.
+ * @rmtoll BSRR BSy LL_GPIO_SetOutputPin
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ WRITE_REG(GPIOx->BSRR, PinMask);
+}
+
+/**
+ * @brief Set several pins to low level on dedicated gpio port.
+ * @rmtoll BRR BRy LL_GPIO_ResetOutputPin
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ WRITE_REG(GPIOx->BRR, PinMask);
+}
+
+/**
+ * @brief Toggle data value for several pin of dedicated port.
+ * @rmtoll ODR ODy LL_GPIO_TogglePin
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ PinMask);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);
+ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct);
+void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) */
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_LL_GPIO_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_ll_hrtim.h b/Inc/stm32f3xx_ll_hrtim.h
new file mode 100644
index 0000000..2a3a90c
--- /dev/null
+++ b/Inc/stm32f3xx_ll_hrtim.h
@@ -0,0 +1,10542 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_hrtim.h
+ * @author MCD Application Team
+ * @brief Header file of HRTIM LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_LL_HRTIM_H
+#define __STM32F3xx_LL_HRTIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx.h"
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined (HRTIM1)
+
+/** @defgroup HRTIM_LL HRTIM
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup HRTIM_LL_Private_Variables HRTIM Private Variables
+ * @{
+ */
+static const uint16_t REG_OFFSET_TAB_TIMER[] =
+{
+ 0x00U, /* 0: MASTER */
+ 0x80U, /* 1: TIMER A */
+ 0x100U, /* 2: TIMER B */
+ 0x180U, /* 3: TIMER C */
+ 0x200U, /* 4: TIMER D */
+ 0x280U, /* 5: TIMER E */
+};
+
+static const uint8_t REG_OFFSET_TAB_ADCxR[] =
+{
+ 0x00U, /* 0: HRTIM_ADC1R */
+ 0x04U, /* 1: HRTIM_ADC2R */
+ 0x08U, /* 2: HRTIM_ADC3R */
+ 0x0CU, /* 3: HRTIM_ADC4R */
+};
+
+static const uint16_t REG_OFFSET_TAB_SETxR[] =
+{
+ 0x00U, /* 0: TA1 */
+ 0x08U, /* 1: TA2 */
+ 0x80U, /* 2: TB1 */
+ 0x88U, /* 3: TB2 */
+ 0x100U, /* 4: TC1 */
+ 0x108U, /* 5: TC2 */
+ 0x180U, /* 6: TD1 */
+ 0x188U, /* 7: TD2 */
+ 0x200U, /* 8: TE1 */
+ 0x208U /* 9: TE2 */
+};
+
+static const uint16_t REG_OFFSET_TAB_OUTxR[] =
+{
+ 0x00U, /* 0: TA1 */
+ 0x00U, /* 1: TA2 */
+ 0x80U, /* 2: TB1 */
+ 0x80U, /* 3: TB2 */
+ 0x100U, /* 4: TC1 */
+ 0x100U, /* 5: TC2 */
+ 0x180U, /* 6: TD1 */
+ 0x180U, /* 7: TD2 */
+ 0x200U, /* 8: TE1 */
+ 0x200U /* 9: TE2 */
+};
+
+
+static const uint8_t REG_OFFSET_TAB_OUT_LEVEL[] =
+{
+ 0x04U, /* 0: LL_HRTIM_OUT_LEVEL_INACTIVE */
+ 0x00U /* 1: LL_HRTIM_OUT_LEVEL_ACTIVE */
+};
+
+static const uint8_t REG_OFFSET_TAB_EECR[] =
+{
+ 0x00U, /* LL_HRTIM_EVENT_1 */
+ 0x00U, /* LL_HRTIM_EVENT_2 */
+ 0x00U, /* LL_HRTIM_EVENT_3 */
+ 0x00U, /* LL_HRTIM_EVENT_4 */
+ 0x00U, /* LL_HRTIM_EVENT_5 */
+ 0x04U, /* LL_HRTIM_EVENT_6 */
+ 0x04U, /* LL_HRTIM_EVENT_7 */
+ 0x04U, /* LL_HRTIM_EVENT_8 */
+ 0x04U, /* LL_HRTIM_EVENT_9 */
+ 0x04U /* LL_HRTIM_EVENT_10 */
+};
+
+static const uint8_t REG_OFFSET_TAB_FLTINR[] =
+{
+ 0x00U, /* LL_HRTIM_FAULT_1 */
+ 0x00U, /* LL_HRTIM_FAULT_2 */
+ 0x00U, /* LL_HRTIM_FAULT_3 */
+ 0x00U, /* LL_HRTIM_FAULT_4 */
+ 0x04U /* LL_HRTIM_FAULT_5 */
+};
+
+static const uint32_t REG_MASK_TAB_UPDATETRIG[] =
+{
+ 0x20000000U, /* 0: MASTER */
+ 0x01FE0000U, /* 1: TIMER A */
+ 0x01FE0000U, /* 2: TIMER B */
+ 0x01FE0000U, /* 3: TIMER C */
+ 0x01FE0000U, /* 4: TIMER D */
+ 0x01FE0000U, /* 5: TIMER E */
+};
+
+static const uint8_t REG_SHIFT_TAB_UPDATETRIG[] =
+{
+ 12U, /* 0: MASTER */
+ 0U, /* 1: TIMER A */
+ 0U, /* 2: TIMER B */
+ 0U, /* 3: TIMER C */
+ 0U, /* 4: TIMER D */
+ 0U, /* 5: TIMER E */
+};
+
+static const uint8_t REG_SHIFT_TAB_EExSRC[] =
+{
+ 0U, /* LL_HRTIM_EVENT_1 */
+ 6U, /* LL_HRTIM_EVENT_2 */
+ 12U, /* LL_HRTIM_EVENT_3 */
+ 18U, /* LL_HRTIM_EVENT_4 */
+ 24U, /* LL_HRTIM_EVENT_5 */
+ 0U, /* LL_HRTIM_EVENT_6 */
+ 6U, /* LL_HRTIM_EVENT_7 */
+ 12U, /* LL_HRTIM_EVENT_8 */
+ 18U, /* LL_HRTIM_EVENT_9 */
+ 24U /* LL_HRTIM_EVENT_10 */
+};
+
+static const uint32_t REG_MASK_TAB_UPDATEGATING[] =
+{
+ HRTIM_MCR_BRSTDMA, /* 0: MASTER */
+ HRTIM_TIMCR_UPDGAT, /* 1: TIMER A */
+ HRTIM_TIMCR_UPDGAT, /* 2: TIMER B */
+ HRTIM_TIMCR_UPDGAT, /* 3: TIMER C */
+ HRTIM_TIMCR_UPDGAT, /* 4: TIMER D */
+ HRTIM_TIMCR_UPDGAT, /* 5: TIMER E */
+};
+
+static const uint8_t REG_SHIFT_TAB_UPDATEGATING[] =
+{
+ 2U, /* 0: MASTER */
+ 0U, /* 1: TIMER A */
+ 0U, /* 2: TIMER B */
+ 0U, /* 3: TIMER C */
+ 0U, /* 4: TIMER D */
+ 0U, /* 5: TIMER E */
+};
+
+static const uint8_t REG_SHIFT_TAB_OUTxR[] =
+{
+ 0U, /* 0: TA1 */
+ 16U, /* 1: TA2 */
+ 0U, /* 2: TB1 */
+ 16U, /* 3: TB2 */
+ 0U, /* 4: TC1 */
+ 16U, /* 5: TC2 */
+ 0U, /* 6: TD1 */
+ 16U, /* 7: TD2 */
+ 0U, /* 8: TE1 */
+ 16U /* 9: TE2 */
+};
+
+static const uint8_t REG_SHIFT_TAB_OxSTAT[] =
+{
+ 0U, /* 0: TA1 */
+ 1U, /* 1: TA2 */
+ 0U, /* 2: TB1 */
+ 1U, /* 3: TB2 */
+ 0U, /* 4: TC1 */
+ 1U, /* 5: TC2 */
+ 0U, /* 6: TD1 */
+ 1U, /* 7: TD2 */
+ 0U, /* 8: TE1 */
+ 1U /* 9: TE2 */
+};
+
+static const uint8_t REG_SHIFT_TAB_FLTxE[] =
+{
+ 0U, /* LL_HRTIM_FAULT_1 */
+ 8U, /* LL_HRTIM_FAULT_2 */
+ 16U, /* LL_HRTIM_FAULT_3 */
+ 24U, /* LL_HRTIM_FAULT_4 */
+ 0U /* LL_HRTIM_FAULT_5 */
+};
+
+/**
+ * @}
+ */
+
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup HRTIM_LL_Private_Constants HRTIM Private Constants
+ * @{
+ */
+#define HRTIM_CR1_UDIS_MASK ((uint32_t)(HRTIM_CR1_MUDIS |\
+ HRTIM_CR1_TAUDIS |\
+ HRTIM_CR1_TBUDIS |\
+ HRTIM_CR1_TCUDIS |\
+ HRTIM_CR1_TDUDIS |\
+ HRTIM_CR1_TEUDIS))
+
+#define HRTIM_CR2_SWUPD_MASK ((uint32_t)(HRTIM_CR2_MSWU |\
+ HRTIM_CR2_TASWU |\
+ HRTIM_CR2_TBSWU |\
+ HRTIM_CR2_TCSWU |\
+ HRTIM_CR2_TDSWU |\
+ HRTIM_CR2_TESWU))
+
+#define HRTIM_CR2_SWRST_MASK ((uint32_t)(HRTIM_CR2_MRST |\
+ HRTIM_CR2_TARST |\
+ HRTIM_CR2_TBRST |\
+ HRTIM_CR2_TCRST |\
+ HRTIM_CR2_TDRST |\
+ HRTIM_CR2_TERST))
+
+#define HRTIM_OENR_OEN_MASK ((uint32_t)(HRTIM_OENR_TA1OEN |\
+ HRTIM_OENR_TA2OEN |\
+ HRTIM_OENR_TB1OEN |\
+ HRTIM_OENR_TB2OEN |\
+ HRTIM_OENR_TC1OEN |\
+ HRTIM_OENR_TC2OEN |\
+ HRTIM_OENR_TD1OEN |\
+ HRTIM_OENR_TD2OEN |\
+ HRTIM_OENR_TE1OEN |\
+ HRTIM_OENR_TE2OEN))
+
+#define HRTIM_OENR_ODIS_MASK ((uint32_t)(HRTIM_ODISR_TA1ODIS |\
+ HRTIM_ODISR_TA2ODIS |\
+ HRTIM_ODISR_TB1ODIS |\
+ HRTIM_ODISR_TB2ODIS |\
+ HRTIM_ODISR_TC1ODIS |\
+ HRTIM_ODISR_TC2ODIS |\
+ HRTIM_ODISR_TD1ODIS |\
+ HRTIM_ODISR_TD2ODIS |\
+ HRTIM_ODISR_TE1ODIS |\
+ HRTIM_ODISR_TE2ODIS))
+
+#define HRTIM_OUT_CONFIG_MASK ((uint32_t)(HRTIM_OUTR_POL1 |\
+ HRTIM_OUTR_IDLM1 |\
+ HRTIM_OUTR_IDLES1 |\
+ HRTIM_OUTR_FAULT1 |\
+ HRTIM_OUTR_CHP1 |\
+ HRTIM_OUTR_DIDL1))
+
+#define HRTIM_EE_CONFIG_MASK ((uint32_t)(HRTIM_EECR1_EE1SRC |\
+ HRTIM_EECR1_EE1POL |\
+ HRTIM_EECR1_EE1SNS |\
+ HRTIM_EECR1_EE1FAST))
+
+#define HRTIM_FLT_CONFIG_MASK ((uint32_t)(HRTIM_FLTINR1_FLT1P |\
+ HRTIM_FLTINR1_FLT1SRC))
+
+#define HRTIM_BM_CONFIG_MASK ((uint32_t)( HRTIM_BMCR_BMPRSC |\
+ HRTIM_BMCR_BMCLK |\
+ HRTIM_BMCR_BMOM))
+
+/**
+ * @}
+ */
+
+
+/* Private macros ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup HRTIM_LL_ES_INIT HRTIM Exported Init structure
+ * @{
+ */
+/* TO BE COMPLETED */
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup HRTIM_LL_Exported_Constants HRTIM Exported Constants
+ * @{
+ */
+
+/** @defgroup HRTIM_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_HRTIM_ReadReg function
+ * @{
+ */
+#define LL_HRTIM_ISR_FLT1 HRTIM_ISR_FLT1
+#define LL_HRTIM_ISR_FLT2 HRTIM_ISR_FLT2
+#define LL_HRTIM_ISR_FLT3 HRTIM_ISR_FLT3
+#define LL_HRTIM_ISR_FLT4 HRTIM_ISR_FLT4
+#define LL_HRTIM_ISR_FLT5 HRTIM_ISR_FLT5
+#define LL_HRTIM_ISR_SYSFLT HRTIM_ISR_SYSFLT
+#define LL_HRTIM_ISR_DLLRDY HRTIM_ISR_DLLRDY
+#define LL_HRTIM_ISR_BMPER HRTIM_ISR_BMPER
+
+#define LL_HRTIM_MISR_MCMP1 HRTIM_MISR_MCMP1
+#define LL_HRTIM_MISR_MCMP2 HRTIM_MISR_MCMP2
+#define LL_HRTIM_MISR_MCMP3 HRTIM_MISR_MCMP3
+#define LL_HRTIM_MISR_MCMP4 HRTIM_MISR_MCMP4
+#define LL_HRTIM_MISR_MREP HRTIM_MISR_MREP
+#define LL_HRTIM_MISR_SYNC HRTIM_MISR_SYNC
+#define LL_HRTIM_MISR_MUPD HRTIM_MISR_MUPD
+
+#define LL_HRTIM_TIMISR_CMP1 HRTIM_TIMISR_CMP1
+#define LL_HRTIM_TIMISR_CMP2 HRTIM_TIMISR_CMP2
+#define LL_HRTIM_TIMISR_CMP3 HRTIM_TIMISR_CMP3
+#define LL_HRTIM_TIMISR_CMP4 HRTIM_TIMISR_CMP4
+#define LL_HRTIM_TIMISR_REP HRTIM_TIMISR_REP
+#define LL_HRTIM_TIMISR_UPD HRTIM_TIMISR_UPD
+#define LL_HRTIM_TIMISR_CPT1 HRTIM_TIMISR_CPT1
+#define LL_HRTIM_TIMISR_CPT2 HRTIM_TIMISR_CPT2
+#define LL_HRTIM_TIMISR_SET1 HRTIM_TIMISR_SET1
+#define LL_HRTIM_TIMISR_RST1 HRTIM_TIMISR_RST1
+#define LL_HRTIM_TIMISR_SET2 HRTIM_TIMISR_SET2
+#define LL_HRTIM_TIMISR_RST2 HRTIM_TIMISR_RST2
+#define LL_HRTIM_TIMISR_RST HRTIM_TIMISR_RST
+#define LL_HRTIM_TIMISR_DLYPRT HRTIM_TIMISR_DLYPRT
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_HRTIM_ReadReg and LL_HRTIM_WriteReg functions
+ * @{
+ */
+#define LL_HRTIM_IER_FLT1IE HRTIM_IER_FLT1IE
+#define LL_HRTIM_IER_FLT2IE HRTIM_IER_FLT2IE
+#define LL_HRTIM_IER_FLT3IE HRTIM_IER_FLT3IE
+#define LL_HRTIM_IER_FLT4IE HRTIM_IER_FLT4IE
+#define LL_HRTIM_IER_FLT5IE HRTIM_IER_FLT5IE
+#define LL_HRTIM_IER_SYSFLTIE HRTIM_IER_SYSFLTIE
+#define LL_HRTIM_IER_DLLRDYIE HRTIM_IER_DLLRDYIE
+#define LL_HRTIM_IER_BMPERIE HRTIM_IER_BMPERIE
+
+#define LL_HRTIM_MDIER_MCMP1IE HRTIM_MDIER_MCMP1IE
+#define LL_HRTIM_MDIER_MCMP2IE HRTIM_MDIER_MCMP2IE
+#define LL_HRTIM_MDIER_MCMP3IE HRTIM_MDIER_MCMP3IE
+#define LL_HRTIM_MDIER_MCMP4IE HRTIM_MDIER_MCMP4IE
+#define LL_HRTIM_MDIER_MREPIE HRTIM_MDIER_MREPIE
+#define LL_HRTIM_MDIER_SYNCIE HRTIM_MDIER_SYNCIE
+#define LL_HRTIM_MDIER_MUPDIE HRTIM_MDIER_MUPDIE
+
+
+#define LL_HRTIM_TIMDIER_CMP1IE HRTIM_TIMDIER_CMP1IE
+#define LL_HRTIM_TIMDIER_CMP2IE HRTIM_TIMDIER_CMP2IE
+#define LL_HRTIM_TIMDIER_CMP3IE HRTIM_TIMDIER_CMP3IE
+#define LL_HRTIM_TIMDIER_CMP4IE HRTIM_TIMDIER_CMP4IE
+#define LL_HRTIM_TIMDIER_REPIE HRTIM_TIMDIER_REPIE
+#define LL_HRTIM_TIMDIER_UPDIE HRTIM_TIMDIER_UPDIE
+#define LL_HRTIM_TIMDIER_CPT1IE HRTIM_TIMDIER_CPT1IE
+#define LL_HRTIM_TIMDIER_CPT2IE HRTIM_TIMDIER_CPT2IE
+#define LL_HRTIM_TIMDIER_SET1IE HRTIM_TIMDIER_SET1IE
+#define LL_HRTIM_TIMDIER_RST1IE HRTIM_TIMDIER_RST1IE
+#define LL_HRTIM_TIMDIER_SET2IE HRTIM_TIMDIER_SET2IE
+#define LL_HRTIM_TIMDIER_RST2IE HRTIM_TIMDIER_RST2IE
+#define LL_HRTIM_TIMDIER_RSTIE HRTIM_TIMDIER_RSTIE
+#define LL_HRTIM_TIMDIER_DLYPRTIE HRTIM_TIMDIER_DLYPRTIE
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_SYNCIN_SRC SYNCHRONIZATION INPUT SOURCE
+ * @{
+ * @brief Constants defining defining the synchronization input source.
+ */
+#define LL_HRTIM_SYNCIN_SRC_NONE ((uint32_t)0x00000000U) /*!< HRTIM is not synchronized and runs in standalone mode */
+#define LL_HRTIM_SYNCIN_SRC_TIM_EVENT (HRTIM_MCR_SYNC_IN_1) /*!< The HRTIM is synchronized with the on-chip timer */
+#define LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT (HRTIM_MCR_SYNC_IN_1 | HRTIM_MCR_SYNC_IN_0) /*!< A positive pulse on SYNCIN input triggers the HRTIM */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_SYNCOUT_SRC SYNCHRONIZATION OUTPUT SOURCE
+ * @{
+ * @brief Constants defining the source and event to be sent on the synchronization output.
+ */
+#define LL_HRTIM_SYNCOUT_SRC_MASTER_START ((uint32_t)0x00000000U) /*!< A pulse is sent on the SYNCOUT output upon master timer start event */
+#define LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output upon master timer compare 1 event*/
+#define LL_HRTIM_SYNCOUT_SRC_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /*!< A pulse is sent on the SYNCOUT output upon timer A start or reset events */
+#define LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output upon timer A compare 1 event */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_SYNCOUT_POLARITY SYNCHRONIZATION OUTPUT POLARITY
+ * @{
+ * @brief Constants defining the routing and conditioning of the synchronization output event.
+ */
+#define LL_HRTIM_SYNCOUT_DISABLED ((uint32_t)0x00000000U) /*!< Synchronization output event is disabled */
+#define LL_HRTIM_SYNCOUT_POSITIVE_PULSE (HRTIM_MCR_SYNC_OUT_1) /*!< SCOUT pin has a low idle level and issues a positive pulse of 16 fHRTIM clock cycles length for the synchronization */
+#define LL_HRTIM_SYNCOUT_NEGATIVE_PULSE (HRTIM_MCR_SYNC_OUT_1 | HRTIM_MCR_SYNC_OUT_0) /*!< SCOUT pin has a high idle level and issues a negative pulse of 16 fHRTIM clock cycles length for the synchronization */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_TIMER TIMER ID
+ * @{
+ * @brief Constants identifying a timing unit.
+ */
+#define LL_HRTIM_TIMER_MASTER HRTIM_MCR_MCEN /*!< Master timer identifier */
+#define LL_HRTIM_TIMER_A HRTIM_MCR_TACEN /*!< Timer A identifier */
+#define LL_HRTIM_TIMER_B HRTIM_MCR_TBCEN /*!< Timer B identifier */
+#define LL_HRTIM_TIMER_C HRTIM_MCR_TCCEN /*!< Timer C identifier */
+#define LL_HRTIM_TIMER_D HRTIM_MCR_TDCEN /*!< Timer D identifier */
+#define LL_HRTIM_TIMER_E HRTIM_MCR_TECEN /*!< Timer E identifier */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_OUTPUT OUTPUT ID
+ * @{
+ * @brief Constants identifying an HRTIM output.
+ */
+#define LL_HRTIM_OUTPUT_TA1 HRTIM_OENR_TA1OEN /*!< Timer A - Output 1 identifier */
+#define LL_HRTIM_OUTPUT_TA2 HRTIM_OENR_TA2OEN /*!< Timer A - Output 2 identifier */
+#define LL_HRTIM_OUTPUT_TB1 HRTIM_OENR_TB1OEN /*!< Timer B - Output 1 identifier */
+#define LL_HRTIM_OUTPUT_TB2 HRTIM_OENR_TB2OEN /*!< Timer B - Output 2 identifier */
+#define LL_HRTIM_OUTPUT_TC1 HRTIM_OENR_TC1OEN /*!< Timer C - Output 1 identifier */
+#define LL_HRTIM_OUTPUT_TC2 HRTIM_OENR_TC2OEN /*!< Timer C - Output 2 identifier */
+#define LL_HRTIM_OUTPUT_TD1 HRTIM_OENR_TD1OEN /*!< Timer D - Output 1 identifier */
+#define LL_HRTIM_OUTPUT_TD2 HRTIM_OENR_TD2OEN /*!< Timer D - Output 2 identifier */
+#define LL_HRTIM_OUTPUT_TE1 HRTIM_OENR_TE1OEN /*!< Timer E - Output 1 identifier */
+#define LL_HRTIM_OUTPUT_TE2 HRTIM_OENR_TE2OEN /*!< Timer E - Output 2 identifier */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_COMPAREUNIT COMPARE UNIT ID
+ * @{
+ * @brief Constants identifying a compare unit.
+ */
+#define LL_HRTIM_COMPAREUNIT_2 HRTIM_TIMCR_DELCMP2 /*!< Compare unit 2 identifier */
+#define LL_HRTIM_COMPAREUNIT_4 HRTIM_TIMCR_DELCMP4 /*!< Compare unit 4 identifier */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_CAPTUREUNIT CAPTURE UNIT ID
+ * @{
+ * @brief Constants identifying a capture unit.
+ */
+#define LL_HRTIM_CAPTUREUNIT_1 0 /*!< Capture unit 1 identifier */
+#define LL_HRTIM_CAPTUREUNIT_2 1 /*!< Capture unit 2 identifier */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_FAULT FAULT ID
+ * @{
+ * @brief Constants identifying a fault channel.
+ */
+#define LL_HRTIM_FAULT_1 HRTIM_FLTR_FLT1EN /*!< Fault channel 1 identifier */
+#define LL_HRTIM_FAULT_2 HRTIM_FLTR_FLT2EN /*!< Fault channel 2 identifier */
+#define LL_HRTIM_FAULT_3 HRTIM_FLTR_FLT3EN /*!< Fault channel 3 identifier */
+#define LL_HRTIM_FAULT_4 HRTIM_FLTR_FLT4EN /*!< Fault channel 4 identifier */
+#define LL_HRTIM_FAULT_5 HRTIM_FLTR_FLT5EN /*!< Fault channel 5 identifier */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_EVENT EXTERNAL EVENT ID
+ * @{
+ * @brief Constants identifying an external event channel.
+ */
+#define LL_HRTIM_EVENT_1 ((uint32_t)0x00000001U) /*!< External event channel 1 identifier */
+#define LL_HRTIM_EVENT_2 ((uint32_t)0x00000002U) /*!< External event channel 2 identifier */
+#define LL_HRTIM_EVENT_3 ((uint32_t)0x00000004U) /*!< External event channel 3 identifier */
+#define LL_HRTIM_EVENT_4 ((uint32_t)0x00000008U) /*!< External event channel 4 identifier */
+#define LL_HRTIM_EVENT_5 ((uint32_t)0x00000010U) /*!< External event channel 5 identifier */
+#define LL_HRTIM_EVENT_6 ((uint32_t)0x00000020U) /*!< External event channel 6 identifier */
+#define LL_HRTIM_EVENT_7 ((uint32_t)0x00000040U) /*!< External event channel 7 identifier */
+#define LL_HRTIM_EVENT_8 ((uint32_t)0x00000080U) /*!< External event channel 8 identifier */
+#define LL_HRTIM_EVENT_9 ((uint32_t)0x00000100U) /*!< External event channel 9 identifier */
+#define LL_HRTIM_EVENT_10 ((uint32_t)0x00000200U) /*!< External event channel 10 identifier */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_OUTPUTSTATE OUTPUT STATE
+ * @{
+ * @brief Constants defining the state of an HRTIM output.
+ */
+#define LL_HRTIM_OUTPUTSTATE_IDLE ((uint32_t)0x00000001U) /*!< Main operating mode, where the output can take the active or inactive level as programmed in the crossbar unit */
+#define LL_HRTIM_OUTPUTSTATE_RUN ((uint32_t)0x00000002U) /*!< Default operating state (e.g. after an HRTIM reset, when the outputs are disabled by software or during a burst mode operation) */
+#define LL_HRTIM_OUTPUTSTATE_FAULT ((uint32_t)0x00000003U) /*!< Safety state, entered in case of a shut-down request on FAULTx inputs */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_ADCTRIG ADC TRIGGER
+ * @{
+ * @brief Constants identifying an ADC trigger.
+ */
+#define LL_HRTIM_ADCTRIG_1 ((uint32_t)0x00000000U) /*!< ADC trigger 1 identifier */
+#define LL_HRTIM_ADCTRIG_2 ((uint32_t)0x00000001U) /*!< ADC trigger 2 identifier */
+#define LL_HRTIM_ADCTRIG_3 ((uint32_t)0x00000002U) /*!< ADC trigger 3 identifier */
+#define LL_HRTIM_ADCTRIG_4 ((uint32_t)0x00000003U) /*!< ADC trigger 4 identifier */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_ADCTRIG_UPDATE ADC TRIGGER UPDATE
+ * @{
+ * @brief constants defining the source triggering the update of the HRTIM_ADCxR register (transfer from preload to active register).
+ */
+#define LL_HRTIM_ADCTRIG_UPDATE_MASTER ((uint32_t)0x00000000U) /*!< HRTIM_ADCxR register update is triggered by the Master timer */
+#define LL_HRTIM_ADCTRIG_UPDATE_TIMER_A (HRTIM_CR1_ADC1USRC_0) /*!< HRTIM_ADCxR register update is triggered by the Timer A */
+#define LL_HRTIM_ADCTRIG_UPDATE_TIMER_B (HRTIM_CR1_ADC1USRC_1) /*!< HRTIM_ADCxR register update is triggered by the Timer B */
+#define LL_HRTIM_ADCTRIG_UPDATE_TIMER_C (HRTIM_CR1_ADC1USRC_1 | HRTIM_CR1_ADC1USRC_0) /*!< HRTIM_ADCxR register update is triggered by the Timer C */
+#define LL_HRTIM_ADCTRIG_UPDATE_TIMER_D (HRTIM_CR1_ADC1USRC_2) /*!< HRTIM_ADCxR register update is triggered by the Timer D */
+#define LL_HRTIM_ADCTRIG_UPDATE_TIMER_E (HRTIM_CR1_ADC1USRC_2 | HRTIM_CR1_ADC1USRC_0) /*!< HRTIM_ADCxR register update is triggered by the Timer E */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_ADCTRIG_SRC13 ADC TRIGGER 1/3 SOURCE
+ * @{
+ * @brief constants defining the events triggering ADC conversion for ADC Triggers 1 and 3.
+ */
+#define LL_HRTIM_ADCTRIG_SRC13_NONE ((uint32_t)0x00000000U) /*!< No ADC trigger event */
+#define LL_HRTIM_ADCTRIG_SRC13_MCMP1 HRTIM_ADC1R_AD1MC1 /*!< ADC Trigger on master compare 1 */
+#define LL_HRTIM_ADCTRIG_SRC13_MCMP2 HRTIM_ADC1R_AD1MC2 /*!< ADC Trigger on master compare 2 */
+#define LL_HRTIM_ADCTRIG_SRC13_MCMP3 HRTIM_ADC1R_AD1MC3 /*!< ADC Trigger on master compare 3 */
+#define LL_HRTIM_ADCTRIG_SRC13_MCMP4 HRTIM_ADC1R_AD1MC4 /*!< ADC Trigger on master compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC13_MPER HRTIM_ADC1R_AD1MPER /*!< ADC Trigger on master period */
+#define LL_HRTIM_ADCTRIG_SRC13_EEV1 HRTIM_ADC1R_AD1EEV1 /*!< ADC Trigger on external event 1 */
+#define LL_HRTIM_ADCTRIG_SRC13_EEV2 HRTIM_ADC1R_AD1EEV2 /*!< ADC Trigger on external event 2 */
+#define LL_HRTIM_ADCTRIG_SRC13_EEV3 HRTIM_ADC1R_AD1EEV3 /*!< ADC Trigger on external event 3 */
+#define LL_HRTIM_ADCTRIG_SRC13_EEV4 HRTIM_ADC1R_AD1EEV4 /*!< ADC Trigger on external event 4 */
+#define LL_HRTIM_ADCTRIG_SRC13_EEV5 HRTIM_ADC1R_AD1EEV5 /*!< ADC Trigger on external event 5 */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMACMP2 HRTIM_ADC1R_AD1TAC2 /*!< ADC Trigger on Timer A compare 2 */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMACMP3 HRTIM_ADC1R_AD1TAC3 /*!< ADC Trigger on Timer A compare 3 */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMACMP4 HRTIM_ADC1R_AD1TAC4 /*!< ADC Trigger on Timer A compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMAPER HRTIM_ADC1R_AD1TAPER /*!< ADC Trigger on Timer A period */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMARST HRTIM_ADC1R_AD1TARST /*!< ADC Trigger on Timer A reset */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP2 HRTIM_ADC1R_AD1TBC2 /*!< ADC Trigger on Timer B compare 2 */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3 HRTIM_ADC1R_AD1TBC3 /*!< ADC Trigger on Timer B compare 3 */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4 HRTIM_ADC1R_AD1TBC4 /*!< ADC Trigger on Timer B compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMBPER HRTIM_ADC1R_AD1TBPER /*!< ADC Trigger on Timer B period */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMBRST HRTIM_ADC1R_AD1TBRST /*!< ADC Trigger on Timer B reset */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP2 HRTIM_ADC1R_AD1TCC2 /*!< ADC Trigger on Timer C compare 2 */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3 HRTIM_ADC1R_AD1TCC3 /*!< ADC Trigger on Timer C compare 3 */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4 HRTIM_ADC1R_AD1TCC4 /*!< ADC Trigger on Timer C compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMCPER HRTIM_ADC1R_AD1TCPER /*!< ADC Trigger on Timer C period */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP2 HRTIM_ADC1R_AD1TDC2 /*!< ADC Trigger on Timer D compare 2 */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3 HRTIM_ADC1R_AD1TDC3 /*!< ADC Trigger on Timer D compare 3 */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4 HRTIM_ADC1R_AD1TDC4 /*!< ADC Trigger on Timer D compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMDPER HRTIM_ADC1R_AD1TDPER /*!< ADC Trigger on Timer D period */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMECMP2 HRTIM_ADC1R_AD1TEC2 /*!< ADC Trigger on Timer E compare 2 */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMECMP3 HRTIM_ADC1R_AD1TEC3 /*!< ADC Trigger on Timer E compare 3 */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMECMP4 HRTIM_ADC1R_AD1TEC4 /*!< ADC Trigger on Timer E compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMEPER HRTIM_ADC1R_AD1TEPER /*!< ADC Trigger on Timer E period */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_ADCTRIG_SRC24 ADC TRIGGER 2/4 SOURCE
+ * @{
+ * @brief constants defining the events triggering ADC conversion for ADC Triggers 2 and 4.
+ */
+#define LL_HRTIM_ADCTRIG_SRC24_NONE ((uint32_t)0x00000000U)/*!< No ADC trigger event */
+#define LL_HRTIM_ADCTRIG_SRC24_MCMP1 HRTIM_ADC2R_AD2MC1 /*!< ADC Trigger on master compare 1 */
+#define LL_HRTIM_ADCTRIG_SRC24_MCMP2 HRTIM_ADC2R_AD2MC2 /*!< ADC Trigger on master compare 2 */
+#define LL_HRTIM_ADCTRIG_SRC24_MCMP3 HRTIM_ADC2R_AD2MC3 /*!< ADC Trigger on master compare 3 */
+#define LL_HRTIM_ADCTRIG_SRC24_MCMP4 HRTIM_ADC2R_AD2MC4 /*!< ADC Trigger on master compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC24_MPER HRTIM_ADC2R_AD2MPER /*!< ADC Trigger on master period */
+#define LL_HRTIM_ADCTRIG_SRC24_EEV6 HRTIM_ADC2R_AD2EEV6 /*!< ADC Trigger on external event 6 */
+#define LL_HRTIM_ADCTRIG_SRC24_EEV7 HRTIM_ADC2R_AD2EEV7 /*!< ADC Trigger on external event 7 */
+#define LL_HRTIM_ADCTRIG_SRC24_EEV8 HRTIM_ADC2R_AD2EEV8 /*!< ADC Trigger on external event 8 */
+#define LL_HRTIM_ADCTRIG_SRC24_EEV9 HRTIM_ADC2R_AD2EEV9 /*!< ADC Trigger on external event 9 */
+#define LL_HRTIM_ADCTRIG_SRC24_EEV10 HRTIM_ADC2R_AD2EEV10 /*!< ADC Trigger on external event 10 */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMACMP2 HRTIM_ADC2R_AD2TAC2 /*!< ADC Trigger on Timer A compare 2 */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMACMP3 HRTIM_ADC2R_AD2TAC3 /*!< ADC Trigger on Timer A compare 3 */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMACMP4 HRTIM_ADC2R_AD2TAC4 /*!< ADC Trigger on Timer A compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMAPER HRTIM_ADC2R_AD2TAPER /*!< ADC Trigger on Timer A period */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2 HRTIM_ADC2R_AD2TBC2 /*!< ADC Trigger on Timer B compare 2 */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP3 HRTIM_ADC2R_AD2TBC3 /*!< ADC Trigger on Timer B compare 3 */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4 HRTIM_ADC2R_AD2TBC4 /*!< ADC Trigger on Timer B compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMBPER HRTIM_ADC2R_AD2TBPER /*!< ADC Trigger on Timer B period */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2 HRTIM_ADC2R_AD2TCC2 /*!< ADC Trigger on Timer C compare 2 */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP3 HRTIM_ADC2R_AD2TCC3 /*!< ADC Trigger on Timer C compare 3 */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4 HRTIM_ADC2R_AD2TCC4 /*!< ADC Trigger on Timer C compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMCPER HRTIM_ADC2R_AD2TCPER /*!< ADC Trigger on Timer C period */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMCRST HRTIM_ADC2R_AD2TCRST /*!< ADC Trigger on Timer C reset */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2 HRTIM_ADC2R_AD2TDC2 /*!< ADC Trigger on Timer D compare 2 */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP3 HRTIM_ADC2R_AD2TDC3 /*!< ADC Trigger on Timer D compare 3 */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4 HRTIM_ADC2R_AD2TDC4 /*!< ADC Trigger on Timer D compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMDPER HRTIM_ADC2R_AD2TDPER /*!< ADC Trigger on Timer D period */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMDRST HRTIM_ADC2R_AD2TDRST /*!< ADC Trigger on Timer D reset */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMECMP2 HRTIM_ADC2R_AD2TEC2 /*!< ADC Trigger on Timer E compare 2 */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMECMP3 HRTIM_ADC2R_AD2TEC3 /*!< ADC Trigger on Timer E compare 3 */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMECMP4 HRTIM_ADC2R_AD2TEC4 /*!< ADC Trigger on Timer E compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMERST HRTIM_ADC2R_AD2TERST /*!< ADC Trigger on Timer E reset */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_DLLCALIBRATION_MODE DLL CALIBRATION MODE
+ * @{
+ * @brief Constants defining the DLL calibration mode.
+ */
+#define LL_HRTIM_DLLCALIBRATION_MODE_SINGLESHOT ((uint32_t)0x00000000U)/*!<Calibration is perfomed only once */
+#define LL_HRTIM_DLLCALIBRATION_MODE_CONTINUOUS HRTIM_DLLCR_CALEN /*!<Calibration is performed periodically */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_CALIBRATIONRATE DLL CALIBRATION RATE
+ * @{
+ * @brief Constants defining the DLL calibration periods (in micro seconds).
+ */
+#define LL_HRTIM_DLLCALIBRATION_RATE_7300 ((uint32_t)0x00000000U) /*!< Periodic DLL calibration: T = 1048576 * tHRTIM (7.3 ms) */
+#define LL_HRTIM_DLLCALIBRATION_RATE_910 (HRTIM_DLLCR_CALRTE_0) /*!< Periodic DLL calibration: T = 131072 * tHRTIM (910 ms) */
+#define LL_HRTIM_DLLCALIBRATION_RATE_114 (HRTIM_DLLCR_CALRTE_1) /*!< Periodic DLL calibration: T = 16384 * tHRTIM (114 ms) */
+#define LL_HRTIM_DLLCALIBRATION_RATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) /*!< Periodic DLL calibration: T = 2048 * tHRTIM (14 ms) */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_PRESCALERRATIO PRESCALER RATIO
+ * @{
+ * @brief Constants defining timer high-resolution clock prescaler ratio.
+ */
+#define LL_HRTIM_PRESCALERRATIO_MUL32 ((uint32_t)0x00000000U) /*!< fHRCK: fHRTIM x 32 = 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz) */
+#define LL_HRTIM_PRESCALERRATIO_MUL16 ((uint32_t)0x00000001U) /*!< fHRCK: fHRTIM x 16 = 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz) */
+#define LL_HRTIM_PRESCALERRATIO_MUL8 ((uint32_t)0x00000002U) /*!< fHRCK: fHRTIM x 8 = 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz) */
+#define LL_HRTIM_PRESCALERRATIO_MUL4 ((uint32_t)0x00000003U) /*!< fHRCK: fHRTIM x 4 = 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz) */
+#define LL_HRTIM_PRESCALERRATIO_MUL2 ((uint32_t)0x00000004U) /*!< fHRCK: fHRTIM x 2 = 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz) */
+#define LL_HRTIM_PRESCALERRATIO_DIV1 ((uint32_t)0x00000005U) /*!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) */
+#define LL_HRTIM_PRESCALERRATIO_DIV2 ((uint32_t)0x00000006U) /*!< fHRCK: fHRTIM / 2 = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) */
+#define LL_HRTIM_PRESCALERRATIO_DIV4 ((uint32_t)0x00000007U) /*!< fHRCK: fHRTIM / 4 = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_MODE COUNTER MODE
+ * @{
+ * @brief Constants defining timer counter operating mode.
+ */
+#define LL_HRTIM_MODE_CONTINUOUS ((uint32_t)0x00000008U) /*!< The timer operates in continuous (free-running) mode */
+#define LL_HRTIM_MODE_SINGLESHOT ((uint32_t)0x00000000U) /*!< The timer operates in non retriggerable single-shot mode */
+#define LL_HRTIM_MODE_RETRIGGERABLE ((uint32_t)0x00000010U) /*!< The timer operates in retriggerable single-shot mode */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_DACTRIG DAC TRIGGER
+ * @{
+ * @brief Constants defining on which output the DAC synchronization event is sent.
+ */
+#define LL_HRTIM_DACTRIG_NONE ((uint32_t)0x00000000U) /*!< No DAC synchronization event generated */
+#define LL_HRTIM_DACTRIG_DACTRIGOUT_1 (HRTIM_MCR_DACSYNC_0) /*!< DAC synchronization event generated on DACTrigOut1 output upon timer update */
+#define LL_HRTIM_DACTRIG_DACTRIGOUT_2 (HRTIM_MCR_DACSYNC_1) /*!< DAC synchronization event generated on DACTrigOut2 output upon timer update */
+#define LL_HRTIM_DACTRIG_DACTRIGOUT_3 (HRTIM_MCR_DACSYNC_1 | HRTIM_MCR_DACSYNC_0) /*!< DAC synchronization event generated on DACTrigOut3 output upon timer update */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_UPDATETRIG UPDATE TRIGGER
+ * @{
+ * @brief Constants defining whether the registers update is done synchronously with any other timer or master update.
+ */
+#define LL_HRTIM_UPDATETRIG_NONE ((uint32_t)0x00000000U)/*!< Register update is disabled */
+#define LL_HRTIM_UPDATETRIG_MASTER HRTIM_TIMCR_MSTU /*!< Register update is triggered by the master timer update */
+#define LL_HRTIM_UPDATETRIG_TIMER_A HRTIM_TIMCR_TAU /*!< Register update is triggered by the timer A update */
+#define LL_HRTIM_UPDATETRIG_TIMER_B HRTIM_TIMCR_TBU /*!< Register update is triggered by the timer B update */
+#define LL_HRTIM_UPDATETRIG_TIMER_C HRTIM_TIMCR_TCU /*!< Register update is triggered by the timer C update*/
+#define LL_HRTIM_UPDATETRIG_TIMER_D HRTIM_TIMCR_TDU /*!< Register update is triggered by the timer D update */
+#define LL_HRTIM_UPDATETRIG_TIMER_E HRTIM_TIMCR_TEU /*!< Register update is triggered by the timer E update */
+#define LL_HRTIM_UPDATETRIG_REPETITION HRTIM_TIMCR_TREPU /*!< Register update is triggered when the counter rolls over and HRTIM_REPx = 0*/
+#define LL_HRTIM_UPDATETRIG_RESET HRTIM_TIMCR_TRSTU /*!< Register update is triggered by counter reset or roll-over to 0 after reaching the period value in continuous mode */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_UPDATEGATING UPDATE GATING
+ * @{
+ * @brief Constants defining how the update occurs relatively to the burst DMA transaction and the external update request on update enable inputs 1 to 3.
+ */
+#define LL_HRTIM_UPDATEGATING_INDEPENDENT ((uint32_t)0x00000000U) /*!< Update done independently from the DMA burst transfer completion */
+#define LL_HRTIM_UPDATEGATING_DMABURST (HRTIM_TIMCR_UPDGAT_0) /*!< Update done when the DMA burst transfer is completed */
+#define LL_HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1) /*!< Update done on timer roll-over following a DMA burst transfer completion*/
+#define LL_HRTIM_UPDATEGATING_UPDEN1 (HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 1 */
+#define LL_HRTIM_UPDATEGATING_UPDEN2 (HRTIM_TIMCR_UPDGAT_2) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 2 */
+#define LL_HRTIM_UPDATEGATING_UPDEN3 (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 3 */
+#define LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 1 */
+#define LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 2 */
+#define LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE (HRTIM_TIMCR_UPDGAT_3) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 3 */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_COMPAREMODE COMPARE MODE
+ * @{
+ * @brief Constants defining whether the compare register is behaving in regular mode (compare match issued as soon as counter equal compare) or in auto-delayed mode.
+ */
+#define LL_HRTIM_COMPAREMODE_REGULAR ((uint32_t)0x00000000U) /*!< standard compare mode */
+#define LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT (HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated only if a capture has occurred */
+#define LL_HRTIM_COMPAREMODE_DELAY_CMP1 (HRTIM_TIMCR_DELCMP2_1) /*!< Compare event generated if a capture has occurred or after a Compare 1 match (timeout if capture event is missing) */
+#define LL_HRTIM_COMPAREMODE_DELAY_CMP3 (HRTIM_TIMCR_DELCMP2_1 | HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated if a capture has occurred or after a Compare 3 match (timeout if capture event is missing) */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_RESETTRIG RESET TRIGGER
+ * @{
+ * @brief Constants defining the events that can be selected to trigger the reset of the timer counter.
+ */
+#define LL_HRTIM_RESETTRIG_NONE ((uint32_t)0x00000000U)/*!< No counter reset trigger */
+#define LL_HRTIM_RESETTRIG_UPDATE HRTIM_RSTR_UPDATE /*!< The timer counter is reset upon update event */
+#define LL_HRTIM_RESETTRIG_CMP2 HRTIM_RSTR_CMP2 /*!< The timer counter is reset upon Timer Compare 2 event */
+#define LL_HRTIM_RESETTRIG_CMP4 HRTIM_RSTR_CMP4 /*!< The timer counter is reset upon Timer Compare 4 event */
+#define LL_HRTIM_RESETTRIG_MASTER_PER HRTIM_RSTR_MSTPER /*!< The timer counter is reset upon master timer period event */
+#define LL_HRTIM_RESETTRIG_MASTER_CMP1 HRTIM_RSTR_MSTCMP1 /*!< The timer counter is reset upon master timer Compare 1 event */
+#define LL_HRTIM_RESETTRIG_MASTER_CMP2 HRTIM_RSTR_MSTCMP2 /*!< The timer counter is reset upon master timer Compare 2 event */
+#define LL_HRTIM_RESETTRIG_MASTER_CMP3 HRTIM_RSTR_MSTCMP3 /*!< The timer counter is reset upon master timer Compare 3 event */
+#define LL_HRTIM_RESETTRIG_MASTER_CMP4 HRTIM_RSTR_MSTCMP4 /*!< The timer counter is reset upon master timer Compare 4 event */
+#define LL_HRTIM_RESETTRIG_EEV_1 HRTIM_RSTR_EXTEVNT1 /*!< The timer counter is reset upon external event 1 */
+#define LL_HRTIM_RESETTRIG_EEV_2 HRTIM_RSTR_EXTEVNT2 /*!< The timer counter is reset upon external event 2 */
+#define LL_HRTIM_RESETTRIG_EEV_3 HRTIM_RSTR_EXTEVNT3 /*!< The timer counter is reset upon external event 3 */
+#define LL_HRTIM_RESETTRIG_EEV_4 HRTIM_RSTR_EXTEVNT4 /*!< The timer counter is reset upon external event 4 */
+#define LL_HRTIM_RESETTRIG_EEV_5 HRTIM_RSTR_EXTEVNT5 /*!< The timer counter is reset upon external event 5 */
+#define LL_HRTIM_RESETTRIG_EEV_6 HRTIM_RSTR_EXTEVNT6 /*!< The timer counter is reset upon external event 6 */
+#define LL_HRTIM_RESETTRIG_EEV_7 HRTIM_RSTR_EXTEVNT7 /*!< The timer counter is reset upon external event 7 */
+#define LL_HRTIM_RESETTRIG_EEV_8 HRTIM_RSTR_EXTEVNT8 /*!< The timer counter is reset upon external event 8 */
+#define LL_HRTIM_RESETTRIG_EEV_9 HRTIM_RSTR_EXTEVNT9 /*!< The timer counter is reset upon external event 9 */
+#define LL_HRTIM_RESETTRIG_EEV_10 HRTIM_RSTR_EXTEVNT10 /*!< The timer counter is reset upon external event 10 */
+#define LL_HRTIM_RESETTRIG_OTHER1_CMP1 HRTIM_RSTR_TIMBCMP1 /*!< The timer counter is reset upon other timer Compare 1 event */
+#define LL_HRTIM_RESETTRIG_OTHER1_CMP2 HRTIM_RSTR_TIMBCMP2 /*!< The timer counter is reset upon other timer Compare 2 event */
+#define LL_HRTIM_RESETTRIG_OTHER1_CMP4 HRTIM_RSTR_TIMBCMP4 /*!< The timer counter is reset upon other timer Compare 4 event */
+#define LL_HRTIM_RESETTRIG_OTHER2_CMP1 HRTIM_RSTR_TIMCCMP1 /*!< The timer counter is reset upon other timer Compare 1 event */
+#define LL_HRTIM_RESETTRIG_OTHER2_CMP2 HRTIM_RSTR_TIMCCMP2 /*!< The timer counter is reset upon other timer Compare 2 event */
+#define LL_HRTIM_RESETTRIG_OTHER2_CMP4 HRTIM_RSTR_TIMCCMP4 /*!< The timer counter is reset upon other timer Compare 4 event */
+#define LL_HRTIM_RESETTRIG_OTHER3_CMP1 HRTIM_RSTR_TIMDCMP1 /*!< The timer counter is reset upon other timer Compare 1 event */
+#define LL_HRTIM_RESETTRIG_OTHER3_CMP2 HRTIM_RSTR_TIMDCMP2 /*!< The timer counter is reset upon other timer Compare 2 event */
+#define LL_HRTIM_RESETTRIG_OTHER3_CMP4 HRTIM_RSTR_TIMDCMP4 /*!< The timer counter is reset upon other timer Compare 4 event */
+#define LL_HRTIM_RESETTRIG_OTHER4_CMP1 HRTIM_RSTR_TIMECMP1 /*!< The timer counter is reset upon other timer Compare 1 event */
+#define LL_HRTIM_RESETTRIG_OTHER4_CMP2 HRTIM_RSTR_TIMECMP2 /*!< The timer counter is reset upon other timer Compare 2 event */
+#define LL_HRTIM_RESETTRIG_OTHER4_CMP4 HRTIM_RSTR_TIMECMP4 /*!< The timer counter is reset upon other timer Compare 4 event */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_CAPTURETRIG CAPTURE TRIGGER
+ * @{
+ * @brief Constants defining the events that can be selected to trigger the capture of the timing unit counter.
+ */
+#define LL_HRTIM_CAPTURETRIG_NONE ((uint32_t)0x00000000U)/*!< Capture trigger is disabled */
+#define LL_HRTIM_CAPTURETRIG_UPDATE HRTIM_CPT1CR_UPDCPT /*!< The update event triggers the Capture */
+#define LL_HRTIM_CAPTURETRIG_EEV_1 HRTIM_CPT1CR_EXEV1CPT /*!< The External event 1 triggers the Capture */
+#define LL_HRTIM_CAPTURETRIG_EEV_2 HRTIM_CPT1CR_EXEV2CPT /*!< The External event 2 triggers the Capture */
+#define LL_HRTIM_CAPTURETRIG_EEV_3 HRTIM_CPT1CR_EXEV3CPT /*!< The External event 3 triggers the Capture */
+#define LL_HRTIM_CAPTURETRIG_EEV_4 HRTIM_CPT1CR_EXEV4CPT /*!< The External event 4 triggers the Capture */
+#define LL_HRTIM_CAPTURETRIG_EEV_5 HRTIM_CPT1CR_EXEV5CPT /*!< The External event 5 triggers the Capture */
+#define LL_HRTIM_CAPTURETRIG_EEV_6 HRTIM_CPT1CR_EXEV6CPT /*!< The External event 6 triggers the Capture */
+#define LL_HRTIM_CAPTURETRIG_EEV_7 HRTIM_CPT1CR_EXEV7CPT /*!< The External event 7 triggers the Capture */
+#define LL_HRTIM_CAPTURETRIG_EEV_8 HRTIM_CPT1CR_EXEV8CPT /*!< The External event 8 triggers the Capture */
+#define LL_HRTIM_CAPTURETRIG_EEV_9 HRTIM_CPT1CR_EXEV9CPT /*!< The External event 9 triggers the Capture */
+#define LL_HRTIM_CAPTURETRIG_EEV_10 HRTIM_CPT1CR_EXEV10CPT /*!< The External event 10 triggers the Capture */
+#define LL_HRTIM_CAPTURETRIG_TA1_SET HRTIM_CPT1CR_TA1SET /*!< Capture is triggered by TA1 output inactive to active transition */
+#define LL_HRTIM_CAPTURETRIG_TA1_RESET HRTIM_CPT1CR_TA1RST /*!< Capture is triggered by TA1 output active to inactive transition */
+#define LL_HRTIM_CAPTURETRIG_TIMA_CMP1 HRTIM_CPT1CR_TIMACMP1 /*!< Timer A Compare 1 triggers Capture */
+#define LL_HRTIM_CAPTURETRIG_TIMA_CMP2 HRTIM_CPT1CR_TIMACMP2 /*!< Timer A Compare 2 triggers Capture */
+#define LL_HRTIM_CAPTURETRIG_TB1_SET HRTIM_CPT1CR_TB1SET /*!< Capture is triggered by TB1 output inactive to active transition */
+#define LL_HRTIM_CAPTURETRIG_TB1_RESET HRTIM_CPT1CR_TB1RST /*!< Capture is triggered by TB1 output active to inactive transition */
+#define LL_HRTIM_CAPTURETRIG_TIMB_CMP1 HRTIM_CPT1CR_TIMBCMP1 /*!< Timer B Compare 1 triggers Capture */
+#define LL_HRTIM_CAPTURETRIG_TIMB_CMP2 HRTIM_CPT1CR_TIMBCMP2 /*!< Timer B Compare 2 triggers Capture */
+#define LL_HRTIM_CAPTURETRIG_TC1_SET HRTIM_CPT1CR_TC1SET /*!< Capture is triggered by TC1 output inactive to active transition */
+#define LL_HRTIM_CAPTURETRIG_TC1_RESET HRTIM_CPT1CR_TC1RST /*!< Capture is triggered by TC1 output active to inactive transition */
+#define LL_HRTIM_CAPTURETRIG_TIMC_CMP1 HRTIM_CPT1CR_TIMCCMP1 /*!< Timer C Compare 1 triggers Capture */
+#define LL_HRTIM_CAPTURETRIG_TIMC_CMP2 HRTIM_CPT1CR_TIMCCMP2 /*!< Timer C Compare 2 triggers Capture */
+#define LL_HRTIM_CAPTURETRIG_TD1_SET HRTIM_CPT1CR_TD1SET /*!< Capture is triggered by TD1 output inactive to active transition */
+#define LL_HRTIM_CAPTURETRIG_TD1_RESET HRTIM_CPT1CR_TD1RST /*!< Capture is triggered by TD1 output active to inactive transition */
+#define LL_HRTIM_CAPTURETRIG_TIMD_CMP1 HRTIM_CPT1CR_TIMDCMP1 /*!< Timer D Compare 1 triggers Capture */
+#define LL_HRTIM_CAPTURETRIG_TIMD_CMP2 HRTIM_CPT1CR_TIMDCMP2 /*!< Timer D Compare 2 triggers Capture */
+#define LL_HRTIM_CAPTURETRIG_TE1_SET HRTIM_CPT1CR_TE1SET /*!< Capture is triggered by TE1 output inactive to active transition */
+#define LL_HRTIM_CAPTURETRIG_TE1_RESET HRTIM_CPT1CR_TE1RST /*!< Capture is triggered by TE1 output active to inactive transition */
+#define LL_HRTIM_CAPTURETRIG_TIME_CMP1 HRTIM_CPT1CR_TIMECMP1 /*!< Timer E Compare 1 triggers Capture */
+#define LL_HRTIM_CAPTURETRIG_TIME_CMP2 HRTIM_CPT1CR_TIMECMP2 /*!< Timer E Compare 2 triggers Capture */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_DLYPRT DELAYED PROTECTION (DLYPRT) MODE
+ * @{
+ * @brief Constants defining all possible delayed protection modes for a timer (also define the source and outputs on which the delayed protection schemes are applied).
+ */
+#define LL_HRTIM_DLYPRT_DELAYOUT1_EEV6 ((uint32_t)0x00000000U) /*!< Timers A, B, C: Output 1 delayed Idle on external Event 6 */
+#define LL_HRTIM_DLYPRT_DELAYOUT2_EEV6 (HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 6 */
+#define LL_HRTIM_DLYPRT_DELAYBOTH_EEV6 (HRTIM_OUTR_DLYPRT_1) /*!< Timers A, B, C: Output 1 and output 2 delayed Idle on external Event 6 */
+#define LL_HRTIM_DLYPRT_BALANCED_EEV6 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Balanced Idle on external Event 6 */
+#define LL_HRTIM_DLYPRT_DELAYOUT1_EEV7 (HRTIM_OUTR_DLYPRT_2) /*!< Timers A, B, C: Output 1 delayed Idle on external Event 7 */
+#define LL_HRTIM_DLYPRT_DELAYOUT2_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 7 */
+#define LL_HRTIM_DLYPRT_DELAYBOTH_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1) /*!< Timers A, B, C: Output 1 and output2 delayed Idle on external Event 7 */
+#define LL_HRTIM_DLYPRT_BALANCED_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Balanced Idle on external Event 7 */
+
+#define LL_HRTIM_DLYPRT_DELAYOUT1_EEV8 ((uint32_t)0x00000000U) /*!< Timers D, E: Output 1 delayed Idle on external Event 8 */
+#define LL_HRTIM_DLYPRT_DELAYOUT2_EEV8 (HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Output 2 delayed Idle on external Event 8 */
+#define LL_HRTIM_DLYPRT_DELAYBOTH_EEV8 (HRTIM_OUTR_DLYPRT_1) /*!< Timers D, E: Output 1 and output 2 delayed Idle on external Event 8 */
+#define LL_HRTIM_DLYPRT_BALANCED_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Balanced Idle on external Event 8 */
+#define LL_HRTIM_DLYPRT_DELAYOUT1_EEV9 (HRTIM_OUTR_DLYPRT_2) /*!< Timers D, E: Output 1 delayed Idle on external Event 9 */
+#define LL_HRTIM_DLYPRT_DELAYOUT2_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Output 2 delayed Idle on external Event 9 */
+#define LL_HRTIM_DLYPRT_DELAYBOTH_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1) /*!< Timers D, E: Output 1 and output2 delayed Idle on external Event 9 */
+#define LL_HRTIM_DLYPRT_BALANCED_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Balanced Idle on external Event 9 */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_BURSTMODE BURST MODE
+ * @{
+ * @brief Constants defining how the timer behaves during a burst mode operation.
+ */
+#define LL_HRTIM_BURSTMODE_MAINTAINCLOCK (uint32_t)0x000000 /*!< Timer counter clock is maintained and the timer operates normally */
+#define LL_HRTIM_BURSTMODE_RESETCOUNTER (HRTIM_BMCR_MTBM) /*!< Timer counter clock is stopped and the counter is reset */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_BURSTDMA BURST DMA
+ * @{
+ * @brief Constants defining the registers that can be written during a burst DMA operation.
+ */
+#define LL_HRTIM_BURSTDMA_NONE ((uint32_t)0x00000000U) /*!< No register is updated by Burst DMA accesses */
+
+#define LL_HRTIM_BURSTDMA_MCR (HRTIM_BDMUPR_MCR) /*!< MCR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_MICR (HRTIM_BDMUPR_MICR) /*!< MICR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_MDIER (HRTIM_BDMUPR_MDIER) /*!< MDIER register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_MCNT (HRTIM_BDMUPR_MCNT) /*!< MCNTR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_MPER (HRTIM_BDMUPR_MPER) /*!< MPER register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_MREP (HRTIM_BDMUPR_MREP) /*!< MREPR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_MCMP1 (HRTIM_BDMUPR_MCMP1) /*!< MCMP1R register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_MCMP2 (HRTIM_BDMUPR_MCMP2) /*!< MCMP2R register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_MCMP3 (HRTIM_BDMUPR_MCMP3) /*!< MCMP3R register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_MCMP4 (HRTIM_BDMUPR_MCMP4) /*!< MCMP4R register is updated by Burst DMA accesses */
+
+#define LL_HRTIM_BURSTDMA_TIMMCR (HRTIM_BDTUPR_TIMCR) /*!< TIMxCR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMICR (HRTIM_BDTUPR_TIMICR) /*!< TIMxICR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMDIER (HRTIM_BDTUPR_TIMDIER) /*!< TIMxDIER register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMCNT (HRTIM_BDTUPR_TIMCNT) /*!< CNTxCR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMPER (HRTIM_BDTUPR_TIMPER) /*!< PERxR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMREP (HRTIM_BDTUPR_TIMREP) /*!< REPxR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMCMP1 (HRTIM_BDTUPR_TIMCMP1) /*!< CMP1xR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMCMP2 (HRTIM_BDTUPR_TIMCMP2) /*!< CMP2xR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMCMP3 (HRTIM_BDTUPR_TIMCMP3) /*!< CMP3xR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMCMP4 (HRTIM_BDTUPR_TIMCMP4) /*!< CMP4xR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMDTR (HRTIM_BDTUPR_TIMDTR) /*!< DTxR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMSET1R (HRTIM_BDTUPR_TIMSET1R) /*!< SET1R register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMRST1R (HRTIM_BDTUPR_TIMRST1R) /*!< RST1R register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMSET2R (HRTIM_BDTUPR_TIMSET2R) /*!< SET2R register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMRST2R (HRTIM_BDTUPR_TIMRST2R) /*!< RST1R register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMEEFR1 (HRTIM_BDTUPR_TIMEEFR1) /*!< EEFxR1 register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMEEFR2 (HRTIM_BDTUPR_TIMEEFR2) /*!< EEFxR2 register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMRSTR (HRTIM_BDTUPR_TIMRSTR) /*!< RSTxR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMCHPR (HRTIM_BDTUPR_TIMCHPR) /*!< CHPxR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMOUTR (HRTIM_BDTUPR_TIMOUTR) /*!< OUTxR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMFLTR (HRTIM_BDTUPR_TIMFLTR) /*!< FLTxR register is updated by Burst DMA accesses */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_CPPSTAT CURRENT PUSH-PULL STATUS
+ * @{
+ * @brief Constants defining on which output the signal is currently applied in push-pull mode.
+ */
+#define LL_HRTIM_CPPSTAT_OUTPUT1 ((uint32_t) 0x00000000U) /*!< Signal applied on output 1 and output 2 forced inactive */
+#define LL_HRTIM_CPPSTAT_OUTPUT2 (HRTIM_TIMISR_CPPSTAT) /*!< Signal applied on output 2 and output 1 forced inactive */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_IPPSTAT IDLE PUSH-PULL STATUS
+ * @{
+ * @brief Constants defining on which output the signal was applied, in push-pull mode balanced fault mode or delayed idle mode, when the protection was triggered.
+ */
+#define LL_HRTIM_IPPSTAT_OUTPUT1 ((uint32_t) 0x00000000U) /*!< Protection occurred when the output 1 was active and output 2 forced inactive */
+#define LL_HRTIM_IPPSTAT_OUTPUT2 (HRTIM_TIMISR_IPPSTAT) /*!< Protection occurred when the output 2 was active and output 1 forced inactive */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_TIM_EEFLTR TIMER EXTERNAL EVENT FILTER
+ * @{
+ * @brief Constants defining the event filtering applied to external events by a timer.
+ */
+#define LL_HRTIM_EEFLTR_NONE ((uint32_t)0x00000000U)
+#define LL_HRTIM_EEFLTR_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 1 */
+#define LL_HRTIM_EEFLTR_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from counter reset/roll-over to Compare 2 */
+#define LL_HRTIM_EEFLTR_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 3 */
+#define LL_HRTIM_EEFLTR_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from counter reset/roll-over to Compare 4 */
+#define LL_HRTIM_EEFLTR_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
+#define LL_HRTIM_EEFLTR_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
+#define LL_HRTIM_EEFLTR_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
+#define LL_HRTIM_EEFLTR_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
+#define LL_HRTIM_EEFLTR_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
+#define LL_HRTIM_EEFLTR_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
+#define LL_HRTIM_EEFLTR_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
+#define LL_HRTIM_EEFLTR_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
+#define LL_HRTIM_EEFLTR_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from counter reset/roll-over to Compare 2 */
+#define LL_HRTIM_EEFLTR_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Windowing from counter reset/roll-over to Compare 3 */
+#define LL_HRTIM_EEFLTR_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from another timing unit: TIMWIN source */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_TIM_LATCHSTATUS TIMER EXTERNAL EVENT LATCH STATUS
+ * @{
+ * @brief Constants defining whether or not the external event is memorized (latched) and generated as soon as the blanking period is completed or the window ends.
+ */
+#define LL_HRTIM_EELATCH_DISABLED ((uint32_t)0x00000000U) /*!< Event is ignored if it happens during a blank, or passed through during a window */
+#define LL_HRTIM_EELATCH_ENABLED HRTIM_EEFR1_EE1LTCH /*!< Event is latched and delayed till the end of the blanking or windowing period */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_DT_PRESCALER DEADTIME PRESCALER
+ * @{
+ * @brief Constants defining division ratio between the timer clock frequency (fHRTIM) and the deadtime generator clock (fDTG).
+ */
+#define LL_HRTIM_DT_PRESCALER_MUL8 ((uint32_t)0x00000000U) /*!< fDTG = fHRTIM * 8 */
+#define LL_HRTIM_DT_PRESCALER_MUL4 (HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM * 4 */
+#define LL_HRTIM_DT_PRESCALER_MUL2 (HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM * 2 */
+#define LL_HRTIM_DT_PRESCALER_DIV1 (HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM */
+#define LL_HRTIM_DT_PRESCALER_DIV2 (HRTIM_DTR_DTPRSC_2) /*!< fDTG = fHRTIM / 2 */
+#define LL_HRTIM_DT_PRESCALER_DIV4 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 4 */
+#define LL_HRTIM_DT_PRESCALER_DIV8 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM / 8 */
+#define LL_HRTIM_DT_PRESCALER_DIV16 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 16 */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_DT_RISING_SIGN DEADTIME RISING SIGN
+ * @{
+ * @brief Constants defining whether the deadtime is positive or negative (overlapping signal) on rising edge.
+ */
+#define LL_HRTIM_DT_RISING_POSITIVE ((uint32_t)0x00000000U) /*!< Positive deadtime on rising edge */
+#define LL_HRTIM_DT_RISING_NEGATIVE (HRTIM_DTR_SDTR) /*!< Negative deadtime on rising edge */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_DT_FALLING_SIGN DEADTIME FALLING SIGN
+ * @{
+ * @brief Constants defining whether the deadtime is positive or negative (overlapping signal) on falling edge.
+ */
+#define LL_HRTIM_DT_FALLING_POSITIVE ((uint32_t)0x00000000U) /*!< Positive deadtime on falling edge */
+#define LL_HRTIM_DT_FALLING_NEGATIVE (HRTIM_DTR_SDTF) /*!< Negative deadtime on falling edge */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_CHP_PRESCALER CHOPPER MODE PRESCALER
+ * @{
+ * @brief Constants defining the frequency of the generated high frequency carrier (fCHPFRQ).
+ */
+#define LL_HRTIM_CHP_PRESCALER_DIV16 ((uint32_t)0x00000000U) /*!< fCHPFRQ = fHRTIM / 16 */
+#define LL_HRTIM_CHP_PRESCALER_DIV32 (HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 32 */
+#define LL_HRTIM_CHP_PRESCALER_DIV48 (HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 48 */
+#define LL_HRTIM_CHP_PRESCALER_DIV64 (HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 64 */
+#define LL_HRTIM_CHP_PRESCALER_DIV80 (HRTIM_CHPR_CARFRQ_2) /*!< fCHPFRQ = fHRTIM / 80 */
+#define LL_HRTIM_CHP_PRESCALER_DIV96 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 96 */
+#define LL_HRTIM_CHP_PRESCALER_DIV112 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 112 */
+#define LL_HRTIM_CHP_PRESCALER_DIV128 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 128 */
+#define LL_HRTIM_CHP_PRESCALER_DIV144 (HRTIM_CHPR_CARFRQ_3) /*!< fCHPFRQ = fHRTIM / 144 */
+#define LL_HRTIM_CHP_PRESCALER_DIV160 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 160 */
+#define LL_HRTIM_CHP_PRESCALER_DIV176 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 176 */
+#define LL_HRTIM_CHP_PRESCALER_DIV192 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 192 */
+#define LL_HRTIM_CHP_PRESCALER_DIV208 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2) /*!< fCHPFRQ = fHRTIM / 208 */
+#define LL_HRTIM_CHP_PRESCALER_DIV224 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 224 */
+#define LL_HRTIM_CHP_PRESCALER_DIV240 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 240 */
+#define LL_HRTIM_CHP_PRESCALER_DIV256 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 256 */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_CHP_DUTYCYCLE CHOPPER MODE DUTY CYCLE
+ * @{
+ * @brief Constants defining the duty cycle of the generated high frequency carrier. Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8).
+ */
+#define LL_HRTIM_CHP_DUTYCYCLE_0 ((uint32_t)0x00000000U) /*!< Only 1st pulse is present */
+#define LL_HRTIM_CHP_DUTYCYCLE_125 (HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 12.5 % */
+#define LL_HRTIM_CHP_DUTYCYCLE_250 (HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 25 % */
+#define LL_HRTIM_CHP_DUTYCYCLE_375 (HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 37.5 % */
+#define LL_HRTIM_CHP_DUTYCYCLE_500 (HRTIM_CHPR_CARDTY_2) /*!< Duty cycle of the carrier signal is 50 % */
+#define LL_HRTIM_CHP_DUTYCYCLE_625 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 62.5 % */
+#define LL_HRTIM_CHP_DUTYCYCLE_750 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 75 % */
+#define LL_HRTIM_CHP_DUTYCYCLE_875 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 87.5 % */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_CHP_PULSEWIDTH CHOPPER MODE PULSE WIDTH
+ * @{
+ * @brief Constants defining the pulse width of the first pulse of the generated high frequency carrier.
+ */
+#define LL_HRTIM_CHP_PULSEWIDTH_16 ((uint32_t)0x00000000U) /*!< tSTPW = tHRTIM x 16 */
+#define LL_HRTIM_CHP_PULSEWIDTH_32 (HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 32 */
+#define LL_HRTIM_CHP_PULSEWIDTH_48 (HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 48 */
+#define LL_HRTIM_CHP_PULSEWIDTH_64 (HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 64 */
+#define LL_HRTIM_CHP_PULSEWIDTH_80 (HRTIM_CHPR_STRPW_2) /*!< tSTPW = tHRTIM x 80 */
+#define LL_HRTIM_CHP_PULSEWIDTH_96 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 96 */
+#define LL_HRTIM_CHP_PULSEWIDTH_112 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 112 */
+#define LL_HRTIM_CHP_PULSEWIDTH_128 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 128 */
+#define LL_HRTIM_CHP_PULSEWIDTH_144 (HRTIM_CHPR_STRPW_3) /*!< tSTPW = tHRTIM x 144 */
+#define LL_HRTIM_CHP_PULSEWIDTH_160 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 160 */
+#define LL_HRTIM_CHP_PULSEWIDTH_176 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 176 */
+#define LL_HRTIM_CHP_PULSEWIDTH_192 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 192 */
+#define LL_HRTIM_CHP_PULSEWIDTH_208 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2) /*!< tSTPW = tHRTIM x 208 */
+#define LL_HRTIM_CHP_PULSEWIDTH_224 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 224 */
+#define LL_HRTIM_CHP_PULSEWIDTH_240 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 240 */
+#define LL_HRTIM_CHP_PULSEWIDTH_256 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 256 */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_CROSSBAR_INPUT CROSSBAR INPUT
+ * @{
+ * @brief Constants defining the events that can be selected to configure the set/reset crossbar of a timer output.
+ */
+#define LL_HRTIM_CROSSBAR_NONE ((uint32_t)0x00000000U) /*!< Reset the output set crossbar */
+#define LL_HRTIM_CROSSBAR_RESYNC (HRTIM_SET1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces an output level transision */
+#define LL_HRTIM_CROSSBAR_TIMPER (HRTIM_SET1R_PER) /*!< Timer period event forces an output level transision */
+#define LL_HRTIM_CROSSBAR_TIMCMP1 (HRTIM_SET1R_CMP1) /*!< Timer compare 1 event forces an output level transision */
+#define LL_HRTIM_CROSSBAR_TIMCMP2 (HRTIM_SET1R_CMP2) /*!< Timer compare 2 event forces an output level transision */
+#define LL_HRTIM_CROSSBAR_TIMCMP3 (HRTIM_SET1R_CMP3) /*!< Timer compare 3 event forces an output level transision */
+#define LL_HRTIM_CROSSBAR_TIMCMP4 (HRTIM_SET1R_CMP4) /*!< Timer compare 4 event forces an output level transision */
+#define LL_HRTIM_CROSSBAR_MASTERPER (HRTIM_SET1R_MSTPER) /*!< The master timer period event forces an output level transision */
+#define LL_HRTIM_CROSSBAR_MASTERCMP1 (HRTIM_SET1R_MSTCMP1) /*!< Master Timer compare 1 event forces an output level transision */
+#define LL_HRTIM_CROSSBAR_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) /*!< Master Timer compare 2 event forces an output level transision */
+#define LL_HRTIM_CROSSBAR_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) /*!< Master Timer compare 3 event forces an output level transision */
+#define LL_HRTIM_CROSSBAR_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) /*!< Master Timer compare 4 event forces an output level transision */
+#define LL_HRTIM_CROSSBAR_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces an output level transision */
+#define LL_HRTIM_CROSSBAR_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces an output level transision */
+#define LL_HRTIM_CROSSBAR_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces an output level transision */
+#define LL_HRTIM_CROSSBAR_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces an output level transision */
+#define LL_HRTIM_CROSSBAR_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces an output level transision */
+#define LL_HRTIM_CROSSBAR_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces an output level transision */
+#define LL_HRTIM_CROSSBAR_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces an output level transision */
+#define LL_HRTIM_CROSSBAR_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces an output level transision */
+#define LL_HRTIM_CROSSBAR_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces an output level transision */
+#define LL_HRTIM_CROSSBAR_EEV_1 (HRTIM_SET1R_EXTVNT1) /*!< External event 1 forces an output level transision */
+#define LL_HRTIM_CROSSBAR_EEV_2 (HRTIM_SET1R_EXTVNT2) /*!< External event 2 forces an output level transision */
+#define LL_HRTIM_CROSSBAR_EEV_3 (HRTIM_SET1R_EXTVNT3) /*!< External event 3 forces an output level transision */
+#define LL_HRTIM_CROSSBAR_EEV_4 (HRTIM_SET1R_EXTVNT4) /*!< External event 4 forces an output level transision */
+#define LL_HRTIM_CROSSBAR_EEV_5 (HRTIM_SET1R_EXTVNT5) /*!< External event 5 forces an output level transision */
+#define LL_HRTIM_CROSSBAR_EEV_6 (HRTIM_SET1R_EXTVNT6) /*!< External event 6 forces an output level transision */
+#define LL_HRTIM_CROSSBAR_EEV_7 (HRTIM_SET1R_EXTVNT7) /*!< External event 7 forces an output level transision */
+#define LL_HRTIM_CROSSBAR_EEV_8 (HRTIM_SET1R_EXTVNT8) /*!< External event 8 forces an output level transision */
+#define LL_HRTIM_CROSSBAR_EEV_9 (HRTIM_SET1R_EXTVNT9) /*!< External event 9 forces an output level transision */
+#define LL_HRTIM_CROSSBAR_EEV_10 (HRTIM_SET1R_EXTVNT10) /*!< External event 10 forces an output level transision */
+#define LL_HRTIM_CROSSBAR_UPDATE (HRTIM_SET1R_UPDATE) /*!< Timer register update event forces an output level transision */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_OUT_POLARITY OUPUT_POLARITY
+ * @{
+ * @brief Constants defining the polarity of a timer output.
+ */
+#define LL_HRTIM_OUT_POSITIVE_POLARITY ((uint32_t)0x00000000U) /*!< Output is acitve HIGH */
+#define LL_HRTIM_OUT_NEGATIVE_POLARITY (HRTIM_OUTR_POL1) /*!< Output is active LOW */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_OUT_IDLEMODE OUTPUT IDLE MODE
+ * @{
+ * @brief Constants defining whether or not the timer output transition to its IDLE state when burst mode is entered.
+ */
+#define LL_HRTIM_OUT_NO_IDLE ((uint32_t)0x00000000U)/*!< The output is not affected by the burst mode operation */
+#define LL_HRTIM_OUT_IDLE_WHEN_BURST (HRTIM_OUTR_IDLM1) /*!< The output is in idle state when requested by the burst mode controller */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_OUT_IDLELEVEL OUTPUT IDLE LEVEL
+ * @{
+ * @brief Constants defining the output level when output is in IDLE state
+ */
+#define LL_HRTIM_OUT_IDLELEVEL_INACTIVE ((uint32_t)0x00000000U)/*!< Output at inactive level when in IDLE state */
+#define LL_HRTIM_OUT_IDLELEVEL_ACTIVE (HRTIM_OUTR_IDLES1) /*!< Output at active level when in IDLE state */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_OUT_FAULTSTATE OUTPUT FAULT STATE
+ * @{
+ * @brief Constants defining the output level when output is in FAULT state.
+ */
+#define LL_HRTIM_OUT_FAULTSTATE_NO_ACTION ((uint32_t)0x00000000U) /*!< The output is not affected by the fault input */
+#define LL_HRTIM_OUT_FAULTSTATE_ACTIVE (HRTIM_OUTR_FAULT1_0) /*!< Output at active level when in FAULT state */
+#define LL_HRTIM_OUT_FAULTSTATE_INACTIVE (HRTIM_OUTR_FAULT1_1) /*!< Output at inactive level when in FAULT state */
+#define LL_HRTIM_OUT_FAULTSTATE_HIGHZ (HRTIM_OUTR_FAULT1_1 | HRTIM_OUTR_FAULT1_0) /*!< Output is tri-stated when in FAULT state */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_OUT_CHOPPERMODE OUTPUT CHOPPER MODE
+ * @{
+ * @brief Constants defining whether or not chopper mode is enabled for a timer output.
+ */
+#define LL_HRTIM_OUT_CHOPPERMODE_DISABLED ((uint32_t)0x00000000U) /*!< Output signal is not altered */
+#define LL_HRTIM_OUT_CHOPPERMODE_ENABLED (HRTIM_OUTR_CHP1) /*!< Output signal is chopped by a carrier signal */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_OUT_BM_ENTRYMODE OUTPUT BURST MODE ENTRY MODE
+ * @{
+ * @brief Constants defining the idle state entry mode during a burst mode operation. It is possible to delay the burst mode entry and force the output to an inactive state
+during a programmable period before the output takes its idle state.
+ */
+#define LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR ((uint32_t)0x00000000U)/*!< The programmed Idle state is applied immediately to the Output */
+#define LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED (HRTIM_OUTR_DIDL1) /*!< Deadtime is inserted on output before entering the idle mode */
+/**
+ * @}
+ */
+/** @defgroup HRTIM_EC_OUT_LEVEL OUTPUT LEVEL
+ * @{
+ * @brief Constants defining the level of a timer output.
+ */
+#define LL_HRTIM_OUT_LEVEL_INACTIVE ((uint32_t)0x00000000U)/*!< Corresponds to a logic level 0 for a positive polarity (High) and to a logic level 1 for a negative polarity (Low) */
+#define LL_HRTIM_OUT_LEVEL_ACTIVE ((uint32_t)0x00000001) /*!< Corresponds to a logic level 1 for a positive polarity (High) and to a logic level 0 for a negative polarity (Low) */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_EE_SRC EXTERNAL EVENT SOURCE
+ * @{
+ * @brief Constants defining available sources associated to external events.
+ */
+#define LL_HRTIM_EE_SRC_1 ((uint32_t)0x00000000U) /*!< External event source 1 (EExSrc1)*/
+#define LL_HRTIM_EE_SRC_2 (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 (EExSrc2) */
+#define LL_HRTIM_EE_SRC_3 (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 (EExSrc3) */
+#define LL_HRTIM_EE_SRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 (EExSrc4) */
+/**
+ * @}
+ */
+/** @defgroup HRTIM_EC_EE_POLARITY EXTERNAL EVENT POLARITY
+ * @{
+ * @brief Constants defining the polarity of an external event.
+ */
+#define LL_HRTIM_EE_POLARITY_HIGH ((uint32_t)0x00000000U) /*!< External event is active high */
+#define LL_HRTIM_EE_POLARITY_LOW (HRTIM_EECR1_EE1POL) /*!< External event is active low */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_EE_SENSITIVITY EXTERNAL EVENT SENSITIVITY
+ * @{
+ * @brief Constants defining the sensitivity (level-sensitive or edge-sensitive) of an external event.
+ */
+#define LL_HRTIM_EE_SENSITIVITY_LEVEL ((uint32_t)0x00000000U) /*!< External event is active on level */
+#define LL_HRTIM_EE_SENSITIVITY_RISINGEDGE (HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising edge */
+#define LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE (HRTIM_EECR1_EE1SNS_1) /*!< External event is active on Falling edge */
+#define LL_HRTIM_EE_SENSITIVITY_BOTHEDGES (HRTIM_EECR1_EE1SNS_1 | HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising and Falling edges */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_EE_FASTMODE EXTERNAL EVENT FAST MODE
+ * @{
+ * @brief Constants defining whether or not an external event is programmed in fast mode.
+ */
+#define LL_HRTIM_EE_FASTMODE_DISABLE ((uint32_t)0x00000000U) /*!< External Event is re-synchronized by the HRTIM logic before acting on outputs */
+#define LL_HRTIM_EE_FASTMODE_ENABLE (HRTIM_EECR1_EE1FAST) /*!< External Event is acting asynchronously on outputs (low latency mode) */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_EE_FILTER EXTERNAL EVENT DIGITAL FILTER
+ * @{
+ * @brief Constants defining the frequency used to sample an external event input (fSAMPLING) and the length (N) of the digital filter applied.
+ */
+#define LL_HRTIM_EE_FILTER_NONE ((uint32_t)0x00000000U) /*!< Filter disabled */
+#define LL_HRTIM_EE_FILTER_1 (HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fHRTIM, N=2 */
+#define LL_HRTIM_EE_FILTER_2 (HRTIM_EECR3_EE6F_1) /*!< fSAMPLING = fHRTIM, N=4 */
+#define LL_HRTIM_EE_FILTER_3 (HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fHRTIM, N=8 */
+#define LL_HRTIM_EE_FILTER_4 (HRTIM_EECR3_EE6F_2) /*!< fSAMPLING = fEEVS/2, N=6 */
+#define LL_HRTIM_EE_FILTER_5 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/2, N=8 */
+#define LL_HRTIM_EE_FILTER_6 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING = fEEVS/4, N=6 */
+#define LL_HRTIM_EE_FILTER_7 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/4, N=8 */
+#define LL_HRTIM_EE_FILTER_8 (HRTIM_EECR3_EE6F_3) /*!< fSAMPLING = fEEVS/8, N=6 */
+#define LL_HRTIM_EE_FILTER_9 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/8, N=8 */
+#define LL_HRTIM_EE_FILTER_10 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING = fEEVS/16, N=5 */
+#define LL_HRTIM_EE_FILTER_11 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/16, N=6 */
+#define LL_HRTIM_EE_FILTER_12 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2) /*!< fSAMPLING = fEEVS/16, N=8 */
+#define LL_HRTIM_EE_FILTER_13 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/32, N=5 */
+#define LL_HRTIM_EE_FILTER_14 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING = fEEVS/32, N=6 */
+#define LL_HRTIM_EE_FILTER_15 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/32, N=8 */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_EE_PRESCALER EXTERNAL EVENT PRESCALER
+ * @{
+ * @brief Constants defining division ratio between the timer clock frequency (fHRTIM) and the external event signal sampling clock (fEEVS) used by the digital filters.
+ */
+#define LL_HRTIM_EE_PRESCALER_DIV1 ((uint32_t)0x00000000U) /*!< fEEVS = fHRTIM */
+#define LL_HRTIM_EE_PRESCALER_DIV2 (HRTIM_EECR3_EEVSD_0) /*!< fEEVS = fHRTIM / 2 */
+#define LL_HRTIM_EE_PRESCALER_DIV4 (HRTIM_EECR3_EEVSD_1) /*!< fEEVS = fHRTIM / 4 */
+#define LL_HRTIM_EE_PRESCALER_DIV8 (HRTIM_EECR3_EEVSD_1 | HRTIM_EECR3_EEVSD_0) /*!< fEEVS = fHRTIM / 8 */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_FLT_SRC FAULT SOURCE
+ * @{
+ * @brief Constants defining whether a faults is be triggered by any external or internal fault source.
+ */
+#define LL_HRTIM_FLT_SRC_DIGITALINPUT ((uint32_t)0x00000000U) /*!< Fault input is FLT input pin */
+#define LL_HRTIM_FLT_SRC_INTERNAL (HRTIM_FLTINR1_FLT1SRC) /*!< Fault input is FLT_Int signal (e.g. internal comparator) */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_FLT_POLARITY FAULT POLARITY
+ * @{
+ * @brief Constants defining the polarity of a fault event.
+ */
+#define LL_HRTIM_FLT_POLARITY_LOW ((uint32_t)0x00000000U) /*!< Fault input is active low */
+#define LL_HRTIM_FLT_POLARITY_HIGH (HRTIM_FLTINR1_FLT1P) /*!< Fault input is active high */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_FLT_FILTER FAULT DIGITAL FILTER
+ * @{
+ * @brief Constants defining the frequency used to sample the fault input (fSAMPLING) and the length (N) of the digital filter applied.
+ */
+#define LL_HRTIM_FLT_FILTER_NONE ((uint32_t)0x00000000U) /*!< Filter disabled */
+#define LL_HRTIM_FLT_FILTER_1 (HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=2 */
+#define LL_HRTIM_FLT_FILTER_2 (HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fHRTIM, N=4 */
+#define LL_HRTIM_FLT_FILTER_3 (HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=8 */
+#define LL_HRTIM_FLT_FILTER_4 (HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/2, N=6 */
+#define LL_HRTIM_FLT_FILTER_5 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/2, N=8 */
+#define LL_HRTIM_FLT_FILTER_6 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/4, N=6 */
+#define LL_HRTIM_FLT_FILTER_7 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/4, N=8 */
+#define LL_HRTIM_FLT_FILTER_8 (HRTIM_FLTINR1_FLT1F_3) /*!< fSAMPLING= fFLTS/8, N=6 */
+#define LL_HRTIM_FLT_FILTER_9 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/8, N=8 */
+#define LL_HRTIM_FLT_FILTER_10 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/16, N=5 */
+#define LL_HRTIM_FLT_FILTER_11 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/16, N=6 */
+#define LL_HRTIM_FLT_FILTER_12 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/16, N=8 */
+#define LL_HRTIM_FLT_FILTER_13 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32, N=5 */
+#define LL_HRTIM_FLT_FILTER_14 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/32, N=6 */
+#define LL_HRTIM_FLT_FILTER_15 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32, N=8 */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_FLT_PRESCALER BURST FAULT PRESCALER
+ * @{
+ * @brief Constants defining the division ratio between the timer clock frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used by the digital filters.
+ */
+#define LL_HRTIM_FLT_PRESCALER_DIV1 ((uint32_t)0x00000000U) /*!< fFLTS = fHRTIM */
+#define LL_HRTIM_FLT_PRESCALER_DIV2 (HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS = fHRTIM / 2 */
+#define LL_HRTIM_FLT_PRESCALER_DIV4 (HRTIM_FLTINR2_FLTSD_1) /*!< fFLTS = fHRTIM / 4 */
+#define LL_HRTIM_FLT_PRESCALER_DIV8 (HRTIM_FLTINR2_FLTSD_1 | HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS = fHRTIM / 8 */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_BM_MODE BURST MODE OPERATING MODE
+ * @{
+ * @brief Constants defining if the burst mode is entered once or if it is continuously operating.
+ */
+#define LL_HRTIM_BM_MODE_SINGLESHOT ((uint32_t)0x00000000U) /*!< Burst mode operates in single shot mode */
+#define LL_HRTIM_BM_MODE_CONTINOUS (HRTIM_BMCR_BMOM) /*!< Burst mode operates in continuous mode */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_BM_CLKSRC BURST MODE CLOCK SOURCE
+ * @{
+ * @brief Constants defining the clock source for the burst mode counter.
+ */
+#define LL_HRTIM_BM_CLKSRC_MASTER ((uint32_t)0x00000000U) /*!< Master timer counter reset/roll-over is used as clock source for the burst mode counter */
+#define LL_HRTIM_BM_CLKSRC_TIMER_A (HRTIM_BMCR_BMCLK_0) /*!< Timer A counter reset/roll-over is used as clock source for the burst mode counter */
+#define LL_HRTIM_BM_CLKSRC_TIMER_B (HRTIM_BMCR_BMCLK_1) /*!< Timer B counter reset/roll-over is used as clock source for the burst mode counter */
+#define LL_HRTIM_BM_CLKSRC_TIMER_C (HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< Timer C counter reset/roll-over is used as clock source for the burst mode counter */
+#define LL_HRTIM_BM_CLKSRC_TIMER_D (HRTIM_BMCR_BMCLK_2) /*!< Timer D counter reset/roll-over is used as clock source for the burst mode counter */
+#define LL_HRTIM_BM_CLKSRC_TIMER_E (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0) /*!< Timer E counter reset/roll-over is used as clock source for the burst mode counter */
+#define LL_HRTIM_BM_CLKSRC_TIM16_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1) /*!< On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock */
+#define LL_HRTIM_BM_CLKSRC_TIM17_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock */
+#define LL_HRTIM_BM_CLKSRC_TIM7_TRGO (HRTIM_BMCR_BMCLK_3) /*!< On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock */
+#define LL_HRTIM_BM_CLKSRC_FHRTIM (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1) /*!< Prescaled fHRTIM clock is used as clock source for the burst mode counter */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_BM_PRESCALER BURST MODE PRESCALER
+ * @{
+ * @brief Constants defining the prescaling ratio of the fHRTIM clock for the burst mode controller (fBRST).
+ */
+#define LL_HRTIM_BM_PRESCALER_DIV1 ((uint32_t)0x00000000U) /*!< fBRST = fHRTIM */
+#define LL_HRTIM_BM_PRESCALER_DIV2 (HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2 */
+#define LL_HRTIM_BM_PRESCALER_DIV4 (HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/4 */
+#define LL_HRTIM_BM_PRESCALER_DIV8 (HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8 */
+#define LL_HRTIM_BM_PRESCALER_DIV16 (HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/16 */
+#define LL_HRTIM_BM_PRESCALER_DIV32 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32 */
+#define LL_HRTIM_BM_PRESCALER_DIV64 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/64 */
+#define LL_HRTIM_BM_PRESCALER_DIV128 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/128 */
+#define LL_HRTIM_BM_PRESCALER_DIV256 (HRTIM_BMCR_BMPRSC_3) /*!< fBRST = fHRTIM/256 */
+#define LL_HRTIM_BM_PRESCALER_DIV512 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/512 */
+#define LL_HRTIM_BM_PRESCALER_DIV1024 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/1024 */
+#define LL_HRTIM_BM_PRESCALER_DIV2048 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2048*/
+#define LL_HRTIM_BM_PRESCALER_DIV4096 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/4096 */
+#define LL_HRTIM_BM_PRESCALER_DIV8192 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8192 */
+#define LL_HRTIM_BM_PRESCALER_DIV16384 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/16384 */
+#define LL_HRTIM_BM_PRESCALER_DIV32768 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32768 */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_BM_TRIG HRTIM BURST MODE TRIGGER
+ * @{
+ * @brief Constants defining the events that can be used to trig the burst mode operation.
+ */
+#define LL_HRTIM_BM_TRIG_NONE (uint32_t)0x00000000 /*!< No trigger */
+#define LL_HRTIM_BM_TRIG_MASTER_RESET (HRTIM_BMTRGR_MSTRST) /*!< Master timer reset event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_MASTER_REPETITION (HRTIM_BMTRGR_MSTREP) /*!< Master timer repetition event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_MASTER_CMP1 (HRTIM_BMTRGR_MSTCMP1) /*!< Master timer compare 1 event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_MASTER_CMP2 (HRTIM_BMTRGR_MSTCMP2) /*!< Master timer compare 2 event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_MASTER_CMP3 (HRTIM_BMTRGR_MSTCMP3) /*!< Master timer compare 3 event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_MASTER_CMP4 (HRTIM_BMTRGR_MSTCMP4) /*!< Master timer compare 4 event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMA_RESET (HRTIM_BMTRGR_TARST) /*!< Timer A reset event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMA_REPETITION (HRTIM_BMTRGR_TAREP) /*!< Timer A repetition event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMA_CMP1 (HRTIM_BMTRGR_TACMP1) /*!< Timer A compare 1 event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMA_CMP2 (HRTIM_BMTRGR_TACMP2) /*!< Timer A compare 2 event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMB_RESET (HRTIM_BMTRGR_TBRST) /*!< Timer B reset event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMB_REPETITION (HRTIM_BMTRGR_TBREP) /*!< Timer B repetition event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMB_CMP1 (HRTIM_BMTRGR_TBCMP1) /*!< Timer B compare 1 event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMB_CMP2 (HRTIM_BMTRGR_TBCMP2) /*!< Timer B compare 2 event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMC_RESET (HRTIM_BMTRGR_TCRST) /*!< Timer C resetevent is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMC_REPETITION (HRTIM_BMTRGR_TCREP) /*!< Timer C repetition event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMC_CMP1 (HRTIM_BMTRGR_TCCMP1) /*!< Timer C compare 1 event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMC_CMP2 (HRTIM_BMTRGR_TCCMP2) /*!< Timer C compare 2 event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMD_RESET (HRTIM_BMTRGR_TDRST) /*!< Timer D reset event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMD_REPETITION (HRTIM_BMTRGR_TDREP) /*!< Timer D repetition event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMD_CMP1 (HRTIM_BMTRGR_TDCMP1) /*!< Timer D compare 1 event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMD_CMP2 (HRTIM_BMTRGR_TDCMP2) /*!< Timer D compare 2 event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIME_RESET (HRTIM_BMTRGR_TERST) /*!< Timer E reset event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIME_REPETITION (HRTIM_BMTRGR_TEREP) /*!< Timer E repetition event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIME_CMP1 (HRTIM_BMTRGR_TECMP1) /*!< Timer E compare 1 event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIME_CMP2 (HRTIM_BMTRGR_TECMP2) /*!< Timer E compare 2 event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMA_EVENT7 (HRTIM_BMTRGR_TAEEV7) /*!< Timer A period following an external event 7 (conditioned by TIMA filters) is starting the burst
+mode operation */
+#define LL_HRTIM_BM_TRIG_TIMD_EVENT8 (HRTIM_BMTRGR_TDEEV8) /*!< Timer D period following an external event 8 (conditioned by TIMD filters) is starting the burst
+mode operation */
+#define LL_HRTIM_BM_TRIG_EVENT_7 (HRTIM_BMTRGR_EEV7) /*!< External event 7 conditioned by TIMA filters is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_EVENT_8 (HRTIM_BMTRGR_EEV8) /*!< External event 8 conditioned by TIMD filters is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_EVENT_ONCHIP (HRTIM_BMTRGR_OCHPEV) /*!< A rising edge on an on-chip Event (for instance from GP timer or comparator) triggers the burst mode
+operation */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_BM_STATUS HRTIM BURST MODE STATUS
+ * @{
+ * @brief Constants defining the operating state of the burst mode controller.
+ */
+#define LL_HRTIM_BM_STATUS_NORMAL ((uint32_t) 0x00000000U) /*!< Normal operation */
+#define LL_HRTIM_BM_STATUS_BURST_ONGOING (HRTIM_BMCR_BMSTAT) /*!< Burst operation on-going */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup HRTIM_LL_Exported_Macros HRTIM Exported Macros
+ * @{
+ */
+
+/** @defgroup HRTIM_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in HRTIM register
+ * @param __INSTANCE__ HRTIM Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_HRTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in HRTIM register
+ * @param __INSTANCE__ HRTIM Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_HRTIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_LL_EM_Exported_Macros Exported_Macros
+ * @{
+ */
+/**
+ * @brief HELPER macro returning the output state from output enable/disable status
+ * @param __OUTPUT_STATUS_EN__ output enable status
+ * @param __OUTPUT_STATUS_DIS__ output Disable status
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_HRTIM_OUTPUTSTATE_IDLE
+ * @arg @ref LL_HRTIM_OUTPUTSTATE_RUN
+ * @arg @ref LL_HRTIM_OUTPUTSTATE_FAULT
+*/
+#define __LL_HRTIM_GET_OUTPUT_STATE(__OUTPUT_STATUS_EN__, __OUTPUT_STATUS_DIS__)\
+ (((__OUTPUT_STATUS_EN__) == 1) ? LL_HRTIM_OUTPUTSTATE_RUN :\
+ ((__OUTPUT_STATUS_DIS__) == 0) ? LL_HRTIM_OUTPUTSTATE_IDLE : LL_HRTIM_OUTPUTSTATE_FAULT)
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup HRTIM_LL_Exported_Functions HRTIM Exported Functions
+ * @{
+ */
+/** @defgroup HRTIM_EF_HRTIM_Control HRTIM_Control
+ * @{
+ */
+
+/**
+ * @brief Select the HRTIM synchronization input source.
+ * @note This function must not be called when the concerned timer(s) is (are) enabled .
+ * @rmtoll MCR SYNCIN LL_HRTIM_SetSyncInSrc
+ * @param HRTIMx High Resolution Timer instance
+ * @param SyncInSrc This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_SYNCIN_SRC_NONE
+ * @arg @ref LL_HRTIM_SYNCIN_SRC_TIM_EVENT
+ * @arg @ref LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_SetSyncInSrc(HRTIM_TypeDef *HRTIMx, uint32_t SyncInSrc)
+{
+ MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_IN, SyncInSrc);
+}
+
+/**
+ * @brief Get actual HRTIM synchronization input source.
+ * @rmtoll MCR SYNCIN LL_HRTIM_SetSyncInSrc
+ * @param HRTIMx High Resolution Timer instance
+ * @retval SyncInSrc Returned value can be one of the following values:
+ * @arg @ref LL_HRTIM_SYNCIN_SRC_NONE
+ * @arg @ref LL_HRTIM_SYNCIN_SRC_TIM_EVENT
+ * @arg @ref LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_GetSyncInSrc(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_IN));
+}
+
+/**
+ * @brief Configure the HRTIM synchronization output.
+ * @rmtoll MCR SYNCSRC LL_HRTIM_ConfigSyncOut\n
+ * MCR SYNCOUT LL_HRTIM_ConfigSyncOut
+ * @param HRTIMx High Resolution Timer instance
+ * @param Config This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_SYNCOUT_DISABLED
+ * @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE
+ * @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
+ * @param Src This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START
+ * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1
+ * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START
+ * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ConfigSyncOut(HRTIM_TypeDef *HRTIMx, uint32_t Config, uint32_t Src)
+{
+ MODIFY_REG(HRTIMx->sMasterRegs.MCR, (HRTIM_MCR_SYNC_OUT | HRTIM_MCR_SYNC_SRC), (Config | Src));
+}
+
+/**
+ * @brief Set the routing and conditioning of the synchronization output event.
+ * @rmtoll MCR SYNCOUT LL_HRTIM_SetSyncOutConfig
+ * @note This function can be called only when the master timer is enabled.
+ * @param HRTIMx High Resolution Timer instance
+ * @param SyncOutConfig This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_SYNCOUT_DISABLED
+ * @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE
+ * @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_SetSyncOutConfig(HRTIM_TypeDef *HRTIMx, uint32_t SyncOutConfig)
+{
+ MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_OUT, SyncOutConfig);
+}
+
+/**
+ * @brief Get actual routing and conditioning of the synchronization output event.
+ * @rmtoll MCR SYNCOUT LL_HRTIM_GetSyncOutConfig
+ * @param HRTIMx High Resolution Timer instance
+ * @retval SyncOutConfig Returned value can be one of the following values:
+ * @arg @ref LL_HRTIM_SYNCOUT_DISABLED
+ * @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE
+ * @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_GetSyncOutConfig(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_OUT));
+}
+
+/**
+ * @brief Set the source and event to be sent on the HRTIM synchronization output.
+ * @rmtoll MCR SYNCSRC LL_HRTIM_SetSyncOutSrc
+ * @param HRTIMx High Resolution Timer instance
+ * @param SyncOutSrc This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START
+ * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1
+ * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START
+ * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_SetSyncOutSrc(HRTIM_TypeDef *HRTIMx, uint32_t SyncOutSrc)
+{
+ MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_SRC, SyncOutSrc);
+}
+
+/**
+ * @brief Get actual source and event sent on the HRTIM synchronization output.
+ * @rmtoll MCR SYNCSRC LL_HRTIM_GetSyncOutSrc
+ * @param HRTIMx High Resolution Timer instance
+ * @retval SyncOutSrc Returned value can be one of the following values:
+ * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START
+ * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1
+ * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START
+ * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_GetSyncOutSrc(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_SRC));
+}
+
+/**
+ * @brief Disable (temporarily) update event generation.
+ * @rmtoll CR1 MUDIS LL_HRTIM_SuspendUpdate\n
+ * CR1 TAUDIS LL_HRTIM_SuspendUpdate\n
+ * CR1 TBUDIS LL_HRTIM_SuspendUpdate\n
+ * CR1 TCUDIS LL_HRTIM_SuspendUpdate\n
+ * CR1 TDUDIS LL_HRTIM_SuspendUpdate\n
+ * CR1 TEUDIS LL_HRTIM_SuspendUpdate
+ * @note Allow to temporarily disable the transfer from preload to active
+ * registers, whatever the selected update event. This allows to modify
+ * several registers in multiple timers.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timers This parameter can be a combination of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_SuspendUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
+{
+ SET_BIT(HRTIMx->sCommonRegs.CR1, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR1_UDIS_MASK));
+}
+
+/**
+ * @brief Enable update event generation.
+ * @rmtoll CR1 MUDIS LL_HRTIM_ResumeUpdate\n
+ * CR1 TAUDIS LL_HRTIM_ResumeUpdate\n
+ * CR1 TBUDIS LL_HRTIM_ResumeUpdate\n
+ * CR1 TCUDIS LL_HRTIM_ResumeUpdate\n
+ * CR1 TDUDIS LL_HRTIM_ResumeUpdate\n
+ * CR1 TEUDIS LL_HRTIM_ResumeUpdate
+ * @note The regular update event takes place.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timers This parameter can be a combination of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ResumeUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
+{
+ CLEAR_BIT(HRTIMx->sCommonRegs.CR1, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR1_UDIS_MASK));
+}
+
+/**
+ * @brief Force an immediate transfer from the preload to the active register .
+ * @rmtoll CR2 MSWU LL_HRTIM_ForceUpdate\n
+ * CR2 TASWU LL_HRTIM_ForceUpdate\n
+ * CR2 TBSWU LL_HRTIM_ForceUpdate\n
+ * CR2 TCSWU LL_HRTIM_ForceUpdate\n
+ * CR2 TDSWU LL_HRTIM_ForceUpdate\n
+ * CR2 TESWU LL_HRTIM_ForceUpdate
+ * @note Any pending update request is cancelled.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timers This parameter can be a combination of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ForceUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
+{
+ SET_BIT(HRTIMx->sCommonRegs.CR2, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR2_SWUPD_MASK));
+}
+
+/**
+ * @brief Reset the HRTIM timer(s) counter.
+ * @rmtoll CR2 MRST LL_HRTIM_CounterReset\n
+ * CR2 TARST LL_HRTIM_CounterReset\n
+ * CR2 TBRST LL_HRTIM_CounterReset\n
+ * CR2 TCRST LL_HRTIM_CounterReset\n
+ * CR2 TDRST LL_HRTIM_CounterReset\n
+ * CR2 TERST LL_HRTIM_CounterReset
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timers This parameter can be a combination of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_CounterReset(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
+{
+ SET_BIT(HRTIMx->sCommonRegs.CR2, (((Timers >> HRTIM_MCR_MCEN_Pos) << HRTIM_CR2_MRST_Pos) & HRTIM_CR2_SWRST_MASK));
+}
+
+/**
+ * @brief Enable the HRTIM timer(s) output(s) .
+ * @rmtoll OENR TA1OEN LL_HRTIM_EnableOutput\n
+ * OENR TA2OEN LL_HRTIM_EnableOutput\n
+ * OENR TB1OEN LL_HRTIM_EnableOutput\n
+ * OENR TB2OEN LL_HRTIM_EnableOutput\n
+ * OENR TC1OEN LL_HRTIM_EnableOutput\n
+ * OENR TC2OEN LL_HRTIM_EnableOutput\n
+ * OENR TD1OEN LL_HRTIM_EnableOutput\n
+ * OENR TD2OEN LL_HRTIM_EnableOutput\n
+ * OENR TE1OEN LL_HRTIM_EnableOutput\n
+ * OENR TE2OEN LL_HRTIM_EnableOutput
+ * @param HRTIMx High Resolution Timer instance
+ * @param Outputs This parameter can be a combination of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableOutput(HRTIM_TypeDef *HRTIMx, uint32_t Outputs)
+{
+ SET_BIT(HRTIMx->sCommonRegs.OENR, (Outputs & HRTIM_OENR_OEN_MASK));
+}
+
+/**
+ * @brief Disable the HRTIM timer(s) output(s) .
+ * @rmtoll OENR TA1OEN LL_HRTIM_DisableOutput\n
+ * OENR TA2OEN LL_HRTIM_DisableOutput\n
+ * OENR TB1OEN LL_HRTIM_DisableOutput\n
+ * OENR TB2OEN LL_HRTIM_DisableOutput\n
+ * OENR TC1OEN LL_HRTIM_DisableOutput\n
+ * OENR TC2OEN LL_HRTIM_DisableOutput\n
+ * OENR TD1OEN LL_HRTIM_DisableOutput\n
+ * OENR TD2OEN LL_HRTIM_DisableOutput\n
+ * OENR TE1OEN LL_HRTIM_DisableOutput\n
+ * OENR TE2OEN LL_HRTIM_DisableOutput
+ * @param HRTIMx High Resolution Timer instance
+ * @param Outputs This parameter can be a combination of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableOutput(HRTIM_TypeDef *HRTIMx, uint32_t Outputs)
+{
+ SET_BIT(HRTIMx->sCommonRegs.ODISR, (Outputs & HRTIM_OENR_ODIS_MASK));
+}
+
+/**
+ * @brief Indicates whether the HRTIM timer output is enabled.
+ * @rmtoll OENR TA1OEN LL_HRTIM_IsEnabledOutput\n
+ * OENR TA2OEN LL_HRTIM_IsEnabledOutput\n
+ * OENR TB1OEN LL_HRTIM_IsEnabledOutput\n
+ * OENR TB2OEN LL_HRTIM_IsEnabledOutput\n
+ * OENR TC1OEN LL_HRTIM_IsEnabledOutput\n
+ * OENR TC2OEN LL_HRTIM_IsEnabledOutput\n
+ * OENR TD1OEN LL_HRTIM_IsEnabledOutput\n
+ * OENR TD2OEN LL_HRTIM_IsEnabledOutput\n
+ * OENR TE1OEN LL_HRTIM_IsEnabledOutput\n
+ * OENR TE2OEN LL_HRTIM_IsEnabledOutput
+ * @param HRTIMx High Resolution Timer instance
+ * @param Output This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @retval State of TxyOEN bit in HRTIM_OENR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledOutput(HRTIM_TypeDef *HRTIMx, uint32_t Output)
+{
+ return (READ_BIT(HRTIMx->sCommonRegs.OENR, Output) == Output);
+}
+
+/**
+ * @brief Indicates whether the HRTIM timer output is disabled.
+ * @rmtoll ODISR TA1ODIS LL_HRTIM_IsDisabledOutput\n
+ * ODISR TA2ODIS LL_HRTIM_IsDisabledOutput\n
+ * ODISR TB1ODIS LL_HRTIM_IsDisabledOutput\n
+ * ODISR TB2ODIS LL_HRTIM_IsDisabledOutput\n
+ * ODISR TC1ODIS LL_HRTIM_IsDisabledOutput\n
+ * ODISR TC2ODIS LL_HRTIM_IsDisabledOutput\n
+ * ODISR TD1ODIS LL_HRTIM_IsDisabledOutput\n
+ * ODISR TD2ODIS LL_HRTIM_IsDisabledOutput\n
+ * ODISR TE1ODIS LL_HRTIM_IsDisabledOutput\n
+ * ODISR TE2ODIS LL_HRTIM_IsDisabledOutput
+ * @param HRTIMx High Resolution Timer instance
+ * @param Output This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @retval State of TxyODS bit in HRTIM_ODSR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsDisabledOutput(HRTIM_TypeDef *HRTIMx, uint32_t Output)
+{
+ return (READ_BIT(HRTIMx->sCommonRegs.ODISR, Output) == Output);
+}
+
+/**
+ * @brief Configure an ADC trigger.
+ * @rmtoll CR1 ADC1USRC LL_HRTIM_ConfigADCTrig\n
+ * CR1 ADC2USRC LL_HRTIM_ConfigADCTrig\n
+ * CR1 ADC3USRC LL_HRTIM_ConfigADCTrig\n
+ * CR1 ADC4USRC LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1MC4 LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1MPER LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1EEV1 LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1EEV2 LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1EEV3 LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1EEV4 LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1EEV5 LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1TAC2 LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1TAC3 LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1TAC4 LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1TAPER LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1TARST LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1TBC2 LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1TBC3 LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1TBC4 LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1TBPER LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1TBRST LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1TCC2 LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1TCC3 LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1TCC4 LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1TCPER LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1TDC2 LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1TDC3 LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1TDC4 LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1TDPER LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1TEC2 LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1TEC3 LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1TEC4 LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1TEPER LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2MC1 LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2MC2 LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2MC3 LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2MC4 LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2MPER LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2EEV6 LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2EEV7 LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2EEV8 LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2EEV9 LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2EEV10 LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2TAC2 LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2TAC3 LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2TAC4 LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2TAPER LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2TBC2 LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2TBC3 LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2TBC4 LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2TBPER LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2TCC2 LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2TCC3 LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2TCC4 LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2TCPER LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2TCRST LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2TDC2 LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2TDC3 LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2TDC4 LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2TDPER LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2TDRST LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2TEC2 LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2TEC3 LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2TEC4 LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2TERST LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3MC1 LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3MC2 LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3MC3 LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3MC4 LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3MPER LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3EEV1 LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3EEV2 LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3EEV3 LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3EEV4 LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3EEV5 LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3TAC2 LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3TAC3 LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3TAC4 LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3TAPER LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3TARST LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3TBC2 LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3TBC3 LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3TBC4 LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3TBPER LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3TBRST LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3TCC2 LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3TCC3 LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3TCC4 LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3TCPER LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3TDC2 LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3TDC3 LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3TDC4 LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3TDPER LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3TEC2 LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3TEC3 LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3TEC4 LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3TEPER LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4MC1 LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4MC2 LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4MC3 LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4MC4 LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4MPER LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4EEV6 LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4EEV7 LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4EEV8 LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4EEV9 LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4EEV10 LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4TAC2 LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4TAC3 LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4TAC4 LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4TAPER LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4TBC2 LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4TBC3 LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4TBC4 LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4TBPER LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4TCC2 LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4TCC3 LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4TCC4 LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4TCPER LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4TCRST LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4TDC2 LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4TDC3 LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4TDC4 LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4TDPER LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4TDRST LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4TEC2 LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4TEC3 LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4TEC4 LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4TERST LL_HRTIM_ConfigADCTrig
+ * @param HRTIMx High Resolution Timer instance
+ * @param ADCTrig This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_ADCTRIG_1
+ * @arg @ref LL_HRTIM_ADCTRIG_2
+ * @arg @ref LL_HRTIM_ADCTRIG_3
+ * @arg @ref LL_HRTIM_ADCTRIG_4
+ * @param Update This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER
+ * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A
+ * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B
+ * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C
+ * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
+ * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
+ * @param Src This parameter can be a combination of the following values:
+ *
+ * For ADC trigger 1 and ADC trigger 3:
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER
+ *
+ * For ADC trigger 2 and ADC trigger 4:
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ConfigADCTrig(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Update, uint32_t Src)
+{
+ register uint32_t shift = 3 * ADCTrig;
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
+ REG_OFFSET_TAB_ADCxR[ADCTrig]));
+ MODIFY_REG(HRTIMx->sCommonRegs.CR1, (HRTIM_CR1_ADC1USRC << shift), (Update << shift));
+ WRITE_REG(*pReg, Src);
+}
+
+/**
+ * @brief Associate the ADCx trigger to a timer triggering the update of the HRTIM_ADCxR register.
+ * @rmtoll CR1 ADC1USRC LL_HRTIM_SetADCTrigUpdate\n
+ * CR1 ADC2USRC LL_HRTIM_SetADCTrigUpdate\n
+ * CR1 ADC3USRC LL_HRTIM_SetADCTrigUpdate\n
+ * CR1 ADC4USRC LL_HRTIM_SetADCTrigUpdate
+ * @note When the preload is disabled in the source timer, the HRTIM_ADCxR
+ * registers are not preloaded either: a write access will result in an
+ * immediate update of the trigger source.
+ * @param HRTIMx High Resolution Timer instance
+ * @param ADCTrig This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_ADCTRIG_1
+ * @arg @ref LL_HRTIM_ADCTRIG_2
+ * @arg @ref LL_HRTIM_ADCTRIG_3
+ * @arg @ref LL_HRTIM_ADCTRIG_4
+ * @param Update This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER
+ * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A
+ * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B
+ * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C
+ * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
+ * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_SetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Update)
+{
+ register uint32_t shift = 3 * ADCTrig;
+ MODIFY_REG(HRTIMx->sCommonRegs.CR1, (HRTIM_CR1_ADC1USRC << shift), (Update << shift));
+}
+
+/**
+ * @brief Get the source timer triggering the update of the HRTIM_ADCxR register.
+ * @rmtoll CR1 ADC1USRC LL_HRTIM_GetADCTrigUpdate\n
+ * CR1 ADC2USRC LL_HRTIM_GetADCTrigUpdate\n
+ * CR1 ADC3USRC LL_HRTIM_GetADCTrigUpdate\n
+ * CR1 ADC4USRC LL_HRTIM_GetADCTrigUpdate
+ * @param HRTIMx High Resolution Timer instance
+ * @param ADCTrig This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_ADCTRIG_1
+ * @arg @ref LL_HRTIM_ADCTRIG_2
+ * @arg @ref LL_HRTIM_ADCTRIG_3
+ * @arg @ref LL_HRTIM_ADCTRIG_4
+ * @retval Update Returned value can be one of the following values:
+ * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER
+ * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A
+ * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B
+ * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C
+ * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
+ * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig)
+{
+ register uint32_t shift = 3 * ADCTrig;
+ return (READ_BIT(HRTIMx->sCommonRegs.CR1, (HRTIM_CR1_ADC1USRC << shift)) >> shift);
+}
+
+/**
+ * @brief Specify which events (timer events and/or external events) are used as triggers for ADC conversion.
+ * @rmtoll ADC1R ADC1MC4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1MPER LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1EEV1 LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1EEV2 LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1EEV3 LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1EEV4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1EEV5 LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1TAC2 LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1TAC3 LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1TAC4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1TAPER LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1TARST LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1TBC2 LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1TBC3 LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1TBC4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1TBPER LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1TBRST LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1TCC2 LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1TCC3 LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1TCC4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1TCPER LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1TDC2 LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1TDC3 LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1TDC4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1TDPER LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1TEC2 LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1TEC3 LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1TEC4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1TEPER LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2MC1 LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2MC2 LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2MC3 LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2MC4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2MPER LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2EEV6 LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2EEV7 LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2EEV8 LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2EEV9 LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2EEV10 LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2TAC2 LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2TAC3 LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2TAC4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2TAPER LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2TBC2 LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2TBC3 LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2TBC4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2TBPER LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2TCC2 LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2TCC3 LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2TCC4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2TCPER LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2TCRST LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2TDC2 LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2TDC3 LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2TDC4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2TDPER LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2TDRST LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2TEC2 LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2TEC3 LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2TEC4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2TERST LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3MC1 LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3MC2 LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3MC3 LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3MC4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3MPER LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3EEV1 LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3EEV2 LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3EEV3 LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3EEV4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3EEV5 LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3TAC2 LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3TAC3 LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3TAC4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3TAPER LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3TARST LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3TBC2 LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3TBC3 LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3TBC4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3TBPER LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3TBRST LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3TCC2 LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3TCC3 LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3TCC4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3TCPER LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3TDC2 LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3TDC3 LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3TDC4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3TDPER LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3TEC2 LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3TEC3 LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3TEC4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3TEPER LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4MC1 LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4MC2 LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4MC3 LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4MC4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4MPER LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4EEV6 LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4EEV7 LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4EEV8 LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4EEV9 LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4EEV10 LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4TAC2 LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4TAC3 LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4TAC4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4TAPER LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4TBC2 LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4TBC3 LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4TBC4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4TBPER LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4TCC2 LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4TCC3 LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4TCC4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4TCPER LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4TCRST LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4TDC2 LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4TDC3 LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4TDC4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4TDPER LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4TDRST LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4TEC2 LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4TEC3 LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4TEC4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4TERST LL_HRTIM_SetADCTrigSrc
+ * @param HRTIMx High Resolution Timer instance
+ * @param ADCTrig This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_ADCTRIG_1
+ * @arg @ref LL_HRTIM_ADCTRIG_2
+ * @arg @ref LL_HRTIM_ADCTRIG_3
+ * @arg @ref LL_HRTIM_ADCTRIG_4
+ * @param Src This parameter can be a combination of the following values:
+ *
+ * For ADC trigger 1 and ADC trigger 3:
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER
+ *
+ * For ADC trigger 2 and ADC trigger 4:
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST
+* @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_SetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Src)
+{
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
+ REG_OFFSET_TAB_ADCxR[ADCTrig]));
+ WRITE_REG(*pReg, Src);
+}
+
+/**
+ * @brief Indicate which events (timer events and/or external events) are currently used as triggers for ADC conversion.
+ * @rmtoll ADC1R ADC1MC4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1MPER LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1EEV1 LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1EEV2 LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1EEV3 LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1EEV4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1EEV5 LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1TAC2 LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1TAC3 LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1TAC4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1TAPER LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1TARST LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1TBC2 LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1TBC3 LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1TBC4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1TBPER LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1TBRST LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1TCC2 LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1TCC3 LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1TCC4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1TCPER LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1TDC2 LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1TDC3 LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1TDC4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1TDPER LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1TEC2 LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1TEC3 LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1TEC4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1TEPER LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2MC1 LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2MC2 LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2MC3 LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2MC4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2MPER LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2EEV6 LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2EEV7 LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2EEV8 LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2EEV9 LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2EEV10 LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2TAC2 LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2TAC3 LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2TAC4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2TAPER LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2TBC2 LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2TBC3 LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2TBC4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2TBPER LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2TCC2 LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2TCC3 LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2TCC4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2TCPER LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2TCRST LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2TDC2 LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2TDC3 LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2TDC4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2TDPER LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2TDRST LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2TEC2 LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2TEC3 LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2TEC4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2TERST LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3MC1 LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3MC2 LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3MC3 LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3MC4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3MPER LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3EEV1 LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3EEV2 LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3EEV3 LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3EEV4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3EEV5 LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3TAC2 LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3TAC3 LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3TAC4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3TAPER LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3TARST LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3TBC2 LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3TBC3 LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3TBC4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3TBPER LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3TBRST LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3TCC2 LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3TCC3 LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3TCC4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3TCPER LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3TDC2 LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3TDC3 LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3TDC4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3TDPER LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3TEC2 LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3TEC3 LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3TEC4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3TEPER LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4MC1 LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4MC2 LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4MC3 LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4MC4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4MPER LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4EEV6 LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4EEV7 LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4EEV8 LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4EEV9 LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4EEV10 LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4TAC2 LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4TAC3 LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4TAC4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4TAPER LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4TBC2 LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4TBC3 LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4TBC4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4TBPER LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4TCC2 LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4TCC3 LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4TCC4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4TCPER LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4TCRST LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4TDC2 LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4TDC3 LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4TDC4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4TDPER LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4TDRST LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4TEC2 LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4TEC3 LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4TEC4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4TERST LL_HRTIM_GetADCTrigSrc
+ * @param HRTIMx High Resolution Timer instance
+ * @param ADCTrig This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_ADCTRIG_1
+ * @arg @ref LL_HRTIM_ADCTRIG_2
+ * @arg @ref LL_HRTIM_ADCTRIG_3
+ * @arg @ref LL_HRTIM_ADCTRIG_4
+ * @retval Src This parameter can be a combination of the following values:
+ *
+ * For ADC trigger 1 and ADC trigger 3:
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER
+ *
+ * For ADC trigger 2 and ADC trigger 4:
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig)
+{
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
+ REG_OFFSET_TAB_ADCxR[ADCTrig]));
+ return (*pReg);
+}
+
+/**
+ * @brief Configure the DLL calibration mode.
+ * @rmtoll DLLCR CALEN LL_HRTIM_ConfigDLLCalibration\n
+ * DLLCR CALRTE LL_HRTIM_ConfigDLLCalibration
+ * @param HRTIMx High Resolution Timer instance
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_DLLCALIBRATION_MODE_SINGLESHOT
+ * @arg @ref LL_HRTIM_DLLCALIBRATION_MODE_CONTINUOUS
+ * @param Period This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_DLLCALIBRATION_RATE_7300
+ * @arg @ref LL_HRTIM_DLLCALIBRATION_RATE_910
+ * @arg @ref LL_HRTIM_DLLCALIBRATION_RATE_114
+ * @arg @ref LL_HRTIM_DLLCALIBRATION_RATE_14
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ConfigDLLCalibration(HRTIM_TypeDef *HRTIMx, uint32_t Mode, uint32_t Period)
+{
+ MODIFY_REG(HRTIMx->sCommonRegs.DLLCR, (HRTIM_DLLCR_CALEN | HRTIM_DLLCR_CALRTE), (Mode | Period));
+}
+
+/**
+ * @brief Launch DLL calibration
+ * @rmtoll DLLCR CAL LL_HRTIM_StartDLLCalibration
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_StartDLLCalibration(HRTIM_TypeDef *HRTIMx)
+{
+ SET_BIT(HRTIMx->sCommonRegs.DLLCR, HRTIM_DLLCR_CAL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EF_HRTIM_Timer_Control HRTIM_Timer_Control
+ * @{
+ */
+
+/**
+ * @brief Enable timer(s) counter.
+ * @rmtoll MDIER TECEN LL_HRTIM_TIM_CounterEnable\n
+ * MDIER TDCEN LL_HRTIM_TIM_CounterEnable\n
+ * MDIER TCCEN LL_HRTIM_TIM_CounterEnable\n
+ * MDIER TBCEN LL_HRTIM_TIM_CounterEnable\n
+ * MDIER TACEN LL_HRTIM_TIM_CounterEnable\n
+ * MDIER MCEN LL_HRTIM_TIM_CounterEnable
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timers This parameter can be a combination of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_CounterEnable(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
+{
+ SET_BIT(HRTIMx->sMasterRegs.MCR, Timers);
+}
+
+/**
+ * @brief Disable timer(s) counter.
+ * @rmtoll MDIER TECEN LL_HRTIM_TIM_CounterDisable\n
+ * MDIER TDCEN LL_HRTIM_TIM_CounterDisable\n
+ * MDIER TCCEN LL_HRTIM_TIM_CounterDisable\n
+ * MDIER TBCEN LL_HRTIM_TIM_CounterDisable\n
+ * MDIER TACEN LL_HRTIM_TIM_CounterDisable\n
+ * MDIER MCEN LL_HRTIM_TIM_CounterDisable
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timers This parameter can be a combination of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_CounterDisable(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
+{
+ CLEAR_BIT(HRTIMx->sMasterRegs.MCR, Timers);
+}
+
+/**
+ * @brief Indicate whether the timer counter is enabled.
+ * @rmtoll MDIER TECEN LL_HRTIM_TIM_IsCounterEnabled\n
+ * MDIER TDCEN LL_HRTIM_TIM_IsCounterEnabled\n
+ * MDIER TCCEN LL_HRTIM_TIM_IsCounterEnabled\n
+ * MDIER TBCEN LL_HRTIM_TIM_IsCounterEnabled\n
+ * MDIER TACEN LL_HRTIM_TIM_IsCounterEnabled\n
+ * MDIER MCEN LL_HRTIM_TIM_IsCounterEnabled
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of MCEN or TxCEN bit HRTIM_MCR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsCounterEnabled(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ return (READ_BIT(HRTIMx->sMasterRegs.MCR, Timer) == (Timer));
+}
+
+/**
+ * @brief Set the timer clock prescaler ratio.
+ * @rmtoll MCR CKPSC LL_HRTIM_TIM_SetPrescaler\n
+ * TIMxCR CKPSC LL_HRTIM_TIM_SetPrescaler
+ * @note The counter clock equivalent frequency (CK_CNT) is equal to fHRCK / 2^CKPSC[2:0].
+ * @note The prescaling ratio cannot be modified once the timer counter is enabled.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL32
+ * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL16
+ * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL8
+ * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL4
+ * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL2
+ * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV1
+ * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV2
+ * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV4
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ MODIFY_REG(*pReg, HRTIM_MCR_CK_PSC, Prescaler);
+}
+
+/**
+ * @brief Get the timer clock prescaler ratio
+ * @rmtoll MCR CKPSC LL_HRTIM_TIM_GetPrescaler\n
+ * TIMxCR CKPSC LL_HRTIM_TIM_GetPrescaler
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval Prescaler Returned value can be one of the following values:
+ * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL32
+ * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL16
+ * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL8
+ * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL4
+ * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL2
+ * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV1
+ * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV2
+ * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV4
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MCR_CK_PSC));
+}
+
+/**
+ * @brief Set the counter operating mode mode (single-shot, continuous or re-triggerable).
+ * @rmtoll MCR CONT LL_HRTIM_TIM_SetCounterMode\n
+ * MCR RETRIG LL_HRTIM_TIM_SetCounterMode\n
+ * TIMxCR CONT LL_HRTIM_TIM_SetCounterMode\n
+ * TIMxCR RETRIG LL_HRTIM_TIM_SetCounterMode
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_MODE_CONTINUOUS
+ * @arg @ref LL_HRTIM_MODE_SINGLESHOT
+ * @arg @ref LL_HRTIM_MODE_RETRIGGERABLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_SetCounterMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ MODIFY_REG(*pReg, (HRTIM_TIMCR_RETRIG | HRTIM_MCR_CONT), Mode);
+}
+
+/**
+ * @brief Get the counter operating mode mode
+ * @rmtoll MCR CONT LL_HRTIM_TIM_GetCounterMode\n
+ * MCR RETRIG LL_HRTIM_TIM_GetCounterMode\n
+ * TIMxCR CONT LL_HRTIM_TIM_GetCounterMode\n
+ * TIMxCR RETRIG LL_HRTIM_TIM_GetCounterMode
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval Mode Returned value can be one of the following values:
+ * @arg @ref LL_HRTIM_MODE_CONTINUOUS
+ * @arg @ref LL_HRTIM_MODE_SINGLESHOT
+ * @arg @ref LL_HRTIM_MODE_RETRIGGERABLE
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounterMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, (HRTIM_MCR_RETRIG | HRTIM_MCR_CONT)));
+}
+
+/**
+ * @brief Enable the half duty-cycle mode.
+ * @rmtoll MCR HALF LL_HRTIM_TIM_EnableHalfMode\n
+ * TIMxCR HALF LL_HRTIM_TIM_EnableHalfMode
+ * @note When the half mode is enabled, HRTIM_MCMP1R (or HRTIM_CMP1xR)
+ * active register is automatically updated with HRTIM_MPER/2
+ * (or HRTIM_PERxR/2) value when HRTIM_MPER (or HRTIM_PERxR) register is written.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_EnableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_MCR_HALF);
+}
+
+/**
+ * @brief Disable the half duty-cycle mode.
+ * @rmtoll MCR HALF LL_HRTIM_TIM_DisableHalfMode\n
+ * TIMxCR HALF LL_HRTIM_TIM_DisableHalfMode
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_DisableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_MCR_HALF);
+}
+
+/**
+ * @brief Indicate whether half duty-cycle mode is enabled for a given timer.
+ * @rmtoll MCR HALF LL_HRTIM_TIM_IsEnabledHalfMode\n
+ * TIMxCR HALF LL_HRTIM_TIM_IsEnabledHalfMode
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of HALF bit to 1 in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MCR_HALF) == HRTIM_MCR_HALF);
+}
+
+/**
+ * @brief Enable the timer start when receiving a synchronization input event.
+ * @rmtoll MCR SYNCSTRTM LL_HRTIM_TIM_EnableStartOnSync\n
+ * TIMxCR SYNSTRTA LL_HRTIM_TIM_EnableStartOnSync
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_EnableStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_MCR_SYNCSTRTM);
+}
+
+/**
+ * @brief Disable the timer start when receiving a synchronization input event.
+ * @rmtoll MCR SYNCSTRTM LL_HRTIM_TIM_DisableStartOnSync\n
+ * TIMxCR SYNSTRTA LL_HRTIM_TIM_DisableStartOnSync
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_DisableStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_MCR_SYNCSTRTM);
+}
+
+/**
+ * @brief Indicate whether the timer start when receiving a synchronization input event.
+ * @rmtoll MCR SYNCSTRTM LL_HRTIM_TIM_IsEnabledStartOnSync\n
+ * TIMxCR SYNSTRTA LL_HRTIM_TIM_IsEnabledStartOnSync
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of SYNCSTRTx bit in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MCR_SYNCSTRTM) == HRTIM_MCR_SYNCSTRTM);
+}
+
+/**
+ * @brief Enable the timer reset when receiving a synchronization input event.
+ * @rmtoll MCR SYNCRSTM LL_HRTIM_TIM_EnableResetOnSync\n
+ * TIMxCR SYNCRSTA LL_HRTIM_TIM_EnableResetOnSync
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_EnableResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_MCR_SYNCRSTM);
+}
+
+/**
+ * @brief Disable the timer reset when receiving a synchronization input event.
+ * @rmtoll MCR SYNCRSTM LL_HRTIM_TIM_DisableResetOnSync\n
+ * TIMxCR SYNCRSTA LL_HRTIM_TIM_DisableResetOnSync
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_DisableResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_MCR_SYNCRSTM);
+}
+
+/**
+ * @brief Indicate whether the timer reset when receiving a synchronization input event.
+ * @rmtoll MCR SYNCRSTM LL_HRTIM_TIM_IsEnabledResetOnSync\n
+ * TIMxCR SYNCRSTA LL_HRTIM_TIM_IsEnabledResetOnSync
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MCR_SYNCRSTM) == HRTIM_MCR_SYNCRSTM);
+}
+
+/**
+ * @brief Set the HRTIM output the DAC synchronization event is generated on (DACtrigOutx).
+ * @rmtoll MCR DACSYNC LL_HRTIM_TIM_SetDACTrig\n
+ * TIMxCR DACSYNC LL_HRTIM_TIM_SetDACTrig
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param DACTrig This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_DACTRIG_NONE
+ * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_1
+ * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_2
+ * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_3
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_SetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DACTrig)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ MODIFY_REG(*pReg, HRTIM_MCR_DACSYNC, DACTrig);
+}
+
+/**
+ * @brief Get the HRTIM output the DAC synchronization event is generated on (DACtrigOutx).
+ * @rmtoll MCR DACSYNC LL_HRTIM_TIM_GetDACTrig\n
+ * TIMxCR DACSYNC LL_HRTIM_TIM_GetDACTrig
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval DACTrig Returned value can be one of the following values:
+ * @arg @ref LL_HRTIM_DACTRIG_NONE
+ * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_1
+ * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_2
+ * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_3
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MCR_DACSYNC));
+}
+
+/**
+ * @brief Enable the timer registers preload mechanism.
+ * @rmtoll MCR PREEN LL_HRTIM_TIM_EnablePreload\n
+ * TIMxCR PREEN LL_HRTIM_TIM_EnablePreload
+ * @note When the preload mode is enabled, accessed registers are shadow registers.
+ * Their content is transferred into the active register after an update request,
+ * either software or synchronized with an event.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_EnablePreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_MCR_PREEN);
+}
+
+/**
+ * @brief Disable the timer registers preload mechanism.
+ * @rmtoll MCR PREEN LL_HRTIM_TIM_DisablePreload\n
+ * TIMxCR PREEN LL_HRTIM_TIM_DisablePreload
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_DisablePreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_MCR_PREEN);
+}
+
+/**
+ * @brief Indicate whether the timer registers preload mechanism is enabled.
+ * @rmtoll MCR PREEN LL_HRTIM_TIM_IsEnabledPreload\n
+ * TIMxCR PREEN LL_HRTIM_TIM_IsEnabledPreload
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of PREEN bit in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MCR_PREEN) == HRTIM_MCR_PREEN);
+}
+
+/**
+ * @brief Set the timer register update trigger.
+ * @rmtoll MCR MREPU LL_HRTIM_TIM_SetUpdateTrig\n
+ * TIMxCR TAU LL_HRTIM_TIM_SetUpdateTrig\n
+ * TIMxCR TBU LL_HRTIM_TIM_SetUpdateTrig\n
+ * TIMxCR TCU LL_HRTIM_TIM_SetUpdateTrig\n
+ * TIMxCR TDU LL_HRTIM_TIM_SetUpdateTrig\n
+ * TIMxCR TEU LL_HRTIM_TIM_SetUpdateTrig\n
+ * TIMxCR MSTU LL_HRTIM_TIM_SetUpdateTrig
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param UpdateTrig This parameter can be one of the following values:
+ *
+ * For the master timer this parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_UPDATETRIG_NONE
+ * @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
+ *
+ * For timer A..E this parameter can be:
+ * @arg @ref LL_HRTIM_UPDATETRIG_NONE
+ * or a combination of the following values:
+ * @arg @ref LL_HRTIM_UPDATETRIG_MASTER
+ * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_A
+ * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_B
+ * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_C
+ * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_D
+ * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_E
+ * @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
+ * @arg @ref LL_HRTIM_UPDATETRIG_RESET
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_SetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t UpdateTrig)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ MODIFY_REG(*pReg, REG_MASK_TAB_UPDATETRIG[iTimer], UpdateTrig << REG_SHIFT_TAB_UPDATETRIG[iTimer]);
+}
+
+/**
+ * @brief Set the timer register update trigger.
+ * @rmtoll MCR MREPU LL_HRTIM_TIM_GetUpdateTrig\n
+ * TIMxCR TBU LL_HRTIM_TIM_GetUpdateTrig\n
+ * TIMxCR TCU LL_HRTIM_TIM_GetUpdateTrig\n
+ * TIMxCR TDU LL_HRTIM_TIM_GetUpdateTrig\n
+ * TIMxCR TEU LL_HRTIM_TIM_GetUpdateTrig\n
+ * TIMxCR MSTU LL_HRTIM_TIM_GetUpdateTrig
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval UpdateTrig Returned value can be one of the following values:
+ *
+ * For the master timer this parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_UPDATETRIG_NONE
+ * @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
+ *
+ * For timer A..E this parameter can be:
+ * @arg @ref LL_HRTIM_UPDATETRIG_NONE
+ * or a combination of the following values:
+ * @arg @ref LL_HRTIM_UPDATETRIG_MASTER
+ * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_A
+ * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_B
+ * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_C
+ * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_D
+ * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_E
+ * @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
+ * @arg @ref LL_HRTIM_UPDATETRIG_RESET
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, REG_MASK_TAB_UPDATETRIG[iTimer]) >> REG_SHIFT_TAB_UPDATETRIG[iTimer]);
+}
+
+/**
+ * @brief Set the timer registers update condition (how the registers update occurs relatively to the burst DMA transaction or an external update request received on one of the update enable inputs (UPD_EN[3:1])).
+ * @rmtoll MCR BRSTDMA LL_HRTIM_TIM_SetUpdateGating\n
+ * TIMxCR UPDGAT LL_HRTIM_TIM_SetUpdateGating
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param UpdateGating This parameter can be one of the following values:
+ *
+ * For the master timer this parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
+ * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
+ * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
+ *
+ * For the timer A..E this parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
+ * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
+ * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
+ * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1
+ * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2
+ * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3
+ * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE
+ * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE
+ * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_SetUpdateGating(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t UpdateGating)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ MODIFY_REG(*pReg, REG_MASK_TAB_UPDATEGATING[iTimer], (UpdateGating << REG_SHIFT_TAB_UPDATEGATING[iTimer]));
+}
+
+/**
+ * @brief Get the timer registers update condition.
+ * @rmtoll MCR BRSTDMA LL_HRTIM_TIM_GetUpdateGating\n
+ * TIMxCR UPDGAT LL_HRTIM_TIM_GetUpdateGating
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval UpdateGating Returned value can be one of the following values:
+ *
+ * For the master timer this parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
+ * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
+ * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
+ *
+ * For the timer A..E this parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
+ * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
+ * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
+ * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1
+ * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2
+ * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3
+ * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE
+ * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE
+ * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateGating(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, REG_MASK_TAB_UPDATEGATING[iTimer]) >> REG_SHIFT_TAB_UPDATEGATING[iTimer]);
+}
+
+/**
+ * @brief Enable the push-pull mode.
+ * @rmtoll TIMxCR PSHPLL LL_HRTIM_TIM_EnablePushPullMode
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_EnablePushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_TIMCR_PSHPLL);
+}
+
+/**
+ * @brief Disable the push-pull mode.
+ * @rmtoll TIMxCR PSHPLL LL_HRTIM_TIM_DisablePushPullMode
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_DisablePushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_TIMCR_PSHPLL);
+}
+
+/**
+ * @brief Indicate whether the push-pull mode is enabled.
+ * @rmtoll TIMxCR PSHPLL LL_HRTIM_TIM_IsEnabledPushPullMode\n
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of PSHPLL bit in HRTIM_TIMxCR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMCR_PSHPLL) == HRTIM_TIMCR_PSHPLL);
+}
+
+/**
+ * @brief Set the functioning mode of the compare unit (CMP2 or CMP4 can operate in standard mode or in auto delayed mode).
+ * @rmtoll TIMxCR DELCMP2 LL_HRTIM_TIM_SetCompareMode\n
+ * TIMxCR DELCMP4 LL_HRTIM_TIM_SetCompareMode
+ * @note In auto-delayed mode the compare match occurs independently from the timer counter value.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param CompareUnit This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_COMPAREUNIT_2
+ * @arg @ref LL_HRTIM_COMPAREUNIT_4
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_COMPAREMODE_REGULAR
+ * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT
+ * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP1
+ * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP3
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_SetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit,
+ uint32_t Mode)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ register uint32_t shift = POSITION_VAL(CompareUnit) - POSITION_VAL(LL_HRTIM_COMPAREUNIT_2);
+ MODIFY_REG(* pReg, (HRTIM_TIMCR_DELCMP2 << shift), (Mode << shift));
+}
+
+/**
+ * @brief Get the functioning mode of the compare unit.
+ * @rmtoll TIMxCR DELCMP2 LL_HRTIM_TIM_GetCompareMode\n
+ * TIMxCR DELCMP4 LL_HRTIM_TIM_GetCompareMode
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param CompareUnit This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_COMPAREUNIT_2
+ * @arg @ref LL_HRTIM_COMPAREUNIT_4
+ * @retval Mode Returned value can be one of the following values:
+ * @arg @ref LL_HRTIM_COMPAREMODE_REGULAR
+ * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT
+ * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP1
+ * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP3
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ register uint32_t shift = POSITION_VAL(CompareUnit) - POSITION_VAL(LL_HRTIM_COMPAREUNIT_2);
+ return (READ_BIT(*pReg, (HRTIM_TIMCR_DELCMP2 << shift)) >> shift);
+}
+
+/**
+ * @brief Set the timer counter value.
+ * @rmtoll MCNTR MCNT LL_HRTIM_TIM_SetCounter\n
+ * CNTxR CNTx LL_HRTIM_TIM_SetCounter
+ * @note This function can only be called when the timer is stopped.
+ * @note For HR clock prescaling ratio below 32 (CKPSC[2:0] < 5), the least
+ * significant bits of the counter are not significant. They cannot be
+ * written and return 0 when read.
+ * @note The timer behavior is not guaranteed if the counter value is set above
+ * the period.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param Counter Value between 0 and 0xFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_SetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Counter)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ MODIFY_REG(* pReg, HRTIM_MCNTR_MCNTR, Counter);
+}
+
+/**
+ * @brief Get actual timer counter value.
+ * @rmtoll MCNTR MCNT LL_HRTIM_TIM_GetCounter\n
+ * CNTxR CNTx LL_HRTIM_TIM_GetCounter
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval Counter Value between 0 and 0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MCNTR_MCNTR));
+}
+
+/**
+ * @brief Set the timer period value.
+ * @rmtoll MPER MPER LL_HRTIM_TIM_SetPeriod\n
+ * PERxR PERx LL_HRTIM_TIM_SetPeriod
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param Period Value between 0 and 0xFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Period)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ MODIFY_REG(* pReg, HRTIM_MPER_MPER, Period);
+}
+
+/**
+ * @brief Get actual timer period value.
+ * @rmtoll MPER MPER LL_HRTIM_TIM_GetPeriod\n
+ * PERxR PERx LL_HRTIM_TIM_GetPeriod
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval Period Value between 0 and 0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MPER_MPER));
+}
+
+/**
+ * @brief Set the timer repetition period value.
+ * @rmtoll MREP MREP LL_HRTIM_TIM_SetRepetition\n
+ * REPxR REPx LL_HRTIM_TIM_SetRepetition
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param Repetition Value between 0 and 0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_SetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Repetition)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ MODIFY_REG(* pReg, HRTIM_MREP_MREP, Repetition);
+}
+
+/**
+ * @brief Get actual timer repetition period value.
+ * @rmtoll MREP MREP LL_HRTIM_TIM_GetRepetition\n
+ * REPxR REPx LL_HRTIM_TIM_GetRepetition
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval Repetition Value between 0 and 0xFF
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MREP_MREP));
+}
+
+/**
+ * @brief Set the compare value of the compare unit 1.
+ * @rmtoll MCMP1R MCMP1 LL_HRTIM_TIM_SetCompare1\n
+ * CMP1xR CMP1x LL_HRTIM_TIM_SetCompare1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param CompareValue Compare value must be above or equal to 3
+ * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
+ * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_SetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP1R, CompareValue);
+}
+
+/**
+ * @brief Get actual compare value of the compare unit 1.
+ * @rmtoll MCMP1R MCMP1 LL_HRTIM_TIM_GetCompare1\n
+ * CMP1xR CMP1x LL_HRTIM_TIM_GetCompare1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval CompareValue Compare value must be above or equal to 3
+ * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
+ * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP1R));
+}
+
+/**
+ * @brief Set the compare value of the compare unit 2.
+ * @rmtoll MCMP2R MCMP2 LL_HRTIM_TIM_SetCompare2\n
+ * CMP2xR CMP2x LL_HRTIM_TIM_SetCompare2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param CompareValue Compare value must be above or equal to 3
+ * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
+ * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_SetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP2R, CompareValue);
+}
+
+/**
+ * @brief Get actual compare value of the compare unit 2.
+ * @rmtoll MCMP2R MCMP2 LL_HRTIM_TIM_GetCompare2\n
+ * CMP2xR CMP2x LL_HRTIM_TIM_GetCompare2\n
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval CompareValue Compare value must be above or equal to 3
+ * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
+ * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP2R));
+}
+
+/**
+ * @brief Set the compare value of the compare unit 3.
+ * @rmtoll MCMP3R MCMP3 LL_HRTIM_TIM_SetCompare3\n
+ * CMP3xR CMP3x LL_HRTIM_TIM_SetCompare3
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param CompareValue Compare value must be above or equal to 3
+ * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
+ * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_SetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP3R, CompareValue);
+}
+
+/**
+ * @brief Get actual compare value of the compare unit 3.
+ * @rmtoll MCMP3R MCMP3 LL_HRTIM_TIM_GetCompare3\n
+ * CMP3xR CMP3x LL_HRTIM_TIM_GetCompare3
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval CompareValue Compare value must be above or equal to 3
+ * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
+ * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP3R));
+}
+
+/**
+ * @brief Set the compare value of the compare unit 4.
+ * @rmtoll MCMP4R MCMP4 LL_HRTIM_TIM_SetCompare4\n
+ * CMP4xR CMP4x LL_HRTIM_TIM_SetCompare4
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param CompareValue Compare value must be above or equal to 3
+ * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
+ * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_SetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP4R, CompareValue);
+}
+
+/**
+ * @brief Get actual compare value of the compare unit 4.
+ * @rmtoll MCMP4R MCMP4 LL_HRTIM_TIM_GetCompare4\n
+ * CMP4xR CMP4x LL_HRTIM_TIM_GetCompare4
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval CompareValue Compare value must be above or equal to 3
+ * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
+ * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP4R));
+}
+
+/**
+ * @brief Set the reset trigger of a timer counter.
+ * @rmtoll RSTxR UPDT LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR CMP2 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR CMP4 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR MSTPER LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR MSTCMP1 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR MSTCMP2 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR MSTCMP3 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR MSTCMP4 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR EXTEVNT1 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR EXTEVNT2 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR EXTEVNT3 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR EXTEVNT4 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR EXTEVNT5 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR EXTEVNT6 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR EXTEVNT7 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR EXTEVNT8 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR EXTEVNT9 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR EXTEVNT10 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR TIMBCMP1 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR TIMBCMP2 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR TIMBCMP4 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR TIMCCMP1 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR TIMCCMP2 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR TIMCCMP4 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR TIMDCMP1 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR TIMDCMP2 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR TIMDCMP4 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR TIMECMP1 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR TIMECMP2 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR TIMECMP4 LL_HRTIM_TIM_SetResetTrig
+ * @note The reset of the timer counter can be triggered by up to 30 events
+ * that can be selected among the following sources:
+ * @arg The timing unit: Compare 2, Compare 4 and Update (3 events).
+ * @arg The master timer: Reset and Compare 1..4 (5 events).
+ * @arg The external events EXTEVNT1..10 (10 events).
+ * @arg All other timing units (e.g. Timer B..E for timer A): Compare 1, 2 and 4 (12 events).
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param ResetTrig This parameter can be a combination of the following values:
+ * @arg @ref LL_HRTIM_RESETTRIG_NONE
+ * @arg @ref LL_HRTIM_RESETTRIG_UPDATE
+ * @arg @ref LL_HRTIM_RESETTRIG_CMP2
+ * @arg @ref LL_HRTIM_RESETTRIG_CMP4
+ * @arg @ref LL_HRTIM_RESETTRIG_MASTER_PER
+ * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP1
+ * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP2
+ * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP3
+ * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP4
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_1
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_2
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_3
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_4
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_5
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_6
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_7
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_8
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_9
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_10
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP1
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP2
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP4
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP1
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP2
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP4
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP1
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP2
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP4
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP1
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP2
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP4
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_SetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t ResetTrig)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ WRITE_REG(*pReg, ResetTrig);
+}
+
+/**
+ * @brief Get actual reset trigger of a timer counter.
+ * @rmtoll RSTxR UPDT LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR CMP2 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR CMP4 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR MSTPER LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR MSTCMP1 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR MSTCMP2 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR MSTCMP3 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR MSTCMP4 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR EXTEVNT1 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR EXTEVNT2 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR EXTEVNT3 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR EXTEVNT4 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR EXTEVNT5 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR EXTEVNT6 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR EXTEVNT7 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR EXTEVNT8 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR EXTEVNT9 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR EXTEVNT10 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR TIMBCMP1 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR TIMBCMP2 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR TIMBCMP4 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR TIMCCMP1 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR TIMCCMP2 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR TIMCCMP4 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR TIMDCMP1 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR TIMDCMP2 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR TIMDCMP4 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR TIMECMP1 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR TIMECMP2 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR TIMECMP4 LL_HRTIM_TIM_GetResetTrig
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval ResetTrig Returned value can be one of the following values:
+ * @arg @ref LL_HRTIM_RESETTRIG_NONE
+ * @arg @ref LL_HRTIM_RESETTRIG_UPDATE
+ * @arg @ref LL_HRTIM_RESETTRIG_CMP2
+ * @arg @ref LL_HRTIM_RESETTRIG_CMP4
+ * @arg @ref LL_HRTIM_RESETTRIG_MASTER_PER
+ * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP1
+ * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP2
+ * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP3
+ * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP4
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_1
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_2
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_3
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_4
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_5
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_6
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_7
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_8
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_9
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_10
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP1
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP2
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP4
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP1
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP2
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP4
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP1
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP2
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP4
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP1
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP2
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP4
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_REG(*pReg));
+}
+
+/**
+ * @brief Get captured value for capture unit 1.
+ * @rmtoll CPT1xR CPT1x LL_HRTIM_TIM_GetCapture1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval Captured value
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_REG(*pReg));
+}
+
+/**
+ * @brief Get captured value for capture unit 2.
+ * @rmtoll CPT2xR CPT2x LL_HRTIM_TIM_GetCapture2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval Captured value
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT2xR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_REG(*pReg));
+}
+
+/**
+ * @brief Set the trigger of a capture unit for a given timer.
+ * @rmtoll CPT1xCR SWCPT LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR UPDCPT LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR EXEV1CPT LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR EXEV2CPT LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR EXEV3CPT LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR EXEV4CPT LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR EXEV5CPT LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR EXEV6CPT LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR EXEV7CPT LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR EXEV8CPT LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR EXEV9CPT LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR EXEV10CPT LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR TA1SET LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR TA1RST LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR TACMP1 LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR TACMP2 LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR TB1SET LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR TB1RST LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR TBCMP1 LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR TBCMP2 LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR TC1SET LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR TC1RST LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR TCCMP1 LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR TCCMP2 LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR TD1SET LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR TD1RST LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR TDCMP1 LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR TDCMP2 LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR TE1SET LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR TE1RST LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR TECMP1 LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR TECMP2 LL_HRTIM_TIM_SetCaptureTrig
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param CaptureUnit This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_CAPTUREUNIT_1
+ * @arg @ref LL_HRTIM_CAPTUREUNIT_2
+ * @param CaptureTrig This parameter can be a combination of the following values:
+ * @arg @ref LL_HRTIM_CAPTURETRIG_NONE
+ * @arg @ref LL_HRTIM_CAPTURETRIG_UPDATE
+ * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_1
+ * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_2
+ * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_3
+ * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_4
+ * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_5
+ * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_6
+ * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_7
+ * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_8
+ * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_9
+ * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_10
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TA1_SET
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TA1_RESET
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP1
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP2
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TB1_SET
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TB1_RESET
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP1
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP2
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TC1_SET
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TC1_RESET
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP1
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP2
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TD1_SET
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TD1_RESET
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP1
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP2
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TE1_SET
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TE1_RESET
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP1
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP2
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_SetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit,
+ uint32_t CaptureTrig)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xCR) +
+ REG_OFFSET_TAB_TIMER[iTimer] + CaptureUnit * 4));
+ WRITE_REG(*pReg, CaptureTrig);
+}
+
+/**
+ * @brief Get actual trigger of a capture unit for a given timer.
+ * @rmtoll CPT1xCR SWCPT LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR UPDCPT LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR EXEV1CPT LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR EXEV2CPT LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR EXEV3CPT LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR EXEV4CPT LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR EXEV5CPT LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR EXEV6CPT LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR EXEV7CPT LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR EXEV8CPT LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR EXEV9CPT LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR EXEV10CPT LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR TA1SET LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR TA1RST LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR TACMP1 LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR TACMP2 LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR TB1SET LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR TB1RST LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR TBCMP1 LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR TBCMP2 LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR TC1SET LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR TC1RST LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR TCCMP1 LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR TCCMP2 LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR TD1SET LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR TD1RST LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR TDCMP1 LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR TDCMP2 LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR TE1SET LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR TE1RST LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR TECMP1 LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR TECMP2 LL_HRTIM_TIM_GetCaptureTrig
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param CaptureUnit This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_CAPTUREUNIT_1
+ * @arg @ref LL_HRTIM_CAPTUREUNIT_2
+ * @retval CaptureTrig This parameter can be a combination of the following values:
+ * @arg @ref LL_HRTIM_CAPTURETRIG_NONE
+ * @arg @ref LL_HRTIM_CAPTURETRIG_UPDATE
+ * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_1
+ * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_2
+ * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_3
+ * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_4
+ * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_5
+ * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_6
+ * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_7
+ * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_8
+ * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_9
+ * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_10
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TA1_SET
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TA1_RESET
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP1
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP2
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TB1_SET
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TB1_RESET
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP1
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP2
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TC1_SET
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TC1_RESET
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP1
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP2
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TD1_SET
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TD1_RESET
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP1
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP2
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TE1_SET
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TE1_RESET
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP1
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP2
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xCR) +
+ REG_OFFSET_TAB_TIMER[iTimer] + CaptureUnit * 4));
+ return (READ_REG(*pReg));
+}
+
+/**
+ * @brief Enable deadtime insertion for a given timer.
+ * @rmtoll OUTxR DTEN LL_HRTIM_TIM_EnableDeadTime
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_EnableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_OUTR_DTEN);
+}
+
+/**
+ * @brief Disable deadtime insertion for a given timer.
+ * @rmtoll OUTxR DTEN LL_HRTIM_TIM_DisableDeadTime
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_DisableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_OUTR_DTEN);
+}
+
+/**
+ * @brief Indicate whether deadtime insertion is enabled for a given timer.
+ * @rmtoll OUTxR DTEN LL_HRTIM_TIM_IsEnabledDeadTime
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of DTEN bit in HRTIM_OUTxR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_OUTR_DTEN) == HRTIM_OUTR_DTEN);
+}
+
+/**
+ * @brief Set the delayed protection (DLYPRT) mode.
+ * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_SetDLYPRTMode\n
+ * OUTxR DLYPRT LL_HRTIM_TIM_SetDLYPRTMode
+ * @note This function must be called prior enabling the delayed protection
+ * @note Balanced Idle mode is only available in push-pull mode
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param DLYPRTMode Delayed protection (DLYPRT) mode
+ *
+ * For timers A, B and C this parameter can be one of the following vallues:
+ * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV6
+ * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV6
+ * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV6
+ * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV6
+ * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV7
+ * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV7
+ * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV7
+ * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV7
+ *
+ * For timers D and E this parameter can be one of the following vallues:
+ * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV8
+ * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV8
+ * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV8
+ * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV8
+ * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV9
+ * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV9
+ * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV9
+ * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV9
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_SetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DLYPRTMode)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ MODIFY_REG(*pReg, HRTIM_OUTR_DLYPRT, DLYPRTMode);
+}
+
+/**
+ * @brief Get the delayed protection (DLYPRT) mode.
+ * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_GetDLYPRTMode\n
+ * OUTxR DLYPRT LL_HRTIM_TIM_GetDLYPRTMode
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval DLYPRTMode Delayed protection (DLYPRT) mode
+ *
+ * For timers A, B and C this parameter can be one of the following vallues:
+ * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV6
+ * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV6
+ * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV6
+ * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV6
+ * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV7
+ * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV7
+ * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV7
+ * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV7
+ *
+ * For timers D and E this parameter can be one of the following vallues:
+ * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV8
+ * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV8
+ * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV8
+ * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV8
+ * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV9
+ * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV9
+ * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV9
+ * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV9
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_OUTR_DLYPRT));
+}
+
+/**
+ * @brief Enable delayed protection (DLYPRT) for a given timer.
+ * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_EnableDLYPRT
+ * @note This function must not be called once the concerned timer is enabled
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_EnableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_OUTR_DLYPRTEN);
+}
+
+/**
+ * @brief Disable delayed protection (DLYPRT) for a given timer.
+ * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_DisableDLYPRT
+ * @note This function must not be called once the concerned timer is enabled
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_DisableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_OUTR_DLYPRTEN);
+}
+
+/**
+ * @brief Indicate whether delayed protection (DLYPRT) is enabled for a given timer.
+ * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_IsEnabledDLYPRT
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of DLYPRTEN bit in HRTIM_OUTxR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_OUTR_DLYPRTEN) == HRTIM_OUTR_DLYPRTEN);
+}
+
+/**
+ * @brief Enable the fault channel(s) for a given timer.
+ * @rmtoll FLTxR FLT1EN LL_HRTIM_TIM_EnableFault\n
+ * FLTxR FLT2EN LL_HRTIM_TIM_EnableFault\n
+ * FLTxR FLT3EN LL_HRTIM_TIM_EnableFault\n
+ * FLTxR FLT4EN LL_HRTIM_TIM_EnableFault\n
+ * FLTxR FLT5EN LL_HRTIM_TIM_EnableFault
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param Faults This parameter can be a combination of the following values:
+ * @arg @ref LL_HRTIM_FAULT_1
+ * @arg @ref LL_HRTIM_FAULT_2
+ * @arg @ref LL_HRTIM_FAULT_3
+ * @arg @ref LL_HRTIM_FAULT_4
+ * @arg @ref LL_HRTIM_FAULT_5
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_EnableFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Faults)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, Faults);
+}
+
+/**
+ * @brief Disable the fault channel(s) for a given timer.
+ * @rmtoll FLTxR FLT1EN LL_HRTIM_TIM_DisableFault\n
+ * FLTxR FLT2EN LL_HRTIM_TIM_DisableFault\n
+ * FLTxR FLT3EN LL_HRTIM_TIM_DisableFault\n
+ * FLTxR FLT4EN LL_HRTIM_TIM_DisableFault\n
+ * FLTxR FLT5EN LL_HRTIM_TIM_DisableFault
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param Faults This parameter can be a combination of the following values:
+ * @arg @ref LL_HRTIM_FAULT_1
+ * @arg @ref LL_HRTIM_FAULT_2
+ * @arg @ref LL_HRTIM_FAULT_3
+ * @arg @ref LL_HRTIM_FAULT_4
+ * @arg @ref LL_HRTIM_FAULT_5
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_DisableFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Faults)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, Faults);
+}
+
+/**
+ * @brief Indicate whether the fault channel is enabled for a given timer.
+ * @rmtoll FLTxR FLT1EN LL_HRTIM_TIM_IsEnabledFault\n
+ * FLTxR FLT2EN LL_HRTIM_TIM_IsEnabledFault\n
+ * FLTxR FLT3EN LL_HRTIM_TIM_IsEnabledFault\n
+ * FLTxR FLT4EN LL_HRTIM_TIM_IsEnabledFault\n
+ * FLTxR FLT5EN LL_HRTIM_TIM_IsEnabledFault
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param Fault This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_FAULT_1
+ * @arg @ref LL_HRTIM_FAULT_2
+ * @arg @ref LL_HRTIM_FAULT_3
+ * @arg @ref LL_HRTIM_FAULT_4
+ * @arg @ref LL_HRTIM_FAULT_5
+ * @retval State of FLTxEN bit in HRTIM_FLTxR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Fault)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, Fault) == (Fault));
+}
+
+/**
+ * @brief Lock the fault conditioning set-up for a given timer.
+ * @rmtoll FLTxR FLTLCK LL_HRTIM_TIM_LockFault
+ * @note Timer fault-related set-up is frozen until the next HRTIM or system reset
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_LockFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_FLTR_FLTLCK);
+}
+
+/**
+ * @brief Define how the timer behaves during a burst mode operation.
+ * @rmtoll BMCR MTBM LL_HRTIM_TIM_SetBurstModeOption\n
+ * BMCR TABM LL_HRTIM_TIM_SetBurstModeOption\n
+ * BMCR TBBM LL_HRTIM_TIM_SetBurstModeOption\n
+ * BMCR TCBM LL_HRTIM_TIM_SetBurstModeOption\n
+ * BMCR TDBM LL_HRTIM_TIM_SetBurstModeOption\n
+ * BMCR TEBM LL_HRTIM_TIM_SetBurstModeOption
+ * @note This function must not be called when the burst mode is enabled
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param BurtsModeOption This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_BURSTMODE_MAINTAINCLOCK
+ * @arg @ref LL_HRTIM_BURSTMODE_RESETCOUNTER
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_SetBurstModeOption(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t BurtsModeOption)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ MODIFY_REG(HRTIMx->sCommonRegs.BMCR, Timer, BurtsModeOption << iTimer);
+}
+
+/**
+ * @brief Retrieve how the timer behaves during a burst mode operation.
+ * @rmtoll BMCR MCR LL_HRTIM_TIM_GetBurstModeOption\n
+ * BMCR TABM LL_HRTIM_TIM_GetBurstModeOption\n
+ * BMCR TBBM LL_HRTIM_TIM_GetBurstModeOption\n
+ * BMCR TCBM LL_HRTIM_TIM_GetBurstModeOption\n
+ * BMCR TDBM LL_HRTIM_TIM_GetBurstModeOption\n
+ * BMCR TEBM LL_HRTIM_TIM_GetBurstModeOption
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval BurtsMode This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_BURSTMODE_MAINTAINCLOCK
+ * @arg @ref LL_HRTIM_BURSTMODE_RESETCOUNTER
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetBurstModeOption(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ return (READ_BIT(HRTIMx->sCommonRegs.BMCR, Timer) >> iTimer);
+}
+
+/**
+ * @brief Program which registers are to be written by Burst DMA transfers.
+ * @rmtoll BDMUPDR MTBM LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDMUPDR MICR LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDMUPDR MDIER LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDMUPDR MCNT LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDMUPDR MPER LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDMUPDR MREP LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDMUPDR MCMP1 LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDMUPDR MCMP2 LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDMUPDR MCMP3 LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDMUPDR MCMP4 LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDTxUPDR TIMxCR LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDTxUPDR TIMxICR LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDTxUPDR TIMxDIER LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDTxUPDR TIMxCNT LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDTxUPDR TIMxPER LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDTxUPDR TIMxREP LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDTxUPDR TIMxCMP1 LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDTxUPDR TIMxCMP2 LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDTxUPDR TIMxCMP3 LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDTxUPDR TIMxCMP4 LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDTxUPDR TIMxDTR LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDTxUPDR TIMxSET1R LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDTxUPDR TIMxRST1R LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDTxUPDR TIMxSET2R LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDTxUPDR TIMxRST2R LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDTxUPDR TIAEEFR1 LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDTxUPDR TIMxEEFR2 LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDTxUPDR TIMxRSTR LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDTxUPDR TIMxOUTR LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDTxUPDR TIMxLTCH LL_HRTIM_TIM_ConfigBurstDMA
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param Registers Registers to be updated by the DMA request
+ *
+ * For Master timer this parameter can be can be a combination of the following values:
+ * @arg @ref LL_HRTIM_BURSTDMA_NONE
+ * @arg @ref LL_HRTIM_BURSTDMA_MCR
+ * @arg @ref LL_HRTIM_BURSTDMA_MICR
+ * @arg @ref LL_HRTIM_BURSTDMA_MDIER
+ * @arg @ref LL_HRTIM_BURSTDMA_MCNT
+ * @arg @ref LL_HRTIM_BURSTDMA_MPER
+ * @arg @ref LL_HRTIM_BURSTDMA_MREP
+ * @arg @ref LL_HRTIM_BURSTDMA_MCMP1
+ * @arg @ref LL_HRTIM_BURSTDMA_MCMP2
+ * @arg @ref LL_HRTIM_BURSTDMA_MCMP3
+ * @arg @ref LL_HRTIM_BURSTDMA_MCMP4
+ *
+ * For Timers A..E this parameter can be can be a combination of the following values:
+ * @arg @ref LL_HRTIM_BURSTDMA_NONE
+ * @arg @ref LL_HRTIM_BURSTDMA_TIMMCR
+ * @arg @ref LL_HRTIM_BURSTDMA_TIMICR
+ * @arg @ref LL_HRTIM_BURSTDMA_TIMDIER
+ * @arg @ref LL_HRTIM_BURSTDMA_TIMCNT
+ * @arg @ref LL_HRTIM_BURSTDMA_TIMPER
+ * @arg @ref LL_HRTIM_BURSTDMA_TIMREP
+ * @arg @ref LL_HRTIM_BURSTDMA_TIMCMP1
+ * @arg @ref LL_HRTIM_BURSTDMA_TIMCMP2
+ * @arg @ref LL_HRTIM_BURSTDMA_TIMCMP3
+ * @arg @ref LL_HRTIM_BURSTDMA_TIMCMP4
+ * @arg @ref LL_HRTIM_BURSTDMA_TIMDTR
+ * @arg @ref LL_HRTIM_BURSTDMA_TIMSET1R
+ * @arg @ref LL_HRTIM_BURSTDMA_TIMRST1R
+ * @arg @ref LL_HRTIM_BURSTDMA_TIMSET2R
+ * @arg @ref LL_HRTIM_BURSTDMA_TIMRST2R
+ * @arg @ref LL_HRTIM_BURSTDMA_TIMEEFR1
+ * @arg @ref LL_HRTIM_BURSTDMA_TIMEEFR2
+ * @arg @ref LL_HRTIM_BURSTDMA_TIMRSTR
+ * @arg @ref LL_HRTIM_BURSTDMA_TIMCHPR
+ * @arg @ref LL_HRTIM_BURSTDMA_TIMOUTR
+ * @arg @ref LL_HRTIM_BURSTDMA_TIMFLTR
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_ConfigBurstDMA(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Registers)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.BDMUPR) + 4 * iTimer));
+ WRITE_REG(*pReg, Registers);
+}
+
+/**
+ * @brief Indicate on which output the signal is currently applied.
+ * @rmtoll TIMxISR CPPSTAT LL_HRTIM_TIM_GetCurrentPushPullStatus
+ * @note Only significant when the timer operates in push-pull mode.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval CPPSTAT This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_CPPSTAT_OUTPUT1
+ * @arg @ref LL_HRTIM_CPPSTAT_OUTPUT2
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCurrentPushPullStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMISR_CPPSTAT));
+}
+
+/**
+ * @brief Indicate on which output the signal was applied, in push-pull mode, balanced fault mode or delayed idle mode, when the protection was triggered.
+ * @rmtoll TIMxISR IPPSTAT LL_HRTIM_TIM_GetIdlePushPullStatus
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval IPPSTAT This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_IPPSTAT_OUTPUT1
+ * @arg @ref LL_HRTIM_IPPSTAT_OUTPUT2
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetIdlePushPullStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMISR_IPPSTAT));
+}
+
+/**
+ * @brief Set the event filter for a given timer.
+ * @rmtoll EEFxR1 EE1LTCH LL_HRTIM_TIM_SetEventFilter\n
+ * EEFxR1 EE2LTCH LL_HRTIM_TIM_SetEventFilter\n
+ * EEFxR1 EE3LTCH LL_HRTIM_TIM_SetEventFilter\n
+ * EEFxR1 EE4LTCH LL_HRTIM_TIM_SetEventFilter\n
+ * EEFxR1 EE5LTCH LL_HRTIM_TIM_SetEventFilter\n
+ * EEFxR2 EE6LTCH LL_HRTIM_TIM_SetEventFilter\n
+ * EEFxR2 EE7LTCH LL_HRTIM_TIM_SetEventFilter\n
+ * EEFxR2 EE8LTCH LL_HRTIM_TIM_SetEventFilter\n
+ * EEFxR2 EE9LTCH LL_HRTIM_TIM_SetEventFilter\n
+ * EEFxR2 EE10LTCH LL_HRTIM_TIM_SetEventFilter
+ * @note This function must not be called when the timer counter is enabled.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param Event This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EVENT_1
+ * @arg @ref LL_HRTIM_EVENT_2
+ * @arg @ref LL_HRTIM_EVENT_3
+ * @arg @ref LL_HRTIM_EVENT_4
+ * @arg @ref LL_HRTIM_EVENT_5
+ * @arg @ref LL_HRTIM_EVENT_6
+ * @arg @ref LL_HRTIM_EVENT_7
+ * @arg @ref LL_HRTIM_EVENT_8
+ * @arg @ref LL_HRTIM_EVENT_9
+ * @arg @ref LL_HRTIM_EVENT_10
+ * @param Filter This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EEFLTR_NONE
+ * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP1
+ * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP2
+ * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP3
+ * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP4
+ * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR1
+ * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR2
+ * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR3
+ * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR4
+ * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR5
+ * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR6
+ * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR7
+ * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR8
+ * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP2
+ * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP3
+ * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGTIM
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_SetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event, uint32_t Filter)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+ register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
+ REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
+ MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1FLTR << REG_SHIFT_TAB_EExSRC[iEvent]), (Filter << REG_SHIFT_TAB_EExSRC[iEvent]));
+}
+
+/**
+ * @brief Get actual event filter settings for a given timer.
+ * @rmtoll EEFxR1 EE1FLTR LL_HRTIM_TIM_GetEventFilter\n
+ * EEFxR1 EE2FLTR LL_HRTIM_TIM_GetEventFilter\n
+ * EEFxR1 EE3FLTR LL_HRTIM_TIM_GetEventFilter\n
+ * EEFxR1 EE4FLTR LL_HRTIM_TIM_GetEventFilter\n
+ * EEFxR1 EE5FLTR LL_HRTIM_TIM_GetEventFilter\n
+ * EEFxR2 EE6FLTR LL_HRTIM_TIM_GetEventFilter\n
+ * EEFxR2 EE7FLTR LL_HRTIM_TIM_GetEventFilter\n
+ * EEFxR2 EE8FLTR LL_HRTIM_TIM_GetEventFilter\n
+ * EEFxR2 EE9FLTR LL_HRTIM_TIM_GetEventFilter\n
+ * EEFxR2 EE10FLTR LL_HRTIM_TIM_GetEventFilter
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param Event This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EVENT_1
+ * @arg @ref LL_HRTIM_EVENT_2
+ * @arg @ref LL_HRTIM_EVENT_3
+ * @arg @ref LL_HRTIM_EVENT_4
+ * @arg @ref LL_HRTIM_EVENT_5
+ * @arg @ref LL_HRTIM_EVENT_6
+ * @arg @ref LL_HRTIM_EVENT_7
+ * @arg @ref LL_HRTIM_EVENT_8
+ * @arg @ref LL_HRTIM_EVENT_9
+ * @arg @ref LL_HRTIM_EVENT_10
+ * @retval Filter This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EEFLTR_NONE
+ * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP1
+ * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP2
+ * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP3
+ * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP4
+ * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR1
+ * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR2
+ * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR3
+ * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR4
+ * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR5
+ * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR6
+ * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR7
+ * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR8
+ * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP2
+ * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP3
+ * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGTIM
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+ register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
+ REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
+ return (READ_BIT(*pReg, HRTIM_EEFR1_EE1FLTR << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
+}
+
+/**
+ * @brief Enable or disable event latch mechanism for a given timer.
+ * @rmtoll EEFxR1 EE1LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
+ * EEFxR1 EE2LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
+ * EEFxR1 EE3LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
+ * EEFxR1 EE4LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
+ * EEFxR1 EE5LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
+ * EEFxR2 EE6LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
+ * EEFxR2 EE7LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
+ * EEFxR2 EE8LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
+ * EEFxR2 EE9LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
+ * EEFxR2 EE10LTCH LL_HRTIM_TIM_SetEventLatchStatus
+ * @note This function must not be called when the timer counter is enabled.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param Event This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EVENT_1
+ * @arg @ref LL_HRTIM_EVENT_2
+ * @arg @ref LL_HRTIM_EVENT_3
+ * @arg @ref LL_HRTIM_EVENT_4
+ * @arg @ref LL_HRTIM_EVENT_5
+ * @arg @ref LL_HRTIM_EVENT_6
+ * @arg @ref LL_HRTIM_EVENT_7
+ * @arg @ref LL_HRTIM_EVENT_8
+ * @arg @ref LL_HRTIM_EVENT_9
+ * @arg @ref LL_HRTIM_EVENT_10
+ * @param LatchStatus This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EELATCH_DISABLED
+ * @arg @ref LL_HRTIM_EELATCH_ENABLED
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_SetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event,
+ uint32_t LatchStatus)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+ register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
+ REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
+ MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1LTCH << REG_SHIFT_TAB_EExSRC[iEvent]), (LatchStatus << REG_SHIFT_TAB_EExSRC[iEvent]));
+}
+
+/**
+ * @brief Get actual event latch status for a given timer.
+ * @rmtoll EEFxR1 EE1LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
+ * EEFxR1 EE2LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
+ * EEFxR1 EE3LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
+ * EEFxR1 EE4LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
+ * EEFxR1 EE5LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
+ * EEFxR2 EE6LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
+ * EEFxR2 EE7LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
+ * EEFxR2 EE8LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
+ * EEFxR2 EE9LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
+ * EEFxR2 EE10LTCH LL_HRTIM_TIM_GetEventLatchStatus
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param Event This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EVENT_1
+ * @arg @ref LL_HRTIM_EVENT_2
+ * @arg @ref LL_HRTIM_EVENT_3
+ * @arg @ref LL_HRTIM_EVENT_4
+ * @arg @ref LL_HRTIM_EVENT_5
+ * @arg @ref LL_HRTIM_EVENT_6
+ * @arg @ref LL_HRTIM_EVENT_7
+ * @arg @ref LL_HRTIM_EVENT_8
+ * @arg @ref LL_HRTIM_EVENT_9
+ * @arg @ref LL_HRTIM_EVENT_10
+ * @retval LatchStatus This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EELATCH_DISABLED
+ * @arg @ref LL_HRTIM_EELATCH_ENABLED
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+ register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
+ REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
+ return (READ_BIT(*pReg, HRTIM_EEFR1_EE1LTCH << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EF_Dead_Time_Configuration Dead_Time_Configuration
+ * @{
+ */
+
+/**
+ * @brief Configure the dead time insertion feature for a given timer.
+ * @rmtoll DTxR DTPRSC LL_HRTIM_DT_Config\n
+ * DTxR SDTF LL_HRTIM_DT_Config\n
+ * DTxR SDRT LL_HRTIM_DT_Config
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param Configuration This parameter must be a combination of all the following values:
+ * @arg @ref LL_HRTIM_DT_PRESCALER_MUL8 or ... or @ref LL_HRTIM_DT_PRESCALER_DIV16
+ * @arg @ref LL_HRTIM_DT_RISING_POSITIVE or @ref LL_HRTIM_DT_RISING_NEGATIVE
+ * @arg @ref LL_HRTIM_DT_FALLING_POSITIVE or @ref LL_HRTIM_DT_FALLING_NEGATIVE
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Configuration)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ MODIFY_REG(*pReg, HRTIM_DTR_SDTF | HRTIM_DTR_DTPRSC | HRTIM_DTR_SDTR, Configuration);
+}
+
+/**
+ * @brief Set the deadtime prescaler value.
+ * @rmtoll DTxR DTPRSC LL_HRTIM_DT_SetPrescaler
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_DT_PRESCALER_MUL8
+ * @arg @ref LL_HRTIM_DT_PRESCALER_MUL4
+ * @arg @ref LL_HRTIM_DT_PRESCALER_MUL2
+ * @arg @ref LL_HRTIM_DT_PRESCALER_DIV1
+ * @arg @ref LL_HRTIM_DT_PRESCALER_DIV2
+ * @arg @ref LL_HRTIM_DT_PRESCALER_DIV4
+ * @arg @ref LL_HRTIM_DT_PRESCALER_DIV8
+ * @arg @ref LL_HRTIM_DT_PRESCALER_DIV16
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ MODIFY_REG(*pReg, HRTIM_DTR_DTPRSC, Prescaler);
+}
+
+/**
+ * @brief Get actual deadtime prescaler value.
+ * @rmtoll DTxR DTPRSC LL_HRTIM_DT_GetPrescaler
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_DT_PRESCALER_MUL8
+ * @arg @ref LL_HRTIM_DT_PRESCALER_MUL4
+ * @arg @ref LL_HRTIM_DT_PRESCALER_MUL2
+ * @arg @ref LL_HRTIM_DT_PRESCALER_DIV1
+ * @arg @ref LL_HRTIM_DT_PRESCALER_DIV2
+ * @arg @ref LL_HRTIM_DT_PRESCALER_DIV4
+ * @arg @ref LL_HRTIM_DT_PRESCALER_DIV8
+ * @arg @ref LL_HRTIM_DT_PRESCALER_DIV16
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_DT_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_DTR_DTPRSC));
+}
+
+/**
+ * @brief Set the deadtime rising value.
+ * @rmtoll DTxR DTR LL_HRTIM_DT_SetRisingValue
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param RisingValue Value between 0 and 0x1FF
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DT_SetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t RisingValue)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ MODIFY_REG(*pReg, HRTIM_DTR_DTR, RisingValue);
+}
+
+/**
+ * @brief Get actual deadtime rising value.
+ * @rmtoll DTxR DTR LL_HRTIM_DT_GetRisingValue
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval RisingValue Value between 0 and 0x1FF
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_DTR_DTR));
+}
+
+/**
+ * @brief Set the deadtime sign on rising edge.
+ * @rmtoll DTxR SDTR LL_HRTIM_DT_SetRisingSign
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param RisingSign This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_DT_RISING_POSITIVE
+ * @arg @ref LL_HRTIM_DT_RISING_NEGATIVE
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DT_SetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t RisingSign)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ MODIFY_REG(*pReg, HRTIM_DTR_SDTR, RisingSign);
+}
+
+/**
+ * @brief Get actual deadtime sign on rising edge.
+ * @rmtoll DTxR SDTR LL_HRTIM_DT_GetRisingSign
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval RisingSign This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_DT_RISING_POSITIVE
+ * @arg @ref LL_HRTIM_DT_RISING_NEGATIVE
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_DTR_SDTR));
+}
+
+/**
+ * @brief Set the deadime falling value.
+ * @rmtoll DTxR DTF LL_HRTIM_DT_SetFallingValue
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param FallingValue Value between 0 and 0x1FF
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DT_SetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t FallingValue)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ MODIFY_REG(*pReg, HRTIM_DTR_DTF, FallingValue << HRTIM_DTR_DTF_Pos);
+}
+
+/**
+ * @brief Get actual deadtime falling value
+ * @rmtoll DTxR DTF LL_HRTIM_DT_GetFallingValue
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval FallingValue Value between 0 and 0x1FF
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return ((READ_BIT(*pReg, HRTIM_DTR_DTF)) >> HRTIM_DTR_DTF_Pos);
+}
+
+/**
+ * @brief Set the deadtime sign on falling edge.
+ * @rmtoll DTxR SDTF LL_HRTIM_DT_SetFallingSign
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param FallingSign This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_DT_FALLING_POSITIVE
+ * @arg @ref LL_HRTIM_DT_FALLING_NEGATIVE
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DT_SetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t FallingSign)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ MODIFY_REG(*pReg, HRTIM_DTR_SDTF, FallingSign);
+}
+
+/**
+ * @brief Get actual deadtime sign on falling edge.
+ * @rmtoll DTxR SDTF LL_HRTIM_DT_GetFallingSign
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval FallingSign This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_DT_FALLING_POSITIVE
+ * @arg @ref LL_HRTIM_DT_FALLING_NEGATIVE
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_DTR_SDTF));
+}
+
+/**
+ * @brief Lock the deadtime value and sign on rising edge.
+ * @rmtoll DTxR DTRLK LL_HRTIM_DT_LockRising
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DT_LockRising(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_DTR_DTRLK);
+}
+
+/**
+ * @brief Lock the deadtime sign on rising edge.
+ * @rmtoll DTxR DTRSLK LL_HRTIM_DT_LockRisingSign
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DT_LockRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_DTR_DTRSLK);
+}
+
+/**
+ * @brief Lock the deadtime value and sign on falling edge.
+ * @rmtoll DTxR DTFLK LL_HRTIM_DT_LockFalling
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DT_LockFalling(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_DTR_DTFLK);
+}
+
+/**
+ * @brief Lock the deadtime sign on falling edge.
+ * @rmtoll DTxR DTFSLK LL_HRTIM_DT_LockFallingSign
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DT_LockFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_DTR_DTFSLK);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EF_Chopper_Mode_Configuration Chopper_Mode_Configuration
+ * @{
+ */
+
+/**
+ * @brief Configure the chopper stage for a given timer.
+ * @rmtoll CHPxR CARFRQ LL_HRTIM_CHP_Config\n
+ * CHPxR CARDTY LL_HRTIM_CHP_Config\n
+ * CHPxR STRTPW LL_HRTIM_CHP_Config
+ * @note This function must not be called if the chopper mode is already
+ * enabled for one of the timer outputs.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param Configuration This parameter must be a combination of all the following values:
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16 or ... or @ref LL_HRTIM_CHP_PRESCALER_DIV256
+ * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0 or ... or @ref LL_HRTIM_CHP_DUTYCYCLE_875
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16 or ... or @ref LL_HRTIM_CHP_PULSEWIDTH_256
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_CHP_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Configuration)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ MODIFY_REG(*pReg, HRTIM_CHPR_STRPW | HRTIM_CHPR_CARDTY | HRTIM_CHPR_CARFRQ, Configuration);
+}
+
+/**
+ * @brief Set prescaler determining the carrier frequency to be added on top
+ * of the timer output signals when chopper mode is enabled.
+ * @rmtoll CHPxR CARFRQ LL_HRTIM_CHP_SetPrescaler
+ * @note This function must not be called if the chopper mode is already
+ * enabled for one of the timer outputs.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV32
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV48
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV64
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV80
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV96
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV112
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV128
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV144
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV160
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV176
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV192
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV208
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV224
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV240
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV256
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_CHP_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ MODIFY_REG(*pReg, HRTIM_CHPR_CARFRQ, Prescaler);
+}
+
+/**
+ * @brief Get actual chopper stage prescaler value.
+ * @rmtoll CHPxR CARFRQ LL_HRTIM_CHP_GetPrescaler
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV32
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV48
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV64
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV80
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV96
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV112
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV128
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV144
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV160
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV176
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV192
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV208
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV224
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV240
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV256
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_CHPR_CARFRQ));
+}
+
+/**
+ * @brief Set the chopper duty cycle.
+ * @rmtoll CHPxR CARDTY LL_HRTIM_CHP_SetDutyCycle
+ * @note Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8)
+ * @note This function must not be called if the chopper mode is already
+ * enabled for one of the timer outputs.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param DutyCycle This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0
+ * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_125
+ * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_250
+ * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_375
+ * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_500
+ * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_625
+ * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_750
+ * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_875
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_CHP_SetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DutyCycle)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ MODIFY_REG(*pReg, HRTIM_CHPR_CARDTY, DutyCycle);
+}
+
+/**
+ * @brief Get actual chopper duty cycle.
+ * @rmtoll CHPxR CARDTY LL_HRTIM_CHP_GetDutyCycle
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval DutyCycle This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0
+ * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_125
+ * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_250
+ * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_375
+ * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_500
+ * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_625
+ * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_750
+ * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_875
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_CHP_GetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_CHPR_CARDTY));
+}
+
+/**
+ * @brief Set the start pulse width.
+ * @rmtoll CHPxR STRPW LL_HRTIM_CHP_SetPulseWidth
+ * @note This function must not be called if the chopper mode is already
+ * enabled for one of the timer outputs.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param PulseWidth This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_32
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_48
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_64
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_80
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_96
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_112
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_128
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_144
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_160
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_176
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_192
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_208
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_224
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_240
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_256
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_CHP_SetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t PulseWidth)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ MODIFY_REG(*pReg, HRTIM_CHPR_STRPW, PulseWidth);
+}
+
+/**
+ * @brief Get actual start pulse width.
+ * @rmtoll CHPxR STRPW LL_HRTIM_CHP_GetPulseWidth
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval PulseWidth This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_32
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_48
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_64
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_80
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_96
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_112
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_128
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_144
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_160
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_176
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_192
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_208
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_224
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_240
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_256
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_CHPR_STRPW));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EF_Output_Management Output_Management
+ * @{
+ */
+
+/**
+ * @brief Set the timer output set source.
+ * @rmtoll SETx1R SST LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R RESYNC LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R PER LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R CMP1 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R CMP2 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R CMP3 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R CMP4 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R MSTPER LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R MSTCMP1 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R MSTCMP2 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R MSTCMP3 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R MSTCMP4 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R EXEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R EXEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R EXEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R EXEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R EXEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R EXEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R EXEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R EXEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R EXEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R EXEVNT10 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R UPDATE LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R SST LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R RESYNC LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R PER LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R CMP1 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R CMP2 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R CMP3 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R CMP4 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R MSTPER LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R MSTCMP1 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R MSTCMP2 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R MSTCMP3 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R MSTCMP4 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R EXEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R EXEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R EXEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R EXEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R EXEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R EXEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R EXEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R EXEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R EXEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R EXEVNT10 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R UPDATE LL_HRTIM_OUT_SetOutputSetSrc
+ * @param HRTIMx High Resolution Timer instance
+ * @param Output This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @param SetSrc This parameter can be a combination of the following values:
+ * @arg @ref LL_HRTIM_CROSSBAR_NONE
+ * @arg @ref LL_HRTIM_CROSSBAR_RESYNC
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMPER
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4
+ * @arg @ref LL_HRTIM_CROSSBAR_MASTERPER
+ * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1
+ * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2
+ * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3
+ * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_1
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_2
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_3
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_4
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_5
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_6
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_7
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_8
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_9
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_10
+ * @arg @ref LL_HRTIM_CROSSBAR_UPDATE
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_OUT_SetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t SetSrc)
+{
+ register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
+ REG_OFFSET_TAB_SETxR[iOutput]));
+ WRITE_REG(*pReg, SetSrc);
+}
+
+/**
+ * @brief Get the timer output set source.
+ * @rmtoll SETx1R SST LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R RESYNC LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R PER LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R CMP1 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R CMP2 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R CMP3 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R CMP4 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R MSTPER LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R MSTCMP1 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R MSTCMP2 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R MSTCMP3 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R MSTCMP4 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R EXEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R EXEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R EXEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R EXEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R EXEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R EXEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R EXEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R EXEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R EXEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R EXEVNT10 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R UPDATE LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R SST LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R RESYNC LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R PER LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R CMP1 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R CMP2 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R CMP3 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R CMP4 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R MSTPER LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R MSTCMP1 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R MSTCMP2 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R MSTCMP3 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R MSTCMP4 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R EXEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R EXEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R EXEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R EXEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R EXEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R EXEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R EXEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R EXEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R EXEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R EXEVNT10 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R UPDATE LL_HRTIM_OUT_GetOutputSetSrc
+ * @param HRTIMx High Resolution Timer instance
+ * @param Output This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @retval SetSrc This parameter can be a combination of the following values:
+ * @arg @ref LL_HRTIM_CROSSBAR_NONE
+ * @arg @ref LL_HRTIM_CROSSBAR_RESYNC
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMPER
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4
+ * @arg @ref LL_HRTIM_CROSSBAR_MASTERPER
+ * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1
+ * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2
+ * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3
+ * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_1
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_2
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_3
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_4
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_5
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_6
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_7
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_8
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_9
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_10
+ * @arg @ref LL_HRTIM_CROSSBAR_UPDATE
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output)
+{
+ register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
+ REG_OFFSET_TAB_SETxR[iOutput]));
+ return (uint32_t) READ_REG(*pReg);
+}
+
+/**
+ * @brief Set the timer output reset source.
+ * @rmtoll RSTx1R RST LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R RESYNC LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R PER LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R CMP1 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R CMP2 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R CMP3 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R CMP4 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R MSTPER LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R MSTCMP1 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R MSTCMP2 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R MSTCMP3 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R MSTCMP4 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R EXEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R EXEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R EXEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R EXEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R EXEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R EXEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R EXEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R EXEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R EXEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R EXEVNT10 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R UPDATE LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R RST LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R RESYNC LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R PER LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R CMP1 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R CMP2 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R CMP3 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R CMP4 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R MSTPER LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R MSTCMP1 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R MSTCMP2 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R MSTCMP3 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R MSTCMP4 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R EXEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R EXEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R EXEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R EXEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R EXEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R EXEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R EXEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R EXEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R EXEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R EXEVNT10 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R UPDATE LL_HRTIM_OUT_SetOutputResetSrc
+ * @param HRTIMx High Resolution Timer instance
+ * @param Output This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @param ResetSrc This parameter can be a combination of the following values:
+ * @arg @ref LL_HRTIM_CROSSBAR_NONE
+ * @arg @ref LL_HRTIM_CROSSBAR_RESYNC
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMPER
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4
+ * @arg @ref LL_HRTIM_CROSSBAR_MASTERPER
+ * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1
+ * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2
+ * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3
+ * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_1
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_2
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_3
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_4
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_5
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_6
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_7
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_8
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_9
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_10
+ * @arg @ref LL_HRTIM_CROSSBAR_UPDATE
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_OUT_SetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t ResetSrc)
+{
+ register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) +
+ REG_OFFSET_TAB_SETxR[iOutput]));
+ WRITE_REG(*pReg, ResetSrc);
+}
+
+/**
+ * @brief Get the timer output set source.
+ * @rmtoll RSTx1R RST LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R RESYNC LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R PER LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R CMP1 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R CMP2 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R CMP3 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R CMP4 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R MSTPER LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R MSTCMP1 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R MSTCMP2 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R MSTCMP3 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R MSTCMP4 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R EXEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R EXEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R EXEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R EXEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R EXEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R EXEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R EXEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R EXEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R EXEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R EXEVNT10 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R UPDATE LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R RST LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R RESYNC LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R PER LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R CMP1 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R CMP2 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R CMP3 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R CMP4 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R MSTPER LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R MSTCMP1 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R MSTCMP2 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R MSTCMP3 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R MSTCMP4 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R EXEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R EXEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R EXEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R EXEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R EXEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R EXEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R EXEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R EXEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R EXEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R EXEVNT10 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R UPDATE LL_HRTIM_OUT_GetOutputResetSrc
+ * @param HRTIMx High Resolution Timer instance
+ * @param Output This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @retval ResetSrc This parameter can be a combination of the following values:
+ * @arg @ref LL_HRTIM_CROSSBAR_NONE
+ * @arg @ref LL_HRTIM_CROSSBAR_RESYNC
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMPER
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4
+ * @arg @ref LL_HRTIM_CROSSBAR_MASTERPER
+ * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1
+ * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2
+ * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3
+ * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_1
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_2
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_3
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_4
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_5
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_6
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_7
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_8
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_9
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_10
+ * @arg @ref LL_HRTIM_CROSSBAR_UPDATE
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output)
+{
+ register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) +
+ REG_OFFSET_TAB_SETxR[iOutput]));
+ return (uint32_t) READ_REG(*pReg);
+}
+
+/**
+ * @brief Configure a timer output.
+ * @rmtoll OUTxR POL1 LL_HRTIM_OUT_Config\n
+ * OUTxR IDLEM1 LL_HRTIM_OUT_Config\n
+ * OUTxR IDLES1 LL_HRTIM_OUT_Config\n
+ * OUTxR FAULT1 LL_HRTIM_OUT_Config\n
+ * OUTxR CHP1 LL_HRTIM_OUT_Config\n
+ * OUTxR DIDL1 LL_HRTIM_OUT_Config\n
+ * OUTxR POL2 LL_HRTIM_OUT_Config\n
+ * OUTxR IDLEM2 LL_HRTIM_OUT_Config\n
+ * OUTxR IDLES2 LL_HRTIM_OUT_Config\n
+ * OUTxR FAULT2 LL_HRTIM_OUT_Config\n
+ * OUTxR CHP2 LL_HRTIM_OUT_Config\n
+ * OUTxR DIDL2 LL_HRTIM_OUT_Config
+ * @param HRTIMx High Resolution Timer instance
+ * @param Output This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @param Configuration This parameter must be a combination of all the following values:
+ * @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY or @ref LL_HRTIM_OUT_NEGATIVE_POLARITY
+ * @arg @ref LL_HRTIM_OUT_NO_IDLE or @ref LL_HRTIM_OUT_IDLE_WHEN_BURST
+ * @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE or @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE
+ * @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION or @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE or @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE or @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ
+ * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED or @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED
+ * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR or @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_OUT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t Configuration)
+{
+ register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ REG_OFFSET_TAB_OUTxR[iOutput]));
+ MODIFY_REG(*pReg, (HRTIM_OUT_CONFIG_MASK << REG_SHIFT_TAB_OUTxR[iOutput]),
+ (Configuration << REG_SHIFT_TAB_OUTxR[iOutput]));
+}
+
+/**
+ * @brief Set the polarity of a timer output.
+ * @rmtoll OUTxR POL1 LL_HRTIM_OUT_SetPolarity\n
+ * OUTxR POL2 LL_HRTIM_OUT_SetPolarity
+ * @param HRTIMx High Resolution Timer instance
+ * @param Output This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY
+ * @arg @ref LL_HRTIM_OUT_NEGATIVE_POLARITY
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_OUT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t Polarity)
+{
+ register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ REG_OFFSET_TAB_OUTxR[iOutput]));
+ MODIFY_REG(*pReg, (HRTIM_OUTR_POL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (Polarity << REG_SHIFT_TAB_OUTxR[iOutput]));
+}
+
+/**
+ * @brief Get actual polarity of the timer output.
+ * @rmtoll OUTxR POL1 LL_HRTIM_OUT_GetPolarity\n
+ * OUTxR POL2 LL_HRTIM_OUT_GetPolarity
+ * @param HRTIMx High Resolution Timer instance
+ * @param Output This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @retval Polarity This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY
+ * @arg @ref LL_HRTIM_OUT_NEGATIVE_POLARITY
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Output)
+{
+ register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ REG_OFFSET_TAB_OUTxR[iOutput]));
+ return (READ_BIT(*pReg, (HRTIM_OUTR_POL1 << REG_SHIFT_TAB_OUTxR[iOutput])) >> REG_SHIFT_TAB_OUTxR[iOutput]);
+}
+
+/**
+ * @brief Set the output IDLE mode.
+ * @rmtoll OUTxR IDLEM1 LL_HRTIM_OUT_SetIdleMode\n
+ * OUTxR IDLEM2 LL_HRTIM_OUT_SetIdleMode
+ * @note This function must not be called when the burst mode is active
+ * @param HRTIMx High Resolution Timer instance
+ * @param Output This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @param IdleMode This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUT_NO_IDLE
+ * @arg @ref LL_HRTIM_OUT_IDLE_WHEN_BURST
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_OUT_SetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t IdleMode)
+{
+ register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ REG_OFFSET_TAB_OUTxR[iOutput]));
+ MODIFY_REG(*pReg, (HRTIM_OUTR_IDLM1 << REG_SHIFT_TAB_OUTxR[iOutput]), (IdleMode << REG_SHIFT_TAB_OUTxR[iOutput]));
+}
+
+/**
+ * @brief Get actual output IDLE mode.
+ * @rmtoll OUTxR IDLEM1 LL_HRTIM_OUT_GetIdleMode\n
+ * OUTxR IDLEM2 LL_HRTIM_OUT_GetIdleMode
+ * @param HRTIMx High Resolution Timer instance
+ * @param Output This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @retval IdleMode This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUT_NO_IDLE
+ * @arg @ref LL_HRTIM_OUT_IDLE_WHEN_BURST
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Output)
+{
+ register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ REG_OFFSET_TAB_OUTxR[iOutput]));
+ return (READ_BIT(*pReg, (HRTIM_OUTR_IDLM1 << REG_SHIFT_TAB_OUTxR[iOutput])) >> REG_SHIFT_TAB_OUTxR[iOutput]);
+}
+
+/**
+ * @brief Set the output IDLE level.
+ * @rmtoll OUTxR IDLES1 LL_HRTIM_OUT_SetIdleLevel\n
+ * OUTxR IDLES2 LL_HRTIM_OUT_SetIdleLevel
+ * @note This function must be called prior enabling the timer.
+ * @note Idle level isn't relevant when the output idle mode is set to LL_HRTIM_OUT_NO_IDLE.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Output This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @param IdleLevel This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE
+ * @arg @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_OUT_SetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t IdleLevel)
+{
+ register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ REG_OFFSET_TAB_OUTxR[iOutput]));
+ MODIFY_REG(*pReg, (HRTIM_OUTR_IDLES1 << REG_SHIFT_TAB_OUTxR[iOutput]), (IdleLevel << REG_SHIFT_TAB_OUTxR[iOutput]));
+}
+
+/**
+ * @brief Get actual output IDLE level.
+ * @rmtoll OUTxR IDLES1 LL_HRTIM_OUT_GetIdleLevel\n
+ * OUTxR IDLES2 LL_HRTIM_OUT_GetIdleLevel
+ * @param HRTIMx High Resolution Timer instance
+ * @param Output This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @retval IdleLevel This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE
+ * @arg @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output)
+{
+ register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ REG_OFFSET_TAB_OUTxR[iOutput]));
+ return (READ_BIT(*pReg, (HRTIM_OUTR_IDLES1 << REG_SHIFT_TAB_OUTxR[iOutput])) >> REG_SHIFT_TAB_OUTxR[iOutput]);
+}
+
+/**
+ * @brief Set the output FAULT state.
+ * @rmtoll OUTxR FAULT1 LL_HRTIM_OUT_SetFaultState\n
+ * OUTxR FAULT2 LL_HRTIM_OUT_SetFaultState
+ * @note This function must not called when the timer is enabled and a fault
+ * channel is enabled at timer level.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Output This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @param FaultState This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION
+ * @arg @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE
+ * @arg @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE
+ * @arg @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_OUT_SetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t FaultState)
+{
+ register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ REG_OFFSET_TAB_OUTxR[iOutput]));
+ MODIFY_REG(*pReg, (HRTIM_OUTR_FAULT1 << REG_SHIFT_TAB_OUTxR[iOutput]), (FaultState << REG_SHIFT_TAB_OUTxR[iOutput]));
+}
+
+/**
+ * @brief Get actual FAULT state.
+ * @rmtoll OUTxR FAULT1 LL_HRTIM_OUT_GetFaultState\n
+ * OUTxR FAULT2 LL_HRTIM_OUT_GetFaultState
+ * @param HRTIMx High Resolution Timer instance
+ * @param Output This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @retval FaultState This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION
+ * @arg @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE
+ * @arg @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE
+ * @arg @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t Output)
+{
+ register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ REG_OFFSET_TAB_OUTxR[iOutput]));
+ return (READ_BIT(*pReg, (HRTIM_OUTR_FAULT1 << REG_SHIFT_TAB_OUTxR[iOutput])) >> REG_SHIFT_TAB_OUTxR[iOutput]);
+}
+
+/**
+ * @brief Set the output chopper mode.
+ * @rmtoll OUTxR CHP1 LL_HRTIM_OUT_SetChopperMode\n
+ * OUTxR CHP2 LL_HRTIM_OUT_SetChopperMode
+ * @note This function must not called when the timer is enabled.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Output This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @param ChopperMode This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED
+ * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_OUT_SetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t ChopperMode)
+{
+ register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ REG_OFFSET_TAB_OUTxR[iOutput]));
+ MODIFY_REG(*pReg, (HRTIM_OUTR_CHP1 << REG_SHIFT_TAB_OUTxR[iOutput]), (ChopperMode << REG_SHIFT_TAB_OUTxR[iOutput]));
+}
+
+/**
+ * @brief Get actual output chopper mode
+ * @rmtoll OUTxR CHP1 LL_HRTIM_OUT_GetChopperMode\n
+ * OUTxR CHP2 LL_HRTIM_OUT_GetChopperMode
+ * @param HRTIMx High Resolution Timer instance
+ * @param Output This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @retval ChopperMode This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED
+ * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t Output)
+{
+ register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ REG_OFFSET_TAB_OUTxR[iOutput]));
+ return (READ_BIT(*pReg, (HRTIM_OUTR_CHP1 << REG_SHIFT_TAB_OUTxR[iOutput])) >> REG_SHIFT_TAB_OUTxR[iOutput]);
+}
+
+/**
+ * @brief Set the output burst mode entry mode.
+ * @rmtoll OUTxR DIDL1 LL_HRTIM_OUT_SetBMEntryMode\n
+ * OUTxR DIDL2 LL_HRTIM_OUT_SetBMEntryMode
+ * @note This function must not called when the timer is enabled.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Output This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @param BMEntryMode This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR
+ * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_OUT_SetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t BMEntryMode)
+{
+ register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ REG_OFFSET_TAB_OUTxR[iOutput]));
+ MODIFY_REG(*pReg, (HRTIM_OUTR_DIDL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (BMEntryMode << REG_SHIFT_TAB_OUTxR[iOutput]));
+}
+
+/**
+ * @brief Get actual output burst mode entry mode.
+ * @rmtoll OUTxR DIDL1 LL_HRTIM_OUT_GetBMEntryMode\n
+ * OUTxR DIDL2 LL_HRTIM_OUT_GetBMEntryMode
+ * @param HRTIMx High Resolution Timer instance
+ * @param Output This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @retval BMEntryMode This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR
+ * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t Output)
+{
+ register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ REG_OFFSET_TAB_OUTxR[iOutput]));
+ return (READ_BIT(*pReg, (HRTIM_OUTR_DIDL1 << REG_SHIFT_TAB_OUTxR[iOutput])) >> REG_SHIFT_TAB_OUTxR[iOutput]);
+}
+
+/**
+ * @brief Get the level (active or inactive) of the designated output when the
+ * delayed protection was triggered.
+ * @rmtoll TIMxISR O1SRSR LL_HRTIM_OUT_GetDLYPRTOutStatus\n
+ * TIMxISR O2SRSR LL_HRTIM_OUT_GetDLYPRTOutStatus
+ * @param HRTIMx High Resolution Timer instance
+ * @param Output This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @retval OutputLevel This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE
+ * @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetDLYPRTOutStatus(HRTIM_TypeDef *HRTIMx, uint32_t Output)
+{
+ register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) +
+ REG_OFFSET_TAB_OUTxR[iOutput]));
+ return ((READ_BIT(*pReg, (HRTIM_TIMISR_O1STAT << REG_SHIFT_TAB_OxSTAT[iOutput])) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >>
+ HRTIM_TIMISR_O1STAT_Pos);
+}
+
+/**
+ * @brief Force the timer output to its active or inactive level.
+ * @rmtoll SETx1R SST LL_HRTIM_OUT_ForceLevel\n
+ * RSTx1R SRT LL_HRTIM_OUT_ForceLevel\n
+ * SETx2R SST LL_HRTIM_OUT_ForceLevel\n
+ * RSTx2R SRT LL_HRTIM_OUT_ForceLevel
+ * @param HRTIMx High Resolution Timer instance
+ * @param Output This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @param OutputLevel This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE
+ * @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_OUT_ForceLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t OutputLevel)
+{
+ register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
+ REG_OFFSET_TAB_SETxR[iOutput] + REG_OFFSET_TAB_OUT_LEVEL[OutputLevel]));
+ SET_BIT(*pReg, HRTIM_SET1R_SST);
+}
+
+/**
+ * @brief Get actual output level, before the output stage (chopper, polarity).
+ * @rmtoll TIMxISR O1CPY LL_HRTIM_OUT_GetLevel\n
+ * TIMxISR O2CPY LL_HRTIM_OUT_GetLevel
+ * @param HRTIMx High Resolution Timer instance
+ * @param Output This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @retval OutputLevel This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE
+ * @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output)
+{
+ register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) +
+ REG_OFFSET_TAB_OUTxR[iOutput]));
+ return ((READ_BIT(*pReg, (HRTIM_TIMISR_O1CPY << REG_SHIFT_TAB_OxSTAT[iOutput])) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >>
+ HRTIM_TIMISR_O1CPY_Pos);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EF_External_Event_management External_Event_management
+ * @{
+ */
+
+/**
+ * @brief Configure external event conditioning.
+ * @rmtoll EECR1 EE1SRC LL_HRTIM_EE_Config\n
+ * EECR1 EE1POL LL_HRTIM_EE_Config\n
+ * EECR1 EE1SNS LL_HRTIM_EE_Config\n
+ * EECR1 EE1FAST LL_HRTIM_EE_Config\n
+ * EECR1 EE2SRC LL_HRTIM_EE_Config\n
+ * EECR1 EE2POL LL_HRTIM_EE_Config\n
+ * EECR1 EE2SNS LL_HRTIM_EE_Config\n
+ * EECR1 EE2FAST LL_HRTIM_EE_Config\n
+ * EECR1 EE3SRC LL_HRTIM_EE_Config\n
+ * EECR1 EE3POL LL_HRTIM_EE_Config\n
+ * EECR1 EE3SNS LL_HRTIM_EE_Config\n
+ * EECR1 EE3FAST LL_HRTIM_EE_Config\n
+ * EECR1 EE4SRC LL_HRTIM_EE_Config\n
+ * EECR1 EE4POL LL_HRTIM_EE_Config\n
+ * EECR1 EE4SNS LL_HRTIM_EE_Config\n
+ * EECR1 EE4FAST LL_HRTIM_EE_Config\n
+ * EECR1 EE5SRC LL_HRTIM_EE_Config\n
+ * EECR1 EE5POL LL_HRTIM_EE_Config\n
+ * EECR1 EE5SNS LL_HRTIM_EE_Config\n
+ * EECR1 EE5FAST LL_HRTIM_EE_Config\n
+ * EECR2 EE6SRC LL_HRTIM_EE_Config\n
+ * EECR2 EE6POL LL_HRTIM_EE_Config\n
+ * EECR2 EE6SNS LL_HRTIM_EE_Config\n
+ * EECR2 EE6FAST LL_HRTIM_EE_Config\n
+ * EECR2 EE7SRC LL_HRTIM_EE_Config\n
+ * EECR2 EE7POL LL_HRTIM_EE_Config\n
+ * EECR2 EE7SNS LL_HRTIM_EE_Config\n
+ * EECR2 EE7FAST LL_HRTIM_EE_Config\n
+ * EECR2 EE8SRC LL_HRTIM_EE_Config\n
+ * EECR2 EE8POL LL_HRTIM_EE_Config\n
+ * EECR2 EE8SNS LL_HRTIM_EE_Config\n
+ * EECR2 EE8FAST LL_HRTIM_EE_Config\n
+ * EECR2 EE9SRC LL_HRTIM_EE_Config\n
+ * EECR2 EE9POL LL_HRTIM_EE_Config\n
+ * EECR2 EE9SNS LL_HRTIM_EE_Config\n
+ * EECR2 EE9FAST LL_HRTIM_EE_Config\n
+ * EECR2 EE10SRC LL_HRTIM_EE_Config\n
+ * EECR2 EE10POL LL_HRTIM_EE_Config\n
+ * EECR2 EE10SNS LL_HRTIM_EE_Config\n
+ * EECR2 EE10FAST LL_HRTIM_EE_Config
+ * @note This function must not be called when the timer counter is enabled.
+ * @note Event source (EExSrc1..EExSRC4) mapping depends on configured event channel.
+ * @note Fast mode is available only for LL_HRTIM_EVENT_1..5.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Event This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EVENT_1
+ * @arg @ref LL_HRTIM_EVENT_2
+ * @arg @ref LL_HRTIM_EVENT_3
+ * @arg @ref LL_HRTIM_EVENT_4
+ * @arg @ref LL_HRTIM_EVENT_5
+ * @arg @ref LL_HRTIM_EVENT_6
+ * @arg @ref LL_HRTIM_EVENT_7
+ * @arg @ref LL_HRTIM_EVENT_8
+ * @arg @ref LL_HRTIM_EVENT_9
+ * @arg @ref LL_HRTIM_EVENT_10
+ * @param Configuration This parameter must be a combination of all the following values:
+ * @arg @ref LL_HRTIM_EE_SRC_1 or @ref LL_HRTIM_EE_SRC_2 or @ref LL_HRTIM_EE_SRC_3 or @ref LL_HRTIM_EE_SRC_4
+ * @arg @ref LL_HRTIM_EE_POLARITY_HIGH or @ref LL_HRTIM_EE_POLARITY_LOW
+ * @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL or @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE or @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE or @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES
+ * @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE or @ref LL_HRTIM_EE_FASTMODE_ENABLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EE_Config(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Configuration)
+{
+ register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
+ REG_OFFSET_TAB_EECR[iEvent]));
+ MODIFY_REG(*pReg, (HRTIM_EE_CONFIG_MASK << REG_SHIFT_TAB_EExSRC[iEvent]),
+ (Configuration << REG_SHIFT_TAB_EExSRC[iEvent]));
+}
+
+/**
+ * @brief Set the external event source.
+ * @rmtoll EECR1 EE1SRC LL_HRTIM_EE_SetSrc\n
+ * EECR1 EE2SRC LL_HRTIM_EE_SetSrc\n
+ * EECR1 EE3SRC LL_HRTIM_EE_SetSrc\n
+ * EECR1 EE4SRC LL_HRTIM_EE_SetSrc\n
+ * EECR1 EE5SRC LL_HRTIM_EE_SetSrc\n
+ * EECR2 EE6SRC LL_HRTIM_EE_SetSrc\n
+ * EECR2 EE7SRC LL_HRTIM_EE_SetSrc\n
+ * EECR2 EE8SRC LL_HRTIM_EE_SetSrc\n
+ * EECR2 EE9SRC LL_HRTIM_EE_SetSrc\n
+ * EECR2 EE10SRC LL_HRTIM_EE_SetSrc
+ * @param HRTIMx High Resolution Timer instance
+ * @param Event This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EVENT_1
+ * @arg @ref LL_HRTIM_EVENT_2
+ * @arg @ref LL_HRTIM_EVENT_3
+ * @arg @ref LL_HRTIM_EVENT_4
+ * @arg @ref LL_HRTIM_EVENT_5
+ * @arg @ref LL_HRTIM_EVENT_6
+ * @arg @ref LL_HRTIM_EVENT_7
+ * @arg @ref LL_HRTIM_EVENT_8
+ * @arg @ref LL_HRTIM_EVENT_9
+ * @arg @ref LL_HRTIM_EVENT_10
+ * @param Src This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EE_SRC_1
+ * @arg @ref LL_HRTIM_EE_SRC_2
+ * @arg @ref LL_HRTIM_EE_SRC_3
+ * @arg @ref LL_HRTIM_EE_SRC_4
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EE_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Src)
+{
+ register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
+ REG_OFFSET_TAB_EECR[iEvent]));
+ MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SRC << REG_SHIFT_TAB_EExSRC[iEvent]), (Src << REG_SHIFT_TAB_EExSRC[iEvent]));
+}
+
+/**
+ * @brief Get actual external event source.
+ * @rmtoll EECR1 EE1SRC LL_HRTIM_EE_GetSrc\n
+ * EECR1 EE2SRC LL_HRTIM_EE_GetSrc\n
+ * EECR1 EE3SRC LL_HRTIM_EE_GetSrc\n
+ * EECR1 EE4SRC LL_HRTIM_EE_GetSrc\n
+ * EECR1 EE5SRC LL_HRTIM_EE_GetSrc\n
+ * EECR2 EE6SRC LL_HRTIM_EE_GetSrc\n
+ * EECR2 EE7SRC LL_HRTIM_EE_GetSrc\n
+ * EECR2 EE8SRC LL_HRTIM_EE_GetSrc\n
+ * EECR2 EE9SRC LL_HRTIM_EE_GetSrc\n
+ * EECR2 EE10SRC LL_HRTIM_EE_GetSrc
+ * @param HRTIMx High Resolution Timer instance
+ * @param Event This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EVENT_1
+ * @arg @ref LL_HRTIM_EVENT_2
+ * @arg @ref LL_HRTIM_EVENT_3
+ * @arg @ref LL_HRTIM_EVENT_4
+ * @arg @ref LL_HRTIM_EVENT_5
+ * @arg @ref LL_HRTIM_EVENT_6
+ * @arg @ref LL_HRTIM_EVENT_7
+ * @arg @ref LL_HRTIM_EVENT_8
+ * @arg @ref LL_HRTIM_EVENT_9
+ * @arg @ref LL_HRTIM_EVENT_10
+ * @retval EventSrc This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EE_SRC_1
+ * @arg @ref LL_HRTIM_EE_SRC_2
+ * @arg @ref LL_HRTIM_EE_SRC_3
+ * @arg @ref LL_HRTIM_EE_SRC_4
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_EE_GetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event)
+{
+ register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
+ REG_OFFSET_TAB_EECR[iEvent]));
+ return (READ_BIT(*pReg, HRTIM_EECR1_EE1SRC << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
+}
+
+/**
+ * @brief Set the polarity of an external event.
+ * @rmtoll EECR1 EE1POL LL_HRTIM_EE_SetPolarity\n
+ * EECR1 EE2POL LL_HRTIM_EE_SetPolarity\n
+ * EECR1 EE3POL LL_HRTIM_EE_SetPolarity\n
+ * EECR1 EE4POL LL_HRTIM_EE_SetPolarity\n
+ * EECR1 EE5POL LL_HRTIM_EE_SetPolarity\n
+ * EECR2 EE6POL LL_HRTIM_EE_SetPolarity\n
+ * EECR2 EE7POL LL_HRTIM_EE_SetPolarity\n
+ * EECR2 EE8POL LL_HRTIM_EE_SetPolarity\n
+ * EECR2 EE9POL LL_HRTIM_EE_SetPolarity\n
+ * EECR2 EE10POL LL_HRTIM_EE_SetPolarity
+ * @note This function must not be called when the timer counter is enabled.
+ * @note Event polarity is only significant when event detection is level-sensitive.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Event This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EVENT_1
+ * @arg @ref LL_HRTIM_EVENT_2
+ * @arg @ref LL_HRTIM_EVENT_3
+ * @arg @ref LL_HRTIM_EVENT_4
+ * @arg @ref LL_HRTIM_EVENT_5
+ * @arg @ref LL_HRTIM_EVENT_6
+ * @arg @ref LL_HRTIM_EVENT_7
+ * @arg @ref LL_HRTIM_EVENT_8
+ * @arg @ref LL_HRTIM_EVENT_9
+ * @arg @ref LL_HRTIM_EVENT_10
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EE_POLARITY_HIGH
+ * @arg @ref LL_HRTIM_EE_POLARITY_LOW
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EE_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Polarity)
+{
+ register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
+ REG_OFFSET_TAB_EECR[iEvent]));
+ MODIFY_REG(*pReg, (HRTIM_EECR1_EE1POL << REG_SHIFT_TAB_EExSRC[iEvent]), (Polarity << REG_SHIFT_TAB_EExSRC[iEvent]));
+}
+
+/**
+ * @brief Get actual polarity setting of an external event.
+ * @rmtoll EECR1 EE1POL LL_HRTIM_EE_GetPolarity\n
+ * EECR1 EE2POL LL_HRTIM_EE_GetPolarity\n
+ * EECR1 EE3POL LL_HRTIM_EE_GetPolarity\n
+ * EECR1 EE4POL LL_HRTIM_EE_GetPolarity\n
+ * EECR1 EE5POL LL_HRTIM_EE_GetPolarity\n
+ * EECR2 EE6POL LL_HRTIM_EE_GetPolarity\n
+ * EECR2 EE7POL LL_HRTIM_EE_GetPolarity\n
+ * EECR2 EE8POL LL_HRTIM_EE_GetPolarity\n
+ * EECR2 EE9POL LL_HRTIM_EE_GetPolarity\n
+ * EECR2 EE10POL LL_HRTIM_EE_GetPolarity
+ * @param HRTIMx High Resolution Timer instance
+ * @param Event This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EVENT_1
+ * @arg @ref LL_HRTIM_EVENT_2
+ * @arg @ref LL_HRTIM_EVENT_3
+ * @arg @ref LL_HRTIM_EVENT_4
+ * @arg @ref LL_HRTIM_EVENT_5
+ * @arg @ref LL_HRTIM_EVENT_6
+ * @arg @ref LL_HRTIM_EVENT_7
+ * @arg @ref LL_HRTIM_EVENT_8
+ * @arg @ref LL_HRTIM_EVENT_9
+ * @arg @ref LL_HRTIM_EVENT_10
+ * @retval Polarity This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EE_POLARITY_HIGH
+ * @arg @ref LL_HRTIM_EE_POLARITY_LOW
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_EE_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Event)
+{
+ register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
+ REG_OFFSET_TAB_EECR[iEvent]));
+ return (READ_BIT(*pReg, HRTIM_EECR1_EE1POL << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
+}
+
+/**
+ * @brief Set the sensitivity of an external event.
+ * @rmtoll EECR1 EE1SNS LL_HRTIM_EE_SetSensitivity\n
+ * EECR1 EE2SNS LL_HRTIM_EE_SetSensitivity\n
+ * EECR1 EE3SNS LL_HRTIM_EE_SetSensitivity\n
+ * EECR1 EE4SNS LL_HRTIM_EE_SetSensitivity\n
+ * EECR1 EE5SNS LL_HRTIM_EE_SetSensitivity\n
+ * EECR2 EE6SNS LL_HRTIM_EE_SetSensitivity\n
+ * EECR2 EE7SNS LL_HRTIM_EE_SetSensitivity\n
+ * EECR2 EE8SNS LL_HRTIM_EE_SetSensitivity\n
+ * EECR2 EE9SNS LL_HRTIM_EE_SetSensitivity\n
+ * EECR2 EE10SNS LL_HRTIM_EE_SetSensitivity
+ * @param HRTIMx High Resolution Timer instance
+ * @param Event This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EVENT_1
+ * @arg @ref LL_HRTIM_EVENT_2
+ * @arg @ref LL_HRTIM_EVENT_3
+ * @arg @ref LL_HRTIM_EVENT_4
+ * @arg @ref LL_HRTIM_EVENT_5
+ * @arg @ref LL_HRTIM_EVENT_6
+ * @arg @ref LL_HRTIM_EVENT_7
+ * @arg @ref LL_HRTIM_EVENT_8
+ * @arg @ref LL_HRTIM_EVENT_9
+ * @arg @ref LL_HRTIM_EVENT_10
+ * @param Sensitivity This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL
+ * @arg @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE
+ * @arg @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE
+ * @arg @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES
+ * @retval None
+ */
+
+__STATIC_INLINE void LL_HRTIM_EE_SetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Sensitivity)
+{
+ register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
+ REG_OFFSET_TAB_EECR[iEvent]));
+ MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SNS << REG_SHIFT_TAB_EExSRC[iEvent]), (Sensitivity << REG_SHIFT_TAB_EExSRC[iEvent]));
+}
+
+/**
+ * @brief Get actual sensitivity setting of an external event.
+ * @rmtoll EECR1 EE1SNS LL_HRTIM_EE_GetSensitivity\n
+ * EECR1 EE2SNS LL_HRTIM_EE_GetSensitivity\n
+ * EECR1 EE3SNS LL_HRTIM_EE_GetSensitivity\n
+ * EECR1 EE4SNS LL_HRTIM_EE_GetSensitivity\n
+ * EECR1 EE5SNS LL_HRTIM_EE_GetSensitivity\n
+ * EECR2 EE6SNS LL_HRTIM_EE_GetSensitivity\n
+ * EECR2 EE7SNS LL_HRTIM_EE_GetSensitivity\n
+ * EECR2 EE8SNS LL_HRTIM_EE_GetSensitivity\n
+ * EECR2 EE9SNS LL_HRTIM_EE_GetSensitivity\n
+ * EECR2 EE10SNS LL_HRTIM_EE_GetSensitivity
+ * @param HRTIMx High Resolution Timer instance
+ * @param Event This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EVENT_1
+ * @arg @ref LL_HRTIM_EVENT_2
+ * @arg @ref LL_HRTIM_EVENT_3
+ * @arg @ref LL_HRTIM_EVENT_4
+ * @arg @ref LL_HRTIM_EVENT_5
+ * @arg @ref LL_HRTIM_EVENT_6
+ * @arg @ref LL_HRTIM_EVENT_7
+ * @arg @ref LL_HRTIM_EVENT_8
+ * @arg @ref LL_HRTIM_EVENT_9
+ * @arg @ref LL_HRTIM_EVENT_10
+ * @retval Polarity This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL
+ * @arg @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE
+ * @arg @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE
+ * @arg @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_EE_GetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t Event)
+{
+ register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
+ REG_OFFSET_TAB_EECR[iEvent]));
+ return (READ_BIT(*pReg, HRTIM_EECR1_EE1SNS << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
+}
+
+/**
+ * @brief Set the fast mode of an external event.
+ * @rmtoll EECR1 EE1FAST LL_HRTIM_EE_SetFastMode\n
+ * EECR1 EE2FAST LL_HRTIM_EE_SetFastMode\n
+ * EECR1 EE3FAST LL_HRTIM_EE_SetFastMode\n
+ * EECR1 EE4FAST LL_HRTIM_EE_SetFastMode\n
+ * EECR1 EE5FAST LL_HRTIM_EE_SetFastMode\n
+ * EECR2 EE6FAST LL_HRTIM_EE_SetFastMode\n
+ * EECR2 EE7FAST LL_HRTIM_EE_SetFastMode\n
+ * EECR2 EE8FAST LL_HRTIM_EE_SetFastMode\n
+ * EECR2 EE9FAST LL_HRTIM_EE_SetFastMode\n
+ * EECR2 EE10FAST LL_HRTIM_EE_SetFastMode
+ * @note This function must not be called when the timer counter is enabled.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Event This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EVENT_1
+ * @arg @ref LL_HRTIM_EVENT_2
+ * @arg @ref LL_HRTIM_EVENT_3
+ * @arg @ref LL_HRTIM_EVENT_4
+ * @arg @ref LL_HRTIM_EVENT_5
+ * @param FastMode This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE
+ * @arg @ref LL_HRTIM_EE_FASTMODE_ENABLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EE_SetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t FastMode)
+{
+ register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
+ REG_OFFSET_TAB_EECR[iEvent]));
+ MODIFY_REG(*pReg, (HRTIM_EECR1_EE1FAST << REG_SHIFT_TAB_EExSRC[iEvent]), (FastMode << REG_SHIFT_TAB_EExSRC[iEvent]));
+}
+
+/**
+ * @brief Get actual fast mode setting of an external event.
+ * @rmtoll EECR1 EE1FAST LL_HRTIM_EE_GetFastMode\n
+ * EECR1 EE2FAST LL_HRTIM_EE_GetFastMode\n
+ * EECR1 EE3FAST LL_HRTIM_EE_GetFastMode\n
+ * EECR1 EE4FAST LL_HRTIM_EE_GetFastMode\n
+ * EECR1 EE5FAST LL_HRTIM_EE_GetFastMode\n
+ * EECR2 EE6FAST LL_HRTIM_EE_GetFastMode\n
+ * EECR2 EE7FAST LL_HRTIM_EE_GetFastMode\n
+ * EECR2 EE8FAST LL_HRTIM_EE_GetFastMode\n
+ * EECR2 EE9FAST LL_HRTIM_EE_GetFastMode\n
+ * EECR2 EE10FAST LL_HRTIM_EE_GetFastMode
+ * @param HRTIMx High Resolution Timer instance
+ * @param Event This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EVENT_1
+ * @arg @ref LL_HRTIM_EVENT_2
+ * @arg @ref LL_HRTIM_EVENT_3
+ * @arg @ref LL_HRTIM_EVENT_4
+ * @arg @ref LL_HRTIM_EVENT_5
+ * @retval FastMode This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE
+ * @arg @ref LL_HRTIM_EE_FASTMODE_ENABLE
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_EE_GetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Event)
+{
+ register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
+ REG_OFFSET_TAB_EECR[iEvent]));
+ return (READ_BIT(*pReg, HRTIM_EECR1_EE1FAST << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
+}
+
+/**
+ * @brief Set the digital noise filter of a external event.
+ * @rmtoll EECR3 EE6F LL_HRTIM_EE_SetFilter\n
+ * EECR3 EE7F LL_HRTIM_EE_SetFilter\n
+ * EECR3 EE8F LL_HRTIM_EE_SetFilter\n
+ * EECR3 EE9F LL_HRTIM_EE_SetFilter\n
+ * EECR3 EE10F LL_HRTIM_EE_SetFilter
+ * @param HRTIMx High Resolution Timer instance
+ * @param Event This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EVENT_6
+ * @arg @ref LL_HRTIM_EVENT_7
+ * @arg @ref LL_HRTIM_EVENT_8
+ * @arg @ref LL_HRTIM_EVENT_9
+ * @arg @ref LL_HRTIM_EVENT_10
+ * @param Filter This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EE_FILTER_NONE
+ * @arg @ref LL_HRTIM_EE_FILTER_1
+ * @arg @ref LL_HRTIM_EE_FILTER_2
+ * @arg @ref LL_HRTIM_EE_FILTER_3
+ * @arg @ref LL_HRTIM_EE_FILTER_4
+ * @arg @ref LL_HRTIM_EE_FILTER_5
+ * @arg @ref LL_HRTIM_EE_FILTER_6
+ * @arg @ref LL_HRTIM_EE_FILTER_7
+ * @arg @ref LL_HRTIM_EE_FILTER_8
+ * @arg @ref LL_HRTIM_EE_FILTER_9
+ * @arg @ref LL_HRTIM_EE_FILTER_10
+ * @arg @ref LL_HRTIM_EE_FILTER_11
+ * @arg @ref LL_HRTIM_EE_FILTER_12
+ * @arg @ref LL_HRTIM_EE_FILTER_13
+ * @arg @ref LL_HRTIM_EE_FILTER_14
+ * @arg @ref LL_HRTIM_EE_FILTER_15
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EE_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Filter)
+{
+ register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+ MODIFY_REG(HRTIMx->sCommonRegs.EECR3, (HRTIM_EECR3_EE6F << REG_SHIFT_TAB_EExSRC[iEvent]),
+ (Filter << REG_SHIFT_TAB_EExSRC[iEvent]));
+}
+
+/**
+ * @brief Get actual digital noise filter setting of a external event.
+ * @rmtoll EECR3 EE6F LL_HRTIM_EE_GetFilter\n
+ * EECR3 EE7F LL_HRTIM_EE_GetFilter\n
+ * EECR3 EE8F LL_HRTIM_EE_GetFilter\n
+ * EECR3 EE9F LL_HRTIM_EE_GetFilter\n
+ * EECR3 EE10F LL_HRTIM_EE_GetFilter
+ * @param HRTIMx High Resolution Timer instance
+ * @param Event This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EVENT_6
+ * @arg @ref LL_HRTIM_EVENT_7
+ * @arg @ref LL_HRTIM_EVENT_8
+ * @arg @ref LL_HRTIM_EVENT_9
+ * @arg @ref LL_HRTIM_EVENT_10
+ * @retval Filter This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EE_FILTER_NONE
+ * @arg @ref LL_HRTIM_EE_FILTER_1
+ * @arg @ref LL_HRTIM_EE_FILTER_2
+ * @arg @ref LL_HRTIM_EE_FILTER_3
+ * @arg @ref LL_HRTIM_EE_FILTER_4
+ * @arg @ref LL_HRTIM_EE_FILTER_5
+ * @arg @ref LL_HRTIM_EE_FILTER_6
+ * @arg @ref LL_HRTIM_EE_FILTER_7
+ * @arg @ref LL_HRTIM_EE_FILTER_8
+ * @arg @ref LL_HRTIM_EE_FILTER_9
+ * @arg @ref LL_HRTIM_EE_FILTER_10
+ * @arg @ref LL_HRTIM_EE_FILTER_11
+ * @arg @ref LL_HRTIM_EE_FILTER_12
+ * @arg @ref LL_HRTIM_EE_FILTER_13
+ * @arg @ref LL_HRTIM_EE_FILTER_14
+ * @arg @ref LL_HRTIM_EE_FILTER_15
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_EE_GetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Event)
+{
+ register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_6));
+ return (READ_BIT(HRTIMx->sCommonRegs.EECR3,
+ (HRTIM_EECR3_EE6F << REG_SHIFT_TAB_EExSRC[iEvent])) >> REG_SHIFT_TAB_EExSRC[iEvent]);
+}
+
+/**
+ * @brief Set the external event prescaler.
+ * @rmtoll EECR3 EEVSD LL_HRTIM_EE_SetPrescaler
+ * @param HRTIMx High Resolution Timer instance
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EE_PRESCALER_DIV1
+ * @arg @ref LL_HRTIM_EE_PRESCALER_DIV2
+ * @arg @ref LL_HRTIM_EE_PRESCALER_DIV4
+ * @arg @ref LL_HRTIM_EE_PRESCALER_DIV8
+ * @retval None
+ */
+
+__STATIC_INLINE void LL_HRTIM_EE_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler)
+{
+ MODIFY_REG(HRTIMx->sCommonRegs.EECR3, HRTIM_EECR3_EEVSD, Prescaler);
+}
+
+/**
+ * @brief Get actual external event prescaler setting.
+ * @rmtoll EECR3 EEVSD LL_HRTIM_EE_GetPrescaler
+ * @param HRTIMx High Resolution Timer instance
+ * @retval Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EE_PRESCALER_DIV1
+ * @arg @ref LL_HRTIM_EE_PRESCALER_DIV2
+ * @arg @ref LL_HRTIM_EE_PRESCALER_DIV4
+ * @arg @ref LL_HRTIM_EE_PRESCALER_DIV8
+ */
+
+__STATIC_INLINE uint32_t LL_HRTIM_EE_GetPrescaler(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sCommonRegs.EECR3, HRTIM_EECR3_EEVSD));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EF_Fault_management Fault_management
+ * @{
+ */
+
+/**
+ * @brief Configure fault signal conditioning.
+ * @rmtoll FLTINR1 FLT1P LL_HRTIM_FLT_Config\n
+ * FLTINR1 FLT1SRC LL_HRTIM_FLT_Config\n
+ * FLTINR1 FLT2P LL_HRTIM_FLT_Config\n
+ * FLTINR1 FLT2SRC LL_HRTIM_FLT_Config\n
+ * FLTINR1 FLT3P LL_HRTIM_FLT_Config\n
+ * FLTINR1 FLT3SRC LL_HRTIM_FLT_Config\n
+ * FLTINR1 FLT4P LL_HRTIM_FLT_Config\n
+ * FLTINR1 FLT4SRC LL_HRTIM_FLT_Config\n
+ * FLTINR2 FLT5P LL_HRTIM_FLT_Config\n
+ * FLTINR2 FLT5SRC LL_HRTIM_FLT_Config
+ * @note This function must not be called when the fault channel is enabled.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Fault This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_FAULT_1
+ * @arg @ref LL_HRTIM_FAULT_2
+ * @arg @ref LL_HRTIM_FAULT_3
+ * @arg @ref LL_HRTIM_FAULT_4
+ * @arg @ref LL_HRTIM_FAULT_5
+ * @param Configuration This parameter must be a combination of all the following values:
+ * @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT or @ref LL_HRTIM_FLT_SRC_INTERNAL
+ * @arg @ref LL_HRTIM_FLT_POLARITY_LOW or @ref LL_HRTIM_FLT_POLARITY_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_FLT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Configuration)
+{
+ register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
+ REG_OFFSET_TAB_FLTINR[iFault]));
+ MODIFY_REG(*pReg, (HRTIM_FLT_CONFIG_MASK << REG_SHIFT_TAB_FLTxE[iFault]),
+ (Configuration << REG_SHIFT_TAB_FLTxE[iFault]));
+}
+
+/**
+ * @brief Set the source of a fault signal.
+ * @rmtoll FLTINR1 FLT1SRC LL_HRTIM_FLT_SetSrc\n
+ * FLTINR1 FLT2SRC LL_HRTIM_FLT_SetSrc\n
+ * FLTINR1 FLT3SRC LL_HRTIM_FLT_SetSrc\n
+ * FLTINR1 FLT4SRC LL_HRTIM_FLT_SetSrc\n
+ * FLTINR2 FLT5SRC LL_HRTIM_FLT_SetSrc
+ * @note This function must not be called when the fault channel is enabled.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Fault This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_FAULT_1
+ * @arg @ref LL_HRTIM_FAULT_2
+ * @arg @ref LL_HRTIM_FAULT_3
+ * @arg @ref LL_HRTIM_FAULT_4
+ * @arg @ref LL_HRTIM_FAULT_5
+ * @param Src This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT
+ * @arg @ref LL_HRTIM_FLT_SRC_INTERNAL
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_FLT_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Src)
+{
+ register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
+ REG_OFFSET_TAB_FLTINR[iFault]));
+ MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1SRC << REG_SHIFT_TAB_FLTxE[iFault]), (Src << REG_SHIFT_TAB_FLTxE[iFault]));
+}
+
+/**
+ * @brief Get actual source of a fault signal.
+ * @rmtoll FLTINR1 FLT1SRC LL_HRTIM_FLT_GetSrc\n
+ * FLTINR1 FLT2SRC LL_HRTIM_FLT_GetSrc\n
+ * FLTINR1 FLT3SRC LL_HRTIM_FLT_GetSrc\n
+ * FLTINR1 FLT4SRC LL_HRTIM_FLT_GetSrc\n
+ * FLTINR2 FLT5SRC LL_HRTIM_FLT_GetSrc
+ * @param HRTIMx High Resolution Timer instance
+ * @param Fault This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_FAULT_1
+ * @arg @ref LL_HRTIM_FAULT_2
+ * @arg @ref LL_HRTIM_FAULT_3
+ * @arg @ref LL_HRTIM_FAULT_4
+ * @arg @ref LL_HRTIM_FAULT_5
+ * @retval Src This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT
+ * @arg @ref LL_HRTIM_FLT_SRC_INTERNAL
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
+{
+ register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
+ REG_OFFSET_TAB_FLTINR[iFault]));
+ return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1SRC << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]);
+}
+
+/**
+ * @brief Set the polarity of a fault signal.
+ * @rmtoll FLTINR1 FLT1P LL_HRTIM_FLT_SetPolarity\n
+ * FLTINR1 FLT2P LL_HRTIM_FLT_SetPolarity\n
+ * FLTINR1 FLT3P LL_HRTIM_FLT_SetPolarity\n
+ * FLTINR1 FLT4P LL_HRTIM_FLT_SetPolarity\n
+ * FLTINR2 FLT5P LL_HRTIM_FLT_SetPolarity
+ * @note This function must not be called when the fault channel is enabled.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Fault This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_FAULT_1
+ * @arg @ref LL_HRTIM_FAULT_2
+ * @arg @ref LL_HRTIM_FAULT_3
+ * @arg @ref LL_HRTIM_FAULT_4
+ * @arg @ref LL_HRTIM_FAULT_5
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_FLT_POLARITY_LOW
+ * @arg @ref LL_HRTIM_FLT_POLARITY_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_FLT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Polarity)
+{
+ register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
+ REG_OFFSET_TAB_FLTINR[iFault]));
+ MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1P << REG_SHIFT_TAB_FLTxE[iFault]), (Polarity << REG_SHIFT_TAB_FLTxE[iFault]));
+}
+
+/**
+ * @brief Get actual polarity of a fault signal.
+ * @rmtoll FLTINR1 FLT1P LL_HRTIM_FLT_GetPolarity\n
+ * FLTINR1 FLT2P LL_HRTIM_FLT_GetPolarity\n
+ * FLTINR1 FLT3P LL_HRTIM_FLT_GetPolarity\n
+ * FLTINR1 FLT4P LL_HRTIM_FLT_GetPolarity\n
+ * FLTINR2 FLT5P LL_HRTIM_FLT_GetPolarity
+ * @param HRTIMx High Resolution Timer instance
+ * @param Fault This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_FAULT_1
+ * @arg @ref LL_HRTIM_FAULT_2
+ * @arg @ref LL_HRTIM_FAULT_3
+ * @arg @ref LL_HRTIM_FAULT_4
+ * @arg @ref LL_HRTIM_FAULT_5
+ * @retval Polarity This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_FLT_POLARITY_LOW
+ * @arg @ref LL_HRTIM_FLT_POLARITY_HIGH
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
+{
+ register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
+ REG_OFFSET_TAB_FLTINR[iFault]));
+ return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1P << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]);
+}
+
+/**
+ * @brief Set the digital noise filter of a fault signal.
+ * @rmtoll FLTINR1 FLT1F LL_HRTIM_FLT_SetFilter\n
+ * FLTINR1 FLT2F LL_HRTIM_FLT_SetFilter\n
+ * FLTINR1 FLT3F LL_HRTIM_FLT_SetFilter\n
+ * FLTINR1 FLT4F LL_HRTIM_FLT_SetFilter\n
+ * FLTINR2 FLT5F LL_HRTIM_FLT_SetFilter
+ * @note This function must not be called when the fault channel is enabled.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Fault This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_FAULT_1
+ * @arg @ref LL_HRTIM_FAULT_2
+ * @arg @ref LL_HRTIM_FAULT_3
+ * @arg @ref LL_HRTIM_FAULT_4
+ * @arg @ref LL_HRTIM_FAULT_5
+ * @param Filter This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_FLT_FILTER_NONE
+ * @arg @ref LL_HRTIM_FLT_FILTER_1
+ * @arg @ref LL_HRTIM_FLT_FILTER_2
+ * @arg @ref LL_HRTIM_FLT_FILTER_3
+ * @arg @ref LL_HRTIM_FLT_FILTER_4
+ * @arg @ref LL_HRTIM_FLT_FILTER_5
+ * @arg @ref LL_HRTIM_FLT_FILTER_6
+ * @arg @ref LL_HRTIM_FLT_FILTER_7
+ * @arg @ref LL_HRTIM_FLT_FILTER_8
+ * @arg @ref LL_HRTIM_FLT_FILTER_9
+ * @arg @ref LL_HRTIM_FLT_FILTER_10
+ * @arg @ref LL_HRTIM_FLT_FILTER_11
+ * @arg @ref LL_HRTIM_FLT_FILTER_12
+ * @arg @ref LL_HRTIM_FLT_FILTER_13
+ * @arg @ref LL_HRTIM_FLT_FILTER_14
+ * @arg @ref LL_HRTIM_FLT_FILTER_15
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_FLT_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Filter)
+{
+ register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
+ REG_OFFSET_TAB_FLTINR[iFault]));
+ MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1F << REG_SHIFT_TAB_FLTxE[iFault]), (Filter << REG_SHIFT_TAB_FLTxE[iFault]));
+}
+
+/**
+ * @brief Get actual digital noise filter setting of a fault signal.
+ * @rmtoll FLTINR1 FLT1F LL_HRTIM_FLT_GetFilter\n
+ * FLTINR1 FLT2F LL_HRTIM_FLT_GetFilter\n
+ * FLTINR1 FLT3F LL_HRTIM_FLT_GetFilter\n
+ * FLTINR1 FLT4F LL_HRTIM_FLT_GetFilter\n
+ * FLTINR2 FLT5F LL_HRTIM_FLT_GetFilter
+ * @param HRTIMx High Resolution Timer instance
+ * @param Fault This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_FAULT_1
+ * @arg @ref LL_HRTIM_FAULT_2
+ * @arg @ref LL_HRTIM_FAULT_3
+ * @arg @ref LL_HRTIM_FAULT_4
+ * @arg @ref LL_HRTIM_FAULT_5
+ * @retval Filter This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_FLT_FILTER_NONE
+ * @arg @ref LL_HRTIM_FLT_FILTER_1
+ * @arg @ref LL_HRTIM_FLT_FILTER_2
+ * @arg @ref LL_HRTIM_FLT_FILTER_3
+ * @arg @ref LL_HRTIM_FLT_FILTER_4
+ * @arg @ref LL_HRTIM_FLT_FILTER_5
+ * @arg @ref LL_HRTIM_FLT_FILTER_6
+ * @arg @ref LL_HRTIM_FLT_FILTER_7
+ * @arg @ref LL_HRTIM_FLT_FILTER_8
+ * @arg @ref LL_HRTIM_FLT_FILTER_9
+ * @arg @ref LL_HRTIM_FLT_FILTER_10
+ * @arg @ref LL_HRTIM_FLT_FILTER_11
+ * @arg @ref LL_HRTIM_FLT_FILTER_12
+ * @arg @ref LL_HRTIM_FLT_FILTER_13
+ * @arg @ref LL_HRTIM_FLT_FILTER_14
+ * @arg @ref LL_HRTIM_FLT_FILTER_15
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
+{
+ register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
+ REG_OFFSET_TAB_FLTINR[iFault]));
+ return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1F << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]);
+}
+
+/**
+ * @brief Set the fault circuitry prescaler.
+ * @rmtoll FLTINR2 FLTSD LL_HRTIM_FLT_SetPrescaler
+ * @param HRTIMx High Resolution Timer instance
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV1
+ * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV2
+ * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV4
+ * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV8
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_FLT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler)
+{
+ MODIFY_REG(HRTIMx->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLTSD, Prescaler);
+}
+
+/**
+ * @brief Get actual fault circuitry prescaler setting.
+ * @rmtoll FLTINR2 FLTSD LL_HRTIM_FLT_GetPrescaler
+ * @param HRTIMx High Resolution Timer instance
+ * @retval Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV1
+ * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV2
+ * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV4
+ * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV8
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPrescaler(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLTSD));
+
+}
+
+/**
+ * @brief Lock the fault signal conditioning settings.
+ * @rmtoll FLTINR1 FLT1LCK LL_HRTIM_FLT_Lock\n
+ * FLTINR1 FLT2LCK LL_HRTIM_FLT_Lock\n
+ * FLTINR1 FLT3LCK LL_HRTIM_FLT_Lock\n
+ * FLTINR1 FLT4LCK LL_HRTIM_FLT_Lock\n
+ * FLTINR2 FLT5LCK LL_HRTIM_FLT_Lock
+ * @param HRTIMx High Resolution Timer instance
+ * @param Fault This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_FAULT_1
+ * @arg @ref LL_HRTIM_FAULT_2
+ * @arg @ref LL_HRTIM_FAULT_3
+ * @arg @ref LL_HRTIM_FAULT_4
+ * @arg @ref LL_HRTIM_FAULT_5
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_FLT_Lock(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
+{
+ register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
+ REG_OFFSET_TAB_FLTINR[iFault]));
+ SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1LCK << REG_SHIFT_TAB_FLTxE[iFault]));
+}
+
+/**
+ * @brief Enable the fault circuitry for the designated fault input.
+ * @rmtoll FLTINR1 FLT1E LL_HRTIM_FLT_Enable\n
+ * FLTINR1 FLT2E LL_HRTIM_FLT_Enable\n
+ * FLTINR1 FLT3E LL_HRTIM_FLT_Enable\n
+ * FLTINR1 FLT4E LL_HRTIM_FLT_Enable\n
+ * FLTINR2 FLT5E LL_HRTIM_FLT_Enable
+ * @param HRTIMx High Resolution Timer instance
+ * @param Fault This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_FAULT_1
+ * @arg @ref LL_HRTIM_FAULT_2
+ * @arg @ref LL_HRTIM_FAULT_3
+ * @arg @ref LL_HRTIM_FAULT_4
+ * @arg @ref LL_HRTIM_FAULT_5
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_FLT_Enable(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
+{
+ register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
+ REG_OFFSET_TAB_FLTINR[iFault]));
+ SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault]));
+}
+
+/**
+ * @brief Disable the fault circuitry for for the designated fault input.
+ * @rmtoll FLTINR1 FLT1E LL_HRTIM_FLT_Disable\n
+ * FLTINR1 FLT2E LL_HRTIM_FLT_Disable\n
+ * FLTINR1 FLT3E LL_HRTIM_FLT_Disable\n
+ * FLTINR1 FLT4E LL_HRTIM_FLT_Disable\n
+ * FLTINR2 FLT5E LL_HRTIM_FLT_Disable
+ * @param HRTIMx High Resolution Timer instance
+ * @param Fault This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_FAULT_1
+ * @arg @ref LL_HRTIM_FAULT_2
+ * @arg @ref LL_HRTIM_FAULT_3
+ * @arg @ref LL_HRTIM_FAULT_4
+ * @arg @ref LL_HRTIM_FAULT_5
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_FLT_Disable(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
+{
+ register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
+ REG_OFFSET_TAB_FLTINR[iFault]));
+ CLEAR_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault]));
+}
+
+/**
+ * @brief Indicate whether the fault circuitry is enabled for a given fault input.
+ * @rmtoll FLTINR1 FLT1E LL_HRTIM_FLT_IsEnabled\n
+ * FLTINR1 FLT2E LL_HRTIM_FLT_IsEnabled\n
+ * FLTINR1 FLT3E LL_HRTIM_FLT_IsEnabled\n
+ * FLTINR1 FLT4E LL_HRTIM_FLT_IsEnabled\n
+ * FLTINR2 FLT5E LL_HRTIM_FLT_IsEnabled
+ * @param HRTIMx High Resolution Timer instance * @param HRTIMx High Resolution Timer instance
+ * @param Fault This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_FAULT_1
+ * @arg @ref LL_HRTIM_FAULT_2
+ * @arg @ref LL_HRTIM_FAULT_3
+ * @arg @ref LL_HRTIM_FAULT_4
+ * @arg @ref LL_HRTIM_FAULT_5
+ * @retval State of FLTxEN bit in HRTIM_FLTINRx register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_FLT_IsEnabled(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
+{
+ register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
+ REG_OFFSET_TAB_FLTINR[iFault]));
+ return ((READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]) ==
+ (HRTIM_IER_FLT1));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EF_Burst_Mode_management Burst_Mode_management
+ * @{
+ */
+
+/**
+ * @brief Configure the burst mode controller.
+ * @rmtoll BMCR BMOM LL_HRTIM_BM_Config\n
+ * BMCR BMCLK LL_HRTIM_BM_Config\n
+ * BMCR BMPRSC LL_HRTIM_BM_Config
+ * @param HRTIMx High Resolution Timer instance
+ * @param Configuration This parameter must be a combination of all the following values:
+ * @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT or @ref LL_HRTIM_BM_MODE_CONTINOUS
+ * @arg @ref LL_HRTIM_BM_CLKSRC_MASTER or ... or @ref LL_HRTIM_BM_CLKSRC_FHRTIM
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1 or ... @ref LL_HRTIM_BM_PRESCALER_DIV32768
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_BM_Config(HRTIM_TypeDef *HRTIMx, uint32_t Configuration)
+{
+ MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BM_CONFIG_MASK, Configuration);
+}
+
+/**
+ * @brief Set the burst mode controller operating mode.
+ * @rmtoll BMCR BMOM LL_HRTIM_BM_SetMode
+ * @param HRTIMx High Resolution Timer instance
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT
+ * @arg @ref LL_HRTIM_BM_MODE_CONTINOUS
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_BM_SetMode(HRTIM_TypeDef *HRTIMx, uint32_t Mode)
+{
+ MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMOM, Mode);
+}
+
+/**
+ * @brief Get actual burst mode controller operating mode.
+ * @rmtoll BMCR BMOM LL_HRTIM_BM_GetMode
+ * @param HRTIMx High Resolution Timer instance
+ * @retval Mode This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT
+ * @arg @ref LL_HRTIM_BM_MODE_CONTINOUS
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_BM_GetMode(HRTIM_TypeDef *HRTIMx)
+{
+ return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMOM);
+}
+
+/**
+ * @brief Set the burst mode controller clock source.
+ * @rmtoll BMCR BMCLK LL_HRTIM_BM_SetClockSrc
+ * @param HRTIMx High Resolution Timer instance
+ * @param ClockSrc This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_BM_CLKSRC_MASTER
+ * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_A
+ * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_B
+ * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_C
+ * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_D
+ * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_E
+ * @arg @ref LL_HRTIM_BM_CLKSRC_TIM16_OC
+ * @arg @ref LL_HRTIM_BM_CLKSRC_TIM17_OC
+ * @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO
+ * @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_BM_SetClockSrc(HRTIM_TypeDef *HRTIMx, uint32_t ClockSrc)
+{
+ MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMCLK, ClockSrc);
+}
+
+/**
+ * @brief Get actual burst mode controller clock source.
+ * @rmtoll BMCR BMCLK LL_HRTIM_BM_GetClockSrc
+ * @param HRTIMx High Resolution Timer instance
+ * @retval ClockSrc This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_BM_CLKSRC_MASTER
+ * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_A
+ * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_B
+ * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_C
+ * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_D
+ * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_E
+ * @arg @ref LL_HRTIM_BM_CLKSRC_TIM16_OC
+ * @arg @ref LL_HRTIM_BM_CLKSRC_TIM17_OC
+ * @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO
+ * @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_BM_GetClockSrc(HRTIM_TypeDef *HRTIMx)
+{
+ return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMCLK);
+}
+
+/**
+ * @brief Set the burst mode controller prescaler.
+ * @rmtoll BMCR BMPRSC LL_HRTIM_BM_SetPrescaler
+ * @param HRTIMx High Resolution Timer instance
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV2
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV4
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV8
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV16
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV32
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV64
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV128
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV256
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV512
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1024
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV2048
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV4096
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV8192
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV16384
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV32768
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_BM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler)
+{
+ MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPRSC, Prescaler);
+}
+
+/**
+ * @brief Get actual burst mode controller prescaler setting.
+ * @rmtoll BMCR BMPRSC LL_HRTIM_BM_GetPrescaler
+ * @param HRTIMx High Resolution Timer instance
+ * @retval Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV2
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV4
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV8
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV16
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV32
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV64
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV128
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV256
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV512
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1024
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV2048
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV4096
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV8192
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV16384
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV32768
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_BM_GetPrescaler(HRTIM_TypeDef *HRTIMx)
+{
+ return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPRSC);
+}
+
+/**
+ * @brief Enable burst mode compare and period registers preload.
+ * @rmtoll BMCR BMPREN LL_HRTIM_BM_EnablePreload
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_BM_EnablePreload(HRTIM_TypeDef *HRTIMx)
+{
+ SET_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN);
+}
+
+/**
+ * @brief Disable burst mode compare and period registers preload.
+ * @rmtoll BMCR BMPREN LL_HRTIM_BM_DisablePreload
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_BM_DisablePreload(HRTIM_TypeDef *HRTIMx)
+{
+ CLEAR_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN);
+}
+
+/**
+ * @brief Indicate whether burst mode compare and period registers are preloaded.
+ * @rmtoll BMCR BMPREN LL_HRTIM_BM_IsEnabledPreload
+ * @param HRTIMx High Resolution Timer instance
+ * @retval State of BMPREN bit in HRTIM_BMCR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_BM_IsEnabledPreload(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN) == HRTIM_BMCR_BMPREN);
+}
+
+/**
+ * @brief Set the burst mode controller trigger
+ * @rmtoll BMTRGR SW LL_HRTIM_BM_SetTrig\n
+ * BMTRGR MSTRST LL_HRTIM_BM_SetTrig\n
+ * BMTRGR MSTREP LL_HRTIM_BM_SetTrig\n
+ * BMTRGR MSTCMP1 LL_HRTIM_BM_SetTrig\n
+ * BMTRGR MSTCMP2 LL_HRTIM_BM_SetTrig\n
+ * BMTRGR MSTCMP3 LL_HRTIM_BM_SetTrig\n
+ * BMTRGR MSTCMP4 LL_HRTIM_BM_SetTrig\n
+ * BMTRGR TARST LL_HRTIM_BM_SetTrig\n
+ * BMTRGR TAREP LL_HRTIM_BM_SetTrig\n
+ * BMTRGR TACMP1 LL_HRTIM_BM_SetTrig\n
+ * BMTRGR TACMP2 LL_HRTIM_BM_SetTrig\n
+ * BMTRGR TBRST LL_HRTIM_BM_SetTrig\n
+ * BMTRGR TBREP LL_HRTIM_BM_SetTrig\n
+ * BMTRGR TBCMP1 LL_HRTIM_BM_SetTrig\n
+ * BMTRGR TBCMP2 LL_HRTIM_BM_SetTrig\n
+ * BMTRGR TCRST LL_HRTIM_BM_SetTrig\n
+ * BMTRGR TCREP LL_HRTIM_BM_SetTrig\n
+ * BMTRGR TCCMP1 LL_HRTIM_BM_SetTrig\n
+ * BMTRGR TCCMP2 LL_HRTIM_BM_SetTrig\n
+ * BMTRGR TDRST LL_HRTIM_BM_SetTrig\n
+ * BMTRGR TDREP LL_HRTIM_BM_SetTrig\n
+ * BMTRGR TDCMP1 LL_HRTIM_BM_SetTrig\n
+ * BMTRGR TDCMP2 LL_HRTIM_BM_SetTrig\n
+ * BMTRGR TERST LL_HRTIM_BM_SetTrig\n
+ * BMTRGR TEREP LL_HRTIM_BM_SetTrig\n
+ * BMTRGR TECMP1 LL_HRTIM_BM_SetTrig\n
+ * BMTRGR TECMP2 LL_HRTIM_BM_SetTrig\n
+ * BMTRGR TAEEV7 LL_HRTIM_BM_SetTrig\n
+ * BMTRGR TAEEV8 LL_HRTIM_BM_SetTrig\n
+ * BMTRGR EEV7 LL_HRTIM_BM_SetTrig\n
+ * BMTRGR EEV8 LL_HRTIM_BM_SetTrig\n
+ * BMTRGR OCHIPEV LL_HRTIM_BM_SetTrig
+ * @param HRTIMx High Resolution Timer instance
+ * @param Trig This parameter can be a combination of the following values:
+ * @arg @ref LL_HRTIM_BM_TRIG_NONE
+ * @arg @ref LL_HRTIM_BM_TRIG_MASTER_RESET
+ * @arg @ref LL_HRTIM_BM_TRIG_MASTER_REPETITION
+ * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP1
+ * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP2
+ * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP3
+ * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP4
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMA_RESET
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMA_REPETITION
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP1
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP2
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMB_RESET
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMB_REPETITION
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP1
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP2
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMC_RESET
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMC_REPETITION
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP1
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP2
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMD_RESET
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMD_REPETITION
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP1
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP2
+ * @arg @ref LL_HRTIM_BM_TRIG_TIME_RESET
+ * @arg @ref LL_HRTIM_BM_TRIG_TIME_REPETITION
+ * @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP1
+ * @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP2
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMA_EVENT7
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMD_EVENT8
+ * @arg @ref LL_HRTIM_BM_TRIG_EVENT_7
+ * @arg @ref LL_HRTIM_BM_TRIG_EVENT_8
+ * @arg @ref LL_HRTIM_BM_TRIG_EVENT_ONCHIP
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_BM_SetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Trig)
+{
+ WRITE_REG(HRTIMx->sCommonRegs.BMTRGR, Trig);
+}
+
+/**
+ * @brief Get actual burst mode controller trigger.
+ * @rmtoll BMTRGR SW LL_HRTIM_BM_GetTrig\n
+ * BMTRGR MSTRST LL_HRTIM_BM_GetTrig\n
+ * BMTRGR MSTREP LL_HRTIM_BM_GetTrig\n
+ * BMTRGR MSTCMP1 LL_HRTIM_BM_GetTrig\n
+ * BMTRGR MSTCMP2 LL_HRTIM_BM_GetTrig\n
+ * BMTRGR MSTCMP3 LL_HRTIM_BM_GetTrig\n
+ * BMTRGR MSTCMP4 LL_HRTIM_BM_GetTrig\n
+ * BMTRGR TARST LL_HRTIM_BM_GetTrig\n
+ * BMTRGR TAREP LL_HRTIM_BM_GetTrig\n
+ * BMTRGR TACMP1 LL_HRTIM_BM_GetTrig\n
+ * BMTRGR TACMP2 LL_HRTIM_BM_GetTrig\n
+ * BMTRGR TBRST LL_HRTIM_BM_GetTrig\n
+ * BMTRGR TBREP LL_HRTIM_BM_GetTrig\n
+ * BMTRGR TBCMP1 LL_HRTIM_BM_GetTrig\n
+ * BMTRGR TBCMP2 LL_HRTIM_BM_GetTrig\n
+ * BMTRGR TCRST LL_HRTIM_BM_GetTrig\n
+ * BMTRGR TCREP LL_HRTIM_BM_GetTrig\n
+ * BMTRGR TCCMP1 LL_HRTIM_BM_GetTrig\n
+ * BMTRGR TCCMP2 LL_HRTIM_BM_GetTrig\n
+ * BMTRGR TDRST LL_HRTIM_BM_GetTrig\n
+ * BMTRGR TDREP LL_HRTIM_BM_GetTrig\n
+ * BMTRGR TDCMP1 LL_HRTIM_BM_GetTrig\n
+ * BMTRGR TDCMP2 LL_HRTIM_BM_GetTrig\n
+ * BMTRGR TERST LL_HRTIM_BM_GetTrig\n
+ * BMTRGR TEREP LL_HRTIM_BM_GetTrig\n
+ * BMTRGR TECMP1 LL_HRTIM_BM_GetTrig\n
+ * BMTRGR TECMP2 LL_HRTIM_BM_GetTrig\n
+ * BMTRGR TAEEV7 LL_HRTIM_BM_GetTrig\n
+ * BMTRGR TAEEV8 LL_HRTIM_BM_GetTrig\n
+ * BMTRGR EEV7 LL_HRTIM_BM_GetTrig\n
+ * BMTRGR EEV8 LL_HRTIM_BM_GetTrig\n
+ * BMTRGR OCHIPEV LL_HRTIM_BM_GetTrig
+ * @param HRTIMx High Resolution Timer instance
+ * @retval Trig This parameter can be a combination of the following values:
+ * @arg @ref LL_HRTIM_BM_TRIG_NONE
+ * @arg @ref LL_HRTIM_BM_TRIG_MASTER_RESET
+ * @arg @ref LL_HRTIM_BM_TRIG_MASTER_REPETITION
+ * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP1
+ * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP2
+ * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP3
+ * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP4
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMA_RESET
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMA_REPETITION
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP1
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP2
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMB_RESET
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMB_REPETITION
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP1
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP2
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMC_RESET
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMC_REPETITION
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP1
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP2
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMD_RESET
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMD_REPETITION
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP1
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP2
+ * @arg @ref LL_HRTIM_BM_TRIG_TIME_RESET
+ * @arg @ref LL_HRTIM_BM_TRIG_TIME_REPETITION
+ * @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP1
+ * @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP2
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMA_EVENT7
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMD_EVENT8
+ * @arg @ref LL_HRTIM_BM_TRIG_EVENT_7
+ * @arg @ref LL_HRTIM_BM_TRIG_EVENT_8
+ * @arg @ref LL_HRTIM_BM_TRIG_EVENT_ONCHIP
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_BM_GetTrig(HRTIM_TypeDef *HRTIMx)
+{
+ return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMTRGR);
+}
+
+/**
+ * @brief Set the burst mode controller compare value.
+ * @rmtoll BMCMPR BMCMP LL_HRTIM_BM_SetCompare
+ * @param HRTIMx High Resolution Timer instance
+ * @param CompareValue Compare value must be above or equal to 3
+ * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
+ * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_BM_SetCompare(HRTIM_TypeDef *HRTIMx, uint32_t CompareValue)
+{
+ WRITE_REG(HRTIMx->sCommonRegs.BMCMPR, CompareValue);
+}
+
+/**
+ * @brief Get actual burst mode controller compare value.
+ * @rmtoll BMCMPR BMCMP LL_HRTIM_BM_GetCompare
+ * @param HRTIMx High Resolution Timer instance
+ * @retval CompareValue Compare value must be above or equal to 3
+ * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
+ * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_BM_GetCompare(HRTIM_TypeDef *HRTIMx)
+{
+ return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMCMPR);
+}
+
+/**
+ * @brief Set the burst mode controller period.
+ * @rmtoll BMPER BMPER LL_HRTIM_BM_SetPeriod
+ * @param HRTIMx High Resolution Timer instance
+ * @param Period The period value must be above or equal to 3 periods of the fHRTIM clock,
+ * that is 0x60 if CKPSC[2:0] = 0, 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
+ * The maximum value is 0x0000 FFDF.
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_BM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Period)
+{
+ WRITE_REG(HRTIMx->sCommonRegs.BMPER, Period);
+}
+
+/**
+ * @brief Get actual burst mode controller period.
+ * @rmtoll BMPER BMPER LL_HRTIM_BM_GetPeriod
+ * @param HRTIMx High Resolution Timer instance
+ * @retval The period value must be above or equal to 3 periods of the fHRTIM clock,
+ * that is 0x60 if CKPSC[2:0] = 0, 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
+ * The maximum value is 0x0000 FFDF.
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_BM_GetPeriod(HRTIM_TypeDef *HRTIMx)
+{
+ return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMPER);
+}
+
+/**
+ * @brief Enable the burst mode controller
+ * @rmtoll BMCR BME LL_HRTIM_BM_Enable
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_BM_Enable(HRTIM_TypeDef *HRTIMx)
+{
+ SET_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME);
+}
+
+/**
+ * @brief Disable the burst mode controller
+ * @rmtoll BMCR BME LL_HRTIM_BM_Disable
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_BM_Disable(HRTIM_TypeDef *HRTIMx)
+{
+ CLEAR_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME);
+}
+
+/**
+ * @brief Indicate whether the burst mode controller is enabled.
+ * @rmtoll BMCR BME LL_HRTIM_BM_IsEnabled
+ * @param HRTIMx High Resolution Timer instance
+ * @retval State of BME bit in HRTIM_BMCR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_BM_IsEnabled(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME) == HRTIM_BMCR_BME);
+}
+
+/**
+ * @brief Trigger the burst operation (software trigger)
+ * @rmtoll BMTRGR SW LL_HRTIM_BM_Start
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_BM_Start(HRTIM_TypeDef *HRTIMx)
+{
+ SET_BIT(HRTIMx->sCommonRegs.BMTRGR, HRTIM_BMTRGR_SW);
+}
+
+/**
+ * @brief Stop the burst mode operation.
+ * @rmtoll BMCR BMSTAT LL_HRTIM_BM_Stop
+ * @note Causes a burst mode early termination.
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_BM_Stop(HRTIM_TypeDef *HRTIMx)
+{
+ CLEAR_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMSTAT);
+}
+
+/**
+ * @brief Get actual burst mode status
+ * @rmtoll BMCR BMSTAT LL_HRTIM_BM_GetStatus
+ * @param HRTIMx High Resolution Timer instance
+ * @retval Status This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_BM_STATUS_NORMAL
+ * @arg @ref LL_HRTIM_BM_STATUS_BURST_ONGOING
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_BM_GetStatus(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMSTAT));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+
+/**
+ * @brief Clear the Fault 1 interrupt flag.
+ * @rmtoll ICR FLT1C LL_HRTIM_ClearFlag_FLT1
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_FLT1(HRTIM_TypeDef *HRTIMx)
+{
+ SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT1C);
+}
+
+/**
+ * @brief Indicate whether Fault 1 interrupt occurred.
+ * @rmtoll ICR FLT1 LL_HRTIM_IsActiveFlag_FLT1
+ * @param HRTIMx High Resolution Timer instance
+ * @retval State of FLT1 bit in HRTIM_ISR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT1(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT1) == (HRTIM_ISR_FLT1));
+}
+
+/**
+ * @brief Clear the Fault 2 interrupt flag.
+ * @rmtoll ICR FLT2C LL_HRTIM_ClearFlag_FLT2
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_FLT2(HRTIM_TypeDef *HRTIMx)
+{
+ SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT2C);
+}
+
+/**
+ * @brief Indicate whether Fault 2 interrupt occurred.
+ * @rmtoll ICR FLT2 LL_HRTIM_IsActiveFlag_FLT2
+ * @param HRTIMx High Resolution Timer instance
+ * @retval State of FLT2 bit in HRTIM_ISR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT2(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT2) == (HRTIM_ISR_FLT2));
+}
+
+/**
+ * @brief Clear the Fault 3 interrupt flag.
+ * @rmtoll ICR FLT3C LL_HRTIM_ClearFlag_FLT3
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_FLT3(HRTIM_TypeDef *HRTIMx)
+{
+ SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT3C);
+}
+
+/**
+ * @brief Indicate whether Fault 3 interrupt occurred.
+ * @rmtoll ICR FLT3 LL_HRTIM_IsActiveFlag_FLT3
+ * @param HRTIMx High Resolution Timer instance
+ * @retval State of FLT3 bit in HRTIM_ISR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT3(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT3) == (HRTIM_ISR_FLT3));
+}
+
+/**
+ * @brief Clear the Fault 4 interrupt flag.
+ * @rmtoll ICR FLT4C LL_HRTIM_ClearFlag_FLT4
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_FLT4(HRTIM_TypeDef *HRTIMx)
+{
+ SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT4C);
+}
+
+/**
+ * @brief Indicate whether Fault 4 interrupt occurred.
+ * @rmtoll ICR FLT4 LL_HRTIM_IsActiveFlag_FLT4
+ * @param HRTIMx High Resolution Timer instance
+ * @retval State of FLT4 bit in HRTIM_ISR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT4(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT4) == (HRTIM_ISR_FLT4));
+}
+
+/**
+ * @brief Clear the Fault 5 interrupt flag.
+ * @rmtoll ICR FLT5C LL_HRTIM_ClearFlag_FLT5
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_FLT5(HRTIM_TypeDef *HRTIMx)
+{
+ SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT5C);
+}
+
+/**
+ * @brief Indicate whether Fault 5 interrupt occurred.
+ * @rmtoll ICR FLT5 LL_HRTIM_IsActiveFlag_FLT5
+ * @param HRTIMx High Resolution Timer instance
+ * @retval State of FLT5 bit in HRTIM_ISR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT5(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT5) == (HRTIM_ISR_FLT5));
+}
+
+/**
+ * @brief Clear the System Fault interrupt flag.
+ * @rmtoll ICR SYSFLTC LL_HRTIM_ClearFlag_SYSFLT
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_SYSFLT(HRTIM_TypeDef *HRTIMx)
+{
+ SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_SYSFLTC);
+}
+
+/**
+ * @brief Indicate whether System Fault interrupt occurred.
+ * @rmtoll ISR SYSFLT LL_HRTIM_IsActiveFlag_SYSFLT
+ * @param HRTIMx High Resolution Timer instance
+ * @retval State of SYSFLT bit in HRTIM_ISR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SYSFLT(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_SYSFLT) == (HRTIM_ISR_SYSFLT));
+}
+
+/**
+ * @brief Clear the DLL ready interrupt flag.
+ * @rmtoll ICR DLLRDYC LL_HRTIM_ClearFlag_DLLRDY
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_DLLRDY(HRTIM_TypeDef *HRTIMx)
+{
+ SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_DLLRDYC);
+}
+
+/**
+ * @brief Indicate whether DLL ready interrupt occurred.
+ * @rmtoll ISR DLLRDY LL_HRTIM_IsActiveFlag_DLLRDY
+ * @param HRTIMx High Resolution Timer instance
+ * @retval State of DLLRDY bit in HRTIM_ISR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_DLLRDY(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_DLLRDY) == (HRTIM_ISR_DLLRDY));
+}
+
+/**
+ * @brief Clear the Burst Mode period interrupt flag.
+ * @rmtoll ICR BMPERC LL_HRTIM_ClearFlag_BMPER
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_BMPER(HRTIM_TypeDef *HRTIMx)
+{
+ SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_BMPERC);
+}
+
+/**
+ * @brief Indicate whether Burst Mode period interrupt occurred.
+ * @rmtoll ISR BMPER LL_HRTIM_IsActiveFlag_BMPER
+ * @param HRTIMx High Resolution Timer instance
+ * @retval State of BMPER bit in HRTIM_ISR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_BMPER(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_BMPER) == (HRTIM_ISR_BMPER));
+}
+
+/**
+ * @brief Clear the Synchronization Input interrupt flag.
+ * @rmtoll MICR SYNCC LL_HRTIM_ClearFlag_SYNC
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_SYNC(HRTIM_TypeDef *HRTIMx)
+{
+ SET_BIT(HRTIMx->sMasterRegs.MICR, HRTIM_MICR_SYNC);
+}
+
+/**
+ * @brief Indicate whether the Synchronization Input interrupt occurred.
+ * @rmtoll MISR SYNC LL_HRTIM_IsActiveFlag_SYNC
+ * @param HRTIMx High Resolution Timer instance
+ * @retval State of SYNC bit in HRTIM_MISR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SYNC(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sMasterRegs.MISR, HRTIM_MISR_SYNC) == (HRTIM_MISR_SYNC));
+}
+
+/**
+ * @brief Clear the update interrupt flag for a given timer (including the master timer) .
+ * @rmtoll MICR MUPDC LL_HRTIM_ClearFlag_UPDATE\n
+ * TIMxICR UPDC LL_HRTIM_ClearFlag_UPDATE
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_MICR_MUPD);
+}
+
+/**
+ * @brief Indicate whether the update interrupt has occurred for a given timer (including the master timer) .
+ * @rmtoll MISR MUPD LL_HRTIM_IsActiveFlag_UPDATE\n
+ * TIMxISR UPD LL_HRTIM_IsActiveFlag_UPDATE
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of MUPD/UPD bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MISR_MUPD) == (HRTIM_MISR_MUPD));
+}
+
+/**
+ * @brief Clear the repetition interrupt flag for a given timer (including the master timer) .
+ * @rmtoll MICR MREPC LL_HRTIM_ClearFlag_REP\n
+ * TIMxICR REPC LL_HRTIM_ClearFlag_REP
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_MICR_MREP);
+
+}
+
+/**
+ * @brief Indicate whether the repetition interrupt has occurred for a given timer (including the master timer) .
+ * @rmtoll MISR MREP LL_HRTIM_IsActiveFlag_REP\n
+ * TIMxISR REP LL_HRTIM_IsActiveFlag_REP
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of MREP/REP bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MISR_MREP) == (HRTIM_MISR_MREP));
+}
+
+/**
+ * @brief Clear the compare 1 match interrupt for a given timer (including the master timer).
+ * @rmtoll MICR MCMP1C LL_HRTIM_ClearFlag_CMP1\n
+ * TIMxICR CMP1C LL_HRTIM_ClearFlag_CMP1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_MICR_MCMP1);
+}
+
+/**
+ * @brief Indicate whether the compare match 1 interrupt has occurred for a given timer (including the master timer) .
+ * @rmtoll MISR MCMP1 LL_HRTIM_IsActiveFlag_CMP1\n
+ * TIMxISR CMP1 LL_HRTIM_IsActiveFlag_CMP1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of MCMP1/CMP1 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MISR_MCMP1) == (HRTIM_MISR_MCMP1));
+}
+
+/**
+ * @brief Clear the compare 2 match interrupt for a given timer (including the master timer).
+ * @rmtoll MICR MCMP2C LL_HRTIM_ClearFlag_CMP2\n
+ * TIMxICR CMP2C LL_HRTIM_ClearFlag_CMP2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_MICR_MCMP2);
+}
+
+/**
+ * @brief Indicate whether the compare match 2 interrupt has occurred for a given timer (including the master timer) .
+ * @rmtoll MISR MCMP2 LL_HRTIM_IsActiveFlag_CMP2\n
+ * TIMxISR CMP2 LL_HRTIM_IsActiveFlag_CMP2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of MCMP2/CMP2 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MISR_MCMP2) == (HRTIM_MISR_MCMP2));
+}
+
+/**
+ * @brief Clear the compare 3 match interrupt for a given timer (including the master timer).
+ * @rmtoll MICR MCMP3C LL_HRTIM_ClearFlag_CMP3\n
+ * TIMxICR CMP3C LL_HRTIM_ClearFlag_CMP3
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_MICR_MCMP3);
+}
+
+/**
+ * @brief Indicate whether the compare match 3 interrupt has occurred for a given timer (including the master timer) .
+ * @rmtoll MISR MCMP3 LL_HRTIM_IsActiveFlag_CMP3\n
+ * TIMxISR CMP3 LL_HRTIM_IsActiveFlag_CMP3
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of MCMP3/CMP3 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MISR_MCMP3) == (HRTIM_MISR_MCMP3));
+}
+
+/**
+ * @brief Clear the compare 4 match interrupt for a given timer (including the master timer).
+ * @rmtoll MICR MCMP4C LL_HRTIM_ClearFlag_CMP4\n
+ * TIMxICR CMP4C LL_HRTIM_ClearFlag_CMP4
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_MICR_MCMP4);
+}
+
+/**
+ * @brief Indicate whether the compare match 4 interrupt has occurred for a given timer (including the master timer) .
+ * @rmtoll MISR MCMP4 LL_HRTIM_IsActiveFlag_CMP4\n
+ * TIMxISR CMP4 LL_HRTIM_IsActiveFlag_CMP4
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of MCMP4/CMP4 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MISR_MCMP4) == (HRTIM_MISR_MCMP4));
+}
+
+/**
+ * @brief Clear the capture 1 interrupt flag for a given timer.
+ * @rmtoll TIMxICR CPT1C LL_HRTIM_ClearFlag_CPT1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_TIMICR_CPT1C);
+}
+
+/**
+ * @brief Indicate whether the capture 1 interrupt occurred for a given timer.
+ * @rmtoll TIMxISR CPT1 LL_HRTIM_IsActiveFlag_CPT1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of CPT1 bit in HRTIM_TIMxISR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMISR_CPT1) == (HRTIM_TIMISR_CPT1));
+}
+
+/**
+ * @brief Clear the capture 2 interrupt flag for a given timer.
+ * @rmtoll TIMxICR CPT2C LL_HRTIM_ClearFlag_CPT2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_TIMICR_CPT2C);
+}
+
+/**
+ * @brief Indicate whether the capture 2 interrupt occurred for a given timer.
+ * @rmtoll TIMxISR CPT2 LL_HRTIM_IsActiveFlag_CPT2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of CPT2 bit in HRTIM_TIMxISR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMISR_CPT2) == (HRTIM_TIMISR_CPT2));
+}
+
+/**
+ * @brief Clear the output 1 set interrupt flag for a given timer.
+ * @rmtoll TIMxICR SET1C LL_HRTIM_ClearFlag_SET1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_TIMICR_SET1C);
+}
+
+/**
+ * @brief Indicate whether the output 1 set interrupt occurred for a given timer.
+ * @rmtoll TIMxISR SET1 LL_HRTIM_IsActiveFlag_SET1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of SETx1 bit in HRTIM_TIMxISR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMISR_SET1) == (HRTIM_TIMISR_SET1));
+}
+
+/**
+ * @brief Clear the output 1 reset interrupt flag for a given timer.
+ * @rmtoll TIMxICR RST1C LL_HRTIM_ClearFlag_RST1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_TIMICR_RST1C);
+}
+
+/**
+ * @brief Indicate whether the output 1 reset interrupt occurred for a given timer.
+ * @rmtoll TIMxISR RST1 LL_HRTIM_IsActiveFlag_RST1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of RSTx1 bit in HRTIM_TIMxISR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMISR_RST1) == (HRTIM_TIMISR_RST1));
+}
+
+/**
+ * @brief Clear the output 2 set interrupt flag for a given timer.
+ * @rmtoll TIMxICR SET2C LL_HRTIM_ClearFlag_SET2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_TIMICR_SET2C);
+}
+
+/**
+ * @brief Indicate whether the output 2 set interrupt occurred for a given timer.
+ * @rmtoll TIMxISR SET2 LL_HRTIM_IsActiveFlag_SET2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of SETx2 bit in HRTIM_TIMxISR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMISR_SET2) == (HRTIM_TIMISR_SET2));
+}
+
+/**
+ * @brief Clear the output 2reset interrupt flag for a given timer.
+ * @rmtoll TIMxICR RST2C LL_HRTIM_ClearFlag_RST2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_TIMICR_RST2C);
+}
+
+/**
+ * @brief Indicate whether the output 2 reset interrupt occurred for a given timer.
+ * @rmtoll TIMxISR RST2 LL_HRTIM_IsActiveFlag_RST2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of RSTx2 bit in HRTIM_TIMxISR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMISR_RST2) == (HRTIM_TIMISR_RST2));
+}
+
+/**
+ * @brief Clear the reset and/or roll-over interrupt flag for a given timer.
+ * @rmtoll TIMxICR RSTC LL_HRTIM_ClearFlag_RST
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_TIMICR_RSTC);
+}
+
+/**
+ * @brief Indicate whether the reset and/or roll-over interrupt occurred for a given timer.
+ * @rmtoll TIMxISR RST LL_HRTIM_IsActiveFlag_RST
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of RST bit in HRTIM_TIMxISR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMISR_RST) == (HRTIM_TIMISR_RST));
+}
+
+/**
+ * @brief Clear the delayed protection interrupt flag for a given timer.
+ * @rmtoll TIMxICR DLYPRTC LL_HRTIM_ClearFlag_DLYPRT
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_TIMICR_DLYPRT1C);
+}
+
+/**
+ * @brief Indicate whether the delayed protection interrupt occurred for a given timer.
+ * @rmtoll TIMxISR DLYPRT LL_HRTIM_IsActiveFlag_DLYPRT
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of DLYPRT bit in HRTIM_TIMxISR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMISR_DLYPRT) == (HRTIM_TIMISR_DLYPRT));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EF_IT_Management IT_Management
+ * @{
+ */
+
+/**
+ * @brief Enable the fault 1 interrupt.
+ * @rmtoll IER FLT1IE LL_HRTIM_EnableIT_FLT1
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableIT_FLT1(HRTIM_TypeDef *HRTIMx)
+{
+ SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1);
+}
+
+/**
+ * @brief Disable the fault 1 interrupt.
+ * @rmtoll IER FLT1IE LL_HRTIM_DisableIT_FLT1
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableIT_FLT1(HRTIM_TypeDef *HRTIMx)
+{
+ CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1);
+}
+
+/**
+ * @brief Indicate whether the fault 1 interrupt is enabled.
+ * @rmtoll IER FLT1IE LL_HRTIM_IsEnabledIT_FLT1
+ * @param HRTIMx High Resolution Timer instance
+ * @retval State of FLT1IE bit in HRTIM_IER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT1(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1) == (HRTIM_IER_FLT1));
+}
+
+/**
+ * @brief Enable the fault 2 interrupt.
+ * @rmtoll IER FLT2IE LL_HRTIM_EnableIT_FLT2
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableIT_FLT2(HRTIM_TypeDef *HRTIMx)
+{
+ SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2);
+}
+
+/**
+ * @brief Disable the fault 2 interrupt.
+ * @rmtoll IER FLT2IE LL_HRTIM_DisableIT_FLT2
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableIT_FLT2(HRTIM_TypeDef *HRTIMx)
+{
+ CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2);
+}
+
+/**
+ * @brief Indicate whether the fault 2 interrupt is enabled.
+ * @rmtoll IER FLT2IE LL_HRTIM_IsEnabledIT_FLT2
+ * @param HRTIMx High Resolution Timer instance
+ * @retval State of FLT2IE bit in HRTIM_IER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT2(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2) == (HRTIM_IER_FLT2));
+}
+
+/**
+ * @brief Enable the fault 3 interrupt.
+ * @rmtoll IER FLT3IE LL_HRTIM_EnableIT_FLT3
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableIT_FLT3(HRTIM_TypeDef *HRTIMx)
+{
+ SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3);
+}
+
+/**
+ * @brief Disable the fault 3 interrupt.
+ * @rmtoll IER FLT3IE LL_HRTIM_DisableIT_FLT3
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableIT_FLT3(HRTIM_TypeDef *HRTIMx)
+{
+ CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3);
+}
+
+/**
+ * @brief Indicate whether the fault 3 interrupt is enabled.
+ * @rmtoll IER FLT3IE LL_HRTIM_IsEnabledIT_FLT3
+ * @param HRTIMx High Resolution Timer instance
+ * @retval State of FLT3IE bit in HRTIM_IER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT3(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3) == (HRTIM_IER_FLT3));
+}
+
+/**
+ * @brief Enable the fault 4 interrupt.
+ * @rmtoll IER FLT4IE LL_HRTIM_EnableIT_FLT4
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableIT_FLT4(HRTIM_TypeDef *HRTIMx)
+{
+ SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4);
+}
+
+/**
+ * @brief Disable the fault 4 interrupt.
+ * @rmtoll IER FLT4IE LL_HRTIM_DisableIT_FLT4
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableIT_FLT4(HRTIM_TypeDef *HRTIMx)
+{
+ CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4);
+}
+
+/**
+ * @brief Indicate whether the fault 4 interrupt is enabled.
+ * @rmtoll IER FLT4IE LL_HRTIM_IsEnabledIT_FLT4
+ * @param HRTIMx High Resolution Timer instance
+ * @retval State of FLT4IE bit in HRTIM_IER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT4(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4) == (HRTIM_IER_FLT4));
+}
+
+/**
+ * @brief Enable the fault 5 interrupt.
+ * @rmtoll IER FLT5IE LL_HRTIM_EnableIT_FLT5
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableIT_FLT5(HRTIM_TypeDef *HRTIMx)
+{
+ SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5);
+}
+
+/**
+ * @brief Disable the fault 5 interrupt.
+ * @rmtoll IER FLT5IE LL_HRTIM_DisableIT_FLT5
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableIT_FLT5(HRTIM_TypeDef *HRTIMx)
+{
+ CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5);
+}
+
+/**
+ * @brief Indicate whether the fault 5 interrupt is enabled.
+ * @rmtoll IER FLT5IE LL_HRTIM_IsEnabledIT_FLT5
+ * @param HRTIMx High Resolution Timer instance
+ * @retval State of FLT5IE bit in HRTIM_IER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT5(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5) == (HRTIM_IER_FLT5));
+}
+
+/**
+ * @brief Enable the system fault interrupt.
+ * @rmtoll IER SYSFLTIE LL_HRTIM_EnableIT_SYSFLT
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableIT_SYSFLT(HRTIM_TypeDef *HRTIMx)
+{
+ SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT);
+}
+
+/**
+ * @brief Disable the system fault interrupt.
+ * @rmtoll IER SYSFLTIE LL_HRTIM_DisableIT_SYSFLT
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableIT_SYSFLT(HRTIM_TypeDef *HRTIMx)
+{
+ CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT);
+}
+
+/**
+ * @brief Indicate whether the system fault interrupt is enabled.
+ * @rmtoll IER SYSFLTIE LL_HRTIM_IsEnabledIT_SYSFLT
+ * @param HRTIMx High Resolution Timer instance
+ * @retval State of SYSFLTIE bit in HRTIM_IER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SYSFLT(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT) == (HRTIM_IER_SYSFLT));
+}
+
+/**
+ * @brief Enable the DLL ready interrupt.
+ * @rmtoll IER DLLRDYIE LL_HRTIM_EnableIT_DLLRDY
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableIT_DLLRDY(HRTIM_TypeDef *HRTIMx)
+{
+ SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_DLLRDY);
+}
+
+/**
+ * @brief Disable the DLL ready interrupt.
+ * @rmtoll IER DLLRDYIE LL_HRTIM_DisableIT_DLLRDY
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableIT_DLLRDY(HRTIM_TypeDef *HRTIMx)
+{
+ CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_DLLRDY);
+}
+
+/**
+ * @brief Indicate whether the DLL ready interrupt is enabled.
+ * @rmtoll IER DLLRDYIE LL_HRTIM_IsEnabledIT_DLLRDY
+ * @param HRTIMx High Resolution Timer instance
+ * @retval State of DLLRDYIE bit in HRTIM_IER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_DLLRDY(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_DLLRDY) == (HRTIM_IER_DLLRDY));
+}
+
+/**
+ * @brief Enable the burst mode period interrupt.
+ * @rmtoll IER BMPERIE LL_HRTIM_EnableIT_BMPER
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableIT_BMPER(HRTIM_TypeDef *HRTIMx)
+{
+ SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER);
+}
+
+/**
+ * @brief Disable the burst mode period interrupt.
+ * @rmtoll IER BMPERIE LL_HRTIM_DisableIT_BMPER
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableIT_BMPER(HRTIM_TypeDef *HRTIMx)
+{
+ CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER);
+}
+
+/**
+ * @brief Indicate whether the burst mode period interrupt is enabled.
+ * @rmtoll IER BMPERIE LL_HRTIM_IsEnabledIT_BMPER
+ * @param HRTIMx High Resolution Timer instance
+ * @retval State of BMPERIE bit in HRTIM_IER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_BMPER(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER) == (HRTIM_IER_BMPER));
+}
+
+/**
+ * @brief Enable the synchronization input interrupt.
+ * @rmtoll MDIER SYNCIE LL_HRTIM_EnableIT_SYNC
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableIT_SYNC(HRTIM_TypeDef *HRTIMx)
+{
+ SET_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE);
+}
+
+/**
+ * @brief Disable the synchronization input interrupt.
+ * @rmtoll MDIER SYNCIE LL_HRTIM_DisableIT_SYNC
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableIT_SYNC(HRTIM_TypeDef *HRTIMx)
+{
+ CLEAR_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE);
+}
+
+/**
+ * @brief Indicate whether the synchronization input interrupt is enabled.
+ * @rmtoll MDIER SYNCIE LL_HRTIM_IsEnabledIT_SYNC
+ * @param HRTIMx High Resolution Timer instance
+ * @retval State of SYNCIE bit in HRTIM_MDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SYNC(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE) == (HRTIM_MDIER_SYNCIE));
+}
+
+/**
+ * @brief Enable the update interrupt for a given timer.
+ * @rmtoll MDIER MUPDIE LL_HRTIM_EnableIT_UPDATE\n
+ * TIMxDIER UPDIE LL_HRTIM_EnableIT_UPDATE
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_MDIER_MUPDIE);
+}
+
+/**
+ * @brief Disable the update interrupt for a given timer.
+ * @rmtoll MDIER MUPDIE LL_HRTIM_DisableIT_UPDATE\n
+ * TIMxDIER UPDIE LL_HRTIM_DisableIT_UPDATE
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDIE);
+}
+
+/**
+ * @brief Indicate whether the update interrupt is enabled for a given timer.
+ * @rmtoll MDIER MUPDIE LL_HRTIM_IsEnabledIT_UPDATE\n
+ * TIMxDIER UPDIE LL_HRTIM_IsEnabledIT_UPDATE
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of MUPDIE/UPDIE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MDIER_MUPDIE) == (HRTIM_MDIER_MUPDIE));
+}
+
+/**
+ * @brief Enable the repetition interrupt for a given timer.
+ * @rmtoll MDIER MREPIE LL_HRTIM_EnableIT_REP\n
+ * TIMxDIER REPIE LL_HRTIM_EnableIT_REP
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_MDIER_MREPIE);
+}
+
+/**
+ * @brief Disable the repetition interrupt for a given timer.
+ * @rmtoll MDIER MREPIE LL_HRTIM_DisableIT_REP\n
+ * TIMxDIER REPIE LL_HRTIM_DisableIT_REP
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_MDIER_MREPIE);
+}
+
+/**
+ * @brief Indicate whether the repetition interrupt is enabled for a given timer.
+ * @rmtoll MDIER MREPIE LL_HRTIM_IsEnabledIT_REP\n
+ * TIMxDIER REPIE LL_HRTIM_IsEnabledIT_REP
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of MREPIE/REPIE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MDIER_MREPIE) == (HRTIM_MDIER_MREPIE));
+}
+
+/**
+ * @brief Enable the compare 1 interrupt for a given timer.
+ * @rmtoll MDIER MCMP1IE LL_HRTIM_EnableIT_CMP1\n
+ * TIMxDIER CMP1IE LL_HRTIM_EnableIT_CMP1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_MDIER_MCMP1IE);
+}
+
+/**
+ * @brief Disable the compare 1 interrupt for a given timer.
+ * @rmtoll MDIER MCMP1IE LL_HRTIM_DisableIT_CMP1\n
+ * TIMxDIER CMP1IE LL_HRTIM_DisableIT_CMP1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1IE);
+}
+
+/**
+ * @brief Indicate whether the compare 1 interrupt is enabled for a given timer.
+ * @rmtoll MDIER MCMP1IE LL_HRTIM_IsEnabledIT_CMP1\n
+ * TIMxDIER CMP1IE LL_HRTIM_IsEnabledIT_CMP1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of MCMP1IE/CMP1IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MDIER_MCMP1IE) == (HRTIM_MDIER_MCMP1IE));
+}
+
+/**
+ * @brief Enable the compare 2 interrupt for a given timer.
+ * @rmtoll MDIER MCMP2IE LL_HRTIM_EnableIT_CMP2\n
+ * TIMxDIER CMP2IE LL_HRTIM_EnableIT_CMP2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_MDIER_MCMP2IE);
+}
+
+/**
+ * @brief Disable the compare 2 interrupt for a given timer.
+ * @rmtoll MDIER MCMP2IE LL_HRTIM_DisableIT_CMP2\n
+ * TIMxDIER CMP2IE LL_HRTIM_DisableIT_CMP2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2IE);
+}
+
+/**
+ * @brief Indicate whether the compare 2 interrupt is enabled for a given timer.
+ * @rmtoll MDIER MCMP2IE LL_HRTIM_IsEnabledIT_CMP2\n
+ * TIMxDIER CMP2IE LL_HRTIM_IsEnabledIT_CMP2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of MCMP2IE/CMP2IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MDIER_MCMP2IE) == (HRTIM_MDIER_MCMP2IE));
+}
+
+/**
+ * @brief Enable the compare 3 interrupt for a given timer.
+ * @rmtoll MDIER MCMP3IE LL_HRTIM_EnableIT_CMP3\n
+ * TIMxDIER CMP3IE LL_HRTIM_EnableIT_CMP3
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_MDIER_MCMP3IE);
+}
+
+/**
+ * @brief Disable the compare 3 interrupt for a given timer.
+ * @rmtoll MDIER MCMP3IE LL_HRTIM_DisableIT_CMP3\n
+ * TIMxDIER CMP3IE LL_HRTIM_DisableIT_CMP3
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3IE);
+}
+
+/**
+ * @brief Indicate whether the compare 3 interrupt is enabled for a given timer.
+ * @rmtoll MDIER MCMP3IE LL_HRTIM_IsEnabledIT_CMP3\n
+ * TIMxDIER CMP3IE LL_HRTIM_IsEnabledIT_CMP3
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of MCMP3IE/CMP3IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MDIER_MCMP3IE) == (HRTIM_MDIER_MCMP3IE));
+}
+
+/**
+ * @brief Enable the compare 4 interrupt for a given timer.
+ * @rmtoll MDIER MCMP4IE LL_HRTIM_EnableIT_CMP4\n
+ * TIMxDIER CMP4IE LL_HRTIM_EnableIT_CMP4
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_MDIER_MCMP4IE);
+}
+
+/**
+ * @brief Disable the compare 4 interrupt for a given timer.
+ * @rmtoll MDIER MCMP4IE LL_HRTIM_DisableIT_CMP4\n
+ * TIMxDIER CMP4IE LL_HRTIM_DisableIT_CMP4
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4IE);
+}
+
+/**
+ * @brief Indicate whether the compare 4 interrupt is enabled for a given timer.
+ * @rmtoll MDIER MCMP4IE LL_HRTIM_IsEnabledIT_CMP4\n
+ * TIMxDIER CMP4IE LL_HRTIM_IsEnabledIT_CMP4
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of MCMP4IE/CMP4IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MDIER_MCMP4IE) == (HRTIM_MDIER_MCMP4IE));
+}
+
+/**
+ * @brief Enable the capture 1 interrupt for a given timer.
+ * @rmtoll TIMxDIER CPT1IE LL_HRTIM_EnableIT_CPT1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_TIMDIER_CPT1IE);
+}
+
+/**
+ * @brief Enable the capture 1 interrupt for a given timer.
+ * @rmtoll TIMxDIER CPT1IE LL_HRTIM_DisableIT_CPT1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1IE);
+}
+
+/**
+ * @brief Indicate whether the capture 1 interrupt is enabled for a given timer.
+ * @rmtoll TIMxDIER CPT1IE LL_HRTIM_IsEnabledIT_CPT1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of CPT1IE bit in HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMDIER_CPT1IE) == (HRTIM_TIMDIER_CPT1IE));
+}
+
+/**
+ * @brief Enable the capture 2 interrupt for a given timer.
+ * @rmtoll TIMxDIER CPT2IE LL_HRTIM_EnableIT_CPT2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_TIMDIER_CPT2IE);
+}
+
+/**
+ * @brief Enable the capture 2 interrupt for a given timer.
+ * @rmtoll TIMxDIER CPT2IE LL_HRTIM_DisableIT_CPT2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2IE);
+}
+
+/**
+ * @brief Indicate whether the capture 2 interrupt is enabled for a given timer.
+ * @rmtoll TIMxDIER CPT2IE LL_HRTIM_IsEnabledIT_CPT2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of CPT2IE bit in HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMDIER_CPT2IE) == (HRTIM_TIMDIER_CPT2IE));
+}
+
+/**
+ * @brief Enable the output 1 set interrupt for a given timer.
+ * @rmtoll TIMxDIER SET1IE LL_HRTIM_EnableIT_SET1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_TIMDIER_SET1IE);
+}
+
+/**
+ * @brief Disable the output 1 set interrupt for a given timer.
+ * @rmtoll TIMxDIER SET1IE LL_HRTIM_DisableIT_SET1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1IE);
+}
+
+/**
+ * @brief Indicate whether the output 1 set interrupt is enabled for a given timer.
+ * @rmtoll TIMxDIER SET1IE LL_HRTIM_IsEnabledIT_SET1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of SET1xIE bit in HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMDIER_SET1IE) == (HRTIM_TIMDIER_SET1IE));
+}
+
+/**
+ * @brief Enable the output 1 reset interrupt for a given timer.
+ * @rmtoll TIMxDIER RST1IE LL_HRTIM_EnableIT_RST1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_TIMDIER_RST1IE);
+}
+
+/**
+ * @brief Disable the output 1 reset interrupt for a given timer.
+ * @rmtoll TIMxDIER RST1IE LL_HRTIM_DisableIT_RST1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1IE);
+}
+
+/**
+ * @brief Indicate whether the output 1 reset interrupt is enabled for a given timer.
+ * @rmtoll TIMxDIER RST1IE LL_HRTIM_IsEnabledIT_RST1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of RST1xIE bit in HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMDIER_RST1IE) == (HRTIM_TIMDIER_RST1IE));
+}
+
+/**
+ * @brief Enable the output 2 set interrupt for a given timer.
+ * @rmtoll TIMxDIER SET2IE LL_HRTIM_EnableIT_SET2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_TIMDIER_SET2IE);
+}
+
+/**
+ * @brief Disable the output 2 set interrupt for a given timer.
+ * @rmtoll TIMxDIER SET2IE LL_HRTIM_DisableIT_SET2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2IE);
+}
+
+/**
+ * @brief Indicate whether the output 2 set interrupt is enabled for a given timer.
+ * @rmtoll TIMxDIER SET2IE LL_HRTIM_IsEnabledIT_SET2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of SET2xIE bit in HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMDIER_SET2IE) == (HRTIM_TIMDIER_SET2IE));
+}
+
+/**
+ * @brief Enable the output 2 reset interrupt for a given timer.
+ * @rmtoll TIMxDIER RST2IE LL_HRTIM_EnableIT_RST2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_TIMDIER_RST2IE);
+}
+
+/**
+ * @brief Disable the output 2 reset interrupt for a given timer.
+ * @rmtoll TIMxDIER RST2IE LL_HRTIM_DisableIT_RST2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2IE);
+}
+
+/**
+ * @brief Indicate whether the output 2 reset LL_HRTIM_IsEnabledIT_RST2 is enabled for a given timer.
+ * @rmtoll TIMxDIER RST2IE LL_HRTIM_DisableIT_RST2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of RST2xIE bit in HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMDIER_RST2IE) == (HRTIM_TIMDIER_RST2IE));
+}
+
+/**
+ * @brief Enable the reset/roll-over interrupt for a given timer.
+ * @rmtoll TIMxDIER RSTIE LL_HRTIM_EnableIT_RST
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_TIMDIER_RSTIE);
+}
+
+/**
+ * @brief Disable the reset/roll-over interrupt for a given timer.
+ * @rmtoll TIMxDIER RSTIE LL_HRTIM_DisableIT_RST
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTIE);
+}
+
+/**
+ * @brief Indicate whether the reset/roll-over interrupt is enabled for a given timer.
+ * @rmtoll TIMxDIER RSTIE LL_HRTIM_IsEnabledIT_RST
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of RSTIE bit in HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMDIER_RSTIE) == (HRTIM_TIMDIER_RSTIE));
+}
+
+/**
+ * @brief Enable the delayed protection interrupt for a given timer.
+ * @rmtoll TIMxDIER DLYPRTIE LL_HRTIM_EnableIT_DLYPRT
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE);
+}
+
+/**
+ * @brief Disable the delayed protection interrupt for a given timer.
+ * @rmtoll TIMxDIER DLYPRTIE LL_HRTIM_DisableIT_DLYPRT
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE);
+}
+
+/**
+ * @brief Indicate whether the delayed protection interrupt is enabled for a given timer.
+ * @rmtoll TIMxDIER DLYPRTIE LL_HRTIM_IsEnabledIT_DLYPRT
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of DLYPRTIE bit in HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE) == (HRTIM_TIMDIER_DLYPRTIE));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EF_DMA_Management DMA_Management
+ * @{
+ */
+
+/**
+ * @brief Enable the synchronization input DMA request.
+ * @rmtoll MDIER SYNCDE LL_HRTIM_EnableDMAReq_SYNC
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_SYNC(HRTIM_TypeDef *HRTIMx)
+{
+ SET_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE);
+}
+
+/**
+ * @brief Disable the synchronization input DMA request
+ * @rmtoll MDIER SYNCDE LL_HRTIM_DisableDMAReq_SYNC
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_SYNC(HRTIM_TypeDef *HRTIMx)
+{
+ CLEAR_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE);
+}
+
+/**
+ * @brief Indicate whether the synchronization input DMA request is enabled.
+ * @rmtoll MDIER SYNCDE LL_HRTIM_IsEnabledDMAReq_SYNC
+ * @param HRTIMx High Resolution Timer instance
+ * @retval State of SYNCDE bit in HRTIM_MDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SYNC(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE) == (HRTIM_MDIER_SYNCDE));
+}
+
+/**
+ * @brief Enable the update DMA request for a given timer.
+ * @rmtoll MDIER MUPDDE LL_HRTIM_EnableDMAReq_UPDATE\n
+ * TIMxDIER UPDDE LL_HRTIM_EnableDMAReq_UPDATE
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_MDIER_MUPDDE);
+}
+
+/**
+ * @brief Disable the update DMA request for a given timer.
+ * @rmtoll MDIER MUPDDE LL_HRTIM_DisableDMAReq_UPDATE\n
+ * TIMxDIER UPDDE LL_HRTIM_DisableDMAReq_UPDATE
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDDE);
+}
+
+/**
+ * @brief Indicate whether the update DMA request is enabled for a given timer.
+ * @rmtoll MDIER MUPDDE LL_HRTIM_IsEnabledDMAReq_UPDATE\n
+ * TIMxDIER UPDDE LL_HRTIM_IsEnabledDMAReq_UPDATE
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of MUPDDE/UPDDE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MDIER_MUPDDE) == (HRTIM_MDIER_MUPDDE));
+}
+
+/**
+ * @brief Enable the repetition DMA request for a given timer.
+ * @rmtoll MDIER MREPDE LL_HRTIM_EnableDMAReq_REP\n
+ * TIMxDIER REPDE LL_HRTIM_EnableDMAReq_REP
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_MDIER_MREPDE);
+}
+
+/**
+ * @brief Disable the repetition DMA request for a given timer.
+ * @rmtoll MDIER MREPDE LL_HRTIM_DisableDMAReq_REP\n
+ * TIMxDIER REPDE LL_HRTIM_DisableDMAReq_REP
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_MDIER_MREPDE);
+}
+
+/**
+ * @brief Indicate whether the repetition DMA request is enabled for a given timer.
+ * @rmtoll MDIER MREPDE LL_HRTIM_IsEnabledDMAReq_REP\n
+ * TIMxDIER REPDE LL_HRTIM_IsEnabledDMAReq_REP
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of MREPDE/REPDE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MDIER_MREPDE) == (HRTIM_MDIER_MREPDE));
+}
+
+/**
+ * @brief Enable the compare 1 DMA request for a given timer.
+ * @rmtoll MDIER MCMP1DE LL_HRTIM_EnableDMAReq_CMP1\n
+ * TIMxDIER CMP1DE LL_HRTIM_EnableDMAReq_CMP1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_MDIER_MCMP1DE);
+}
+
+/**
+ * @brief Disable the compare 1 DMA request for a given timer.
+ * @rmtoll MDIER MCMP1DE LL_HRTIM_DisableDMAReq_CMP1\n
+ * TIMxDIER CMP1DE LL_HRTIM_DisableDMAReq_CMP1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1DE);
+}
+
+/**
+ * @brief Indicate whether the compare 1 DMA request is enabled for a given timer.
+ * @rmtoll MDIER MCMP1DE LL_HRTIM_IsEnabledDMAReq_CMP1\n
+ * TIMxDIER CMP1DE LL_HRTIM_IsEnabledDMAReq_CMP1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of MCMP1DE/CMP1DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MDIER_MCMP1DE) == (HRTIM_MDIER_MCMP1DE));
+}
+
+/**
+ * @brief Enable the compare 2 DMA request for a given timer.
+ * @rmtoll MDIER MCMP2DE LL_HRTIM_EnableDMAReq_CMP2\n
+ * TIMxDIER CMP2DE LL_HRTIM_EnableDMAReq_CMP2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_MDIER_MCMP2DE);
+}
+
+/**
+ * @brief Disable the compare 2 DMA request for a given timer.
+ * @rmtoll MDIER MCMP2DE LL_HRTIM_DisableDMAReq_CMP2\n
+ * TIMxDIER CMP2DE LL_HRTIM_DisableDMAReq_CMP2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2DE);
+}
+
+/**
+ * @brief Indicate whether the compare 2 DMA request is enabled for a given timer.
+ * @rmtoll MDIER MCMP2DE LL_HRTIM_IsEnabledDMAReq_CMP2\n
+ * TIMxDIER CMP2DE LL_HRTIM_IsEnabledDMAReq_CMP2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of MCMP2DE/CMP2DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MDIER_MCMP2DE) == (HRTIM_MDIER_MCMP2DE));
+}
+
+/**
+ * @brief Enable the compare 3 DMA request for a given timer.
+ * @rmtoll MDIER MCMP3DE LL_HRTIM_EnableDMAReq_CMP3\n
+ * TIMxDIER CMP3DE LL_HRTIM_EnableDMAReq_CMP3
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_MDIER_MCMP3DE);
+}
+
+/**
+ * @brief Disable the compare 3 DMA request for a given timer.
+ * @rmtoll MDIER MCMP3DE LL_HRTIM_DisableDMAReq_CMP3\n
+ * TIMxDIER CMP3DE LL_HRTIM_DisableDMAReq_CMP3
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3DE);
+}
+
+/**
+ * @brief Indicate whether the compare 3 DMA request is enabled for a given timer.
+ * @rmtoll MDIER MCMP3DE LL_HRTIM_IsEnabledDMAReq_CMP3\n
+ * TIMxDIER CMP3DE LL_HRTIM_IsEnabledDMAReq_CMP3
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of MCMP3DE/CMP3DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MDIER_MCMP3DE) == (HRTIM_MDIER_MCMP3DE));
+}
+
+/**
+ * @brief Enable the compare 4 DMA request for a given timer.
+ * @rmtoll MDIER MCMP4DE LL_HRTIM_EnableDMAReq_CMP4\n
+ * TIMxDIER CMP4DE LL_HRTIM_EnableDMAReq_CMP4
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_MDIER_MCMP4DE);
+}
+
+/**
+ * @brief Disable the compare 4 DMA request for a given timer.
+ * @rmtoll MDIER MCMP4DE LL_HRTIM_DisableDMAReq_CMP4\n
+ * TIMxDIER CMP4DE LL_HRTIM_DisableDMAReq_CMP4
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4DE);
+}
+
+/**
+ * @brief Indicate whether the compare 4 DMA request is enabled for a given timer.
+ * @rmtoll MDIER MCMP4DE LL_HRTIM_IsEnabledDMAReq_CMP4\n
+ * TIMxDIER CMP4DE LL_HRTIM_IsEnabledDMAReq_CMP4
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of MCMP4DE/CMP4DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MDIER_MCMP4DE) == (HRTIM_MDIER_MCMP4DE));
+}
+
+/**
+ * @brief Enable the capture 1 DMA request for a given timer.
+ * @rmtoll TIMxDIER CPT1DE LL_HRTIM_EnableDMAReq_CPT1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_TIMDIER_CPT1DE);
+}
+
+/**
+ * @brief Disable the capture 1 DMA request for a given timer.
+ * @rmtoll TIMxDIER CPT1DE LL_HRTIM_DisableDMAReq_CPT1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1DE);
+}
+
+/**
+ * @brief Indicate whether the capture 1 DMA request is enabled for a given timer.
+ * @rmtoll TIMxDIER CPT1DE LL_HRTIM_IsEnabledDMAReq_CPT1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of CPT1DE bit in HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMDIER_CPT1DE) == (HRTIM_TIMDIER_CPT1DE));
+}
+
+/**
+ * @brief Enable the capture 2 DMA request for a given timer.
+ * @rmtoll TIMxDIER CPT2DE LL_HRTIM_EnableDMAReq_CPT2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_TIMDIER_CPT2DE);
+}
+
+/**
+ * @brief Disable the capture 2 DMA request for a given timer.
+ * @rmtoll TIMxDIER CPT2DE LL_HRTIM_DisableDMAReq_CPT2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2DE);
+}
+
+/**
+ * @brief Indicate whether the capture 2 DMA request is enabled for a given timer.
+ * @rmtoll TIMxDIER CPT2DE LL_HRTIM_IsEnabledDMAReq_CPT2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of CPT2DE bit in HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMDIER_CPT2DE) == (HRTIM_TIMDIER_CPT2DE));
+}
+
+/**
+ * @brief Enable the output 1 set DMA request for a given timer.
+ * @rmtoll TIMxDIER SET1DE LL_HRTIM_EnableDMAReq_SET1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_TIMDIER_SET1DE);
+}
+
+/**
+ * @brief Disable the output 1 set DMA request for a given timer.
+ * @rmtoll TIMxDIER SET1DE LL_HRTIM_DisableDMAReq_SET1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1DE);
+}
+
+/**
+ * @brief Indicate whether the output 1 set DMA request is enabled for a given timer.
+ * @rmtoll TIMxDIER SET1DE LL_HRTIM_IsEnabledDMAReq_SET1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of SET1xDE bit in HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMDIER_SET1DE) == (HRTIM_TIMDIER_SET1DE));
+}
+
+/**
+ * @brief Enable the output 1 reset DMA request for a given timer.
+ * @rmtoll TIMxDIER RST1DE LL_HRTIM_EnableDMAReq_RST1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_TIMDIER_RST1DE);
+}
+
+/**
+ * @brief Disable the output 1 reset DMA request for a given timer.
+ * @rmtoll TIMxDIER RST1DE LL_HRTIM_DisableDMAReq_RST1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1DE);
+}
+
+/**
+ * @brief Indicate whether the output 1 reset interrupt is enabled for a given timer.
+ * @rmtoll TIMxDIER RST1DE LL_HRTIM_IsEnabledDMAReq_RST1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of RST1xDE bit in HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMDIER_RST1DE) == (HRTIM_TIMDIER_RST1DE));
+}
+
+/**
+ * @brief Enable the output 2 set DMA request for a given timer.
+ * @rmtoll TIMxDIER SET2DE LL_HRTIM_EnableDMAReq_SET2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_TIMDIER_SET2DE);
+}
+
+/**
+ * @brief Disable the output 2 set DMA request for a given timer.
+ * @rmtoll TIMxDIER SET2DE LL_HRTIM_DisableDMAReq_SET2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2DE);
+}
+
+/**
+ * @brief Indicate whether the output 2 set DMA request is enabled for a given timer.
+ * @rmtoll TIMxDIER SET2DE LL_HRTIM_IsEnabledDMAReq_SET2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of SET2xDE bit in HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMDIER_SET2DE) == (HRTIM_TIMDIER_SET2DE));
+}
+
+/**
+ * @brief Enable the output 2 reset DMA request for a given timer.
+ * @rmtoll TIMxDIER RST2DE LL_HRTIM_EnableDMAReq_RST2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_TIMDIER_RST2DE);
+}
+
+/**
+ * @brief Disable the output 2 reset DMA request for a given timer.
+ * @rmtoll TIMxDIER RST2DE LL_HRTIM_DisableDMAReq_RST2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2DE);
+}
+
+/**
+ * @brief Indicate whether the output 2 reset DMA request is enabled for a given timer.
+ * @rmtoll TIMxDIER RST2DE LL_HRTIM_IsEnabledDMAReq_RST2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of RST2xDE bit in HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMDIER_RST2DE) == (HRTIM_TIMDIER_RST2DE));
+}
+
+/**
+ * @brief Enable the reset/roll-over DMA request for a given timer.
+ * @rmtoll TIMxDIER RSTDE LL_HRTIM_EnableDMAReq_RST
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_TIMDIER_RSTDE);
+}
+
+/**
+ * @brief Disable the reset/roll-over DMA request for a given timer.
+ * @rmtoll TIMxDIER RSTDE LL_HRTIM_DisableDMAReq_RST
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTDE);
+}
+
+/**
+ * @brief Indicate whether the reset/roll-over DMA request is enabled for a given timer.
+ * @rmtoll TIMxDIER RSTDE LL_HRTIM_IsEnabledDMAReq_RST
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of RSTDE bit in HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMDIER_RSTDE) == (HRTIM_TIMDIER_RSTDE));
+}
+
+/**
+ * @brief Enable the delayed protection DMA request for a given timer.
+ * @rmtoll TIMxDIER DLYPRTDE LL_HRTIM_EnableDMAReq_DLYPRT
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE);
+}
+
+/**
+ * @brief Disable the delayed protection DMA request for a given timer.
+ * @rmtoll TIMxDIER DLYPRTDE LL_HRTIM_DisableDMAReq_DLYPRT
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE);
+}
+
+/**
+ * @brief Indicate whether the delayed protection DMA request is enabled for a given timer.
+ * @rmtoll TIMxDIER DLYPRTDE LL_HRTIM_IsEnabledDMAReq_DLYPRT
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of DLYPRTDE bit in HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE) == (HRTIM_TIMDIER_DLYPRTDE));
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup HRTIM_LL_EF_Init Initialisation and deinitialisation functions
+ * @{
+ */
+ErrorStatus LL_HRTIM_DeInit(HRTIM_TypeDef* HRTIMx);
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HRTIM1 */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_LL_HRTIM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_ll_i2c.h b/Inc/stm32f3xx_ll_i2c.h
new file mode 100644
index 0000000..e19b12b
--- /dev/null
+++ b/Inc/stm32f3xx_ll_i2c.h
@@ -0,0 +1,2244 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_i2c.h
+ * @author MCD Application Team
+ * @brief Header file of I2C LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_LL_I2C_H
+#define __STM32F3xx_LL_I2C_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx.h"
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined (I2C1) || defined (I2C2) || defined (I2C3)
+
+/** @defgroup I2C_LL I2C
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2C_LL_Private_Constants I2C Private Constants
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2C_LL_Private_Macros I2C Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
+ * @{
+ */
+typedef struct
+{
+ uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
+ This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE
+
+ This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
+
+ uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
+ This parameter must be set by referring to the STM32CubeMX Tool and
+ the helper macro @ref __LL_I2C_CONVERT_TIMINGS()
+
+ This feature can be modified afterwards using unitary function @ref LL_I2C_SetTiming(). */
+
+ uint32_t AnalogFilter; /*!< Enables or disables analog noise filter.
+ This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION
+
+ This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
+
+ uint32_t DigitalFilter; /*!< Configures the digital noise filter.
+ This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F
+
+ This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */
+
+ uint32_t OwnAddress1; /*!< Specifies the device own address 1.
+ This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
+
+ This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
+
+ uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
+ This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE
+
+ This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
+
+ uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
+ This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1
+
+ This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
+} LL_I2C_InitTypeDef;
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
+ * @{
+ */
+
+/** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines
+ * @brief Flags defines which can be used with LL_I2C_WriteReg function
+ * @{
+ */
+#define LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF /*!< Address Matched flag */
+#define LL_I2C_ICR_NACKCF I2C_ICR_NACKCF /*!< Not Acknowledge flag */
+#define LL_I2C_ICR_STOPCF I2C_ICR_STOPCF /*!< Stop detection flag */
+#define LL_I2C_ICR_BERRCF I2C_ICR_BERRCF /*!< Bus error flag */
+#define LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF /*!< Arbitration Lost flag */
+#define LL_I2C_ICR_OVRCF I2C_ICR_OVRCF /*!< Overrun/Underrun flag */
+#define LL_I2C_ICR_PECCF I2C_ICR_PECCF /*!< PEC error flag */
+#define LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF /*!< Timeout detection flag */
+#define LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF /*!< Alert flag */
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_I2C_ReadReg function
+ * @{
+ */
+#define LL_I2C_ISR_TXE I2C_ISR_TXE /*!< Transmit data register empty */
+#define LL_I2C_ISR_TXIS I2C_ISR_TXIS /*!< Transmit interrupt status */
+#define LL_I2C_ISR_RXNE I2C_ISR_RXNE /*!< Receive data register not empty */
+#define LL_I2C_ISR_ADDR I2C_ISR_ADDR /*!< Address matched (slave mode) */
+#define LL_I2C_ISR_NACKF I2C_ISR_NACKF /*!< Not Acknowledge received flag */
+#define LL_I2C_ISR_STOPF I2C_ISR_STOPF /*!< Stop detection flag */
+#define LL_I2C_ISR_TC I2C_ISR_TC /*!< Transfer Complete (master mode) */
+#define LL_I2C_ISR_TCR I2C_ISR_TCR /*!< Transfer Complete Reload */
+#define LL_I2C_ISR_BERR I2C_ISR_BERR /*!< Bus error */
+#define LL_I2C_ISR_ARLO I2C_ISR_ARLO /*!< Arbitration lost */
+#define LL_I2C_ISR_OVR I2C_ISR_OVR /*!< Overrun/Underrun (slave mode) */
+#define LL_I2C_ISR_PECERR I2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */
+#define LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */
+#define LL_I2C_ISR_ALERT I2C_ISR_ALERT /*!< SMBus alert (SMBus mode) */
+#define LL_I2C_ISR_BUSY I2C_ISR_BUSY /*!< Bus busy */
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
+ * @{
+ */
+#define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable */
+#define LL_I2C_CR1_RXIE I2C_CR1_RXIE /*!< RX Interrupt enable */
+#define LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE /*!< Address match Interrupt enable (slave only) */
+#define LL_I2C_CR1_NACKIE I2C_CR1_NACKIE /*!< Not acknowledge received Interrupt enable */
+#define LL_I2C_CR1_STOPIE I2C_CR1_STOPIE /*!< STOP detection Interrupt enable */
+#define LL_I2C_CR1_TCIE I2C_CR1_TCIE /*!< Transfer Complete interrupt enable */
+#define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable */
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
+ * @{
+ */
+#define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */
+#define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */
+#define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode (Default address not acknowledge) */
+#define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
+ * @{
+ */
+#define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U /*!< Analog filter is enabled. */
+#define LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /*!< Analog filter is disabled. */
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
+ * @{
+ */
+#define LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U /*!< Master operates in 7-bit addressing mode. */
+#define LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10 /*!< Master operates in 10-bit addressing mode.*/
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
+ * @{
+ */
+#define LL_I2C_OWNADDRESS1_7BIT 0x00000000U /*!< Own address 1 is a 7-bit address. */
+#define LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE /*!< Own address 1 is a 10-bit address.*/
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
+ * @{
+ */
+#define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */
+#define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */
+#define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */
+#define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */
+#define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */
+#define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */
+#define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */
+#define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /*!< No comparison is done. All Address2 are acknowledged.*/
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
+ * @{
+ */
+#define LL_I2C_ACK 0x00000000U /*!< ACK is sent after current received byte. */
+#define LL_I2C_NACK I2C_CR2_NACK /*!< NACK is sent after current received byte.*/
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length
+ * @{
+ */
+#define LL_I2C_ADDRSLAVE_7BIT 0x00000000U /*!< Slave Address in 7-bit. */
+#define LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10 /*!< Slave Address in 10-bit.*/
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction
+ * @{
+ */
+#define LL_I2C_REQUEST_WRITE 0x00000000U /*!< Master request a write transfer. */
+#define LL_I2C_REQUEST_READ I2C_CR2_RD_WRN /*!< Master request a read transfer. */
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_MODE Transfer End Mode
+ * @{
+ */
+#define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /*!< Enable I2C Reload mode. */
+#define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /*!< Enable I2C Automatic end mode with no HW PEC comparison. */
+#define LL_I2C_MODE_SOFTEND 0x00000000U /*!< Enable I2C Software end mode with no HW PEC comparison. */
+#define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
+#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
+#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode with HW PEC comparison. */
+#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE) /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
+#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE) /*!< Enable SMBUS Software end mode with HW PEC comparison. */
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
+ * @{
+ */
+#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U /*!< Don't Generate Stop and Start condition. */
+#define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) /*!< Generate Stop condition (Size should be set to 0). */
+#define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Start for read request. */
+#define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Start for write request. */
+#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Restart for read request, slave 7Bit address. */
+#define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Restart for write request, slave 7Bit address. */
+#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */
+#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Restart for write request, slave 10Bit address.*/
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
+ * @{
+ */
+#define LL_I2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master, slave enters receiver mode. */
+#define LL_I2C_DIRECTION_READ I2C_ISR_DIR /*!< Read transfer request by master, slave enters transmitter mode.*/
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data
+ * @{
+ */
+#define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */
+#define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
+ * @{
+ */
+#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect SCL low level timeout. */
+#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect both SCL and SDA high level timeout.*/
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection
+ * @{
+ */
+#define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */
+#define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock) enable bit */
+#define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB (extended clock) enable bits */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
+ * @{
+ */
+
+/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in I2C register
+ * @param __INSTANCE__ I2C Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in I2C register
+ * @param __INSTANCE__ I2C Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings
+ * @{
+ */
+/**
+ * @brief Configure the SDA setup, hold time and the SCL high, low period.
+ * @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
+ * @param __DATA_SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tscldel = (SCLDEL+1)xtpresc)
+ * @param __DATA_HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tsdadel = SDADELxtpresc)
+ * @param __CLOCK_HIGH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tsclh = (SCLH+1)xtpresc)
+ * @param __CLOCK_LOW_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tscll = (SCLL+1)xtpresc)
+ * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
+ */
+#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__) \
+ ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \
+ (((uint32_t)(__DATA_SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \
+ (((uint32_t)(__DATA_HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \
+ (((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \
+ (((uint32_t)(__CLOCK_LOW_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
+ * @{
+ */
+
+/** @defgroup I2C_LL_EF_Configuration Configuration
+ * @{
+ */
+
+/**
+ * @brief Enable I2C peripheral (PE = 1).
+ * @rmtoll CR1 PE LL_I2C_Enable
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_PE);
+}
+
+/**
+ * @brief Disable I2C peripheral (PE = 0).
+ * @note When PE = 0, the I2C SCL and SDA lines are released.
+ * Internal state machines and status bits are put back to their reset value.
+ * When cleared, PE must be kept low for at least 3 APB clock cycles.
+ * @rmtoll CR1 PE LL_I2C_Disable
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
+}
+
+/**
+ * @brief Check if the I2C peripheral is enabled or disabled.
+ * @rmtoll CR1 PE LL_I2C_IsEnabled
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE));
+}
+
+/**
+ * @brief Configure Noise Filters (Analog and Digital).
+ * @note If the analog filter is also enabled, the digital filter is added to analog filter.
+ * The filters can only be programmed when the I2C is disabled (PE = 0).
+ * @rmtoll CR1 ANFOFF LL_I2C_ConfigFilters\n
+ * CR1 DNF LL_I2C_ConfigFilters
+ * @param I2Cx I2C Instance.
+ * @param AnalogFilter This parameter can be one of the following values:
+ * @arg @ref LL_I2C_ANALOGFILTER_ENABLE
+ * @arg @ref LL_I2C_ANALOGFILTER_DISABLE
+ * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
+ * This parameter is used to configure the digital noise filter on SDA and SCL input.
+ * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
+{
+ MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos));
+}
+
+/**
+ * @brief Configure Digital Noise Filter.
+ * @note If the analog filter is also enabled, the digital filter is added to analog filter.
+ * This filter can only be programmed when the I2C is disabled (PE = 0).
+ * @rmtoll CR1 DNF LL_I2C_SetDigitalFilter
+ * @param I2Cx I2C Instance.
+ * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
+ * This parameter is used to configure the digital noise filter on SDA and SCL input.
+ * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
+{
+ MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos);
+}
+
+/**
+ * @brief Get the current Digital Noise Filter configuration.
+ * @rmtoll CR1 DNF LL_I2C_GetDigitalFilter
+ * @param I2Cx I2C Instance.
+ * @retval Value between Min_Data=0x0 and Max_Data=0xF
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos);
+}
+
+/**
+ * @brief Enable Analog Noise Filter.
+ * @note This filter can only be programmed when the I2C is disabled (PE = 0).
+ * @rmtoll CR1 ANFOFF LL_I2C_EnableAnalogFilter
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
+}
+
+/**
+ * @brief Disable Analog Noise Filter.
+ * @note This filter can only be programmed when the I2C is disabled (PE = 0).
+ * @rmtoll CR1 ANFOFF LL_I2C_DisableAnalogFilter
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
+}
+
+/**
+ * @brief Check if Analog Noise Filter is enabled or disabled.
+ * @rmtoll CR1 ANFOFF LL_I2C_IsEnabledAnalogFilter
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF));
+}
+
+/**
+ * @brief Enable DMA transmission requests.
+ * @rmtoll CR1 TXDMAEN LL_I2C_EnableDMAReq_TX
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
+}
+
+/**
+ * @brief Disable DMA transmission requests.
+ * @rmtoll CR1 TXDMAEN LL_I2C_DisableDMAReq_TX
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
+}
+
+/**
+ * @brief Check if DMA transmission requests are enabled or disabled.
+ * @rmtoll CR1 TXDMAEN LL_I2C_IsEnabledDMAReq_TX
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN));
+}
+
+/**
+ * @brief Enable DMA reception requests.
+ * @rmtoll CR1 RXDMAEN LL_I2C_EnableDMAReq_RX
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
+}
+
+/**
+ * @brief Disable DMA reception requests.
+ * @rmtoll CR1 RXDMAEN LL_I2C_DisableDMAReq_RX
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
+}
+
+/**
+ * @brief Check if DMA reception requests are enabled or disabled.
+ * @rmtoll CR1 RXDMAEN LL_I2C_IsEnabledDMAReq_RX
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN));
+}
+
+/**
+ * @brief Get the data register address used for DMA transfer
+ * @rmtoll TXDR TXDATA LL_I2C_DMA_GetRegAddr\n
+ * RXDR RXDATA LL_I2C_DMA_GetRegAddr
+ * @param I2Cx I2C Instance
+ * @param Direction This parameter can be one of the following values:
+ * @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT
+ * @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
+ * @retval Address of data register
+ */
+__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction)
+{
+ register uint32_t data_reg_addr = 0U;
+
+ if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)
+ {
+ /* return address of TXDR register */
+ data_reg_addr = (uint32_t) & (I2Cx->TXDR);
+ }
+ else
+ {
+ /* return address of RXDR register */
+ data_reg_addr = (uint32_t) & (I2Cx->RXDR);
+ }
+
+ return data_reg_addr;
+}
+
+/**
+ * @brief Enable Clock stretching.
+ * @note This bit can only be programmed when the I2C is disabled (PE = 0).
+ * @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
+}
+
+/**
+ * @brief Disable Clock stretching.
+ * @note This bit can only be programmed when the I2C is disabled (PE = 0).
+ * @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
+}
+
+/**
+ * @brief Check if Clock stretching is enabled or disabled.
+ * @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH));
+}
+
+/**
+ * @brief Enable hardware byte control in slave mode.
+ * @rmtoll CR1 SBC LL_I2C_EnableSlaveByteControl
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_SBC);
+}
+
+/**
+ * @brief Disable hardware byte control in slave mode.
+ * @rmtoll CR1 SBC LL_I2C_DisableSlaveByteControl
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC);
+}
+
+/**
+ * @brief Check if hardware byte control in slave mode is enabled or disabled.
+ * @rmtoll CR1 SBC LL_I2C_IsEnabledSlaveByteControl
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC));
+}
+
+/**
+ * @brief Enable Wakeup from STOP.
+ * @note Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
+ * WakeUpFromStop feature is supported by the I2Cx Instance.
+ * @note This bit can only be programmed when Digital Filter is disabled.
+ * @rmtoll CR1 WUPEN LL_I2C_EnableWakeUpFromStop
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
+}
+
+/**
+ * @brief Disable Wakeup from STOP.
+ * @note Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
+ * WakeUpFromStop feature is supported by the I2Cx Instance.
+ * @rmtoll CR1 WUPEN LL_I2C_DisableWakeUpFromStop
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
+}
+
+/**
+ * @brief Check if Wakeup from STOP is enabled or disabled.
+ * @note Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
+ * WakeUpFromStop feature is supported by the I2Cx Instance.
+ * @rmtoll CR1 WUPEN LL_I2C_IsEnabledWakeUpFromStop
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN));
+}
+
+/**
+ * @brief Enable General Call.
+ * @note When enabled the Address 0x00 is ACKed.
+ * @rmtoll CR1 GCEN LL_I2C_EnableGeneralCall
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_GCEN);
+}
+
+/**
+ * @brief Disable General Call.
+ * @note When disabled the Address 0x00 is NACKed.
+ * @rmtoll CR1 GCEN LL_I2C_DisableGeneralCall
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN);
+}
+
+/**
+ * @brief Check if General Call is enabled or disabled.
+ * @rmtoll CR1 GCEN LL_I2C_IsEnabledGeneralCall
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN));
+}
+
+/**
+ * @brief Configure the Master to operate in 7-bit or 10-bit addressing mode.
+ * @note Changing this bit is not allowed, when the START bit is set.
+ * @rmtoll CR2 ADD10 LL_I2C_SetMasterAddressingMode
+ * @param I2Cx I2C Instance.
+ * @param AddressingMode This parameter can be one of the following values:
+ * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
+ * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode)
+{
+ MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode);
+}
+
+/**
+ * @brief Get the Master addressing mode.
+ * @rmtoll CR2 ADD10 LL_I2C_GetMasterAddressingMode
+ * @param I2Cx I2C Instance.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
+ * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
+}
+
+/**
+ * @brief Set the Own Address1.
+ * @rmtoll OAR1 OA1 LL_I2C_SetOwnAddress1\n
+ * OAR1 OA1MODE LL_I2C_SetOwnAddress1
+ * @param I2Cx I2C Instance.
+ * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
+ * @param OwnAddrSize This parameter can be one of the following values:
+ * @arg @ref LL_I2C_OWNADDRESS1_7BIT
+ * @arg @ref LL_I2C_OWNADDRESS1_10BIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
+{
+ MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize);
+}
+
+/**
+ * @brief Enable acknowledge on Own Address1 match address.
+ * @rmtoll OAR1 OA1EN LL_I2C_EnableOwnAddress1
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
+}
+
+/**
+ * @brief Disable acknowledge on Own Address1 match address.
+ * @rmtoll OAR1 OA1EN LL_I2C_DisableOwnAddress1
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
+}
+
+/**
+ * @brief Check if Own Address1 acknowledge is enabled or disabled.
+ * @rmtoll OAR1 OA1EN LL_I2C_IsEnabledOwnAddress1
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN));
+}
+
+/**
+ * @brief Set the 7bits Own Address2.
+ * @note This action has no effect if own address2 is enabled.
+ * @rmtoll OAR2 OA2 LL_I2C_SetOwnAddress2\n
+ * OAR2 OA2MSK LL_I2C_SetOwnAddress2
+ * @param I2Cx I2C Instance.
+ * @param OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F.
+ * @param OwnAddrMask This parameter can be one of the following values:
+ * @arg @ref LL_I2C_OWNADDRESS2_NOMASK
+ * @arg @ref LL_I2C_OWNADDRESS2_MASK01
+ * @arg @ref LL_I2C_OWNADDRESS2_MASK02
+ * @arg @ref LL_I2C_OWNADDRESS2_MASK03
+ * @arg @ref LL_I2C_OWNADDRESS2_MASK04
+ * @arg @ref LL_I2C_OWNADDRESS2_MASK05
+ * @arg @ref LL_I2C_OWNADDRESS2_MASK06
+ * @arg @ref LL_I2C_OWNADDRESS2_MASK07
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
+{
+ MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask);
+}
+
+/**
+ * @brief Enable acknowledge on Own Address2 match address.
+ * @rmtoll OAR2 OA2EN LL_I2C_EnableOwnAddress2
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
+}
+
+/**
+ * @brief Disable acknowledge on Own Address2 match address.
+ * @rmtoll OAR2 OA2EN LL_I2C_DisableOwnAddress2
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
+}
+
+/**
+ * @brief Check if Own Address1 acknowledge is enabled or disabled.
+ * @rmtoll OAR2 OA2EN LL_I2C_IsEnabledOwnAddress2
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN));
+}
+
+/**
+ * @brief Configure the SDA setup, hold time and the SCL high, low period.
+ * @note This bit can only be programmed when the I2C is disabled (PE = 0).
+ * @rmtoll TIMINGR TIMINGR LL_I2C_SetTiming
+ * @param I2Cx I2C Instance.
+ * @param Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
+ * @note This parameter is computed with the STM32CubeMX Tool.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing)
+{
+ WRITE_REG(I2Cx->TIMINGR, Timing);
+}
+
+/**
+ * @brief Get the Timing Prescaler setting.
+ * @rmtoll TIMINGR PRESC LL_I2C_GetTimingPrescaler
+ * @param I2Cx I2C Instance.
+ * @retval Value between Min_Data=0x0 and Max_Data=0xF
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos);
+}
+
+/**
+ * @brief Get the SCL low period setting.
+ * @rmtoll TIMINGR SCLL LL_I2C_GetClockLowPeriod
+ * @param I2Cx I2C Instance.
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos);
+}
+
+/**
+ * @brief Get the SCL high period setting.
+ * @rmtoll TIMINGR SCLH LL_I2C_GetClockHighPeriod
+ * @param I2Cx I2C Instance.
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos);
+}
+
+/**
+ * @brief Get the SDA hold time.
+ * @rmtoll TIMINGR SDADEL LL_I2C_GetDataHoldTime
+ * @param I2Cx I2C Instance.
+ * @retval Value between Min_Data=0x0 and Max_Data=0xF
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos);
+}
+
+/**
+ * @brief Get the SDA setup time.
+ * @rmtoll TIMINGR SCLDEL LL_I2C_GetDataSetupTime
+ * @param I2Cx I2C Instance.
+ * @retval Value between Min_Data=0x0 and Max_Data=0xF
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos);
+}
+
+/**
+ * @brief Configure peripheral mode.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll CR1 SMBHEN LL_I2C_SetMode\n
+ * CR1 SMBDEN LL_I2C_SetMode
+ * @param I2Cx I2C Instance.
+ * @param PeripheralMode This parameter can be one of the following values:
+ * @arg @ref LL_I2C_MODE_I2C
+ * @arg @ref LL_I2C_MODE_SMBUS_HOST
+ * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
+ * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
+{
+ MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode);
+}
+
+/**
+ * @brief Get peripheral mode.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll CR1 SMBHEN LL_I2C_GetMode\n
+ * CR1 SMBDEN LL_I2C_GetMode
+ * @param I2Cx I2C Instance.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2C_MODE_I2C
+ * @arg @ref LL_I2C_MODE_SMBUS_HOST
+ * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
+ * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN));
+}
+
+/**
+ * @brief Enable SMBus alert (Host or Device mode)
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note SMBus Device mode:
+ * - SMBus Alert pin is drived low and
+ * Alert Response Address Header acknowledge is enabled.
+ * SMBus Host mode:
+ * - SMBus Alert pin management is supported.
+ * @rmtoll CR1 ALERTEN LL_I2C_EnableSMBusAlert
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
+}
+
+/**
+ * @brief Disable SMBus alert (Host or Device mode)
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note SMBus Device mode:
+ * - SMBus Alert pin is not drived (can be used as a standard GPIO) and
+ * Alert Response Address Header acknowledge is disabled.
+ * SMBus Host mode:
+ * - SMBus Alert pin management is not supported.
+ * @rmtoll CR1 ALERTEN LL_I2C_DisableSMBusAlert
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
+}
+
+/**
+ * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN));
+}
+
+/**
+ * @brief Enable SMBus Packet Error Calculation (PEC).
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll CR1 PECEN LL_I2C_EnableSMBusPEC
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_PECEN);
+}
+
+/**
+ * @brief Disable SMBus Packet Error Calculation (PEC).
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll CR1 PECEN LL_I2C_DisableSMBusPEC
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN);
+}
+
+/**
+ * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll CR1 PECEN LL_I2C_IsEnabledSMBusPEC
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN));
+}
+
+/**
+ * @brief Configure the SMBus Clock Timeout.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
+ * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout\n
+ * TIMEOUTR TIDLE LL_I2C_ConfigSMBusTimeout\n
+ * TIMEOUTR TIMEOUTB LL_I2C_ConfigSMBusTimeout
+ * @param I2Cx I2C Instance.
+ * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
+ * @param TimeoutAMode This parameter can be one of the following values:
+ * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
+ * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
+ * @param TimeoutB
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode,
+ uint32_t TimeoutB)
+{
+ MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB,
+ TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos));
+}
+
+/**
+ * @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note These bits can only be programmed when TimeoutA is disabled.
+ * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA
+ * @param I2Cx I2C Instance.
+ * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA)
+{
+ WRITE_REG(I2Cx->TIMEOUTR, TimeoutA);
+}
+
+/**
+ * @brief Get the SMBus Clock TimeoutA setting.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA
+ * @param I2Cx I2C Instance.
+ * @retval Value between Min_Data=0 and Max_Data=0xFFF
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));
+}
+
+/**
+ * @brief Set the SMBus Clock TimeoutA mode.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note This bit can only be programmed when TimeoutA is disabled.
+ * @rmtoll TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode
+ * @param I2Cx I2C Instance.
+ * @param TimeoutAMode This parameter can be one of the following values:
+ * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
+ * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
+{
+ WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode);
+}
+
+/**
+ * @brief Get the SMBus Clock TimeoutA mode.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode
+ * @param I2Cx I2C Instance.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
+ * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));
+}
+
+/**
+ * @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note These bits can only be programmed when TimeoutB is disabled.
+ * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB
+ * @param I2Cx I2C Instance.
+ * @param TimeoutB This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB)
+{
+ WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos);
+}
+
+/**
+ * @brief Get the SMBus Extented Cumulative Clock TimeoutB setting.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB
+ * @param I2Cx I2C Instance.
+ * @retval Value between Min_Data=0 and Max_Data=0xFFF
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos);
+}
+
+/**
+ * @brief Enable the SMBus Clock Timeout.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout\n
+ * TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout
+ * @param I2Cx I2C Instance.
+ * @param ClockTimeout This parameter can be one of the following values:
+ * @arg @ref LL_I2C_SMBUS_TIMEOUTA
+ * @arg @ref LL_I2C_SMBUS_TIMEOUTB
+ * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
+{
+ SET_BIT(I2Cx->TIMEOUTR, ClockTimeout);
+}
+
+/**
+ * @brief Disable the SMBus Clock Timeout.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout\n
+ * TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout
+ * @param I2Cx I2C Instance.
+ * @param ClockTimeout This parameter can be one of the following values:
+ * @arg @ref LL_I2C_SMBUS_TIMEOUTA
+ * @arg @ref LL_I2C_SMBUS_TIMEOUTB
+ * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
+{
+ CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout);
+}
+
+/**
+ * @brief Check if the SMBus Clock Timeout is enabled or disabled.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout\n
+ * TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout
+ * @param I2Cx I2C Instance.
+ * @param ClockTimeout This parameter can be one of the following values:
+ * @arg @ref LL_I2C_SMBUS_TIMEOUTA
+ * @arg @ref LL_I2C_SMBUS_TIMEOUTB
+ * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
+{
+ return (READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == (ClockTimeout));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EF_IT_Management IT_Management
+ * @{
+ */
+
+/**
+ * @brief Enable TXIS interrupt.
+ * @rmtoll CR1 TXIE LL_I2C_EnableIT_TX
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_TXIE);
+}
+
+/**
+ * @brief Disable TXIS interrupt.
+ * @rmtoll CR1 TXIE LL_I2C_DisableIT_TX
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE);
+}
+
+/**
+ * @brief Check if the TXIS Interrupt is enabled or disabled.
+ * @rmtoll CR1 TXIE LL_I2C_IsEnabledIT_TX
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE));
+}
+
+/**
+ * @brief Enable RXNE interrupt.
+ * @rmtoll CR1 RXIE LL_I2C_EnableIT_RX
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_RXIE);
+}
+
+/**
+ * @brief Disable RXNE interrupt.
+ * @rmtoll CR1 RXIE LL_I2C_DisableIT_RX
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE);
+}
+
+/**
+ * @brief Check if the RXNE Interrupt is enabled or disabled.
+ * @rmtoll CR1 RXIE LL_I2C_IsEnabledIT_RX
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE));
+}
+
+/**
+ * @brief Enable Address match interrupt (slave mode only).
+ * @rmtoll CR1 ADDRIE LL_I2C_EnableIT_ADDR
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
+}
+
+/**
+ * @brief Disable Address match interrupt (slave mode only).
+ * @rmtoll CR1 ADDRIE LL_I2C_DisableIT_ADDR
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
+}
+
+/**
+ * @brief Check if Address match interrupt is enabled or disabled.
+ * @rmtoll CR1 ADDRIE LL_I2C_IsEnabledIT_ADDR
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE));
+}
+
+/**
+ * @brief Enable Not acknowledge received interrupt.
+ * @rmtoll CR1 NACKIE LL_I2C_EnableIT_NACK
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
+}
+
+/**
+ * @brief Disable Not acknowledge received interrupt.
+ * @rmtoll CR1 NACKIE LL_I2C_DisableIT_NACK
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
+}
+
+/**
+ * @brief Check if Not acknowledge received interrupt is enabled or disabled.
+ * @rmtoll CR1 NACKIE LL_I2C_IsEnabledIT_NACK
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE));
+}
+
+/**
+ * @brief Enable STOP detection interrupt.
+ * @rmtoll CR1 STOPIE LL_I2C_EnableIT_STOP
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
+}
+
+/**
+ * @brief Disable STOP detection interrupt.
+ * @rmtoll CR1 STOPIE LL_I2C_DisableIT_STOP
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
+}
+
+/**
+ * @brief Check if STOP detection interrupt is enabled or disabled.
+ * @rmtoll CR1 STOPIE LL_I2C_IsEnabledIT_STOP
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE));
+}
+
+/**
+ * @brief Enable Transfer Complete interrupt.
+ * @note Any of these events will generate interrupt :
+ * Transfer Complete (TC)
+ * Transfer Complete Reload (TCR)
+ * @rmtoll CR1 TCIE LL_I2C_EnableIT_TC
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_TCIE);
+}
+
+/**
+ * @brief Disable Transfer Complete interrupt.
+ * @note Any of these events will generate interrupt :
+ * Transfer Complete (TC)
+ * Transfer Complete Reload (TCR)
+ * @rmtoll CR1 TCIE LL_I2C_DisableIT_TC
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE);
+}
+
+/**
+ * @brief Check if Transfer Complete interrupt is enabled or disabled.
+ * @rmtoll CR1 TCIE LL_I2C_IsEnabledIT_TC
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE));
+}
+
+/**
+ * @brief Enable Error interrupts.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note Any of these errors will generate interrupt :
+ * Arbitration Loss (ARLO)
+ * Bus Error detection (BERR)
+ * Overrun/Underrun (OVR)
+ * SMBus Timeout detection (TIMEOUT)
+ * SMBus PEC error detection (PECERR)
+ * SMBus Alert pin event detection (ALERT)
+ * @rmtoll CR1 ERRIE LL_I2C_EnableIT_ERR
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
+}
+
+/**
+ * @brief Disable Error interrupts.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note Any of these errors will generate interrupt :
+ * Arbitration Loss (ARLO)
+ * Bus Error detection (BERR)
+ * Overrun/Underrun (OVR)
+ * SMBus Timeout detection (TIMEOUT)
+ * SMBus PEC error detection (PECERR)
+ * SMBus Alert pin event detection (ALERT)
+ * @rmtoll CR1 ERRIE LL_I2C_DisableIT_ERR
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
+}
+
+/**
+ * @brief Check if Error interrupts are enabled or disabled.
+ * @rmtoll CR1 ERRIE LL_I2C_IsEnabledIT_ERR
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EF_FLAG_management FLAG_management
+ * @{
+ */
+
+/**
+ * @brief Indicate the status of Transmit data register empty flag.
+ * @note RESET: When next data is written in Transmit data register.
+ * SET: When Transmit data register is empty.
+ * @rmtoll ISR TXE LL_I2C_IsActiveFlag_TXE
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE));
+}
+
+/**
+ * @brief Indicate the status of Transmit interrupt flag.
+ * @note RESET: When next data is written in Transmit data register.
+ * SET: When Transmit data register is empty.
+ * @rmtoll ISR TXIS LL_I2C_IsActiveFlag_TXIS
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS));
+}
+
+/**
+ * @brief Indicate the status of Receive data register not empty flag.
+ * @note RESET: When Receive data register is read.
+ * SET: When the received data is copied in Receive data register.
+ * @rmtoll ISR RXNE LL_I2C_IsActiveFlag_RXNE
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE));
+}
+
+/**
+ * @brief Indicate the status of Address matched flag (slave mode).
+ * @note RESET: Clear default value.
+ * SET: When the received slave address matched with one of the enabled slave address.
+ * @rmtoll ISR ADDR LL_I2C_IsActiveFlag_ADDR
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR));
+}
+
+/**
+ * @brief Indicate the status of Not Acknowledge received flag.
+ * @note RESET: Clear default value.
+ * SET: When a NACK is received after a byte transmission.
+ * @rmtoll ISR NACKF LL_I2C_IsActiveFlag_NACK
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF));
+}
+
+/**
+ * @brief Indicate the status of Stop detection flag.
+ * @note RESET: Clear default value.
+ * SET: When a Stop condition is detected.
+ * @rmtoll ISR STOPF LL_I2C_IsActiveFlag_STOP
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF));
+}
+
+/**
+ * @brief Indicate the status of Transfer complete flag (master mode).
+ * @note RESET: Clear default value.
+ * SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
+ * @rmtoll ISR TC LL_I2C_IsActiveFlag_TC
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC));
+}
+
+/**
+ * @brief Indicate the status of Transfer complete flag (master mode).
+ * @note RESET: Clear default value.
+ * SET: When RELOAD=1 and NBYTES date have been transferred.
+ * @rmtoll ISR TCR LL_I2C_IsActiveFlag_TCR
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR));
+}
+
+/**
+ * @brief Indicate the status of Bus error flag.
+ * @note RESET: Clear default value.
+ * SET: When a misplaced Start or Stop condition is detected.
+ * @rmtoll ISR BERR LL_I2C_IsActiveFlag_BERR
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR));
+}
+
+/**
+ * @brief Indicate the status of Arbitration lost flag.
+ * @note RESET: Clear default value.
+ * SET: When arbitration lost.
+ * @rmtoll ISR ARLO LL_I2C_IsActiveFlag_ARLO
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO));
+}
+
+/**
+ * @brief Indicate the status of Overrun/Underrun flag (slave mode).
+ * @note RESET: Clear default value.
+ * SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
+ * @rmtoll ISR OVR LL_I2C_IsActiveFlag_OVR
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR));
+}
+
+/**
+ * @brief Indicate the status of SMBus PEC error flag in reception.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note RESET: Clear default value.
+ * SET: When the received PEC does not match with the PEC register content.
+ * @rmtoll ISR PECERR LL_I2C_IsActiveSMBusFlag_PECERR
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR));
+}
+
+/**
+ * @brief Indicate the status of SMBus Timeout detection flag.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note RESET: Clear default value.
+ * SET: When a timeout or extended clock timeout occurs.
+ * @rmtoll ISR TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT));
+}
+
+/**
+ * @brief Indicate the status of SMBus alert flag.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note RESET: Clear default value.
+ * SET: When SMBus host configuration, SMBus alert enabled and
+ * a falling edge event occurs on SMBA pin.
+ * @rmtoll ISR ALERT LL_I2C_IsActiveSMBusFlag_ALERT
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT));
+}
+
+/**
+ * @brief Indicate the status of Bus Busy flag.
+ * @note RESET: Clear default value.
+ * SET: When a Start condition is detected.
+ * @rmtoll ISR BUSY LL_I2C_IsActiveFlag_BUSY
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY));
+}
+
+/**
+ * @brief Clear Address Matched flag.
+ * @rmtoll ICR ADDRCF LL_I2C_ClearFlag_ADDR
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF);
+}
+
+/**
+ * @brief Clear Not Acknowledge flag.
+ * @rmtoll ICR NACKCF LL_I2C_ClearFlag_NACK
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF);
+}
+
+/**
+ * @brief Clear Stop detection flag.
+ * @rmtoll ICR STOPCF LL_I2C_ClearFlag_STOP
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF);
+}
+
+/**
+ * @brief Clear Transmit data register empty flag (TXE).
+ * @note This bit can be clear by software in order to flush the transmit data register (TXDR).
+ * @rmtoll ISR TXE LL_I2C_ClearFlag_TXE
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx)
+{
+ WRITE_REG(I2Cx->ISR, I2C_ISR_TXE);
+}
+
+/**
+ * @brief Clear Bus error flag.
+ * @rmtoll ICR BERRCF LL_I2C_ClearFlag_BERR
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF);
+}
+
+/**
+ * @brief Clear Arbitration lost flag.
+ * @rmtoll ICR ARLOCF LL_I2C_ClearFlag_ARLO
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF);
+}
+
+/**
+ * @brief Clear Overrun/Underrun flag.
+ * @rmtoll ICR OVRCF LL_I2C_ClearFlag_OVR
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF);
+}
+
+/**
+ * @brief Clear SMBus PEC error flag.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll ICR PECCF LL_I2C_ClearSMBusFlag_PECERR
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->ICR, I2C_ICR_PECCF);
+}
+
+/**
+ * @brief Clear SMBus Timeout detection flag.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF);
+}
+
+/**
+ * @brief Clear SMBus Alert flag.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EF_Data_Management Data_Management
+ * @{
+ */
+
+/**
+ * @brief Enable automatic STOP condition generation (master mode).
+ * @note Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred.
+ * This bit has no effect in slave mode or when RELOAD bit is set.
+ * @rmtoll CR2 AUTOEND LL_I2C_EnableAutoEndMode
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
+}
+
+/**
+ * @brief Disable automatic STOP condition generation (master mode).
+ * @note Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
+ * @rmtoll CR2 AUTOEND LL_I2C_DisableAutoEndMode
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
+}
+
+/**
+ * @brief Check if automatic STOP condition is enabled or disabled.
+ * @rmtoll CR2 AUTOEND LL_I2C_IsEnabledAutoEndMode
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND));
+}
+
+/**
+ * @brief Enable reload mode (master mode).
+ * @note The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
+ * @rmtoll CR2 RELOAD LL_I2C_EnableReloadMode
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
+}
+
+/**
+ * @brief Disable reload mode (master mode).
+ * @note The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
+ * @rmtoll CR2 RELOAD LL_I2C_DisableReloadMode
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
+}
+
+/**
+ * @brief Check if reload mode is enabled or disabled.
+ * @rmtoll CR2 RELOAD LL_I2C_IsEnabledReloadMode
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD));
+}
+
+/**
+ * @brief Configure the number of bytes for transfer.
+ * @note Changing these bits when START bit is set is not allowed.
+ * @rmtoll CR2 NBYTES LL_I2C_SetTransferSize
+ * @param I2Cx I2C Instance.
+ * @param TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize)
+{
+ MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos);
+}
+
+/**
+ * @brief Get the number of bytes configured for transfer.
+ * @rmtoll CR2 NBYTES LL_I2C_GetTransferSize
+ * @param I2Cx I2C Instance.
+ * @retval Value between Min_Data=0x0 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos);
+}
+
+/**
+ * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
+ * @note Usage in Slave mode only.
+ * @rmtoll CR2 NACK LL_I2C_AcknowledgeNextData
+ * @param I2Cx I2C Instance.
+ * @param TypeAcknowledge This parameter can be one of the following values:
+ * @arg @ref LL_I2C_ACK
+ * @arg @ref LL_I2C_NACK
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
+{
+ MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge);
+}
+
+/**
+ * @brief Generate a START or RESTART condition
+ * @note The START bit can be set even if bus is BUSY or I2C is in slave mode.
+ * This action has no effect when RELOAD is set.
+ * @rmtoll CR2 START LL_I2C_GenerateStartCondition
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR2, I2C_CR2_START);
+}
+
+/**
+ * @brief Generate a STOP condition after the current byte transfer (master mode).
+ * @rmtoll CR2 STOP LL_I2C_GenerateStopCondition
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR2, I2C_CR2_STOP);
+}
+
+/**
+ * @brief Enable automatic RESTART Read request condition for 10bit address header (master mode).
+ * @note The master sends the complete 10bit slave address read sequence :
+ * Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address in Read direction.
+ * @rmtoll CR2 HEAD10R LL_I2C_EnableAuto10BitRead
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
+}
+
+/**
+ * @brief Disable automatic RESTART Read request condition for 10bit address header (master mode).
+ * @note The master only sends the first 7 bits of 10bit address in Read direction.
+ * @rmtoll CR2 HEAD10R LL_I2C_DisableAuto10BitRead
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
+}
+
+/**
+ * @brief Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
+ * @rmtoll CR2 HEAD10R LL_I2C_IsEnabledAuto10BitRead
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R));
+}
+
+/**
+ * @brief Configure the transfer direction (master mode).
+ * @note Changing these bits when START bit is set is not allowed.
+ * @rmtoll CR2 RD_WRN LL_I2C_SetTransferRequest
+ * @param I2Cx I2C Instance.
+ * @param TransferRequest This parameter can be one of the following values:
+ * @arg @ref LL_I2C_REQUEST_WRITE
+ * @arg @ref LL_I2C_REQUEST_READ
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest)
+{
+ MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest);
+}
+
+/**
+ * @brief Get the transfer direction requested (master mode).
+ * @rmtoll CR2 RD_WRN LL_I2C_GetTransferRequest
+ * @param I2Cx I2C Instance.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2C_REQUEST_WRITE
+ * @arg @ref LL_I2C_REQUEST_READ
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
+}
+
+/**
+ * @brief Configure the slave address for transfer (master mode).
+ * @note Changing these bits when START bit is set is not allowed.
+ * @rmtoll CR2 SADD LL_I2C_SetSlaveAddr
+ * @param I2Cx I2C Instance.
+ * @param SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
+{
+ MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr);
+}
+
+/**
+ * @brief Get the slave address programmed for transfer.
+ * @rmtoll CR2 SADD LL_I2C_GetSlaveAddr
+ * @param I2Cx I2C Instance.
+ * @retval Value between Min_Data=0x0 and Max_Data=0x3F
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
+}
+
+/**
+ * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
+ * @rmtoll CR2 SADD LL_I2C_HandleTransfer\n
+ * CR2 ADD10 LL_I2C_HandleTransfer\n
+ * CR2 RD_WRN LL_I2C_HandleTransfer\n
+ * CR2 START LL_I2C_HandleTransfer\n
+ * CR2 STOP LL_I2C_HandleTransfer\n
+ * CR2 RELOAD LL_I2C_HandleTransfer\n
+ * CR2 NBYTES LL_I2C_HandleTransfer\n
+ * CR2 AUTOEND LL_I2C_HandleTransfer\n
+ * CR2 HEAD10R LL_I2C_HandleTransfer
+ * @param I2Cx I2C Instance.
+ * @param SlaveAddr Specifies the slave address to be programmed.
+ * @param SlaveAddrSize This parameter can be one of the following values:
+ * @arg @ref LL_I2C_ADDRSLAVE_7BIT
+ * @arg @ref LL_I2C_ADDRSLAVE_10BIT
+ * @param TransferSize Specifies the number of bytes to be programmed.
+ * This parameter must be a value between Min_Data=0 and Max_Data=255.
+ * @param EndMode This parameter can be one of the following values:
+ * @arg @ref LL_I2C_MODE_RELOAD
+ * @arg @ref LL_I2C_MODE_AUTOEND
+ * @arg @ref LL_I2C_MODE_SOFTEND
+ * @arg @ref LL_I2C_MODE_SMBUS_RELOAD
+ * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC
+ * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC
+ * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC
+ * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC
+ * @param Request This parameter can be one of the following values:
+ * @arg @ref LL_I2C_GENERATE_NOSTARTSTOP
+ * @arg @ref LL_I2C_GENERATE_STOP
+ * @arg @ref LL_I2C_GENERATE_START_READ
+ * @arg @ref LL_I2C_GENERATE_START_WRITE
+ * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ
+ * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE
+ * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ
+ * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
+ uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
+{
+ MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
+ I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
+ SlaveAddr | SlaveAddrSize | TransferSize << I2C_CR2_NBYTES_Pos | EndMode | Request);
+}
+
+/**
+ * @brief Indicate the value of transfer direction (slave mode).
+ * @note RESET: Write transfer, Slave enters in receiver mode.
+ * SET: Read transfer, Slave enters in transmitter mode.
+ * @rmtoll ISR DIR LL_I2C_GetTransferDirection
+ * @param I2Cx I2C Instance.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2C_DIRECTION_WRITE
+ * @arg @ref LL_I2C_DIRECTION_READ
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
+}
+
+/**
+ * @brief Return the slave matched address.
+ * @rmtoll ISR ADDCODE LL_I2C_GetAddressMatchCode
+ * @param I2Cx I2C Instance.
+ * @retval Value between Min_Data=0x00 and Max_Data=0x3F
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1);
+}
+
+/**
+ * @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received.
+ * This bit has no effect when RELOAD bit is set.
+ * This bit has no effect in device mode when SBC bit is not set.
+ * @rmtoll CR2 PECBYTE LL_I2C_EnableSMBusPECCompare
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE);
+}
+
+/**
+ * @brief Check if the SMBus Packet Error byte internal comparison is requested or not.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE));
+}
+
+/**
+ * @brief Get the SMBus Packet Error byte calculated.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll PECR PEC LL_I2C_GetSMBusPEC
+ * @param I2Cx I2C Instance.
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+*/
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
+}
+
+/**
+ * @brief Read Receive Data register.
+ * @rmtoll RXDR RXDATA LL_I2C_ReceiveData8
+ * @param I2Cx I2C Instance.
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
+{
+ return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
+}
+
+/**
+ * @brief Write in Transmit Data Register .
+ * @rmtoll TXDR TXDATA LL_I2C_TransmitData8
+ * @param I2Cx I2C Instance.
+ * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
+{
+ WRITE_REG(I2Cx->TXDR, Data);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
+uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx);
+void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
+
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* I2C1 || I2C2 || I2C3 */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_LL_I2C_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_ll_iwdg.h b/Inc/stm32f3xx_ll_iwdg.h
new file mode 100644
index 0000000..d5bcc9d
--- /dev/null
+++ b/Inc/stm32f3xx_ll_iwdg.h
@@ -0,0 +1,361 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_iwdg.h
+ * @author MCD Application Team
+ * @brief Header file of IWDG LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_LL_IWDG_H
+#define __STM32F3xx_LL_IWDG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx.h"
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined(IWDG)
+
+/** @defgroup IWDG_LL IWDG
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup IWDG_LL_Private_Constants IWDG Private Constants
+ * @{
+ */
+
+#define LL_IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */
+#define LL_IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */
+#define LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */
+#define LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup IWDG_LL_Exported_Constants IWDG Exported Constants
+ * @{
+ */
+
+/** @defgroup IWDG_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_IWDG_ReadReg function
+ * @{
+ */
+#define LL_IWDG_SR_PVU IWDG_SR_PVU /*!< Watchdog prescaler value update */
+#define LL_IWDG_SR_RVU IWDG_SR_RVU /*!< Watchdog counter reload value update */
+#define LL_IWDG_SR_WVU IWDG_SR_WVU /*!< Watchdog counter window value update */
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_LL_EC_PRESCALER Prescaler Divider
+ * @{
+ */
+#define LL_IWDG_PRESCALER_4 0x00000000U /*!< Divider by 4 */
+#define LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0) /*!< Divider by 8 */
+#define LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1) /*!< Divider by 16 */
+#define LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< Divider by 32 */
+#define LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2) /*!< Divider by 64 */
+#define LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< Divider by 128 */
+#define LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< Divider by 256 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup IWDG_LL_Exported_Macros IWDG Exported Macros
+ * @{
+ */
+
+/** @defgroup IWDG_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in IWDG register
+ * @param __INSTANCE__ IWDG Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in IWDG register
+ * @param __INSTANCE__ IWDG Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup IWDG_LL_Exported_Functions IWDG Exported Functions
+ * @{
+ */
+/** @defgroup IWDG_LL_EF_Configuration Configuration
+ * @{
+ */
+
+/**
+ * @brief Start the Independent Watchdog
+ * @note Except if the hardware watchdog option is selected
+ * @rmtoll KR KEY LL_IWDG_Enable
+ * @param IWDGx IWDG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx)
+{
+ WRITE_REG(IWDG->KR, LL_IWDG_KEY_ENABLE);
+}
+
+/**
+ * @brief Reloads IWDG counter with value defined in the reload register
+ * @rmtoll KR KEY LL_IWDG_ReloadCounter
+ * @param IWDGx IWDG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx)
+{
+ WRITE_REG(IWDG->KR, LL_IWDG_KEY_RELOAD);
+}
+
+/**
+ * @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
+ * @rmtoll KR KEY LL_IWDG_EnableWriteAccess
+ * @param IWDGx IWDG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx)
+{
+ WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE);
+}
+
+/**
+ * @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
+ * @rmtoll KR KEY LL_IWDG_DisableWriteAccess
+ * @param IWDGx IWDG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx)
+{
+ WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE);
+}
+
+/**
+ * @brief Select the prescaler of the IWDG
+ * @rmtoll PR PR LL_IWDG_SetPrescaler
+ * @param IWDGx IWDG Instance
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_IWDG_PRESCALER_4
+ * @arg @ref LL_IWDG_PRESCALER_8
+ * @arg @ref LL_IWDG_PRESCALER_16
+ * @arg @ref LL_IWDG_PRESCALER_32
+ * @arg @ref LL_IWDG_PRESCALER_64
+ * @arg @ref LL_IWDG_PRESCALER_128
+ * @arg @ref LL_IWDG_PRESCALER_256
+ * @retval None
+ */
+__STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescaler)
+{
+ WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler);
+}
+
+/**
+ * @brief Get the selected prescaler of the IWDG
+ * @rmtoll PR PR LL_IWDG_GetPrescaler
+ * @param IWDGx IWDG Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_IWDG_PRESCALER_4
+ * @arg @ref LL_IWDG_PRESCALER_8
+ * @arg @ref LL_IWDG_PRESCALER_16
+ * @arg @ref LL_IWDG_PRESCALER_32
+ * @arg @ref LL_IWDG_PRESCALER_64
+ * @arg @ref LL_IWDG_PRESCALER_128
+ * @arg @ref LL_IWDG_PRESCALER_256
+ */
+__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx)
+{
+ return (uint32_t)(READ_REG(IWDGx->PR));
+}
+
+/**
+ * @brief Specify the IWDG down-counter reload value
+ * @rmtoll RLR RL LL_IWDG_SetReloadCounter
+ * @param IWDGx IWDG Instance
+ * @param Counter Value between Min_Data=0 and Max_Data=0x0FFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Counter)
+{
+ WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter);
+}
+
+/**
+ * @brief Get the specified IWDG down-counter reload value
+ * @rmtoll RLR RL LL_IWDG_GetReloadCounter
+ * @param IWDGx IWDG Instance
+ * @retval Value between Min_Data=0 and Max_Data=0x0FFF
+ */
+__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx)
+{
+ return (uint32_t)(READ_REG(IWDGx->RLR));
+}
+
+/**
+ * @brief Specify high limit of the window value to be compared to the down-counter.
+ * @rmtoll WINR WIN LL_IWDG_SetWindow
+ * @param IWDGx IWDG Instance
+ * @param Window Value between Min_Data=0 and Max_Data=0x0FFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_IWDG_SetWindow(IWDG_TypeDef *IWDGx, uint32_t Window)
+{
+ WRITE_REG(IWDGx->WINR, IWDG_WINR_WIN & Window);
+}
+
+/**
+ * @brief Get the high limit of the window value specified.
+ * @rmtoll WINR WIN LL_IWDG_GetWindow
+ * @param IWDGx IWDG Instance
+ * @retval Value between Min_Data=0 and Max_Data=0x0FFF
+ */
+__STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx)
+{
+ return (uint32_t)(READ_REG(IWDGx->WINR));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+
+/**
+ * @brief Check if flag Prescaler Value Update is set or not
+ * @rmtoll SR PVU LL_IWDG_IsActiveFlag_PVU
+ * @param IWDGx IWDG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx)
+{
+ return (READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU));
+}
+
+/**
+ * @brief Check if flag Reload Value Update is set or not
+ * @rmtoll SR RVU LL_IWDG_IsActiveFlag_RVU
+ * @param IWDGx IWDG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx)
+{
+ return (READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU));
+}
+
+/**
+ * @brief Check if flag Window Value Update is set or not
+ * @rmtoll SR WVU LL_IWDG_IsActiveFlag_WVU
+ * @param IWDGx IWDG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx)
+{
+ return (READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU));
+}
+
+/**
+ * @brief Check if all flags Prescaler, Reload & Window Value Update are reset or not
+ * @rmtoll SR PVU LL_IWDG_IsReady\n
+ * SR WVU LL_IWDG_IsReady\n
+ * SR RVU LL_IWDG_IsReady
+ * @param IWDGx IWDG Instance
+ * @retval State of bits (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
+{
+ return (READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU) == 0U);
+}
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* IWDG) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_LL_IWDG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_ll_opamp.h b/Inc/stm32f3xx_ll_opamp.h
new file mode 100644
index 0000000..cb20141
--- /dev/null
+++ b/Inc/stm32f3xx_ll_opamp.h
@@ -0,0 +1,903 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_opamp.h
+ * @author MCD Application Team
+ * @brief Header file of OPAMP LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_LL_OPAMP_H
+#define __STM32F3xx_LL_OPAMP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx.h"
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined (OPAMP1) || defined (OPAMP2) || defined (OPAMP3) || defined (OPAMP4)
+
+/** @defgroup OPAMP_LL OPAMP
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup OPAMP_LL_Private_Constants OPAMP Private Constants
+ * @{
+ */
+
+/* Internal mask for OPAMP trimming of transistors differential pair NMOS */
+/* or PMOS. */
+/* To select into literal LL_OPAMP_TRIMMING_x the relevant bits for: */
+/* - OPAMP trimming selection of transistors differential pair */
+/* - OPAMP trimming values of transistors differential pair */
+#define OPAMP_TRIMMING_SELECT_MASK (OPAMP_CSR_CALSEL)
+#define OPAMP_TRIMMING_VALUE_MASK (OPAMP_CSR_TRIMOFFSETN | OPAMP_CSR_TRIMOFFSETP)
+
+/**
+ * @}
+ */
+
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup OPAMP_LL_Private_Macros OPAMP Private Macros
+ * @{
+ */
+
+/**
+ * @brief Driver macro reserved for internal use: set a pointer to
+ * a register from a register basis from which an offset
+ * is applied.
+ * @param __REG__ Register basis from which the offset is applied.
+ * @param __REG_OFFSET__ Offset to be applied (unit: number of registers).
+ * @retval Register address
+*/
+#define __OPAMP_PTR_REG_OFFSET(__REG__, __REG_OFFSET__) \
+ ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFSET__) << 2U))))
+
+
+
+
+/**
+ * @}
+ */
+
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup OPAMP_LL_ES_INIT OPAMP Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief Structure definition of some features of OPAMP instance.
+ */
+typedef struct
+{
+ uint32_t FunctionalMode; /*!< Set OPAMP functional mode by setting internal connections: OPAMP operation in standalone, follower, ...
+ This parameter can be a value of @ref OPAMP_LL_EC_FUNCTIONAL_MODE
+ @note If OPAMP is configured in mode PGA, the gain can be configured using function @ref LL_OPAMP_SetPGAGain().
+
+ This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetFunctionalMode(). */
+
+ uint32_t InputNonInverting; /*!< Set OPAMP input non-inverting connection.
+ This parameter can be a value of @ref OPAMP_LL_EC_INPUT_NONINVERTING
+
+ This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetInputNonInverting(). */
+
+ uint32_t InputInverting; /*!< Set OPAMP inverting input connection.
+ This parameter can be a value of @ref OPAMP_LL_EC_INPUT_INVERTING
+ @note OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin), this parameter is discarded.
+
+ This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetInputInverting(). */
+
+} LL_OPAMP_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup OPAMP_LL_Exported_Constants OPAMP Exported Constants
+ * @{
+ */
+
+/** @defgroup OPAMP_LL_EC_MODE OPAMP mode calibration or functional.
+ * @{
+ */
+#define LL_OPAMP_MODE_FUNCTIONAL ((uint32_t)0x00000000U) /*!< OPAMP functional mode */
+#define LL_OPAMP_MODE_CALIBRATION (OPAMP_CSR_CALON) /*!< OPAMP calibration mode */
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_LL_EC_FUNCTIONAL_MODE OPAMP functional mode
+ * @{
+ */
+#define LL_OPAMP_MODE_STANDALONE ((uint32_t)0x00000000U) /*!< OPAMP functional mode, OPAMP operation in standalone */
+#define LL_OPAMP_MODE_FOLLOWER (OPAMP_CSR_VMSEL_1 | OPAMP_CSR_VMSEL_0) /*!< OPAMP functional mode, OPAMP operation in follower */
+#define LL_OPAMP_MODE_PGA (OPAMP_CSR_VMSEL_1) /*!< OPAMP functional mode, OPAMP operation in PGA */
+#define LL_OPAMP_MODE_PGA_EXT_FILT_IO0 (OPAMP_CSR_PGGAIN_3 | OPAMP_CSR_VMSEL_1) /*!< OPAMP functional mode, OPAMP operation in PGA with external filtering on OPAMP input IO0. */
+#define LL_OPAMP_MODE_PGA_EXT_FILT_IO1 (OPAMP_CSR_PGGAIN_3 | OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_VMSEL_1) /*!< OPAMP functional mode, OPAMP operation in PGA with external filtering on OPAMP input IO1. */
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_LL_EC_MODE_PGA_GAIN OPAMP PGA gain (relevant when OPAMP is in functional mode PGA)
+ * @{
+ */
+#define LL_OPAMP_PGA_GAIN_2 ((uint32_t)0x00000000U) /*!< OPAMP PGA gain 2 */
+#define LL_OPAMP_PGA_GAIN_4 (OPAMP_CSR_PGGAIN_0) /*!< OPAMP PGA gain 4 */
+#define LL_OPAMP_PGA_GAIN_8 (OPAMP_CSR_PGGAIN_1) /*!< OPAMP PGA gain 8 */
+#define LL_OPAMP_PGA_GAIN_16 (OPAMP_CSR_PGGAIN_1 | OPAMP_CSR_PGGAIN_0 ) /*!< OPAMP PGA gain 16 */
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_LL_EC_INPUT_NONINVERTING OPAMP input non-inverting
+ * @{
+ */
+#define LL_OPAMP_INPUT_NONINVERT_IO0 (OPAMP_CSR_VPSEL) /*!< OPAMP non inverting input connected to GPIO pin (pin PA1 for OPAMP1, pin PA7 for OPAMP2, pin PB0 for OPAMP3, pin PB13 for OPAMP4) */
+#define LL_OPAMP_INPUT_NONINVERT_IO1 ((uint32_t)0x00000000) /*!< OPAMP non inverting input connected to GPIO pin (pin PA7 for OPAMP1, pin PD14 for OPAMP2, pin PB13 for OPAMP3, pin PD11 for OPAMP4) */
+#define LL_OPAMP_INPUT_NONINVERT_IO2 (OPAMP_CSR_VPSEL_1) /*!< OPAMP non inverting input connected to GPIO pin (pin PA3 for OPAMP1, pin PB0 for OPAMP2, pin PA1 for OPAMP3, pin PB11 for OPAMP4) */
+#define LL_OPAMP_INPUT_NONINVERT_IO3 (OPAMP_CSR_VPSEL_0) /*!< OPAMP non inverting input connected to GPIO pin (pin PA5 for OPAMP1, pin PB14 for OPAMP2, pin PA5 for OPAMP3, pin PA4 for OPAMP4) */
+#define LL_OPAMP_INPUT_NONINV_DAC1_CH1 (LL_OPAMP_INPUT_NONINVERT_IO3) /*!< OPAMP non inverting input connected to DAC1 channel1 output (specific to OPAMP instances: OPAMP4) */
+#define LL_OPAMP_INPUT_NONINV_DAC1_CH2 (LL_OPAMP_INPUT_NONINVERT_IO3) /*!< OPAMP non inverting input connected to DAC1 channel2 output (specific to OPAMP instances: OPAMP1, OPAMP3) */
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_LL_EC_INPUT_INVERTING OPAMP input inverting
+ * @{
+ */
+#define LL_OPAMP_INPUT_INVERT_IO0 ((uint32_t)0x00000000U) /*!< OPAMP inverting input connected to GPIO pin (pin PC5 for OPAMP1, pin PC5 for OPAMP2, pin PB10 for OPAMP3, pin PB10 for OPAMP4). Note: OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin). */
+#define LL_OPAMP_INPUT_INVERT_IO1 (OPAMP_CSR_VMSEL_0) /*!< OPAMP inverting input connected to GPIO pin (pin PA3 for OPAMP1, pin PA5 for OPAMP2, pin PB2 for OPAMP3, pin PD8 for OPAMP4). Note: OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin). */
+#define LL_OPAMP_INPUT_INVERT_CONNECT_NO (OPAMP_CSR_VMSEL_1) /*!< OPAMP inverting input not externally connected (intended for OPAMP in mode follower or PGA without external capacitors for filtering). Note: On this STM32 serie, this literal include cases of value 0x11 for mode follower and value 0x10 for mode PGA. */
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_LL_EC_INPUT_NONINVERTING_SECONDARY OPAMP input non-inverting secondary
+ * @{
+ */
+#define LL_OPAMP_INPUT_NONINVERT_IO0_SEC (LL_OPAMP_INPUT_NONINVERT_IO0 << (OPAMP_CSR_VPSSEL_Pos - OPAMP_CSR_VPSEL_Pos)) /*!< OPAMP non inverting input secondary connected to GPIO pin (pin PA1 for OPAMP1, pin PA7 for OPAMP2, pin PB0 for OPAMP3, pin PB13 for OPAMP4) */
+#define LL_OPAMP_INPUT_NONINVERT_IO1_SEC (LL_OPAMP_INPUT_NONINVERT_IO1 << (OPAMP_CSR_VPSSEL_Pos - OPAMP_CSR_VPSEL_Pos)) /*!< OPAMP non inverting input secondary connected to GPIO pin (pin PA7 for OPAMP1, pin PD14 for OPAMP2, pin PB13 for OPAMP3, pin PD11 for OPAMP4) */
+#define LL_OPAMP_INPUT_NONINVERT_IO2_SEC (LL_OPAMP_INPUT_NONINVERT_IO2 << (OPAMP_CSR_VPSSEL_Pos - OPAMP_CSR_VPSEL_Pos)) /*!< OPAMP non inverting input secondary connected to GPIO pin (pin PA3 for OPAMP1, pin PB0 for OPAMP2, pin PA1 for OPAMP3, pin PB11 for OPAMP4) */
+#define LL_OPAMP_INPUT_NONINVERT_IO3_SEC (LL_OPAMP_INPUT_NONINVERT_IO3 << (OPAMP_CSR_VPSSEL_Pos - OPAMP_CSR_VPSEL_Pos)) /*!< OPAMP non inverting input secondary connected to GPIO pin (pin PA5 for OPAMP1, pin PD14 for OPAMP2, pin PA5 for OPAMP3, pin PA4 for OPAMP4) */
+#define LL_OPAMP_INPUT_NONINV_DAC1_CH1_SEC (LL_OPAMP_INPUT_NONINV_DAC1_CH1 << (OPAMP_CSR_VPSSEL_Pos - OPAMP_CSR_VPSEL_Pos)) /*!< OPAMP non inverting input secondary connected to DAC1 channel1 output (specific to OPAMP instances: OPAMP4) */
+#define LL_OPAMP_INPUT_NONINV_DAC1_CH2_SEC (LL_OPAMP_INPUT_NONINV_DAC1_CH2 << (OPAMP_CSR_VPSSEL_Pos - OPAMP_CSR_VPSEL_Pos)) /*!< OPAMP non inverting input secondary connected to DAC1 channel2 output (specific to OPAMP instances: OPAMP1, OPAMP3) */
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_LL_EC_INPUT_INVERTING_SECONDARY OPAMP input inverting secondary
+ * @{
+ */
+#define LL_OPAMP_INPUT_INVERT_IO0_SEC (LL_OPAMP_INPUT_INVERT_IO0 << (OPAMP_CSR_VMSSEL_Pos - OPAMP_CSR_VMSEL_Pos)) /*!< OPAMP inverting input secondary connected to GPIO pin (pin PC5 for OPAMP1, pin PC5 for OPAMP2, pin PB10 for OPAMP3, pin PB10 for OPAMP4). Note: OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin). */
+#define LL_OPAMP_INPUT_INVERT_IO1_SEC (LL_OPAMP_INPUT_INVERT_IO1 << (OPAMP_CSR_VMSSEL_Pos - OPAMP_CSR_VMSEL_Pos)) /*!< OPAMP inverting input secondary connected to GPIO pin (pin PA3 for OPAMP1, pin PA5 for OPAMP2, pin PB2 for OPAMP3, pin PD8 for OPAMP4). Note: OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin). */
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_LL_EC_INPUT_MUX_MODE OPAMP inputs multiplexer mode
+ * @{
+ */
+#define LL_OPAMP_INPUT_MUX_DISABLE ((uint32_t)0x00000000U) /*!< OPAMP inputs multiplexer mode dosabled. */
+#define LL_OPAMP_INPUT_MUX_TIM1_CH6 (OPAMP_CSR_TCMEN) /*!< OPAMP inputs multiplexer mode enabled, controlled by TIM1 CC6. */
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_LL_EC_VREF_OUTPUT OPAMP internal reference voltage path state to output
+ * @{
+ */
+#define LL_OPAMP_VREF_OUTPUT_DISABLE ((uint32_t)0x00000000U) /*!< OPAMP internal reference voltage path to output is disabled. */
+#define LL_OPAMP_VREF_OUTPUT_ENABLE (OPAMP_CSR_TSTREF) /*!< OPAMP internal reference voltage path to output is enabled. */
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_LL_EC_TRIMMING_MODE OPAMP trimming mode
+ * @{
+ */
+#define LL_OPAMP_TRIMMING_FACTORY ((uint32_t)0x00000000U) /*!< OPAMP trimming factors set to factory values */
+#define LL_OPAMP_TRIMMING_USER (OPAMP_CSR_USERTRIM) /*!< OPAMP trimming factors set to user values */
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_LL_EC_TRIMMING_TRANSISTORS_DIFF_PAIR OPAMP trimming of transistors differential pair NMOS or PMOS
+ * @{
+ */
+#define LL_OPAMP_TRIMMING_NMOS_VREF_90PC_VDDA (OPAMP_CSR_TRIMOFFSETN | OPAMP_CSR_CALSEL_1 | OPAMP_CSR_CALSEL_0) /*!< OPAMP trimming of transistors differential pair NMOS (internal reference voltage set to 0.9*Vdda). Default parameters to be used for calibration using two trimming steps (one with each transistors differential pair NMOS and PMOS). */
+#define LL_OPAMP_TRIMMING_NMOS_VREF_50PC_VDDA (OPAMP_CSR_TRIMOFFSETN | OPAMP_CSR_CALSEL_1 ) /*!< OPAMP trimming of transistors differential pair NMOS (internal reference voltage set to 0.5*Vdda). */
+#define LL_OPAMP_TRIMMING_PMOS_VREF_10PC_VDDA (OPAMP_CSR_TRIMOFFSETP | OPAMP_CSR_CALSEL_0) /*!< OPAMP trimming of transistors differential pair PMOS (internal reference voltage set to 0.1*Vdda). Default parameters to be used for calibration using two trimming steps (one with each transistors differential pair NMOS and PMOS). */
+#define LL_OPAMP_TRIMMING_PMOS_VREF_3_3PC_VDDA (OPAMP_CSR_TRIMOFFSETP ) /*!< OPAMP trimming of transistors differential pair PMOS (internal reference voltage set to 0.33*Vdda). */
+#define LL_OPAMP_TRIMMING_NMOS (LL_OPAMP_TRIMMING_NMOS_VREF_90PC_VDDA) /*!< OPAMP trimming of transistors differential pair NMOS (internal reference voltage set to 0.9*Vdda). Default parameters to be used for calibration using two trimming steps (one with each transistors differential pair NMOS and PMOS). */
+#define LL_OPAMP_TRIMMING_PMOS (LL_OPAMP_TRIMMING_PMOS_VREF_10PC_VDDA) /*!< OPAMP trimming of transistors differential pair PMOS (internal reference voltage set to 0.1*Vdda). Default parameters to be used for calibration using two trimming steps (one with each transistors differential pair NMOS and PMOS). */
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_LL_EC_HW_DELAYS Definitions of OPAMP hardware constraints delays
+ * @note Only OPAMP IP HW delays are defined in OPAMP LL driver driver,
+ * not timeout values.
+ * For details on delays values, refer to descriptions in source code
+ * above each literal definition.
+ * @{
+ */
+
+/* Delay for OPAMP startup time (transition from state disable to enable). */
+/* Note: OPAMP startup time depends on board application environment: */
+/* impedance connected to OPAMP output. */
+/* The delay below is specified under conditions: */
+/* - OPAMP in functional mode follower */
+/* - load impedance of 4kOhm (min), 50pF (max) */
+/* Literal set to maximum value (refer to device datasheet, */
+/* parameter "tWAKEUP"). */
+/* Unit: us */
+#define LL_OPAMP_DELAY_STARTUP_US ((uint32_t) 5U) /*!< Delay for OPAMP startup time */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup OPAMP_LL_Exported_Macros OPAMP Exported Macros
+ * @{
+ */
+/** @defgroup OPAMP_LL_EM_WRITE_READ Common write and read registers macro
+ * @{
+ */
+/**
+ * @brief Write a value in OPAMP register
+ * @param __INSTANCE__ OPAMP Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_OPAMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in OPAMP register
+ * @param __INSTANCE__ OPAMP Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_OPAMP_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup OPAMP_LL_Exported_Functions OPAMP Exported Functions
+ * @{
+ */
+
+/** @defgroup OPAMP_LL_EF_CONFIGURATION_OPAMP_INSTANCE Configuration of OPAMP hierarchical scope: OPAMP instance
+ * @{
+ */
+
+/**
+ * @brief Set OPAMP mode calibration or functional.
+ * @note OPAMP mode corresponds to functional or calibration mode:
+ * - functional mode: OPAMP operation in standalone, follower, ...
+ * Set functional mode using function
+ * @ref LL_OPAMP_SetFunctionalMode().
+ * - calibration mode: offset calibration of the selected
+ * transistors differential pair NMOS or PMOS.
+ * @rmtoll CSR CALON LL_OPAMP_SetMode
+ * @param OPAMPx OPAMP instance
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_OPAMP_MODE_FUNCTIONAL
+ * @arg @ref LL_OPAMP_MODE_CALIBRATION
+ * @retval None
+ */
+__STATIC_INLINE void LL_OPAMP_SetMode(OPAMP_TypeDef *OPAMPx, uint32_t Mode)
+{
+ MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_CALON, Mode);
+}
+
+/**
+ * @brief Get OPAMP mode calibration or functional.
+ * @note OPAMP mode corresponds to functional or calibration mode:
+ * - functional mode: OPAMP operation in standalone, follower, ...
+ * Set functional mode using function
+ * @ref LL_OPAMP_SetFunctionalMode().
+ * - calibration mode: offset calibration of the selected
+ * transistors differential pair NMOS or PMOS.
+ * @rmtoll CSR CALON LL_OPAMP_GetMode
+ * @param OPAMPx OPAMP instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_OPAMP_MODE_FUNCTIONAL
+ * @arg @ref LL_OPAMP_MODE_CALIBRATION
+ */
+__STATIC_INLINE uint32_t LL_OPAMP_GetMode(OPAMP_TypeDef *OPAMPx)
+{
+ return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALON));
+}
+
+/**
+ * @brief Set OPAMP functional mode by setting internal connections.
+ * OPAMP operation in standalone, follower, ...
+ * @note This function reset bit of calibration mode to ensure
+ * to be in functional mode, in order to have OPAMP parameters
+ * (inputs selection, ...) set with the corresponding OPAMP mode
+ * to be effective.
+ * @rmtoll CSR VMSEL LL_OPAMP_SetFunctionalMode
+ * @param OPAMPx OPAMP instance
+ * @param FunctionalMode This parameter can be one of the following values:
+ * @arg @ref LL_OPAMP_MODE_STANDALONE
+ * @arg @ref LL_OPAMP_MODE_FOLLOWER
+ * @arg @ref LL_OPAMP_MODE_PGA
+ * @arg @ref LL_OPAMP_MODE_PGA_EXT_FILT_IO0
+ * @arg @ref LL_OPAMP_MODE_PGA_EXT_FILT_IO1
+ * @retval None
+ */
+__STATIC_INLINE void LL_OPAMP_SetFunctionalMode(OPAMP_TypeDef *OPAMPx, uint32_t FunctionalMode)
+{
+ /* Note: Bit OPAMP_CSR_CALON reset to ensure to be in functional mode */
+ MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_PGGAIN_3 | OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_VMSEL | OPAMP_CSR_CALON, FunctionalMode);
+}
+
+/**
+ * @brief Get OPAMP functional mode from setting of internal connections.
+ * OPAMP operation in standalone, follower, ...
+ * @rmtoll CSR VMSEL LL_OPAMP_GetFunctionalMode
+ * @param OPAMPx OPAMP instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_OPAMP_MODE_STANDALONE
+ * @arg @ref LL_OPAMP_MODE_FOLLOWER
+ * @arg @ref LL_OPAMP_MODE_PGA
+ * @arg @ref LL_OPAMP_MODE_PGA_EXT_FILT_IO0
+ * @arg @ref LL_OPAMP_MODE_PGA_EXT_FILT_IO1
+ */
+__STATIC_INLINE uint32_t LL_OPAMP_GetFunctionalMode(OPAMP_TypeDef *OPAMPx)
+{
+ return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_PGGAIN_3 | OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_VMSEL));
+}
+
+/**
+ * @brief Set OPAMP PGA gain.
+ * @note Preliminarily, OPAMP must be set in mode PGA
+ * using function @ref LL_OPAMP_SetFunctionalMode().
+ * @rmtoll CSR PGGAIN LL_OPAMP_SetPGAGain
+ * @param OPAMPx OPAMP instance
+ * @param PGAGain This parameter can be one of the following values:
+ * @arg @ref LL_OPAMP_PGA_GAIN_2
+ * @arg @ref LL_OPAMP_PGA_GAIN_4
+ * @arg @ref LL_OPAMP_PGA_GAIN_8
+ * @arg @ref LL_OPAMP_PGA_GAIN_16
+ * @retval None
+ */
+__STATIC_INLINE void LL_OPAMP_SetPGAGain(OPAMP_TypeDef *OPAMPx, uint32_t PGAGain)
+{
+ MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_PGGAIN_1 | OPAMP_CSR_PGGAIN_0, PGAGain);
+}
+
+/**
+ * @brief Get OPAMP PGA gain.
+ * @note Preliminarily, OPAMP must be set in mode PGA
+ * using function @ref LL_OPAMP_SetFunctionalMode().
+ * @rmtoll CSR PGGAIN LL_OPAMP_GetPGAGain
+ * @param OPAMPx OPAMP instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_OPAMP_PGA_GAIN_2
+ * @arg @ref LL_OPAMP_PGA_GAIN_4
+ * @arg @ref LL_OPAMP_PGA_GAIN_8
+ * @arg @ref LL_OPAMP_PGA_GAIN_16
+ */
+__STATIC_INLINE uint32_t LL_OPAMP_GetPGAGain(OPAMP_TypeDef *OPAMPx)
+{
+ return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_PGGAIN_1 | OPAMP_CSR_PGGAIN_0));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_LL_EF_CONFIGURATION_INPUTS Configuration of OPAMP inputs
+ * @{
+ */
+
+/**
+ * @brief Set OPAMP non-inverting input connection.
+ * @rmtoll CSR VPSEL LL_OPAMP_SetInputNonInverting
+ * @param OPAMPx OPAMP instance
+ * @param InputNonInverting This parameter can be one of the following values:
+ * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0
+ * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO1
+ * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO2
+ * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO3
+ * @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH1 (1)
+ * @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH2 (2)
+ *
+ * (1) Parameter specific to OPAMP instances: OPAMP4.\n
+ * (2) Parameter specific to OPAMP instances: OPAMP1, OPAMP3.
+ * @retval None
+ */
+__STATIC_INLINE void LL_OPAMP_SetInputNonInverting(OPAMP_TypeDef *OPAMPx, uint32_t InputNonInverting)
+{
+ MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_VPSEL, InputNonInverting);
+}
+
+/**
+ * @brief Get OPAMP non-inverting input connection.
+ * @rmtoll CSR VPSEL LL_OPAMP_GetInputNonInverting
+ * @param OPAMPx OPAMP instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0
+ * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO1
+ * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO2
+ * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO3
+ * @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH1 (1)
+ * @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH2 (2)
+ *
+ * (1) Parameter specific to OPAMP instances: OPAMP4.\n
+ * (2) Parameter specific to OPAMP instances: OPAMP1, OPAMP3.
+ */
+__STATIC_INLINE uint32_t LL_OPAMP_GetInputNonInverting(OPAMP_TypeDef *OPAMPx)
+{
+ return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_VPSEL));
+}
+
+/**
+ * @brief Set OPAMP inverting input connection.
+ * @note OPAMP inverting input is used with OPAMP in mode standalone
+ * or PGA with external capacitors for filtering circuit.
+ * Otherwise (OPAMP in mode follower), OPAMP inverting input
+ * is not used (not connected to GPIO pin).
+ * @rmtoll CSR VMSEL LL_OPAMP_SetInputInverting
+ * @param OPAMPx OPAMP instance
+ * @param InputInverting This parameter can be one of the following values:
+ * @arg @ref LL_OPAMP_INPUT_INVERT_IO0
+ * @arg @ref LL_OPAMP_INPUT_INVERT_IO1
+ * @arg @ref LL_OPAMP_INPUT_INVERT_CONNECT_NO
+ * @retval None
+ */
+__STATIC_INLINE void LL_OPAMP_SetInputInverting(OPAMP_TypeDef *OPAMPx, uint32_t InputInverting)
+{
+ /* Manage cases of OPAMP inverting input not connected (0x10 and 0x11) */
+ /* to not modify OPAMP mode follower or PGA. */
+ /* Bit OPAMP_CSR_VMSEL_1 is set by OPAMP mode (follower, PGA). */
+ MODIFY_REG(OPAMPx->CSR, (~(InputInverting >> 1)) & OPAMP_CSR_VMSEL_0, InputInverting);
+}
+
+/**
+ * @brief Get OPAMP inverting input connection.
+ * @rmtoll CSR VMSEL LL_OPAMP_GetInputInverting
+ * @param OPAMPx OPAMP instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_OPAMP_INPUT_INVERT_IO0
+ * @arg @ref LL_OPAMP_INPUT_INVERT_IO1
+ * @arg @ref LL_OPAMP_INPUT_INVERT_CONNECT_NO
+ */
+__STATIC_INLINE uint32_t LL_OPAMP_GetInputInverting(OPAMP_TypeDef *OPAMPx)
+{
+ register uint32_t input_inverting = READ_BIT(OPAMPx->CSR, OPAMP_CSR_VMSEL);
+
+ /* Manage cases 0x10 and 0x11 to return the same value: OPAMP inverting */
+ /* input not connected. */
+ return (input_inverting & ~((input_inverting >> 1) & OPAMP_CSR_VMSEL_0));
+}
+
+/**
+ * @brief Set OPAMP non-inverting input secondary connection.
+ * @rmtoll CSR VPSSEL LL_OPAMP_SetInputNonInvertingSecondary
+ * @param OPAMPx OPAMP instance
+ * @param InputNonInverting This parameter can be one of the following values:
+ * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0_SEC
+ * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO1_SEC
+ * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO2_SEC
+ * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO3_SEC
+ * @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH1_SEC (1)
+ * @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH2_SEC (2)
+ *
+ * (1) Parameter specific to OPAMP instances: OPAMP4.\n
+ * (2) Parameter specific to OPAMP instances: OPAMP1, OPAMP3.
+ * @retval None
+ */
+__STATIC_INLINE void LL_OPAMP_SetInputNonInvertingSecondary(OPAMP_TypeDef *OPAMPx, uint32_t InputNonInverting)
+{
+ MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_VPSSEL, InputNonInverting);
+}
+
+/**
+ * @brief Get OPAMP non-inverting input secondary connection.
+ * @rmtoll CSR VPSSEL LL_OPAMP_GetInputNonInvertingSecondary
+ * @param OPAMPx OPAMP instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0_SEC
+ * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO1_SEC
+ * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO2_SEC
+ * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO3_SEC
+ * @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH1_SEC (1)
+ * @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH2_SEC (2)
+ *
+ * (1) Parameter specific to OPAMP instances: OPAMP4.\n
+ * (2) Parameter specific to OPAMP instances: OPAMP1, OPAMP3.
+ */
+__STATIC_INLINE uint32_t LL_OPAMP_GetInputNonInvertingSecondary(OPAMP_TypeDef *OPAMPx)
+{
+ return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_VPSSEL));
+}
+
+/**
+ * @brief Set OPAMP inverting input secondary connection.
+ * @note OPAMP inverting input is used with OPAMP in mode standalone
+ * or PGA with external capacitors for filtering circuit.
+ * Otherwise (OPAMP in mode follower), OPAMP inverting input
+ * is not used (not connected to GPIO pin).
+ * @rmtoll CSR VMSSEL LL_OPAMP_SetInputInvertingSecondary
+ * @param OPAMPx OPAMP instance
+ * @param InputInverting This parameter can be one of the following values:
+ * @arg @ref LL_OPAMP_INPUT_INVERT_IO0_SEC
+ * @arg @ref LL_OPAMP_INPUT_INVERT_IO1_SEC
+ * @retval None
+ */
+__STATIC_INLINE void LL_OPAMP_SetInputInvertingSecondary (OPAMP_TypeDef *OPAMPx, uint32_t InputInverting)
+{
+ MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_VMSSEL, InputInverting);
+}
+
+/**
+ * @brief Get OPAMP inverting input secondary connection.
+ * @rmtoll CSR VMSSEL LL_OPAMP_GetInputInvertingSecondary
+ * @param OPAMPx OPAMP instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_OPAMP_INPUT_INVERT_IO0_SEC
+ * @arg @ref LL_OPAMP_INPUT_INVERT_IO1_SEC
+ */
+__STATIC_INLINE uint32_t LL_OPAMP_GetInputInvertingSecondary(OPAMP_TypeDef *OPAMPx)
+{
+ return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_VMSSEL));
+}
+
+/**
+ * @brief Set OPAMP inputs multiplexer mode.
+ * @rmtoll CSR TCMEN LL_OPAMP_SetInputsMuxMode
+ * @param OPAMPx OPAMP instance
+ * @param InputsMuxMode This parameter can be one of the following values:
+ * @arg @ref LL_OPAMP_INPUT_MUX_DISABLE
+ * @arg @ref LL_OPAMP_INPUT_MUX_TIM1_CH6
+ * @retval None
+ */
+__STATIC_INLINE void LL_OPAMP_SetInputsMuxMode(OPAMP_TypeDef *OPAMPx, uint32_t InputsMuxMode)
+{
+ MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_TCMEN, InputsMuxMode);
+}
+
+/**
+ * @brief Get OPAMP inputs multiplexer mode.
+ * @rmtoll CSR TCMEN LL_OPAMP_GetInputsMuxMode
+ * @param OPAMPx OPAMP instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_OPAMP_INPUT_MUX_DISABLE
+ * @arg @ref LL_OPAMP_INPUT_MUX_TIM1_CH6
+ */
+__STATIC_INLINE uint32_t LL_OPAMP_GetInputsMuxMode(OPAMP_TypeDef *OPAMPx)
+{
+ return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_TCMEN));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_LL_EF_OPAMP_TRIMMING Configuration and operation of OPAMP trimming
+ * @{
+ */
+
+/**
+ * @brief Set OPAMP trimming mode.
+ * @rmtoll CSR USERTRIM LL_OPAMP_SetTrimmingMode
+ * @param OPAMPx OPAMP instance
+ * @param TrimmingMode This parameter can be one of the following values:
+ * @arg @ref LL_OPAMP_TRIMMING_FACTORY
+ * @arg @ref LL_OPAMP_TRIMMING_USER
+ * @retval None
+ */
+__STATIC_INLINE void LL_OPAMP_SetTrimmingMode(OPAMP_TypeDef *OPAMPx, uint32_t TrimmingMode)
+{
+ MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_USERTRIM, TrimmingMode);
+}
+
+/**
+ * @brief Get OPAMP trimming mode.
+ * @rmtoll CSR USERTRIM LL_OPAMP_GetTrimmingMode
+ * @param OPAMPx OPAMP instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_OPAMP_TRIMMING_FACTORY
+ * @arg @ref LL_OPAMP_TRIMMING_USER
+ */
+__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingMode(OPAMP_TypeDef *OPAMPx)
+{
+ return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_USERTRIM));
+}
+
+/**
+ * @brief Set OPAMP offset to calibrate the selected transistors
+ * differential pair NMOS or PMOS.
+ * @note Preliminarily, OPAMP must be set in mode calibration
+ * using function @ref LL_OPAMP_SetMode().
+ * @rmtoll CSR CALSEL LL_OPAMP_SetCalibrationSelection
+ * @param OPAMPx OPAMP instance
+ * @param TransistorsDiffPair This parameter can be one of the following values:
+ * @arg @ref LL_OPAMP_TRIMMING_NMOS (1)
+ * @arg @ref LL_OPAMP_TRIMMING_PMOS (1)
+ * @arg @ref LL_OPAMP_TRIMMING_NMOS_VREF_50PC_VDDA
+ * @arg @ref LL_OPAMP_TRIMMING_PMOS_VREF_3_3PC_VDDA
+ *
+ * (1) Default parameters to be used for calibration
+ * using two trimming steps (one with each transistors differential
+ * pair NMOS and PMOS)
+ * @retval None
+ */
+__STATIC_INLINE void LL_OPAMP_SetCalibrationSelection(OPAMP_TypeDef *OPAMPx, uint32_t TransistorsDiffPair)
+{
+ /* Parameter used with mask "OPAMP_TRIMMING_SELECT_MASK" because */
+ /* containing other bits reserved for other purpose. */
+ MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_CALSEL, (TransistorsDiffPair & OPAMP_TRIMMING_SELECT_MASK));
+}
+
+/**
+ * @brief Get OPAMP offset to calibrate the selected transistors
+ * differential pair NMOS or PMOS.
+ * @note Preliminarily, OPAMP must be set in mode calibration
+ * using function @ref LL_OPAMP_SetMode().
+ * @rmtoll CSR CALSEL LL_OPAMP_GetCalibrationSelection
+ * @param OPAMPx OPAMP instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_OPAMP_TRIMMING_NMOS (1)
+ * @arg @ref LL_OPAMP_TRIMMING_PMOS (1)
+ * @arg @ref LL_OPAMP_TRIMMING_NMOS_VREF_50PC_VDDA
+ * @arg @ref LL_OPAMP_TRIMMING_PMOS_VREF_3_3PC_VDDA
+ *
+ * (1) Default parameters to be used for calibration
+ * using two trimming steps (one with each transistors differential
+ * pair NMOS and PMOS)
+ */
+__STATIC_INLINE uint32_t LL_OPAMP_GetCalibrationSelection(OPAMP_TypeDef *OPAMPx)
+{
+ register uint32_t CalibrationSelection = (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALSEL));
+
+ return (CalibrationSelection |
+ ((OPAMP_CSR_TRIMOFFSETN) << (POSITION_VAL(OPAMP_CSR_TRIMOFFSETP) * (CalibrationSelection && OPAMP_CSR_CALSEL))));
+}
+
+/**
+ * @brief Set OPAMP calibration internal reference voltage to output.
+ * @rmtoll CSR TSTREF LL_OPAMP_SetCalibrationVrefOutput
+ * @param OPAMPx OPAMP instance
+ * @param CalibrationVrefOutput This parameter can be one of the following values:
+ * @arg @ref LL_OPAMP_VREF_OUTPUT_DISABLE
+ * @arg @ref LL_OPAMP_VREF_OUTPUT_ENABLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_OPAMP_SetCalibrationVrefOutput(OPAMP_TypeDef *OPAMPx, uint32_t CalibrationVrefOutput)
+{
+ MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_TSTREF, CalibrationVrefOutput);
+}
+
+/**
+ * @brief Get OPAMP calibration internal reference voltage to output.
+ * @rmtoll CSR TSTREF LL_OPAMP_GetCalibrationVrefOutput
+ * @param OPAMPx OPAMP instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_OPAMP_VREF_OUTPUT_DISABLE
+ * @arg @ref LL_OPAMP_VREF_OUTPUT_ENABLE
+ */
+__STATIC_INLINE uint32_t LL_OPAMP_GetCalibrationVrefOutput(OPAMP_TypeDef *OPAMPx)
+{
+ return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_TSTREF));
+}
+
+/**
+ * @brief Get OPAMP calibration result of toggling output.
+ * @note This functions returns:
+ * 0 if OPAMP calibration output is reset
+ * 1 if OPAMP calibration output is set
+ * @rmtoll CSR OUTCAL LL_OPAMP_IsCalibrationOutputSet
+ * @param OPAMPx OPAMP instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_OPAMP_IsCalibrationOutputSet(OPAMP_TypeDef *OPAMPx)
+{
+ return (READ_BIT(OPAMPx->CSR, OPAMP_CSR_OUTCAL) == OPAMP_CSR_OUTCAL);
+}
+
+/**
+ * @brief Set OPAMP trimming factor for the selected transistors
+ * differential pair NMOS or PMOS, corresponding to the selected
+ * power mode.
+ * @rmtoll CSR TRIMOFFSETN LL_OPAMP_SetTrimmingValue\n
+ * CSR TRIMOFFSETP LL_OPAMP_SetTrimmingValue
+ * @param OPAMPx OPAMP instance
+ * @param TransistorsDiffPair This parameter can be one of the following values:
+ * @arg @ref LL_OPAMP_TRIMMING_NMOS
+ * @arg @ref LL_OPAMP_TRIMMING_PMOS
+ * @param TrimmingValue 0x00...0x1F
+ * @retval None
+ */
+__STATIC_INLINE void LL_OPAMP_SetTrimmingValue(OPAMP_TypeDef* OPAMPx, uint32_t TransistorsDiffPair, uint32_t TrimmingValue)
+{
+ MODIFY_REG(OPAMPx->CSR,
+ (TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK),
+ TrimmingValue << (POSITION_VAL(TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK)));
+}
+
+/**
+ * @brief Get OPAMP trimming factor for the selected transistors
+ * differential pair NMOS or PMOS, corresponding to the selected
+ * power mode.
+ * @rmtoll CSR TRIMOFFSETN LL_OPAMP_GetTrimmingValue\n
+ * CSR TRIMOFFSETP LL_OPAMP_GetTrimmingValue
+ * @param OPAMPx OPAMP instance
+ * @param TransistorsDiffPair This parameter can be one of the following values:
+ * @arg @ref LL_OPAMP_TRIMMING_NMOS
+ * @arg @ref LL_OPAMP_TRIMMING_PMOS
+ * @retval 0x0...0x1F
+ */
+__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingValue(OPAMP_TypeDef* OPAMPx, uint32_t TransistorsDiffPair)
+{
+ return (uint32_t)(READ_BIT(OPAMPx->CSR, (TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK))
+ >> (POSITION_VAL(TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK))
+ );
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_LL_EF_OPERATION Operation on OPAMP instance
+ * @{
+ */
+/**
+ * @brief Enable OPAMP instance.
+ * @note After enable from off state, OPAMP requires a delay
+ * to fullfill wake up time specification.
+ * Refer to device datasheet, parameter "tWAKEUP".
+ * @rmtoll CSR OPAMPXEN LL_OPAMP_Enable
+ * @param OPAMPx OPAMP instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_OPAMP_Enable(OPAMP_TypeDef *OPAMPx)
+{
+ SET_BIT(OPAMPx->CSR, OPAMP_CSR_OPAMPxEN);
+}
+
+/**
+ * @brief Disable OPAMP instance.
+ * @rmtoll CSR OPAMPXEN LL_OPAMP_Disable
+ * @param OPAMPx OPAMP instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_OPAMP_Disable(OPAMP_TypeDef *OPAMPx)
+{
+ CLEAR_BIT(OPAMPx->CSR, OPAMP_CSR_OPAMPxEN);
+}
+
+/**
+ * @brief Get OPAMP instance enable state
+ * (0: OPAMP is disabled, 1: OPAMP is enabled)
+ * @rmtoll CSR OPAMPXEN LL_OPAMP_IsEnabled
+ * @param OPAMPx OPAMP instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_OPAMP_IsEnabled(OPAMP_TypeDef *OPAMPx)
+{
+ return (READ_BIT(OPAMPx->CSR, OPAMP_CSR_OPAMPxEN) == (OPAMP_CSR_OPAMPxEN));
+}
+
+/**
+ * @brief Lock OPAMP instance.
+ * @note Once locked, OPAMP configuration can be accessed in read-only.
+ * @note The only way to unlock the OPAMP is a device hardware reset.
+ * @rmtoll CSR LOCK LL_OPAMP_Lock
+ * @param OPAMPx OPAMP instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_OPAMP_Lock(OPAMP_TypeDef *OPAMPx)
+{
+ SET_BIT(OPAMPx->CSR, OPAMP_CSR_LOCK);
+}
+
+/**
+ * @brief Get OPAMP lock state
+ * (0: OPAMP is unlocked, 1: OPAMP is locked).
+ * @note Once locked, OPAMP configuration can be accessed in read-only.
+ * @note The only way to unlock the OPAMP is a device hardware reset.
+ * @rmtoll CSR LOCK LL_OPAMP_IsLocked
+ * @param OPAMPx OPAMP instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_OPAMP_IsLocked(OPAMP_TypeDef *OPAMPx)
+{
+ return (READ_BIT(OPAMPx->CSR, OPAMP_CSR_LOCK) == (OPAMP_CSR_LOCK));
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup OPAMP_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_OPAMP_DeInit(OPAMP_TypeDef *OPAMPx);
+ErrorStatus LL_OPAMP_Init(OPAMP_TypeDef *OPAMPx, LL_OPAMP_InitTypeDef *OPAMP_InitStruct);
+void LL_OPAMP_StructInit(LL_OPAMP_InitTypeDef *OPAMP_InitStruct);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* OPAMP1 || OPAMP2 || OPAMP3 || OPAMP4 */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_LL_OPAMP_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_ll_pwr.h b/Inc/stm32f3xx_ll_pwr.h
new file mode 100644
index 0000000..806324a
--- /dev/null
+++ b/Inc/stm32f3xx_ll_pwr.h
@@ -0,0 +1,570 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_pwr.h
+ * @author MCD Application Team
+ * @brief Header file of PWR LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_LL_PWR_H
+#define __STM32F3xx_LL_PWR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx.h"
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined(PWR)
+
+/** @defgroup PWR_LL PWR
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
+ * @{
+ */
+
+/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
+ * @brief Flags defines which can be used with LL_PWR_WriteReg function
+ * @{
+ */
+#define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */
+#define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_PWR_ReadReg function
+ * @{
+ */
+#define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */
+#define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */
+#if defined(PWR_PVD_SUPPORT)
+#define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */
+#endif /* PWR_PVD_SUPPORT */
+#if defined(PWR_CSR_VREFINTRDYF)
+#define LL_PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF /*!< VREFINT ready flag */
+#endif /* PWR_CSR_VREFINTRDYF */
+#define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP1 /*!< Enable WKUP pin 1 */
+#define LL_PWR_CSR_EWUP2 PWR_CSR_EWUP2 /*!< Enable WKUP pin 2 */
+#if defined(PWR_CSR_EWUP3)
+#define LL_PWR_CSR_EWUP3 PWR_CSR_EWUP3 /*!< Enable WKUP pin 3 */
+#endif /* PWR_CSR_EWUP3 */
+/**
+ * @}
+ */
+
+
+/** @defgroup PWR_LL_EC_MODE_PWR Mode Power
+ * @{
+ */
+#define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */
+#define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */
+#define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */
+/**
+ * @}
+ */
+
+#if defined(PWR_CR_LPDS)
+/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode
+ * @{
+ */
+#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */
+#define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage Regulator in low-power mode during deepsleep mode */
+/**
+ * @}
+ */
+#endif /* PWR_CR_LPDS */
+
+#if defined(PWR_PVD_SUPPORT)
+/** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
+ * @{
+ */
+#define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold detected by PVD 2.2 V */
+#define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold detected by PVD 2.3 V */
+#define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold detected by PVD 2.4 V */
+#define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold detected by PVD 2.5 V */
+#define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold detected by PVD 2.6 V */
+#define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold detected by PVD 2.7 V */
+#define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold detected by PVD 2.8 V */
+#define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold detected by PVD 2.9 V */
+/**
+ * @}
+ */
+#endif /* PWR_PVD_SUPPORT */
+/** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins
+ * @{
+ */
+#define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP1) /*!< WKUP pin 1 : PA0 */
+#define LL_PWR_WAKEUP_PIN2 (PWR_CSR_EWUP2) /*!< WKUP pin 2 : PC13 */
+#if defined(PWR_CSR_EWUP3)
+#define LL_PWR_WAKEUP_PIN3 (PWR_CSR_EWUP3) /*!< WKUP pin 3 : PE6 or PA2 according to device */
+#endif /* PWR_CSR_EWUP3 */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_SDADC_ANALOG_X SDADC Analogx
+ * @{
+ */
+#if defined(SDADC1)
+#define LL_PWR_SDADC_ANALOG1 (PWR_CR_ENSD1) /*!< Enable SDADC1 */
+#endif /* SDADC1 */
+#if defined(SDADC2)
+#define LL_PWR_SDADC_ANALOG2 (PWR_CR_ENSD2) /*!< Enable SDADC2 */
+#endif /* SDADC2 */
+#if defined(SDADC3)
+#define LL_PWR_SDADC_ANALOG3 (PWR_CR_ENSD3) /*!< Enable SDADC3 */
+#endif /* SDADC3 */
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
+ * @{
+ */
+
+/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in PWR register
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in PWR register
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
+ * @{
+ */
+
+/** @defgroup PWR_LL_EF_Configuration Configuration
+ * @{
+ */
+/**
+ * @brief Enables the SDADC peripheral functionality
+ * @rmtoll CR ENSD1 LL_PWR_EnableSDADC\n
+ * CR ENSD2 LL_PWR_EnableSDADC\n
+ * CR ENSD3 LL_PWR_EnableSDADC
+ * @param Analogx This parameter can be a combination of the following values:
+ * @arg @ref LL_PWR_SDADC_ANALOG1
+ * @arg @ref LL_PWR_SDADC_ANALOG2
+ * @arg @ref LL_PWR_SDADC_ANALOG3
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableSDADC(uint32_t Analogx)
+{
+ SET_BIT(PWR->CR, Analogx);
+}
+
+/**
+ * @brief Disables the SDADC peripheral functionality
+ * @rmtoll CR ENSD1 LL_PWR_EnableSDADC\n
+ * CR ENSD2 LL_PWR_EnableSDADC\n
+ * CR ENSD3 LL_PWR_EnableSDADC
+ * @param Analogx This parameter can be a combination of the following values:
+ * @arg @ref LL_PWR_SDADC_ANALOG1
+ * @arg @ref LL_PWR_SDADC_ANALOG2
+ * @arg @ref LL_PWR_SDADC_ANALOG3
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableSDADC(uint32_t Analogx)
+{
+ CLEAR_BIT(PWR->CR, Analogx);
+}
+
+/**
+ * @brief Check if SDADCx has been enabled or not
+ * @rmtoll CR ENSD1 LL_PWR_IsEnabledSDADC\n
+ * CR ENSD2 LL_PWR_IsEnabledSDADC\n
+ * CR ENSD3 LL_PWR_IsEnabledSDADC
+ * @param Analogx This parameter can be a combination of the following values:
+ * @arg @ref LL_PWR_SDADC_ANALOG1
+ * @arg @ref LL_PWR_SDADC_ANALOG2
+ * @arg @ref LL_PWR_SDADC_ANALOG3
+ * @retval None
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledSDADC(uint32_t Analogx)
+{
+ return (READ_BIT(PWR->CR, Analogx) == (Analogx));
+}
+
+/**
+ * @brief Enable access to the backup domain
+ * @rmtoll CR DBP LL_PWR_EnableBkUpAccess
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
+{
+ SET_BIT(PWR->CR, PWR_CR_DBP);
+}
+
+/**
+ * @brief Disable access to the backup domain
+ * @rmtoll CR DBP LL_PWR_DisableBkUpAccess
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
+{
+ CLEAR_BIT(PWR->CR, PWR_CR_DBP);
+}
+
+/**
+ * @brief Check if the backup domain is enabled
+ * @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
+{
+ return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP));
+}
+
+#if defined(PWR_CR_LPDS)
+/**
+ * @brief Set voltage Regulator mode during deep sleep mode
+ * @rmtoll CR LPDS LL_PWR_SetRegulModeDS
+ * @param RegulMode This parameter can be one of the following values:
+ * @arg @ref LL_PWR_REGU_DSMODE_MAIN
+ * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
+{
+ MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode);
+}
+
+/**
+ * @brief Get voltage Regulator mode during deep sleep mode
+ * @rmtoll CR LPDS LL_PWR_GetRegulModeDS
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_PWR_REGU_DSMODE_MAIN
+ * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
+ */
+__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
+{
+ return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS));
+}
+#endif /* PWR_CR_LPDS */
+
+/**
+ * @brief Set Power Down mode when CPU enters deepsleep
+ * @rmtoll CR PDDS LL_PWR_SetPowerMode\n
+ * @rmtoll CR LPDS LL_PWR_SetPowerMode
+ * @param PDMode This parameter can be one of the following values:
+ * @arg @ref LL_PWR_MODE_STOP_MAINREGU
+ * @arg @ref LL_PWR_MODE_STOP_LPREGU
+ * @arg @ref LL_PWR_MODE_STANDBY
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
+{
+ MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode);
+}
+
+/**
+ * @brief Get Power Down mode when CPU enters deepsleep
+ * @rmtoll CR PDDS LL_PWR_GetPowerMode\n
+ * @rmtoll CR LPDS LL_PWR_GetPowerMode
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_PWR_MODE_STOP_MAINREGU
+ * @arg @ref LL_PWR_MODE_STOP_LPREGU
+ * @arg @ref LL_PWR_MODE_STANDBY
+ */
+__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
+{
+ return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS)));
+}
+
+#if defined(PWR_PVD_SUPPORT)
+/**
+ * @brief Configure the voltage threshold detected by the Power Voltage Detector
+ * @rmtoll CR PLS LL_PWR_SetPVDLevel
+ * @param PVDLevel This parameter can be one of the following values:
+ * @arg @ref LL_PWR_PVDLEVEL_0
+ * @arg @ref LL_PWR_PVDLEVEL_1
+ * @arg @ref LL_PWR_PVDLEVEL_2
+ * @arg @ref LL_PWR_PVDLEVEL_3
+ * @arg @ref LL_PWR_PVDLEVEL_4
+ * @arg @ref LL_PWR_PVDLEVEL_5
+ * @arg @ref LL_PWR_PVDLEVEL_6
+ * @arg @ref LL_PWR_PVDLEVEL_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
+{
+ MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel);
+}
+
+/**
+ * @brief Get the voltage threshold detection
+ * @rmtoll CR PLS LL_PWR_GetPVDLevel
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_PWR_PVDLEVEL_0
+ * @arg @ref LL_PWR_PVDLEVEL_1
+ * @arg @ref LL_PWR_PVDLEVEL_2
+ * @arg @ref LL_PWR_PVDLEVEL_3
+ * @arg @ref LL_PWR_PVDLEVEL_4
+ * @arg @ref LL_PWR_PVDLEVEL_5
+ * @arg @ref LL_PWR_PVDLEVEL_6
+ * @arg @ref LL_PWR_PVDLEVEL_7
+ */
+__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
+{
+ return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS));
+}
+
+/**
+ * @brief Enable Power Voltage Detector
+ * @rmtoll CR PVDE LL_PWR_EnablePVD
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnablePVD(void)
+{
+ SET_BIT(PWR->CR, PWR_CR_PVDE);
+}
+
+/**
+ * @brief Disable Power Voltage Detector
+ * @rmtoll CR PVDE LL_PWR_DisablePVD
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisablePVD(void)
+{
+ CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
+}
+
+/**
+ * @brief Check if Power Voltage Detector is enabled
+ * @rmtoll CR PVDE LL_PWR_IsEnabledPVD
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
+{
+ return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE));
+}
+#endif /* PWR_PVD_SUPPORT */
+
+/**
+ * @brief Enable the WakeUp PINx functionality
+ * @rmtoll CSR EWUP1 LL_PWR_EnableWakeUpPin\n
+ * @rmtoll CSR EWUP2 LL_PWR_EnableWakeUpPin\n
+ * @rmtoll CSR EWUP3 LL_PWR_EnableWakeUpPin
+ * @param WakeUpPin This parameter can be one of the following values:
+ * @arg @ref LL_PWR_WAKEUP_PIN1
+ * @arg @ref LL_PWR_WAKEUP_PIN2
+ * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
+ *
+ * (*) not available on all devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
+{
+ SET_BIT(PWR->CSR, WakeUpPin);
+}
+
+/**
+ * @brief Disable the WakeUp PINx functionality
+ * @rmtoll CSR EWUP1 LL_PWR_DisableWakeUpPin\n
+ * @rmtoll CSR EWUP2 LL_PWR_DisableWakeUpPin\n
+ * @rmtoll CSR EWUP3 LL_PWR_DisableWakeUpPin
+ * @param WakeUpPin This parameter can be one of the following values:
+ * @arg @ref LL_PWR_WAKEUP_PIN1
+ * @arg @ref LL_PWR_WAKEUP_PIN2
+ * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
+ *
+ * (*) not available on all devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
+{
+ CLEAR_BIT(PWR->CSR, WakeUpPin);
+}
+
+/**
+ * @brief Check if the WakeUp PINx functionality is enabled
+ * @rmtoll CSR EWUP1 LL_PWR_IsEnabledWakeUpPin\n
+ * @rmtoll CSR EWUP2 LL_PWR_IsEnabledWakeUpPin\n
+ * @rmtoll CSR EWUP3 LL_PWR_IsEnabledWakeUpPin
+ * @param WakeUpPin This parameter can be one of the following values:
+ * @arg @ref LL_PWR_WAKEUP_PIN1
+ * @arg @ref LL_PWR_WAKEUP_PIN2
+ * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
+ *
+ * (*) not available on all devices
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
+{
+ return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin));
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+
+/**
+ * @brief Get Wake-up Flag
+ * @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void)
+{
+ return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF));
+}
+
+/**
+ * @brief Get Standby Flag
+ * @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
+{
+ return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF));
+}
+
+#if defined(PWR_PVD_SUPPORT)
+/**
+ * @brief Indicate whether VDD voltage is below the selected PVD threshold
+ * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
+{
+ return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO));
+}
+#endif /* PWR_PVD_SUPPORT */
+
+#if defined(PWR_CSR_VREFINTRDYF)
+/**
+ * @brief Get Internal Reference VrefInt Flag
+ * @rmtoll CSR VREFINTRDYF LL_PWR_IsActiveFlag_VREFINTRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VREFINTRDY(void)
+{
+ return (READ_BIT(PWR->CSR, PWR_CSR_VREFINTRDYF) == (PWR_CSR_VREFINTRDYF));
+}
+#endif /* PWR_CSR_VREFINTRDYF */
+/**
+ * @brief Clear Standby Flag
+ * @rmtoll CR CSBF LL_PWR_ClearFlag_SB
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
+{
+ SET_BIT(PWR->CR, PWR_CR_CSBF);
+}
+
+/**
+ * @brief Clear Wake-up Flags
+ * @rmtoll CR CWUF LL_PWR_ClearFlag_WU
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
+{
+ SET_BIT(PWR->CR, PWR_CR_CWUF);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup PWR_LL_EF_Init De-initialization function
+ * @{
+ */
+ErrorStatus LL_PWR_DeInit(void);
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(PWR) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_LL_PWR_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_ll_rcc.h b/Inc/stm32f3xx_ll_rcc.h
new file mode 100644
index 0000000..1784397
--- /dev/null
+++ b/Inc/stm32f3xx_ll_rcc.h
@@ -0,0 +1,2834 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_rcc.h
+ * @author MCD Application Team
+ * @brief Header file of RCC LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_LL_RCC_H
+#define __STM32F3xx_LL_RCC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx.h"
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined(RCC)
+
+/** @defgroup RCC_LL RCC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RCC_LL_Private_Constants RCC Private Constants
+ * @{
+ */
+/* Defines used for the bit position in the register and perform offsets*/
+#define RCC_POSITION_HPRE (uint32_t)POSITION_VAL(RCC_CFGR_HPRE) /*!< field position in register RCC_CFGR */
+#define RCC_POSITION_PPRE1 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE1) /*!< field position in register RCC_CFGR */
+#define RCC_POSITION_PPRE2 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE2) /*!< field position in register RCC_CFGR */
+#define RCC_POSITION_HSICAL (uint32_t)POSITION_VAL(RCC_CR_HSICAL) /*!< field position in register RCC_CR */
+#define RCC_POSITION_HSITRIM (uint32_t)POSITION_VAL(RCC_CR_HSITRIM) /*!< field position in register RCC_CR */
+#define RCC_POSITION_PLLMUL (uint32_t)POSITION_VAL(RCC_CFGR_PLLMUL) /*!< field position in register RCC_CFGR */
+#define RCC_POSITION_USART1SW (uint32_t)0U /*!< field position in register RCC_CFGR3 */
+#define RCC_POSITION_USART2SW (uint32_t)16U /*!< field position in register RCC_CFGR3 */
+#define RCC_POSITION_USART3SW (uint32_t)18U /*!< field position in register RCC_CFGR3 */
+#define RCC_POSITION_TIM1SW (uint32_t)8U /*!< field position in register RCC_CFGR3 */
+#define RCC_POSITION_TIM8SW (uint32_t)9U /*!< field position in register RCC_CFGR3 */
+#define RCC_POSITION_TIM15SW (uint32_t)10U /*!< field position in register RCC_CFGR3 */
+#define RCC_POSITION_TIM16SW (uint32_t)11U /*!< field position in register RCC_CFGR3 */
+#define RCC_POSITION_TIM17SW (uint32_t)13U /*!< field position in register RCC_CFGR3 */
+#define RCC_POSITION_TIM20SW (uint32_t)15U /*!< field position in register RCC_CFGR3 */
+#define RCC_POSITION_TIM2SW (uint32_t)24U /*!< field position in register RCC_CFGR3 */
+#define RCC_POSITION_TIM34SW (uint32_t)25U /*!< field position in register RCC_CFGR3 */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_Private_Macros RCC Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_Exported_Types RCC Exported Types
+ * @{
+ */
+
+/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
+ * @{
+ */
+
+/**
+ * @brief RCC Clocks Frequency Structure
+ */
+typedef struct
+{
+ uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
+ uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
+ uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
+ uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */
+} LL_RCC_ClocksTypeDef;
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
+ * @{
+ */
+
+/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
+ * @brief Defines used to adapt values of different oscillators
+ * @note These values could be modified in the user environment according to
+ * HW set-up.
+ * @{
+ */
+#if !defined (HSE_VALUE)
+#define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSI_VALUE)
+#define HSI_VALUE 8000000U /*!< Value of the HSI oscillator in Hz */
+#endif /* HSI_VALUE */
+
+#if !defined (LSE_VALUE)
+#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
+#endif /* LSE_VALUE */
+
+#if !defined (LSI_VALUE)
+#define LSI_VALUE 40000U /*!< Value of the LSI oscillator in Hz */
+#endif /* LSI_VALUE */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
+ * @brief Flags defines which can be used with LL_RCC_WriteReg function
+ * @{
+ */
+#define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */
+#define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */
+#define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */
+#define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */
+#define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */
+#define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_RCC_ReadReg function
+ * @{
+ */
+#define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */
+#define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */
+#define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */
+#define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */
+#define LL_RCC_CFGR_MCOF RCC_CFGR_MCOF /*!< MCO flag */
+#define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */
+#define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */
+#define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */
+#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */
+#define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */
+#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */
+#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
+#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
+#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */
+#if defined(RCC_CSR_V18PWRRSTF)
+#define LL_RCC_CSR_V18PWRRSTF RCC_CSR_V18PWRRSTF /*!< Reset flag of the 1.8 V domain. */
+#endif /* RCC_CSR_V18PWRRSTF */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
+ * @{
+ */
+#define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */
+#define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */
+#define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */
+#define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */
+#define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
+ * @{
+ */
+#define LL_RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U) /*!< Xtal mode lower driving capability */
+#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium low driving capability */
+#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium high driving capability */
+#define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
+ * @{
+ */
+#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
+#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
+#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
+ * @{
+ */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
+ * @{
+ */
+#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
+#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
+#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
+#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
+#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
+#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
+#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
+#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
+#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
+ * @{
+ */
+#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
+#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
+#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
+#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
+#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
+ * @{
+ */
+#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */
+#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */
+#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */
+#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */
+#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
+ * @{
+ */
+#define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK /*!< MCO output disabled, no clock on MCO */
+#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_SYSCLK /*!< SYSCLK selection as MCO source */
+#define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCOSEL_HSI /*!< HSI selection as MCO source */
+#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_HSE /*!< HSE selection as MCO source */
+#define LL_RCC_MCO1SOURCE_LSI RCC_CFGR_MCOSEL_LSI /*!< LSI selection as MCO source */
+#define LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL_LSE /*!< LSE selection as MCO source */
+#define LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 RCC_CFGR_MCOSEL_PLL_DIV2 /*!< PLL clock divided by 2*/
+#if defined(RCC_CFGR_PLLNODIV)
+#define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_PLL_DIV2 | RCC_CFGR_PLLNODIV) /*!< PLL clock selected*/
+#endif /* RCC_CFGR_PLLNODIV */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler
+ * @{
+ */
+#define LL_RCC_MCO1_DIV_1 ((uint32_t)0x00000000U)/*!< MCO Clock divided by 1 */
+#if defined(RCC_CFGR_MCOPRE)
+#define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO Clock divided by 2 */
+#define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO Clock divided by 4 */
+#define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO Clock divided by 8 */
+#define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO Clock divided by 16 */
+#define LL_RCC_MCO1_DIV_32 RCC_CFGR_MCOPRE_DIV32 /*!< MCO Clock divided by 32 */
+#define LL_RCC_MCO1_DIV_64 RCC_CFGR_MCOPRE_DIV64 /*!< MCO Clock divided by 64 */
+#define LL_RCC_MCO1_DIV_128 RCC_CFGR_MCOPRE_DIV128 /*!< MCO Clock divided by 128 */
+#endif /* RCC_CFGR_MCOPRE */
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
+ * @{
+ */
+#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
+#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup RCC_LL_EC_USART1_CLKSOURCE Peripheral USART clock source selection
+ * @{
+ */
+#if defined(RCC_CFGR3_USART1SW_PCLK1)
+#define LL_RCC_USART1_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_PCLK1) /*!< PCLK1 clock used as USART1 clock source */
+#else
+#define LL_RCC_USART1_CLKSOURCE_PCLK2 (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_PCLK2) /*!< PCLK2 clock used as USART1 clock source */
+#endif /*RCC_CFGR3_USART1SW_PCLK1*/
+#define LL_RCC_USART1_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_SYSCLK) /*!< System clock selected as USART1 clock source */
+#define LL_RCC_USART1_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_LSE) /*!< LSE oscillator clock used as USART1 clock source */
+#define LL_RCC_USART1_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_HSI) /*!< HSI oscillator clock used as USART1 clock source */
+#if defined(RCC_CFGR3_USART2SW)
+#define LL_RCC_USART2_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_PCLK) /*!< PCLK1 clock used as USART2 clock source */
+#define LL_RCC_USART2_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_SYSCLK) /*!< System clock selected as USART2 clock source */
+#define LL_RCC_USART2_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_LSE) /*!< LSE oscillator clock used as USART2 clock source */
+#define LL_RCC_USART2_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_HSI) /*!< HSI oscillator clock used as USART2 clock source */
+#endif /* RCC_CFGR3_USART2SW */
+#if defined(RCC_CFGR3_USART3SW)
+#define LL_RCC_USART3_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_PCLK) /*!< PCLK1 clock used as USART3 clock source */
+#define LL_RCC_USART3_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_SYSCLK) /*!< System clock selected as USART3 clock source */
+#define LL_RCC_USART3_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_LSE) /*!< LSE oscillator clock used as USART3 clock source */
+#define LL_RCC_USART3_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_HSI) /*!< HSI oscillator clock used as USART3 clock source */
+#endif /* RCC_CFGR3_USART3SW */
+/**
+ * @}
+ */
+
+#if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW)
+/** @defgroup RCC_LL_EC_UART4_CLKSOURCE Peripheral UART clock source selection
+ * @{
+ */
+#define LL_RCC_UART4_CLKSOURCE_PCLK1 (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_PCLK) /*!< PCLK1 clock used as UART4 clock source */
+#define LL_RCC_UART4_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_SYSCLK) /*!< System clock selected as UART4 clock source */
+#define LL_RCC_UART4_CLKSOURCE_LSE (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_LSE) /*!< LSE oscillator clock used as UART4 clock source */
+#define LL_RCC_UART4_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_HSI) /*!< HSI oscillator clock used as UART4 clock source */
+#define LL_RCC_UART5_CLKSOURCE_PCLK1 (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_PCLK) /*!< PCLK1 clock used as UART5 clock source */
+#define LL_RCC_UART5_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_SYSCLK) /*!< System clock selected as UART5 clock source */
+#define LL_RCC_UART5_CLKSOURCE_LSE (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_LSE) /*!< LSE oscillator clock used as UART5 clock source */
+#define LL_RCC_UART5_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_HSI) /*!< HSI oscillator clock used as UART5 clock source */
+/**
+ * @}
+ */
+
+#endif /* RCC_CFGR3_UART4SW || RCC_CFGR3_UART5SW */
+
+/** @defgroup RCC_LL_EC_I2C1_CLKSOURCE Peripheral I2C clock source selection
+ * @{
+ */
+#define LL_RCC_I2C1_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_I2C1SW << 24U) | RCC_CFGR3_I2C1SW_HSI) /*!< HSI oscillator clock used as I2C1 clock source */
+#define LL_RCC_I2C1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_I2C1SW << 24U) | RCC_CFGR3_I2C1SW_SYSCLK) /*!< System clock selected as I2C1 clock source */
+#if defined(RCC_CFGR3_I2C2SW)
+#define LL_RCC_I2C2_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_I2C2SW << 24U) | RCC_CFGR3_I2C2SW_HSI) /*!< HSI oscillator clock used as I2C2 clock source */
+#define LL_RCC_I2C2_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_I2C2SW << 24U) | RCC_CFGR3_I2C2SW_SYSCLK) /*!< System clock selected as I2C2 clock source */
+#endif /*RCC_CFGR3_I2C2SW*/
+#if defined(RCC_CFGR3_I2C3SW)
+#define LL_RCC_I2C3_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_I2C3SW << 24U) | RCC_CFGR3_I2C3SW_HSI) /*!< HSI oscillator clock used as I2C3 clock source */
+#define LL_RCC_I2C3_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_I2C3SW << 24U) | RCC_CFGR3_I2C3SW_SYSCLK) /*!< System clock selected as I2C3 clock source */
+#endif /*RCC_CFGR3_I2C3SW*/
+/**
+ * @}
+ */
+
+#if defined(RCC_CFGR_I2SSRC)
+/** @defgroup RCC_LL_EC_I2S_CLKSOURCE Peripheral I2S clock source selection
+ * @{
+ */
+#define LL_RCC_I2S_CLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK /*!< System clock selected as I2S clock source */
+#define LL_RCC_I2S_CLKSOURCE_PIN RCC_CFGR_I2SSRC_EXT /*!< External clock selected as I2S clock source */
+/**
+ * @}
+ */
+
+#endif /* RCC_CFGR_I2SSRC */
+
+#if defined(RCC_CFGR3_TIMSW)
+/** @defgroup RCC_LL_EC_TIM1_CLKSOURCE Peripheral TIM clock source selection
+ * @{
+ */
+#define LL_RCC_TIM1_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM1SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM1SW_PCLK2) /*!< PCLK2 used as TIM1 clock source */
+#define LL_RCC_TIM1_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM1SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM1SW_PLL) /*!< PLL clock used as TIM1 clock source */
+#if defined(RCC_CFGR3_TIM8SW)
+#define LL_RCC_TIM8_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM8SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM8SW_PCLK2) /*!< PCLK2 used as TIM8 clock source */
+#define LL_RCC_TIM8_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM8SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM8SW_PLL) /*!< PLL clock used as TIM8 clock source */
+#endif /*RCC_CFGR3_TIM8SW*/
+#if defined(RCC_CFGR3_TIM15SW)
+#define LL_RCC_TIM15_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM15SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM15SW_PCLK2) /*!< PCLK2 used as TIM15 clock source */
+#define LL_RCC_TIM15_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM15SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM15SW_PLL) /*!< PLL clock used as TIM15 clock source */
+#endif /*RCC_CFGR3_TIM15SW*/
+#if defined(RCC_CFGR3_TIM16SW)
+#define LL_RCC_TIM16_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM16SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM16SW_PCLK2) /*!< PCLK2 used as TIM16 clock source */
+#define LL_RCC_TIM16_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM16SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM16SW_PLL) /*!< PLL clock used as TIM16 clock source */
+#endif /*RCC_CFGR3_TIM16SW*/
+#if defined(RCC_CFGR3_TIM17SW)
+#define LL_RCC_TIM17_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM17SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM17SW_PCLK2) /*!< PCLK2 used as TIM17 clock source */
+#define LL_RCC_TIM17_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM17SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM17SW_PLL) /*!< PLL clock used as TIM17 clock source */
+#endif /*RCC_CFGR3_TIM17SW*/
+#if defined(RCC_CFGR3_TIM20SW)
+#define LL_RCC_TIM20_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM20SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM20SW_PCLK2) /*!< PCLK2 used as TIM20 clock source */
+#define LL_RCC_TIM20_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM20SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM20SW_PLL) /*!< PLL clock used as TIM20 clock source */
+#endif /*RCC_CFGR3_TIM20SW*/
+#if defined(RCC_CFGR3_TIM2SW)
+#define LL_RCC_TIM2_CLKSOURCE_PCLK1 (uint32_t)(((RCC_POSITION_TIM2SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM2SW_PCLK1) /*!< PCLK1 used as TIM2 clock source */
+#define LL_RCC_TIM2_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM2SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM2SW_PLL) /*!< PLL clock used as TIM2 clock source */
+#endif /*RCC_CFGR3_TIM2SW*/
+#if defined(RCC_CFGR3_TIM34SW)
+#define LL_RCC_TIM34_CLKSOURCE_PCLK1 (uint32_t)(((RCC_POSITION_TIM34SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM34SW_PCLK1) /*!< PCLK1 used as TIM3/4 clock source */
+#define LL_RCC_TIM34_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM34SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM34SW_PLL) /*!< PLL clock used as TIM3/4 clock source */
+#endif /*RCC_CFGR3_TIM34SW*/
+/**
+ * @}
+ */
+
+#endif /* RCC_CFGR3_TIMSW */
+
+#if defined(HRTIM1)
+/** @defgroup RCC_LL_EC_HRTIM1_CLKSOURCE Peripheral HRTIM1 clock source selection
+ * @{
+ */
+#define LL_RCC_HRTIM1_CLKSOURCE_PCLK2 RCC_CFGR3_HRTIM1SW_PCLK2 /*!< PCLK2 used as HRTIM1 clock source */
+#define LL_RCC_HRTIM1_CLKSOURCE_PLL RCC_CFGR3_HRTIM1SW_PLL /*!< PLL clock used as HRTIM1 clock source */
+/**
+ * @}
+ */
+
+#endif /* HRTIM1 */
+
+#if defined(CEC)
+/** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection
+ * @{
+ */
+#define LL_RCC_CEC_CLKSOURCE_HSI_DIV244 RCC_CFGR3_CECSW_HSI_DIV244 /*!< HSI clock divided by 244 selected as HDMI CEC entry clock source */
+#define LL_RCC_CEC_CLKSOURCE_LSE RCC_CFGR3_CECSW_LSE /*!< LSE clock selected as HDMI CEC entry clock source */
+/**
+ * @}
+ */
+
+#endif /* CEC */
+
+#if defined(USB)
+/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
+ * @{
+ */
+#define LL_RCC_USB_CLKSOURCE_PLL RCC_CFGR_USBPRE_DIV1 /*!< USB prescaler is PLL clock divided by 1 */
+#define LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 RCC_CFGR_USBPRE_DIV1_5 /*!< USB prescaler is PLL clock divided by 1.5 */
+/**
+ * @}
+ */
+
+#endif /* USB */
+
+#if defined(RCC_CFGR_ADCPRE)
+/** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection
+ * @{
+ */
+#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 RCC_CFGR_ADCPRE_DIV2 /*!< ADC prescaler PCLK divided by 2 */
+#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 RCC_CFGR_ADCPRE_DIV4 /*!< ADC prescaler PCLK divided by 4 */
+#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 RCC_CFGR_ADCPRE_DIV6 /*!< ADC prescaler PCLK divided by 6 */
+#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 RCC_CFGR_ADCPRE_DIV8 /*!< ADC prescaler PCLK divided by 8 */
+/**
+ * @}
+ */
+
+#elif defined(RCC_CFGR2_ADC1PRES)
+/** @defgroup RCC_LL_EC_ADC1_CLKSOURCE Peripheral ADC clock source selection
+ * @{
+ */
+#define LL_RCC_ADC1_CLKSRC_HCLK RCC_CFGR2_ADC1PRES_NO /*!< ADC1 clock disabled, ADC1 can use AHB clock */
+#define LL_RCC_ADC1_CLKSRC_PLL_DIV_1 RCC_CFGR2_ADC1PRES_DIV1 /*!< ADC1 PLL clock divided by 1 */
+#define LL_RCC_ADC1_CLKSRC_PLL_DIV_2 RCC_CFGR2_ADC1PRES_DIV2 /*!< ADC1 PLL clock divided by 2 */
+#define LL_RCC_ADC1_CLKSRC_PLL_DIV_4 RCC_CFGR2_ADC1PRES_DIV4 /*!< ADC1 PLL clock divided by 4 */
+#define LL_RCC_ADC1_CLKSRC_PLL_DIV_6 RCC_CFGR2_ADC1PRES_DIV6 /*!< ADC1 PLL clock divided by 6 */
+#define LL_RCC_ADC1_CLKSRC_PLL_DIV_8 RCC_CFGR2_ADC1PRES_DIV8 /*!< ADC1 PLL clock divided by 8 */
+#define LL_RCC_ADC1_CLKSRC_PLL_DIV_10 RCC_CFGR2_ADC1PRES_DIV10 /*!< ADC1 PLL clock divided by 10 */
+#define LL_RCC_ADC1_CLKSRC_PLL_DIV_12 RCC_CFGR2_ADC1PRES_DIV12 /*!< ADC1 PLL clock divided by 12 */
+#define LL_RCC_ADC1_CLKSRC_PLL_DIV_16 RCC_CFGR2_ADC1PRES_DIV16 /*!< ADC1 PLL clock divided by 16 */
+#define LL_RCC_ADC1_CLKSRC_PLL_DIV_32 RCC_CFGR2_ADC1PRES_DIV32 /*!< ADC1 PLL clock divided by 32 */
+#define LL_RCC_ADC1_CLKSRC_PLL_DIV_64 RCC_CFGR2_ADC1PRES_DIV64 /*!< ADC1 PLL clock divided by 64 */
+#define LL_RCC_ADC1_CLKSRC_PLL_DIV_128 RCC_CFGR2_ADC1PRES_DIV128 /*!< ADC1 PLL clock divided by 128 */
+#define LL_RCC_ADC1_CLKSRC_PLL_DIV_256 RCC_CFGR2_ADC1PRES_DIV256 /*!< ADC1 PLL clock divided by 256 */
+/**
+ * @}
+ */
+
+#elif defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
+#if defined(RCC_CFGR2_ADCPRE12) && defined(RCC_CFGR2_ADCPRE34)
+/** @defgroup RCC_LL_EC_ADC12_CLKSOURCE Peripheral ADC12 clock source selection
+ * @{
+ */
+#define LL_RCC_ADC12_CLKSRC_HCLK (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_NO) /*!< ADC12 clock disabled, ADC12 can use AHB clock */
+#define LL_RCC_ADC12_CLKSRC_PLL_DIV_1 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV1) /*!< ADC12 PLL clock divided by 1 */
+#define LL_RCC_ADC12_CLKSRC_PLL_DIV_2 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV2) /*!< ADC12 PLL clock divided by 2 */
+#define LL_RCC_ADC12_CLKSRC_PLL_DIV_4 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV4) /*!< ADC12 PLL clock divided by 4 */
+#define LL_RCC_ADC12_CLKSRC_PLL_DIV_6 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV6) /*!< ADC12 PLL clock divided by 6 */
+#define LL_RCC_ADC12_CLKSRC_PLL_DIV_8 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV8) /*!< ADC12 PLL clock divided by 8 */
+#define LL_RCC_ADC12_CLKSRC_PLL_DIV_10 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV10) /*!< ADC12 PLL clock divided by 10 */
+#define LL_RCC_ADC12_CLKSRC_PLL_DIV_12 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV12) /*!< ADC12 PLL clock divided by 12 */
+#define LL_RCC_ADC12_CLKSRC_PLL_DIV_16 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV16) /*!< ADC12 PLL clock divided by 16 */
+#define LL_RCC_ADC12_CLKSRC_PLL_DIV_32 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV32) /*!< ADC12 PLL clock divided by 32 */
+#define LL_RCC_ADC12_CLKSRC_PLL_DIV_64 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV64) /*!< ADC12 PLL clock divided by 64 */
+#define LL_RCC_ADC12_CLKSRC_PLL_DIV_128 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV128) /*!< ADC12 PLL clock divided by 128 */
+#define LL_RCC_ADC12_CLKSRC_PLL_DIV_256 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV256) /*!< ADC12 PLL clock divided by 256 */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_ADC34_CLKSOURCE Peripheral ADC34 clock source selection
+ * @{
+ */
+#define LL_RCC_ADC34_CLKSRC_HCLK (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_NO) /*!< ADC34 clock disabled, ADC34 can use AHB clock */
+#define LL_RCC_ADC34_CLKSRC_PLL_DIV_1 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV1) /*!< ADC34 PLL clock divided by 1 */
+#define LL_RCC_ADC34_CLKSRC_PLL_DIV_2 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV2) /*!< ADC34 PLL clock divided by 2 */
+#define LL_RCC_ADC34_CLKSRC_PLL_DIV_4 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV4) /*!< ADC34 PLL clock divided by 4 */
+#define LL_RCC_ADC34_CLKSRC_PLL_DIV_6 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV6) /*!< ADC34 PLL clock divided by 6 */
+#define LL_RCC_ADC34_CLKSRC_PLL_DIV_8 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV8) /*!< ADC34 PLL clock divided by 8 */
+#define LL_RCC_ADC34_CLKSRC_PLL_DIV_10 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV10) /*!< ADC34 PLL clock divided by 10 */
+#define LL_RCC_ADC34_CLKSRC_PLL_DIV_12 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV12) /*!< ADC34 PLL clock divided by 12 */
+#define LL_RCC_ADC34_CLKSRC_PLL_DIV_16 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV16) /*!< ADC34 PLL clock divided by 16 */
+#define LL_RCC_ADC34_CLKSRC_PLL_DIV_32 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV32) /*!< ADC34 PLL clock divided by 32 */
+#define LL_RCC_ADC34_CLKSRC_PLL_DIV_64 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV64) /*!< ADC34 PLL clock divided by 64 */
+#define LL_RCC_ADC34_CLKSRC_PLL_DIV_128 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV128) /*!< ADC34 PLL clock divided by 128 */
+#define LL_RCC_ADC34_CLKSRC_PLL_DIV_256 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV256) /*!< ADC34 PLL clock divided by 256 */
+/**
+ * @}
+ */
+
+#else
+/** @defgroup RCC_LL_EC_ADC12_CLKSOURCE Peripheral ADC clock source selection
+ * @{
+ */
+#define LL_RCC_ADC12_CLKSRC_HCLK RCC_CFGR2_ADCPRE12_NO /*!< ADC12 clock disabled, ADC12 can use AHB clock */
+#define LL_RCC_ADC12_CLKSRC_PLL_DIV_1 RCC_CFGR2_ADCPRE12_DIV1 /*!< ADC12 PLL clock divided by 1 */
+#define LL_RCC_ADC12_CLKSRC_PLL_DIV_2 RCC_CFGR2_ADCPRE12_DIV2 /*!< ADC12 PLL clock divided by 2 */
+#define LL_RCC_ADC12_CLKSRC_PLL_DIV_4 RCC_CFGR2_ADCPRE12_DIV4 /*!< ADC12 PLL clock divided by 4 */
+#define LL_RCC_ADC12_CLKSRC_PLL_DIV_6 RCC_CFGR2_ADCPRE12_DIV6 /*!< ADC12 PLL clock divided by 6 */
+#define LL_RCC_ADC12_CLKSRC_PLL_DIV_8 RCC_CFGR2_ADCPRE12_DIV8 /*!< ADC12 PLL clock divided by 8 */
+#define LL_RCC_ADC12_CLKSRC_PLL_DIV_10 RCC_CFGR2_ADCPRE12_DIV10 /*!< ADC12 PLL clock divided by 10 */
+#define LL_RCC_ADC12_CLKSRC_PLL_DIV_12 RCC_CFGR2_ADCPRE12_DIV12 /*!< ADC12 PLL clock divided by 12 */
+#define LL_RCC_ADC12_CLKSRC_PLL_DIV_16 RCC_CFGR2_ADCPRE12_DIV16 /*!< ADC12 PLL clock divided by 16 */
+#define LL_RCC_ADC12_CLKSRC_PLL_DIV_32 RCC_CFGR2_ADCPRE12_DIV32 /*!< ADC12 PLL clock divided by 32 */
+#define LL_RCC_ADC12_CLKSRC_PLL_DIV_64 RCC_CFGR2_ADCPRE12_DIV64 /*!< ADC12 PLL clock divided by 64 */
+#define LL_RCC_ADC12_CLKSRC_PLL_DIV_128 RCC_CFGR2_ADCPRE12_DIV128 /*!< ADC12 PLL clock divided by 128 */
+#define LL_RCC_ADC12_CLKSRC_PLL_DIV_256 RCC_CFGR2_ADCPRE12_DIV256 /*!< ADC12 PLL clock divided by 256 */
+/**
+ * @}
+ */
+
+#endif /* RCC_CFGR2_ADCPRE12 && RCC_CFGR2_ADCPRE34 */
+
+#endif /* RCC_CFGR_ADCPRE */
+
+#if defined(RCC_CFGR_SDPRE)
+/** @defgroup RCC_LL_EC_SDADC_CLKSOURCE_SYSCLK Peripheral SDADC clock source selection
+ * @{
+ */
+#define LL_RCC_SDADC_CLKSRC_SYS_DIV_1 RCC_CFGR_SDPRE_DIV1 /*!< SDADC CLK not divided */
+#define LL_RCC_SDADC_CLKSRC_SYS_DIV_2 RCC_CFGR_SDPRE_DIV2 /*!< SDADC CLK divided by 2 */
+#define LL_RCC_SDADC_CLKSRC_SYS_DIV_4 RCC_CFGR_SDPRE_DIV4 /*!< SDADC CLK divided by 4 */
+#define LL_RCC_SDADC_CLKSRC_SYS_DIV_6 RCC_CFGR_SDPRE_DIV6 /*!< SDADC CLK divided by 6 */
+#define LL_RCC_SDADC_CLKSRC_SYS_DIV_8 RCC_CFGR_SDPRE_DIV8 /*!< SDADC CLK divided by 8 */
+#define LL_RCC_SDADC_CLKSRC_SYS_DIV_10 RCC_CFGR_SDPRE_DIV10 /*!< SDADC CLK divided by 10 */
+#define LL_RCC_SDADC_CLKSRC_SYS_DIV_12 RCC_CFGR_SDPRE_DIV12 /*!< SDADC CLK divided by 12 */
+#define LL_RCC_SDADC_CLKSRC_SYS_DIV_14 RCC_CFGR_SDPRE_DIV14 /*!< SDADC CLK divided by 14 */
+#define LL_RCC_SDADC_CLKSRC_SYS_DIV_16 RCC_CFGR_SDPRE_DIV16 /*!< SDADC CLK divided by 16 */
+#define LL_RCC_SDADC_CLKSRC_SYS_DIV_20 RCC_CFGR_SDPRE_DIV20 /*!< SDADC CLK divided by 20 */
+#define LL_RCC_SDADC_CLKSRC_SYS_DIV_24 RCC_CFGR_SDPRE_DIV24 /*!< SDADC CLK divided by 24 */
+#define LL_RCC_SDADC_CLKSRC_SYS_DIV_28 RCC_CFGR_SDPRE_DIV28 /*!< SDADC CLK divided by 28 */
+#define LL_RCC_SDADC_CLKSRC_SYS_DIV_32 RCC_CFGR_SDPRE_DIV32 /*!< SDADC CLK divided by 32 */
+#define LL_RCC_SDADC_CLKSRC_SYS_DIV_36 RCC_CFGR_SDPRE_DIV36 /*!< SDADC CLK divided by 36 */
+#define LL_RCC_SDADC_CLKSRC_SYS_DIV_40 RCC_CFGR_SDPRE_DIV40 /*!< SDADC CLK divided by 40 */
+#define LL_RCC_SDADC_CLKSRC_SYS_DIV_44 RCC_CFGR_SDPRE_DIV44 /*!< SDADC CLK divided by 44 */
+#define LL_RCC_SDADC_CLKSRC_SYS_DIV_48 RCC_CFGR_SDPRE_DIV48 /*!< SDADC CLK divided by 48 */
+/**
+ * @}
+ */
+
+#endif /* RCC_CFGR_SDPRE */
+
+/** @defgroup RCC_LL_EC_USART Peripheral USART get clock source
+ * @{
+ */
+#define LL_RCC_USART1_CLKSOURCE RCC_POSITION_USART1SW /*!< USART1 Clock source selection */
+#if defined(RCC_CFGR3_USART2SW)
+#define LL_RCC_USART2_CLKSOURCE RCC_POSITION_USART2SW /*!< USART2 Clock source selection */
+#endif /* RCC_CFGR3_USART2SW */
+#if defined(RCC_CFGR3_USART3SW)
+#define LL_RCC_USART3_CLKSOURCE RCC_POSITION_USART3SW /*!< USART3 Clock source selection */
+#endif /* RCC_CFGR3_USART3SW */
+/**
+ * @}
+ */
+
+#if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW)
+/** @defgroup RCC_LL_EC_UART Peripheral UART get clock source
+ * @{
+ */
+#define LL_RCC_UART4_CLKSOURCE RCC_CFGR3_UART4SW /*!< UART4 Clock source selection */
+#define LL_RCC_UART5_CLKSOURCE RCC_CFGR3_UART5SW /*!< UART5 Clock source selection */
+/**
+ * @}
+ */
+
+#endif /* RCC_CFGR3_UART4SW || RCC_CFGR3_UART5SW */
+
+/** @defgroup RCC_LL_EC_I2C Peripheral I2C get clock source
+ * @{
+ */
+#define LL_RCC_I2C1_CLKSOURCE RCC_CFGR3_I2C1SW /*!< I2C1 Clock source selection */
+#if defined(RCC_CFGR3_I2C2SW)
+#define LL_RCC_I2C2_CLKSOURCE RCC_CFGR3_I2C2SW /*!< I2C2 Clock source selection */
+#endif /*RCC_CFGR3_I2C2SW*/
+#if defined(RCC_CFGR3_I2C3SW)
+#define LL_RCC_I2C3_CLKSOURCE RCC_CFGR3_I2C3SW /*!< I2C3 Clock source selection */
+#endif /*RCC_CFGR3_I2C3SW*/
+/**
+ * @}
+ */
+
+#if defined(RCC_CFGR_I2SSRC)
+/** @defgroup RCC_LL_EC_I2S Peripheral I2S get clock source
+ * @{
+ */
+#define LL_RCC_I2S_CLKSOURCE RCC_CFGR_I2SSRC /*!< I2S Clock source selection */
+/**
+ * @}
+ */
+
+#endif /* RCC_CFGR_I2SSRC */
+
+#if defined(RCC_CFGR3_TIMSW)
+/** @defgroup RCC_LL_EC_TIM TIMx Peripheral TIM get clock source
+ * @{
+ */
+#define LL_RCC_TIM1_CLKSOURCE (RCC_POSITION_TIM1SW - RCC_POSITION_TIM1SW) /*!< TIM1 Clock source selection */
+#if defined(RCC_CFGR3_TIM2SW)
+#define LL_RCC_TIM2_CLKSOURCE (RCC_POSITION_TIM2SW - RCC_POSITION_TIM1SW) /*!< TIM2 Clock source selection */
+#endif /*RCC_CFGR3_TIM2SW*/
+#if defined(RCC_CFGR3_TIM8SW)
+#define LL_RCC_TIM8_CLKSOURCE (RCC_POSITION_TIM8SW - RCC_POSITION_TIM1SW) /*!< TIM8 Clock source selection */
+#endif /*RCC_CFGR3_TIM8SW*/
+#if defined(RCC_CFGR3_TIM15SW)
+#define LL_RCC_TIM15_CLKSOURCE (RCC_POSITION_TIM15SW - RCC_POSITION_TIM1SW) /*!< TIM15 Clock source selection */
+#endif /*RCC_CFGR3_TIM15SW*/
+#if defined(RCC_CFGR3_TIM16SW)
+#define LL_RCC_TIM16_CLKSOURCE (RCC_POSITION_TIM16SW - RCC_POSITION_TIM1SW) /*!< TIM16 Clock source selection */
+#endif /*RCC_CFGR3_TIM16SW*/
+#if defined(RCC_CFGR3_TIM17SW)
+#define LL_RCC_TIM17_CLKSOURCE (RCC_POSITION_TIM17SW - RCC_POSITION_TIM1SW) /*!< TIM17 Clock source selection */
+#endif /*RCC_CFGR3_TIM17SW*/
+#if defined(RCC_CFGR3_TIM20SW)
+#define LL_RCC_TIM20_CLKSOURCE (RCC_POSITION_TIM20SW - RCC_POSITION_TIM1SW) /*!< TIM20 Clock source selection */
+#endif /*RCC_CFGR3_TIM20SW*/
+#if defined(RCC_CFGR3_TIM34SW)
+#define LL_RCC_TIM34_CLKSOURCE (RCC_POSITION_TIM34SW - RCC_POSITION_TIM1SW) /*!< TIM3/4 Clock source selection */
+#endif /*RCC_CFGR3_TIM34SW*/
+/**
+ * @}
+ */
+
+#endif /* RCC_CFGR3_TIMSW */
+
+#if defined(HRTIM1)
+/** @defgroup RCC_LL_EC_HRTIM1 Peripheral HRTIM1 get clock source
+ * @{
+ */
+#define LL_RCC_HRTIM1_CLKSOURCE RCC_CFGR3_HRTIM1SW /*!< HRTIM1 Clock source selection */
+/**
+ * @}
+ */
+
+#endif /* HRTIM1 */
+
+#if defined(CEC)
+/** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source
+ * @{
+ */
+#define LL_RCC_CEC_CLKSOURCE RCC_CFGR3_CECSW /*!< CEC Clock source selection */
+/**
+ * @}
+ */
+
+#endif /* CEC */
+
+#if defined(USB)
+/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
+ * @{
+ */
+#define LL_RCC_USB_CLKSOURCE RCC_CFGR_USBPRE /*!< USB Clock source selection */
+/**
+ * @}
+ */
+
+#endif /* USB */
+
+#if defined(RCC_CFGR_ADCPRE)
+/** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source
+ * @{
+ */
+#define LL_RCC_ADC_CLKSOURCE RCC_CFGR_ADCPRE /*!< ADC Clock source selection */
+/**
+ * @}
+ */
+
+#endif /* RCC_CFGR_ADCPRE */
+
+#if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
+/** @defgroup RCC_LL_EC_ADCXX Peripheral ADC get clock source
+ * @{
+ */
+#if defined(RCC_CFGR2_ADC1PRES)
+#define LL_RCC_ADC1_CLKSOURCE RCC_CFGR2_ADC1PRES /*!< ADC1 Clock source selection */
+#else
+#define LL_RCC_ADC12_CLKSOURCE RCC_CFGR2_ADCPRE12 /*!< ADC12 Clock source selection */
+#if defined(RCC_CFGR2_ADCPRE34)
+#define LL_RCC_ADC34_CLKSOURCE RCC_CFGR2_ADCPRE34 /*!< ADC34 Clock source selection */
+#endif /*RCC_CFGR2_ADCPRE34*/
+#endif /*RCC_CFGR2_ADC1PRES*/
+/**
+ * @}
+ */
+
+#endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */
+
+#if defined(RCC_CFGR_SDPRE)
+/** @defgroup RCC_LL_EC_SDADC Peripheral SDADC get clock source
+ * @{
+ */
+#define LL_RCC_SDADC_CLKSOURCE RCC_CFGR_SDPRE /*!< SDADC Clock source selection */
+/**
+ * @}
+ */
+
+#endif /* RCC_CFGR_SDPRE */
+
+
+/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
+ * @{
+ */
+#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor
+ * @{
+ */
+#define LL_RCC_PLL_MUL_2 RCC_CFGR_PLLMUL2 /*!< PLL input clock*2 */
+#define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMUL3 /*!< PLL input clock*3 */
+#define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMUL4 /*!< PLL input clock*4 */
+#define LL_RCC_PLL_MUL_5 RCC_CFGR_PLLMUL5 /*!< PLL input clock*5 */
+#define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMUL6 /*!< PLL input clock*6 */
+#define LL_RCC_PLL_MUL_7 RCC_CFGR_PLLMUL7 /*!< PLL input clock*7 */
+#define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMUL8 /*!< PLL input clock*8 */
+#define LL_RCC_PLL_MUL_9 RCC_CFGR_PLLMUL9 /*!< PLL input clock*9 */
+#define LL_RCC_PLL_MUL_10 RCC_CFGR_PLLMUL10 /*!< PLL input clock*10 */
+#define LL_RCC_PLL_MUL_11 RCC_CFGR_PLLMUL11 /*!< PLL input clock*11 */
+#define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMUL12 /*!< PLL input clock*12 */
+#define LL_RCC_PLL_MUL_13 RCC_CFGR_PLLMUL13 /*!< PLL input clock*13 */
+#define LL_RCC_PLL_MUL_14 RCC_CFGR_PLLMUL14 /*!< PLL input clock*14 */
+#define LL_RCC_PLL_MUL_15 RCC_CFGR_PLLMUL15 /*!< PLL input clock*15 */
+#define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMUL16 /*!< PLL input clock*16 */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE
+ * @{
+ */
+#define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< HSE/PREDIV clock selected as PLL entry clock source */
+#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
+#define LL_RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV /*!< HSI/PREDIV clock selected as PLL entry clock source */
+#else
+#define LL_RCC_PLLSOURCE_HSI_DIV_2 RCC_CFGR_PLLSRC_HSI_DIV2 /*!< HSI clock divided by 2 selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_1 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV1) /*!< HSE clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV2) /*!< HSE/2 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_3 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV3) /*!< HSE/3 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_4 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV4) /*!< HSE/4 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_5 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV5) /*!< HSE/5 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_6 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV6) /*!< HSE/6 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_7 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV7) /*!< HSE/7 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_8 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV8) /*!< HSE/8 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_9 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV9) /*!< HSE/9 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_10 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV10) /*!< HSE/10 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_11 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV11) /*!< HSE/11 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_12 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV12) /*!< HSE/12 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_13 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV13) /*!< HSE/13 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_14 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV14) /*!< HSE/14 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_15 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV15) /*!< HSE/15 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_16 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV16) /*!< HSE/16 clock selected as PLL entry clock source */
+#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_PREDIV_DIV PREDIV Division factor
+ * @{
+ */
+#define LL_RCC_PREDIV_DIV_1 RCC_CFGR2_PREDIV_DIV1 /*!< PREDIV input clock not divided */
+#define LL_RCC_PREDIV_DIV_2 RCC_CFGR2_PREDIV_DIV2 /*!< PREDIV input clock divided by 2 */
+#define LL_RCC_PREDIV_DIV_3 RCC_CFGR2_PREDIV_DIV3 /*!< PREDIV input clock divided by 3 */
+#define LL_RCC_PREDIV_DIV_4 RCC_CFGR2_PREDIV_DIV4 /*!< PREDIV input clock divided by 4 */
+#define LL_RCC_PREDIV_DIV_5 RCC_CFGR2_PREDIV_DIV5 /*!< PREDIV input clock divided by 5 */
+#define LL_RCC_PREDIV_DIV_6 RCC_CFGR2_PREDIV_DIV6 /*!< PREDIV input clock divided by 6 */
+#define LL_RCC_PREDIV_DIV_7 RCC_CFGR2_PREDIV_DIV7 /*!< PREDIV input clock divided by 7 */
+#define LL_RCC_PREDIV_DIV_8 RCC_CFGR2_PREDIV_DIV8 /*!< PREDIV input clock divided by 8 */
+#define LL_RCC_PREDIV_DIV_9 RCC_CFGR2_PREDIV_DIV9 /*!< PREDIV input clock divided by 9 */
+#define LL_RCC_PREDIV_DIV_10 RCC_CFGR2_PREDIV_DIV10 /*!< PREDIV input clock divided by 10 */
+#define LL_RCC_PREDIV_DIV_11 RCC_CFGR2_PREDIV_DIV11 /*!< PREDIV input clock divided by 11 */
+#define LL_RCC_PREDIV_DIV_12 RCC_CFGR2_PREDIV_DIV12 /*!< PREDIV input clock divided by 12 */
+#define LL_RCC_PREDIV_DIV_13 RCC_CFGR2_PREDIV_DIV13 /*!< PREDIV input clock divided by 13 */
+#define LL_RCC_PREDIV_DIV_14 RCC_CFGR2_PREDIV_DIV14 /*!< PREDIV input clock divided by 14 */
+#define LL_RCC_PREDIV_DIV_15 RCC_CFGR2_PREDIV_DIV15 /*!< PREDIV input clock divided by 15 */
+#define LL_RCC_PREDIV_DIV_16 RCC_CFGR2_PREDIV_DIV16 /*!< PREDIV input clock divided by 16 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
+ * @{
+ */
+
+/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in RCC register
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in RCC register
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
+ * @{
+ */
+
+#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
+/**
+ * @brief Helper macro to calculate the PLLCLK frequency
+ * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetMultiplicator()
+ * , @ref LL_RCC_PLL_GetPrediv());
+ * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+ * @param __PLLMUL__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLL_MUL_2
+ * @arg @ref LL_RCC_PLL_MUL_3
+ * @arg @ref LL_RCC_PLL_MUL_4
+ * @arg @ref LL_RCC_PLL_MUL_5
+ * @arg @ref LL_RCC_PLL_MUL_6
+ * @arg @ref LL_RCC_PLL_MUL_7
+ * @arg @ref LL_RCC_PLL_MUL_8
+ * @arg @ref LL_RCC_PLL_MUL_9
+ * @arg @ref LL_RCC_PLL_MUL_10
+ * @arg @ref LL_RCC_PLL_MUL_11
+ * @arg @ref LL_RCC_PLL_MUL_12
+ * @arg @ref LL_RCC_PLL_MUL_13
+ * @arg @ref LL_RCC_PLL_MUL_14
+ * @arg @ref LL_RCC_PLL_MUL_15
+ * @arg @ref LL_RCC_PLL_MUL_16
+ * @param __PLLPREDIV__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PREDIV_DIV_1
+ * @arg @ref LL_RCC_PREDIV_DIV_2
+ * @arg @ref LL_RCC_PREDIV_DIV_3
+ * @arg @ref LL_RCC_PREDIV_DIV_4
+ * @arg @ref LL_RCC_PREDIV_DIV_5
+ * @arg @ref LL_RCC_PREDIV_DIV_6
+ * @arg @ref LL_RCC_PREDIV_DIV_7
+ * @arg @ref LL_RCC_PREDIV_DIV_8
+ * @arg @ref LL_RCC_PREDIV_DIV_9
+ * @arg @ref LL_RCC_PREDIV_DIV_10
+ * @arg @ref LL_RCC_PREDIV_DIV_11
+ * @arg @ref LL_RCC_PREDIV_DIV_12
+ * @arg @ref LL_RCC_PREDIV_DIV_13
+ * @arg @ref LL_RCC_PREDIV_DIV_14
+ * @arg @ref LL_RCC_PREDIV_DIV_15
+ * @arg @ref LL_RCC_PREDIV_DIV_16
+ * @retval PLL clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__, __PLLPREDIV__) \
+ (((__INPUTFREQ__) / ((((__PLLPREDIV__) & RCC_CFGR2_PREDIV) + 1U))) * ((((__PLLMUL__) & RCC_CFGR_PLLMUL) >> RCC_POSITION_PLLMUL) + 2U))
+
+#else
+/**
+ * @brief Helper macro to calculate the PLLCLK frequency
+ * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator());
+ * @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv / HSI div 2)
+ * @param __PLLMUL__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLL_MUL_2
+ * @arg @ref LL_RCC_PLL_MUL_3
+ * @arg @ref LL_RCC_PLL_MUL_4
+ * @arg @ref LL_RCC_PLL_MUL_5
+ * @arg @ref LL_RCC_PLL_MUL_6
+ * @arg @ref LL_RCC_PLL_MUL_7
+ * @arg @ref LL_RCC_PLL_MUL_8
+ * @arg @ref LL_RCC_PLL_MUL_9
+ * @arg @ref LL_RCC_PLL_MUL_10
+ * @arg @ref LL_RCC_PLL_MUL_11
+ * @arg @ref LL_RCC_PLL_MUL_12
+ * @arg @ref LL_RCC_PLL_MUL_13
+ * @arg @ref LL_RCC_PLL_MUL_14
+ * @arg @ref LL_RCC_PLL_MUL_15
+ * @arg @ref LL_RCC_PLL_MUL_16
+ * @retval PLL clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) \
+ ((__INPUTFREQ__) * ((((__PLLMUL__) & RCC_CFGR_PLLMUL) >> RCC_POSITION_PLLMUL) + 2U))
+#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
+/**
+ * @brief Helper macro to calculate the HCLK frequency
+ * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler
+ * ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler())
+ * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
+ * @param __AHBPRESCALER__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SYSCLK_DIV_1
+ * @arg @ref LL_RCC_SYSCLK_DIV_2
+ * @arg @ref LL_RCC_SYSCLK_DIV_4
+ * @arg @ref LL_RCC_SYSCLK_DIV_8
+ * @arg @ref LL_RCC_SYSCLK_DIV_16
+ * @arg @ref LL_RCC_SYSCLK_DIV_64
+ * @arg @ref LL_RCC_SYSCLK_DIV_128
+ * @arg @ref LL_RCC_SYSCLK_DIV_256
+ * @arg @ref LL_RCC_SYSCLK_DIV_512
+ * @retval HCLK clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
+
+/**
+ * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
+ * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler
+ * ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler())
+ * @param __HCLKFREQ__ HCLK frequency
+ * @param __APB1PRESCALER__: This parameter can be one of the following values:
+ * @arg @ref LL_RCC_APB1_DIV_1
+ * @arg @ref LL_RCC_APB1_DIV_2
+ * @arg @ref LL_RCC_APB1_DIV_4
+ * @arg @ref LL_RCC_APB1_DIV_8
+ * @arg @ref LL_RCC_APB1_DIV_16
+ * @retval PCLK1 clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
+
+/**
+ * @brief Helper macro to calculate the PCLK2 frequency (ABP2)
+ * @note: __APB2PRESCALER__ be retrieved by @ref LL_RCC_GetAPB2Prescaler
+ * ex: __LL_RCC_CALC_PCLK2_FREQ(LL_RCC_GetAPB2Prescaler())
+ * @param __HCLKFREQ__ HCLK frequency
+ * @param __APB2PRESCALER__: This parameter can be one of the following values:
+ * @arg @ref LL_RCC_APB2_DIV_1
+ * @arg @ref LL_RCC_APB2_DIV_2
+ * @arg @ref LL_RCC_APB2_DIV_4
+ * @arg @ref LL_RCC_APB2_DIV_8
+ * @arg @ref LL_RCC_APB2_DIV_16
+ * @retval PCLK2 clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
+ * @{
+ */
+
+/** @defgroup RCC_LL_EF_HSE HSE
+ * @{
+ */
+
+/**
+ * @brief Enable the Clock Security System.
+ * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_CSSON);
+}
+
+/**
+ * @brief Disable the Clock Security System.
+ * @note Cannot be disabled in HSE is ready (only by hardware)
+ * @rmtoll CR CSSON LL_RCC_HSE_DisableCSS
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSE_DisableCSS(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_CSSON);
+}
+
+/**
+ * @brief Enable HSE external oscillator (HSE Bypass)
+ * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_HSEBYP);
+}
+
+/**
+ * @brief Disable HSE external oscillator (HSE Bypass)
+ * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
+}
+
+/**
+ * @brief Enable HSE crystal oscillator (HSE ON)
+ * @rmtoll CR HSEON LL_RCC_HSE_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSE_Enable(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_HSEON);
+}
+
+/**
+ * @brief Disable HSE crystal oscillator (HSE ON)
+ * @rmtoll CR HSEON LL_RCC_HSE_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSE_Disable(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
+}
+
+/**
+ * @brief Check if HSE oscillator Ready
+ * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
+{
+ return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_HSI HSI
+ * @{
+ */
+
+/**
+ * @brief Enable HSI oscillator
+ * @rmtoll CR HSION LL_RCC_HSI_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSI_Enable(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_HSION);
+}
+
+/**
+ * @brief Disable HSI oscillator
+ * @rmtoll CR HSION LL_RCC_HSI_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSI_Disable(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_HSION);
+}
+
+/**
+ * @brief Check if HSI clock is ready
+ * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
+{
+ return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
+}
+
+/**
+ * @brief Get HSI Calibration value
+ * @note When HSITRIM is written, HSICAL is updated with the sum of
+ * HSITRIM and the factory trim value
+ * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration
+ * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
+ */
+__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos);
+}
+
+/**
+ * @brief Set HSI Calibration trimming
+ * @note user-programmable trimming value that is added to the HSICAL
+ * @note Default value is 16, which, when added to the HSICAL value,
+ * should trim the HSI to 16 MHz +/- 1 %
+ * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming
+ * @param Value between Min_Data = 0x00 and Max_Data = 0x1F
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
+{
+ MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos);
+}
+
+/**
+ * @brief Get HSI Calibration trimming
+ * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming
+ * @retval Between Min_Data = 0x00 and Max_Data = 0x1F
+ */
+__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_LSE LSE
+ * @{
+ */
+
+/**
+ * @brief Enable Low Speed External (LSE) crystal.
+ * @rmtoll BDCR LSEON LL_RCC_LSE_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSE_Enable(void)
+{
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
+}
+
+/**
+ * @brief Disable Low Speed External (LSE) crystal.
+ * @rmtoll BDCR LSEON LL_RCC_LSE_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSE_Disable(void)
+{
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
+}
+
+/**
+ * @brief Enable external clock source (LSE bypass).
+ * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
+{
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
+}
+
+/**
+ * @brief Disable external clock source (LSE bypass).
+ * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
+{
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
+}
+
+/**
+ * @brief Set LSE oscillator drive capability
+ * @note The oscillator is in Xtal mode when it is not in bypass mode.
+ * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
+ * @param LSEDrive This parameter can be one of the following values:
+ * @arg @ref LL_RCC_LSEDRIVE_LOW
+ * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
+ * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
+ * @arg @ref LL_RCC_LSEDRIVE_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
+{
+ MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
+}
+
+/**
+ * @brief Get LSE oscillator drive capability
+ * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_LSEDRIVE_LOW
+ * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
+ * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
+ * @arg @ref LL_RCC_LSEDRIVE_HIGH
+ */
+__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
+{
+ return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
+}
+
+/**
+ * @brief Check if LSE oscillator Ready
+ * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
+{
+ return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_LSI LSI
+ * @{
+ */
+
+/**
+ * @brief Enable LSI Oscillator
+ * @rmtoll CSR LSION LL_RCC_LSI_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSI_Enable(void)
+{
+ SET_BIT(RCC->CSR, RCC_CSR_LSION);
+}
+
+/**
+ * @brief Disable LSI Oscillator
+ * @rmtoll CSR LSION LL_RCC_LSI_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSI_Disable(void)
+{
+ CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
+}
+
+/**
+ * @brief Check if LSI is Ready
+ * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
+{
+ return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_System System
+ * @{
+ */
+
+/**
+ * @brief Configure the system clock source
+ * @rmtoll CFGR SW LL_RCC_SetSysClkSource
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
+}
+
+/**
+ * @brief Get the system clock source
+ * @rmtoll CFGR SWS LL_RCC_GetSysClkSource
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
+}
+
+/**
+ * @brief Set AHB prescaler
+ * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SYSCLK_DIV_1
+ * @arg @ref LL_RCC_SYSCLK_DIV_2
+ * @arg @ref LL_RCC_SYSCLK_DIV_4
+ * @arg @ref LL_RCC_SYSCLK_DIV_8
+ * @arg @ref LL_RCC_SYSCLK_DIV_16
+ * @arg @ref LL_RCC_SYSCLK_DIV_64
+ * @arg @ref LL_RCC_SYSCLK_DIV_128
+ * @arg @ref LL_RCC_SYSCLK_DIV_256
+ * @arg @ref LL_RCC_SYSCLK_DIV_512
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
+}
+
+/**
+ * @brief Set APB1 prescaler
+ * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_RCC_APB1_DIV_1
+ * @arg @ref LL_RCC_APB1_DIV_2
+ * @arg @ref LL_RCC_APB1_DIV_4
+ * @arg @ref LL_RCC_APB1_DIV_8
+ * @arg @ref LL_RCC_APB1_DIV_16
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
+}
+
+/**
+ * @brief Set APB2 prescaler
+ * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_RCC_APB2_DIV_1
+ * @arg @ref LL_RCC_APB2_DIV_2
+ * @arg @ref LL_RCC_APB2_DIV_4
+ * @arg @ref LL_RCC_APB2_DIV_8
+ * @arg @ref LL_RCC_APB2_DIV_16
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
+}
+
+/**
+ * @brief Get AHB prescaler
+ * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_SYSCLK_DIV_1
+ * @arg @ref LL_RCC_SYSCLK_DIV_2
+ * @arg @ref LL_RCC_SYSCLK_DIV_4
+ * @arg @ref LL_RCC_SYSCLK_DIV_8
+ * @arg @ref LL_RCC_SYSCLK_DIV_16
+ * @arg @ref LL_RCC_SYSCLK_DIV_64
+ * @arg @ref LL_RCC_SYSCLK_DIV_128
+ * @arg @ref LL_RCC_SYSCLK_DIV_256
+ * @arg @ref LL_RCC_SYSCLK_DIV_512
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
+}
+
+/**
+ * @brief Get APB1 prescaler
+ * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_APB1_DIV_1
+ * @arg @ref LL_RCC_APB1_DIV_2
+ * @arg @ref LL_RCC_APB1_DIV_4
+ * @arg @ref LL_RCC_APB1_DIV_8
+ * @arg @ref LL_RCC_APB1_DIV_16
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
+}
+
+/**
+ * @brief Get APB2 prescaler
+ * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_APB2_DIV_1
+ * @arg @ref LL_RCC_APB2_DIV_2
+ * @arg @ref LL_RCC_APB2_DIV_4
+ * @arg @ref LL_RCC_APB2_DIV_8
+ * @arg @ref LL_RCC_APB2_DIV_16
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_MCO MCO
+ * @{
+ */
+
+/**
+ * @brief Configure MCOx
+ * @rmtoll CFGR MCO LL_RCC_ConfigMCO\n
+ * CFGR MCOPRE LL_RCC_ConfigMCO\n
+ * CFGR PLLNODIV LL_RCC_ConfigMCO
+ * @param MCOxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
+ * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
+ * @arg @ref LL_RCC_MCO1SOURCE_HSI
+ * @arg @ref LL_RCC_MCO1SOURCE_HSE
+ * @arg @ref LL_RCC_MCO1SOURCE_LSI
+ * @arg @ref LL_RCC_MCO1SOURCE_LSE
+ * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK (*)
+ * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK_DIV_2
+ *
+ * (*) value not defined in all devices
+ * @param MCOxPrescaler This parameter can be one of the following values:
+ * @arg @ref LL_RCC_MCO1_DIV_1
+ * @arg @ref LL_RCC_MCO1_DIV_2 (*)
+ * @arg @ref LL_RCC_MCO1_DIV_4 (*)
+ * @arg @ref LL_RCC_MCO1_DIV_8 (*)
+ * @arg @ref LL_RCC_MCO1_DIV_16 (*)
+ * @arg @ref LL_RCC_MCO1_DIV_32 (*)
+ * @arg @ref LL_RCC_MCO1_DIV_64 (*)
+ * @arg @ref LL_RCC_MCO1_DIV_128 (*)
+ *
+ * (*) value not defined in all devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
+{
+#if defined(RCC_CFGR_MCOPRE)
+#if defined(RCC_CFGR_PLLNODIV)
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE | RCC_CFGR_PLLNODIV, MCOxSource | MCOxPrescaler);
+#else
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler);
+#endif /* RCC_CFGR_PLLNODIV */
+#else
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL, MCOxSource);
+#endif /* RCC_CFGR_MCOPRE */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
+ * @{
+ */
+
+/**
+ * @brief Configure USARTx clock source
+ * @rmtoll CFGR3 USART1SW LL_RCC_SetUSARTClockSource\n
+ * CFGR3 USART2SW LL_RCC_SetUSARTClockSource\n
+ * CFGR3 USART3SW LL_RCC_SetUSARTClockSource
+ * @param USARTxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1 (*)
+ * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 (*)
+ * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*)
+ * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*)
+ * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*)
+ * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*)
+ * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
+ * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
+ * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)
+ * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
+{
+ MODIFY_REG(RCC->CFGR3, (RCC_CFGR3_USART1SW << ((USARTxSource & 0xFF000000U) >> 24U)), (USARTxSource & 0x00FFFFFFU));
+}
+
+#if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW)
+/**
+ * @brief Configure UARTx clock source
+ * @rmtoll CFGR3 UART4SW LL_RCC_SetUARTClockSource\n
+ * CFGR3 UART5SW LL_RCC_SetUARTClockSource
+ * @param UARTxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource)
+{
+ MODIFY_REG(RCC->CFGR3, ((UARTxSource & 0x0000FFFFU) << 8U), (UARTxSource & (RCC_CFGR3_UART4SW | RCC_CFGR3_UART5SW)));
+}
+#endif /* RCC_CFGR3_UART4SW || RCC_CFGR3_UART5SW */
+
+/**
+ * @brief Configure I2Cx clock source
+ * @rmtoll CFGR3 I2C1SW LL_RCC_SetI2CClockSource\n
+ * CFGR3 I2C2SW LL_RCC_SetI2CClockSource\n
+ * CFGR3 I2C3SW LL_RCC_SetI2CClockSource
+ * @param I2CxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*)
+ * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*)
+ * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*)
+ * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
+{
+ MODIFY_REG(RCC->CFGR3, ((I2CxSource & 0xFF000000U) >> 24U), (I2CxSource & 0x00FFFFFFU));
+}
+
+#if defined(RCC_CFGR_I2SSRC)
+/**
+ * @brief Configure I2Sx clock source
+ * @rmtoll CFGR I2SSRC LL_RCC_SetI2SClockSource
+ * @param I2SxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_I2S_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_I2S_CLKSOURCE_PIN
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, I2SxSource);
+}
+#endif /* RCC_CFGR_I2SSRC */
+
+#if defined(RCC_CFGR3_TIMSW)
+/**
+ * @brief Configure TIMx clock source
+ * @rmtoll CFGR3 TIM1SW LL_RCC_SetTIMClockSource\n
+ * CFGR3 TIM8SW LL_RCC_SetTIMClockSource\n
+ * CFGR3 TIM15SW LL_RCC_SetTIMClockSource\n
+ * CFGR3 TIM16SW LL_RCC_SetTIMClockSource\n
+ * CFGR3 TIM17SW LL_RCC_SetTIMClockSource\n
+ * CFGR3 TIM20SW LL_RCC_SetTIMClockSource\n
+ * CFGR3 TIM2SW LL_RCC_SetTIMClockSource\n
+ * CFGR3 TIM34SW LL_RCC_SetTIMClockSource
+ * @param TIMxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_TIM1_CLKSOURCE_PCLK2
+ * @arg @ref LL_RCC_TIM1_CLKSOURCE_PLL
+ * @arg @ref LL_RCC_TIM8_CLKSOURCE_PCLK2 (*)
+ * @arg @ref LL_RCC_TIM8_CLKSOURCE_PLL (*)
+ * @arg @ref LL_RCC_TIM15_CLKSOURCE_PCLK2 (*)
+ * @arg @ref LL_RCC_TIM15_CLKSOURCE_PLL (*)
+ * @arg @ref LL_RCC_TIM16_CLKSOURCE_PCLK2 (*)
+ * @arg @ref LL_RCC_TIM16_CLKSOURCE_PLL (*)
+ * @arg @ref LL_RCC_TIM17_CLKSOURCE_PCLK2 (*)
+ * @arg @ref LL_RCC_TIM17_CLKSOURCE_PLL (*)
+ * @arg @ref LL_RCC_TIM20_CLKSOURCE_PCLK2 (*)
+ * @arg @ref LL_RCC_TIM20_CLKSOURCE_PLL (*)
+ * @arg @ref LL_RCC_TIM2_CLKSOURCE_PCLK1 (*)
+ * @arg @ref LL_RCC_TIM2_CLKSOURCE_PLL (*)
+ * @arg @ref LL_RCC_TIM34_CLKSOURCE_PCLK1 (*)
+ * @arg @ref LL_RCC_TIM34_CLKSOURCE_PLL (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetTIMClockSource(uint32_t TIMxSource)
+{
+ MODIFY_REG(RCC->CFGR3, (RCC_CFGR3_TIM1SW << (TIMxSource >> 27U)), (TIMxSource & 0x03FFFFFFU));
+}
+#endif /* RCC_CFGR3_TIMSW */
+
+#if defined(HRTIM1)
+/**
+ * @brief Configure HRTIMx clock source
+ * @rmtoll CFGR3 HRTIMSW LL_RCC_SetHRTIMClockSource
+ * @param HRTIMxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_HRTIM1_CLKSOURCE_PCLK2
+ * @arg @ref LL_RCC_HRTIM1_CLKSOURCE_PLL
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetHRTIMClockSource(uint32_t HRTIMxSource)
+{
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_HRTIMSW, HRTIMxSource);
+}
+#endif /* HRTIM1 */
+
+#if defined(CEC)
+/**
+ * @brief Configure CEC clock source
+ * @rmtoll CFGR3 CECSW LL_RCC_SetCECClockSource
+ * @param CECxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV244
+ * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t CECxSource)
+{
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, CECxSource);
+}
+#endif /* CEC */
+
+#if defined(USB)
+/**
+ * @brief Configure USB clock source
+ * @rmtoll CFGR USBPRE LL_RCC_SetUSBClockSource
+ * @param USBxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
+ * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, USBxSource);
+}
+#endif /* USB */
+
+#if defined(RCC_CFGR_ADCPRE)
+/**
+ * @brief Configure ADC clock source
+ * @rmtoll CFGR ADCPRE LL_RCC_SetADCClockSource
+ * @param ADCxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2
+ * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4
+ * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6
+ * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, ADCxSource);
+}
+
+#elif defined(RCC_CFGR2_ADC1PRES)
+/**
+ * @brief Configure ADC clock source
+ * @rmtoll CFGR2 ADC1PRES LL_RCC_SetADCClockSource
+ * @param ADCxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_ADC1_CLKSRC_HCLK
+ * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_1
+ * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_2
+ * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_4
+ * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_6
+ * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_8
+ * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_10
+ * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_12
+ * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_16
+ * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_32
+ * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_64
+ * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_128
+ * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_256
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
+{
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADC1PRES, ADCxSource);
+}
+
+#elif defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
+/**
+ * @brief Configure ADC clock source
+ * @rmtoll CFGR2 ADCPRE12 LL_RCC_SetADCClockSource\n
+ * CFGR2 ADCPRE34 LL_RCC_SetADCClockSource
+ * @param ADCxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_ADC12_CLKSRC_HCLK
+ * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_1
+ * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_2
+ * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_4
+ * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_6
+ * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_8
+ * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_10
+ * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_12
+ * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_16
+ * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_32
+ * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_64
+ * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_128
+ * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_256
+ * @arg @ref LL_RCC_ADC34_CLKSRC_HCLK (*)
+ * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_1 (*)
+ * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_2 (*)
+ * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_4 (*)
+ * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_6 (*)
+ * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_8 (*)
+ * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_10 (*)
+ * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_12 (*)
+ * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_16 (*)
+ * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_32 (*)
+ * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_64 (*)
+ * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_128 (*)
+ * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_256 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
+{
+#if defined(RCC_CFGR2_ADCPRE34)
+ MODIFY_REG(RCC->CFGR2, (ADCxSource >> 16U), (ADCxSource & 0x0000FFFFU));
+#else
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, ADCxSource);
+#endif /* RCC_CFGR2_ADCPRE34 */
+}
+#endif /* RCC_CFGR_ADCPRE */
+
+#if defined(RCC_CFGR_SDPRE)
+/**
+ * @brief Configure SDADCx clock source
+ * @rmtoll CFGR SDPRE LL_RCC_SetSDADCClockSource
+ * @param SDADCxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_1
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_2
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_4
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_6
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_8
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_10
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_12
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_14
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_16
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_20
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_24
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_28
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_32
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_36
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_40
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_44
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_48
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetSDADCClockSource(uint32_t SDADCxSource)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_SDPRE, SDADCxSource);
+}
+#endif /* RCC_CFGR_SDPRE */
+
+/**
+ * @brief Get USARTx clock source
+ * @rmtoll CFGR3 USART1SW LL_RCC_GetUSARTClockSource\n
+ * CFGR3 USART2SW LL_RCC_GetUSARTClockSource\n
+ * CFGR3 USART3SW LL_RCC_GetUSARTClockSource
+ * @param USARTx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_USART1_CLKSOURCE
+ * @arg @ref LL_RCC_USART2_CLKSOURCE (*)
+ * @arg @ref LL_RCC_USART3_CLKSOURCE (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1 (*)
+ * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 (*)
+ * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*)
+ * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*)
+ * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*)
+ * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*)
+ * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
+ * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
+ * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)
+ * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)
+ *
+ * (*) value not defined in all devices.
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR3, (RCC_CFGR3_USART1SW << USARTx)) | (USARTx << 24U));
+}
+
+#if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW)
+/**
+ * @brief Get UARTx clock source
+ * @rmtoll CFGR3 UART4SW LL_RCC_GetUARTClockSource\n
+ * CFGR3 UART5SW LL_RCC_GetUARTClockSource
+ * @param UARTx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_UART4_CLKSOURCE
+ * @arg @ref LL_RCC_UART5_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR3, UARTx) | (UARTx >> 8U));
+}
+#endif /* RCC_CFGR3_UART4SW || RCC_CFGR3_UART5SW */
+
+/**
+ * @brief Get I2Cx clock source
+ * @rmtoll CFGR3 I2C1SW LL_RCC_GetI2CClockSource\n
+ * CFGR3 I2C2SW LL_RCC_GetI2CClockSource\n
+ * CFGR3 I2C3SW LL_RCC_GetI2CClockSource
+ * @param I2Cx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_I2C1_CLKSOURCE
+ * @arg @ref LL_RCC_I2C2_CLKSOURCE (*)
+ * @arg @ref LL_RCC_I2C3_CLKSOURCE (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*)
+ * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*)
+ * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*)
+ * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK (*)
+ *
+ * (*) value not defined in all devices.
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR3, I2Cx) | (I2Cx << 24U));
+}
+
+#if defined(RCC_CFGR_I2SSRC)
+/**
+ * @brief Get I2Sx clock source
+ * @rmtoll CFGR I2SSRC LL_RCC_GetI2SClockSource
+ * @param I2Sx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_I2S_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_I2S_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_I2S_CLKSOURCE_PIN
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx));
+}
+#endif /* RCC_CFGR_I2SSRC */
+
+#if defined(RCC_CFGR3_TIMSW)
+/**
+ * @brief Get TIMx clock source
+ * @rmtoll CFGR3 TIM1SW LL_RCC_GetTIMClockSource\n
+ * CFGR3 TIM8SW LL_RCC_GetTIMClockSource\n
+ * CFGR3 TIM15SW LL_RCC_GetTIMClockSource\n
+ * CFGR3 TIM16SW LL_RCC_GetTIMClockSource\n
+ * CFGR3 TIM17SW LL_RCC_GetTIMClockSource\n
+ * CFGR3 TIM20SW LL_RCC_GetTIMClockSource\n
+ * CFGR3 TIM2SW LL_RCC_GetTIMClockSource\n
+ * CFGR3 TIM34SW LL_RCC_GetTIMClockSource
+ * @param TIMx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_TIM1_CLKSOURCE
+ * @arg @ref LL_RCC_TIM2_CLKSOURCE (*)
+ * @arg @ref LL_RCC_TIM8_CLKSOURCE (*)
+ * @arg @ref LL_RCC_TIM15_CLKSOURCE (*)
+ * @arg @ref LL_RCC_TIM16_CLKSOURCE (*)
+ * @arg @ref LL_RCC_TIM17_CLKSOURCE (*)
+ * @arg @ref LL_RCC_TIM20_CLKSOURCE (*)
+ * @arg @ref LL_RCC_TIM34_CLKSOURCE (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_TIM1_CLKSOURCE_PCLK2
+ * @arg @ref LL_RCC_TIM1_CLKSOURCE_PLL
+ * @arg @ref LL_RCC_TIM8_CLKSOURCE_PCLK2 (*)
+ * @arg @ref LL_RCC_TIM8_CLKSOURCE_PLL (*)
+ * @arg @ref LL_RCC_TIM15_CLKSOURCE_PCLK2 (*)
+ * @arg @ref LL_RCC_TIM15_CLKSOURCE_PLL (*)
+ * @arg @ref LL_RCC_TIM16_CLKSOURCE_PCLK2 (*)
+ * @arg @ref LL_RCC_TIM16_CLKSOURCE_PLL (*)
+ * @arg @ref LL_RCC_TIM17_CLKSOURCE_PCLK2 (*)
+ * @arg @ref LL_RCC_TIM17_CLKSOURCE_PLL (*)
+ * @arg @ref LL_RCC_TIM20_CLKSOURCE_PCLK2 (*)
+ * @arg @ref LL_RCC_TIM20_CLKSOURCE_PLL (*)
+ * @arg @ref LL_RCC_TIM2_CLKSOURCE_PCLK1 (*)
+ * @arg @ref LL_RCC_TIM2_CLKSOURCE_PLL (*)
+ * @arg @ref LL_RCC_TIM34_CLKSOURCE_PCLK1 (*)
+ * @arg @ref LL_RCC_TIM34_CLKSOURCE_PLL (*)
+ *
+ * (*) value not defined in all devices.
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetTIMClockSource(uint32_t TIMx)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR3, (RCC_CFGR3_TIM1SW << TIMx)) | (TIMx << 27U));
+}
+#endif /* RCC_CFGR3_TIMSW */
+
+#if defined(HRTIM1)
+/**
+ * @brief Get HRTIMx clock source
+ * @rmtoll CFGR3 HRTIMSW LL_RCC_GetHRTIMClockSource
+ * @param HRTIMx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_HRTIM1_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_HRTIM1_CLKSOURCE_PCLK2
+ * @arg @ref LL_RCC_HRTIM1_CLKSOURCE_PLL
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetHRTIMClockSource(uint32_t HRTIMx)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR3, HRTIMx));
+}
+#endif /* HRTIM1 */
+
+#if defined(CEC)
+/**
+ * @brief Get CEC clock source
+ * @rmtoll CFGR3 CECSW LL_RCC_GetCECClockSource
+ * @param CECx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_CEC_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV244
+ * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR3, CECx));
+}
+#endif /* CEC */
+
+#if defined(USB)
+/**
+ * @brief Get USBx clock source
+ * @rmtoll CFGR USBPRE LL_RCC_GetUSBClockSource
+ * @param USBx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_USB_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
+ * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR, USBx));
+}
+#endif /* USB */
+
+#if defined(RCC_CFGR_ADCPRE)
+/**
+ * @brief Get ADCx clock source
+ * @rmtoll CFGR ADCPRE LL_RCC_GetADCClockSource
+ * @param ADCx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_ADC_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2
+ * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4
+ * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6
+ * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR, ADCx));
+}
+
+#elif defined(RCC_CFGR2_ADC1PRES)
+/**
+ * @brief Get ADCx clock source
+ * @rmtoll CFGR2 ADC1PRES LL_RCC_GetADCClockSource
+ * @param ADCx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_ADC1_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_ADC1_CLKSRC_HCLK
+ * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_1
+ * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_2
+ * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_4
+ * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_6
+ * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_8
+ * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_10
+ * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_12
+ * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_16
+ * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_32
+ * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_64
+ * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_128
+ * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_256
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR2, ADCx));
+}
+
+#elif defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
+/**
+ * @brief Get ADCx clock source
+ * @rmtoll CFGR2 ADCPRE12 LL_RCC_GetADCClockSource\n
+ * CFGR2 ADCPRE34 LL_RCC_GetADCClockSource
+ * @param ADCx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_ADC12_CLKSOURCE
+ * @arg @ref LL_RCC_ADC34_CLKSOURCE (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_ADC12_CLKSRC_HCLK
+ * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_1
+ * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_2
+ * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_4
+ * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_6
+ * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_8
+ * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_10
+ * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_12
+ * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_16
+ * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_32
+ * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_64
+ * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_128
+ * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_256
+ * @arg @ref LL_RCC_ADC34_CLKSRC_HCLK (*)
+ * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_1 (*)
+ * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_2 (*)
+ * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_4 (*)
+ * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_6 (*)
+ * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_8 (*)
+ * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_10 (*)
+ * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_12 (*)
+ * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_16 (*)
+ * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_32 (*)
+ * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_64 (*)
+ * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_128 (*)
+ * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_256 (*)
+ *
+ * (*) value not defined in all devices.
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
+{
+#if defined(RCC_CFGR2_ADCPRE34)
+ return (uint32_t)(READ_BIT(RCC->CFGR2, ADCx) | (ADCx << 16U));
+#else
+ return (uint32_t)(READ_BIT(RCC->CFGR2, ADCx));
+#endif /*RCC_CFGR2_ADCPRE34*/
+}
+#endif /* RCC_CFGR_ADCPRE */
+
+#if defined(RCC_CFGR_SDPRE)
+/**
+ * @brief Get SDADCx clock source
+ * @rmtoll CFGR SDPRE LL_RCC_GetSDADCClockSource
+ * @param SDADCx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SDADC_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_1
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_2
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_4
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_6
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_8
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_10
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_12
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_14
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_16
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_20
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_24
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_28
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_32
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_36
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_40
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_44
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_48
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetSDADCClockSource(uint32_t SDADCx)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR, SDADCx));
+}
+#endif /* RCC_CFGR_SDPRE */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_RTC RTC
+ * @{
+ */
+
+/**
+ * @brief Set RTC Clock Source
+ * @note Once the RTC clock source has been selected, it cannot be changed any more unless
+ * the Backup domain is reset. The BDRST bit can be used to reset them.
+ * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
+{
+ MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
+}
+
+/**
+ * @brief Get RTC Clock Source
+ * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
+{
+ return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
+}
+
+/**
+ * @brief Enable RTC
+ * @rmtoll BDCR RTCEN LL_RCC_EnableRTC
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableRTC(void)
+{
+ SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
+}
+
+/**
+ * @brief Disable RTC
+ * @rmtoll BDCR RTCEN LL_RCC_DisableRTC
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableRTC(void)
+{
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
+}
+
+/**
+ * @brief Check if RTC has been enabled or not
+ * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
+{
+ return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
+}
+
+/**
+ * @brief Force the Backup domain reset
+ * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
+{
+ SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
+}
+
+/**
+ * @brief Release the Backup domain reset
+ * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
+{
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_PLL PLL
+ * @{
+ */
+
+/**
+ * @brief Enable PLL
+ * @rmtoll CR PLLON LL_RCC_PLL_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_Enable(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_PLLON);
+}
+
+/**
+ * @brief Disable PLL
+ * @note Cannot be disabled if the PLL clock is used as the system clock
+ * @rmtoll CR PLLON LL_RCC_PLL_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_Disable(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
+}
+
+/**
+ * @brief Check if PLL Ready
+ * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
+{
+ return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
+}
+
+#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
+/**
+ * @brief Configure PLL used for SYSCLK Domain
+ * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
+ * CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n
+ * CFGR2 PREDIV LL_RCC_PLL_ConfigDomain_SYS
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @param PLLMul This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLL_MUL_2
+ * @arg @ref LL_RCC_PLL_MUL_3
+ * @arg @ref LL_RCC_PLL_MUL_4
+ * @arg @ref LL_RCC_PLL_MUL_5
+ * @arg @ref LL_RCC_PLL_MUL_6
+ * @arg @ref LL_RCC_PLL_MUL_7
+ * @arg @ref LL_RCC_PLL_MUL_8
+ * @arg @ref LL_RCC_PLL_MUL_9
+ * @arg @ref LL_RCC_PLL_MUL_10
+ * @arg @ref LL_RCC_PLL_MUL_11
+ * @arg @ref LL_RCC_PLL_MUL_12
+ * @arg @ref LL_RCC_PLL_MUL_13
+ * @arg @ref LL_RCC_PLL_MUL_14
+ * @arg @ref LL_RCC_PLL_MUL_15
+ * @arg @ref LL_RCC_PLL_MUL_16
+ * @param PLLDiv This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PREDIV_DIV_1
+ * @arg @ref LL_RCC_PREDIV_DIV_2
+ * @arg @ref LL_RCC_PREDIV_DIV_3
+ * @arg @ref LL_RCC_PREDIV_DIV_4
+ * @arg @ref LL_RCC_PREDIV_DIV_5
+ * @arg @ref LL_RCC_PREDIV_DIV_6
+ * @arg @ref LL_RCC_PREDIV_DIV_7
+ * @arg @ref LL_RCC_PREDIV_DIV_8
+ * @arg @ref LL_RCC_PREDIV_DIV_9
+ * @arg @ref LL_RCC_PREDIV_DIV_10
+ * @arg @ref LL_RCC_PREDIV_DIV_11
+ * @arg @ref LL_RCC_PREDIV_DIV_12
+ * @arg @ref LL_RCC_PREDIV_DIV_13
+ * @arg @ref LL_RCC_PREDIV_DIV_14
+ * @arg @ref LL_RCC_PREDIV_DIV_15
+ * @arg @ref LL_RCC_PREDIV_DIV_16
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul, uint32_t PLLDiv)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL, Source | PLLMul);
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, PLLDiv);
+}
+
+#else
+
+/**
+ * @brief Configure PLL used for SYSCLK Domain
+ * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
+ * CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n
+ * CFGR2 PREDIV LL_RCC_PLL_ConfigDomain_SYS
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_1
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_2
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_3
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_4
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_5
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_6
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_7
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_8
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_9
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_10
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_11
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_12
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_13
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_14
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_15
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_16
+ * @param PLLMul This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLL_MUL_2
+ * @arg @ref LL_RCC_PLL_MUL_3
+ * @arg @ref LL_RCC_PLL_MUL_4
+ * @arg @ref LL_RCC_PLL_MUL_5
+ * @arg @ref LL_RCC_PLL_MUL_6
+ * @arg @ref LL_RCC_PLL_MUL_7
+ * @arg @ref LL_RCC_PLL_MUL_8
+ * @arg @ref LL_RCC_PLL_MUL_9
+ * @arg @ref LL_RCC_PLL_MUL_10
+ * @arg @ref LL_RCC_PLL_MUL_11
+ * @arg @ref LL_RCC_PLL_MUL_12
+ * @arg @ref LL_RCC_PLL_MUL_13
+ * @arg @ref LL_RCC_PLL_MUL_14
+ * @arg @ref LL_RCC_PLL_MUL_15
+ * @arg @ref LL_RCC_PLL_MUL_16
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL, (Source & RCC_CFGR_PLLSRC) | PLLMul);
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (Source & RCC_CFGR2_PREDIV));
+}
+#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
+
+/**
+ * @brief Get the oscillator used as PLL clock source.
+ * @rmtoll CFGR PLLSRC LL_RCC_PLL_GetMainSource
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_HSI (*)
+ * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ *
+ * (*) value not defined in all devices
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC));
+}
+
+/**
+ * @brief Get PLL multiplication Factor
+ * @rmtoll CFGR PLLMUL LL_RCC_PLL_GetMultiplicator
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLL_MUL_2
+ * @arg @ref LL_RCC_PLL_MUL_3
+ * @arg @ref LL_RCC_PLL_MUL_4
+ * @arg @ref LL_RCC_PLL_MUL_5
+ * @arg @ref LL_RCC_PLL_MUL_6
+ * @arg @ref LL_RCC_PLL_MUL_7
+ * @arg @ref LL_RCC_PLL_MUL_8
+ * @arg @ref LL_RCC_PLL_MUL_9
+ * @arg @ref LL_RCC_PLL_MUL_10
+ * @arg @ref LL_RCC_PLL_MUL_11
+ * @arg @ref LL_RCC_PLL_MUL_12
+ * @arg @ref LL_RCC_PLL_MUL_13
+ * @arg @ref LL_RCC_PLL_MUL_14
+ * @arg @ref LL_RCC_PLL_MUL_15
+ * @arg @ref LL_RCC_PLL_MUL_16
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMUL));
+}
+
+/**
+ * @brief Get PREDIV division factor for the main PLL
+ * @note They can be written only when the PLL is disabled
+ * @rmtoll CFGR2 PREDIV LL_RCC_PLL_GetPrediv
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PREDIV_DIV_1
+ * @arg @ref LL_RCC_PREDIV_DIV_2
+ * @arg @ref LL_RCC_PREDIV_DIV_3
+ * @arg @ref LL_RCC_PREDIV_DIV_4
+ * @arg @ref LL_RCC_PREDIV_DIV_5
+ * @arg @ref LL_RCC_PREDIV_DIV_6
+ * @arg @ref LL_RCC_PREDIV_DIV_7
+ * @arg @ref LL_RCC_PREDIV_DIV_8
+ * @arg @ref LL_RCC_PREDIV_DIV_9
+ * @arg @ref LL_RCC_PREDIV_DIV_10
+ * @arg @ref LL_RCC_PREDIV_DIV_11
+ * @arg @ref LL_RCC_PREDIV_DIV_12
+ * @arg @ref LL_RCC_PREDIV_DIV_13
+ * @arg @ref LL_RCC_PREDIV_DIV_14
+ * @arg @ref LL_RCC_PREDIV_DIV_15
+ * @arg @ref LL_RCC_PREDIV_DIV_16
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetPrediv(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
+ * @{
+ */
+
+/**
+ * @brief Clear LSI ready interrupt flag
+ * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
+}
+
+/**
+ * @brief Clear LSE ready interrupt flag
+ * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
+}
+
+/**
+ * @brief Clear HSI ready interrupt flag
+ * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
+}
+
+/**
+ * @brief Clear HSE ready interrupt flag
+ * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
+}
+
+/**
+ * @brief Clear PLL ready interrupt flag
+ * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
+}
+
+/**
+ * @brief Clear Clock security system interrupt flag
+ * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_CSSC);
+}
+
+/**
+ * @brief Check if LSI ready interrupt occurred or not
+ * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF));
+}
+
+/**
+ * @brief Check if LSE ready interrupt occurred or not
+ * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF));
+}
+
+/**
+ * @brief Check if HSI ready interrupt occurred or not
+ * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF));
+}
+
+/**
+ * @brief Check if HSE ready interrupt occurred or not
+ * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF));
+}
+
+#if defined(RCC_CFGR_MCOF)
+/**
+ * @brief Check if switch to new MCO source is effective or not
+ * @rmtoll CFGR MCOF LL_RCC_IsActiveFlag_MCO1
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MCO1(void)
+{
+ return (READ_BIT(RCC->CFGR, RCC_CFGR_MCOF) == (RCC_CFGR_MCOF));
+}
+#endif /* RCC_CFGR_MCOF */
+
+/**
+ * @brief Check if PLL ready interrupt occurred or not
+ * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF));
+}
+
+/**
+ * @brief Check if Clock security system interrupt occurred or not
+ * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF));
+}
+
+/**
+ * @brief Check if RCC flag Independent Watchdog reset is set or not.
+ * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
+{
+ return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
+}
+
+/**
+ * @brief Check if RCC flag Low Power reset is set or not.
+ * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
+{
+ return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
+}
+
+/**
+ * @brief Check if RCC flag is set or not.
+ * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
+{
+ return (READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF));
+}
+
+/**
+ * @brief Check if RCC flag Pin reset is set or not.
+ * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
+{
+ return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
+}
+
+/**
+ * @brief Check if RCC flag POR/PDR reset is set or not.
+ * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
+{
+ return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));
+}
+
+/**
+ * @brief Check if RCC flag Software reset is set or not.
+ * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
+{
+ return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
+}
+
+/**
+ * @brief Check if RCC flag Window Watchdog reset is set or not.
+ * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
+{
+ return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
+}
+
+#if defined(RCC_CSR_V18PWRRSTF)
+/**
+ * @brief Check if RCC Reset flag of the 1.8 V domain is set or not.
+ * @rmtoll CSR V18PWRRSTF LL_RCC_IsActiveFlag_V18PWRRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_V18PWRRST(void)
+{
+ return (READ_BIT(RCC->CSR, RCC_CSR_V18PWRRSTF) == (RCC_CSR_V18PWRRSTF));
+}
+#endif /* RCC_CSR_V18PWRRSTF */
+
+/**
+ * @brief Set RMVF bit to clear the reset flags.
+ * @rmtoll CSR RMVF LL_RCC_ClearResetFlags
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
+{
+ SET_BIT(RCC->CSR, RCC_CSR_RMVF);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_IT_Management IT Management
+ * @{
+ */
+
+/**
+ * @brief Enable LSI ready interrupt
+ * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
+}
+
+/**
+ * @brief Enable LSE ready interrupt
+ * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
+}
+
+/**
+ * @brief Enable HSI ready interrupt
+ * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
+}
+
+/**
+ * @brief Enable HSE ready interrupt
+ * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
+}
+
+/**
+ * @brief Enable PLL ready interrupt
+ * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
+}
+
+/**
+ * @brief Disable LSI ready interrupt
+ * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
+{
+ CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
+}
+
+/**
+ * @brief Disable LSE ready interrupt
+ * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
+{
+ CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
+}
+
+/**
+ * @brief Disable HSI ready interrupt
+ * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
+{
+ CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
+}
+
+/**
+ * @brief Disable HSE ready interrupt
+ * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
+{
+ CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
+}
+
+/**
+ * @brief Disable PLL ready interrupt
+ * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
+{
+ CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
+}
+
+/**
+ * @brief Checks if LSI ready interrupt source is enabled or disabled.
+ * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE));
+}
+
+/**
+ * @brief Checks if LSE ready interrupt source is enabled or disabled.
+ * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE));
+}
+
+/**
+ * @brief Checks if HSI ready interrupt source is enabled or disabled.
+ * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE));
+}
+
+/**
+ * @brief Checks if HSE ready interrupt source is enabled or disabled.
+ * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE));
+}
+
+/**
+ * @brief Checks if PLL ready interrupt source is enabled or disabled.
+ * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE));
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_EF_Init De-initialization function
+ * @{
+ */
+ErrorStatus LL_RCC_DeInit(void);
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
+ * @{
+ */
+void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
+uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
+#if defined(UART4) || defined(UART5)
+uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource);
+#endif /* UART4 || UART5 */
+uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
+#if defined(RCC_CFGR_I2SSRC)
+uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
+#endif /* RCC_CFGR_I2SSRC */
+#if defined(USB_OTG_FS) || defined(USB)
+uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
+#endif /* USB_OTG_FS || USB */
+#if (defined(RCC_CFGR_ADCPRE) || defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34))
+uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
+#endif /*RCC_CFGR_ADCPRE || RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */
+#if defined(RCC_CFGR_SDPRE)
+uint32_t LL_RCC_GetSDADCClockFreq(uint32_t SDADCxSource);
+#endif /*RCC_CFGR_SDPRE */
+#if defined(CEC)
+uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource);
+#endif /* CEC */
+#if defined(RCC_CFGR3_TIMSW)
+uint32_t LL_RCC_GetTIMClockFreq(uint32_t TIMxSource);
+#endif /*RCC_CFGR3_TIMSW*/
+uint32_t LL_RCC_GetHRTIMClockFreq(uint32_t HRTIMxSource);
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* RCC */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_LL_RCC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_ll_rtc.h b/Inc/stm32f3xx_ll_rtc.h
new file mode 100644
index 0000000..eaa4435
--- /dev/null
+++ b/Inc/stm32f3xx_ll_rtc.h
@@ -0,0 +1,3752 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_rtc.h
+ * @author MCD Application Team
+ * @brief Header file of RTC LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_LL_RTC_H
+#define __STM32F3xx_LL_RTC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx.h"
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined(RTC)
+
+/** @defgroup RTC_LL RTC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RTC_LL_Private_Constants RTC Private Constants
+ * @{
+ */
+/* Masks Definition */
+#define RTC_INIT_MASK 0xFFFFFFFFU
+#define RTC_RSF_MASK 0xFFFFFF5FU
+
+/* Write protection defines */
+#define RTC_WRITE_PROTECTION_DISABLE ((uint8_t)0xFFU)
+#define RTC_WRITE_PROTECTION_ENABLE_1 ((uint8_t)0xCAU)
+#define RTC_WRITE_PROTECTION_ENABLE_2 ((uint8_t)0x53U)
+
+/* Defines used to combine date & time */
+#define RTC_OFFSET_WEEKDAY 24U
+#define RTC_OFFSET_DAY 16U
+#define RTC_OFFSET_MONTH 8U
+#define RTC_OFFSET_HOUR 16U
+#define RTC_OFFSET_MINUTE 8U
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RTC_LL_Private_Macros RTC Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RTC_LL_ES_INIT RTC Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief RTC Init structures definition
+ */
+typedef struct
+{
+ uint32_t HourFormat; /*!< Specifies the RTC Hours Format.
+ This parameter can be a value of @ref RTC_LL_EC_HOURFORMAT
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RTC_SetHourFormat(). */
+
+ uint32_t AsynchPrescaler; /*!< Specifies the RTC Asynchronous Predivider value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RTC_SetAsynchPrescaler(). */
+
+ uint32_t SynchPrescaler; /*!< Specifies the RTC Synchronous Predivider value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RTC_SetSynchPrescaler(). */
+} LL_RTC_InitTypeDef;
+
+/**
+ * @brief RTC Time structure definition
+ */
+typedef struct
+{
+ uint32_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
+ This parameter can be a value of @ref RTC_LL_EC_TIME_FORMAT
+
+ This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetFormat(). */
+
+ uint8_t Hours; /*!< Specifies the RTC Time Hours.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the @ref LL_RTC_TIME_FORMAT_PM is selected.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the @ref LL_RTC_TIME_FORMAT_AM_OR_24 is selected.
+
+ This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetHour(). */
+
+ uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 59
+
+ This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetMinute(). */
+
+ uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 59
+
+ This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetSecond(). */
+} LL_RTC_TimeTypeDef;
+
+/**
+ * @brief RTC Date structure definition
+ */
+typedef struct
+{
+ uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay.
+ This parameter can be a value of @ref RTC_LL_EC_WEEKDAY
+
+ This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetWeekDay(). */
+
+ uint8_t Month; /*!< Specifies the RTC Date Month.
+ This parameter can be a value of @ref RTC_LL_EC_MONTH
+
+ This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetMonth(). */
+
+ uint8_t Day; /*!< Specifies the RTC Date Day.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 31
+
+ This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetDay(). */
+
+ uint8_t Year; /*!< Specifies the RTC Date Year.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 99
+
+ This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetYear(). */
+} LL_RTC_DateTypeDef;
+
+/**
+ * @brief RTC Alarm structure definition
+ */
+typedef struct
+{
+ LL_RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members. */
+
+ uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks.
+ This parameter can be a value of @ref RTC_LL_EC_ALMA_MASK for ALARM A or @ref RTC_LL_EC_ALMB_MASK for ALARM B.
+
+ This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetMask() for ALARM A
+ or @ref LL_RTC_ALMB_SetMask() for ALARM B
+ */
+
+ uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on day or WeekDay.
+ This parameter can be a value of @ref RTC_LL_EC_ALMA_WEEKDAY_SELECTION for ALARM A or @ref RTC_LL_EC_ALMB_WEEKDAY_SELECTION for ALARM B
+
+ This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_EnableWeekday() or @ref LL_RTC_ALMA_DisableWeekday()
+ for ALARM A or @ref LL_RTC_ALMB_EnableWeekday() or @ref LL_RTC_ALMB_DisableWeekday() for ALARM B
+ */
+
+ uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Day/WeekDay.
+ If AlarmDateWeekDaySel set to day, this parameter must be a number between Min_Data = 1 and Max_Data = 31.
+
+ This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetDay()
+ for ALARM A or @ref LL_RTC_ALMB_SetDay() for ALARM B.
+
+ If AlarmDateWeekDaySel set to Weekday, this parameter can be a value of @ref RTC_LL_EC_WEEKDAY.
+
+ This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetWeekDay()
+ for ALARM A or @ref LL_RTC_ALMB_SetWeekDay() for ALARM B.
+ */
+} LL_RTC_AlarmTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RTC_LL_Exported_Constants RTC Exported Constants
+ * @{
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RTC_LL_EC_FORMAT FORMAT
+ * @{
+ */
+#define LL_RTC_FORMAT_BIN 0x000000000U /*!< Binary data format */
+#define LL_RTC_FORMAT_BCD 0x000000001U /*!< BCD data format */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_ALMA_WEEKDAY_SELECTION RTC Alarm A Date WeekDay
+ * @{
+ */
+#define LL_RTC_ALMA_DATEWEEKDAYSEL_DATE 0x00000000U /*!< Alarm A Date is selected */
+#define LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL /*!< Alarm A WeekDay is selected */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_ALMB_WEEKDAY_SELECTION RTC Alarm B Date WeekDay
+ * @{
+ */
+#define LL_RTC_ALMB_DATEWEEKDAYSEL_DATE 0x00000000U /*!< Alarm B Date is selected */
+#define LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL /*!< Alarm B WeekDay is selected */
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup RTC_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_RTC_ReadReg function
+ * @{
+ */
+#define LL_RTC_ISR_RECALPF RTC_ISR_RECALPF
+#define LL_RTC_ISR_TAMP3F RTC_ISR_TAMP3F
+#define LL_RTC_ISR_TAMP2F RTC_ISR_TAMP2F
+#define LL_RTC_ISR_TAMP1F RTC_ISR_TAMP1F
+#define LL_RTC_ISR_TSOVF RTC_ISR_TSOVF
+#define LL_RTC_ISR_TSF RTC_ISR_TSF
+#define LL_RTC_ISR_WUTF RTC_ISR_WUTF
+#define LL_RTC_ISR_ALRBF RTC_ISR_ALRBF
+#define LL_RTC_ISR_ALRAF RTC_ISR_ALRAF
+#define LL_RTC_ISR_INITF RTC_ISR_INITF
+#define LL_RTC_ISR_RSF RTC_ISR_RSF
+#define LL_RTC_ISR_INITS RTC_ISR_INITS
+#define LL_RTC_ISR_SHPF RTC_ISR_SHPF
+#define LL_RTC_ISR_WUTWF RTC_ISR_WUTWF
+#define LL_RTC_ISR_ALRBWF RTC_ISR_ALRBWF
+#define LL_RTC_ISR_ALRAWF RTC_ISR_ALRAWF
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_RTC_ReadReg and LL_RTC_WriteReg functions
+ * @{
+ */
+#define LL_RTC_CR_TSIE RTC_CR_TSIE
+#define LL_RTC_CR_WUTIE RTC_CR_WUTIE
+#define LL_RTC_CR_ALRBIE RTC_CR_ALRBIE
+#define LL_RTC_CR_ALRAIE RTC_CR_ALRAIE
+#define LL_RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_WEEKDAY WEEK DAY
+ * @{
+ */
+#define LL_RTC_WEEKDAY_MONDAY ((uint8_t)0x01U) /*!< Monday */
+#define LL_RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U) /*!< Tuesday */
+#define LL_RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U) /*!< Wednesday */
+#define LL_RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U) /*!< Thrusday */
+#define LL_RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U) /*!< Friday */
+#define LL_RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U) /*!< Saturday */
+#define LL_RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U) /*!< Sunday */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_MONTH MONTH
+ * @{
+ */
+#define LL_RTC_MONTH_JANUARY ((uint8_t)0x01U) /*!< January */
+#define LL_RTC_MONTH_FEBRUARY ((uint8_t)0x02U) /*!< February */
+#define LL_RTC_MONTH_MARCH ((uint8_t)0x03U) /*!< March */
+#define LL_RTC_MONTH_APRIL ((uint8_t)0x04U) /*!< April */
+#define LL_RTC_MONTH_MAY ((uint8_t)0x05U) /*!< May */
+#define LL_RTC_MONTH_JUNE ((uint8_t)0x06U) /*!< June */
+#define LL_RTC_MONTH_JULY ((uint8_t)0x07U) /*!< July */
+#define LL_RTC_MONTH_AUGUST ((uint8_t)0x08U) /*!< August */
+#define LL_RTC_MONTH_SEPTEMBER ((uint8_t)0x09U) /*!< September */
+#define LL_RTC_MONTH_OCTOBER ((uint8_t)0x10U) /*!< October */
+#define LL_RTC_MONTH_NOVEMBER ((uint8_t)0x11U) /*!< November */
+#define LL_RTC_MONTH_DECEMBER ((uint8_t)0x12U) /*!< December */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_HOURFORMAT HOUR FORMAT
+ * @{
+ */
+#define LL_RTC_HOURFORMAT_24HOUR 0x00000000U /*!< 24 hour/day format */
+#define LL_RTC_HOURFORMAT_AMPM RTC_CR_FMT /*!< AM/PM hour format */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_ALARMOUT ALARM OUTPUT
+ * @{
+ */
+#define LL_RTC_ALARMOUT_DISABLE 0x00000000U /*!< Output disabled */
+#define LL_RTC_ALARMOUT_ALMA RTC_CR_OSEL_0 /*!< Alarm A output enabled */
+#define LL_RTC_ALARMOUT_ALMB RTC_CR_OSEL_1 /*!< Alarm B output enabled */
+#define LL_RTC_ALARMOUT_WAKEUP RTC_CR_OSEL /*!< Wakeup output enabled */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_ALARM_OUTPUTTYPE ALARM OUTPUT TYPE
+ * @{
+ */
+#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN 0x00000000U /*!< RTC_ALARM, when mapped on PC13, is open-drain output */
+#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL RTC_TAFCR_ALARMOUTTYPE /*!< RTC_ALARM, when mapped on PC13, is push-pull output */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_PIN PIN
+ * @{
+ */
+#define LL_RTC_PIN_PC13 RTC_TAFCR_PC13MODE /*!< PC13 is forced to push-pull output if all RTC alternate functions are disabled */
+#define LL_RTC_PIN_PC14 RTC_TAFCR_PC14MODE /*!< PC14 is forced to push-pull output if LSE is disabled */
+#define LL_RTC_PIN_PC15 RTC_TAFCR_PC15MODE /*!< PC15 is forced to push-pull output if LSE is disabled */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_OUTPUTPOLARITY_PIN OUTPUT POLARITY PIN
+ * @{
+ */
+#define LL_RTC_OUTPUTPOLARITY_PIN_HIGH 0x00000000U /*!< Pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL)*/
+#define LL_RTC_OUTPUTPOLARITY_PIN_LOW RTC_CR_POL /*!< Pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL) */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_TIME_FORMAT TIME FORMAT
+ * @{
+ */
+#define LL_RTC_TIME_FORMAT_AM_OR_24 0x00000000U /*!< AM or 24-hour format */
+#define LL_RTC_TIME_FORMAT_PM RTC_TR_PM /*!< PM */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_SHIFT_SECOND SHIFT SECOND
+ * @{
+ */
+#define LL_RTC_SHIFT_SECOND_DELAY 0x00000000U /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */
+#define LL_RTC_SHIFT_SECOND_ADVANCE RTC_SHIFTR_ADD1S /* Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_ALMA_MASK ALARMA MASK
+ * @{
+ */
+#define LL_RTC_ALMA_MASK_NONE 0x00000000U /*!< No masks applied on Alarm A*/
+#define LL_RTC_ALMA_MASK_DATEWEEKDAY RTC_ALRMAR_MSK4 /*!< Date/day do not care in Alarm A comparison */
+#define LL_RTC_ALMA_MASK_HOURS RTC_ALRMAR_MSK3 /*!< Hours do not care in Alarm A comparison */
+#define LL_RTC_ALMA_MASK_MINUTES RTC_ALRMAR_MSK2 /*!< Minutes do not care in Alarm A comparison */
+#define LL_RTC_ALMA_MASK_SECONDS RTC_ALRMAR_MSK1 /*!< Seconds do not care in Alarm A comparison */
+#define LL_RTC_ALMA_MASK_ALL (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1) /*!< Masks all */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_ALMA_TIME_FORMAT ALARMA TIME FORMAT
+ * @{
+ */
+#define LL_RTC_ALMA_TIME_FORMAT_AM 0x00000000U /*!< AM or 24-hour format */
+#define LL_RTC_ALMA_TIME_FORMAT_PM RTC_ALRMAR_PM /*!< PM */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_ALMB_MASK ALARMB MASK
+ * @{
+ */
+#define LL_RTC_ALMB_MASK_NONE 0x00000000U /*!< No masks applied on Alarm B*/
+#define LL_RTC_ALMB_MASK_DATEWEEKDAY RTC_ALRMBR_MSK4 /*!< Date/day do not care in Alarm B comparison */
+#define LL_RTC_ALMB_MASK_HOURS RTC_ALRMBR_MSK3 /*!< Hours do not care in Alarm B comparison */
+#define LL_RTC_ALMB_MASK_MINUTES RTC_ALRMBR_MSK2 /*!< Minutes do not care in Alarm B comparison */
+#define LL_RTC_ALMB_MASK_SECONDS RTC_ALRMBR_MSK1 /*!< Seconds do not care in Alarm B comparison */
+#define LL_RTC_ALMB_MASK_ALL (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1) /*!< Masks all */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_ALMB_TIME_FORMAT ALARMB TIME FORMAT
+ * @{
+ */
+#define LL_RTC_ALMB_TIME_FORMAT_AM 0x00000000U /*!< AM or 24-hour format */
+#define LL_RTC_ALMB_TIME_FORMAT_PM RTC_ALRMBR_PM /*!< PM */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_TIMESTAMP_EDGE TIMESTAMP EDGE
+ * @{
+ */
+#define LL_RTC_TIMESTAMP_EDGE_RISING 0x00000000U /*!< RTC_TS input rising edge generates a time-stamp event */
+#define LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE /*!< RTC_TS input falling edge generates a time-stamp even */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_TS_TIME_FORMAT TIMESTAMP TIME FORMAT
+ * @{
+ */
+#define LL_RTC_TS_TIME_FORMAT_AM 0x00000000U /*!< AM or 24-hour format */
+#define LL_RTC_TS_TIME_FORMAT_PM RTC_TSTR_PM /*!< PM */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_TAMPER TAMPER
+ * @{
+ */
+#if defined(RTC_TAMPER1_SUPPORT)
+#define LL_RTC_TAMPER_1 RTC_TAFCR_TAMP1E /*!< RTC_TAMP1 input detection */
+#endif /* RTC_TAMPER1_SUPPORT */
+#if defined(RTC_TAMPER2_SUPPORT)
+#define LL_RTC_TAMPER_2 RTC_TAFCR_TAMP2E /*!< RTC_TAMP2 input detection */
+#endif /* RTC_TAMPER2_SUPPORT */
+#if defined(RTC_TAMPER3_SUPPORT)
+#define LL_RTC_TAMPER_3 RTC_TAFCR_TAMP3E /*!< RTC_TAMP3 input detection */
+#endif /* RTC_TAMPER3_SUPPORT */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_TAMPER_MASK TAMPER MASK
+ * @{
+ */
+#if defined(RTC_TAMPER1_SUPPORT)
+#define LL_RTC_TAMPER_MASK_TAMPER1 RTC_TAFCR_TAMP1MF /*!< Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased */
+#endif /* RTC_TAMPER1_SUPPORT */
+#if defined(RTC_TAMPER2_SUPPORT)
+#define LL_RTC_TAMPER_MASK_TAMPER2 RTC_TAFCR_TAMP2MF /*!< Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */
+#endif /* RTC_TAMPER2_SUPPORT */
+#if defined(RTC_TAMPER3_SUPPORT)
+#define LL_RTC_TAMPER_MASK_TAMPER3 RTC_TAFCR_TAMP3MF /*!< Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by hardware. The backup registers are not erased */
+#endif /* RTC_TAMPER3_SUPPORT */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_TAMPER_NOERASE TAMPER NO ERASE
+ * @{
+ */
+#if defined(RTC_TAMPER1_SUPPORT)
+#define LL_RTC_TAMPER_NOERASE_TAMPER1 RTC_TAFCR_TAMP1NOERASE /*!< Tamper 1 event does not erase the backup registers. */
+#endif /* RTC_TAMPER1_SUPPORT */
+#if defined(RTC_TAMPER2_SUPPORT)
+#define LL_RTC_TAMPER_NOERASE_TAMPER2 RTC_TAFCR_TAMP2NOERASE /*!< Tamper 2 event does not erase the backup registers. */
+#endif /* RTC_TAMPER2_SUPPORT */
+#if defined(RTC_TAMPER3_SUPPORT)
+#define LL_RTC_TAMPER_NOERASE_TAMPER3 RTC_TAFCR_TAMP3NOERASE /*!< Tamper 3 event does not erase the backup registers. */
+#endif /* RTC_TAMPER3_SUPPORT */
+/**
+ * @}
+ */
+
+#if defined(RTC_TAFCR_TAMPPRCH)
+/** @defgroup RTC_LL_EC_TAMPER_DURATION TAMPER DURATION
+ * @{
+ */
+#define LL_RTC_TAMPER_DURATION_1RTCCLK 0x00000000U /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle */
+#define LL_RTC_TAMPER_DURATION_2RTCCLK RTC_TAFCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */
+#define LL_RTC_TAMPER_DURATION_4RTCCLK RTC_TAFCR_TAMPPRCH_1 /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */
+#define LL_RTC_TAMPER_DURATION_8RTCCLK RTC_TAFCR_TAMPPRCH /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */
+/**
+ * @}
+ */
+#endif /* RTC_TAFCR_TAMPPRCH */
+
+#if defined(RTC_TAFCR_TAMPFLT)
+/** @defgroup RTC_LL_EC_TAMPER_FILTER TAMPER FILTER
+ * @{
+ */
+#define LL_RTC_TAMPER_FILTER_DISABLE 0x00000000U /*!< Tamper filter is disabled */
+#define LL_RTC_TAMPER_FILTER_2SAMPLE RTC_TAFCR_TAMPFLT_0 /*!< Tamper is activated after 2 consecutive samples at the active level */
+#define LL_RTC_TAMPER_FILTER_4SAMPLE RTC_TAFCR_TAMPFLT_1 /*!< Tamper is activated after 4 consecutive samples at the active level */
+#define LL_RTC_TAMPER_FILTER_8SAMPLE RTC_TAFCR_TAMPFLT /*!< Tamper is activated after 8 consecutive samples at the active level. */
+/**
+ * @}
+ */
+#endif /* RTC_TAFCR_TAMPFLT */
+
+#if defined(RTC_TAFCR_TAMPFREQ)
+/** @defgroup RTC_LL_EC_TAMPER_SAMPLFREQDIV TAMPER SAMPLING FREQUENCY DIVIDER
+ * @{
+ */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_32768 0x00000000U /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768 */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_16384 RTC_TAFCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384 */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_8192 RTC_TAFCR_TAMPFREQ_1 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192 */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_4096 (RTC_TAFCR_TAMPFREQ_1 | RTC_TAFCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096 */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_2048 RTC_TAFCR_TAMPFREQ_2 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048 */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_1024 (RTC_TAFCR_TAMPFREQ_2 | RTC_TAFCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024 */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_512 (RTC_TAFCR_TAMPFREQ_2 | RTC_TAFCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 512 */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_256 RTC_TAFCR_TAMPFREQ /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 256 */
+/**
+ * @}
+ */
+#endif /* RTC_TAFCR_TAMPFREQ */
+
+/** @defgroup RTC_LL_EC_TAMPER_ACTIVELEVEL TAMPER ACTIVE LEVEL
+ * @{
+ */
+#if defined(RTC_TAMPER1_SUPPORT)
+#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 RTC_TAFCR_TAMP1TRG /*!< RTC_TAMP1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/
+#endif /* RTC_TAMPER1_SUPPORT */
+#if defined(RTC_TAMPER2_SUPPORT)
+#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 RTC_TAFCR_TAMP2TRG /*!< RTC_TAMP2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/
+#endif /* RTC_TAMPER2_SUPPORT */
+#if defined(RTC_TAMPER3_SUPPORT)
+#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 RTC_TAFCR_TAMP3TRG /*!< RTC_TAMP3 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/
+#endif /* RTC_TAMPER3_SUPPORT */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_WAKEUPCLOCK_DIV WAKEUP CLOCK DIV
+ * @{
+ */
+#define LL_RTC_WAKEUPCLOCK_DIV_16 0x00000000U /*!< RTC/16 clock is selected */
+#define LL_RTC_WAKEUPCLOCK_DIV_8 (RTC_CR_WUCKSEL_0) /*!< RTC/8 clock is selected */
+#define LL_RTC_WAKEUPCLOCK_DIV_4 (RTC_CR_WUCKSEL_1) /*!< RTC/4 clock is selected */
+#define LL_RTC_WAKEUPCLOCK_DIV_2 (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0) /*!< RTC/2 clock is selected */
+#define LL_RTC_WAKEUPCLOCK_CKSPRE (RTC_CR_WUCKSEL_2) /*!< ck_spre (usually 1 Hz) clock is selected */
+#define LL_RTC_WAKEUPCLOCK_CKSPRE_WUT (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1) /*!< ck_spre (usually 1 Hz) clock is selected and 2exp16 is added to the WUT counter value*/
+/**
+ * @}
+ */
+
+#if defined(RTC_BACKUP_SUPPORT)
+/** @defgroup RTC_LL_EC_BKP BACKUP
+ * @{
+ */
+#define LL_RTC_BKP_DR0 0x00000000U
+#define LL_RTC_BKP_DR1 0x00000001U
+#define LL_RTC_BKP_DR2 0x00000002U
+#define LL_RTC_BKP_DR3 0x00000003U
+#define LL_RTC_BKP_DR4 0x00000004U
+#if RTC_BKP_NUMBER > 5
+#define LL_RTC_BKP_DR5 0x00000005U
+#define LL_RTC_BKP_DR6 0x00000006U
+#define LL_RTC_BKP_DR7 0x00000007U
+#define LL_RTC_BKP_DR8 0x00000008U
+#define LL_RTC_BKP_DR9 0x00000009U
+#define LL_RTC_BKP_DR10 0x0000000AU
+#define LL_RTC_BKP_DR11 0x0000000BU
+#define LL_RTC_BKP_DR12 0x0000000CU
+#define LL_RTC_BKP_DR13 0x0000000DU
+#define LL_RTC_BKP_DR14 0x0000000EU
+#define LL_RTC_BKP_DR15 0x0000000FU
+#endif /* RTC_BKP_NUMBER > 5 */
+
+#if RTC_BKP_NUMBER > 16
+#define LL_RTC_BKP_DR16 0x00000010U
+#define LL_RTC_BKP_DR17 0x00000011U
+#define LL_RTC_BKP_DR18 0x00000012U
+#define LL_RTC_BKP_DR19 0x00000013U
+#endif /* RTC_BKP_NUMBER > 16 */
+
+#if RTC_BKP_NUMBER > 20
+#define LL_RTC_BKP_DR20 0x00000014U
+#define LL_RTC_BKP_DR21 0x00000015U
+#define LL_RTC_BKP_DR22 0x00000016U
+#define LL_RTC_BKP_DR23 0x00000017U
+#define LL_RTC_BKP_DR24 0x00000018U
+#define LL_RTC_BKP_DR25 0x00000019U
+#define LL_RTC_BKP_DR26 0x0000001AU
+#define LL_RTC_BKP_DR27 0x0000001BU
+#define LL_RTC_BKP_DR28 0x0000001CU
+#define LL_RTC_BKP_DR29 0x0000001DU
+#define LL_RTC_BKP_DR30 0x0000001EU
+#define LL_RTC_BKP_DR31 0x0000001FU
+#endif /* RTC_BKP_NUMBER > 20 */
+/**
+ * @}
+ */
+#endif /* RTC_BACKUP_SUPPORT */
+
+/** @defgroup RTC_LL_EC_CALIB_OUTPUT Calibration output
+ * @{
+ */
+#define LL_RTC_CALIB_OUTPUT_NONE 0x00000000U /*!< Calibration output disabled */
+#define LL_RTC_CALIB_OUTPUT_1HZ (RTC_CR_COE | RTC_CR_COSEL) /*!< Calibration output is 1 Hz */
+#define LL_RTC_CALIB_OUTPUT_512HZ (RTC_CR_COE) /*!< Calibration output is 512 Hz */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_CALIB_INSERTPULSE Calibration pulse insertion
+ * @{
+ */
+#define LL_RTC_CALIB_INSERTPULSE_NONE 0x00000000U /*!< No RTCCLK pulses are added */
+#define LL_RTC_CALIB_INSERTPULSE_SET RTC_CALR_CALP /*!< One RTCCLK pulse is effectively inserted every 2exp11 pulses (frequency increased by 488.5 ppm) */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_CALIB_PERIOD Calibration period
+ * @{
+ */
+#define LL_RTC_CALIB_PERIOD_32SEC 0x00000000U /*!< Use a 32-second calibration cycle period */
+#define LL_RTC_CALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< Use a 16-second calibration cycle period */
+#define LL_RTC_CALIB_PERIOD_8SEC RTC_CALR_CALW8 /*!< Use a 8-second calibration cycle period */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RTC_LL_Exported_Macros RTC Exported Macros
+ * @{
+ */
+
+/** @defgroup RTC_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in RTC register
+ * @param __INSTANCE__ RTC Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_RTC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in RTC register
+ * @param __INSTANCE__ RTC Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_RTC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EM_Convert Convert helper Macros
+ * @{
+ */
+
+/**
+ * @brief Helper macro to convert a value from 2 digit decimal format to BCD format
+ * @param __VALUE__ Byte to be converted
+ * @retval Converted byte
+ */
+#define __LL_RTC_CONVERT_BIN2BCD(__VALUE__) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U))
+
+/**
+ * @brief Helper macro to convert a value from BCD format to 2 digit decimal format
+ * @param __VALUE__ BCD value to be converted
+ * @retval Converted byte
+ */
+#define __LL_RTC_CONVERT_BCD2BIN(__VALUE__) (uint8_t)(((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U + ((__VALUE__) & (uint8_t)0x0FU))
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EM_Date Date helper Macros
+ * @{
+ */
+
+/**
+ * @brief Helper macro to retrieve weekday.
+ * @param __RTC_DATE__ Date returned by @ref LL_RTC_DATE_Get function.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_WEEKDAY_MONDAY
+ * @arg @ref LL_RTC_WEEKDAY_TUESDAY
+ * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+ * @arg @ref LL_RTC_WEEKDAY_THURSDAY
+ * @arg @ref LL_RTC_WEEKDAY_FRIDAY
+ * @arg @ref LL_RTC_WEEKDAY_SATURDAY
+ * @arg @ref LL_RTC_WEEKDAY_SUNDAY
+ */
+#define __LL_RTC_GET_WEEKDAY(__RTC_DATE__) (((__RTC_DATE__) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU)
+
+/**
+ * @brief Helper macro to retrieve Year in BCD format
+ * @param __RTC_DATE__ Value returned by @ref LL_RTC_DATE_Get
+ * @retval Year in BCD format (0x00 . . . 0x99)
+ */
+#define __LL_RTC_GET_YEAR(__RTC_DATE__) ((__RTC_DATE__) & 0x000000FFU)
+
+/**
+ * @brief Helper macro to retrieve Month in BCD format
+ * @param __RTC_DATE__ Value returned by @ref LL_RTC_DATE_Get
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_MONTH_JANUARY
+ * @arg @ref LL_RTC_MONTH_FEBRUARY
+ * @arg @ref LL_RTC_MONTH_MARCH
+ * @arg @ref LL_RTC_MONTH_APRIL
+ * @arg @ref LL_RTC_MONTH_MAY
+ * @arg @ref LL_RTC_MONTH_JUNE
+ * @arg @ref LL_RTC_MONTH_JULY
+ * @arg @ref LL_RTC_MONTH_AUGUST
+ * @arg @ref LL_RTC_MONTH_SEPTEMBER
+ * @arg @ref LL_RTC_MONTH_OCTOBER
+ * @arg @ref LL_RTC_MONTH_NOVEMBER
+ * @arg @ref LL_RTC_MONTH_DECEMBER
+ */
+#define __LL_RTC_GET_MONTH(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_MONTH) & 0x000000FFU)
+
+/**
+ * @brief Helper macro to retrieve Day in BCD format
+ * @param __RTC_DATE__ Value returned by @ref LL_RTC_DATE_Get
+ * @retval Day in BCD format (0x01 . . . 0x31)
+ */
+#define __LL_RTC_GET_DAY(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_DAY) & 0x000000FFU)
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EM_Time Time helper Macros
+ * @{
+ */
+
+/**
+ * @brief Helper macro to retrieve hour in BCD format
+ * @param __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
+ * @retval Hours in BCD format (0x01. . .0x12 or between Min_Data=0x00 and Max_Data=0x23)
+ */
+#define __LL_RTC_GET_HOUR(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_HOUR) & 0x000000FFU)
+
+/**
+ * @brief Helper macro to retrieve minute in BCD format
+ * @param __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
+ * @retval Minutes in BCD format (0x00. . .0x59)
+ */
+#define __LL_RTC_GET_MINUTE(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_MINUTE) & 0x000000FFU)
+
+/**
+ * @brief Helper macro to retrieve second in BCD format
+ * @param __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
+ * @retval Seconds in format (0x00. . .0x59)
+ */
+#define __LL_RTC_GET_SECOND(__RTC_TIME__) ((__RTC_TIME__) & 0x000000FFU)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RTC_LL_Exported_Functions RTC Exported Functions
+ * @{
+ */
+
+/** @defgroup RTC_LL_EF_Configuration Configuration
+ * @{
+ */
+
+/**
+ * @brief Set Hours format (24 hour/day or AM/PM hour format)
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+ * @rmtoll CR FMT LL_RTC_SetHourFormat
+ * @param RTCx RTC Instance
+ * @param HourFormat This parameter can be one of the following values:
+ * @arg @ref LL_RTC_HOURFORMAT_24HOUR
+ * @arg @ref LL_RTC_HOURFORMAT_AMPM
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_SetHourFormat(RTC_TypeDef *RTCx, uint32_t HourFormat)
+{
+ MODIFY_REG(RTCx->CR, RTC_CR_FMT, HourFormat);
+}
+
+/**
+ * @brief Get Hours format (24 hour/day or AM/PM hour format)
+ * @rmtoll CR FMT LL_RTC_GetHourFormat
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_HOURFORMAT_24HOUR
+ * @arg @ref LL_RTC_HOURFORMAT_AMPM
+ */
+__STATIC_INLINE uint32_t LL_RTC_GetHourFormat(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_FMT));
+}
+
+/**
+ * @brief Select the flag to be routed to RTC_ALARM output
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR OSEL LL_RTC_SetAlarmOutEvent
+ * @param RTCx RTC Instance
+ * @param AlarmOutput This parameter can be one of the following values:
+ * @arg @ref LL_RTC_ALARMOUT_DISABLE
+ * @arg @ref LL_RTC_ALARMOUT_ALMA
+ * @arg @ref LL_RTC_ALARMOUT_ALMB
+ * @arg @ref LL_RTC_ALARMOUT_WAKEUP
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_SetAlarmOutEvent(RTC_TypeDef *RTCx, uint32_t AlarmOutput)
+{
+ MODIFY_REG(RTCx->CR, RTC_CR_OSEL, AlarmOutput);
+}
+
+/**
+ * @brief Get the flag to be routed to RTC_ALARM output
+ * @rmtoll CR OSEL LL_RTC_GetAlarmOutEvent
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_ALARMOUT_DISABLE
+ * @arg @ref LL_RTC_ALARMOUT_ALMA
+ * @arg @ref LL_RTC_ALARMOUT_ALMB
+ * @arg @ref LL_RTC_ALARMOUT_WAKEUP
+ */
+__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_OSEL));
+}
+
+/**
+ * @brief Set RTC_ALARM output type (ALARM in push-pull or open-drain output)
+ * @note Used only when RTC_ALARM is mapped on PC13
+ * @note If all RTC alternate functions are disabled and PC13MODE = 1, PC13VALUE configures the
+ * PC13 output data
+ * @rmtoll TAFCR ALARMOUTTYPE LL_RTC_SetAlarmOutputType
+ * @param RTCx RTC Instance
+ * @param Output This parameter can be one of the following values:
+ * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
+ * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_SetAlarmOutputType(RTC_TypeDef *RTCx, uint32_t Output)
+{
+ MODIFY_REG(RTCx->TAFCR, RTC_TAFCR_ALARMOUTTYPE, Output);
+}
+
+/**
+ * @brief Get RTC_ALARM output type (ALARM in push-pull or open-drain output)
+ * @note used only when RTC_ALARM is mapped on PC13
+ * @note If all RTC alternate functions are disabled and PC13MODE = 1, PC13VALUE configures the
+ * PC13 output data
+ * @rmtoll TAFCR ALARMOUTTYPE LL_RTC_GetAlarmOutputType
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
+ * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL
+ */
+__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_ALARMOUTTYPE));
+}
+
+/**
+ * @brief Enable push-pull output on PC13, PC14 and/or PC15
+ * @note PC13 forced to push-pull output if all RTC alternate functions are disabled
+ * @note PC14 and PC15 forced to push-pull output if LSE is disabled
+ * @rmtoll TAFCR PC13MODE LL_RTC_EnablePushPullMode\n
+ * @rmtoll TAFCR PC14MODE LL_RTC_EnablePushPullMode\n
+ * @rmtoll TAFCR PC15MODE LL_RTC_EnablePushPullMode
+ * @param RTCx RTC Instance
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_RTC_PIN_PC13
+ * @arg @ref LL_RTC_PIN_PC14
+ * @arg @ref LL_RTC_PIN_PC15
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnablePushPullMode(RTC_TypeDef *RTCx, uint32_t PinMask)
+{
+ SET_BIT(RTCx->TAFCR, PinMask);
+}
+
+/**
+ * @brief Disable push-pull output on PC13, PC14 and/or PC15
+ * @note PC13, PC14 and/or PC15 are controlled by the GPIO configuration registers.
+ * Consequently PC13, PC14 and/or PC15 are floating in Standby mode.
+ * @rmtoll TAFCR PC13MODE LL_RTC_DisablePushPullMode\n
+ * TAFCR PC14MODE LL_RTC_DisablePushPullMode\n
+ * TAFCR PC15MODE LL_RTC_DisablePushPullMode
+ * @param RTCx RTC Instance
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_RTC_PIN_PC13
+ * @arg @ref LL_RTC_PIN_PC14
+ * @arg @ref LL_RTC_PIN_PC15
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisablePushPullMode(RTC_TypeDef* RTCx, uint32_t PinMask)
+{
+ CLEAR_BIT(RTCx->TAFCR, PinMask);
+}
+
+/**
+ * @brief Set PC14 and/or PC15 to high level.
+ * @note Output data configuration is possible if the LSE is disabled and PushPull output is enabled (through @ref LL_RTC_EnablePushPullMode)
+ * @rmtoll TAFCR PC14VALUE LL_RTC_SetOutputPin\n
+ * TAFCR PC15VALUE LL_RTC_SetOutputPin
+ * @param RTCx RTC Instance
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_RTC_PIN_PC14
+ * @arg @ref LL_RTC_PIN_PC15
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_SetOutputPin(RTC_TypeDef* RTCx, uint32_t PinMask)
+{
+ SET_BIT(RTCx->TAFCR, (PinMask >> 1));
+}
+
+/**
+ * @brief Set PC14 and/or PC15 to low level.
+ * @note Output data configuration is possible if the LSE is disabled and PushPull output is enabled (through @ref LL_RTC_EnablePushPullMode)
+ * @rmtoll TAFCR PC14VALUE LL_RTC_ResetOutputPin\n
+ * TAFCR PC15VALUE LL_RTC_ResetOutputPin
+ * @param RTCx RTC Instance
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_RTC_PIN_PC14
+ * @arg @ref LL_RTC_PIN_PC15
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ResetOutputPin(RTC_TypeDef* RTCx, uint32_t PinMask)
+{
+ CLEAR_BIT(RTCx->TAFCR, (PinMask >> 1));
+}
+
+/**
+ * @brief Enable initialization mode
+ * @note Initialization mode is used to program time and date register (RTC_TR and RTC_DR)
+ * and prescaler register (RTC_PRER).
+ * Counters are stopped and start counting from the new value when INIT is reset.
+ * @rmtoll ISR INIT LL_RTC_EnableInitMode
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableInitMode(RTC_TypeDef *RTCx)
+{
+ /* Set the Initialization mode */
+ WRITE_REG(RTCx->ISR, RTC_INIT_MASK);
+}
+
+/**
+ * @brief Disable initialization mode (Free running mode)
+ * @rmtoll ISR INIT LL_RTC_DisableInitMode
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableInitMode(RTC_TypeDef *RTCx)
+{
+ /* Exit Initialization mode */
+ WRITE_REG(RTCx->ISR, (uint32_t)~RTC_ISR_INIT);
+}
+
+/**
+ * @brief Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted)
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR POL LL_RTC_SetOutputPolarity
+ * @param RTCx RTC Instance
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH
+ * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_SetOutputPolarity(RTC_TypeDef *RTCx, uint32_t Polarity)
+{
+ MODIFY_REG(RTCx->CR, RTC_CR_POL, Polarity);
+}
+
+/**
+ * @brief Get Output polarity
+ * @rmtoll CR POL LL_RTC_GetOutputPolarity
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH
+ * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW
+ */
+__STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_POL));
+}
+
+/**
+ * @brief Enable Bypass the shadow registers
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR BYPSHAD LL_RTC_EnableShadowRegBypass
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableShadowRegBypass(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_BYPSHAD);
+}
+
+/**
+ * @brief Disable Bypass the shadow registers
+ * @rmtoll CR BYPSHAD LL_RTC_DisableShadowRegBypass
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableShadowRegBypass(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_BYPSHAD);
+}
+
+/**
+ * @brief Check if Shadow registers bypass is enabled or not.
+ * @rmtoll CR BYPSHAD LL_RTC_IsShadowRegBypassEnabled
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->CR, RTC_CR_BYPSHAD) == (RTC_CR_BYPSHAD));
+}
+
+/**
+ * @brief Enable RTC_REFIN reference clock detection (50 or 60 Hz)
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+ * @rmtoll CR REFCKON LL_RTC_EnableRefClock
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableRefClock(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_REFCKON);
+}
+
+/**
+ * @brief Disable RTC_REFIN reference clock detection (50 or 60 Hz)
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+ * @rmtoll CR REFCKON LL_RTC_DisableRefClock
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableRefClock(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_REFCKON);
+}
+
+/**
+ * @brief Set Asynchronous prescaler factor
+ * @rmtoll PRER PREDIV_A LL_RTC_SetAsynchPrescaler
+ * @param RTCx RTC Instance
+ * @param AsynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7F
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_SetAsynchPrescaler(RTC_TypeDef *RTCx, uint32_t AsynchPrescaler)
+{
+ MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_A, AsynchPrescaler << RTC_PRER_PREDIV_A_Pos);
+}
+
+/**
+ * @brief Set Synchronous prescaler factor
+ * @rmtoll PRER PREDIV_S LL_RTC_SetSynchPrescaler
+ * @param RTCx RTC Instance
+ * @param SynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7FFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_SetSynchPrescaler(RTC_TypeDef *RTCx, uint32_t SynchPrescaler)
+{
+ MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_S, SynchPrescaler);
+}
+
+/**
+ * @brief Get Asynchronous prescaler factor
+ * @rmtoll PRER PREDIV_A LL_RTC_GetAsynchPrescaler
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data = 0 and Max_Data = 0x7F
+ */
+__STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_A) >> RTC_PRER_PREDIV_A_Pos);
+}
+
+/**
+ * @brief Get Synchronous prescaler factor
+ * @rmtoll PRER PREDIV_S LL_RTC_GetSynchPrescaler
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data = 0 and Max_Data = 0x7FFF
+ */
+__STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_S));
+}
+
+/**
+ * @brief Enable the write protection for RTC registers.
+ * @rmtoll WPR KEY LL_RTC_EnableWriteProtection
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableWriteProtection(RTC_TypeDef *RTCx)
+{
+ WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_DISABLE);
+}
+
+/**
+ * @brief Disable the write protection for RTC registers.
+ * @rmtoll WPR KEY LL_RTC_DisableWriteProtection
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableWriteProtection(RTC_TypeDef *RTCx)
+{
+ WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_1);
+ WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_2);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EF_Time Time
+ * @{
+ */
+
+/**
+ * @brief Set time format (AM/24-hour or PM notation)
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+ * @rmtoll TR PM LL_RTC_TIME_SetFormat
+ * @param RTCx RTC Instance
+ * @param TimeFormat This parameter can be one of the following values:
+ * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
+ * @arg @ref LL_RTC_TIME_FORMAT_PM
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
+{
+ MODIFY_REG(RTCx->TR, RTC_TR_PM, TimeFormat);
+}
+
+/**
+ * @brief Get time format (AM or PM notation)
+ * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * before reading this bit
+ * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
+ * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
+ * @rmtoll TR PM LL_RTC_TIME_GetFormat
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
+ * @arg @ref LL_RTC_TIME_FORMAT_PM
+ */
+__STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TR, RTC_TR_PM));
+}
+
+/**
+ * @brief Set Hours in BCD format
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert hour from binary to BCD format
+ * @rmtoll TR HT LL_RTC_TIME_SetHour\n
+ * TR HU LL_RTC_TIME_SetHour
+ * @param RTCx RTC Instance
+ * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
+{
+ MODIFY_REG(RTCx->TR, (RTC_TR_HT | RTC_TR_HU),
+ (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)));
+}
+
+/**
+ * @brief Get Hours in BCD format
+ * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * before reading this bit
+ * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
+ * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert hour from BCD to
+ * Binary format
+ * @rmtoll TR HT LL_RTC_TIME_GetHour\n
+ * TR HU LL_RTC_TIME_GetHour
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+ */
+__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)((READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU))) >> RTC_TR_HU_Pos);
+}
+
+/**
+ * @brief Set Minutes in BCD format
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
+ * @rmtoll TR MNT LL_RTC_TIME_SetMinute\n
+ * TR MNU LL_RTC_TIME_SetMinute
+ * @param RTCx RTC Instance
+ * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
+{
+ MODIFY_REG(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU),
+ (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)));
+}
+
+/**
+ * @brief Get Minutes in BCD format
+ * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * before reading this bit
+ * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
+ * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert minute from BCD
+ * to Binary format
+ * @rmtoll TR MNT LL_RTC_TIME_GetMinute\n
+ * TR MNU LL_RTC_TIME_GetMinute
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x59
+ */
+__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU))>> RTC_TR_MNU_Pos);
+}
+
+/**
+ * @brief Set Seconds in BCD format
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
+ * @rmtoll TR ST LL_RTC_TIME_SetSecond\n
+ * TR SU LL_RTC_TIME_SetSecond
+ * @param RTCx RTC Instance
+ * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
+{
+ MODIFY_REG(RTCx->TR, (RTC_TR_ST | RTC_TR_SU),
+ (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos)));
+}
+
+/**
+ * @brief Get Seconds in BCD format
+ * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * before reading this bit
+ * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
+ * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD
+ * to Binary format
+ * @rmtoll TR ST LL_RTC_TIME_GetSecond\n
+ * TR SU LL_RTC_TIME_GetSecond
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x59
+ */
+__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU)) >> RTC_TR_SU_Pos);
+}
+
+/**
+ * @brief Set time (hour, minute and second) in BCD format
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+ * @note TimeFormat and Hours should follow the same format
+ * @rmtoll TR PM LL_RTC_TIME_Config\n
+ * TR HT LL_RTC_TIME_Config\n
+ * TR HU LL_RTC_TIME_Config\n
+ * TR MNT LL_RTC_TIME_Config\n
+ * TR MNU LL_RTC_TIME_Config\n
+ * TR ST LL_RTC_TIME_Config\n
+ * TR SU LL_RTC_TIME_Config
+ * @param RTCx RTC Instance
+ * @param Format12_24 This parameter can be one of the following values:
+ * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
+ * @arg @ref LL_RTC_TIME_FORMAT_PM
+ * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+ * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59
+ * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
+{
+ register uint32_t temp = 0U;
+
+ temp = Format12_24 | \
+ (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)) | \
+ (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)) | \
+ (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos));
+ MODIFY_REG(RTCx->TR, (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU), temp);
+}
+
+/**
+ * @brief Get time (hour, minute and second) in BCD format
+ * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * before reading this bit
+ * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
+ * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
+ * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
+ * are available to get independently each parameter.
+ * @rmtoll TR HT LL_RTC_TIME_Get\n
+ * TR HU LL_RTC_TIME_Get\n
+ * TR MNT LL_RTC_TIME_Get\n
+ * TR MNU LL_RTC_TIME_Get\n
+ * TR ST LL_RTC_TIME_Get\n
+ * TR SU LL_RTC_TIME_Get
+ * @param RTCx RTC Instance
+ * @retval Combination of hours, minutes and seconds (Format: 0x00HHMMSS).
+ */
+__STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx)
+{
+ register uint32_t temp = 0U;
+
+ temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU));
+ return (uint32_t)((((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)) << RTC_OFFSET_HOUR) | \
+ (((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos)) << RTC_OFFSET_MINUTE) | \
+ ((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos)));
+}
+
+/**
+ * @brief Memorize whether the daylight saving time change has been performed
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR BKP LL_RTC_TIME_EnableDayLightStore
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TIME_EnableDayLightStore(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_BKP);
+}
+
+/**
+ * @brief Disable memorization whether the daylight saving time change has been performed.
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR BKP LL_RTC_TIME_DisableDayLightStore
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_BKP);
+}
+
+/**
+ * @brief Check if RTC Day Light Saving stored operation has been enabled or not
+ * @rmtoll CR BKP LL_RTC_TIME_IsDayLightStoreEnabled
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->CR, RTC_CR_BKP) == (RTC_CR_BKP));
+}
+
+/**
+ * @brief Subtract 1 hour (winter time change)
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR SUB1H LL_RTC_TIME_DecHour
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TIME_DecHour(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_SUB1H);
+}
+
+/**
+ * @brief Add 1 hour (summer time change)
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR ADD1H LL_RTC_TIME_IncHour
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TIME_IncHour(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_ADD1H);
+}
+
+/**
+ * @brief Get Sub second value in the synchronous prescaler counter.
+ * @note You can use both SubSeconds value and SecondFraction (PREDIV_S through
+ * LL_RTC_GetSynchPrescaler function) terms returned to convert Calendar
+ * SubSeconds value in second fraction ratio with time unit following
+ * generic formula:
+ * ==> Seconds fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
+ * This conversion can be performed only if no shift operation is pending
+ * (ie. SHFP=0) when PREDIV_S >= SS.
+ * @rmtoll SSR SS LL_RTC_TIME_GetSubSecond
+ * @param RTCx RTC Instance
+ * @retval Sub second value (number between 0 and 65535)
+ */
+__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->SSR, RTC_SSR_SS));
+}
+
+/**
+ * @brief Synchronize to a remote clock with a high degree of precision.
+ * @note This operation effectively subtracts from (delays) or advance the clock of a fraction of a second.
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note When REFCKON is set, firmware must not write to Shift control register.
+ * @rmtoll SHIFTR ADD1S LL_RTC_TIME_Synchronize\n
+ * SHIFTR SUBFS LL_RTC_TIME_Synchronize
+ * @param RTCx RTC Instance
+ * @param ShiftSecond This parameter can be one of the following values:
+ * @arg @ref LL_RTC_SHIFT_SECOND_DELAY
+ * @arg @ref LL_RTC_SHIFT_SECOND_ADVANCE
+ * @param Fraction Number of Seconds Fractions (any value from 0 to 0x7FFF)
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TIME_Synchronize(RTC_TypeDef *RTCx, uint32_t ShiftSecond, uint32_t Fraction)
+{
+ WRITE_REG(RTCx->SHIFTR, ShiftSecond | Fraction);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EF_Date Date
+ * @{
+ */
+
+/**
+ * @brief Set Year in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Year from binary to BCD format
+ * @rmtoll DR YT LL_RTC_DATE_SetYear\n
+ * DR YU LL_RTC_DATE_SetYear
+ * @param RTCx RTC Instance
+ * @param Year Value between Min_Data=0x00 and Max_Data=0x99
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year)
+{
+ MODIFY_REG(RTCx->DR, (RTC_DR_YT | RTC_DR_YU),
+ (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)));
+}
+
+/**
+ * @brief Get Year in BCD format
+ * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * before reading this bit
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format
+ * @rmtoll DR YT LL_RTC_DATE_GetYear\n
+ * DR YU LL_RTC_DATE_GetYear
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x99
+ */
+__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU))) >> RTC_DR_YU_Pos);
+}
+
+/**
+ * @brief Set Week day
+ * @rmtoll DR WDU LL_RTC_DATE_SetWeekDay
+ * @param RTCx RTC Instance
+ * @param WeekDay This parameter can be one of the following values:
+ * @arg @ref LL_RTC_WEEKDAY_MONDAY
+ * @arg @ref LL_RTC_WEEKDAY_TUESDAY
+ * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+ * @arg @ref LL_RTC_WEEKDAY_THURSDAY
+ * @arg @ref LL_RTC_WEEKDAY_FRIDAY
+ * @arg @ref LL_RTC_WEEKDAY_SATURDAY
+ * @arg @ref LL_RTC_WEEKDAY_SUNDAY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
+{
+ MODIFY_REG(RTCx->DR, RTC_DR_WDU, WeekDay << RTC_DR_WDU_Pos);
+}
+
+/**
+ * @brief Get Week day
+ * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * before reading this bit
+ * @rmtoll DR WDU LL_RTC_DATE_GetWeekDay
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_WEEKDAY_MONDAY
+ * @arg @ref LL_RTC_WEEKDAY_TUESDAY
+ * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+ * @arg @ref LL_RTC_WEEKDAY_THURSDAY
+ * @arg @ref LL_RTC_WEEKDAY_FRIDAY
+ * @arg @ref LL_RTC_WEEKDAY_SATURDAY
+ * @arg @ref LL_RTC_WEEKDAY_SUNDAY
+ */
+__STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->DR, RTC_DR_WDU) >> RTC_DR_WDU_Pos);
+}
+
+/**
+ * @brief Set Month in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Month from binary to BCD format
+ * @rmtoll DR MT LL_RTC_DATE_SetMonth\n
+ * DR MU LL_RTC_DATE_SetMonth
+ * @param RTCx RTC Instance
+ * @param Month This parameter can be one of the following values:
+ * @arg @ref LL_RTC_MONTH_JANUARY
+ * @arg @ref LL_RTC_MONTH_FEBRUARY
+ * @arg @ref LL_RTC_MONTH_MARCH
+ * @arg @ref LL_RTC_MONTH_APRIL
+ * @arg @ref LL_RTC_MONTH_MAY
+ * @arg @ref LL_RTC_MONTH_JUNE
+ * @arg @ref LL_RTC_MONTH_JULY
+ * @arg @ref LL_RTC_MONTH_AUGUST
+ * @arg @ref LL_RTC_MONTH_SEPTEMBER
+ * @arg @ref LL_RTC_MONTH_OCTOBER
+ * @arg @ref LL_RTC_MONTH_NOVEMBER
+ * @arg @ref LL_RTC_MONTH_DECEMBER
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month)
+{
+ MODIFY_REG(RTCx->DR, (RTC_DR_MT | RTC_DR_MU),
+ (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)));
+}
+
+/**
+ * @brief Get Month in BCD format
+ * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * before reading this bit
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
+ * @rmtoll DR MT LL_RTC_DATE_GetMonth\n
+ * DR MU LL_RTC_DATE_GetMonth
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_MONTH_JANUARY
+ * @arg @ref LL_RTC_MONTH_FEBRUARY
+ * @arg @ref LL_RTC_MONTH_MARCH
+ * @arg @ref LL_RTC_MONTH_APRIL
+ * @arg @ref LL_RTC_MONTH_MAY
+ * @arg @ref LL_RTC_MONTH_JUNE
+ * @arg @ref LL_RTC_MONTH_JULY
+ * @arg @ref LL_RTC_MONTH_AUGUST
+ * @arg @ref LL_RTC_MONTH_SEPTEMBER
+ * @arg @ref LL_RTC_MONTH_OCTOBER
+ * @arg @ref LL_RTC_MONTH_NOVEMBER
+ * @arg @ref LL_RTC_MONTH_DECEMBER
+ */
+__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU)))>> RTC_DR_MU_Pos);
+}
+
+/**
+ * @brief Set Day in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
+ * @rmtoll DR DT LL_RTC_DATE_SetDay\n
+ * DR DU LL_RTC_DATE_SetDay
+ * @param RTCx RTC Instance
+ * @param Day Value between Min_Data=0x01 and Max_Data=0x31
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
+{
+ MODIFY_REG(RTCx->DR, (RTC_DR_DT | RTC_DR_DU),
+ (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos)));
+}
+
+/**
+ * @brief Get Day in BCD format
+ * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * before reading this bit
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
+ * @rmtoll DR DT LL_RTC_DATE_GetDay\n
+ * DR DU LL_RTC_DATE_GetDay
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x01 and Max_Data=0x31
+ */
+__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU))) >> RTC_DR_DU_Pos);
+}
+
+/**
+ * @brief Set date (WeekDay, Day, Month and Year) in BCD format
+ * @rmtoll DR WDU LL_RTC_DATE_Config\n
+ * DR MT LL_RTC_DATE_Config\n
+ * DR MU LL_RTC_DATE_Config\n
+ * DR DT LL_RTC_DATE_Config\n
+ * DR DU LL_RTC_DATE_Config\n
+ * DR YT LL_RTC_DATE_Config\n
+ * DR YU LL_RTC_DATE_Config
+ * @param RTCx RTC Instance
+ * @param WeekDay This parameter can be one of the following values:
+ * @arg @ref LL_RTC_WEEKDAY_MONDAY
+ * @arg @ref LL_RTC_WEEKDAY_TUESDAY
+ * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+ * @arg @ref LL_RTC_WEEKDAY_THURSDAY
+ * @arg @ref LL_RTC_WEEKDAY_FRIDAY
+ * @arg @ref LL_RTC_WEEKDAY_SATURDAY
+ * @arg @ref LL_RTC_WEEKDAY_SUNDAY
+ * @param Day Value between Min_Data=0x01 and Max_Data=0x31
+ * @param Month This parameter can be one of the following values:
+ * @arg @ref LL_RTC_MONTH_JANUARY
+ * @arg @ref LL_RTC_MONTH_FEBRUARY
+ * @arg @ref LL_RTC_MONTH_MARCH
+ * @arg @ref LL_RTC_MONTH_APRIL
+ * @arg @ref LL_RTC_MONTH_MAY
+ * @arg @ref LL_RTC_MONTH_JUNE
+ * @arg @ref LL_RTC_MONTH_JULY
+ * @arg @ref LL_RTC_MONTH_AUGUST
+ * @arg @ref LL_RTC_MONTH_SEPTEMBER
+ * @arg @ref LL_RTC_MONTH_OCTOBER
+ * @arg @ref LL_RTC_MONTH_NOVEMBER
+ * @arg @ref LL_RTC_MONTH_DECEMBER
+ * @param Year Value between Min_Data=0x00 and Max_Data=0x99
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month, uint32_t Year)
+{
+ register uint32_t temp = 0U;
+
+ temp = (WeekDay << RTC_DR_WDU_Pos) | \
+ (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)) | \
+ (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)) | \
+ (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos));
+
+ MODIFY_REG(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU), temp);
+}
+
+/**
+ * @brief Get date (WeekDay, Day, Month and Year) in BCD format
+ * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * before reading this bit
+ * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH,
+ * and __LL_RTC_GET_DAY are available to get independently each parameter.
+ * @rmtoll DR WDU LL_RTC_DATE_Get\n
+ * DR MT LL_RTC_DATE_Get\n
+ * DR MU LL_RTC_DATE_Get\n
+ * DR DT LL_RTC_DATE_Get\n
+ * DR DU LL_RTC_DATE_Get\n
+ * DR YT LL_RTC_DATE_Get\n
+ * DR YU LL_RTC_DATE_Get
+ * @param RTCx RTC Instance
+ * @retval Combination of WeekDay, Day, Month and Year (Format: 0xWWDDMMYY).
+ */
+__STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx)
+{
+ register uint32_t temp = 0U;
+
+ temp = READ_BIT(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU));
+ return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \
+ (((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos)) << RTC_OFFSET_DAY) | \
+ (((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos)) << RTC_OFFSET_MONTH) | \
+ ((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos)));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EF_ALARMA ALARMA
+ * @{
+ */
+
+/**
+ * @brief Enable Alarm A
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR ALRAE LL_RTC_ALMA_Enable
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_Enable(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_ALRAE);
+}
+
+/**
+ * @brief Disable Alarm A
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR ALRAE LL_RTC_ALMA_Disable
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_Disable(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_ALRAE);
+}
+
+/**
+ * @brief Specify the Alarm A masks.
+ * @rmtoll ALRMAR MSK4 LL_RTC_ALMA_SetMask\n
+ * ALRMAR MSK3 LL_RTC_ALMA_SetMask\n
+ * ALRMAR MSK2 LL_RTC_ALMA_SetMask\n
+ * ALRMAR MSK1 LL_RTC_ALMA_SetMask
+ * @param RTCx RTC Instance
+ * @param Mask This parameter can be a combination of the following values:
+ * @arg @ref LL_RTC_ALMA_MASK_NONE
+ * @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY
+ * @arg @ref LL_RTC_ALMA_MASK_HOURS
+ * @arg @ref LL_RTC_ALMA_MASK_MINUTES
+ * @arg @ref LL_RTC_ALMA_MASK_SECONDS
+ * @arg @ref LL_RTC_ALMA_MASK_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_SetMask(RTC_TypeDef *RTCx, uint32_t Mask)
+{
+ MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1, Mask);
+}
+
+/**
+ * @brief Get the Alarm A masks.
+ * @rmtoll ALRMAR MSK4 LL_RTC_ALMA_GetMask\n
+ * ALRMAR MSK3 LL_RTC_ALMA_GetMask\n
+ * ALRMAR MSK2 LL_RTC_ALMA_GetMask\n
+ * ALRMAR MSK1 LL_RTC_ALMA_GetMask
+ * @param RTCx RTC Instance
+ * @retval Returned value can be can be a combination of the following values:
+ * @arg @ref LL_RTC_ALMA_MASK_NONE
+ * @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY
+ * @arg @ref LL_RTC_ALMA_MASK_HOURS
+ * @arg @ref LL_RTC_ALMA_MASK_MINUTES
+ * @arg @ref LL_RTC_ALMA_MASK_SECONDS
+ * @arg @ref LL_RTC_ALMA_MASK_ALL
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1));
+}
+
+/**
+ * @brief Enable AlarmA Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care)
+ * @rmtoll ALRMAR WDSEL LL_RTC_ALMA_EnableWeekday
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_EnableWeekday(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL);
+}
+
+/**
+ * @brief Disable AlarmA Week day selection (DU[3:0] represents the date )
+ * @rmtoll ALRMAR WDSEL LL_RTC_ALMA_DisableWeekday
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_DisableWeekday(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL);
+}
+
+/**
+ * @brief Set ALARM A Day in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
+ * @rmtoll ALRMAR DT LL_RTC_ALMA_SetDay\n
+ * ALRMAR DU LL_RTC_ALMA_SetDay
+ * @param RTCx RTC Instance
+ * @param Day Value between Min_Data=0x01 and Max_Data=0x31
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
+{
+ MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU),
+ (((Day & 0xF0U) << (RTC_ALRMAR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMAR_DU_Pos)));
+}
+
+/**
+ * @brief Get ALARM A Day in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
+ * @rmtoll ALRMAR DT LL_RTC_ALMA_GetDay\n
+ * ALRMAR DU LL_RTC_ALMA_GetDay
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x01 and Max_Data=0x31
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU))) >> RTC_ALRMAR_DU_Pos);
+}
+
+/**
+ * @brief Set ALARM A Weekday
+ * @rmtoll ALRMAR DU LL_RTC_ALMA_SetWeekDay
+ * @param RTCx RTC Instance
+ * @param WeekDay This parameter can be one of the following values:
+ * @arg @ref LL_RTC_WEEKDAY_MONDAY
+ * @arg @ref LL_RTC_WEEKDAY_TUESDAY
+ * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+ * @arg @ref LL_RTC_WEEKDAY_THURSDAY
+ * @arg @ref LL_RTC_WEEKDAY_FRIDAY
+ * @arg @ref LL_RTC_WEEKDAY_SATURDAY
+ * @arg @ref LL_RTC_WEEKDAY_SUNDAY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
+{
+ MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_DU, WeekDay << RTC_ALRMAR_DU_Pos);
+}
+
+/**
+ * @brief Get ALARM A Weekday
+ * @rmtoll ALRMAR DU LL_RTC_ALMA_GetWeekDay
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_WEEKDAY_MONDAY
+ * @arg @ref LL_RTC_WEEKDAY_TUESDAY
+ * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+ * @arg @ref LL_RTC_WEEKDAY_THURSDAY
+ * @arg @ref LL_RTC_WEEKDAY_FRIDAY
+ * @arg @ref LL_RTC_WEEKDAY_SATURDAY
+ * @arg @ref LL_RTC_WEEKDAY_SUNDAY
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos);
+}
+
+/**
+ * @brief Set Alarm A time format (AM/24-hour or PM notation)
+ * @rmtoll ALRMAR PM LL_RTC_ALMA_SetTimeFormat
+ * @param RTCx RTC Instance
+ * @param TimeFormat This parameter can be one of the following values:
+ * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
+ * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
+{
+ MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM, TimeFormat);
+}
+
+/**
+ * @brief Get Alarm A time format (AM or PM notation)
+ * @rmtoll ALRMAR PM LL_RTC_ALMA_GetTimeFormat
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
+ * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_PM));
+}
+
+/**
+ * @brief Set ALARM A Hours in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format
+ * @rmtoll ALRMAR HT LL_RTC_ALMA_SetHour\n
+ * ALRMAR HU LL_RTC_ALMA_SetHour
+ * @param RTCx RTC Instance
+ * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
+{
+ MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU),
+ (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)));
+}
+
+/**
+ * @brief Get ALARM A Hours in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
+ * @rmtoll ALRMAR HT LL_RTC_ALMA_GetHour\n
+ * ALRMAR HU LL_RTC_ALMA_GetHour
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(( READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU))) >> RTC_ALRMAR_HU_Pos);
+}
+
+/**
+ * @brief Set ALARM A Minutes in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
+ * @rmtoll ALRMAR MNT LL_RTC_ALMA_SetMinute\n
+ * ALRMAR MNU LL_RTC_ALMA_SetMinute
+ * @param RTCx RTC Instance
+ * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
+{
+ MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU),
+ (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)));
+}
+
+/**
+ * @brief Get ALARM A Minutes in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
+ * @rmtoll ALRMAR MNT LL_RTC_ALMA_GetMinute\n
+ * ALRMAR MNU LL_RTC_ALMA_GetMinute
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x59
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU))) >> RTC_ALRMAR_MNU_Pos);
+}
+
+/**
+ * @brief Set ALARM A Seconds in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
+ * @rmtoll ALRMAR ST LL_RTC_ALMA_SetSecond\n
+ * ALRMAR SU LL_RTC_ALMA_SetSecond
+ * @param RTCx RTC Instance
+ * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
+{
+ MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU),
+ (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos)));
+}
+
+/**
+ * @brief Get ALARM A Seconds in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
+ * @rmtoll ALRMAR ST LL_RTC_ALMA_GetSecond\n
+ * ALRMAR SU LL_RTC_ALMA_GetSecond
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x59
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU))) >> RTC_ALRMAR_SU_Pos);
+}
+
+/**
+ * @brief Set Alarm A Time (hour, minute and second) in BCD format
+ * @rmtoll ALRMAR PM LL_RTC_ALMA_ConfigTime\n
+ * ALRMAR HT LL_RTC_ALMA_ConfigTime\n
+ * ALRMAR HU LL_RTC_ALMA_ConfigTime\n
+ * ALRMAR MNT LL_RTC_ALMA_ConfigTime\n
+ * ALRMAR MNU LL_RTC_ALMA_ConfigTime\n
+ * ALRMAR ST LL_RTC_ALMA_ConfigTime\n
+ * ALRMAR SU LL_RTC_ALMA_ConfigTime
+ * @param RTCx RTC Instance
+ * @param Format12_24 This parameter can be one of the following values:
+ * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
+ * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
+ * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+ * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59
+ * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
+{
+ register uint32_t temp = 0U;
+
+ temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)) | \
+ (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)) | \
+ (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos));
+
+ MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM | RTC_ALRMAR_HT | RTC_ALRMAR_HU | RTC_ALRMAR_MNT | RTC_ALRMAR_MNU | RTC_ALRMAR_ST | RTC_ALRMAR_SU, temp);
+}
+
+/**
+ * @brief Get Alarm B Time (hour, minute and second) in BCD format
+ * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
+ * are available to get independently each parameter.
+ * @rmtoll ALRMAR HT LL_RTC_ALMA_GetTime\n
+ * ALRMAR HU LL_RTC_ALMA_GetTime\n
+ * ALRMAR MNT LL_RTC_ALMA_GetTime\n
+ * ALRMAR MNU LL_RTC_ALMA_GetTime\n
+ * ALRMAR ST LL_RTC_ALMA_GetTime\n
+ * ALRMAR SU LL_RTC_ALMA_GetTime
+ * @param RTCx RTC Instance
+ * @retval Combination of hours, minutes and seconds.
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTime(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)((LL_RTC_ALMA_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMA_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMA_GetSecond(RTCx));
+}
+
+/**
+ * @brief Set Alarm A Mask the most-significant bits starting at this bit
+ * @note This register can be written only when ALRAE is reset in RTC_CR register,
+ * or in initialization mode.
+ * @rmtoll ALRMASSR MASKSS LL_RTC_ALMA_SetSubSecondMask
+ * @param RTCx RTC Instance
+ * @param Mask Value between Min_Data=0x00 and Max_Data=0xF
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask)
+{
+ MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS, Mask << RTC_ALRMASSR_MASKSS_Pos);
+}
+
+/**
+ * @brief Get Alarm A Mask the most-significant bits starting at this bit
+ * @rmtoll ALRMASSR MASKSS LL_RTC_ALMA_GetSubSecondMask
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0xF
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS) >> RTC_ALRMASSR_MASKSS_Pos);
+}
+
+/**
+ * @brief Set Alarm A Sub seconds value
+ * @rmtoll ALRMASSR SS LL_RTC_ALMA_SetSubSecond
+ * @param RTCx RTC Instance
+ * @param Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond)
+{
+ MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_SS, Subsecond);
+}
+
+/**
+ * @brief Get Alarm A Sub seconds value
+ * @rmtoll ALRMASSR SS LL_RTC_ALMA_GetSubSecond
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_SS));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EF_ALARMB ALARMB
+ * @{
+ */
+
+/**
+ * @brief Enable Alarm B
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR ALRBE LL_RTC_ALMB_Enable
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_Enable(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_ALRBE);
+}
+
+/**
+ * @brief Disable Alarm B
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR ALRBE LL_RTC_ALMB_Disable
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_Disable(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_ALRBE);
+}
+
+/**
+ * @brief Specify the Alarm B masks.
+ * @rmtoll ALRMBR MSK4 LL_RTC_ALMB_SetMask\n
+ * ALRMBR MSK3 LL_RTC_ALMB_SetMask\n
+ * ALRMBR MSK2 LL_RTC_ALMB_SetMask\n
+ * ALRMBR MSK1 LL_RTC_ALMB_SetMask
+ * @param RTCx RTC Instance
+ * @param Mask This parameter can be a combination of the following values:
+ * @arg @ref LL_RTC_ALMB_MASK_NONE
+ * @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY
+ * @arg @ref LL_RTC_ALMB_MASK_HOURS
+ * @arg @ref LL_RTC_ALMB_MASK_MINUTES
+ * @arg @ref LL_RTC_ALMB_MASK_SECONDS
+ * @arg @ref LL_RTC_ALMB_MASK_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_SetMask(RTC_TypeDef *RTCx, uint32_t Mask)
+{
+ MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1, Mask);
+}
+
+/**
+ * @brief Get the Alarm B masks.
+ * @rmtoll ALRMBR MSK4 LL_RTC_ALMB_GetMask\n
+ * ALRMBR MSK3 LL_RTC_ALMB_GetMask\n
+ * ALRMBR MSK2 LL_RTC_ALMB_GetMask\n
+ * ALRMBR MSK1 LL_RTC_ALMB_GetMask
+ * @param RTCx RTC Instance
+ * @retval Returned value can be can be a combination of the following values:
+ * @arg @ref LL_RTC_ALMB_MASK_NONE
+ * @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY
+ * @arg @ref LL_RTC_ALMB_MASK_HOURS
+ * @arg @ref LL_RTC_ALMB_MASK_MINUTES
+ * @arg @ref LL_RTC_ALMB_MASK_SECONDS
+ * @arg @ref LL_RTC_ALMB_MASK_ALL
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1));
+}
+
+/**
+ * @brief Enable AlarmB Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care)
+ * @rmtoll ALRMBR WDSEL LL_RTC_ALMB_EnableWeekday
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_EnableWeekday(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL);
+}
+
+/**
+ * @brief Disable AlarmB Week day selection (DU[3:0] represents the date )
+ * @rmtoll ALRMBR WDSEL LL_RTC_ALMB_DisableWeekday
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_DisableWeekday(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL);
+}
+
+/**
+ * @brief Set ALARM B Day in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
+ * @rmtoll ALRMBR DT LL_RTC_ALMB_SetDay\n
+ * ALRMBR DU LL_RTC_ALMB_SetDay
+ * @param RTCx RTC Instance
+ * @param Day Value between Min_Data=0x01 and Max_Data=0x31
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
+{
+ MODIFY_REG(RTC->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU),
+ (((Day & 0xF0U) << (RTC_ALRMBR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMBR_DU_Pos)));
+}
+
+/**
+ * @brief Get ALARM B Day in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
+ * @rmtoll ALRMBR DT LL_RTC_ALMB_GetDay\n
+ * ALRMBR DU LL_RTC_ALMB_GetDay
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x01 and Max_Data=0x31
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(( READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU))) >> RTC_ALRMBR_DU_Pos);
+}
+
+/**
+ * @brief Set ALARM B Weekday
+ * @rmtoll ALRMBR DU LL_RTC_ALMB_SetWeekDay
+ * @param RTCx RTC Instance
+ * @param WeekDay This parameter can be one of the following values:
+ * @arg @ref LL_RTC_WEEKDAY_MONDAY
+ * @arg @ref LL_RTC_WEEKDAY_TUESDAY
+ * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+ * @arg @ref LL_RTC_WEEKDAY_THURSDAY
+ * @arg @ref LL_RTC_WEEKDAY_FRIDAY
+ * @arg @ref LL_RTC_WEEKDAY_SATURDAY
+ * @arg @ref LL_RTC_WEEKDAY_SUNDAY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
+{
+ MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_DU, WeekDay << RTC_ALRMBR_DU_Pos);
+}
+
+/**
+ * @brief Get ALARM B Weekday
+ * @rmtoll ALRMBR DU LL_RTC_ALMB_GetWeekDay
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_WEEKDAY_MONDAY
+ * @arg @ref LL_RTC_WEEKDAY_TUESDAY
+ * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+ * @arg @ref LL_RTC_WEEKDAY_THURSDAY
+ * @arg @ref LL_RTC_WEEKDAY_FRIDAY
+ * @arg @ref LL_RTC_WEEKDAY_SATURDAY
+ * @arg @ref LL_RTC_WEEKDAY_SUNDAY
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos);
+}
+
+/**
+ * @brief Set ALARM B time format (AM/24-hour or PM notation)
+ * @rmtoll ALRMBR PM LL_RTC_ALMB_SetTimeFormat
+ * @param RTCx RTC Instance
+ * @param TimeFormat This parameter can be one of the following values:
+ * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
+ * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
+{
+ MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM, TimeFormat);
+}
+
+/**
+ * @brief Get ALARM B time format (AM or PM notation)
+ * @rmtoll ALRMBR PM LL_RTC_ALMB_GetTimeFormat
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
+ * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_PM));
+}
+
+/**
+ * @brief Set ALARM B Hours in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format
+ * @rmtoll ALRMBR HT LL_RTC_ALMB_SetHour\n
+ * ALRMBR HU LL_RTC_ALMB_SetHour
+ * @param RTCx RTC Instance
+ * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
+{
+ MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU),
+ (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)));
+}
+
+/**
+ * @brief Get ALARM B Hours in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
+ * @rmtoll ALRMBR HT LL_RTC_ALMB_GetHour\n
+ * ALRMBR HU LL_RTC_ALMB_GetHour
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU))) >> RTC_ALRMBR_HU_Pos);
+}
+
+/**
+ * @brief Set ALARM B Minutes in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
+ * @rmtoll ALRMBR MNT LL_RTC_ALMB_SetMinute\n
+ * ALRMBR MNU LL_RTC_ALMB_SetMinute
+ * @param RTCx RTC Instance
+ * @param Minutes between Min_Data=0x00 and Max_Data=0x59
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
+{
+ MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU),
+ (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)));
+}
+
+/**
+ * @brief Get ALARM B Minutes in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
+ * @rmtoll ALRMBR MNT LL_RTC_ALMB_GetMinute\n
+ * ALRMBR MNU LL_RTC_ALMB_GetMinute
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x59
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(RTC_TypeDef *RTCx)
+{
+return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU))) >> RTC_ALRMBR_MNU_Pos);
+}
+
+/**
+ * @brief Set ALARM B Seconds in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
+ * @rmtoll ALRMBR ST LL_RTC_ALMB_SetSecond\n
+ * ALRMBR SU LL_RTC_ALMB_SetSecond
+ * @param RTCx RTC Instance
+ * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
+{
+ MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU),
+ (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos)));
+}
+
+/**
+ * @brief Get ALARM B Seconds in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
+ * @rmtoll ALRMBR ST LL_RTC_ALMB_GetSecond\n
+ * ALRMBR SU LL_RTC_ALMB_GetSecond
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x59
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU))) >> RTC_ALRMBR_SU_Pos);
+}
+
+/**
+ * @brief Set Alarm B Time (hour, minute and second) in BCD format
+ * @rmtoll ALRMBR PM LL_RTC_ALMB_ConfigTime\n
+ * ALRMBR HT LL_RTC_ALMB_ConfigTime\n
+ * ALRMBR HU LL_RTC_ALMB_ConfigTime\n
+ * ALRMBR MNT LL_RTC_ALMB_ConfigTime\n
+ * ALRMBR MNU LL_RTC_ALMB_ConfigTime\n
+ * ALRMBR ST LL_RTC_ALMB_ConfigTime\n
+ * ALRMBR SU LL_RTC_ALMB_ConfigTime
+ * @param RTCx RTC Instance
+ * @param Format12_24 This parameter can be one of the following values:
+ * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
+ * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
+ * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+ * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59
+ * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
+{
+ register uint32_t temp = 0U;
+
+ temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)) | \
+ (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)) | \
+ (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos));
+
+ MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM| RTC_ALRMBR_HT | RTC_ALRMBR_HU | RTC_ALRMBR_MNT | RTC_ALRMBR_MNU | RTC_ALRMBR_ST | RTC_ALRMBR_SU, temp);
+}
+
+/**
+ * @brief Get Alarm B Time (hour, minute and second) in BCD format
+ * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
+ * are available to get independently each parameter.
+ * @rmtoll ALRMBR HT LL_RTC_ALMB_GetTime\n
+ * ALRMBR HU LL_RTC_ALMB_GetTime\n
+ * ALRMBR MNT LL_RTC_ALMB_GetTime\n
+ * ALRMBR MNU LL_RTC_ALMB_GetTime\n
+ * ALRMBR ST LL_RTC_ALMB_GetTime\n
+ * ALRMBR SU LL_RTC_ALMB_GetTime
+ * @param RTCx RTC Instance
+ * @retval Combination of hours, minutes and seconds.
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTime(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)((LL_RTC_ALMB_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMB_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMB_GetSecond(RTCx));
+}
+
+/**
+ * @brief Set Alarm B Mask the most-significant bits starting at this bit
+ * @note This register can be written only when ALRBE is reset in RTC_CR register,
+ * or in initialization mode.
+ * @rmtoll ALRMBSSR MASKSS LL_RTC_ALMB_SetSubSecondMask
+ * @param RTCx RTC Instance
+ * @param Mask Value between Min_Data=0x00 and Max_Data=0xF
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask)
+{
+ MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS, Mask << RTC_ALRMBSSR_MASKSS_Pos);
+}
+
+/**
+ * @brief Get Alarm B Mask the most-significant bits starting at this bit
+ * @rmtoll ALRMBSSR MASKSS LL_RTC_ALMB_GetSubSecondMask
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0xF
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS) >> RTC_ALRMBSSR_MASKSS_Pos);
+}
+
+/**
+ * @brief Set Alarm B Sub seconds value
+ * @rmtoll ALRMBSSR SS LL_RTC_ALMB_SetSubSecond
+ * @param RTCx RTC Instance
+ * @param Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond)
+{
+ MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS, Subsecond);
+}
+
+/**
+ * @brief Get Alarm B Sub seconds value
+ * @rmtoll ALRMBSSR SS LL_RTC_ALMB_GetSubSecond
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EF_Timestamp Timestamp
+ * @{
+ */
+
+/**
+ * @brief Enable Timestamp
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR TSE LL_RTC_TS_Enable
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TS_Enable(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_TSE);
+}
+
+/**
+ * @brief Disable Timestamp
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR TSE LL_RTC_TS_Disable
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TS_Disable(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_TSE);
+}
+
+/**
+ * @brief Set Time-stamp event active edge
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting
+ * @rmtoll CR TSEDGE LL_RTC_TS_SetActiveEdge
+ * @param RTCx RTC Instance
+ * @param Edge This parameter can be one of the following values:
+ * @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING
+ * @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TS_SetActiveEdge(RTC_TypeDef *RTCx, uint32_t Edge)
+{
+ MODIFY_REG(RTCx->CR, RTC_CR_TSEDGE, Edge);
+}
+
+/**
+ * @brief Get Time-stamp event active edge
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR TSEDGE LL_RTC_TS_GetActiveEdge
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING
+ * @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING
+ */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TSEDGE));
+}
+
+/**
+ * @brief Get Timestamp AM/PM notation (AM or 24-hour format)
+ * @rmtoll TSTR PM LL_RTC_TS_GetTimeFormat
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_TS_TIME_FORMAT_AM
+ * @arg @ref LL_RTC_TS_TIME_FORMAT_PM
+ */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_PM));
+}
+
+/**
+ * @brief Get Timestamp Hours in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
+ * @rmtoll TSTR HT LL_RTC_TS_GetHour\n
+ * TSTR HU LL_RTC_TS_GetHour
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+ */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU) >> RTC_TSTR_HU_Pos);
+}
+
+/**
+ * @brief Get Timestamp Minutes in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
+ * @rmtoll TSTR MNT LL_RTC_TS_GetMinute\n
+ * TSTR MNU LL_RTC_TS_GetMinute
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x59
+ */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_MNT | RTC_TSTR_MNU) >> RTC_TSTR_MNU_Pos);
+}
+
+/**
+ * @brief Get Timestamp Seconds in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
+ * @rmtoll TSTR ST LL_RTC_TS_GetSecond\n
+ * TSTR SU LL_RTC_TS_GetSecond
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x59
+ */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_ST | RTC_TSTR_SU));
+}
+
+/**
+ * @brief Get Timestamp time (hour, minute and second) in BCD format
+ * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
+ * are available to get independently each parameter.
+ * @rmtoll TSTR HT LL_RTC_TS_GetTime\n
+ * TSTR HU LL_RTC_TS_GetTime\n
+ * TSTR MNT LL_RTC_TS_GetTime\n
+ * TSTR MNU LL_RTC_TS_GetTime\n
+ * TSTR ST LL_RTC_TS_GetTime\n
+ * TSTR SU LL_RTC_TS_GetTime
+ * @param RTCx RTC Instance
+ * @retval Combination of hours, minutes and seconds.
+ */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetTime(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TSTR,
+ RTC_TSTR_HT | RTC_TSTR_HU | RTC_TSTR_MNT | RTC_TSTR_MNU | RTC_TSTR_ST | RTC_TSTR_SU));
+}
+
+/**
+ * @brief Get Timestamp Week day
+ * @rmtoll TSDR WDU LL_RTC_TS_GetWeekDay
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_WEEKDAY_MONDAY
+ * @arg @ref LL_RTC_WEEKDAY_TUESDAY
+ * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+ * @arg @ref LL_RTC_WEEKDAY_THURSDAY
+ * @arg @ref LL_RTC_WEEKDAY_FRIDAY
+ * @arg @ref LL_RTC_WEEKDAY_SATURDAY
+ * @arg @ref LL_RTC_WEEKDAY_SUNDAY
+ */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU) >> RTC_TSDR_WDU_Pos);
+}
+
+/**
+ * @brief Get Timestamp Month in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
+ * @rmtoll TSDR MT LL_RTC_TS_GetMonth\n
+ * TSDR MU LL_RTC_TS_GetMonth
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_MONTH_JANUARY
+ * @arg @ref LL_RTC_MONTH_FEBRUARY
+ * @arg @ref LL_RTC_MONTH_MARCH
+ * @arg @ref LL_RTC_MONTH_APRIL
+ * @arg @ref LL_RTC_MONTH_MAY
+ * @arg @ref LL_RTC_MONTH_JUNE
+ * @arg @ref LL_RTC_MONTH_JULY
+ * @arg @ref LL_RTC_MONTH_AUGUST
+ * @arg @ref LL_RTC_MONTH_SEPTEMBER
+ * @arg @ref LL_RTC_MONTH_OCTOBER
+ * @arg @ref LL_RTC_MONTH_NOVEMBER
+ * @arg @ref LL_RTC_MONTH_DECEMBER
+ */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_MT | RTC_TSDR_MU) >> RTC_TSDR_MU_Pos);
+}
+
+/**
+ * @brief Get Timestamp Day in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
+ * @rmtoll TSDR DT LL_RTC_TS_GetDay\n
+ * TSDR DU LL_RTC_TS_GetDay
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x01 and Max_Data=0x31
+ */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetDay(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_DT | RTC_TSDR_DU));
+}
+
+/**
+ * @brief Get Timestamp date (WeekDay, Day and Month) in BCD format
+ * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_MONTH,
+ * and __LL_RTC_GET_DAY are available to get independently each parameter.
+ * @rmtoll TSDR WDU LL_RTC_TS_GetDate\n
+ * TSDR MT LL_RTC_TS_GetDate\n
+ * TSDR MU LL_RTC_TS_GetDate\n
+ * TSDR DT LL_RTC_TS_GetDate\n
+ * TSDR DU LL_RTC_TS_GetDate
+ * @param RTCx RTC Instance
+ * @retval Combination of Weekday, Day and Month
+ */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetDate(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU | RTC_TSDR_MT | RTC_TSDR_MU | RTC_TSDR_DT | RTC_TSDR_DU));
+}
+
+/**
+ * @brief Get time-stamp sub second value
+ * @rmtoll TSSSR SS LL_RTC_TS_GetSubSecond
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TSSSR, RTC_TSSSR_SS));
+}
+
+#if defined(RTC_TAFCR_TAMPTS)
+/**
+ * @brief Activate timestamp on tamper detection event
+ * @rmtoll TAFCR TAMPTS LL_RTC_TS_EnableOnTamper
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TS_EnableOnTamper(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPTS);
+}
+
+/**
+ * @brief Disable timestamp on tamper detection event
+ * @rmtoll TAFCR TAMPTS LL_RTC_TS_DisableOnTamper
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPTS);
+}
+#endif /* RTC_TAFCR_TAMPTS */
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EF_Tamper Tamper
+ * @{
+ */
+
+/**
+ * @brief Enable RTC_TAMPx input detection
+ * @rmtoll TAFCR TAMP1E LL_RTC_TAMPER_Enable\n
+ * TAFCR TAMP2E LL_RTC_TAMPER_Enable\n
+ * TAFCR TAMP3E LL_RTC_TAMPER_Enable
+ * @param RTCx RTC Instance
+ * @param Tamper This parameter can be a combination of the following values:
+ * @arg @ref LL_RTC_TAMPER_1
+ * @arg @ref LL_RTC_TAMPER_2
+ * @arg @ref LL_RTC_TAMPER_3 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_Enable(RTC_TypeDef *RTCx, uint32_t Tamper)
+{
+ SET_BIT(RTCx->TAFCR, Tamper);
+}
+
+/**
+ * @brief Clear RTC_TAMPx input detection
+ * @rmtoll TAFCR TAMP1E LL_RTC_TAMPER_Disable\n
+ * TAFCR TAMP2E LL_RTC_TAMPER_Disable\n
+ * TAFCR TAMP3E LL_RTC_TAMPER_Disable
+ * @param RTCx RTC Instance
+ * @param Tamper This parameter can be a combination of the following values:
+ * @arg @ref LL_RTC_TAMPER_1
+ * @arg @ref LL_RTC_TAMPER_2
+ * @arg @ref LL_RTC_TAMPER_3 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_Disable(RTC_TypeDef *RTCx, uint32_t Tamper)
+{
+ CLEAR_BIT(RTCx->TAFCR, Tamper);
+}
+
+#if defined(RTC_TAFCR_TAMPPUDIS)
+/**
+ * @brief Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins)
+ * @rmtoll TAFCR TAMPPUDIS LL_RTC_TAMPER_DisablePullUp
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPPUDIS);
+}
+
+/**
+ * @brief Enable RTC_TAMPx pull-up disable ( Precharge RTC_TAMPx pins before sampling)
+ * @rmtoll TAFCR TAMPPUDIS LL_RTC_TAMPER_EnablePullUp
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPPUDIS);
+}
+#endif /* RTC_TAFCR_TAMPPUDIS */
+
+#if defined(RTC_TAFCR_TAMPPRCH)
+/**
+ * @brief Set RTC_TAMPx precharge duration
+ * @rmtoll TAFCR TAMPPRCH LL_RTC_TAMPER_SetPrecharge
+ * @param RTCx RTC Instance
+ * @param Duration This parameter can be one of the following values:
+ * @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK
+ * @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK
+ * @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK
+ * @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(RTC_TypeDef *RTCx, uint32_t Duration)
+{
+ MODIFY_REG(RTCx->TAFCR, RTC_TAFCR_TAMPPRCH, Duration);
+}
+
+/**
+ * @brief Get RTC_TAMPx precharge duration
+ * @rmtoll TAFCR TAMPPRCH LL_RTC_TAMPER_GetPrecharge
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK
+ * @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK
+ * @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK
+ * @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK
+ */
+__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPPRCH));
+}
+#endif /* RTC_TAFCR_TAMPPRCH */
+
+#if defined(RTC_TAFCR_TAMPFLT)
+/**
+ * @brief Set RTC_TAMPx filter count
+ * @rmtoll TAFCR TAMPFLT LL_RTC_TAMPER_SetFilterCount
+ * @param RTCx RTC Instance
+ * @param FilterCount This parameter can be one of the following values:
+ * @arg @ref LL_RTC_TAMPER_FILTER_DISABLE
+ * @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE
+ * @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE
+ * @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(RTC_TypeDef *RTCx, uint32_t FilterCount)
+{
+ MODIFY_REG(RTCx->TAFCR, RTC_TAFCR_TAMPFLT, FilterCount);
+}
+
+/**
+ * @brief Get RTC_TAMPx filter count
+ * @rmtoll TAFCR TAMPFLT LL_RTC_TAMPER_GetFilterCount
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_TAMPER_FILTER_DISABLE
+ * @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE
+ * @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE
+ * @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE
+ */
+__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPFLT));
+}
+#endif /* RTC_TAFCR_TAMPFLT */
+
+#if defined(RTC_TAFCR_TAMPFREQ)
+/**
+ * @brief Set Tamper sampling frequency
+ * @rmtoll TAFCR TAMPFREQ LL_RTC_TAMPER_SetSamplingFreq
+ * @param RTCx RTC Instance
+ * @param SamplingFreq This parameter can be one of the following values:
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(RTC_TypeDef *RTCx, uint32_t SamplingFreq)
+{
+ MODIFY_REG(RTCx->TAFCR, RTC_TAFCR_TAMPFREQ, SamplingFreq);
+}
+
+/**
+ * @brief Get Tamper sampling frequency
+ * @rmtoll TAFCR TAMPFREQ LL_RTC_TAMPER_GetSamplingFreq
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256
+ */
+__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPFREQ));
+}
+#endif /* RTC_TAFCR_TAMPFREQ */
+
+/**
+ * @brief Enable Active level for Tamper input
+ * @rmtoll TAFCR TAMP1TRG LL_RTC_TAMPER_EnableActiveLevel\n
+ * TAFCR TAMP2TRG LL_RTC_TAMPER_EnableActiveLevel\n
+ * TAFCR TAMP3TRG LL_RTC_TAMPER_EnableActiveLevel
+ * @param RTCx RTC Instance
+ * @param Tamper This parameter can be a combination of the following values:
+ * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1
+ * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2
+ * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper)
+{
+ SET_BIT(RTCx->TAFCR, Tamper);
+}
+
+/**
+ * @brief Disable Active level for Tamper input
+ * @rmtoll TAFCR TAMP1TRG LL_RTC_TAMPER_DisableActiveLevel\n
+ * TAFCR TAMP2TRG LL_RTC_TAMPER_DisableActiveLevel\n
+ * TAFCR TAMP3TRG LL_RTC_TAMPER_DisableActiveLevel
+ * @param RTCx RTC Instance
+ * @param Tamper This parameter can be a combination of the following values:
+ * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1
+ * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2
+ * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper)
+{
+ CLEAR_BIT(RTCx->TAFCR, Tamper);
+}
+
+/**
+ * @}
+ */
+
+#if defined(RTC_WAKEUP_SUPPORT)
+/** @defgroup RTC_LL_EF_Wakeup Wakeup
+ * @{
+ */
+
+/**
+ * @brief Enable Wakeup timer
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR WUTE LL_RTC_WAKEUP_Enable
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_WAKEUP_Enable(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_WUTE);
+}
+
+/**
+ * @brief Disable Wakeup timer
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR WUTE LL_RTC_WAKEUP_Disable
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_WAKEUP_Disable(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_WUTE);
+}
+
+/**
+ * @brief Check if Wakeup timer is enabled or not
+ * @rmtoll CR WUTE LL_RTC_WAKEUP_IsEnabled
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE));
+}
+
+/**
+ * @brief Select Wakeup clock
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note Bit can be written only when RTC_CR WUTE bit = 0 and RTC_ISR WUTWF bit = 1
+ * @rmtoll CR WUCKSEL LL_RTC_WAKEUP_SetClock
+ * @param RTCx RTC Instance
+ * @param WakeupClock This parameter can be one of the following values:
+ * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16
+ * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8
+ * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4
+ * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2
+ * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE
+ * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_WAKEUP_SetClock(RTC_TypeDef *RTCx, uint32_t WakeupClock)
+{
+ MODIFY_REG(RTCx->CR, RTC_CR_WUCKSEL, WakeupClock);
+}
+
+/**
+ * @brief Get Wakeup clock
+ * @rmtoll CR WUCKSEL LL_RTC_WAKEUP_GetClock
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16
+ * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8
+ * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4
+ * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2
+ * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE
+ * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT
+ */
+__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_WUCKSEL));
+}
+
+/**
+ * @brief Set Wakeup auto-reload value
+ * @note Bit can be written only when WUTWF is set to 1 in RTC_ISR
+ * @rmtoll WUTR WUT LL_RTC_WAKEUP_SetAutoReload
+ * @param RTCx RTC Instance
+ * @param Value Value between Min_Data=0x00 and Max_Data=0xFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_WAKEUP_SetAutoReload(RTC_TypeDef *RTCx, uint32_t Value)
+{
+ MODIFY_REG(RTCx->WUTR, RTC_WUTR_WUT, Value);
+}
+
+/**
+ * @brief Get Wakeup auto-reload value
+ * @rmtoll WUTR WUT LL_RTC_WAKEUP_GetAutoReload
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->WUTR, RTC_WUTR_WUT));
+}
+
+/**
+ * @}
+ */
+#endif /* RTC_WAKEUP_SUPPORT */
+
+#if defined(RTC_BACKUP_SUPPORT)
+/** @defgroup RTC_LL_EF_Backup_Registers Backup_Registers
+ * @{
+ */
+
+/**
+ * @brief Writes a data in a specified RTC Backup data register.
+ * @rmtoll BKPxR BKP LL_RTC_BAK_SetRegister
+ * @param RTCx RTC Instance
+ * @param BackupRegister This parameter can be one of the following values:
+ * @arg @ref LL_RTC_BKP_DR0
+ * @arg @ref LL_RTC_BKP_DR1
+ * @arg @ref LL_RTC_BKP_DR2
+ * @arg @ref LL_RTC_BKP_DR3
+ * @arg @ref LL_RTC_BKP_DR4
+ * @arg @ref LL_RTC_BKP_DR5 (*)
+ * @arg @ref LL_RTC_BKP_DR6 (*)
+ * @arg @ref LL_RTC_BKP_DR7 (*)
+ * @arg @ref LL_RTC_BKP_DR8 (*)
+ * @arg @ref LL_RTC_BKP_DR9 (*)
+ * @arg @ref LL_RTC_BKP_DR10 (*)
+ * @arg @ref LL_RTC_BKP_DR11 (*)
+ * @arg @ref LL_RTC_BKP_DR12 (*)
+ * @arg @ref LL_RTC_BKP_DR13 (*)
+ * @arg @ref LL_RTC_BKP_DR14 (*)
+ * @arg @ref LL_RTC_BKP_DR15 (*)
+ * @arg @ref LL_RTC_BKP_DR16 (*)
+ * @arg @ref LL_RTC_BKP_DR17 (*)
+ * @arg @ref LL_RTC_BKP_DR18 (*)
+ * @arg @ref LL_RTC_BKP_DR19 (*)
+ * @arg @ref LL_RTC_BKP_DR20 (*)
+ * @arg @ref LL_RTC_BKP_DR21 (*)
+ * @arg @ref LL_RTC_BKP_DR22 (*)
+ * @arg @ref LL_RTC_BKP_DR23 (*)
+ * @arg @ref LL_RTC_BKP_DR24 (*)
+ * @arg @ref LL_RTC_BKP_DR25 (*)
+ * @arg @ref LL_RTC_BKP_DR26 (*)
+ * @arg @ref LL_RTC_BKP_DR27 (*)
+ * @arg @ref LL_RTC_BKP_DR28 (*)
+ * @arg @ref LL_RTC_BKP_DR29 (*)
+ * @arg @ref LL_RTC_BKP_DR30 (*)
+ * @arg @ref LL_RTC_BKP_DR31 (*)
+ *
+ * (*) value not defined in all devices.
+ * @param Data Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_BAK_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data)
+{
+ register uint32_t tmp = 0U;
+
+ tmp = (uint32_t)(&(RTCx->BKP0R));
+ tmp += (BackupRegister * 4U);
+
+ /* Write the specified register */
+ *(__IO uint32_t *)tmp = (uint32_t)Data;
+}
+
+/**
+ * @brief Reads data from the specified RTC Backup data Register.
+ * @rmtoll BKPxR BKP LL_RTC_BAK_GetRegister
+ * @param RTCx RTC Instance
+ * @param BackupRegister This parameter can be one of the following values:
+ * @arg @ref LL_RTC_BKP_DR0
+ * @arg @ref LL_RTC_BKP_DR1
+ * @arg @ref LL_RTC_BKP_DR2
+ * @arg @ref LL_RTC_BKP_DR3
+ * @arg @ref LL_RTC_BKP_DR4
+ * @arg @ref LL_RTC_BKP_DR5 (*)
+ * @arg @ref LL_RTC_BKP_DR6 (*)
+ * @arg @ref LL_RTC_BKP_DR7 (*)
+ * @arg @ref LL_RTC_BKP_DR8 (*)
+ * @arg @ref LL_RTC_BKP_DR9 (*)
+ * @arg @ref LL_RTC_BKP_DR10 (*)
+ * @arg @ref LL_RTC_BKP_DR11 (*)
+ * @arg @ref LL_RTC_BKP_DR12 (*)
+ * @arg @ref LL_RTC_BKP_DR13 (*)
+ * @arg @ref LL_RTC_BKP_DR14 (*)
+ * @arg @ref LL_RTC_BKP_DR15 (*)
+ * @arg @ref LL_RTC_BKP_DR16 (*)
+ * @arg @ref LL_RTC_BKP_DR17 (*)
+ * @arg @ref LL_RTC_BKP_DR18 (*)
+ * @arg @ref LL_RTC_BKP_DR19 (*)
+ * @arg @ref LL_RTC_BKP_DR20 (*)
+ * @arg @ref LL_RTC_BKP_DR21 (*)
+ * @arg @ref LL_RTC_BKP_DR22 (*)
+ * @arg @ref LL_RTC_BKP_DR23 (*)
+ * @arg @ref LL_RTC_BKP_DR24 (*)
+ * @arg @ref LL_RTC_BKP_DR25 (*)
+ * @arg @ref LL_RTC_BKP_DR26 (*)
+ * @arg @ref LL_RTC_BKP_DR27 (*)
+ * @arg @ref LL_RTC_BKP_DR28 (*)
+ * @arg @ref LL_RTC_BKP_DR29 (*)
+ * @arg @ref LL_RTC_BKP_DR30 (*)
+ * @arg @ref LL_RTC_BKP_DR31 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister)
+{
+ register uint32_t tmp = 0U;
+
+ tmp = (uint32_t)(&(RTCx->BKP0R));
+ tmp += (BackupRegister * 4U);
+
+ /* Read the specified register */
+ return (*(__IO uint32_t *)tmp);
+}
+
+/**
+ * @}
+ */
+#endif /* RTC_BACKUP_SUPPORT */
+
+/** @defgroup RTC_LL_EF_Calibration Calibration
+ * @{
+ */
+
+/**
+ * @brief Set Calibration output frequency (1 Hz or 512 Hz)
+ * @note Bits are write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR COE LL_RTC_CAL_SetOutputFreq\n
+ * CR COSEL LL_RTC_CAL_SetOutputFreq
+ * @param RTCx RTC Instance
+ * @param Frequency This parameter can be one of the following values:
+ * @arg @ref LL_RTC_CALIB_OUTPUT_NONE
+ * @arg @ref LL_RTC_CALIB_OUTPUT_1HZ
+ * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_CAL_SetOutputFreq(RTC_TypeDef *RTCx, uint32_t Frequency)
+{
+ MODIFY_REG(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL, Frequency);
+}
+
+/**
+ * @brief Get Calibration output frequency (1 Hz or 512 Hz)
+ * @rmtoll CR COE LL_RTC_CAL_GetOutputFreq\n
+ * CR COSEL LL_RTC_CAL_GetOutputFreq
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_CALIB_OUTPUT_NONE
+ * @arg @ref LL_RTC_CALIB_OUTPUT_1HZ
+ * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ
+ */
+__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL));
+}
+
+/**
+ * @brief Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm)
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note Bit can be written only when RECALPF is set to 0 in RTC_ISR
+ * @rmtoll CALR CALP LL_RTC_CAL_SetPulse
+ * @param RTCx RTC Instance
+ * @param Pulse This parameter can be one of the following values:
+ * @arg @ref LL_RTC_CALIB_INSERTPULSE_NONE
+ * @arg @ref LL_RTC_CALIB_INSERTPULSE_SET
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_CAL_SetPulse(RTC_TypeDef *RTCx, uint32_t Pulse)
+{
+ MODIFY_REG(RTCx->CALR, RTC_CALR_CALP, Pulse);
+}
+
+/**
+ * @brief Check if one RTCCLK has been inserted or not every 2exp11 pulses (frequency increased by 488.5 ppm)
+ * @rmtoll CALR CALP LL_RTC_CAL_IsPulseInserted
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP));
+}
+
+/**
+ * @brief Set the calibration cycle period
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note Bit can be written only when RECALPF is set to 0 in RTC_ISR
+ * @rmtoll CALR CALW8 LL_RTC_CAL_SetPeriod\n
+ * CALR CALW16 LL_RTC_CAL_SetPeriod
+ * @param RTCx RTC Instance
+ * @param Period This parameter can be one of the following values:
+ * @arg @ref LL_RTC_CALIB_PERIOD_32SEC
+ * @arg @ref LL_RTC_CALIB_PERIOD_16SEC
+ * @arg @ref LL_RTC_CALIB_PERIOD_8SEC
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_CAL_SetPeriod(RTC_TypeDef *RTCx, uint32_t Period)
+{
+ MODIFY_REG(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16, Period);
+}
+
+/**
+ * @brief Get the calibration cycle period
+ * @rmtoll CALR CALW8 LL_RTC_CAL_GetPeriod\n
+ * CALR CALW16 LL_RTC_CAL_GetPeriod
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_CALIB_PERIOD_32SEC
+ * @arg @ref LL_RTC_CALIB_PERIOD_16SEC
+ * @arg @ref LL_RTC_CALIB_PERIOD_8SEC
+ */
+__STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16));
+}
+
+/**
+ * @brief Set Calibration minus
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note Bit can be written only when RECALPF is set to 0 in RTC_ISR
+ * @rmtoll CALR CALM LL_RTC_CAL_SetMinus
+ * @param RTCx RTC Instance
+ * @param CalibMinus Value between Min_Data=0x00 and Max_Data=0x1FF
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_CAL_SetMinus(RTC_TypeDef *RTCx, uint32_t CalibMinus)
+{
+ MODIFY_REG(RTCx->CALR, RTC_CALR_CALM, CalibMinus);
+}
+
+/**
+ * @brief Get Calibration minus
+ * @rmtoll CALR CALM LL_RTC_CAL_GetMinus
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data= 0x1FF
+ */
+__STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALM));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+
+/**
+ * @brief Get Recalibration pending Flag
+ * @rmtoll ISR RECALPF LL_RTC_IsActiveFlag_RECALP
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->ISR, RTC_ISR_RECALPF) == (RTC_ISR_RECALPF));
+}
+
+#if defined(RTC_TAMPER3_SUPPORT)
+/**
+ * @brief Get RTC_TAMP3 detection flag
+ * @rmtoll ISR TAMP3F LL_RTC_IsActiveFlag_TAMP3
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->ISR, RTC_ISR_TAMP3F) == (RTC_ISR_TAMP3F));
+}
+#endif /* RTC_TAMPER3_SUPPORT */
+
+#if defined(RTC_TAMPER2_SUPPORT)
+/**
+ * @brief Get RTC_TAMP2 detection flag
+ * @rmtoll ISR TAMP2F LL_RTC_IsActiveFlag_TAMP2
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->ISR, RTC_ISR_TAMP2F) == (RTC_ISR_TAMP2F));
+}
+#endif /* RTC_TAMPER2_SUPPORT */
+
+#if defined(RTC_TAMPER1_SUPPORT)
+/**
+ * @brief Get RTC_TAMP1 detection flag
+ * @rmtoll ISR TAMP1F LL_RTC_IsActiveFlag_TAMP1
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->ISR, RTC_ISR_TAMP1F) == (RTC_ISR_TAMP1F));
+}
+#endif /* RTC_TAMPER1_SUPPORT */
+
+/**
+ * @brief Get Time-stamp overflow flag
+ * @rmtoll ISR TSOVF LL_RTC_IsActiveFlag_TSOV
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->ISR, RTC_ISR_TSOVF) == (RTC_ISR_TSOVF));
+}
+
+/**
+ * @brief Get Time-stamp flag
+ * @rmtoll ISR TSF LL_RTC_IsActiveFlag_TS
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->ISR, RTC_ISR_TSF) == (RTC_ISR_TSF));
+}
+
+#if defined(RTC_WAKEUP_SUPPORT)
+/**
+ * @brief Get Wakeup timer flag
+ * @rmtoll ISR WUTF LL_RTC_IsActiveFlag_WUT
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->ISR, RTC_ISR_WUTF) == (RTC_ISR_WUTF));
+}
+#endif /* RTC_WAKEUP_SUPPORT */
+
+/**
+ * @brief Get Alarm B flag
+ * @rmtoll ISR ALRBF LL_RTC_IsActiveFlag_ALRB
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->ISR, RTC_ISR_ALRBF) == (RTC_ISR_ALRBF));
+}
+
+/**
+ * @brief Get Alarm A flag
+ * @rmtoll ISR ALRAF LL_RTC_IsActiveFlag_ALRA
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->ISR, RTC_ISR_ALRAF) == (RTC_ISR_ALRAF));
+}
+
+#if defined(RTC_TAMPER3_SUPPORT)
+/**
+ * @brief Clear RTC_TAMP3 detection flag
+ * @rmtoll ISR TAMP3F LL_RTC_ClearFlag_TAMP3
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_TAMP3(RTC_TypeDef *RTCx)
+{
+ WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP3F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
+}
+#endif /* RTC_TAMPER3_SUPPORT */
+
+#if defined(RTC_TAMPER2_SUPPORT)
+/**
+ * @brief Clear RTC_TAMP2 detection flag
+ * @rmtoll ISR TAMP2F LL_RTC_ClearFlag_TAMP2
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_TAMP2(RTC_TypeDef *RTCx)
+{
+ WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP2F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
+}
+#endif /* RTC_TAMPER2_SUPPORT */
+
+#if defined(RTC_TAMPER1_SUPPORT)
+/**
+ * @brief Clear RTC_TAMP1 detection flag
+ * @rmtoll ISR TAMP1F LL_RTC_ClearFlag_TAMP1
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_TAMP1(RTC_TypeDef *RTCx)
+{
+ WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP1F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
+}
+#endif /* RTC_TAMPER1_SUPPORT */
+
+/**
+ * @brief Clear Time-stamp overflow flag
+ * @rmtoll ISR TSOVF LL_RTC_ClearFlag_TSOV
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_TSOV(RTC_TypeDef *RTCx)
+{
+ WRITE_REG(RTCx->ISR, (~((RTC_ISR_TSOVF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
+}
+
+/**
+ * @brief Clear Time-stamp flag
+ * @rmtoll ISR TSF LL_RTC_ClearFlag_TS
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_TS(RTC_TypeDef *RTCx)
+{
+ WRITE_REG(RTCx->ISR, (~((RTC_ISR_TSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
+}
+
+#if defined(RTC_WAKEUP_SUPPORT)
+/**
+ * @brief Clear Wakeup timer flag
+ * @rmtoll ISR WUTF LL_RTC_ClearFlag_WUT
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_WUT(RTC_TypeDef *RTCx)
+{
+ WRITE_REG(RTCx->ISR, (~((RTC_ISR_WUTF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
+}
+#endif /* RTC_WAKEUP_SUPPORT */
+
+/**
+ * @brief Clear Alarm B flag
+ * @rmtoll ISR ALRBF LL_RTC_ClearFlag_ALRB
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_ALRB(RTC_TypeDef *RTCx)
+{
+ WRITE_REG(RTCx->ISR, (~((RTC_ISR_ALRBF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
+}
+
+/**
+ * @brief Clear Alarm A flag
+ * @rmtoll ISR ALRAF LL_RTC_ClearFlag_ALRA
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_ALRA(RTC_TypeDef *RTCx)
+{
+ WRITE_REG(RTCx->ISR, (~((RTC_ISR_ALRAF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
+}
+
+/**
+ * @brief Get Initialization flag
+ * @rmtoll ISR INITF LL_RTC_IsActiveFlag_INIT
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->ISR, RTC_ISR_INITF) == (RTC_ISR_INITF));
+}
+
+/**
+ * @brief Get Registers synchronization flag
+ * @rmtoll ISR RSF LL_RTC_IsActiveFlag_RS
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->ISR, RTC_ISR_RSF) == (RTC_ISR_RSF));
+}
+
+/**
+ * @brief Clear Registers synchronization flag
+ * @rmtoll ISR RSF LL_RTC_ClearFlag_RS
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx)
+{
+ WRITE_REG(RTCx->ISR, (~((RTC_ISR_RSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
+}
+
+/**
+ * @brief Get Initialization status flag
+ * @rmtoll ISR INITS LL_RTC_IsActiveFlag_INITS
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->ISR, RTC_ISR_INITS) == (RTC_ISR_INITS));
+}
+
+/**
+ * @brief Get Shift operation pending flag
+ * @rmtoll ISR SHPF LL_RTC_IsActiveFlag_SHP
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->ISR, RTC_ISR_SHPF) == (RTC_ISR_SHPF));
+}
+
+#if defined(RTC_WAKEUP_SUPPORT)
+/**
+ * @brief Get Wakeup timer write flag
+ * @rmtoll ISR WUTWF LL_RTC_IsActiveFlag_WUTW
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->ISR, RTC_ISR_WUTWF) == (RTC_ISR_WUTWF));
+}
+#endif /* RTC_WAKEUP_SUPPORT */
+
+/**
+ * @brief Get Alarm B write flag
+ * @rmtoll ISR ALRBWF LL_RTC_IsActiveFlag_ALRBW
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->ISR, RTC_ISR_ALRBWF) == (RTC_ISR_ALRBWF));
+}
+
+/**
+ * @brief Get Alarm A write flag
+ * @rmtoll ISR ALRAWF LL_RTC_IsActiveFlag_ALRAW
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->ISR, RTC_ISR_ALRAWF) == (RTC_ISR_ALRAWF));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EF_IT_Management IT_Management
+ * @{
+ */
+
+/**
+ * @brief Enable Time-stamp interrupt
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR TSIE LL_RTC_EnableIT_TS
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableIT_TS(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_TSIE);
+}
+
+/**
+ * @brief Disable Time-stamp interrupt
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR TSIE LL_RTC_DisableIT_TS
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableIT_TS(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_TSIE);
+}
+
+#if defined(RTC_WAKEUP_SUPPORT)
+/**
+ * @brief Enable Wakeup timer interrupt
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR WUTIE LL_RTC_EnableIT_WUT
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableIT_WUT(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_WUTIE);
+}
+
+/**
+ * @brief Disable Wakeup timer interrupt
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR WUTIE LL_RTC_DisableIT_WUT
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableIT_WUT(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_WUTIE);
+}
+#endif /* RTC_WAKEUP_SUPPORT */
+
+/**
+ * @brief Enable Alarm B interrupt
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR ALRBIE LL_RTC_EnableIT_ALRB
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableIT_ALRB(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_ALRBIE);
+}
+
+/**
+ * @brief Disable Alarm B interrupt
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR ALRBIE LL_RTC_DisableIT_ALRB
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableIT_ALRB(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_ALRBIE);
+}
+
+/**
+ * @brief Enable Alarm A interrupt
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR ALRAIE LL_RTC_EnableIT_ALRA
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableIT_ALRA(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_ALRAIE);
+}
+
+/**
+ * @brief Disable Alarm A interrupt
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR ALRAIE LL_RTC_DisableIT_ALRA
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableIT_ALRA(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_ALRAIE);
+}
+
+/**
+ * @brief Enable all Tamper Interrupt
+ * @rmtoll TAFCR TAMPIE LL_RTC_EnableIT_TAMP
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableIT_TAMP(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPIE);
+}
+
+/**
+ * @brief Disable all Tamper Interrupt
+ * @rmtoll TAFCR TAMPIE LL_RTC_DisableIT_TAMP
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableIT_TAMP(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPIE);
+}
+
+/**
+ * @brief Check if Time-stamp interrupt is enabled or not
+ * @rmtoll CR TSIE LL_RTC_IsEnabledIT_TS
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->CR, RTC_CR_TSIE) == (RTC_CR_TSIE));
+}
+
+#if defined(RTC_WAKEUP_SUPPORT)
+/**
+ * @brief Check if Wakeup timer interrupt is enabled or not
+ * @rmtoll CR WUTIE LL_RTC_IsEnabledIT_WUT
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE));
+}
+#endif /* RTC_WAKEUP_SUPPORT */
+
+/**
+ * @brief Check if Alarm B interrupt is enabled or not
+ * @rmtoll CR ALRBIE LL_RTC_IsEnabledIT_ALRB
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->CR, RTC_CR_ALRBIE) == (RTC_CR_ALRBIE));
+}
+
+/**
+ * @brief Check if Alarm A interrupt is enabled or not
+ * @rmtoll CR ALRAIE LL_RTC_IsEnabledIT_ALRA
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE));
+}
+
+/**
+ * @brief Check if all the TAMPER interrupts are enabled or not
+ * @rmtoll TAFCR TAMPIE LL_RTC_IsEnabledIT_TAMP
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->TAFCR,
+ RTC_TAFCR_TAMPIE) == (RTC_TAFCR_TAMPIE));
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RTC_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx);
+ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct);
+void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct);
+ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct);
+void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct);
+ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct);
+void LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct);
+ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
+ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
+void LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
+void LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
+ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx);
+ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx);
+ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(RTC) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_LL_RTC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_ll_spi.h b/Inc/stm32f3xx_ll_spi.h
new file mode 100644
index 0000000..972acee
--- /dev/null
+++ b/Inc/stm32f3xx_ll_spi.h
@@ -0,0 +1,2271 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_spi.h
+ * @author MCD Application Team
+ * @brief Header file of SPI LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_LL_SPI_H
+#define __STM32F3xx_LL_SPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx.h"
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4)
+
+/** @defgroup SPI_LL SPI
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief SPI Init structures definition
+ */
+typedef struct
+{
+ uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
+ This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
+
+ uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
+ This parameter can be a value of @ref SPI_LL_EC_MODE.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
+
+ uint32_t DataWidth; /*!< Specifies the SPI data width.
+ This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
+
+ uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
+ This parameter can be a value of @ref SPI_LL_EC_POLARITY.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
+
+ uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
+ This parameter can be a value of @ref SPI_LL_EC_PHASE.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
+
+ uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
+ This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
+
+ uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
+ This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
+ @note The communication clock is derived from the master clock. The slave clock does not need to be set.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
+
+ uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
+ This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
+
+ uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
+ This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
+
+ This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
+
+ uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
+
+} LL_SPI_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
+ * @{
+ */
+
+/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_SPI_ReadReg function
+ * @{
+ */
+#define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */
+#define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */
+#define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */
+#define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag */
+#define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */
+#define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */
+#define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format error flag */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
+ * @{
+ */
+#define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
+#define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
+#define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_MODE Operation Mode
+ * @{
+ */
+#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */
+#define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
+ * @{
+ */
+#define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /*!< Motorola mode. Used as default value */
+#define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /*!< TI mode */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_PHASE Clock Phase
+ * @{
+ */
+#define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is the first data capture edge */
+#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_POLARITY Clock Polarity
+ * @{
+ */
+#define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */
+#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
+ * @{
+ */
+#define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< BaudRate control equal to fPCLK/2 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< BaudRate control equal to fPCLK/32 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/64 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/128 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/256 */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
+ * @{
+ */
+#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */
+#define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/received with the MSB first */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
+ * @{
+ */
+#define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
+#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */
+#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */
+#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
+ * @{
+ */
+#define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */
+#define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in Input. Only used in Master mode */
+#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
+ * @{
+ */
+#define LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 4 bits */
+#define LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2) /*!< Data length for SPI transfer: 5 bits */
+#define LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 6 bits */
+#define LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 7 bits */
+#define LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 8 bits */
+#define LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3) /*!< Data length for SPI transfer: 9 bits */
+#define LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 10 bits */
+#define LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 11 bits */
+#define LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 12 bits */
+#define LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2) /*!< Data length for SPI transfer: 13 bits */
+#define LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 14 bits */
+#define LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 15 bits */
+#define LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 16 bits */
+/**
+ * @}
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
+ * @{
+ */
+#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled */
+#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length
+ * @{
+ */
+#define LL_SPI_CRC_8BIT 0x00000000U /*!< 8-bit CRC length */
+#define LL_SPI_CRC_16BIT (SPI_CR1_CRCL) /*!< 16-bit CRC length */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold
+ * @{
+ */
+#define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /*!< RXNE event is generated if FIFO level is greater than or equel to 1/2 (16-bit) */
+#define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /*!< RXNE event is generated if FIFO level is greater than or equel to 1/4 (8-bit) */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level
+ * @{
+ */
+#define LL_SPI_RX_FIFO_EMPTY 0x00000000U /*!< FIFO reception empty */
+#define LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0) /*!< FIFO reception 1/4 */
+#define LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1) /*!< FIFO reception 1/2 */
+#define LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0) /*!< FIFO reception full */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level
+ * @{
+ */
+#define LL_SPI_TX_FIFO_EMPTY 0x00000000U /*!< FIFO transmission empty */
+#define LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0) /*!< FIFO transmission 1/4 */
+#define LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1) /*!< FIFO transmission 1/2 */
+#define LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0) /*!< FIFO transmission full */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity
+ * @{
+ */
+#define LL_SPI_DMA_PARITY_EVEN 0x00000000U /*!< Select DMA parity Even */
+#define LL_SPI_DMA_PARITY_ODD 0x00000001U /*!< Select DMA parity Odd */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
+ * @{
+ */
+
+/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in SPI register
+ * @param __INSTANCE__ SPI Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in SPI register
+ * @param __INSTANCE__ SPI Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
+ * @{
+ */
+
+/** @defgroup SPI_LL_EF_Configuration Configuration
+ * @{
+ */
+
+/**
+ * @brief Enable SPI peripheral
+ * @rmtoll CR1 SPE LL_SPI_Enable
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR1, SPI_CR1_SPE);
+}
+
+/**
+ * @brief Disable SPI peripheral
+ * @note When disabling the SPI, follow the procedure described in the Reference Manual.
+ * @rmtoll CR1 SPE LL_SPI_Disable
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
+}
+
+/**
+ * @brief Check if SPI peripheral is enabled
+ * @rmtoll CR1 SPE LL_SPI_IsEnabled
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE));
+}
+
+/**
+ * @brief Set SPI operation mode to Master or Slave
+ * @note This bit should not be changed when communication is ongoing.
+ * @rmtoll CR1 MSTR LL_SPI_SetMode\n
+ * CR1 SSI LL_SPI_SetMode
+ * @param SPIx SPI Instance
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_SPI_MODE_MASTER
+ * @arg @ref LL_SPI_MODE_SLAVE
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
+}
+
+/**
+ * @brief Get SPI operation mode (Master or Slave)
+ * @rmtoll CR1 MSTR LL_SPI_GetMode\n
+ * CR1 SSI LL_SPI_GetMode
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_MODE_MASTER
+ * @arg @ref LL_SPI_MODE_SLAVE
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
+}
+
+/**
+ * @brief Set serial protocol used
+ * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+ * @rmtoll CR2 FRF LL_SPI_SetStandard
+ * @param SPIx SPI Instance
+ * @param Standard This parameter can be one of the following values:
+ * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
+ * @arg @ref LL_SPI_PROTOCOL_TI
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
+{
+ MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
+}
+
+/**
+ * @brief Get serial protocol used
+ * @rmtoll CR2 FRF LL_SPI_GetStandard
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
+ * @arg @ref LL_SPI_PROTOCOL_TI
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
+}
+
+/**
+ * @brief Set clock phase
+ * @note This bit should not be changed when communication is ongoing.
+ * This bit is not used in SPI TI mode.
+ * @rmtoll CR1 CPHA LL_SPI_SetClockPhase
+ * @param SPIx SPI Instance
+ * @param ClockPhase This parameter can be one of the following values:
+ * @arg @ref LL_SPI_PHASE_1EDGE
+ * @arg @ref LL_SPI_PHASE_2EDGE
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
+}
+
+/**
+ * @brief Get clock phase
+ * @rmtoll CR1 CPHA LL_SPI_GetClockPhase
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_PHASE_1EDGE
+ * @arg @ref LL_SPI_PHASE_2EDGE
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
+}
+
+/**
+ * @brief Set clock polarity
+ * @note This bit should not be changed when communication is ongoing.
+ * This bit is not used in SPI TI mode.
+ * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
+ * @param SPIx SPI Instance
+ * @param ClockPolarity This parameter can be one of the following values:
+ * @arg @ref LL_SPI_POLARITY_LOW
+ * @arg @ref LL_SPI_POLARITY_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
+}
+
+/**
+ * @brief Get clock polarity
+ * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_POLARITY_LOW
+ * @arg @ref LL_SPI_POLARITY_HIGH
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
+}
+
+/**
+ * @brief Set baud rate prescaler
+ * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
+ * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
+ * @param SPIx SPI Instance
+ * @param BaudRate This parameter can be one of the following values:
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
+}
+
+/**
+ * @brief Get baud rate prescaler
+ * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
+}
+
+/**
+ * @brief Set transfer bit order
+ * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
+ * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
+ * @param SPIx SPI Instance
+ * @param BitOrder This parameter can be one of the following values:
+ * @arg @ref LL_SPI_LSB_FIRST
+ * @arg @ref LL_SPI_MSB_FIRST
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
+}
+
+/**
+ * @brief Get transfer bit order
+ * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_LSB_FIRST
+ * @arg @ref LL_SPI_MSB_FIRST
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
+}
+
+/**
+ * @brief Set transfer direction mode
+ * @note For Half-Duplex mode, Rx Direction is set by default.
+ * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
+ * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
+ * CR1 BIDIMODE LL_SPI_SetTransferDirection\n
+ * CR1 BIDIOE LL_SPI_SetTransferDirection
+ * @param SPIx SPI Instance
+ * @param TransferDirection This parameter can be one of the following values:
+ * @arg @ref LL_SPI_FULL_DUPLEX
+ * @arg @ref LL_SPI_SIMPLEX_RX
+ * @arg @ref LL_SPI_HALF_DUPLEX_RX
+ * @arg @ref LL_SPI_HALF_DUPLEX_TX
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
+}
+
+/**
+ * @brief Get transfer direction mode
+ * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
+ * CR1 BIDIMODE LL_SPI_GetTransferDirection\n
+ * CR1 BIDIOE LL_SPI_GetTransferDirection
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_FULL_DUPLEX
+ * @arg @ref LL_SPI_SIMPLEX_RX
+ * @arg @ref LL_SPI_HALF_DUPLEX_RX
+ * @arg @ref LL_SPI_HALF_DUPLEX_TX
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
+}
+
+/**
+ * @brief Set frame data width
+ * @rmtoll CR2 DS LL_SPI_SetDataWidth
+ * @param SPIx SPI Instance
+ * @param DataWidth This parameter can be one of the following values:
+ * @arg @ref LL_SPI_DATAWIDTH_4BIT
+ * @arg @ref LL_SPI_DATAWIDTH_5BIT
+ * @arg @ref LL_SPI_DATAWIDTH_6BIT
+ * @arg @ref LL_SPI_DATAWIDTH_7BIT
+ * @arg @ref LL_SPI_DATAWIDTH_8BIT
+ * @arg @ref LL_SPI_DATAWIDTH_9BIT
+ * @arg @ref LL_SPI_DATAWIDTH_10BIT
+ * @arg @ref LL_SPI_DATAWIDTH_11BIT
+ * @arg @ref LL_SPI_DATAWIDTH_12BIT
+ * @arg @ref LL_SPI_DATAWIDTH_13BIT
+ * @arg @ref LL_SPI_DATAWIDTH_14BIT
+ * @arg @ref LL_SPI_DATAWIDTH_15BIT
+ * @arg @ref LL_SPI_DATAWIDTH_16BIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
+{
+ MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth);
+}
+
+/**
+ * @brief Get frame data width
+ * @rmtoll CR2 DS LL_SPI_GetDataWidth
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_DATAWIDTH_4BIT
+ * @arg @ref LL_SPI_DATAWIDTH_5BIT
+ * @arg @ref LL_SPI_DATAWIDTH_6BIT
+ * @arg @ref LL_SPI_DATAWIDTH_7BIT
+ * @arg @ref LL_SPI_DATAWIDTH_8BIT
+ * @arg @ref LL_SPI_DATAWIDTH_9BIT
+ * @arg @ref LL_SPI_DATAWIDTH_10BIT
+ * @arg @ref LL_SPI_DATAWIDTH_11BIT
+ * @arg @ref LL_SPI_DATAWIDTH_12BIT
+ * @arg @ref LL_SPI_DATAWIDTH_13BIT
+ * @arg @ref LL_SPI_DATAWIDTH_14BIT
+ * @arg @ref LL_SPI_DATAWIDTH_15BIT
+ * @arg @ref LL_SPI_DATAWIDTH_16BIT
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS));
+}
+
+/**
+ * @brief Set threshold of RXFIFO that triggers an RXNE event
+ * @rmtoll CR2 FRXTH LL_SPI_SetRxFIFOThreshold
+ * @param SPIx SPI Instance
+ * @param Threshold This parameter can be one of the following values:
+ * @arg @ref LL_SPI_RX_FIFO_TH_HALF
+ * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
+{
+ MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold);
+}
+
+/**
+ * @brief Get threshold of RXFIFO that triggers an RXNE event
+ * @rmtoll CR2 FRXTH LL_SPI_GetRxFIFOThreshold
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_RX_FIFO_TH_HALF
+ * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EF_CRC_Management CRC Management
+ * @{
+ */
+
+/**
+ * @brief Enable CRC
+ * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+ * @rmtoll CR1 CRCEN LL_SPI_EnableCRC
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
+}
+
+/**
+ * @brief Disable CRC
+ * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+ * @rmtoll CR1 CRCEN LL_SPI_DisableCRC
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
+}
+
+/**
+ * @brief Check if CRC is enabled
+ * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+ * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN));
+}
+
+/**
+ * @brief Set CRC Length
+ * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+ * @rmtoll CR1 CRCL LL_SPI_SetCRCWidth
+ * @param SPIx SPI Instance
+ * @param CRCLength This parameter can be one of the following values:
+ * @arg @ref LL_SPI_CRC_8BIT
+ * @arg @ref LL_SPI_CRC_16BIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength);
+}
+
+/**
+ * @brief Get CRC Length
+ * @rmtoll CR1 CRCL LL_SPI_GetCRCWidth
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_CRC_8BIT
+ * @arg @ref LL_SPI_CRC_16BIT
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL));
+}
+
+/**
+ * @brief Set CRCNext to transfer CRC on the line
+ * @note This bit has to be written as soon as the last data is written in the SPIx_DR register.
+ * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
+}
+
+/**
+ * @brief Set polynomial for CRC calculation
+ * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
+ * @param SPIx SPI Instance
+ * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
+{
+ WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
+}
+
+/**
+ * @brief Get polynomial for CRC calculation
+ * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
+ * @param SPIx SPI Instance
+ * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_REG(SPIx->CRCPR));
+}
+
+/**
+ * @brief Get Rx CRC
+ * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
+ * @param SPIx SPI Instance
+ * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_REG(SPIx->RXCRCR));
+}
+
+/**
+ * @brief Get Tx CRC
+ * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
+ * @param SPIx SPI Instance
+ * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_REG(SPIx->TXCRCR));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
+ * @{
+ */
+
+/**
+ * @brief Set NSS mode
+ * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
+ * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
+ * @rmtoll CR2 SSOE LL_SPI_SetNSSMode
+ * @param SPIx SPI Instance
+ * @param NSS This parameter can be one of the following values:
+ * @arg @ref LL_SPI_NSS_SOFT
+ * @arg @ref LL_SPI_NSS_HARD_INPUT
+ * @arg @ref LL_SPI_NSS_HARD_OUTPUT
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
+ MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
+}
+
+/**
+ * @brief Get NSS mode
+ * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
+ * @rmtoll CR2 SSOE LL_SPI_GetNSSMode
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_NSS_SOFT
+ * @arg @ref LL_SPI_NSS_HARD_INPUT
+ * @arg @ref LL_SPI_NSS_HARD_OUTPUT
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
+{
+ register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
+ register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
+ return (Ssm | Ssoe);
+}
+
+/**
+ * @brief Enable NSS pulse management
+ * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
+ * @rmtoll CR2 NSSP LL_SPI_EnableNSSPulseMgt
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR2, SPI_CR2_NSSP);
+}
+
+/**
+ * @brief Disable NSS pulse management
+ * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
+ * @rmtoll CR2 NSSP LL_SPI_DisableNSSPulseMgt
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP);
+}
+
+/**
+ * @brief Check if NSS pulse is enabled
+ * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
+ * @rmtoll CR2 NSSP LL_SPI_IsEnabledNSSPulse
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
+ * @{
+ */
+
+/**
+ * @brief Check if Rx buffer is not empty
+ * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE));
+}
+
+/**
+ * @brief Check if Tx buffer is empty
+ * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE));
+}
+
+/**
+ * @brief Get CRC error flag
+ * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR));
+}
+
+/**
+ * @brief Get mode fault error flag
+ * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF));
+}
+
+/**
+ * @brief Get overrun error flag
+ * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR));
+}
+
+/**
+ * @brief Get busy flag
+ * @note The BSY flag is cleared under any one of the following conditions:
+ * -When the SPI is correctly disabled
+ * -When a fault is detected in Master mode (MODF bit set to 1)
+ * -In Master mode, when it finishes a data transmission and no new data is ready to be
+ * sent
+ * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
+ * each data transfer.
+ * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY));
+}
+
+/**
+ * @brief Get frame format error flag
+ * @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE));
+}
+
+/**
+ * @brief Get FIFO reception Level
+ * @rmtoll SR FRLVL LL_SPI_GetRxFIFOLevel
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_RX_FIFO_EMPTY
+ * @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL
+ * @arg @ref LL_SPI_RX_FIFO_HALF_FULL
+ * @arg @ref LL_SPI_RX_FIFO_FULL
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL));
+}
+
+/**
+ * @brief Get FIFO Transmission Level
+ * @rmtoll SR FTLVL LL_SPI_GetTxFIFOLevel
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_TX_FIFO_EMPTY
+ * @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL
+ * @arg @ref LL_SPI_TX_FIFO_HALF_FULL
+ * @arg @ref LL_SPI_TX_FIFO_FULL
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL));
+}
+
+/**
+ * @brief Clear CRC error flag
+ * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
+}
+
+/**
+ * @brief Clear mode fault error flag
+ * @note Clearing this flag is done by a read access to the SPIx_SR
+ * register followed by a write access to the SPIx_CR1 register
+ * @rmtoll SR MODF LL_SPI_ClearFlag_MODF
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
+{
+ __IO uint32_t tmpreg;
+ tmpreg = SPIx->SR;
+ (void) tmpreg;
+ tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
+ (void) tmpreg;
+}
+
+/**
+ * @brief Clear overrun error flag
+ * @note Clearing this flag is done by a read access to the SPIx_DR
+ * register followed by a read access to the SPIx_SR register
+ * @rmtoll SR OVR LL_SPI_ClearFlag_OVR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
+{
+ __IO uint32_t tmpreg;
+ tmpreg = SPIx->DR;
+ (void) tmpreg;
+ tmpreg = SPIx->SR;
+ (void) tmpreg;
+}
+
+/**
+ * @brief Clear frame format error flag
+ * @note Clearing this flag is done by reading SPIx_SR register
+ * @rmtoll SR FRE LL_SPI_ClearFlag_FRE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
+{
+ __IO uint32_t tmpreg;
+ tmpreg = SPIx->SR;
+ (void) tmpreg;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EF_IT_Management Interrupt Management
+ * @{
+ */
+
+/**
+ * @brief Enable error interrupt
+ * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
+ * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
+}
+
+/**
+ * @brief Enable Rx buffer not empty interrupt
+ * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
+}
+
+/**
+ * @brief Enable Tx buffer empty interrupt
+ * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
+}
+
+/**
+ * @brief Disable error interrupt
+ * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
+ * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
+}
+
+/**
+ * @brief Disable Rx buffer not empty interrupt
+ * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
+}
+
+/**
+ * @brief Disable Tx buffer empty interrupt
+ * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
+}
+
+/**
+ * @brief Check if error interrupt is enabled
+ * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE));
+}
+
+/**
+ * @brief Check if Rx buffer not empty interrupt is enabled
+ * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE));
+}
+
+/**
+ * @brief Check if Tx buffer empty interrupt
+ * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EF_DMA_Management DMA Management
+ * @{
+ */
+
+/**
+ * @brief Enable DMA Rx
+ * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
+}
+
+/**
+ * @brief Disable DMA Rx
+ * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
+}
+
+/**
+ * @brief Check if DMA Rx is enabled
+ * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN));
+}
+
+/**
+ * @brief Enable DMA Tx
+ * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
+}
+
+/**
+ * @brief Disable DMA Tx
+ * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
+}
+
+/**
+ * @brief Check if DMA Tx is enabled
+ * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN));
+}
+
+/**
+ * @brief Set parity of Last DMA reception
+ * @rmtoll CR2 LDMARX LL_SPI_SetDMAParity_RX
+ * @param SPIx SPI Instance
+ * @param Parity This parameter can be one of the following values:
+ * @arg @ref LL_SPI_DMA_PARITY_ODD
+ * @arg @ref LL_SPI_DMA_PARITY_EVEN
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity)
+{
+ MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << SPI_CR2_LDMARX_Pos));
+}
+
+/**
+ * @brief Get parity configuration for Last DMA reception
+ * @rmtoll CR2 LDMARX LL_SPI_GetDMAParity_RX
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_DMA_PARITY_ODD
+ * @arg @ref LL_SPI_DMA_PARITY_EVEN
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos);
+}
+
+/**
+ * @brief Set parity of Last DMA transmission
+ * @rmtoll CR2 LDMATX LL_SPI_SetDMAParity_TX
+ * @param SPIx SPI Instance
+ * @param Parity This parameter can be one of the following values:
+ * @arg @ref LL_SPI_DMA_PARITY_ODD
+ * @arg @ref LL_SPI_DMA_PARITY_EVEN
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity)
+{
+ MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << SPI_CR2_LDMATX_Pos));
+}
+
+/**
+ * @brief Get parity configuration for Last DMA transmission
+ * @rmtoll CR2 LDMATX LL_SPI_GetDMAParity_TX
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_DMA_PARITY_ODD
+ * @arg @ref LL_SPI_DMA_PARITY_EVEN
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos);
+}
+
+/**
+ * @brief Get the data register address used for DMA transfer
+ * @rmtoll DR DR LL_SPI_DMA_GetRegAddr
+ * @param SPIx SPI Instance
+ * @retval Address of data register
+ */
+__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
+{
+ return (uint32_t) & (SPIx->DR);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EF_DATA_Management DATA Management
+ * @{
+ */
+
+/**
+ * @brief Read 8-Bits in the data register
+ * @rmtoll DR DR LL_SPI_ReceiveData8
+ * @param SPIx SPI Instance
+ * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
+{
+ return (uint8_t)(READ_REG(SPIx->DR));
+}
+
+/**
+ * @brief Read 16-Bits in the data register
+ * @rmtoll DR DR LL_SPI_ReceiveData16
+ * @param SPIx SPI Instance
+ * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
+ */
+__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
+{
+ return (uint16_t)(READ_REG(SPIx->DR));
+}
+
+/**
+ * @brief Write 8-Bits in the data register
+ * @rmtoll DR DR LL_SPI_TransmitData8
+ * @param SPIx SPI Instance
+ * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
+{
+#if defined (__GNUC__)
+ __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR);
+ *spidr = TxData;
+#else
+ *((__IO uint8_t *)&SPIx->DR) = TxData;
+#endif
+}
+
+/**
+ * @brief Write 16-Bits in the data register
+ * @rmtoll DR DR LL_SPI_TransmitData16
+ * @param SPIx SPI Instance
+ * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
+{
+#if defined (__GNUC__)
+ __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR);
+ *spidr = TxData;
+#else
+ *((__IO uint16_t *)&SPIx->DR) = TxData;
+#endif
+}
+
+/**
+ * @}
+ */
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
+ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
+void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#if defined(SPI_I2S_SUPPORT)
+/** @defgroup I2S_LL I2S
+ * @{
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief I2S Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t Mode; /*!< Specifies the I2S operating mode.
+ This parameter can be a value of @ref I2S_LL_EC_MODE
+
+ This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
+
+ uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
+ This parameter can be a value of @ref I2S_LL_EC_STANDARD
+
+ This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
+
+
+ uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
+ This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
+
+ This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
+
+
+ uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
+ This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
+
+ This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
+
+
+ uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
+ This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
+
+ Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
+ and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
+
+
+ uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
+ This parameter can be a value of @ref I2S_LL_EC_POLARITY
+
+ This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
+
+} LL_I2S_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
+ * @{
+ */
+
+/** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_I2S_ReadReg function
+ * @{
+ */
+#define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /*!< Rx buffer not empty flag */
+#define LL_I2S_SR_TXE LL_SPI_SR_TXE /*!< Tx buffer empty flag */
+#define LL_I2S_SR_BSY LL_SPI_SR_BSY /*!< Busy flag */
+#define LL_I2S_SR_UDR SPI_SR_UDR /*!< Underrun flag */
+#define LL_I2S_SR_OVR LL_SPI_SR_OVR /*!< Overrun flag */
+#define LL_I2S_SR_FRE LL_SPI_SR_FRE /*!< TI mode frame format error flag */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
+ * @{
+ */
+#define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
+#define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
+#define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /*!< Error interrupt enable */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EC_DATA_FORMAT Data format
+ * @{
+ */
+#define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel lenght 16bit */
+#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel lenght 32bit */
+#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel lenght 32bit */
+#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel lenght 32bit */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EC_POLARITY Clock Polarity
+ * @{
+ */
+#define LL_I2S_POLARITY_LOW 0x00000000U /*!< Clock steady state is low level */
+#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /*!< Clock steady state is high level */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EC_STANDARD I2s Standard
+ * @{
+ */
+#define LL_I2S_STANDARD_PHILIPS 0x00000000U /*!< I2S standard philips */
+#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /*!< MSB justified standard (left justified) */
+#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /*!< LSB justified standard (right justified) */
+#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) /*!< PCM standard, short frame synchronization */
+#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EC_MODE Operation Mode
+ * @{
+ */
+#define LL_I2S_MODE_SLAVE_TX 0x00000000U /*!< Slave Tx configuration */
+#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /*!< Slave Rx configuration */
+#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /*!< Master Tx configuration */
+#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
+ * @{
+ */
+#define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /*!< Odd factor: Real divider value is = I2SDIV * 2 */
+#define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+
+/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
+ * @{
+ */
+#define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /*!< Master clock output is disabled */
+#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /*!< Master clock output is enabled */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
+ * @{
+ */
+
+#define LL_I2S_AUDIOFREQ_192K 192000U /*!< Audio Frequency configuration 192000 Hz */
+#define LL_I2S_AUDIOFREQ_96K 96000U /*!< Audio Frequency configuration 96000 Hz */
+#define LL_I2S_AUDIOFREQ_48K 48000U /*!< Audio Frequency configuration 48000 Hz */
+#define LL_I2S_AUDIOFREQ_44K 44100U /*!< Audio Frequency configuration 44100 Hz */
+#define LL_I2S_AUDIOFREQ_32K 32000U /*!< Audio Frequency configuration 32000 Hz */
+#define LL_I2S_AUDIOFREQ_22K 22050U /*!< Audio Frequency configuration 22050 Hz */
+#define LL_I2S_AUDIOFREQ_16K 16000U /*!< Audio Frequency configuration 16000 Hz */
+#define LL_I2S_AUDIOFREQ_11K 11025U /*!< Audio Frequency configuration 11025 Hz */
+#define LL_I2S_AUDIOFREQ_8K 8000U /*!< Audio Frequency configuration 8000 Hz */
+#define LL_I2S_AUDIOFREQ_DEFAULT 2U /*!< Audio Freq not specified. Register I2SDIV = 2 */
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
+ * @{
+ */
+
+/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in I2S register
+ * @param __INSTANCE__ I2S Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in I2S register
+ * @param __INSTANCE__ I2S Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
+ * @{
+ */
+
+/** @defgroup I2S_LL_EF_Configuration Configuration
+ * @{
+ */
+
+/**
+ * @brief Select I2S mode and Enable I2S peripheral
+ * @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
+ * I2SCFGR I2SE LL_I2S_Enable
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
+}
+
+/**
+ * @brief Disable I2S peripheral
+ * @rmtoll I2SCFGR I2SE LL_I2S_Disable
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
+}
+
+/**
+ * @brief Check if I2S peripheral is enabled
+ * @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE));
+}
+
+/**
+ * @brief Set I2S data frame length
+ * @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
+ * I2SCFGR CHLEN LL_I2S_SetDataFormat
+ * @param SPIx SPI Instance
+ * @param DataFormat This parameter can be one of the following values:
+ * @arg @ref LL_I2S_DATAFORMAT_16B
+ * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
+ * @arg @ref LL_I2S_DATAFORMAT_24B
+ * @arg @ref LL_I2S_DATAFORMAT_32B
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
+{
+ MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat);
+}
+
+/**
+ * @brief Get I2S data frame length
+ * @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
+ * I2SCFGR CHLEN LL_I2S_GetDataFormat
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2S_DATAFORMAT_16B
+ * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
+ * @arg @ref LL_I2S_DATAFORMAT_24B
+ * @arg @ref LL_I2S_DATAFORMAT_32B
+ */
+__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN));
+}
+
+/**
+ * @brief Set I2S clock polarity
+ * @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
+ * @param SPIx SPI Instance
+ * @param ClockPolarity This parameter can be one of the following values:
+ * @arg @ref LL_I2S_POLARITY_LOW
+ * @arg @ref LL_I2S_POLARITY_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
+{
+ SET_BIT(SPIx->I2SCFGR, ClockPolarity);
+}
+
+/**
+ * @brief Get I2S clock polarity
+ * @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2S_POLARITY_LOW
+ * @arg @ref LL_I2S_POLARITY_HIGH
+ */
+__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
+}
+
+/**
+ * @brief Set I2S standard protocol
+ * @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
+ * I2SCFGR PCMSYNC LL_I2S_SetStandard
+ * @param SPIx SPI Instance
+ * @param Standard This parameter can be one of the following values:
+ * @arg @ref LL_I2S_STANDARD_PHILIPS
+ * @arg @ref LL_I2S_STANDARD_MSB
+ * @arg @ref LL_I2S_STANDARD_LSB
+ * @arg @ref LL_I2S_STANDARD_PCM_SHORT
+ * @arg @ref LL_I2S_STANDARD_PCM_LONG
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
+{
+ MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
+}
+
+/**
+ * @brief Get I2S standard protocol
+ * @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
+ * I2SCFGR PCMSYNC LL_I2S_GetStandard
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2S_STANDARD_PHILIPS
+ * @arg @ref LL_I2S_STANDARD_MSB
+ * @arg @ref LL_I2S_STANDARD_LSB
+ * @arg @ref LL_I2S_STANDARD_PCM_SHORT
+ * @arg @ref LL_I2S_STANDARD_PCM_LONG
+ */
+__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
+}
+
+/**
+ * @brief Set I2S transfer mode
+ * @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
+ * @param SPIx SPI Instance
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_I2S_MODE_SLAVE_TX
+ * @arg @ref LL_I2S_MODE_SLAVE_RX
+ * @arg @ref LL_I2S_MODE_MASTER_TX
+ * @arg @ref LL_I2S_MODE_MASTER_RX
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
+{
+ MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
+}
+
+/**
+ * @brief Get I2S transfer mode
+ * @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2S_MODE_SLAVE_TX
+ * @arg @ref LL_I2S_MODE_SLAVE_RX
+ * @arg @ref LL_I2S_MODE_MASTER_TX
+ * @arg @ref LL_I2S_MODE_MASTER_RX
+ */
+__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
+}
+
+/**
+ * @brief Set I2S linear prescaler
+ * @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear
+ * @param SPIx SPI Instance
+ * @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
+{
+ MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
+}
+
+/**
+ * @brief Get I2S linear prescaler
+ * @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear
+ * @param SPIx SPI Instance
+ * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
+}
+
+/**
+ * @brief Set I2S parity prescaler
+ * @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity
+ * @param SPIx SPI Instance
+ * @param PrescalerParity This parameter can be one of the following values:
+ * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
+ * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
+{
+ MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
+}
+
+/**
+ * @brief Get I2S parity prescaler
+ * @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
+ * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
+ */
+__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
+}
+
+/**
+ * @brief Enable the master clock ouput (Pin MCK)
+ * @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
+}
+
+/**
+ * @brief Disable the master clock ouput (Pin MCK)
+ * @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
+}
+
+/**
+ * @brief Check if the master clock ouput (Pin MCK) is enabled
+ * @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EF_FLAG FLAG Management
+ * @{
+ */
+
+/**
+ * @brief Check if Rx buffer is not empty
+ * @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsActiveFlag_RXNE(SPIx);
+}
+
+/**
+ * @brief Check if Tx buffer is empty
+ * @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsActiveFlag_TXE(SPIx);
+}
+
+/**
+ * @brief Get busy flag
+ * @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsActiveFlag_BSY(SPIx);
+}
+
+/**
+ * @brief Get overrun error flag
+ * @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsActiveFlag_OVR(SPIx);
+}
+
+/**
+ * @brief Get underrun error flag
+ * @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR));
+}
+
+/**
+ * @brief Get frame format error flag
+ * @rmtoll SR FRE LL_I2S_IsActiveFlag_FRE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsActiveFlag_FRE(SPIx);
+}
+
+/**
+ * @brief Get channel side flag.
+ * @note 0: Channel Left has to be transmitted or has been received\n
+ * 1: Channel Right has to be transmitted or has been received\n
+ * It has no significance in PCM mode.
+ * @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE));
+}
+
+/**
+ * @brief Clear overrun error flag
+ * @rmtoll SR OVR LL_I2S_ClearFlag_OVR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
+{
+ LL_SPI_ClearFlag_OVR(SPIx);
+}
+
+/**
+ * @brief Clear underrun error flag
+ * @rmtoll SR UDR LL_I2S_ClearFlag_UDR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
+{
+ __IO uint32_t tmpreg;
+ tmpreg = SPIx->SR;
+ (void)tmpreg;
+}
+
+/**
+ * @brief Clear frame format error flag
+ * @rmtoll SR FRE LL_I2S_ClearFlag_FRE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
+{
+ LL_SPI_ClearFlag_FRE(SPIx);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EF_IT Interrupt Management
+ * @{
+ */
+
+/**
+ * @brief Enable error IT
+ * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
+ * @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
+{
+ LL_SPI_EnableIT_ERR(SPIx);
+}
+
+/**
+ * @brief Enable Rx buffer not empty IT
+ * @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
+{
+ LL_SPI_EnableIT_RXNE(SPIx);
+}
+
+/**
+ * @brief Enable Tx buffer empty IT
+ * @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
+{
+ LL_SPI_EnableIT_TXE(SPIx);
+}
+
+/**
+ * @brief Disable error IT
+ * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
+ * @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
+{
+ LL_SPI_DisableIT_ERR(SPIx);
+}
+
+/**
+ * @brief Disable Rx buffer not empty IT
+ * @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
+{
+ LL_SPI_DisableIT_RXNE(SPIx);
+}
+
+/**
+ * @brief Disable Tx buffer empty IT
+ * @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
+{
+ LL_SPI_DisableIT_TXE(SPIx);
+}
+
+/**
+ * @brief Check if ERR IT is enabled
+ * @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsEnabledIT_ERR(SPIx);
+}
+
+/**
+ * @brief Check if RXNE IT is enabled
+ * @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsEnabledIT_RXNE(SPIx);
+}
+
+/**
+ * @brief Check if TXE IT is enabled
+ * @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsEnabledIT_TXE(SPIx);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EF_DMA DMA Management
+ * @{
+ */
+
+/**
+ * @brief Enable DMA Rx
+ * @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
+{
+ LL_SPI_EnableDMAReq_RX(SPIx);
+}
+
+/**
+ * @brief Disable DMA Rx
+ * @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
+{
+ LL_SPI_DisableDMAReq_RX(SPIx);
+}
+
+/**
+ * @brief Check if DMA Rx is enabled
+ * @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsEnabledDMAReq_RX(SPIx);
+}
+
+/**
+ * @brief Enable DMA Tx
+ * @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
+{
+ LL_SPI_EnableDMAReq_TX(SPIx);
+}
+
+/**
+ * @brief Disable DMA Tx
+ * @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
+{
+ LL_SPI_DisableDMAReq_TX(SPIx);
+}
+
+/**
+ * @brief Check if DMA Tx is enabled
+ * @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsEnabledDMAReq_TX(SPIx);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EF_DATA DATA Management
+ * @{
+ */
+
+/**
+ * @brief Read 16-Bits in data register
+ * @rmtoll DR DR LL_I2S_ReceiveData16
+ * @param SPIx SPI Instance
+ * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
+ */
+__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_ReceiveData16(SPIx);
+}
+
+/**
+ * @brief Write 16-Bits in data register
+ * @rmtoll DR DR LL_I2S_TransmitData16
+ * @param SPIx SPI Instance
+ * @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
+{
+ LL_SPI_TransmitData16(SPIx, TxData);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
+ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
+void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
+void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
+#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
+ErrorStatus LL_I2S_InitFullDuplex(SPI_TypeDef *I2Sxext, LL_I2S_InitTypeDef *I2S_InitStruct);
+#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* SPI_I2S_SUPPORT */
+
+#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_LL_SPI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_ll_system.h b/Inc/stm32f3xx_ll_system.h
new file mode 100644
index 0000000..eaad3d3
--- /dev/null
+++ b/Inc/stm32f3xx_ll_system.h
@@ -0,0 +1,1740 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_system.h
+ * @author MCD Application Team
+ * @brief Header file of SYSTEM LL module.
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The LL SYSTEM driver contains a set of generic APIs that can be
+ used by user:
+ (+) Some of the FLASH features need to be handled in the SYSTEM file.
+ (+) Access to DBGCMU registers
+ (+) Access to SYSCFG registers
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_LL_SYSTEM_H
+#define __STM32F3xx_LL_SYSTEM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx.h"
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU)
+
+/** @defgroup SYSTEM_LL SYSTEM
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
+ * @{
+ */
+
+/* Offset used to access to SYSCFG_CFGR1 and SYSCFG_CFGR3 registers */
+#define SYSCFG_OFFSET_CFGR1 0x00000000U
+#define SYSCFG_OFFSET_CFGR3 0x00000050U
+
+/* Mask used for TIM breaks functions */
+#if defined(SYSCFG_CFGR2_PVD_LOCK) && defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
+#define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK | SYSCFG_CFGR2_PVD_LOCK)
+#elif defined(SYSCFG_CFGR2_PVD_LOCK) && !defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
+#define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_PVD_LOCK)
+#elif !defined(SYSCFG_CFGR2_PVD_LOCK) && defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
+#define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK)
+#else
+#define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK)
+#endif /* SYSCFG_CFGR2_PVD_LOCK && SYSCFG_CFGR2_SRAM_PARITY_LOCK */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
+ * @{
+ */
+
+/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
+ * @{
+ */
+#define LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000 /* Main Flash memory mapped at 0x00000000 */
+#define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0 /* System Flash memory mapped at 0x00000000 */
+#define LL_SYSCFG_REMAP_SRAM (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0) /* Embedded SRAM mapped at 0x00000000 */
+#if defined(FMC_BANK1)
+#define LL_SYSCFG_REMAP_FMC SYSCFG_CFGR1_MEM_MODE_2 /*<! FMC Bank (Only the first two banks) */
+#endif /* FMC_BANK1 */
+/**
+ * @}
+ */
+
+#if defined(SYSCFG_CFGR3_SPI1_RX_DMA_RMP)
+/** @defgroup SYSTEM_LL_EC_SPI1_DMA_RMP_RX SYSCFG SPI1 RX/TX DMA1 request REMAP
+ * @{
+ */
+#define LL_SYSCFG_SPI1RX_RMP_DMA1_CH2 (SYSCFG_CFGR3_SPI1_RX_DMA_RMP << 16U | (uint32_t)0x00000000U) /*!< SPI1_RX mapped on DMA1 CH2 */
+#define LL_SYSCFG_SPI1RX_RMP_DMA1_CH4 (SYSCFG_CFGR3_SPI1_RX_DMA_RMP << 16U | SYSCFG_CFGR3_SPI1_RX_DMA_RMP_0) /*!< SPI1_RX mapped on DMA1 CH4 */
+#define LL_SYSCFG_SPI1RX_RMP_DMA1_CH6 (SYSCFG_CFGR3_SPI1_RX_DMA_RMP << 16U | SYSCFG_CFGR3_SPI1_RX_DMA_RMP_1) /*!< SPI1_RX mapped on DMA1 CH6 */
+#define LL_SYSCFG_SPI1TX_RMP_DMA1_CH3 (SYSCFG_CFGR3_SPI1_TX_DMA_RMP << 16U | (uint32_t)0x00000000U) /*!< SPI1_TX mapped on DMA1 CH3 */
+#define LL_SYSCFG_SPI1TX_RMP_DMA1_CH5 (SYSCFG_CFGR3_SPI1_TX_DMA_RMP << 16U | SYSCFG_CFGR3_SPI1_TX_DMA_RMP_0) /*!< SPI1_TX mapped on DMA1 CH5 */
+#define LL_SYSCFG_SPI1TX_RMP_DMA1_CH7 (SYSCFG_CFGR3_SPI1_TX_DMA_RMP << 16U | SYSCFG_CFGR3_SPI1_TX_DMA_RMP_1) /*!< SPI1_TX mapped on DMA1 CH7 */
+/**
+ * @}
+ */
+#endif /* SYSCFG_CFGR3_SPI1_RX_DMA_RMP */
+
+#if defined(SYSCFG_CFGR3_I2C1_RX_DMA_RMP)
+/** @defgroup SYSTEM_LL_EC_I2C1_DMA_RMP_RX SYSCFG I2C1 RX/TX DMA1 request REMAP
+ * @{
+ */
+#define LL_SYSCFG_I2C1RX_RMP_DMA1_CH7 (SYSCFG_CFGR3_I2C1_RX_DMA_RMP << 16U | (uint32_t)0x00000000U) /*!< I2C1_RX mapped on DMA1 CH7 */
+#define LL_SYSCFG_I2C1RX_RMP_DMA1_CH3 (SYSCFG_CFGR3_I2C1_RX_DMA_RMP << 16U | SYSCFG_CFGR3_I2C1_RX_DMA_RMP_0) /*!< I2C1_RX mapped on DMA1 CH3 */
+#define LL_SYSCFG_I2C1RX_RMP_DMA1_CH5 (SYSCFG_CFGR3_I2C1_RX_DMA_RMP << 16U | SYSCFG_CFGR3_I2C1_RX_DMA_RMP_1) /*!< I2C1_RX mapped on DMA1 CH5 */
+#define LL_SYSCFG_I2C1TX_RMP_DMA1_CH6 (SYSCFG_CFGR3_I2C1_TX_DMA_RMP << 16U | (uint32_t)0x00000000U) /*!< I2C1_TX mapped on DMA1 CH6 */
+#define LL_SYSCFG_I2C1TX_RMP_DMA1_CH2 (SYSCFG_CFGR3_I2C1_TX_DMA_RMP << 16U | SYSCFG_CFGR3_I2C1_TX_DMA_RMP_0) /*!< I2C1_TX mapped on DMA1 CH2 */
+#define LL_SYSCFG_I2C1TX_RMP_DMA1_CH4 (SYSCFG_CFGR3_I2C1_TX_DMA_RMP << 16U | SYSCFG_CFGR3_I2C1_TX_DMA_RMP_1) /*!< I2C1_TX mapped on DMA1 CH4 */
+/**
+ * @}
+ */
+
+#endif /* SYSCFG_CFGR3_I2C1_RX_DMA_RMP */
+
+#if defined(SYSCFG_CFGR1_ADC24_DMA_RMP) || defined(SYSCFG_CFGR3_ADC2_DMA_RMP)
+/** @defgroup SYSTEM_LL_EC_ADC24_DMA_REMAP SYSCFG ADC DMA request REMAP
+ * @{
+ */
+#if defined (SYSCFG_CFGR1_ADC24_DMA_RMP)
+#define LL_SYSCFG_ADC24_RMP_DMA2_CH12 (SYSCFG_OFFSET_CFGR1 << 24U | SYSCFG_CFGR1_ADC24_DMA_RMP << 8U | (uint32_t)0x00000000U) /*!< ADC24 DMA requests mapped on DMA2 channels 1 and 2 */
+#define LL_SYSCFG_ADC24_RMP_DMA2_CH34 (SYSCFG_OFFSET_CFGR1 << 24U | SYSCFG_CFGR1_ADC24_DMA_RMP << 8U | SYSCFG_CFGR1_ADC24_DMA_RMP) /*!< ADC24 DMA requests mapped on DMA2 channels 3 and 4 */
+#endif /*SYSCFG_CFGR1_ADC24_DMA_RMP*/
+#if defined (SYSCFG_CFGR3_ADC2_DMA_RMP)
+#define LL_SYSCFG_ADC2_RMP_DMA1_CH2 (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_ADC2_DMA_RMP_0 << 8U | (uint32_t)0x00000000U) /*!< ADC2 mapped on DMA1 channel 2 */
+#define LL_SYSCFG_ADC2_RMP_DMA1_CH4 (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_ADC2_DMA_RMP_0 << 8U | SYSCFG_CFGR3_ADC2_DMA_RMP_0) /*!< ADC2 mapped on DMA1 channel 4 */
+#define LL_SYSCFG_ADC2_RMP_DMA2 (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_ADC2_DMA_RMP_1 << 8U | (uint32_t)0x00000000U) /*!< ADC2 mapped on DMA2 */
+#define LL_SYSCFG_ADC2_RMP_DMA1 (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_ADC2_DMA_RMP_1 << 8U | SYSCFG_CFGR3_ADC2_DMA_RMP_1) /*!< ADC2 mapped on DMA1 */
+#endif /*SYSCFG_CFGR3_ADC2_DMA_RMP*/
+/**
+ * @}
+ */
+
+#endif /* SYSCFG_CFGR1_ADC24_DMA_RMP || SYSCFG_CFGR3_ADC2_DMA_RMP */
+
+/** @defgroup SYSTEM_LL_EC_DAC1_DMA2_REMAP SYSCFG DAC1/2 DMA1/2 request REMAP
+ * @{
+ */
+#define LL_SYSCFG_DAC1_CH1_RMP_DMA2_CH3 ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< DAC_CH1 DMA requests mapped on DMA2 channel 3 */
+#define LL_SYSCFG_DAC1_CH1_RMP_DMA1_CH3 ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP) /*!< DAC_CH1 DMA requests mapped on DMA1 channel 3 */
+#if defined(SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP)
+#define LL_SYSCFG_DAC1_OUT2_RMP_DMA2_CH4 ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< DAC1_OUT2 DMA requests mapped on DMA2 channel 4 */
+#define LL_SYSCFG_DAC1_OUT2_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP) /*!< DAC1_OUT2 DMA requests mapped on DMA1 channel 4 */
+#endif /*SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP*/
+#if defined(SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP)
+#define LL_SYSCFG_DAC2_OUT1_RMP_DMA2_CH5 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< DAC2_OUT1 DMA requests mapped on DMA2 channel 5 */
+#define LL_SYSCFG_DAC2_OUT1_RMP_DMA1_CH5 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP) /*!< DAC2_OUT1 DMA requests mapped on DMA1 channel 5 */
+#endif /*SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP*/
+#if defined(SYSCFG_CFGR1_DAC2Ch1_DMA_RMP)
+#define LL_SYSCFG_DAC2_CH1_RMP_NO ((SYSCFG_CFGR1_DAC2Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< No remap */
+#define LL_SYSCFG_DAC2_CH1_RMP_DMA1_CH5 ((SYSCFG_CFGR1_DAC2Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_DAC2Ch1_DMA_RMP) /*!< DAC2_CH1 DMA requests mapped on DMA1 channel 5 */
+#endif /*SYSCFG_CFGR1_DAC2Ch1_DMA_RMP*/
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_TIM16_DMA1_REMAP SYSCFG TIM DMA request REMAP
+ * @{
+ */
+#define LL_SYSCFG_TIM16_RMP_DMA1_CH3 ((SYSCFG_CFGR1_TIM16_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA1 channel 3 */
+#define LL_SYSCFG_TIM16_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM16_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM16_DMA_RMP) /*!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA1 channel 6 */
+#define LL_SYSCFG_TIM17_RMP_DMA1_CH1 ((SYSCFG_CFGR1_TIM17_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA1 channel 1 */
+#define LL_SYSCFG_TIM17_RMP_DMA1_CH7 ((SYSCFG_CFGR1_TIM17_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM17_DMA_RMP) /*!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA1 channel 7 */
+#define LL_SYSCFG_TIM6_RMP_DMA2_CH3 ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< TIM6 DMA requests mapped on DMA2 channel 3 */
+#define LL_SYSCFG_TIM6_RMP_DMA1_CH3 ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP) /*!< TIM6 DMA requests mapped on DMA1 channel 3 */
+#if defined(SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP)
+#define LL_SYSCFG_TIM7_RMP_DMA2_CH4 ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< TIM7 DMA requests mapped on DMA2 channel 4 */
+#define LL_SYSCFG_TIM7_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP) /*!< TIM7 DMA requests mapped on DMA1 channel 4 */
+#endif /*SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP*/
+#if defined(SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP)
+#define LL_SYSCFG_TIM18_RMP_DMA2_CH5 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< TIM18 DMA requests mapped on DMA2 channel 5 */
+#define LL_SYSCFG_TIM18_RMP_DMA1_CH5 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP) /*!< TIM18 DMA requests mapped on DMA1 channel 5 */
+#endif /*SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP*/
+/**
+ * @}
+ */
+
+#if defined(SYSCFG_CFGR1_TIM1_ITR3_RMP) || defined(SYSCFG_CFGR1_ENCODER_MODE)
+/** @defgroup SYSTEM_LL_EC_TIM1_ITR3_RMP_TIM4 SYSCFG TIM REMAP
+ * @{
+ */
+#if defined(SYSCFG_CFGR1_TIM1_ITR3_RMP)
+#define LL_SYSCFG_TIM1_ITR3_RMP_TIM4_TRGO ((SYSCFG_CFGR1_TIM1_ITR3_RMP << 8U) | (uint32_t)0x00000000U) /*!< TIM1_ITR3 = TIM4_TRGO */
+#define LL_SYSCFG_TIM1_ITR3_RMP_TIM17_OC ((SYSCFG_CFGR1_TIM1_ITR3_RMP << 8U) | SYSCFG_CFGR1_TIM1_ITR3_RMP) /*!< TIM1_ITR3 = TIM17_OC */
+#endif /* SYSCFG_CFGR1_TIM1_ITR3_RMP */
+#if defined(SYSCFG_CFGR1_ENCODER_MODE)
+#define LL_SYSCFG_TIM15_ENCODEMODE_NOREDIRECTION ((SYSCFG_CFGR1_ENCODER_MODE << 8U) | (uint32_t)0x00000000U) /*!< No redirection */
+#define LL_SYSCFG_TIM15_ENCODEMODE_TIM2 ((SYSCFG_CFGR1_ENCODER_MODE_0 << 8U) | SYSCFG_CFGR1_ENCODER_MODE_0) /*!< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
+#if defined(SYSCFG_CFGR1_ENCODER_MODE_TIM3)
+#define LL_SYSCFG_TIM15_ENCODEMODE_TIM3 ((SYSCFG_CFGR1_ENCODER_MODE_TIM3 << 8U) | SYSCFG_CFGR1_ENCODER_MODE_TIM3) /*!< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
+#endif /* SYSCFG_CFGR1_ENCODER_MODE_TIM3 */
+#if defined(SYSCFG_CFGR1_ENCODER_MODE_TIM4)
+#define LL_SYSCFG_TIM15_ENCODEMODE_TIM4 ((SYSCFG_CFGR1_ENCODER_MODE_TIM4 << 8U) | SYSCFG_CFGR1_ENCODER_MODE_TIM4) /*!< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
+#endif /* SYSCFG_CFGR1_ENCODER_MODE_TIM4 */
+#endif /* SYSCFG_CFGR1_ENCODER_MODE */
+/**
+ * @}
+ */
+
+#endif /* SYSCFG_CFGR1_TIM1_ITR3_RMP || SYSCFG_CFGR1_ENCODER_MODE */
+
+#if defined(SYSCFG_CFGR4_ADC12_EXT2_RMP)
+/** @defgroup SYSTEM_LL_EC_ADC12_EXT2_RMP_TIM1 SYSCFG ADC Trigger REMAP
+ * @{
+ */
+#define LL_SYSCFG_ADC12_EXT2_RMP_TIM1_CC3 ((SYSCFG_CFGR4_ADC12_EXT2_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC12 regular channel EXT2:Trigger source is TIM1_CC3 */
+#define LL_SYSCFG_ADC12_EXT2_RMP_TIM20_TRGO ((SYSCFG_CFGR4_ADC12_EXT2_RMP << 16U) | SYSCFG_CFGR4_ADC12_EXT2_RMP) /*!< Input trigger of ADC12 regular channel EXT2:Trigger source is TIM20_TRGO */
+#define LL_SYSCFG_ADC12_EXT3_RMP_TIM2_CC2 ((SYSCFG_CFGR4_ADC12_EXT3_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC12 regular channel EXT3:Trigger source is TIM2_CC2 */
+#define LL_SYSCFG_ADC12_EXT3_RMP_TIM20_TRGO2 ((SYSCFG_CFGR4_ADC12_EXT3_RMP << 16U) | SYSCFG_CFGR4_ADC12_EXT3_RMP) /*!< Input trigger of ADC12 regular channel EXT3:Trigger source is TIM20_TRGO2 */
+#define LL_SYSCFG_ADC12_EXT5_RMP_TIM4_CC4 ((SYSCFG_CFGR4_ADC12_EXT5_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC12 regular channel EXT5:Trigger source is TIM4_CC4 */
+#define LL_SYSCFG_ADC12_EXT5_RMP_TIM20_CC1 ((SYSCFG_CFGR4_ADC12_EXT5_RMP << 16U) | SYSCFG_CFGR4_ADC12_EXT5_RMP) /*!< Input trigger of ADC12 regular channel EXT5:Trigger source is TIM20_CC1 */
+#define LL_SYSCFG_ADC12_EXT13_RMP_TIM6_TRGO ((SYSCFG_CFGR4_ADC12_EXT13_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC12 regular channel EXT13:Trigger source is TIM6_TRGO */
+#define LL_SYSCFG_ADC12_EXT13_RMP_TIM20_CC2 ((SYSCFG_CFGR4_ADC12_EXT13_RMP << 16U) | SYSCFG_CFGR4_ADC12_EXT13_RMP) /*!< Input trigger of ADC12 regular channel EXT13:Trigger source is TIM20_CC2 */
+#define LL_SYSCFG_ADC12_EXT15_RMP_TIM3_CC4 ((SYSCFG_CFGR4_ADC12_EXT15_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC12 regular channel EXT15:Trigger source is TIM3_CC4 */
+#define LL_SYSCFG_ADC12_EXT15_RMP_TIM20_CC3 ((SYSCFG_CFGR4_ADC12_EXT15_RMP << 16U) | SYSCFG_CFGR4_ADC12_EXT15_RMP) /*!< Input trigger of ADC12 regular channel EXT15:Trigger source is TIM20_CC3 */
+#define LL_SYSCFG_ADC12_JEXT3_RMP_TIM2_CC1 ((SYSCFG_CFGR4_ADC12_JEXT3_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC12 regular channel JEXT3:Trigger source is TIM2_CC1 */
+#define LL_SYSCFG_ADC12_JEXT3_RMP_TIM20_TRGO ((SYSCFG_CFGR4_ADC12_JEXT3_RMP << 16U) | SYSCFG_CFGR4_ADC12_JEXT3_RMP) /*!< Input trigger of ADC12 regular channel JEXT3:Trigger source is TIM20_TRGO */
+#define LL_SYSCFG_ADC12_JEXT6_RMP_EXTI_LINE_15 ((SYSCFG_CFGR4_ADC12_JEXT6_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC12 regular channel JEXT6:Trigger source is EXTI_LINE_15 */
+#define LL_SYSCFG_ADC12_JEXT6_RMP_TIM20_TRGO2 ((SYSCFG_CFGR4_ADC12_JEXT6_RMP << 16U) | SYSCFG_CFGR4_ADC12_JEXT6_RMP) /*!< Input trigger of ADC12 regular channel JEXT6:Trigger source is TIM20_TRGO2 */
+#define LL_SYSCFG_ADC12_JEXT13_RMP_TIM3_CC1 ((SYSCFG_CFGR4_ADC12_JEXT13_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC12 regular channel JEXT13:Trigger source is TIM3_CC1 */
+#define LL_SYSCFG_ADC12_JEXT13_RMP_TIM20_CC4 ((SYSCFG_CFGR4_ADC12_JEXT13_RMP << 16U) | SYSCFG_CFGR4_ADC12_JEXT13_RMP) /*!< Input trigger of ADC12 regular channel JEXT13:Trigger source is TIM20_CC4 */
+#define LL_SYSCFG_ADC34_EXT5_RMP_EXTI_LINE_2 ((SYSCFG_CFGR4_ADC34_EXT5_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC34 regular channel EXT5:Trigger source is EXTI_LINE_2 */
+#define LL_SYSCFG_ADC34_EXT5_RMP_TIM20_TRGO ((SYSCFG_CFGR4_ADC34_EXT5_RMP << 16U) | SYSCFG_CFGR4_ADC34_EXT5_RMP) /*!< Input trigger of ADC34 regular channel EXT5:Trigger source is TIM20_TRGO */
+#define LL_SYSCFG_ADC34_EXT6_RMP_TIM4_CC1 ((SYSCFG_CFGR4_ADC34_EXT6_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC34 regular channel EXT6:Trigger source is TIM4_CC1 */
+#define LL_SYSCFG_ADC34_EXT6_RMP_TIM20_TRGO2 ((SYSCFG_CFGR4_ADC34_EXT6_RMP << 16U) | SYSCFG_CFGR4_ADC34_EXT6_RMP) /*!< Input trigger of ADC34 regular channel EXT6:Trigger source is TIM20_TRGO2 */
+#define LL_SYSCFG_ADC34_EXT15_RMP_TIM2_CC1 ((SYSCFG_CFGR4_ADC34_EXT15_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC34 regular channel EXT15:Trigger source is TIM2_CC1 */
+#define LL_SYSCFG_ADC34_EXT15_RMP_TIM20_CC1 ((SYSCFG_CFGR4_ADC34_EXT15_RMP << 16U) | SYSCFG_CFGR4_ADC34_EXT15_RMP) /*!< Input trigger of ADC34 regular channel EXT15:Trigger source is TIM20_CC1 */
+#define LL_SYSCFG_ADC34_JEXT5_RMP_TIM4_CC3 ((SYSCFG_CFGR4_ADC34_JEXT5_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC34 regular channel JEXT5:Trigger source is TIM4_CC3 */
+#define LL_SYSCFG_ADC34_JEXT5_RMP_TIM20_TRGO ((SYSCFG_CFGR4_ADC34_JEXT5_RMP << 16U) | SYSCFG_CFGR4_ADC34_JEXT5_RMP) /*!< Input trigger of ADC34 regular channel JEXT5:Trigger source is TIM20_TRGO */
+#define LL_SYSCFG_ADC34_JEXT11_RMP_TIM1_CC3 ((SYSCFG_CFGR4_ADC34_JEXT11_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC34 regular channel JEXT11:Trigger source is TIM1_CC3 */
+#define LL_SYSCFG_ADC34_JEXT11_RMP_TIM20_TRGO2 ((SYSCFG_CFGR4_ADC34_JEXT11_RMP << 16U) | SYSCFG_CFGR4_ADC34_JEXT11_RMP) /*!< Input trigger of ADC34 regular channel JEXT11:Trigger source is TIM20_TRGO2 */
+#define LL_SYSCFG_ADC34_JEXT14_RMP_TIM7_TRGO ((SYSCFG_CFGR4_ADC34_JEXT14_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC34 regular channel JEXT14:Trigger source is TIM7_TRGO */
+#define LL_SYSCFG_ADC34_JEXT14_RMP_TIM20_CC2 ((SYSCFG_CFGR4_ADC34_JEXT14_RMP << 16U) | SYSCFG_CFGR4_ADC34_JEXT14_RMP) /*!< Input trigger of ADC34 regular channel JEXT14:Trigger source is TIM20_CC2 */
+/**
+ * @}
+ */
+
+#endif /* SYSCFG_CFGR4_ADC12_EXT2_RMP */
+
+#if defined(SYSCFG_CFGR1_DAC1_TRIG1_RMP) || defined(SYSCFG_CFGR3_TRIGGER_RMP)
+/** @defgroup SYSTEM_LL_EC_DAC1_TRIG1_REMAP SYSCFG DAC1 Trigger REMAP
+ * @{
+ */
+#if defined(SYSCFG_CFGR1_DAC1_TRIG1_RMP)
+#define LL_SYSCFG_DAC1_TRIG1_RMP_TIM8_TRGO (SYSCFG_OFFSET_CFGR1 << 24U | SYSCFG_CFGR1_DAC1_TRIG1_RMP << 4 | (uint32_t)0x00000000U) /*!< No remap: DAC trigger TRIG1 is TIM8_TRGO */
+#define LL_SYSCFG_DAC1_TRIG1_RMP_TIM3_TRGO (SYSCFG_OFFSET_CFGR1 << 24U | SYSCFG_CFGR1_DAC1_TRIG1_RMP << 4 | SYSCFG_CFGR1_DAC1_TRIG1_RMP) /*!< DAC trigger is TIM3_TRGO */
+#endif /* SYSCFG_CFGR1_DAC1_TRIG1_RMP */
+#if defined(SYSCFG_CFGR3_DAC1_TRG3_RMP)
+#define LL_SYSCFG_DAC1_TRIG3_RMP_TIM15_TRGO (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_DAC1_TRG3_RMP << 4 | (uint32_t)0x00000000U) /*!< DAC trigger is TIM15_TRGO */
+#define LL_SYSCFG_DAC1_TRIG3_RMP_HRTIM1_DAC1_TRIG1 (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_DAC1_TRG3_RMP << 4 | SYSCFG_CFGR3_DAC1_TRG3_RMP) /*!< DAC trigger is HRTIM1_DAC1_TRIG1 */
+#endif /* SYSCFG_CFGR3_DAC1_TRG3_RMP */
+#if defined(SYSCFG_CFGR3_DAC1_TRG5_RMP)
+#define LL_SYSCFG_DAC1_TRIG5_RMP_NO (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_DAC1_TRG5_RMP << 4 | (uint32_t)0x00000000U) /*!< No remap */
+#define LL_SYSCFG_DAC1_TRIG5_RMP_HRTIM1_DAC1_TRIG2 (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_DAC1_TRG5_RMP << 4 | SYSCFG_CFGR3_DAC1_TRG5_RMP) /*!< DAC trigger is HRTIM1_DAC1_TRIG2 */
+#endif /* SYSCFG_CFGR3_DAC1_TRG5_RMP */
+/**
+ * @}
+ */
+
+#endif /* SYSCFG_CFGR1_DAC1_TRIG1_RMP || SYSCFG_CFGR3_TRIGGER_RMP */
+
+/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
+ * @{
+ */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< I2C PB6 Fast mode plus */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< I2C PB7 Fast mode plus */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< I2C PB8 Fast mode plus */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< I2C PB9 Fast mode plus */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< I2C1 Fast mode plus */
+#if defined(SYSCFG_CFGR1_I2C2_FMP)
+#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< I2C2 Fast mode plus */
+#endif /*SYSCFG_CFGR1_I2C2_FMP*/
+#if defined(SYSCFG_CFGR1_I2C3_FMP)
+#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< I2C3 Fast mode plus */
+#endif /*SYSCFG_CFGR1_I2C3_FMP*/
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
+ * @{
+ */
+#define LL_SYSCFG_EXTI_PORTA (uint32_t)0U /*!< EXTI PORT A */
+#define LL_SYSCFG_EXTI_PORTB (uint32_t)1U /*!< EXTI PORT B */
+#define LL_SYSCFG_EXTI_PORTC (uint32_t)2U /*!< EXTI PORT C */
+#define LL_SYSCFG_EXTI_PORTD (uint32_t)3U /*!< EXTI PORT D */
+#if defined(GPIOE)
+#define LL_SYSCFG_EXTI_PORTE (uint32_t)4U /*!< EXTI PORT E */
+#endif /* GPIOE */
+#define LL_SYSCFG_EXTI_PORTF (uint32_t)5U /*!< EXTI PORT F */
+#if defined(GPIOG)
+#define LL_SYSCFG_EXTI_PORTG (uint32_t)6U /*!< EXTI PORT G */
+#endif /* GPIOG */
+#if defined(GPIOH)
+#define LL_SYSCFG_EXTI_PORTH (uint32_t)7U /*!< EXTI PORT H */
+#endif /* GPIOH */
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
+ * @{
+ */
+#define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0x000FU << 16U | 0U) /* EXTI_POSITION_0 | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE1 (uint32_t)(0x00F0U << 16U | 0U) /* EXTI_POSITION_4 | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE2 (uint32_t)(0x0F00U << 16U | 0U) /* EXTI_POSITION_8 | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE3 (uint32_t)(0xF000U << 16U | 0U) /* EXTI_POSITION_12 | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0x000FU << 16U | 1U) /* EXTI_POSITION_0 | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE5 (uint32_t)(0x00F0U << 16U | 1U) /* EXTI_POSITION_4 | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE6 (uint32_t)(0x0F00U << 16U | 1U) /* EXTI_POSITION_8 | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE7 (uint32_t)(0xF000U << 16U | 1U) /* EXTI_POSITION_12 | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0x000FU << 16U | 2U) /* EXTI_POSITION_0 | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE9 (uint32_t)(0x00F0U << 16U | 2U) /* EXTI_POSITION_4 | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE10 (uint32_t)(0x0F00U << 16U | 2U) /* EXTI_POSITION_8 | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE11 (uint32_t)(0xF000U << 16U | 2U) /* EXTI_POSITION_12 | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0x000FU << 16U | 3U) /* EXTI_POSITION_0 | EXTICR[3] */
+#define LL_SYSCFG_EXTI_LINE13 (uint32_t)(0x00F0U << 16U | 3U) /* EXTI_POSITION_4 | EXTICR[3] */
+#define LL_SYSCFG_EXTI_LINE14 (uint32_t)(0x0F00U << 16U | 3U) /* EXTI_POSITION_8 | EXTICR[3] */
+#define LL_SYSCFG_EXTI_LINE15 (uint32_t)(0xF000U << 16U | 3U) /* EXTI_POSITION_12 | EXTICR[3] */
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
+ * @{
+ */
+#if defined(SYSCFG_CFGR2_PVD_LOCK)
+#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Enables and locks the PVD connection with TIMx Break Input and also the PVDE and PLS bits of the Power Control Interface */
+#endif /*SYSCFG_CFGR2_PVD_LOCK*/
+#if defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
+#define LL_SYSCFG_TIMBREAK_SRAM_PARITY SYSCFG_CFGR2_SRAM_PARITY_LOCK /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMx */
+#endif /* SYSCFG_CFGR2_SRAM_PARITY_LOCK */
+#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_LOCKUP_LOCK /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMx */
+/**
+ * @}
+ */
+
+#if defined(SYSCFG_RCR_PAGE0)
+/** @defgroup SYSTEM_LL_EC_CCMSRAMWRP SYSCFG CCM SRAM WRP
+ * @{
+ */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE0 SYSCFG_RCR_PAGE0 /*!< ICODE SRAM Write protection page 0 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE1 SYSCFG_RCR_PAGE1 /*!< ICODE SRAM Write protection page 1 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE2 SYSCFG_RCR_PAGE2 /*!< ICODE SRAM Write protection page 2 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE3 SYSCFG_RCR_PAGE3 /*!< ICODE SRAM Write protection page 3 */
+#if defined(SYSCFG_RCR_PAGE4)
+#define LL_SYSCFG_CCMSRAMWRP_PAGE4 SYSCFG_RCR_PAGE4 /*!< ICODE SRAM Write protection page 4 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE5 SYSCFG_RCR_PAGE5 /*!< ICODE SRAM Write protection page 5 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE6 SYSCFG_RCR_PAGE6 /*!< ICODE SRAM Write protection page 6 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE7 SYSCFG_RCR_PAGE7 /*!< ICODE SRAM Write protection page 7 */
+#endif
+#if defined(SYSCFG_RCR_PAGE8)
+#define LL_SYSCFG_CCMSRAMWRP_PAGE8 SYSCFG_RCR_PAGE8 /*!< ICODE SRAM Write protection page 8 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE9 SYSCFG_RCR_PAGE9 /*!< ICODE SRAM Write protection page 9 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE10 SYSCFG_RCR_PAGE10 /*!< ICODE SRAM Write protection page 10 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE11 SYSCFG_RCR_PAGE11 /*!< ICODE SRAM Write protection page 11 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE12 SYSCFG_RCR_PAGE12 /*!< ICODE SRAM Write protection page 12 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE13 SYSCFG_RCR_PAGE13 /*!< ICODE SRAM Write protection page 13 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE14 SYSCFG_RCR_PAGE14 /*!< ICODE SRAM Write protection page 14 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE15 SYSCFG_RCR_PAGE15 /*!< ICODE SRAM Write protection page 15 */
+#endif
+/**
+ * @}
+ */
+
+#endif /* SYSCFG_RCR_PAGE0 */
+
+/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
+ * @{
+ */
+#define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */
+#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */
+#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
+#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
+#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
+ * @{
+ */
+#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */
+#if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */
+#endif /*DBGMCU_APB1_FZ_DBG_TIM3_STOP*/
+#if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP /*!< TIM4 counter stopped when core is halted */
+#endif /*DBGMCU_APB1_FZ_DBG_TIM4_STOP*/
+#if defined(DBGMCU_APB1_FZ_DBG_TIM5_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP /*!< TIM5 counter stopped when core is halted */
+#endif /*DBGMCU_APB1_FZ_DBG_TIM5_STOP*/
+#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */
+#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */
+#endif /*DBGMCU_APB1_FZ_DBG_TIM7_STOP*/
+#if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP /*!< TIM12 counter stopped when core is halted */
+#endif /*DBGMCU_APB1_FZ_DBG_TIM12_STOP*/
+#if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP /*!< TIM13 counter stopped when core is halted */
+#endif /*DBGMCU_APB1_FZ_DBG_TIM13_STOP*/
+#if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */
+#endif /*DBGMCU_APB1_FZ_DBG_TIM14_STOP*/
+#if defined(DBGMCU_APB1_FZ_DBG_TIM18_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM18_STOP DBGMCU_APB1_FZ_DBG_TIM18_STOP /*!< TIM18 counter stopped when core is halted */
+#endif /*DBGMCU_APB1_FZ_DBG_TIM18_STOP*/
+#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP /*!< RTC counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */
+#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */
+#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+#if defined(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
+#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
+#endif /*DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT*/
+#if defined(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)
+#define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
+#endif /*DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT*/
+#if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP)
+#define LL_DBGMCU_APB1_GRP1_CAN_STOP DBGMCU_APB1_FZ_DBG_CAN_STOP /*!< CAN debug stopped when Core is halted */
+#endif /*DBGMCU_APB1_FZ_DBG_CAN_STOP*/
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
+ * @{
+ */
+#if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP)
+#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */
+#endif /*DBGMCU_APB2_FZ_DBG_TIM1_STOP*/
+#if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP)
+#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP /*!< TIM8 counter stopped when core is halted */
+#endif /*DBGMCU_APB2_FZ_DBG_TIM8_STOP*/
+#define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP /*!< TIM15 counter stopped when core is halted */
+#define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP /*!< TIM16 counter stopped when core is halted */
+#define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP /*!< TIM17 counter stopped when core is halted */
+#if defined(DBGMCU_APB2_FZ_DBG_TIM19_STOP)
+#define LL_DBGMCU_APB2_GRP1_TIM19_STOP DBGMCU_APB2_FZ_DBG_TIM19_STOP /*!< TIM19 counter stopped when core is halted */
+#endif /*DBGMCU_APB2_FZ_DBG_TIM19_STOP*/
+#if defined(DBGMCU_APB2_FZ_DBG_TIM20_STOP)
+#define LL_DBGMCU_APB2_GRP1_TIM20_STOP DBGMCU_APB2_FZ_DBG_TIM20_STOP /*!< TIM20 counter stopped when core is halted */
+#endif /*DBGMCU_APB2_FZ_DBG_TIM20_STOP*/
+#if defined(DBGMCU_APB2_FZ_DBG_HRTIM1_STOP)
+#define LL_DBGMCU_APB2_GRP1_HRTIM1_STOP DBGMCU_APB2_FZ_DBG_HRTIM1_STOP /*!< HRTIM1 counter stopped when core is halted */
+#endif /*DBGMCU_APB2_FZ_DBG_HRTIM1_STOP*/
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
+ * @{
+ */
+#define LL_FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */
+#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */
+#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two Latency cycles */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
+ * @{
+ */
+
+/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
+ * @{
+ */
+
+/**
+ * @brief Set memory mapping at address 0x00000000
+ * @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_SetRemapMemory
+ * @param Memory This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_REMAP_FLASH
+ * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
+ * @arg @ref LL_SYSCFG_REMAP_SRAM
+ * @arg @ref LL_SYSCFG_REMAP_FMC (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
+{
+ MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, Memory);
+}
+
+/**
+ * @brief Get memory mapping at address 0x00000000
+ * @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_GetRemapMemory
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SYSCFG_REMAP_FLASH
+ * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
+ * @arg @ref LL_SYSCFG_REMAP_SRAM
+ * @arg @ref LL_SYSCFG_REMAP_FMC (*)
+ *
+ * (*) value not defined in all devices.
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
+{
+ return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE));
+}
+
+#if defined(SYSCFG_CFGR3_SPI1_RX_DMA_RMP)
+/**
+ * @brief Set DMA request remapping bits for SPI
+ * @rmtoll SYSCFG_CFGR3 SPI1_RX_DMA_RMP LL_SYSCFG_SetRemapDMA_SPI\n
+ * SYSCFG_CFGR3 SPI1_TX_DMA_RMP LL_SYSCFG_SetRemapDMA_SPI
+ * @param Remap This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_SPI1RX_RMP_DMA1_CH2
+ * @arg @ref LL_SYSCFG_SPI1RX_RMP_DMA1_CH4
+ * @arg @ref LL_SYSCFG_SPI1RX_RMP_DMA1_CH6
+ * @arg @ref LL_SYSCFG_SPI1TX_RMP_DMA1_CH3
+ * @arg @ref LL_SYSCFG_SPI1TX_RMP_DMA1_CH5
+ * @arg @ref LL_SYSCFG_SPI1TX_RMP_DMA1_CH7
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_SPI(uint32_t Remap)
+{
+ MODIFY_REG(SYSCFG->CFGR3, (Remap >> 16U), (Remap & 0x0000FFFF));
+}
+#endif /* SYSCFG_CFGR3_SPI1_RX_DMA_RMP */
+
+#if defined(SYSCFG_CFGR3_I2C1_RX_DMA_RMP)
+/**
+ * @brief Set DMA request remapping bits for I2C
+ * @rmtoll SYSCFG_CFGR3 I2C1_RX_DMA_RMP LL_SYSCFG_SetRemapDMA_I2C\n
+ * SYSCFG_CFGR3 I2C1_TX_DMA_RMP LL_SYSCFG_SetRemapDMA_I2C
+ * @param Remap This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_I2C1RX_RMP_DMA1_CH7
+ * @arg @ref LL_SYSCFG_I2C1RX_RMP_DMA1_CH3
+ * @arg @ref LL_SYSCFG_I2C1RX_RMP_DMA1_CH5
+ * @arg @ref LL_SYSCFG_I2C1TX_RMP_DMA1_CH6
+ * @arg @ref LL_SYSCFG_I2C1TX_RMP_DMA1_CH2
+ * @arg @ref LL_SYSCFG_I2C1TX_RMP_DMA1_CH4
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_I2C(uint32_t Remap)
+{
+ MODIFY_REG(SYSCFG->CFGR3, (Remap >> 16U), (Remap & 0x0000FFFF));
+}
+#endif /* SYSCFG_CFGR3_I2C1_RX_DMA_RMP */
+
+#if defined(SYSCFG_CFGR1_ADC24_DMA_RMP) || defined(SYSCFG_CFGR3_ADC2_DMA_RMP)
+/**
+ * @brief Set DMA request remapping bits for ADC
+ * @rmtoll SYSCFG_CFGR1 ADC24_DMA_RMP LL_SYSCFG_SetRemapDMA_ADC\n
+ * SYSCFG_CFGR3 ADC2_DMA_RMP LL_SYSCFG_SetRemapDMA_ADC
+ * @param Remap This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_ADC24_RMP_DMA2_CH12 (*)
+ * @arg @ref LL_SYSCFG_ADC24_RMP_DMA2_CH34 (*)
+ * @arg @ref LL_SYSCFG_ADC2_RMP_DMA1_CH2 (*)
+ * @arg @ref LL_SYSCFG_ADC2_RMP_DMA1_CH4 (*)
+ * @arg @ref LL_SYSCFG_ADC2_RMP_DMA2 (*)
+ * @arg @ref LL_SYSCFG_ADC2_RMP_DMA1 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_ADC(uint32_t Remap)
+{
+ __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(SYSCFG_BASE + (Remap >> 24U));
+ MODIFY_REG(*reg, (Remap & 0x00FF0000U) >> 8U, (Remap & 0x0000FFFFU));
+}
+#endif /* SYSCFG_CFGR1_ADC24_DMA_RMP || SYSCFG_CFGR3_ADC2_DMA_RMP */
+
+/**
+ * @brief Set DMA request remapping bits for DAC
+ * @rmtoll SYSCFG_CFGR1 TIM6DAC1Ch1_DMA_RMP LL_SYSCFG_SetRemapDMA_DAC\n
+ * SYSCFG_CFGR1 DAC2Ch1_DMA_RMP LL_SYSCFG_SetRemapDMA_DAC
+ * @param Remap This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_DAC1_CH1_RMP_DMA2_CH3
+ * @arg @ref LL_SYSCFG_DAC1_CH1_RMP_DMA1_CH3
+ * @arg @ref LL_SYSCFG_DAC1_OUT2_RMP_DMA2_CH4 (*)
+ * @arg @ref LL_SYSCFG_DAC1_OUT2_RMP_DMA1_CH4 (*)
+ * @arg @ref LL_SYSCFG_DAC2_OUT1_RMP_DMA2_CH5 (*)
+ * @arg @ref LL_SYSCFG_DAC2_OUT1_RMP_DMA1_CH5 (*)
+ * @arg @ref LL_SYSCFG_DAC2_CH1_RMP_NO (*)
+ * @arg @ref LL_SYSCFG_DAC2_CH1_RMP_DMA1_CH5 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_DAC(uint32_t Remap)
+{
+ MODIFY_REG(SYSCFG->CFGR1, (Remap & 0x00FF0000U) >> 8U, (Remap & 0x0000FF00U));
+}
+
+/**
+ * @brief Set DMA request remapping bits for TIM
+ * @rmtoll SYSCFG_CFGR1 TIM16_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
+ * SYSCFG_CFGR1 TIM17_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
+ * SYSCFG_CFGR1 TIM6DAC1Ch1_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
+ * SYSCFG_CFGR1 TIM7DAC1Ch2_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
+ * SYSCFG_CFGR1 TIM18DAC2Ch1_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM
+ * @param Remap This parameter can be a combination of the following values:
+ * @arg @ref LL_SYSCFG_TIM16_RMP_DMA1_CH3 or @ref LL_SYSCFG_TIM16_RMP_DMA1_CH6
+ * @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH1 or @ref LL_SYSCFG_TIM17_RMP_DMA1_CH7
+ * @arg @ref LL_SYSCFG_TIM6_RMP_DMA2_CH3 or @ref LL_SYSCFG_TIM6_RMP_DMA1_CH3
+ * @arg @ref LL_SYSCFG_TIM7_RMP_DMA2_CH4 or @ref LL_SYSCFG_TIM7_RMP_DMA1_CH4 (*)
+ * @arg @ref LL_SYSCFG_TIM18_RMP_DMA2_CH5 or @ref LL_SYSCFG_TIM18_RMP_DMA1_CH5 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_TIM(uint32_t Remap)
+{
+ MODIFY_REG(SYSCFG->CFGR1, (Remap & 0x00FF0000U) >> 8U, (Remap & 0x0000FF00U));
+}
+
+#if defined(SYSCFG_CFGR1_TIM1_ITR3_RMP) || defined(SYSCFG_CFGR1_ENCODER_MODE)
+/**
+ * @brief Set Timer input remap
+ * @rmtoll SYSCFG_CFGR1 TIM1_ITR3_RMP LL_SYSCFG_SetRemapInput_TIM\n
+ * SYSCFG_CFGR1 ENCODER_MODE LL_SYSCFG_SetRemapInput_TIM
+ * @param Remap This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_TIM1_ITR3_RMP_TIM4_TRGO (*)
+ * @arg @ref LL_SYSCFG_TIM1_ITR3_RMP_TIM17_OC (*)
+ * @arg @ref LL_SYSCFG_TIM15_ENCODEMODE_NOREDIRECTION (*)
+ * @arg @ref LL_SYSCFG_TIM15_ENCODEMODE_TIM2 (*)
+ * @arg @ref LL_SYSCFG_TIM15_ENCODEMODE_TIM3 (*)
+ * @arg @ref LL_SYSCFG_TIM15_ENCODEMODE_TIM4 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_SetRemapInput_TIM(uint32_t Remap)
+{
+ MODIFY_REG(SYSCFG->CFGR1, (Remap & 0xFF00FF00U) >> 8U, (Remap & 0x00FF00FFU));
+}
+#endif /* SYSCFG_CFGR1_TIM1_ITR3_RMP || SYSCFG_CFGR1_ENCODER_MODE */
+
+#if defined(SYSCFG_CFGR4_ADC12_EXT2_RMP)
+/**
+ * @brief Set ADC Trigger remap
+ * @rmtoll SYSCFG_CFGR4 ADC12_EXT2_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
+ * SYSCFG_CFGR4 ADC12_EXT3_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
+ * SYSCFG_CFGR4 ADC12_EXT5_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
+ * SYSCFG_CFGR4 ADC12_EXT13_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
+ * SYSCFG_CFGR4 ADC12_EXT15_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
+ * SYSCFG_CFGR4 ADC12_JEXT3_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
+ * SYSCFG_CFGR4 ADC12_JEXT6_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
+ * SYSCFG_CFGR4 ADC12_JEXT13_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
+ * SYSCFG_CFGR4 ADC34_EXT5_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
+ * SYSCFG_CFGR4 ADC34_EXT6_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
+ * SYSCFG_CFGR4 ADC34_EXT15_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
+ * SYSCFG_CFGR4 ADC34_JEXT5_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
+ * SYSCFG_CFGR4 ADC34_JEXT11_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
+ * SYSCFG_CFGR4 ADC34_JEXT14_RMP LL_SYSCFG_SetRemapTrigger_ADC
+ * @param Remap This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_ADC12_EXT2_RMP_TIM1_CC3
+ * @arg @ref LL_SYSCFG_ADC12_EXT2_RMP_TIM20_TRGO
+ * @arg @ref LL_SYSCFG_ADC12_EXT3_RMP_TIM2_CC2
+ * @arg @ref LL_SYSCFG_ADC12_EXT3_RMP_TIM20_TRGO2
+ * @arg @ref LL_SYSCFG_ADC12_EXT5_RMP_TIM4_CC4
+ * @arg @ref LL_SYSCFG_ADC12_EXT5_RMP_TIM20_CC1
+ * @arg @ref LL_SYSCFG_ADC12_EXT13_RMP_TIM6_TRGO
+ * @arg @ref LL_SYSCFG_ADC12_EXT13_RMP_TIM20_CC2
+ * @arg @ref LL_SYSCFG_ADC12_EXT15_RMP_TIM3_CC4
+ * @arg @ref LL_SYSCFG_ADC12_EXT15_RMP_TIM20_CC3
+ * @arg @ref LL_SYSCFG_ADC12_JEXT3_RMP_TIM2_CC1
+ * @arg @ref LL_SYSCFG_ADC12_JEXT3_RMP_TIM20_TRGO
+ * @arg @ref LL_SYSCFG_ADC12_JEXT6_RMP_EXTI_LINE_15
+ * @arg @ref LL_SYSCFG_ADC12_JEXT6_RMP_TIM20_TRGO2
+ * @arg @ref LL_SYSCFG_ADC12_JEXT13_RMP_TIM3_CC1
+ * @arg @ref LL_SYSCFG_ADC12_JEXT13_RMP_TIM20_CC4
+ * @arg @ref LL_SYSCFG_ADC34_EXT5_RMP_EXTI_LINE_2
+ * @arg @ref LL_SYSCFG_ADC34_EXT5_RMP_TIM20_TRGO
+ * @arg @ref LL_SYSCFG_ADC34_EXT6_RMP_TIM4_CC1
+ * @arg @ref LL_SYSCFG_ADC34_EXT6_RMP_TIM20_TRGO2
+ * @arg @ref LL_SYSCFG_ADC34_EXT15_RMP_TIM2_CC1
+ * @arg @ref LL_SYSCFG_ADC34_EXT15_RMP_TIM20_CC1
+ * @arg @ref LL_SYSCFG_ADC34_JEXT5_RMP_TIM4_CC3
+ * @arg @ref LL_SYSCFG_ADC34_JEXT5_RMP_TIM20_TRGO
+ * @arg @ref LL_SYSCFG_ADC34_JEXT11_RMP_TIM1_CC3
+ * @arg @ref LL_SYSCFG_ADC34_JEXT11_RMP_TIM20_TRGO2
+ * @arg @ref LL_SYSCFG_ADC34_JEXT14_RMP_TIM7_TRGO
+ * @arg @ref LL_SYSCFG_ADC34_JEXT14_RMP_TIM20_CC2
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_SetRemapTrigger_ADC(uint32_t Remap)
+{
+ MODIFY_REG(SYSCFG->CFGR4, (Remap & 0xFFFF0000U) >> 16U, (Remap & 0x0000FFFFU));
+}
+#endif /* SYSCFG_CFGR4_ADC12_EXT2_RMP */
+
+#if defined(SYSCFG_CFGR1_DAC1_TRIG1_RMP) || defined(SYSCFG_CFGR3_TRIGGER_RMP)
+/**
+ * @brief Set DAC Trigger remap
+ * @rmtoll SYSCFG_CFGR1 DAC1_TRIG1_RMP LL_SYSCFG_SetRemapTrigger_DAC\n
+ * SYSCFG_CFGR3 DAC1_TRG3_RMP LL_SYSCFG_SetRemapTrigger_DAC\n
+ * SYSCFG_CFGR3 DAC1_TRG5_RMP LL_SYSCFG_SetRemapTrigger_DAC
+ * @param Remap This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_DAC1_TRIG1_RMP_TIM8_TRGO (*)
+ * @arg @ref LL_SYSCFG_DAC1_TRIG1_RMP_TIM3_TRGO (*)
+ * @arg @ref LL_SYSCFG_DAC1_TRIG3_RMP_TIM15_TRGO (*)
+ * @arg @ref LL_SYSCFG_DAC1_TRIG3_RMP_HRTIM1_DAC1_TRIG1 (*)
+ * @arg @ref LL_SYSCFG_DAC1_TRIG5_RMP_NO (*)
+ * @arg @ref LL_SYSCFG_DAC1_TRIG5_RMP_HRTIM1_DAC1_TRIG2 (*)
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_SetRemapTrigger_DAC(uint32_t Remap)
+{
+ __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(SYSCFG_BASE + (Remap >> 24U));
+ MODIFY_REG(*reg, (Remap & 0x00F00F00U) >> 4U, (Remap & 0x000F00F0U));
+}
+#endif /* SYSCFG_CFGR1_DAC1_TRIG1_RMP || SYSCFG_CFGR3_TRIGGER_RMP */
+
+#if defined(SYSCFG_CFGR1_USB_IT_RMP)
+/**
+ * @brief Enable USB interrupt remap
+ * @note Remap the USB interrupts (USB_HP, USB_LP and USB_WKUP) on interrupt lines 74, 75 and 76
+ * respectively
+ * @rmtoll SYSCFG_CFGR1 USB_IT_RMP LL_SYSCFG_EnableRemapIT_USB
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableRemapIT_USB(void)
+{
+ SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_USB_IT_RMP);
+}
+
+/**
+ * @brief Disable USB interrupt remap
+ * @rmtoll SYSCFG_CFGR1 USB_IT_RMP LL_SYSCFG_DisableRemapIT_USB
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DisableRemapIT_USB(void)
+{
+ CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_USB_IT_RMP);
+}
+#endif /* SYSCFG_CFGR1_USB_IT_RMP */
+
+#if defined(SYSCFG_CFGR1_VBAT)
+/**
+ * @brief Enable VBAT monitoring (to enable the power switch to deliver VBAT voltage on ADC channel 18 input)
+ * @rmtoll SYSCFG_CFGR1 VBAT LL_SYSCFG_EnableVBATMonitoring
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableVBATMonitoring(void)
+{
+ SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_VBAT);
+}
+
+/**
+ * @brief Disable VBAT monitoring
+ * @rmtoll SYSCFG_CFGR1 VBAT LL_SYSCFG_DisableVBATMonitoring
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DisableVBATMonitoring(void)
+{
+ CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_VBAT);
+}
+#endif /* SYSCFG_CFGR1_VBAT */
+
+/**
+ * @brief Enable the I2C fast mode plus driving capability.
+ * @rmtoll SYSCFG_CFGR1 I2C_PB6_FMP LL_SYSCFG_EnableFastModePlus\n
+ * SYSCFG_CFGR1 I2C_PB7_FMP LL_SYSCFG_EnableFastModePlus\n
+ * SYSCFG_CFGR1 I2C_PB8_FMP LL_SYSCFG_EnableFastModePlus\n
+ * SYSCFG_CFGR1 I2C_PB9_FMP LL_SYSCFG_EnableFastModePlus\n
+ * SYSCFG_CFGR1 I2C1_FMP LL_SYSCFG_EnableFastModePlus\n
+ * SYSCFG_CFGR1 I2C2_FMP LL_SYSCFG_EnableFastModePlus\n
+ * SYSCFG_CFGR1 I2C3_FMP LL_SYSCFG_EnableFastModePlus
+ * @param ConfigFastModePlus This parameter can be a combination of the following values:
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
+{
+ SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
+}
+
+/**
+ * @brief Disable the I2C fast mode plus driving capability.
+ * @rmtoll SYSCFG_CFGR1 I2C_PB6_FMP LL_SYSCFG_DisableFastModePlus\n
+ * SYSCFG_CFGR1 I2C_PB7_FMP LL_SYSCFG_DisableFastModePlus\n
+ * SYSCFG_CFGR1 I2C_PB8_FMP LL_SYSCFG_DisableFastModePlus\n
+ * SYSCFG_CFGR1 I2C_PB9_FMP LL_SYSCFG_DisableFastModePlus\n
+ * SYSCFG_CFGR1 I2C1_FMP LL_SYSCFG_DisableFastModePlus\n
+ * SYSCFG_CFGR1 I2C2_FMP LL_SYSCFG_DisableFastModePlus\n
+ * SYSCFG_CFGR1 I2C3_FMP LL_SYSCFG_DisableFastModePlus
+ * @param ConfigFastModePlus This parameter can be a combination of the following values:
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
+{
+ CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
+}
+
+/**
+ * @brief Enable Floating Point Unit Invalid operation Interrupt
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_EnableIT_FPU_IOC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void)
+{
+ SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
+}
+
+/**
+ * @brief Enable Floating Point Unit Divide-by-zero Interrupt
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_EnableIT_FPU_DZC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void)
+{
+ SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
+}
+
+/**
+ * @brief Enable Floating Point Unit Underflow Interrupt
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_EnableIT_FPU_UFC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void)
+{
+ SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
+}
+
+/**
+ * @brief Enable Floating Point Unit Overflow Interrupt
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_EnableIT_FPU_OFC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void)
+{
+ SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
+}
+
+/**
+ * @brief Enable Floating Point Unit Input denormal Interrupt
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_EnableIT_FPU_IDC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void)
+{
+ SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
+}
+
+/**
+ * @brief Enable Floating Point Unit Inexact Interrupt
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_EnableIT_FPU_IXC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void)
+{
+ SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
+}
+
+/**
+ * @brief Disable Floating Point Unit Invalid operation Interrupt
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_DisableIT_FPU_IOC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void)
+{
+ CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
+}
+
+/**
+ * @brief Disable Floating Point Unit Divide-by-zero Interrupt
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_DisableIT_FPU_DZC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void)
+{
+ CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
+}
+
+/**
+ * @brief Disable Floating Point Unit Underflow Interrupt
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_DisableIT_FPU_UFC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void)
+{
+ CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
+}
+
+/**
+ * @brief Disable Floating Point Unit Overflow Interrupt
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_DisableIT_FPU_OFC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void)
+{
+ CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
+}
+
+/**
+ * @brief Disable Floating Point Unit Input denormal Interrupt
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_DisableIT_FPU_IDC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void)
+{
+ CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
+}
+
+/**
+ * @brief Disable Floating Point Unit Inexact Interrupt
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_DisableIT_FPU_IXC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC(void)
+{
+ CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
+}
+
+/**
+ * @brief Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_IsEnabledIT_FPU_IOC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void)
+{
+ return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0) == (SYSCFG_CFGR1_FPU_IE_0));
+}
+
+/**
+ * @brief Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_IsEnabledIT_FPU_DZC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void)
+{
+ return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1) == (SYSCFG_CFGR1_FPU_IE_1));
+}
+
+/**
+ * @brief Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_IsEnabledIT_FPU_UFC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void)
+{
+ return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2) == (SYSCFG_CFGR1_FPU_IE_2));
+}
+
+/**
+ * @brief Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_IsEnabledIT_FPU_OFC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void)
+{
+ return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3) == (SYSCFG_CFGR1_FPU_IE_3));
+}
+
+/**
+ * @brief Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_IsEnabledIT_FPU_IDC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void)
+{
+ return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4) == (SYSCFG_CFGR1_FPU_IE_4));
+}
+
+/**
+ * @brief Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_IsEnabledIT_FPU_IXC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void)
+{
+ return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5) == (SYSCFG_CFGR1_FPU_IE_5));
+}
+
+/**
+ * @brief Configure source input for the EXTI external interrupt.
+ * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI4 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI5 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI6 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI7 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI8 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI9 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI10 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI11 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI12 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI13 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI14 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI15 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI0 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI1 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI2 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI3 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI8 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI9 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI10 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI11 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI12 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI13 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI14 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI15 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI0 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI1 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI2 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI3 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI4 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI5 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI6 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI7 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI12 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI13 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI14 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI15 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI0 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI1 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI2 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI3 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI4 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI5 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI6 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI7 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI8 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI9 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI10 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI11 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_SetEXTISource
+ * @param Port This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_EXTI_PORTA
+ * @arg @ref LL_SYSCFG_EXTI_PORTB
+ * @arg @ref LL_SYSCFG_EXTI_PORTC
+ * @arg @ref LL_SYSCFG_EXTI_PORTD
+ * @arg @ref LL_SYSCFG_EXTI_PORTE (*)
+ * @arg @ref LL_SYSCFG_EXTI_PORTF
+ * @arg @ref LL_SYSCFG_EXTI_PORTG (*)
+ * @arg @ref LL_SYSCFG_EXTI_PORTH (*)
+ *
+ * (*) value not defined in all devices.
+ * @param Line This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_EXTI_LINE0
+ * @arg @ref LL_SYSCFG_EXTI_LINE1
+ * @arg @ref LL_SYSCFG_EXTI_LINE2
+ * @arg @ref LL_SYSCFG_EXTI_LINE3
+ * @arg @ref LL_SYSCFG_EXTI_LINE4
+ * @arg @ref LL_SYSCFG_EXTI_LINE5
+ * @arg @ref LL_SYSCFG_EXTI_LINE6
+ * @arg @ref LL_SYSCFG_EXTI_LINE7
+ * @arg @ref LL_SYSCFG_EXTI_LINE8
+ * @arg @ref LL_SYSCFG_EXTI_LINE9
+ * @arg @ref LL_SYSCFG_EXTI_LINE10
+ * @arg @ref LL_SYSCFG_EXTI_LINE11
+ * @arg @ref LL_SYSCFG_EXTI_LINE12
+ * @arg @ref LL_SYSCFG_EXTI_LINE13
+ * @arg @ref LL_SYSCFG_EXTI_LINE14
+ * @arg @ref LL_SYSCFG_EXTI_LINE15
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
+{
+ MODIFY_REG(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16U), Port << POSITION_VAL((Line >> 16U)));
+}
+
+/**
+ * @brief Get the configured defined for specific EXTI Line
+ * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI4 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI5 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI6 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI7 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI8 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI9 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI10 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI11 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI12 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI13 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI14 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI15 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI0 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI1 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI2 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI3 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI8 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI9 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI10 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI11 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI12 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI13 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI14 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI15 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI0 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI1 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI2 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI3 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI4 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI5 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI6 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI7 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI12 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI13 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI14 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI15 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI0 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI1 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI2 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI3 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI4 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI5 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI6 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI7 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI8 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI9 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI10 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI11 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_GetEXTISource
+ * @param Line This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_EXTI_LINE0
+ * @arg @ref LL_SYSCFG_EXTI_LINE1
+ * @arg @ref LL_SYSCFG_EXTI_LINE2
+ * @arg @ref LL_SYSCFG_EXTI_LINE3
+ * @arg @ref LL_SYSCFG_EXTI_LINE4
+ * @arg @ref LL_SYSCFG_EXTI_LINE5
+ * @arg @ref LL_SYSCFG_EXTI_LINE6
+ * @arg @ref LL_SYSCFG_EXTI_LINE7
+ * @arg @ref LL_SYSCFG_EXTI_LINE8
+ * @arg @ref LL_SYSCFG_EXTI_LINE9
+ * @arg @ref LL_SYSCFG_EXTI_LINE10
+ * @arg @ref LL_SYSCFG_EXTI_LINE11
+ * @arg @ref LL_SYSCFG_EXTI_LINE12
+ * @arg @ref LL_SYSCFG_EXTI_LINE13
+ * @arg @ref LL_SYSCFG_EXTI_LINE14
+ * @arg @ref LL_SYSCFG_EXTI_LINE15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SYSCFG_EXTI_PORTA
+ * @arg @ref LL_SYSCFG_EXTI_PORTB
+ * @arg @ref LL_SYSCFG_EXTI_PORTC
+ * @arg @ref LL_SYSCFG_EXTI_PORTD
+ * @arg @ref LL_SYSCFG_EXTI_PORTE (*)
+ * @arg @ref LL_SYSCFG_EXTI_PORTF
+ * @arg @ref LL_SYSCFG_EXTI_PORTG (*)
+ * @arg @ref LL_SYSCFG_EXTI_PORTH (*)
+ *
+ * (*) value not defined in all devices.
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
+{
+ return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16U)) >> POSITION_VAL(Line >> 16U));
+}
+
+/**
+ * @brief Set connections to TIMx Break inputs
+ * @rmtoll SYSCFG_CFGR2 LOCKUP_LOCK LL_SYSCFG_SetTIMBreakInputs\n
+ * SYSCFG_CFGR2 SRAM_PARITY_LOCK LL_SYSCFG_SetTIMBreakInputs\n
+ * SYSCFG_CFGR2 PVD_LOCK LL_SYSCFG_SetTIMBreakInputs
+ * @param Break This parameter can be a combination of the following values:
+ * @arg @ref LL_SYSCFG_TIMBREAK_PVD (*)
+ * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY (*)
+ * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
+{
+ MODIFY_REG(SYSCFG->CFGR2, SYSCFG_MASK_TIM_BREAK, Break);
+}
+
+/**
+ * @brief Get connections to TIMx Break inputs
+ * @rmtoll SYSCFG_CFGR2 LOCKUP_LOCK LL_SYSCFG_GetTIMBreakInputs\n
+ * SYSCFG_CFGR2 SRAM_PARITY_LOCK LL_SYSCFG_GetTIMBreakInputs\n
+ * SYSCFG_CFGR2 PVD_LOCK LL_SYSCFG_GetTIMBreakInputs
+ * @retval Returned value can be can be a combination of the following values:
+ * @arg @ref LL_SYSCFG_TIMBREAK_PVD (*)
+ * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY (*)
+ * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
+ *
+ * (*) value not defined in all devices.
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
+{
+ return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_MASK_TIM_BREAK));
+}
+
+#if defined(SYSCFG_CFGR2_BYP_ADDR_PAR)
+/**
+ * @brief Disable RAM Parity Check Disable
+ * @rmtoll SYSCFG_CFGR2 BYP_ADDR_PAR LL_SYSCFG_DisableSRAMParityCheck
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DisableSRAMParityCheck(void)
+{
+ SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_BYP_ADDR_PAR);
+}
+#endif /* SYSCFG_CFGR2_BYP_ADDR_PAR */
+
+#if defined(SYSCFG_CFGR2_SRAM_PE)
+/**
+ * @brief Check if SRAM parity error detected
+ * @rmtoll SYSCFG_CFGR2 SRAM_PE LL_SYSCFG_IsActiveFlag_SP
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void)
+{
+ return (READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PE) == (SYSCFG_CFGR2_SRAM_PE));
+}
+
+/**
+ * @brief Clear SRAM parity error flag
+ * @rmtoll SYSCFG_CFGR2 SRAM_PE LL_SYSCFG_ClearFlag_SP
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void)
+{
+ SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PE);
+}
+#endif /* SYSCFG_CFGR2_SRAM_PE */
+
+#if defined(SYSCFG_RCR_PAGE0)
+/**
+ * @brief Enable CCM SRAM page write protection
+ * @note Write protection is cleared only by a system reset
+ * @rmtoll SYSCFG_RCR PAGE0 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
+ * SYSCFG_RCR PAGE1 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
+ * SYSCFG_RCR PAGE2 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
+ * SYSCFG_RCR PAGE3 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
+ * SYSCFG_RCR PAGE4 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
+ * SYSCFG_RCR PAGE5 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
+ * SYSCFG_RCR PAGE6 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
+ * SYSCFG_RCR PAGE7 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
+ * SYSCFG_RCR PAGE8 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
+ * SYSCFG_RCR PAGE9 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
+ * SYSCFG_RCR PAGE10 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
+ * SYSCFG_RCR PAGE11 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
+ * SYSCFG_RCR PAGE12 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
+ * SYSCFG_RCR PAGE13 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
+ * SYSCFG_RCR PAGE14 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
+ * SYSCFG_RCR PAGE15 LL_SYSCFG_EnableCCM_SRAMPageWRP
+ * @param PageWRP This parameter can be a combination of the following values:
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE0
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE1
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE2
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE3
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE4 (*)
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE5 (*)
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE6 (*)
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE7 (*)
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE8 (*)
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE9 (*)
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE10 (*)
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE11 (*)
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE12 (*)
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE13 (*)
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE14 (*)
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE15 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableCCM_SRAMPageWRP(uint32_t PageWRP)
+{
+ SET_BIT(SYSCFG->RCR, PageWRP);
+}
+#endif /* SYSCFG_RCR_PAGE0 */
+
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
+ * @{
+ */
+
+/**
+ * @brief Return the device identifier
+ * @note For STM32F303xC, STM32F358xx and STM32F302xC devices, the device ID is 0x422
+ * @note For STM32F373xx and STM32F378xx devices, the device ID is 0x432
+ * @note For STM32F303x8, STM32F334xx and STM32F328xx devices, the device ID is 0x438.
+ * @note For STM32F302x8, STM32F301x8 and STM32F318xx devices, the device ID is 0x439
+ * @note For STM32F303xE, STM32F398xx and STM32F302xE devices, the device ID is 0x446
+ * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
+ * @retval Values between Min_Data=0x00 and Max_Data=0xFFF
+ */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
+{
+ return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
+}
+
+/**
+ * @brief Return the device revision identifier
+ * @note This field indicates the revision of the device.
+ * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
+ * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
+{
+ return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
+}
+
+/**
+ * @brief Enable the Debug Module during SLEEP mode
+ * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
+{
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+ * @brief Disable the Debug Module during SLEEP mode
+ * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
+{
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+ * @brief Enable the Debug Module during STOP mode
+ * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
+{
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+ * @brief Disable the Debug Module during STOP mode
+ * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
+{
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+ * @brief Enable the Debug Module during STANDBY mode
+ * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
+{
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+ * @brief Disable the Debug Module during STANDBY mode
+ * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
+{
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+ * @brief Set Trace pin assignment control
+ * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
+ * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
+ * @param PinAssignment This parameter can be one of the following values:
+ * @arg @ref LL_DBGMCU_TRACE_NONE
+ * @arg @ref LL_DBGMCU_TRACE_ASYNCH
+ * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
+ * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
+ * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
+{
+ MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
+}
+
+/**
+ * @brief Get Trace pin assignment control
+ * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
+ * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DBGMCU_TRACE_NONE
+ * @arg @ref LL_DBGMCU_TRACE_ASYNCH
+ * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
+ * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
+ * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
+ */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
+{
+ return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
+}
+
+/**
+ * @brief Freeze APB1 peripherals (group1 peripherals)
+ * @rmtoll APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * APB1_FZ DBG_TIM18_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * APB1_FZ DBG_CAN_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM18_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
+{
+ SET_BIT(DBGMCU->APB1FZ, Periphs);
+}
+
+/**
+ * @brief Unfreeze APB1 peripherals (group1 peripherals)
+ * @rmtoll APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * APB1_FZ DBG_TIM18_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * APB1_FZ DBG_CAN_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM18_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
+{
+ CLEAR_BIT(DBGMCU->APB1FZ, Periphs);
+}
+
+/**
+ * @brief Freeze APB2 peripherals
+ * @rmtoll APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ * APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ * APB2_FZ DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ * APB2_FZ DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ * APB2_FZ DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ * APB2_FZ DBG_TIM19_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ * APB2_FZ DBG_TIM20_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ * APB2_FZ DBG_HRTIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM19_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM20_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM1_STOP (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
+{
+ SET_BIT(DBGMCU->APB2FZ, Periphs);
+}
+
+/**
+ * @brief Unfreeze APB2 peripherals
+ * @rmtoll APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
+ * APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
+ * APB2_FZ DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
+ * APB2_FZ DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
+ * APB2_FZ DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
+ * APB2_FZ DBG_TIM19_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
+ * APB2_FZ DBG_TIM20_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
+ * APB2_FZ DBG_HRTIM1_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM19_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM20_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM1_STOP (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
+{
+ CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EF_FLASH FLASH
+ * @{
+ */
+
+/**
+ * @brief Set FLASH Latency
+ * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
+ * @param Latency This parameter can be one of the following values:
+ * @arg @ref LL_FLASH_LATENCY_0
+ * @arg @ref LL_FLASH_LATENCY_1
+ * @arg @ref LL_FLASH_LATENCY_2
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
+{
+ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
+}
+
+/**
+ * @brief Get FLASH Latency
+ * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_FLASH_LATENCY_0
+ * @arg @ref LL_FLASH_LATENCY_1
+ * @arg @ref LL_FLASH_LATENCY_2
+ */
+__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
+{
+ return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
+}
+
+/**
+ * @brief Enable Prefetch
+ * @rmtoll FLASH_ACR PRFTBE LL_FLASH_EnablePrefetch
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
+{
+ SET_BIT(FLASH->ACR, FLASH_ACR_PRFTBE );
+}
+
+/**
+ * @brief Disable Prefetch
+ * @rmtoll FLASH_ACR PRFTBE LL_FLASH_DisablePrefetch
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
+{
+ CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTBE );
+}
+
+/**
+ * @brief Check if Prefetch buffer is enabled
+ * @rmtoll FLASH_ACR PRFTBS LL_FLASH_IsPrefetchEnabled
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
+{
+ return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTBS) == (FLASH_ACR_PRFTBS));
+}
+
+#if defined(FLASH_ACR_HLFCYA)
+/**
+ * @brief Enable Flash Half Cycle Access
+ * @rmtoll FLASH_ACR HLFCYA LL_FLASH_EnableHalfCycleAccess
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_EnableHalfCycleAccess(void)
+{
+ SET_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
+}
+
+/**
+ * @brief Disable Flash Half Cycle Access
+ * @rmtoll FLASH_ACR HLFCYA LL_FLASH_DisableHalfCycleAccess
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_DisableHalfCycleAccess(void)
+{
+ CLEAR_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
+}
+
+/**
+ * @brief Check if Flash Half Cycle Access is enabled or not
+ * @rmtoll FLASH_ACR HLFCYA LL_FLASH_IsHalfCycleAccessEnabled
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FLASH_IsHalfCycleAccessEnabled(void)
+{
+ return (READ_BIT(FLASH->ACR, FLASH_ACR_HLFCYA) == (FLASH_ACR_HLFCYA));
+}
+#endif /* FLASH_ACR_HLFCYA */
+
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_LL_SYSTEM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_ll_tim.h b/Inc/stm32f3xx_ll_tim.h
new file mode 100644
index 0000000..d241983
--- /dev/null
+++ b/Inc/stm32f3xx_ll_tim.h
@@ -0,0 +1,4964 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_tim.h
+ * @author MCD Application Team
+ * @brief Header file of TIM LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_LL_TIM_H
+#define __STM32F3xx_LL_TIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx.h"
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM18) || defined (TIM19) || defined (TIM20)
+
+/** @defgroup TIM_LL TIM
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Variables TIM Private Variables
+ * @{
+ */
+static const uint8_t OFFSET_TAB_CCMRx[] =
+{
+ 0x00U, /* 0: TIMx_CH1 */
+ 0x00U, /* 1: TIMx_CH1N */
+ 0x00U, /* 2: TIMx_CH2 */
+ 0x00U, /* 3: TIMx_CH2N */
+ 0x04U, /* 4: TIMx_CH3 */
+ 0x04U, /* 5: TIMx_CH3N */
+ 0x04U, /* 6: TIMx_CH4 */
+ 0x3CU, /* 7: TIMx_CH5 */
+ 0x3CU /* 8: TIMx_CH6 */
+};
+
+static const uint8_t SHIFT_TAB_OCxx[] =
+{
+ 0U, /* 0: OC1M, OC1FE, OC1PE */
+ 0U, /* 1: - NA */
+ 8U, /* 2: OC2M, OC2FE, OC2PE */
+ 0U, /* 3: - NA */
+ 0U, /* 4: OC3M, OC3FE, OC3PE */
+ 0U, /* 5: - NA */
+ 8U, /* 6: OC4M, OC4FE, OC4PE */
+ 0U, /* 7: OC5M, OC5FE, OC5PE */
+ 8U /* 8: OC6M, OC6FE, OC6PE */
+};
+
+static const uint8_t SHIFT_TAB_ICxx[] =
+{
+ 0U, /* 0: CC1S, IC1PSC, IC1F */
+ 0U, /* 1: - NA */
+ 8U, /* 2: CC2S, IC2PSC, IC2F */
+ 0U, /* 3: - NA */
+ 0U, /* 4: CC3S, IC3PSC, IC3F */
+ 0U, /* 5: - NA */
+ 8U, /* 6: CC4S, IC4PSC, IC4F */
+ 0U, /* 7: - NA */
+ 0U /* 8: - NA */
+};
+
+static const uint8_t SHIFT_TAB_CCxP[] =
+{
+ 0U, /* 0: CC1P */
+ 2U, /* 1: CC1NP */
+ 4U, /* 2: CC2P */
+ 6U, /* 3: CC2NP */
+ 8U, /* 4: CC3P */
+ 10U, /* 5: CC3NP */
+ 12U, /* 6: CC4P */
+ 16U, /* 7: CC5P */
+ 20U /* 8: CC6P */
+};
+
+static const uint8_t SHIFT_TAB_OISx[] =
+{
+ 0U, /* 0: OIS1 */
+ 1U, /* 1: OIS1N */
+ 2U, /* 2: OIS2 */
+ 3U, /* 3: OIS2N */
+ 4U, /* 4: OIS3 */
+ 5U, /* 5: OIS3N */
+ 6U, /* 6: OIS4 */
+ 8U, /* 7: OIS5 */
+ 10U /* 8: OIS6 */
+};
+/**
+ * @}
+ */
+
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Constants TIM Private Constants
+ * @{
+ */
+
+
+#define TIMx_OR_RMP_SHIFT 16U
+#define TIMx_OR_RMP_MASK 0x0000FFFFU
+#if defined(TIM1)
+#define TIM1_OR_RMP_MASK (TIM1_OR_ETR_RMP << TIMx_OR_RMP_SHIFT)
+#endif /* TIM1 */
+#if defined (TIM8)
+#define TIM8_OR_RMP_MASK (TIM8_OR_ETR_RMP << TIMx_OR_RMP_SHIFT)
+#endif /* TIM8 */
+#if defined(TIM14)
+#define TIM14_OR_RMP_MASK (TIM14_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
+#endif /* TIM14 */
+#if defined(TIM16)
+#define TIM16_OR_RMP_MASK (TIM16_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
+#endif /* TIM16 */
+#if defined(TIM20)
+#define TIM20_OR_RMP_MASK (TIM20_OR_ETR_RMP << TIMx_OR_RMP_SHIFT)
+#endif /* TIM20 */
+
+/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
+#define DT_DELAY_1 ((uint8_t)0x7FU)
+#define DT_DELAY_2 ((uint8_t)0x3FU)
+#define DT_DELAY_3 ((uint8_t)0x1FU)
+#define DT_DELAY_4 ((uint8_t)0x1FU)
+
+/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
+#define DT_RANGE_1 ((uint8_t)0x00U)
+#define DT_RANGE_2 ((uint8_t)0x80U)
+#define DT_RANGE_3 ((uint8_t)0xC0U)
+#define DT_RANGE_4 ((uint8_t)0xE0U)
+
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Macros TIM Private Macros
+ * @{
+ */
+/** @brief Convert channel id into channel index.
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @note CH5 and CH6 channels are not available for all F3 devices
+ * @retval none
+ */
+#if defined(TIM_CCR5_CCR5)
+#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
+(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
+((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
+((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
+((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
+((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
+((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
+((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
+((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
+#else
+#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
+(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
+((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
+((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
+((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
+((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
+((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U)
+#endif
+
+/** @brief Calculate the deadtime sampling period(in ps).
+ * @param __TIMCLK__ timer input clock frequency (in Hz).
+ * @param __CKD__ This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+ * @retval none
+ */
+#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
+ (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
+ ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
+ ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
+/**
+ * @}
+ */
+
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief TIM Time Base configuration structure definition.
+ */
+typedef struct
+{
+ uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
+ This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
+
+ uint32_t CounterMode; /*!< Specifies the counter mode.
+ This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
+
+ uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
+ Auto-Reload Register at the next update event.
+ This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+ Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
+
+ uint32_t ClockDivision; /*!< Specifies the clock division.
+ This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
+
+ uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
+ reaches zero, an update event is generated and counting restarts
+ from the RCR value (N).
+ This means in PWM mode that (N+1) corresponds to:
+ - the number of PWM periods in edge-aligned mode
+ - the number of half PWM period in center-aligned mode
+ This parameter must be a number between 0x00 and 0xFF.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
+} LL_TIM_InitTypeDef;
+
+/**
+ * @brief TIM Output Compare configuration structure definition.
+ */
+typedef struct
+{
+ uint32_t OCMode; /*!< Specifies the output mode.
+ This parameter can be a value of @ref TIM_LL_EC_OCMODE.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
+
+ uint32_t OCState; /*!< Specifies the TIM Output Compare state.
+ This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
+
+ This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
+
+ uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
+ This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
+
+ This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
+
+ uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
+ This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+
+ This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
+
+ uint32_t OCPolarity; /*!< Specifies the output polarity.
+ This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
+
+ uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
+ This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
+
+
+ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
+
+ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
+} LL_TIM_OC_InitTypeDef;
+
+/**
+ * @brief TIM Input Capture configuration structure definition.
+ */
+
+typedef struct
+{
+
+ uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
+
+ uint32_t ICActiveInput; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
+
+ uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
+
+ uint32_t ICFilter; /*!< Specifies the input capture filter.
+ This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
+} LL_TIM_IC_InitTypeDef;
+
+
+/**
+ * @brief TIM Encoder interface configuration structure definition.
+ */
+typedef struct
+{
+ uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
+ This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
+
+ uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
+ This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
+
+ uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
+ This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
+
+ uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
+ This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
+
+ uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
+ This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
+
+ uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
+ This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
+
+ uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
+ This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
+
+ uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
+ This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
+
+ uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
+ This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
+
+} LL_TIM_ENCODER_InitTypeDef;
+
+/**
+ * @brief TIM Hall sensor interface configuration structure definition.
+ */
+typedef struct
+{
+
+ uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
+ This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
+
+ uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
+ Prescaler must be set to get a maximum counter period longer than the
+ time interval between 2 consecutive changes on the Hall inputs.
+ This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
+
+ uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
+ This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
+
+ uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
+ A positive pulse (TRGO event) is generated with a programmable delay every time
+ a change occurs on the Hall inputs.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/
+} LL_TIM_HALLSENSOR_InitTypeDef;
+
+/**
+ * @brief BDTR (Break and Dead Time) structure definition
+ */
+typedef struct
+{
+ uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
+ This parameter can be a value of @ref TIM_LL_EC_OSSR
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
+
+ @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
+
+ uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
+ This parameter can be a value of @ref TIM_LL_EC_OSSI
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
+
+ @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
+
+ uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
+ This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
+
+ @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
+ has been written, their content is frozen until the next reset.*/
+
+ uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
+ switching-on of the outputs.
+ This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime()
+
+ @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */
+
+ uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
+ This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
+
+ This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
+
+ @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+
+ uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
+ This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
+
+ @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+
+#if defined(TIM_BDTR_BKF)
+ uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
+ This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
+
+ @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+
+#endif /* TIM_BDTR_BKF */
+#if defined(TIM_BDTR_BK2E)
+ uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
+ This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
+
+ This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
+
+ @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+
+ uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
+ This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
+
+ @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+
+ uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
+ This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
+
+ @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+
+#endif /* TIM_BDTR_BK2E */
+ uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
+ This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
+
+ This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
+
+ @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+} LL_TIM_BDTR_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
+ * @{
+ */
+
+/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_TIM_ReadReg function.
+ * @{
+ */
+#define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
+#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
+#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
+#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
+#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
+#if defined(TIM_CCMR1_OC1M_3)
+#define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */
+#define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */
+#endif /* TIM_CCMR1_OC1M_3 */
+#define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
+#define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
+#define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
+#define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */
+#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
+#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
+#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
+#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
+ * @{
+ */
+#define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
+#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
+/**
+ * @}
+ */
+#if defined(TIM_BDTR_BK2E)
+
+/** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
+ * @{
+ */
+#define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */
+#define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */
+/**
+ * @}
+ */
+#endif /* TIM_BDTR_BK2E */
+
+/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
+ * @{
+ */
+#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
+#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup TIM_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
+ * @{
+ */
+#define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
+#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
+#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
+#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
+#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
+#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
+#define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
+#define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
+ * @{
+ */
+#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
+#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
+ * @{
+ */
+#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */
+#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter stops counting at the next update event */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
+ * @{
+ */
+#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */
+#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
+#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
+#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
+#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
+ * @{
+ */
+#define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
+#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
+#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
+ * @{
+ */
+#define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
+#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
+ * @{
+ */
+#define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
+#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
+ * @{
+ */
+#define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
+#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
+ * @{
+ */
+#define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
+#define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
+#define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
+#define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_CHANNEL Channel
+ * @{
+ */
+#if defined(TIM_CCMR1_OC1M_3)
+#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
+#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
+#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
+#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
+#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
+#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
+#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
+#define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */
+#define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */
+#else
+#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
+#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
+#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
+#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
+#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
+#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
+#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
+#endif
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
+ * @{
+ */
+#define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
+#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
+ * @{
+ */
+#define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
+#define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
+#define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
+#define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
+#define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
+#define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
+#define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
+#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
+#if defined(TIM_CCMR1_OC1M_3)
+#define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!<Retrigerrable OPM mode 1*/
+#define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/
+#endif
+#if defined(TIM_CCMR1_OC1M_3)
+#define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/
+#define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
+#endif
+#if defined(TIM_CCMR1_OC1M_3)
+#define LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
+#define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
+ * @{
+ */
+#define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
+#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
+ * @{
+ */
+#define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
+#define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
+/**
+ * @}
+ */
+
+#if defined(TIM_CCR5_CCR5)
+/** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
+ * @{
+ */
+#define LL_TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
+#define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
+#define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
+#define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
+/**
+ * @}
+ */
+#endif /* TIM_CCR5_CCR5 */
+
+/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
+ * @{
+ */
+#define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
+#define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
+#define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
+ * @{
+ */
+#define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
+#define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
+#define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
+#define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
+ * @{
+ */
+#define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
+#define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
+#define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
+#define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
+#define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
+#define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
+#define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
+#define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
+#define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
+#define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
+ * @{
+ */
+#define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
+#define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
+#define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
+ * @{
+ */
+#define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
+#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected inpu t*/
+#define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
+ * @{
+ */
+#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
+#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
+#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input l */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_TRGO Trigger Output
+ * @{
+ */
+#define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
+#define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
+#define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
+#define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
+#define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
+#define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
+#define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
+#define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
+/**
+ * @}
+ */
+
+#if defined(TIM_CR2_MMS2)
+/** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
+ * @{
+ */
+#define LL_TIM_TRGO2_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
+#define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
+#define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output 2 */
+#define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< CC1 capture or a compare match is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges are used as trigger output 2 */
+#define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges are used as trigger output 2 */
+#define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
+#define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
+#define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
+#define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
+/**
+ * @}
+ */
+#endif /* TIM_CR2_MMS2 */
+
+/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
+ * @{
+ */
+#define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
+#define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
+#define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
+#define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
+#if defined (TIM_SMCR_SMS_3)
+#define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter */
+#endif /* TIM_SMCR_SMS_3 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_TS Trigger Selection
+ * @{
+ */
+#define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
+#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
+#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
+#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
+#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
+#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
+#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
+#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
+ * @{
+ */
+#define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
+#define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
+ * @{
+ */
+#define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
+#define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
+#define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
+#define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
+ * @{
+ */
+#define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
+#define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
+#define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
+#define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
+/**
+ * @}
+ */
+
+
+/** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
+ * @{
+ */
+#define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
+#define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
+/**
+ * @}
+ */
+
+#if defined(TIM_BDTR_BKF)
+/** @defgroup TIM_LL_EC_BREAK_FILTER break filter
+ * @{
+ */
+#define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
+#define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /*!< fSAMPLING=fCK_INT, N=2 */
+#define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /*!< fSAMPLING=fCK_INT, N=4 */
+#define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /*!< fSAMPLING=fCK_INT, N=8 */
+#define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /*!< fSAMPLING=fDTS/2, N=6 */
+#define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /*!< fSAMPLING=fDTS/2, N=8 */
+#define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /*!< fSAMPLING=fDTS/4, N=8 */
+#define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /*!< fSAMPLING=fDTS/8, N=6 */
+#define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /*!< fSAMPLING=fDTS/8, N=8 */
+#define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /*!< fSAMPLING=fDTS/32, N=8 */
+/**
+ * @}
+ */
+#endif /* TIM_BDTR_BKF */
+
+#if defined(TIM_BDTR_BK2P)
+/** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
+ * @{
+ */
+#define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
+#define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
+/**
+ * @}
+ */
+#endif /* TIM_BDTR_BK2P */
+
+#if defined(TIM_BDTR_BK2F)
+/** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
+ * @{
+ */
+#define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
+#define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /*!< fSAMPLING=fCK_INT, N=2 */
+#define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /*!< fSAMPLING=fCK_INT, N=4 */
+#define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /*!< fSAMPLING=fCK_INT, N=8 */
+#define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /*!< fSAMPLING=fDTS/2, N=6 */
+#define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /*!< fSAMPLING=fDTS/2, N=8 */
+#define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /*!< fSAMPLING=fDTS/4, N=8 */
+#define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /*!< fSAMPLING=fDTS/8, N=6 */
+#define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /*!< fSAMPLING=fDTS/8, N=8 */
+#define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /*!< fSAMPLING=fDTS/32, N=8 */
+/**
+ * @}
+ */
+#endif /* TIM_BDTR_BK2F */
+
+/** @defgroup TIM_LL_EC_OSSI OSSI
+ * @{
+ */
+#define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
+#define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_OSSR OSSR
+ * @{
+ */
+#define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
+#define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
+/**
+ * @}
+ */
+
+
+/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
+ * @{
+ */
+#define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
+#if defined(TIM_CCR6_CCR6)
+#define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
+#endif /* TIM_CCR6_CCR6 */
+#define LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_OR register is the DMA base address for DMA burst */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
+ * @{
+ */
+#define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
+/**
+ * @}
+ */
+
+#if defined(TIM1)
+/** @defgroup TIM_LL_EC_TIM1_ETR_ADC1_RMP TIM1 External Trigger ADC1 Remap
+ * @{
+ */
+#define LL_TIM_TIM1_ETR_ADC1_RMP_NC TIM1_OR_RMP_MASK /*!< TIM1_ETR is not connected to ADC1 analog watchdog x */
+#define LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 (TIM1_OR_ETR_RMP_0 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 1 */
+#define LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 (TIM1_OR_ETR_RMP_1 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 2 */
+#define LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 (TIM1_OR_ETR_RMP_0 | TIM1_OR_ETR_RMP_1| TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 3 */
+/**
+ * @}
+ */
+#if defined(ADC4)
+/** @defgroup TIM_LL_EC_TIM1_ETR_ADC4_RMP TIM1 External Trigger ADC4 Remap
+ * @{
+ */
+#define LL_TIM_TIM1_ETR_ADC4_RMP_NC TIM1_OR_RMP_MASK /*!< TIM1_ETR is not connected to ADC4 analog watchdog x*/
+#define LL_TIM_TIM1_ETR_ADC4_RMP_AWD1 (TIM1_OR_ETR_RMP_2 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC4 analog watchdog 1 */
+#define LL_TIM_TIM1_ETR_ADC4_RMP_AWD2 (TIM1_OR_ETR_RMP_3 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC4 analog watchdog 2 */
+#define LL_TIM_TIM1_ETR_ADC4_RMP_AWD3 (TIM1_OR_ETR_RMP_3 | TIM1_OR_ETR_RMP_2 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC4 analog watchdog 3 */
+/**
+ * @}
+ */
+#else
+/** @defgroup TIM_LL_EC_TIM1_ETR_ADC2_RMP TIM1 External Trigger ADC3 Remap
+ * @{
+ */
+#define LL_TIM_TIM1_ETR_ADC2_RMP_NC TIM1_OR_RMP_MASK /*!< TIM1_ETR is not connected to ADC2 analog watchdog x*/
+#define LL_TIM_TIM1_ETR_ADC2_RMP_AWD1 (TIM1_OR_ETR_RMP_2 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC2 analog watchdog 1 */
+#define LL_TIM_TIM1_ETR_ADC2_RMP_AWD2 (TIM1_OR_ETR_RMP_3 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC2 analog watchdog 2 */
+#define LL_TIM_TIM1_ETR_ADC2_RMP_AWD3 (TIM1_OR_ETR_RMP_3 | TIM1_OR_ETR_RMP_2 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC2 analog watchdog 3 */
+/**
+ * @}
+ */
+#endif /* ADC4 */
+#endif /* TIM1 */
+#if defined(TIM8)
+/** @defgroup TIM_LL_EC_TIM8_ETR_ADC2_RMP TIM8 External Trigger ADC2 Remap
+ * @{
+ */
+#define LL_TIM_TIM8_ETR_ADC2_RMP_NC TIM8_OR_RMP_MASK /*!< TIM8_ETR is not connected to ADC2 analog watchdog x */
+#define LL_TIM_TIM8_ETR_ADC2_RMP_AWD1 (TIM8_OR_ETR_RMP_0 | TIM8_OR_RMP_MASK) /*!< TIM8_ETR is connected to ADC2 analog watchdog */
+#define LL_TIM_TIM8_ETR_ADC2_RMP_AWD2 (TIM8_OR_ETR_RMP_1 | TIM8_OR_RMP_MASK) /*!< TIM8_ETR is connected to ADC2 analog watchdog 2 */
+#define LL_TIM_TIM8_ETR_ADC2_RMP_AWD3 (TIM8_OR_ETR_RMP_0 | TIM8_OR_ETR_RMP_1 | TIM8_OR_RMP_MASK) /*!< TIM8_ETR is connected to ADC2 analog watchdog 3 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_TIM8_ETR_ADC3_RMP TIM8 External Trigger ADC3 Remap
+ * @{
+ */
+#define LL_TIM_TIM8_ETR_ADC3_RMP_NC TIM8_OR_RMP_MASK /*!< TIM8_ETR is not connected to ADC3 analog watchdog x */
+#define LL_TIM_TIM8_ETR_ADC3_RMP_AWD1 (TIM8_OR_ETR_RMP_2 | TIM8_OR_RMP_MASK) /*!< TIM8_ETR is connected to ADC3 analog watchdog 1 */
+#define LL_TIM_TIM8_ETR_ADC3_RMP_AWD2 (TIM8_OR_ETR_RMP_3 | TIM8_OR_RMP_MASK) /*!< TIM8_ETR is connected to ADC3 analog watchdog 2 */
+#define LL_TIM_TIM8_ETR_ADC3_RMP_AWD3 (TIM8_OR_ETR_RMP_2 | TIM8_OR_ETR_RMP_3 | TIM8_OR_RMP_MASK) /*!< TIM8_ETR is connected to ADC3 analog watchdog 3 */
+/**
+ * @}
+ */
+#endif /* TIM8 */
+#if defined(TIM16)
+/** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 External Input Ch1 Remap
+ * @{
+ */
+#define LL_TIM_TIM16_TI1_RMP_GPIO 0x00000000U /*!< TIM16 input capture 1 is connected to GPIO */
+#define LL_TIM_TIM16_TI1_RMP_RTC (TIM16_OR_TI1_RMP_0 | TIM16_OR_RMP_MASK) /*!< TIM16 input capture 1 is connected to RTC wakeup interrupt */
+#define LL_TIM_TIM16_TI1_RMP_HSE_32 (TIM16_OR_TI1_RMP_1 | TIM16_OR_RMP_MASK) /*!< TIM16 input capture 1 is connected to HSE/32 clock */
+#define LL_TIM_TIM16_TI1_RMP_MCO (TIM16_OR_TI1_RMP_1 | TIM16_OR_TI1_RMP_0 | TIM16_OR_RMP_MASK) /*!< TIM16 input capture 1 is connected to MCO */
+/**
+ * @}
+ */
+#endif /* TIM16 */
+#if defined(TIM20)
+/** @defgroup TIM_LL_EC_TIM20_ETR_ADC3_RMP TIM20 External Trigger ADC3 Remap
+ * @{
+ */
+#define LL_TIM_TIM20_ETR_ADC3_RMP_NC TIM20_OR_RMP_MASK /*!< TIM20_ETR is not connected to ADC3 analog watchdog x */
+#define LL_TIM_TIM20_ETR_ADC3_RMP_AWD1 (TIM20_OR_ETR_RMP_0 | TIM20_OR_RMP_MASK) /*!< TIM20_ETR is connected to ADC3 analog watchdog */
+#define LL_TIM_TIM20_ETR_ADC3_RMP_AWD2 (TIM20_OR_ETR_RMP_1 | TIM20_OR_RMP_MASK) /*!< TIM20_ETR is connected to ADC3 analog watchdog 2 */
+#define LL_TIM_TIM20_ETR_ADC3_RMP_AWD3 (TIM20_OR_ETR_RMP_0 | TIM20_OR_ETR_RMP_1 | TIM20_OR_RMP_MASK) /*!< TIM20_ETR is connected to ADC3 analog watchdog 3 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_TIM20_ETR_ADC4_RMP TIM20 External Trigger ADC4 Remap
+ * @{
+ */
+#define LL_TIM_TIM20_ETR_ADC4_RMP_NC TIM20_OR_RMP_MASK /*!< TIM20_ETR is not connected to ADC4 analog watchdog x */
+#define LL_TIM_TIM20_ETR_ADC4_RMP_AWD1 (TIM20_OR_ETR_RMP_2 | TIM20_OR_RMP_MASK) /*!< TIM20_ETR is connected to ADC4 analog watchdog 1 */
+#define LL_TIM_TIM20_ETR_ADC4_RMP_AWD2 (TIM20_OR_ETR_RMP_3 | TIM20_OR_RMP_MASK) /*!< TIM20_ETR is connected to ADC4 analog watchdog 2 */
+#define LL_TIM_TIM20_ETR_ADC4_RMP_AWD3 (TIM20_OR_ETR_RMP_2 | TIM20_OR_ETR_RMP_3 | TIM20_OR_RMP_MASK) /*!< TIM20_ETR is connected to ADC4 analog watchdog 3 */
+/**
+ * @}
+ */
+#endif /* TIM20 */
+#if defined(TIM14)
+/** @defgroup TIM_LL_EC_TIM14_TI1_RMP TIM14 Timer Input1 Remap
+ * @{
+ */
+#define LL_TIM_TIM14_TI1_RMP_GPIO TIM14_OR_RMP_MASK /*!< TIM14_TI1 is connected to GPIO */
+#define LL_TIM_TIM14_TI1_RMP_RTC_CLK (TIM14_OR_TI1_RMP_0 | TIM14_OR_RMP_MASK) /*!< TIM14_TI1 is connected to RTC Clock */
+#define LL_TIM_TIM14_TI1_RMP_HSE (TIM14_OR_TI1_RMP_1 | TIM14_OR_RMP_MASK) /*!< TIM14_TI1 is connected to HSE/32 */
+#define LL_TIM_TIM14_TI1_RMP_MCO (TIM14_OR_TI1_RMP_0 | TIM14_OR_TI1_RMP_1 | TIM14_OR_RMP_MASK) /*!< TIM14_TI1 is connected to MCO */
+/**
+ * @}
+ */
+#endif /* TIM14 */
+
+#if defined(TIM_SMCR_OCCS)
+/** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
+ * @{
+ */
+#define LL_TIM_OCREF_CLR_INT_OCREF_CLR 0x00000000U /*!< OCREF_CLR_INT is connected to the OCREF_CLR input */
+#define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS /*!< OCREF_CLR_INT is connected to ETRF */
+/**
+ * @}
+ */
+#endif /* TIM_SMCR_OCCS*/
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
+ * @{
+ */
+
+/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+/**
+ * @brief Write a value in TIM register.
+ * @param __INSTANCE__ TIM Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in TIM register.
+ * @param __INSTANCE__ TIM Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
+ * @{
+ */
+/**
+ * @brief HELPER macro retrieving the UIFCPY flag from the counter value.
+ * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
+ * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
+ * to TIMx_CNT register bit 31)
+ * @param __CNT__ Counter value
+ * @retval UIF status bit
+ */
+#define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
+ (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
+
+/**
+ * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
+ * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __CKD__ This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+ * @param __DT__ deadtime duration (in ns)
+ * @retval DTG[0:7]
+ */
+#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
+ ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
+ (((uint64_t)((__DT__)*1000U)) < (64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64U) & DT_DELAY_2)) :\
+ (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32U) & DT_DELAY_3)) :\
+ (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32U) & DT_DELAY_4)) :\
+ 0U)
+
+/**
+ * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
+ * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __CNTCLK__ counter clock frequency (in Hz)
+ * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
+ */
+#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
+ ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U
+
+/**
+ * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
+ * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __PSC__ prescaler
+ * @param __FREQ__ output signal frequency (in Hz)
+ * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
+ */
+#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
+ (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U
+
+/**
+ * @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
+ * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __PSC__ prescaler
+ * @param __DELAY__ timer output compare active/inactive delay (in us)
+ * @retval Compare value (between Min_Data=0 and Max_Data=65535)
+ */
+#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
+((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
+ / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
+
+/**
+ * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
+ * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __PSC__ prescaler
+ * @param __DELAY__ timer output compare active/inactive delay (in us)
+ * @param __PULSE__ pulse duration (in us)
+ * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
+ */
+#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
+ ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
+ + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
+
+/**
+ * @brief HELPER macro retrieving the ratio of the input capture prescaler
+ * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
+ * @param __ICPSC__ This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ICPSC_DIV1
+ * @arg @ref LL_TIM_ICPSC_DIV2
+ * @arg @ref LL_TIM_ICPSC_DIV4
+ * @arg @ref LL_TIM_ICPSC_DIV8
+ * @retval Input capture prescaler ratio (1, 2, 4 or 8)
+ */
+#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
+ ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
+
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
+ * @{
+ */
+
+/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
+ * @{
+ */
+/**
+ * @brief Enable timer counter.
+ * @rmtoll CR1 CEN LL_TIM_EnableCounter
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->CR1, TIM_CR1_CEN);
+}
+
+/**
+ * @brief Disable timer counter.
+ * @rmtoll CR1 CEN LL_TIM_DisableCounter
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
+}
+
+/**
+ * @brief Indicates whether the timer counter is enabled.
+ * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN));
+}
+
+/**
+ * @brief Enable update event generation.
+ * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
+}
+
+/**
+ * @brief Disable update event generation.
+ * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
+}
+
+/**
+ * @brief Indicates whether update event generation is enabled.
+ * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
+ * @param TIMx Timer instance
+ * @retval Inverted state of bit (0 or 1).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == RESET);
+}
+
+/**
+ * @brief Set update event source
+ * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
+ * generate an update interrupt or DMA request if enabled:
+ * - Counter overflow/underflow
+ * - Setting the UG bit
+ * - Update generation through the slave mode controller
+ * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
+ * overflow/underflow generates an update interrupt or DMA request if enabled.
+ * @rmtoll CR1 URS LL_TIM_SetUpdateSource
+ * @param TIMx Timer instance
+ * @param UpdateSource This parameter can be one of the following values:
+ * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
+ * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
+{
+ MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
+}
+
+/**
+ * @brief Get actual event update source
+ * @rmtoll CR1 URS LL_TIM_GetUpdateSource
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
+ * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
+}
+
+/**
+ * @brief Set one pulse mode (one shot v.s. repetitive).
+ * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
+ * @param TIMx Timer instance
+ * @param OnePulseMode This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
+ * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
+{
+ MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
+}
+
+/**
+ * @brief Get actual one pulse mode.
+ * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
+ * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
+}
+
+/**
+ * @brief Set the timer counter counting mode.
+ * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+ * check whether or not the counter mode selection feature is supported
+ * by a timer instance.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
+ * CR1 CMS LL_TIM_SetCounterMode
+ * @param TIMx Timer instance
+ * @param CounterMode This parameter can be one of the following values:
+ * @arg @ref LL_TIM_COUNTERMODE_UP
+ * @arg @ref LL_TIM_COUNTERMODE_DOWN
+ * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
+ * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
+ * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
+{
+ MODIFY_REG(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS, CounterMode);
+}
+
+/**
+ * @brief Get actual counter mode.
+ * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+ * check whether or not the counter mode selection feature is supported
+ * by a timer instance.
+ * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
+ * CR1 CMS LL_TIM_GetCounterMode
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_COUNTERMODE_UP
+ * @arg @ref LL_TIM_COUNTERMODE_DOWN
+ * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
+ * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
+ * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS));
+}
+
+/**
+ * @brief Enable auto-reload (ARR) preload.
+ * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
+}
+
+/**
+ * @brief Disable auto-reload (ARR) preload.
+ * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
+}
+
+/**
+ * @brief Indicates whether auto-reload (ARR) preload is enabled.
+ * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE));
+}
+
+/**
+ * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
+ * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+ * whether or not the clock division feature is supported by the timer
+ * instance.
+ * @rmtoll CR1 CKD LL_TIM_SetClockDivision
+ * @param TIMx Timer instance
+ * @param ClockDivision This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
+{
+ MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
+}
+
+/**
+ * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
+ * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+ * whether or not the clock division feature is supported by the timer
+ * instance.
+ * @rmtoll CR1 CKD LL_TIM_GetClockDivision
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
+}
+
+/**
+ * @brief Set the counter value.
+ * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @rmtoll CNT CNT LL_TIM_SetCounter
+ * @param TIMx Timer instance
+ * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
+{
+ WRITE_REG(TIMx->CNT, Counter);
+}
+
+/**
+ * @brief Get the counter value.
+ * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @rmtoll CNT CNT LL_TIM_GetCounter
+ * @param TIMx Timer instance
+ * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CNT));
+}
+
+/**
+ * @brief Get the current direction of the counter
+ * @rmtoll CR1 DIR LL_TIM_GetDirection
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_COUNTERDIRECTION_UP
+ * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
+}
+
+/**
+ * @brief Set the prescaler value.
+ * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
+ * @note The prescaler can be changed on the fly as this control register is buffered. The new
+ * prescaler ratio is taken into account at the next update event.
+ * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
+ * @rmtoll PSC PSC LL_TIM_SetPrescaler
+ * @param TIMx Timer instance
+ * @param Prescaler between Min_Data=0 and Max_Data=65535
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
+{
+ WRITE_REG(TIMx->PSC, Prescaler);
+}
+
+/**
+ * @brief Get the prescaler value.
+ * @rmtoll PSC PSC LL_TIM_GetPrescaler
+ * @param TIMx Timer instance
+ * @retval Prescaler value between Min_Data=0 and Max_Data=65535
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->PSC));
+}
+
+/**
+ * @brief Set the auto-reload value.
+ * @note The counter is blocked while the auto-reload value is null.
+ * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
+ * @rmtoll ARR ARR LL_TIM_SetAutoReload
+ * @param TIMx Timer instance
+ * @param AutoReload between Min_Data=0 and Max_Data=65535
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
+{
+ WRITE_REG(TIMx->ARR, AutoReload);
+}
+
+/**
+ * @brief Get the auto-reload value.
+ * @rmtoll ARR ARR LL_TIM_GetAutoReload
+ * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @param TIMx Timer instance
+ * @retval Auto-reload value
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->ARR));
+}
+
+/**
+ * @brief Set the repetition counter value.
+ * @note For advanced timer instances RepetitionCounter can be up to 65535 except for STM32F373xC and STM32F378xx devices.
+ * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a repetition counter.
+ * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
+ * @param TIMx Timer instance
+ * @param RepetitionCounter between Min_Data=0 and Max_Data=255
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
+{
+ WRITE_REG(TIMx->RCR, RepetitionCounter);
+}
+
+/**
+ * @brief Get the repetition counter value.
+ * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a repetition counter.
+ * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
+ * @param TIMx Timer instance
+ * @retval Repetition counter value
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->RCR));
+}
+
+#if defined(TIM_CR1_UIFREMAP)
+/**
+ * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
+ * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
+ * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
+}
+
+/**
+ * @brief Disable update interrupt flag (UIF) remapping.
+ * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
+}
+
+#endif /* TIM_CR1_UIFREMAP */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
+ * @{
+ */
+/**
+ * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
+ * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
+ * they are updated only when a commutation event (COM) occurs.
+ * @note Only on channels that have a complementary output.
+ * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance is able to generate a commutation event.
+ * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
+}
+
+/**
+ * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
+ * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance is able to generate a commutation event.
+ * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
+}
+
+/**
+ * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
+ * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance is able to generate a commutation event.
+ * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
+ * @param TIMx Timer instance
+ * @param CCUpdateSource This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
+ * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
+{
+ MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
+}
+
+/**
+ * @brief Set the trigger of the capture/compare DMA request.
+ * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
+ * @param TIMx Timer instance
+ * @param DMAReqTrigger This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CCDMAREQUEST_CC
+ * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
+{
+ MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
+}
+
+/**
+ * @brief Get actual trigger of the capture/compare DMA request.
+ * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_CCDMAREQUEST_CC
+ * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
+ */
+__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
+}
+
+/**
+ * @brief Set the lock level to freeze the
+ * configuration of several capture/compare parameters.
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * the lock mechanism is supported by a timer instance.
+ * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
+ * @param TIMx Timer instance
+ * @param LockLevel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_LOCKLEVEL_OFF
+ * @arg @ref LL_TIM_LOCKLEVEL_1
+ * @arg @ref LL_TIM_LOCKLEVEL_2
+ * @arg @ref LL_TIM_LOCKLEVEL_3
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
+{
+ MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
+}
+
+/**
+ * @brief Enable capture/compare channels.
+ * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
+ * CCER CC1NE LL_TIM_CC_EnableChannel\n
+ * CCER CC2E LL_TIM_CC_EnableChannel\n
+ * CCER CC2NE LL_TIM_CC_EnableChannel\n
+ * CCER CC3E LL_TIM_CC_EnableChannel\n
+ * CCER CC3NE LL_TIM_CC_EnableChannel\n
+ * CCER CC4E LL_TIM_CC_EnableChannel\n
+ * CCER CC5E LL_TIM_CC_EnableChannel\n
+ * CCER CC6E LL_TIM_CC_EnableChannel
+ * @param TIMx Timer instance
+ * @param Channels This parameter can be a combination of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @note CH5 and CH6 channels are not available for all F3 devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+{
+ SET_BIT(TIMx->CCER, Channels);
+}
+
+/**
+ * @brief Disable capture/compare channels.
+ * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
+ * CCER CC1NE LL_TIM_CC_DisableChannel\n
+ * CCER CC2E LL_TIM_CC_DisableChannel\n
+ * CCER CC2NE LL_TIM_CC_DisableChannel\n
+ * CCER CC3E LL_TIM_CC_DisableChannel\n
+ * CCER CC3NE LL_TIM_CC_DisableChannel\n
+ * CCER CC4E LL_TIM_CC_DisableChannel\n
+ * CCER CC5E LL_TIM_CC_DisableChannel\n
+ * CCER CC6E LL_TIM_CC_DisableChannel
+ * @param TIMx Timer instance
+ * @param Channels This parameter can be a combination of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @note CH5 and CH6 channels are not available for all F3 devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+{
+ CLEAR_BIT(TIMx->CCER, Channels);
+}
+
+/**
+ * @brief Indicate whether channel(s) is(are) enabled.
+ * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC4E LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC5E LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC6E LL_TIM_CC_IsEnabledChannel
+ * @param TIMx Timer instance
+ * @param Channels This parameter can be a combination of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @note CH5 and CH6 channels are not available for all F3 devices
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+{
+ return (READ_BIT(TIMx->CCER, Channels) == (Channels));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
+ * @{
+ */
+/**
+ * @brief Configure an output channel.
+ * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
+ * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
+ * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
+ * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
+ * @if STM32F334x8
+ * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
+ * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
+ * @elseif STM32F303xC
+ * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
+ * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
+ * @elseif STM32F302x8
+ * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
+ * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
+ * @endif
+ * CCER CC1P LL_TIM_OC_ConfigOutput\n
+ * CCER CC2P LL_TIM_OC_ConfigOutput\n
+ * CCER CC3P LL_TIM_OC_ConfigOutput\n
+ * CCER CC4P LL_TIM_OC_ConfigOutput\n
+ * CCER CC5P LL_TIM_OC_ConfigOutput\n
+ * CCER CC6P LL_TIM_OC_ConfigOutput\n
+ * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
+ * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
+ * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
+ * CR2 OIS4 LL_TIM_OC_ConfigOutput\n
+ * CR2 OIS5 LL_TIM_OC_ConfigOutput\n
+ * CR2 OIS6 LL_TIM_OC_ConfigOutput
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @param Configuration This parameter must be a combination of all the following values:
+ * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
+ * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
+ * @note CH3 CH4 CH5 and CH6 channels are not available for all F3 devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
+ MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
+ (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
+ MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
+ (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
+}
+
+/**
+ * @brief Define the behavior of the output reference signal OCxREF from which
+ * OCx and OCxN (when relevant) are derived.
+ * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
+ * CCMR1 OC2M LL_TIM_OC_SetMode\n
+ * CCMR2 OC3M LL_TIM_OC_SetMode\n
+ * CCMR2 OC4M LL_TIM_OC_SetMode\n
+ * @if STM32F334x8
+ * CCMR3 OC5M LL_TIM_OC_SetMode\n
+ * CCMR3 OC6M LL_TIM_OC_SetMode
+ * @elseif STM32F303xC
+ * CCMR3 OC5M LL_TIM_OC_SetMode\n
+ * CCMR3 OC6M LL_TIM_OC_SetMode
+ * @elseif STM32F302x8
+ * CCMR3 OC5M LL_TIM_OC_SetMode\n
+ * CCMR3 OC6M LL_TIM_OC_SetMode
+ * @endif
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_TIM_OCMODE_FROZEN
+ * @arg @ref LL_TIM_OCMODE_ACTIVE
+ * @arg @ref LL_TIM_OCMODE_INACTIVE
+ * @arg @ref LL_TIM_OCMODE_TOGGLE
+ * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
+ * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
+ * @arg @ref LL_TIM_OCMODE_PWM1
+ * @arg @ref LL_TIM_OCMODE_PWM2
+ * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
+ * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
+ * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
+ * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
+ * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
+ * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
+ * @note The following OC modes are not available on all F3 devices :
+ * - LL_TIM_OCMODE_RETRIG_OPM1
+ * - LL_TIM_OCMODE_RETRIG_OPM2
+ * - LL_TIM_OCMODE_COMBINED_PWM1
+ * - LL_TIM_OCMODE_COMBINED_PWM2
+ * - LL_TIM_OCMODE_ASSYMETRIC_PWM1
+ * - LL_TIM_OCMODE_ASSYMETRIC_PWM2
+ * @note CH5 and CH6 channels are not available for all F3 devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
+}
+
+/**
+ * @brief Get the output compare mode of an output channel.
+ * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
+ * CCMR1 OC2M LL_TIM_OC_GetMode\n
+ * CCMR2 OC3M LL_TIM_OC_GetMode\n
+ * CCMR2 OC4M LL_TIM_OC_GetMode\n
+ * @if STM32F334x8
+ * CCMR3 OC5M LL_TIM_OC_GetMode\n
+ * CCMR3 OC6M LL_TIM_OC_GetMode
+ * @elseif STM32F303xC
+ * CCMR3 OC5M LL_TIM_OC_GetMode\n
+ * CCMR3 OC6M LL_TIM_OC_GetMode
+ * @elseif STM32F302x8
+ * CCMR3 OC5M LL_TIM_OC_GetMode\n
+ * CCMR3 OC6M LL_TIM_OC_GetMode
+ * @endif
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @note The following OC modes are not available on all F3 devices :
+ * - LL_TIM_OCMODE_RETRIG_OPM1
+ * - LL_TIM_OCMODE_RETRIG_OPM2
+ * - LL_TIM_OCMODE_COMBINED_PWM1
+ * - LL_TIM_OCMODE_COMBINED_PWM2
+ * - LL_TIM_OCMODE_ASSYMETRIC_PWM1
+ * - LL_TIM_OCMODE_ASSYMETRIC_PWM2
+ * @note CH5 and CH6 channels are not available for all F3 devices
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_OCMODE_FROZEN
+ * @arg @ref LL_TIM_OCMODE_ACTIVE
+ * @arg @ref LL_TIM_OCMODE_INACTIVE
+ * @arg @ref LL_TIM_OCMODE_TOGGLE
+ * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
+ * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
+ * @arg @ref LL_TIM_OCMODE_PWM1
+ * @arg @ref LL_TIM_OCMODE_PWM2
+ * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
+ * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
+ * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
+ * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
+ * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
+ * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
+}
+
+/**
+ * @brief Set the polarity of an output channel.
+ * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
+ * CCER CC1NP LL_TIM_OC_SetPolarity\n
+ * CCER CC2P LL_TIM_OC_SetPolarity\n
+ * CCER CC2NP LL_TIM_OC_SetPolarity\n
+ * CCER CC3P LL_TIM_OC_SetPolarity\n
+ * CCER CC3NP LL_TIM_OC_SetPolarity\n
+ * CCER CC4P LL_TIM_OC_SetPolarity\n
+ * CCER CC5P LL_TIM_OC_SetPolarity\n
+ * CCER CC6P LL_TIM_OC_SetPolarity
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_TIM_OCPOLARITY_HIGH
+ * @arg @ref LL_TIM_OCPOLARITY_LOW
+ * @note CH5 and CH6 channels are not available for all F3 devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+ * @brief Get the polarity of an output channel.
+ * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
+ * CCER CC1NP LL_TIM_OC_GetPolarity\n
+ * CCER CC2P LL_TIM_OC_GetPolarity\n
+ * CCER CC2NP LL_TIM_OC_GetPolarity\n
+ * CCER CC3P LL_TIM_OC_GetPolarity\n
+ * CCER CC3NP LL_TIM_OC_GetPolarity\n
+ * CCER CC4P LL_TIM_OC_GetPolarity\n
+ * CCER CC5P LL_TIM_OC_GetPolarity\n
+ * CCER CC6P LL_TIM_OC_GetPolarity
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @note CH5 and CH6 channels are not available for all F3 devices
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_OCPOLARITY_HIGH
+ * @arg @ref LL_TIM_OCPOLARITY_LOW
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+ * @brief Set the IDLE state of an output channel
+ * @note This function is significant only for the timer instances
+ * supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx)
+ * can be used to check whether or not a timer instance provides
+ * a break input.
+ * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
+ * CR2 OIS2N LL_TIM_OC_SetIdleState\n
+ * CR2 OIS2 LL_TIM_OC_SetIdleState\n
+ * CR2 OIS2N LL_TIM_OC_SetIdleState\n
+ * CR2 OIS3 LL_TIM_OC_SetIdleState\n
+ * CR2 OIS3N LL_TIM_OC_SetIdleState\n
+ * CR2 OIS4 LL_TIM_OC_SetIdleState\n
+ * CR2 OIS5 LL_TIM_OC_SetIdleState\n
+ * CR2 OIS6 LL_TIM_OC_SetIdleState
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @param IdleState This parameter can be one of the following values:
+ * @arg @ref LL_TIM_OCIDLESTATE_LOW
+ * @arg @ref LL_TIM_OCIDLESTATE_HIGH
+ * @note CH5 and CH6 channels are not available for all F3 devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
+}
+
+/**
+ * @brief Get the IDLE state of an output channel
+ * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
+ * CR2 OIS2N LL_TIM_OC_GetIdleState\n
+ * CR2 OIS2 LL_TIM_OC_GetIdleState\n
+ * CR2 OIS2N LL_TIM_OC_GetIdleState\n
+ * CR2 OIS3 LL_TIM_OC_GetIdleState\n
+ * CR2 OIS3N LL_TIM_OC_GetIdleState\n
+ * CR2 OIS4 LL_TIM_OC_GetIdleState\n
+ * CR2 OIS5 LL_TIM_OC_GetIdleState\n
+ * CR2 OIS6 LL_TIM_OC_GetIdleState
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @note CH5 and CH6 channels are not available for all F3 devices
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_OCIDLESTATE_LOW
+ * @arg @ref LL_TIM_OCIDLESTATE_HIGH
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
+}
+
+/**
+ * @brief Enable fast mode for the output channel.
+ * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
+ * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
+ * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
+ * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
+ * CCMR2 OC4FE LL_TIM_OC_EnableFast\n
+ * @if STM32F334x8
+ * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
+ * CCMR3 OC6FE LL_TIM_OC_EnableFast
+ * @elseif STM32F303xC
+ * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
+ * CCMR3 OC6FE LL_TIM_OC_EnableFast
+ * @elseif STM32F302x8
+ * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
+ * CCMR3 OC6FE LL_TIM_OC_EnableFast
+ * @endif
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @note OC5FE and OC6FE are not available for all F3 devices
+ * @note CH5 and CH6 channels are not available for all F3 devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
+
+}
+
+/**
+ * @brief Disable fast mode for the output channel.
+ * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
+ * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
+ * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
+ * CCMR2 OC4FE LL_TIM_OC_DisableFast\n
+ * @if STM32F334x8
+ * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
+ * CCMR3 OC6FE LL_TIM_OC_DisableFast
+ * @elseif STM32F303xC
+ * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
+ * CCMR3 OC6FE LL_TIM_OC_DisableFast
+ * @elseif STM32F302x8
+ * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
+ * CCMR3 OC6FE LL_TIM_OC_DisableFast
+ * @endif
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @note OC5FE and OC6FE are not available for all F3 devices
+ * @note CH5 and CH6 channels are not available for all F3 devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
+
+}
+
+/**
+ * @brief Indicates whether fast mode is enabled for the output channel.
+ * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
+ * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
+ * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
+ * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
+ * @if STM32F334x8
+ * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
+ * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
+ * @elseif STM32F303xC
+ * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
+ * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
+ * @elseif STM32F302x8
+ * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
+ * CCMR3 OC6FE LL_TIM_OC_DisableFast
+ * @endif
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @note OC5FE and OC6FE are not available for all F3 devices
+ * @note CH5 and CH6 channels are not available for all F3 devices
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
+ return (READ_BIT(*pReg, bitfield) == bitfield);
+}
+
+/**
+ * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
+ * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
+ * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
+ * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
+ * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
+ * @if STM32F334x8
+ * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
+ * CCMR3 OC6PE LL_TIM_OC_EnablePreload
+ * @elseif STM32F303xC
+ * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
+ * CCMR3 OC6PE LL_TIM_OC_EnablePreload
+ * @elseif STM32F302x8
+ * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
+ * CCMR3 OC6PE LL_TIM_OC_EnablePreload
+ * @endif
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @note OC5PE and OC6PE are not available for all F3 devices
+ * @note CH5 and CH6 channels are not available for all F3 devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+ * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
+ * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
+ * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
+ * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
+ * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
+ * @if STM32F334x8
+ * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
+ * CCMR3 OC6PE LL_TIM_OC_DisablePreload
+ * @elseif STM32F303xC
+ * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
+ * CCMR3 OC6PE LL_TIM_OC_DisablePreload
+ * @elseif STM32F302x8
+ * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
+ * CCMR3 OC6PE LL_TIM_OC_DisablePreload
+ * @endif
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @note OC5PE and OC6PE are not available for all F3 devices
+ * @note CH5 and CH6 channels are not available for all F3 devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+ * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
+ * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
+ * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
+ * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
+ * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
+ * @if STM32F334x8
+ * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
+ * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
+ * @elseif STM32F303xC
+ * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
+ * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
+ * @elseif STM32F302x8
+ * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
+ * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
+ * @endif
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @note OC5PE and OC6PE are not available for all F3 devices
+ * @note CH5 and CH6 channels are not available for all F3 devices
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
+ return (READ_BIT(*pReg, bitfield) == bitfield);
+}
+
+/**
+ * @brief Enable clearing the output channel on an external event.
+ * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
+ * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+ * or not a timer instance can clear the OCxREF signal on an external event.
+ * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
+ * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
+ * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
+ * CCMR2 OC4CE LL_TIM_OC_EnableClear\n
+ * @if STM32F334x8
+ * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
+ * CCMR3 OC6CE LL_TIM_OC_EnableClear
+ * @elseif STM32F303xC
+ * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
+ * CCMR3 OC6CE LL_TIM_OC_EnableClear
+ * @elseif STM32F302x8
+ * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
+ * CCMR3 OC6CE LL_TIM_OC_EnableClear
+ * @endif
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @note OC5CE and OC6CE are not available for all F3 devices
+ * @note CH5 and CH6 channels are not available for all F3 devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+ * @brief Disable clearing the output channel on an external event.
+ * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+ * or not a timer instance can clear the OCxREF signal on an external event.
+ * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
+ * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
+ * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
+ * CCMR2 OC4CE LL_TIM_OC_DisableClear\n
+ * @if STM32F334x8
+ * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
+ * CCMR3 OC6CE LL_TIM_OC_DisableClear
+ * @elseif STM32F303xC
+ * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
+ * CCMR3 OC6CE LL_TIM_OC_DisableClear
+ * @elseif STM32F302x8
+ * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
+ * CCMR3 OC6CE LL_TIM_OC_DisableClear
+ * @endif
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @note OC5CE and OC6CE are not available for all F3 devices
+ * @note CH5 and CH6 channels are not available for all F3 devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+ * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
+ * @note This function enables clearing the output channel on an external event.
+ * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
+ * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+ * or not a timer instance can clear the OCxREF signal on an external event.
+ * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
+ * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
+ * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
+ * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
+ * @if STM32F334x8
+ * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
+ * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
+ * @elseif STM32F303xC
+ * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
+ * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
+ * @elseif STM32F302x8
+ * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
+ * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
+ * @endif
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @note OC5CE and OC6CE are not available for all F3 devices
+ * @note CH5 and CH6 channels are not available for all F3 devices
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
+ return (READ_BIT(*pReg, bitfield) == bitfield);
+}
+
+/**
+ * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge if the Ocx and OCxN signals).
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * dead-time insertion feature is supported by a timer instance.
+ * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
+ * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
+ * @param TIMx Timer instance
+ * @param DeadTime between Min_Data=0 and Max_Data=255
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
+{
+ MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
+}
+
+/**
+ * @brief Set compare value for output channel 1 (TIMx_CCR1).
+ * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 1 is supported by a timer instance.
+ * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
+ * @param TIMx Timer instance
+ * @param CompareValue between Min_Data=0 and Max_Data=65535
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+ WRITE_REG(TIMx->CCR1, CompareValue);
+}
+
+/**
+ * @brief Set compare value for output channel 2 (TIMx_CCR2).
+ * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 2 is supported by a timer instance.
+ * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
+ * @param TIMx Timer instance
+ * @param CompareValue between Min_Data=0 and Max_Data=65535
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+ WRITE_REG(TIMx->CCR2, CompareValue);
+}
+
+/**
+ * @brief Set compare value for output channel 3 (TIMx_CCR3).
+ * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+ * output channel is supported by a timer instance.
+ * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
+ * @param TIMx Timer instance
+ * @param CompareValue between Min_Data=0 and Max_Data=65535
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+ WRITE_REG(TIMx->CCR3, CompareValue);
+}
+
+/**
+ * @brief Set compare value for output channel 4 (TIMx_CCR4).
+ * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 4 is supported by a timer instance.
+ * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
+ * @param TIMx Timer instance
+ * @param CompareValue between Min_Data=0 and Max_Data=65535
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+ WRITE_REG(TIMx->CCR4, CompareValue);
+}
+
+#if defined(TIM_CCR5_CCR5)
+/**
+ * @brief Set compare value for output channel 5 (TIMx_CCR5).
+ * @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 5 is supported by a timer instance.
+ * @if STM32F334x8
+ * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
+ * @elseif STM32F303xC
+ * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
+ * @elseif STM32F302x8
+ * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
+ * @endif
+ * @param TIMx Timer instance
+ * @param CompareValue between Min_Data=0 and Max_Data=65535
+ * @note CH5 channel is not available for all F3 devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+ WRITE_REG(TIMx->CCR5, CompareValue);
+}
+
+#endif /* TIM_CCR5_CCR5 */
+#if defined(TIM_CCR6_CCR6)
+/**
+ * @brief Set compare value for output channel 6 (TIMx_CCR6).
+ * @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 6 is supported by a timer instance.
+ * @if STM32F344x8
+ * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
+ * @elseif STM32F303xC
+ * CCR6 CCR6 LL_TIM_OC_SetCompareCH6
+ * @elseif STM32F302x8
+ * CCR6 CCR6 LL_TIM_OC_SetCompareCH6
+ * @endif
+ * @param TIMx Timer instance
+ * @param CompareValue between Min_Data=0 and Max_Data=65535
+ * @note CH6 channel is not available for all F3 devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+ WRITE_REG(TIMx->CCR6, CompareValue);
+}
+
+#endif /* TIM_CCR6_CCR6 */
+/**
+ * @brief Get compare value (TIMx_CCR1) set for output channel 1.
+ * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 1 is supported by a timer instance.
+ * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
+ * @param TIMx Timer instance
+ * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR1));
+}
+
+/**
+ * @brief Get compare value (TIMx_CCR2) set for output channel 2.
+ * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 2 is supported by a timer instance.
+ * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
+ * @param TIMx Timer instance
+ * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR2));
+}
+
+/**
+ * @brief Get compare value (TIMx_CCR3) set for output channel 3.
+ * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 3 is supported by a timer instance.
+ * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
+ * @param TIMx Timer instance
+ * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR3));
+}
+
+/**
+ * @brief Get compare value (TIMx_CCR4) set for output channel 4.
+ * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 4 is supported by a timer instance.
+ * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
+ * @param TIMx Timer instance
+ * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR4));
+}
+
+#if defined(TIM_CCR5_CCR5)
+/**
+ * @brief Get compare value (TIMx_CCR5) set for output channel 5.
+ * @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 5 is supported by a timer instance.
+ * @if STM32F334x8
+ * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
+ * @elseif STM32F303xC
+ * CCR5 CCR5 LL_TIM_OC_GetCompareCH5
+ * @elseif STM32F302x8
+ * CCR5 CCR5 LL_TIM_OC_GetCompareCH5
+ * @endif
+ * @param TIMx Timer instance
+ * @note CH5 channel is not available for all F3 devices
+ * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR5));
+}
+
+#endif /* TIM_CCR5_CCR5 */
+#if defined(TIM_CCR6_CCR6)
+/**
+ * @brief Get compare value (TIMx_CCR6) set for output channel 6.
+ * @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 6 is supported by a timer instance.
+ * @if STM32F334x8
+ * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
+ * @elseif STM32F303xC
+ * CCR6 CCR6 LL_TIM_OC_GetCompareCH6
+ * @elseif STM32F302x8
+ * CCR6 CCR6 LL_TIM_OC_GetCompareCH6
+ * @endif
+ * @param TIMx Timer instance
+ * @note CH6 channel is not available for all F3 devices
+ * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR6));
+}
+
+#endif /* TIM_CCR6_CCR6 */
+#if defined(TIM_CCR5_CCR5)
+/**
+ * @brief Select on which reference signal the OC5REF is combined to.
+ * @note Macro @ref IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports the combined 3-phase PWM mode.
+ * @if STM32F334x8
+ * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
+ * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
+ * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
+ * @elseif STM32F303xC
+ * CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
+ * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
+ * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
+ * @elseif STM32F302x8
+ * CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
+ * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
+ * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
+ * @endif
+ * @param TIMx Timer instance
+ * @param GroupCH5 This parameter can be one of the following values:
+ * @arg @ref LL_TIM_GROUPCH5_NONE
+ * @arg @ref LL_TIM_GROUPCH5_OC1REFC
+ * @arg @ref LL_TIM_GROUPCH5_OC2REFC
+ * @arg @ref LL_TIM_GROUPCH5_OC3REFC
+ * @note CH5 channel is not available for all F3 devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
+{
+ MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, GroupCH5);
+}
+
+#endif /* TIM_CCR5_CCR5 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
+ * @{
+ */
+/**
+ * @brief Configure input channel.
+ * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
+ * CCMR1 IC1PSC LL_TIM_IC_Config\n
+ * CCMR1 IC1F LL_TIM_IC_Config\n
+ * CCMR1 CC2S LL_TIM_IC_Config\n
+ * CCMR1 IC2PSC LL_TIM_IC_Config\n
+ * CCMR1 IC2F LL_TIM_IC_Config\n
+ * CCMR2 CC3S LL_TIM_IC_Config\n
+ * CCMR2 IC3PSC LL_TIM_IC_Config\n
+ * CCMR2 IC3F LL_TIM_IC_Config\n
+ * CCMR2 CC4S LL_TIM_IC_Config\n
+ * CCMR2 IC4PSC LL_TIM_IC_Config\n
+ * CCMR2 IC4F LL_TIM_IC_Config\n
+ * CCER CC1P LL_TIM_IC_Config\n
+ * CCER CC1NP LL_TIM_IC_Config\n
+ * CCER CC2P LL_TIM_IC_Config\n
+ * CCER CC2NP LL_TIM_IC_Config\n
+ * CCER CC3P LL_TIM_IC_Config\n
+ * CCER CC3NP LL_TIM_IC_Config\n
+ * CCER CC4P LL_TIM_IC_Config\n
+ * CCER CC4NP LL_TIM_IC_Config
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param Configuration This parameter must be a combination of all the following values:
+ * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
+ * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
+ * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
+ ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
+ MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
+ (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+ * @brief Set the active input.
+ * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
+ * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
+ * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
+ * CCMR2 CC4S LL_TIM_IC_SetActiveInput
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param ICActiveInput This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
+ * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
+ * @arg @ref LL_TIM_ACTIVEINPUT_TRC
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+ * @brief Get the current active input.
+ * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
+ * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
+ * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
+ * CCMR2 CC4S LL_TIM_IC_GetActiveInput
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
+ * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
+ * @arg @ref LL_TIM_ACTIVEINPUT_TRC
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+ * @brief Set the prescaler of input channel.
+ * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
+ * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
+ * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
+ * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param ICPrescaler This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ICPSC_DIV1
+ * @arg @ref LL_TIM_ICPSC_DIV2
+ * @arg @ref LL_TIM_ICPSC_DIV4
+ * @arg @ref LL_TIM_ICPSC_DIV8
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+ * @brief Get the current prescaler value acting on an input channel.
+ * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
+ * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
+ * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
+ * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_ICPSC_DIV1
+ * @arg @ref LL_TIM_ICPSC_DIV2
+ * @arg @ref LL_TIM_ICPSC_DIV4
+ * @arg @ref LL_TIM_ICPSC_DIV8
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+ * @brief Set the input filter duration.
+ * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
+ * CCMR1 IC2F LL_TIM_IC_SetFilter\n
+ * CCMR2 IC3F LL_TIM_IC_SetFilter\n
+ * CCMR2 IC4F LL_TIM_IC_SetFilter
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param ICFilter This parameter can be one of the following values:
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
+ * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
+ * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+ * @brief Get the input filter duration.
+ * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
+ * CCMR1 IC2F LL_TIM_IC_GetFilter\n
+ * CCMR2 IC3F LL_TIM_IC_GetFilter\n
+ * CCMR2 IC4F LL_TIM_IC_GetFilter
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
+ * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
+ * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+ * @brief Set the input channel polarity.
+ * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
+ * CCER CC1NP LL_TIM_IC_SetPolarity\n
+ * CCER CC2P LL_TIM_IC_SetPolarity\n
+ * CCER CC2NP LL_TIM_IC_SetPolarity\n
+ * CCER CC3P LL_TIM_IC_SetPolarity\n
+ * CCER CC3NP LL_TIM_IC_SetPolarity\n
+ * CCER CC4P LL_TIM_IC_SetPolarity\n
+ * CCER CC4NP LL_TIM_IC_SetPolarity
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param ICPolarity This parameter can be one of the following values:
+ * @arg @ref LL_TIM_IC_POLARITY_RISING
+ * @arg @ref LL_TIM_IC_POLARITY_FALLING
+ * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
+ ICPolarity << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+ * @brief Get the current input channel polarity.
+ * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
+ * CCER CC1NP LL_TIM_IC_GetPolarity\n
+ * CCER CC2P LL_TIM_IC_GetPolarity\n
+ * CCER CC2NP LL_TIM_IC_GetPolarity\n
+ * CCER CC3P LL_TIM_IC_GetPolarity\n
+ * CCER CC3NP LL_TIM_IC_GetPolarity\n
+ * CCER CC4P LL_TIM_IC_GetPolarity\n
+ * CCER CC4NP LL_TIM_IC_GetPolarity
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_IC_POLARITY_RISING
+ * @arg @ref LL_TIM_IC_POLARITY_FALLING
+ * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
+ SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+ * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
+ * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an XOR input.
+ * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
+}
+
+/**
+ * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
+ * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an XOR input.
+ * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
+}
+
+/**
+ * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
+ * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an XOR input.
+ * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S));
+}
+
+/**
+ * @brief Get captured value for input channel 1.
+ * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+ * input channel 1 is supported by a timer instance.
+ * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
+ * @param TIMx Timer instance
+ * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR1));
+}
+
+/**
+ * @brief Get captured value for input channel 2.
+ * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+ * input channel 2 is supported by a timer instance.
+ * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
+ * @param TIMx Timer instance
+ * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR2));
+}
+
+/**
+ * @brief Get captured value for input channel 3.
+ * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+ * input channel 3 is supported by a timer instance.
+ * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
+ * @param TIMx Timer instance
+ * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR3));
+}
+
+/**
+ * @brief Get captured value for input channel 4.
+ * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+ * input channel 4 is supported by a timer instance.
+ * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
+ * @param TIMx Timer instance
+ * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR4));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
+ * @{
+ */
+/**
+ * @brief Enable external clock mode 2.
+ * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
+ * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports external clock mode2.
+ * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
+}
+
+/**
+ * @brief Disable external clock mode 2.
+ * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports external clock mode2.
+ * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
+}
+
+/**
+ * @brief Indicate whether external clock mode 2 is enabled.
+ * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports external clock mode2.
+ * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE));
+}
+
+/**
+ * @brief Set the clock source of the counter clock.
+ * @note when selected clock source is external clock mode 1, the timer input
+ * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
+ * function. This timer input must be configured by calling
+ * the @ref LL_TIM_IC_Config() function.
+ * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports external clock mode1.
+ * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports external clock mode2.
+ * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
+ * SMCR ECE LL_TIM_SetClockSource
+ * @param TIMx Timer instance
+ * @param ClockSource This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
+ * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
+ * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
+{
+ MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
+}
+
+/**
+ * @brief Set the encoder interface mode.
+ * @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports the encoder mode.
+ * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
+ * @param TIMx Timer instance
+ * @param EncoderMode This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
+ * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
+ * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
+{
+ MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
+ * @{
+ */
+/**
+ * @brief Set the trigger output (TRGO) used for timer synchronization .
+ * @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance can operate as a master timer.
+ * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
+ * @param TIMx Timer instance
+ * @param TimerSynchronization This parameter can be one of the following values:
+ * @arg @ref LL_TIM_TRGO_RESET
+ * @arg @ref LL_TIM_TRGO_ENABLE
+ * @arg @ref LL_TIM_TRGO_UPDATE
+ * @arg @ref LL_TIM_TRGO_CC1IF
+ * @arg @ref LL_TIM_TRGO_OC1REF
+ * @arg @ref LL_TIM_TRGO_OC2REF
+ * @arg @ref LL_TIM_TRGO_OC3REF
+ * @arg @ref LL_TIM_TRGO_OC4REF
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
+{
+ MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
+}
+
+#if defined(TIM_CR2_MMS2)
+/**
+ * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
+ * @note Macro @ref IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance can be used for ADC synchronization.
+ * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
+ * @param TIMx Timer Instance
+ * @param ADCSynchronization This parameter can be one of the following values:
+ * @arg @ref LL_TIM_TRGO2_RESET
+ * @arg @ref LL_TIM_TRGO2_ENABLE
+ * @arg @ref LL_TIM_TRGO2_UPDATE
+ * @arg @ref LL_TIM_TRGO2_CC1F
+ * @arg @ref LL_TIM_TRGO2_OC1
+ * @arg @ref LL_TIM_TRGO2_OC2
+ * @arg @ref LL_TIM_TRGO2_OC3
+ * @arg @ref LL_TIM_TRGO2_OC4
+ * @arg @ref LL_TIM_TRGO2_OC5
+ * @arg @ref LL_TIM_TRGO2_OC6
+ * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
+ * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
+ * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
+ * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
+ * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
+ * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
+ * @note OC5 and OC6 are not available for all F3 devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
+{
+ MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
+}
+
+#endif /* TIM_CR2_MMS2 */
+/**
+ * @brief Set the synchronization mode of a slave timer.
+ * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance can operate as a slave timer.
+ * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
+ * @param TIMx Timer instance
+ * @param SlaveMode This parameter can be one of the following values:
+ * @arg @ref LL_TIM_SLAVEMODE_DISABLED
+ * @arg @ref LL_TIM_SLAVEMODE_RESET
+ * @arg @ref LL_TIM_SLAVEMODE_GATED
+ * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
+ * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
+{
+ MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
+}
+
+/**
+ * @brief Set the selects the trigger input to be used to synchronize the counter.
+ * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance can operate as a slave timer.
+ * @rmtoll SMCR TS LL_TIM_SetTriggerInput
+ * @param TIMx Timer instance
+ * @param TriggerInput This parameter can be one of the following values:
+ * @arg @ref LL_TIM_TS_ITR0
+ * @arg @ref LL_TIM_TS_ITR1
+ * @arg @ref LL_TIM_TS_ITR2
+ * @arg @ref LL_TIM_TS_ITR3
+ * @arg @ref LL_TIM_TS_TI1F_ED
+ * @arg @ref LL_TIM_TS_TI1FP1
+ * @arg @ref LL_TIM_TS_TI2FP2
+ * @arg @ref LL_TIM_TS_ETRF
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
+{
+ MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
+}
+
+/**
+ * @brief Enable the Master/Slave mode.
+ * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance can operate as a slave timer.
+ * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
+}
+
+/**
+ * @brief Disable the Master/Slave mode.
+ * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance can operate as a slave timer.
+ * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
+}
+
+/**
+ * @brief Indicates whether the Master/Slave mode is enabled.
+ * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance can operate as a slave timer.
+ * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM));
+}
+
+/**
+ * @brief Configure the external trigger (ETR) input.
+ * @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an external trigger input.
+ * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
+ * SMCR ETPS LL_TIM_ConfigETR\n
+ * SMCR ETF LL_TIM_ConfigETR
+ * @param TIMx Timer instance
+ * @param ETRPolarity This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
+ * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
+ * @param ETRPrescaler This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
+ * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
+ * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
+ * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
+ * @param ETRFilter This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV1
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
+ uint32_t ETRFilter)
+{
+ MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_Break_Function Break function configuration
+ * @{
+ */
+/**
+ * @brief Enable the break function.
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR BKE LL_TIM_EnableBRK
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
+{
+ __IO uint32_t tmpreg;
+
+ SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
+
+ /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
+ tmpreg = READ_REG(TIMx->BDTR);
+ (void)(tmpreg);
+}
+
+/**
+ * @brief Disable the break function.
+ * @rmtoll BDTR BKE LL_TIM_DisableBRK
+ * @param TIMx Timer instance
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
+{
+ __IO uint32_t tmpreg;
+
+ CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
+
+ /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
+ tmpreg = READ_REG(TIMx->BDTR);
+ (void)(tmpreg);
+}
+
+#if defined(TIM_BDTR_BKF)
+/**
+ * @brief Configure the break input.
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
+ * BDTR BKF LL_TIM_ConfigBRK
+ * @param TIMx Timer instance
+ * @param BreakPolarity This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BREAK_POLARITY_LOW
+ * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
+ * @param BreakFilter This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV1
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter)
+{
+ MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter);
+}
+
+#else
+/**
+ * @brief Configure the break input.
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR BKP LL_TIM_ConfigBRK
+ * @param TIMx Timer instance
+ * @param BreakPolarity This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BREAK_POLARITY_LOW
+ * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity)
+{
+ __IO uint32_t tmpreg;
+
+ MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity);
+
+ /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
+ tmpreg = READ_REG(TIMx->BDTR);
+ (void)(tmpreg);
+}
+
+#endif /* TIM_BDTR_BKF */
+#if defined(TIM_BDTR_BK2E)
+/**
+ * @brief Enable the break 2 function.
+ * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a second break input.
+ * @rmtoll BDTR BK2E LL_TIM_EnableBRK2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
+}
+
+/**
+ * @brief Disable the break 2 function.
+ * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a second break input.
+ * @rmtoll BDTR BK2E LL_TIM_DisableBRK2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
+}
+
+/**
+ * @brief Configure the break 2 input.
+ * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a second break input.
+ * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
+ * BDTR BK2F LL_TIM_ConfigBRK2
+ * @param TIMx Timer instance
+ * @param Break2Polarity This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BREAK2_POLARITY_LOW
+ * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
+ * @param Break2Filter This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter)
+{
+ MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter);
+}
+
+#endif /* TIM_BDTR_BK2E */
+/**
+ * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
+ * BDTR OSSR LL_TIM_SetOffStates
+ * @param TIMx Timer instance
+ * @param OffStateIdle This parameter can be one of the following values:
+ * @arg @ref LL_TIM_OSSI_DISABLE
+ * @arg @ref LL_TIM_OSSI_ENABLE
+ * @param OffStateRun This parameter can be one of the following values:
+ * @arg @ref LL_TIM_OSSR_DISABLE
+ * @arg @ref LL_TIM_OSSR_ENABLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
+{
+ MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
+}
+
+/**
+ * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
+}
+
+/**
+ * @brief Disable automatic output (MOE can be set only by software).
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
+}
+
+/**
+ * @brief Indicate whether automatic output is enabled.
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE));
+}
+
+/**
+ * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
+ * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
+ * software and is reset in case of break or break2 event
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
+}
+
+/**
+ * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
+ * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
+ * software and is reset in case of break or break2 event.
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
+}
+
+/**
+ * @brief Indicates whether outputs are enabled.
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
+ * @{
+ */
+/**
+ * @brief Configures the timer DMA burst feature.
+ * @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
+ * not a timer instance supports the DMA burst mode.
+ * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
+ * DCR DBA LL_TIM_ConfigDMABurst
+ * @param TIMx Timer instance
+ * @param DMABurstBaseAddress This parameter can be one of the following values:
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 (*)
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5 (*)
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6 (*)
+ * (*) value not defined in all devices
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_OR
+ * @param DMABurstLength This parameter can be one of the following values:
+ * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
+ * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
+{
+ MODIFY_REG(TIMx->DCR, TIM_DCR_DBL | TIM_DCR_DBA, DMABurstBaseAddress | DMABurstLength);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
+ * @{
+ */
+/**
+ * @brief Remap TIM inputs (input channel, internal/external triggers).
+ * @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
+ * a some timer inputs can be remapped.
+ * @if STM32F334x8
+ * @rmtoll TIM1_OR ETR_RMP LL_TIM_SetRemap\n
+ * TIM16_OR TI1_RMP LL_TIM_SetRemap\n
+ * @elseif STM32F302x8
+ * @rmtoll TIM1_OR ETR_RMP LL_TIM_SetRemap\n
+ * TIM16_OR TI1_RMP LL_TIM_SetRemap\n
+ * @elseif STM32F303xC
+ * @rmtoll TIM1_OR ETR_RMP LL_TIM_SetRemap\n
+ * TIM8_OR ETR_RMP LL_TIM_SetRemap\n
+ * TIM20_OR ETR_RMP LL_TIM_SetRemap\n
+ * @elseif STM32F373xC
+ * @rmtoll TIM14_OR TI1_RMP LL_TIM_SetRemap
+ * @endif
+ * @param TIMx Timer instance
+ * @param Remap Remap params depends on the TIMx. Description available only
+ * in CHM version of the User Manual (not in .pdf).
+ * Otherwise see Reference Manual description of OR registers.
+ *
+ * Below description summarizes "Timer Instance" and "Remap" param combinations:
+ *
+ * TIM1: any combination of ETR_RMP where (**)
+ *
+ * . . ETR_RMP can be one of the following values
+ * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_NC
+ * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 (*)
+ * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 (*)
+ * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 (*)
+ * @arg @ref LL_TIM_TIM1_ETR_ADC2_RMP_NC (*)
+ * @arg @ref LL_TIM_TIM1_ETR_ADC2_RMP_AWD1 (*)
+ * @arg @ref LL_TIM_TIM1_ETR_ADC2_RMP_AWD2 (*)
+ * @arg @ref LL_TIM_TIM1_ETR_ADC2_RMP_AWD3 (*)
+ * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_NC (*)
+ * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD1 (*)
+ * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD2 (*)
+ * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD3 (*)
+ *
+ * TIM8: any combination of ETR_RMP where (**)
+ *
+ * . . ETR_RMP can be one of the following values
+ * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_NC (*)
+ * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD1 (*)
+ * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD2 (*)
+ * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD3 (*)
+ * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_NC (*)
+ * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD1 (*)
+ * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD2 (*)
+ * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD3 (*)
+ *
+ * TIM14: any combination of TI1_RMP where (**)
+ *
+ * . . TI1_RMP can be one of the following values
+ * @arg @ref LL_TIM_TIM14_TI1_RMP_GPIO (*)
+ * @arg @ref LL_TIM_TIM14_TI1_RMP_RTC_CLK (*)
+ * @arg @ref LL_TIM_TIM14_TI1_RMP_HSE (*)
+ * @arg @ref LL_TIM_TIM14_TI1_RMP_MCO (*)
+ *
+ * TIM16: any combination of TI1_RMP where (**)
+ *
+ * . . TI1_RMP can be one of the following values
+ * @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO (*)
+ * @arg @ref LL_TIM_TIM16_TI1_RMP_LSI (*)
+ * @arg @ref LL_TIM_TIM16_TI1_RMP_LSE (*)
+ * @arg @ref LL_TIM_TIM16_TI1_RMP_RTC (*)
+ *
+ * TIM20: any combination of ETR_RMP where (**)
+ *
+ * . . ETR_RMP can be one of the following values
+ * @arg @ref LL_TIM_TIM20_ETR_ADC3_RMP_NC (*)
+ * @arg @ref LL_TIM_TIM20_ETR_ADC3_RMP_AWD1 (*)
+ * @arg @ref LL_TIM_TIM20_ETR_ADC3_RMP_AWD2 (*)
+ * @arg @ref LL_TIM_TIM20_ETR_ADC3_RMP_AWD3 (*)
+ * @arg @ref LL_TIM_TIM20_ETR_ADC4_RMP_NC (*)
+ * @arg @ref LL_TIM_TIM20_ETR_ADC4_RMP_AWD1 (*)
+ * @arg @ref LL_TIM_TIM20_ETR_ADC4_RMP_AWD2 (*)
+ * @arg @ref LL_TIM_TIM20_ETR_ADC4_RMP_AWD3 (*)
+ *
+ * (*) Value not defined in all devices. \n
+ * (**) Register not available in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
+{
+ MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
+}
+
+/**
+ * @}
+ */
+
+#if defined(TIM_SMCR_OCCS)
+/** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
+ * @{
+ */
+/**
+ * @brief Set the OCREF clear input source
+ * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
+ * @note This function can only be used in Output compare and PWM modes.
+ * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
+ * @param TIMx Timer instance
+ * @param OCRefClearInputSource This parameter can be one of the following values:
+ * @arg @ref LL_TIM_OCREF_CLR_INT_OCREF_CLR
+ * @arg @ref LL_TIM_OCREF_CLR_INT_ETR
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
+{
+ MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource);
+}
+/**
+ * @}
+ */
+#endif /* TIM_SMCR_OCCS */
+
+/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
+ * @{
+ */
+/**
+ * @brief Clear the update interrupt flag (UIF).
+ * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
+}
+
+/**
+ * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
+ * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF));
+}
+
+/**
+ * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
+ * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
+ * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF));
+}
+
+/**
+ * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
+ * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
+ * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF));
+}
+
+/**
+ * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
+ * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
+ * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF));
+}
+
+/**
+ * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
+ * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
+ * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF));
+}
+
+#if defined (TIM_SR_CC5IF)
+/**
+ * @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
+ * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
+ * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF));
+}
+
+#endif /* TIM_SR_CC5IF */
+#if defined (TIM_SR_CC6IF)
+/**
+ * @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
+ * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
+ * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF));
+}
+
+#endif /* TIM_SR_CC6IF */
+/**
+ * @brief Clear the commutation interrupt flag (COMIF).
+ * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
+}
+
+/**
+ * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
+ * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF));
+}
+
+/**
+ * @brief Clear the trigger interrupt flag (TIF).
+ * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
+}
+
+/**
+ * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
+ * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF));
+}
+
+/**
+ * @brief Clear the break interrupt flag (BIF).
+ * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
+}
+
+/**
+ * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
+ * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF));
+}
+
+#if defined(TIM_SR_B2IF)
+/**
+ * @brief Clear the break 2 interrupt flag (B2IF).
+ * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
+}
+
+/**
+ * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
+ * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF));
+}
+
+#endif /* TIM_SR_B2IF */
+/**
+ * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
+ * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
+ * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF));
+}
+
+/**
+ * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
+ * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
+ * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF));
+}
+
+/**
+ * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
+ * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
+ * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF));
+}
+
+/**
+ * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
+ * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
+ * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_IT_Management IT-Management
+ * @{
+ */
+/**
+ * @brief Enable update interrupt (UIE).
+ * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_UIE);
+}
+
+/**
+ * @brief Disable update interrupt (UIE).
+ * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
+}
+
+/**
+ * @brief Indicates whether the update interrupt (UIE) is enabled.
+ * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE));
+}
+
+/**
+ * @brief Enable capture/compare 1 interrupt (CC1IE).
+ * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
+}
+
+/**
+ * @brief Disable capture/compare 1 interrupt (CC1IE).
+ * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
+ * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE));
+}
+
+/**
+ * @brief Enable capture/compare 2 interrupt (CC2IE).
+ * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
+}
+
+/**
+ * @brief Disable capture/compare 2 interrupt (CC2IE).
+ * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
+ * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE));
+}
+
+/**
+ * @brief Enable capture/compare 3 interrupt (CC3IE).
+ * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
+}
+
+/**
+ * @brief Disable capture/compare 3 interrupt (CC3IE).
+ * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
+ * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE));
+}
+
+/**
+ * @brief Enable capture/compare 4 interrupt (CC4IE).
+ * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
+}
+
+/**
+ * @brief Disable capture/compare 4 interrupt (CC4IE).
+ * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
+ * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE));
+}
+
+/**
+ * @brief Enable commutation interrupt (COMIE).
+ * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
+}
+
+/**
+ * @brief Disable commutation interrupt (COMIE).
+ * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
+}
+
+/**
+ * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
+ * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE));
+}
+
+/**
+ * @brief Enable trigger interrupt (TIE).
+ * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_TIE);
+}
+
+/**
+ * @brief Disable trigger interrupt (TIE).
+ * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
+}
+
+/**
+ * @brief Indicates whether the trigger interrupt (TIE) is enabled.
+ * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE));
+}
+
+/**
+ * @brief Enable break interrupt (BIE).
+ * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_BIE);
+}
+
+/**
+ * @brief Disable break interrupt (BIE).
+ * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
+}
+
+/**
+ * @brief Indicates whether the break interrupt (BIE) is enabled.
+ * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_DMA_Management DMA-Management
+ * @{
+ */
+/**
+ * @brief Enable update DMA request (UDE).
+ * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_UDE);
+}
+
+/**
+ * @brief Disable update DMA request (UDE).
+ * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
+}
+
+/**
+ * @brief Indicates whether the update DMA request (UDE) is enabled.
+ * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE));
+}
+
+/**
+ * @brief Enable capture/compare 1 DMA request (CC1DE).
+ * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
+}
+
+/**
+ * @brief Disable capture/compare 1 DMA request (CC1DE).
+ * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
+ * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE));
+}
+
+/**
+ * @brief Enable capture/compare 2 DMA request (CC2DE).
+ * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
+}
+
+/**
+ * @brief Disable capture/compare 2 DMA request (CC2DE).
+ * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
+ * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE));
+}
+
+/**
+ * @brief Enable capture/compare 3 DMA request (CC3DE).
+ * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
+}
+
+/**
+ * @brief Disable capture/compare 3 DMA request (CC3DE).
+ * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
+ * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE));
+}
+
+/**
+ * @brief Enable capture/compare 4 DMA request (CC4DE).
+ * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
+}
+
+/**
+ * @brief Disable capture/compare 4 DMA request (CC4DE).
+ * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
+ * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE));
+}
+
+/**
+ * @brief Enable commutation DMA request (COMDE).
+ * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
+}
+
+/**
+ * @brief Disable commutation DMA request (COMDE).
+ * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
+}
+
+/**
+ * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
+ * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE));
+}
+
+/**
+ * @brief Enable trigger interrupt (TDE).
+ * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_TDE);
+}
+
+/**
+ * @brief Disable trigger interrupt (TDE).
+ * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
+}
+
+/**
+ * @brief Indicates whether the trigger interrupt (TDE) is enabled.
+ * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
+ * @{
+ */
+/**
+ * @brief Generate an update event.
+ * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_UG);
+}
+
+/**
+ * @brief Generate Capture/Compare 1 event.
+ * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
+}
+
+/**
+ * @brief Generate Capture/Compare 2 event.
+ * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
+}
+
+/**
+ * @brief Generate Capture/Compare 3 event.
+ * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
+}
+
+/**
+ * @brief Generate Capture/Compare 4 event.
+ * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
+}
+
+/**
+ * @brief Generate commutation event.
+ * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_COMG);
+}
+
+/**
+ * @brief Generate trigger event.
+ * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_TG);
+}
+
+/**
+ * @brief Generate break event.
+ * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_BG);
+}
+
+#if defined(TIM_EGR_B2G)
+/**
+ * @brief Generate break 2 event.
+ * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_B2G);
+}
+
+#endif /* TIM_EGR_B2G */
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
+ * @{
+ */
+
+ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
+void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
+ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct);
+void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
+ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
+void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
+void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
+ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
+void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
+ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
+void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
+ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 || TIM18 || TIM19 || TIM20 */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_LL_TIM_H */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_ll_usart.h b/Inc/stm32f3xx_ll_usart.h
new file mode 100644
index 0000000..4886a23
--- /dev/null
+++ b/Inc/stm32f3xx_ll_usart.h
@@ -0,0 +1,3645 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_usart.h
+ * @author MCD Application Team
+ * @brief Header file of USART LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_LL_USART_H
+#define __STM32F3xx_LL_USART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx.h"
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5)
+
+/** @defgroup USART_LL USART
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup USART_LL_Private_Constants USART Private Constants
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_Private_Macros USART Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_ES_INIT USART Exported Init structures
+ * @{
+ */
+
+/**
+ * @brief LL USART Init Structure definition
+ */
+typedef struct
+{
+ uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate.
+
+ This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/
+
+ uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter can be a value of @ref USART_LL_EC_DATAWIDTH.
+
+ This feature can be modified afterwards using unitary function @ref LL_USART_SetDataWidth().*/
+
+ uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
+ This parameter can be a value of @ref USART_LL_EC_STOPBITS.
+
+ This feature can be modified afterwards using unitary function @ref LL_USART_SetStopBitsLength().*/
+
+ uint32_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref USART_LL_EC_PARITY.
+
+ This feature can be modified afterwards using unitary function @ref LL_USART_SetParity().*/
+
+ uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref USART_LL_EC_DIRECTION.
+
+ This feature can be modified afterwards using unitary function @ref LL_USART_SetTransferDirection().*/
+
+ uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled.
+ This parameter can be a value of @ref USART_LL_EC_HWCONTROL.
+
+ This feature can be modified afterwards using unitary function @ref LL_USART_SetHWFlowCtrl().*/
+
+ uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8.
+ This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING.
+
+ This feature can be modified afterwards using unitary function @ref LL_USART_SetOverSampling().*/
+
+} LL_USART_InitTypeDef;
+
+/**
+ * @brief LL USART Clock Init Structure definition
+ */
+typedef struct
+{
+ uint32_t ClockOutput; /*!< Specifies whether the USART clock is enabled or disabled.
+ This parameter can be a value of @ref USART_LL_EC_CLOCK.
+
+ USART HW configuration can be modified afterwards using unitary functions
+ @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput().
+ For more details, refer to description of this function. */
+
+ uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock.
+ This parameter can be a value of @ref USART_LL_EC_POLARITY.
+
+ USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPolarity().
+ For more details, refer to description of this function. */
+
+ uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture is made.
+ This parameter can be a value of @ref USART_LL_EC_PHASE.
+
+ USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPhase().
+ For more details, refer to description of this function. */
+
+ uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the last transmitted
+ data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+ This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE.
+
+ USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetLastClkPulseOutput().
+ For more details, refer to description of this function. */
+
+} LL_USART_ClockInitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup USART_LL_Exported_Constants USART Exported Constants
+ * @{
+ */
+
+/** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines
+ * @brief Flags defines which can be used with LL_USART_WriteReg function
+ * @{
+ */
+#define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error flag */
+#define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error flag */
+#define LL_USART_ICR_NCF USART_ICR_NCF /*!< Noise detected flag */
+#define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error flag */
+#define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected flag */
+#define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete flag */
+#define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detection flag */
+#define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS flag */
+#define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout flag */
+#define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block flag */
+#define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match flag */
+#define LL_USART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode flag */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_USART_ReadReg function
+ * @{
+ */
+#define LL_USART_ISR_PE USART_ISR_PE /*!< Parity error flag */
+#define LL_USART_ISR_FE USART_ISR_FE /*!< Framing error flag */
+#define LL_USART_ISR_NE USART_ISR_NE /*!< Noise detected flag */
+#define LL_USART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */
+#define LL_USART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */
+#define LL_USART_ISR_RXNE USART_ISR_RXNE /*!< Read data register not empty flag */
+#define LL_USART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */
+#define LL_USART_ISR_TXE USART_ISR_TXE /*!< Transmit data register empty flag */
+#define LL_USART_ISR_LBDF USART_ISR_LBDF /*!< LIN break detection flag */
+#define LL_USART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */
+#define LL_USART_ISR_CTS USART_ISR_CTS /*!< CTS flag */
+#define LL_USART_ISR_RTOF USART_ISR_RTOF /*!< Receiver timeout flag */
+#define LL_USART_ISR_EOBF USART_ISR_EOBF /*!< End of block flag */
+#define LL_USART_ISR_ABRE USART_ISR_ABRE /*!< Auto baud rate error flag */
+#define LL_USART_ISR_ABRF USART_ISR_ABRF /*!< Auto baud rate flag */
+#define LL_USART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */
+#define LL_USART_ISR_CMF USART_ISR_CMF /*!< Character match flag */
+#define LL_USART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */
+#define LL_USART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */
+#define LL_USART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */
+#define LL_USART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */
+#define LL_USART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions
+ * @{
+ */
+#define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */
+#define LL_USART_CR1_RXNEIE USART_CR1_RXNEIE /*!< Read data register not empty interrupt enable */
+#define LL_USART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */
+#define LL_USART_CR1_TXEIE USART_CR1_TXEIE /*!< Transmit data register empty interrupt enable */
+#define LL_USART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */
+#define LL_USART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */
+#define LL_USART_CR1_RTOIE USART_CR1_RTOIE /*!< Receiver timeout interrupt enable */
+#define LL_USART_CR1_EOBIE USART_CR1_EOBIE /*!< End of Block interrupt enable */
+#define LL_USART_CR2_LBDIE USART_CR2_LBDIE /*!< LIN break detection interrupt enable */
+#define LL_USART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */
+#define LL_USART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */
+#define LL_USART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_DIRECTION Communication Direction
+ * @{
+ */
+#define LL_USART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */
+#define LL_USART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */
+#define LL_USART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */
+#define LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_PARITY Parity Control
+ * @{
+ */
+#define LL_USART_PARITY_NONE 0x00000000U /*!< Parity control disabled */
+#define LL_USART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */
+#define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_WAKEUP Wakeup
+ * @{
+ */
+#define LL_USART_WAKEUP_IDLELINE 0x00000000U /*!< USART wake up from Mute mode on Idle Line */
+#define LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< USART wake up from Mute mode on Address Mark */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_DATAWIDTH Datawidth
+ * @{
+ */
+#if defined(USART_7BITS_SUPPORT)
+#define LL_USART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
+#define LL_USART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
+#define LL_USART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
+#else
+#define LL_USART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
+#define LL_USART_DATAWIDTH_9B USART_CR1_M /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling
+ * @{
+ */
+#define LL_USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */
+#define LL_USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_EC_CLOCK Clock Signal
+ * @{
+ */
+
+#define LL_USART_CLOCK_DISABLE 0x00000000U /*!< Clock signal not provided */
+#define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse
+ * @{
+ */
+#define LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U /*!< The clock pulse of the last data bit is not output to the SCLK pin */
+#define LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL /*!< The clock pulse of the last data bit is output to the SCLK pin */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_PHASE Clock Phase
+ * @{
+ */
+#define LL_USART_PHASE_1EDGE 0x00000000U /*!< The first clock transition is the first data capture edge */
+#define LL_USART_PHASE_2EDGE USART_CR2_CPHA /*!< The second clock transition is the first data capture edge */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_POLARITY Clock Polarity
+ * @{
+ */
+#define LL_USART_POLARITY_LOW 0x00000000U /*!< Steady low value on SCLK pin outside transmission window*/
+#define LL_USART_POLARITY_HIGH USART_CR2_CPOL /*!< Steady high value on SCLK pin outside transmission window */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_STOPBITS Stop Bits
+ * @{
+ */
+#define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< 0.5 stop bit */
+#define LL_USART_STOPBITS_1 0x00000000U /*!< 1 stop bit */
+#define LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< 1.5 stop bits */
+#define LL_USART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_TXRX TX RX Pins Swap
+ * @{
+ */
+#define LL_USART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */
+#define LL_USART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
+ * @{
+ */
+#define LL_USART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */
+#define LL_USART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
+ * @{
+ */
+#define LL_USART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */
+#define LL_USART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion
+ * @{
+ */
+#define LL_USART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */
+#define LL_USART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_BITORDER Bit Order
+ * @{
+ */
+#define LL_USART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first, following the start bit */
+#define LL_USART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, following the start bit */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection
+ * @{
+ */
+#define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 0x00000000U /*!< Measurement of the start bit is used to detect the baud rate */
+#define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0 /*!< Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx */
+#define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME USART_CR2_ABRMODE_1 /*!< 0x7F frame detection */
+#define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x55 frame detection */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection
+ * @{
+ */
+#define LL_USART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */
+#define LL_USART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_HWCONTROL Hardware Control
+ * @{
+ */
+#define LL_USART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */
+#define LL_USART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
+#define LL_USART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
+#define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation
+ * @{
+ */
+#define LL_USART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake up active on address match */
+#define LL_USART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */
+#define LL_USART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power
+ * @{
+ */
+#define LL_USART_IRDA_POWER_NORMAL 0x00000000U /*!< IrDA normal power mode */
+#define LL_USART_IRDA_POWER_LOW USART_CR3_IRLP /*!< IrDA low power mode */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length
+ * @{
+ */
+#define LL_USART_LINBREAK_DETECT_10B 0x00000000U /*!< 10-bit break detection method selected */
+#define LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL /*!< 11-bit break detection method selected */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity
+ * @{
+ */
+#define LL_USART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */
+#define LL_USART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data
+ * @{
+ */
+#define LL_USART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */
+#define LL_USART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup USART_LL_Exported_Macros USART Exported Macros
+ * @{
+ */
+
+/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in USART register
+ * @param __INSTANCE__ USART Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in USART register
+ * @param __INSTANCE__ USART Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
+ * @{
+ */
+
+/**
+ * @brief Compute USARTDIV value according to Peripheral Clock and
+ * expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
+ * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance
+ * @param __BAUDRATE__ Baud rate value to achieve
+ * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
+ */
+#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2) + ((__BAUDRATE__)/2))/(__BAUDRATE__))
+
+/**
+ * @brief Compute USARTDIV value according to Peripheral Clock and
+ * expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)
+ * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance
+ * @param __BAUDRATE__ Baud rate value to achieve
+ * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
+ */
+#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__) + ((__BAUDRATE__)/2))/(__BAUDRATE__))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup USART_LL_Exported_Functions USART Exported Functions
+ * @{
+ */
+
+/** @defgroup USART_LL_EF_Configuration Configuration functions
+ * @{
+ */
+
+/**
+ * @brief USART Enable
+ * @rmtoll CR1 UE LL_USART_Enable
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_UE);
+}
+
+/**
+ * @brief USART Disable (all USART prescalers and outputs are disabled)
+ * @note When USART is disabled, USART prescalers and outputs are stopped immediately,
+ * and current operations are discarded. The configuration of the USART is kept, but all the status
+ * flags, in the USARTx_ISR are set to their default values.
+ * @rmtoll CR1 UE LL_USART_Disable
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR1, USART_CR1_UE);
+}
+
+/**
+ * @brief Indicate if USART is enabled
+ * @rmtoll CR1 UE LL_USART_IsEnabled
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE));
+}
+
+/**
+ * @brief USART enabled in STOP Mode.
+ * @note When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that
+ * USART clock selection is HSI or LSE in RCC.
+ * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * Wake-up from Stop mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 UESM LL_USART_EnableInStopMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_UESM);
+}
+
+/**
+ * @brief USART disabled in STOP Mode.
+ * @note When this function is disabled, USART is not able to wake up the MCU from Stop mode
+ * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * Wake-up from Stop mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 UESM LL_USART_DisableInStopMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR1, USART_CR1_UESM);
+}
+
+/**
+ * @brief Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
+ * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * Wake-up from Stop mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 UESM LL_USART_IsEnabledInStopMode
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM));
+}
+
+/**
+ * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit)
+ * @rmtoll CR1 RE LL_USART_EnableDirectionRx
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_RE);
+}
+
+/**
+ * @brief Receiver Disable
+ * @rmtoll CR1 RE LL_USART_DisableDirectionRx
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR1, USART_CR1_RE);
+}
+
+/**
+ * @brief Transmitter Enable
+ * @rmtoll CR1 TE LL_USART_EnableDirectionTx
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_TE);
+}
+
+/**
+ * @brief Transmitter Disable
+ * @rmtoll CR1 TE LL_USART_DisableDirectionTx
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR1, USART_CR1_TE);
+}
+
+/**
+ * @brief Configure simultaneously enabled/disabled states
+ * of Transmitter and Receiver
+ * @rmtoll CR1 RE LL_USART_SetTransferDirection\n
+ * CR1 TE LL_USART_SetTransferDirection
+ * @param USARTx USART Instance
+ * @param TransferDirection This parameter can be one of the following values:
+ * @arg @ref LL_USART_DIRECTION_NONE
+ * @arg @ref LL_USART_DIRECTION_RX
+ * @arg @ref LL_USART_DIRECTION_TX
+ * @arg @ref LL_USART_DIRECTION_TX_RX
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection)
+{
+ MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
+}
+
+/**
+ * @brief Return enabled/disabled states of Transmitter and Receiver
+ * @rmtoll CR1 RE LL_USART_GetTransferDirection\n
+ * CR1 TE LL_USART_GetTransferDirection
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_DIRECTION_NONE
+ * @arg @ref LL_USART_DIRECTION_RX
+ * @arg @ref LL_USART_DIRECTION_TX
+ * @arg @ref LL_USART_DIRECTION_TX_RX
+ */
+__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE));
+}
+
+/**
+ * @brief Configure Parity (enabled/disabled and parity mode if enabled).
+ * @note This function selects if hardware parity control (generation and detection) is enabled or disabled.
+ * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
+ * (9th or 8th bit depending on data width) and parity is checked on the received data.
+ * @rmtoll CR1 PS LL_USART_SetParity\n
+ * CR1 PCE LL_USART_SetParity
+ * @param USARTx USART Instance
+ * @param Parity This parameter can be one of the following values:
+ * @arg @ref LL_USART_PARITY_NONE
+ * @arg @ref LL_USART_PARITY_EVEN
+ * @arg @ref LL_USART_PARITY_ODD
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity)
+{
+ MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
+}
+
+/**
+ * @brief Return Parity configuration (enabled/disabled and parity mode if enabled)
+ * @rmtoll CR1 PS LL_USART_GetParity\n
+ * CR1 PCE LL_USART_GetParity
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_PARITY_NONE
+ * @arg @ref LL_USART_PARITY_EVEN
+ * @arg @ref LL_USART_PARITY_ODD
+ */
+__STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
+}
+
+/**
+ * @brief Set Receiver Wake Up method from Mute mode.
+ * @rmtoll CR1 WAKE LL_USART_SetWakeUpMethod
+ * @param USARTx USART Instance
+ * @param Method This parameter can be one of the following values:
+ * @arg @ref LL_USART_WAKEUP_IDLELINE
+ * @arg @ref LL_USART_WAKEUP_ADDRESSMARK
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method)
+{
+ MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method);
+}
+
+/**
+ * @brief Return Receiver Wake Up method from Mute mode
+ * @rmtoll CR1 WAKE LL_USART_GetWakeUpMethod
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_WAKEUP_IDLELINE
+ * @arg @ref LL_USART_WAKEUP_ADDRESSMARK
+ */
+__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));
+}
+
+/**
+ * @brief Set Word length (i.e. nb of data bits, excluding start and stop bits)
+ * @rmtoll CR1 M0 LL_USART_SetDataWidth\n
+ * CR1 M1 LL_USART_SetDataWidth
+ * @param USARTx USART Instance
+ * @param DataWidth This parameter can be one of the following values:
+ * @arg @ref LL_USART_DATAWIDTH_7B (*)
+ * @arg @ref LL_USART_DATAWIDTH_8B
+ * @arg @ref LL_USART_DATAWIDTH_9B
+ *
+ * (*) Values not available on all devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth)
+{
+ MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth);
+}
+
+/**
+ * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits)
+ * @rmtoll CR1 M0 LL_USART_GetDataWidth\n
+ * CR1 M1 LL_USART_GetDataWidth
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_DATAWIDTH_7B (*)
+ * @arg @ref LL_USART_DATAWIDTH_8B
+ * @arg @ref LL_USART_DATAWIDTH_9B
+ *
+ * (*) Values not available on all devices
+ */
+__STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));
+}
+
+/**
+ * @brief Allow switch between Mute Mode and Active mode
+ * @rmtoll CR1 MME LL_USART_EnableMuteMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_MME);
+}
+
+/**
+ * @brief Prevent Mute Mode use. Set Receiver in active mode permanently.
+ * @rmtoll CR1 MME LL_USART_DisableMuteMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR1, USART_CR1_MME);
+}
+
+/**
+ * @brief Indicate if switch between Mute Mode and Active mode is allowed
+ * @rmtoll CR1 MME LL_USART_IsEnabledMuteMode
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME));
+}
+
+/**
+ * @brief Set Oversampling to 8-bit or 16-bit mode
+ * @rmtoll CR1 OVER8 LL_USART_SetOverSampling
+ * @param USARTx USART Instance
+ * @param OverSampling This parameter can be one of the following values:
+ * @arg @ref LL_USART_OVERSAMPLING_16
+ * @arg @ref LL_USART_OVERSAMPLING_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling)
+{
+ MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling);
+}
+
+/**
+ * @brief Return Oversampling mode
+ * @rmtoll CR1 OVER8 LL_USART_GetOverSampling
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_OVERSAMPLING_16
+ * @arg @ref LL_USART_OVERSAMPLING_8
+ */
+__STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));
+}
+
+/**
+ * @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not
+ * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput
+ * @param USARTx USART Instance
+ * @param LastBitClockPulse This parameter can be one of the following values:
+ * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+ * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse);
+}
+
+/**
+ * @brief Retrieve Clock pulse of the last data bit output configuration
+ * (Last bit Clock pulse output to the SCLK pin or not)
+ * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+ * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+ */
+__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));
+}
+
+/**
+ * @brief Select the phase of the clock output on the SCLK pin in synchronous mode
+ * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 CPHA LL_USART_SetClockPhase
+ * @param USARTx USART Instance
+ * @param ClockPhase This parameter can be one of the following values:
+ * @arg @ref LL_USART_PHASE_1EDGE
+ * @arg @ref LL_USART_PHASE_2EDGE
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase);
+}
+
+/**
+ * @brief Return phase of the clock output on the SCLK pin in synchronous mode
+ * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 CPHA LL_USART_GetClockPhase
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_PHASE_1EDGE
+ * @arg @ref LL_USART_PHASE_2EDGE
+ */
+__STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));
+}
+
+/**
+ * @brief Select the polarity of the clock output on the SCLK pin in synchronous mode
+ * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 CPOL LL_USART_SetClockPolarity
+ * @param USARTx USART Instance
+ * @param ClockPolarity This parameter can be one of the following values:
+ * @arg @ref LL_USART_POLARITY_LOW
+ * @arg @ref LL_USART_POLARITY_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity);
+}
+
+/**
+ * @brief Return polarity of the clock output on the SCLK pin in synchronous mode
+ * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 CPOL LL_USART_GetClockPolarity
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_POLARITY_LOW
+ * @arg @ref LL_USART_POLARITY_HIGH
+ */
+__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));
+}
+
+/**
+ * @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
+ * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Clock Phase configuration using @ref LL_USART_SetClockPhase() function
+ * - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function
+ * - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function
+ * @rmtoll CR2 CPHA LL_USART_ConfigClock\n
+ * CR2 CPOL LL_USART_ConfigClock\n
+ * CR2 LBCL LL_USART_ConfigClock
+ * @param USARTx USART Instance
+ * @param Phase This parameter can be one of the following values:
+ * @arg @ref LL_USART_PHASE_1EDGE
+ * @arg @ref LL_USART_PHASE_2EDGE
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_USART_POLARITY_LOW
+ * @arg @ref LL_USART_POLARITY_HIGH
+ * @param LBCPOutput This parameter can be one of the following values:
+ * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+ * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput);
+}
+
+/**
+ * @brief Enable Clock output on SCLK pin
+ * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+ * @brief Disable Clock output on SCLK pin
+ * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+ * @brief Indicate if Clock output on SCLK pin is enabled
+ * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN));
+}
+
+/**
+ * @brief Set the length of the stop bits
+ * @rmtoll CR2 STOP LL_USART_SetStopBitsLength
+ * @param USARTx USART Instance
+ * @param StopBits This parameter can be one of the following values:
+ * @arg @ref LL_USART_STOPBITS_0_5
+ * @arg @ref LL_USART_STOPBITS_1
+ * @arg @ref LL_USART_STOPBITS_1_5
+ * @arg @ref LL_USART_STOPBITS_2
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+ * @brief Retrieve the length of the stop bits
+ * @rmtoll CR2 STOP LL_USART_GetStopBitsLength
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_STOPBITS_0_5
+ * @arg @ref LL_USART_STOPBITS_1
+ * @arg @ref LL_USART_STOPBITS_1_5
+ * @arg @ref LL_USART_STOPBITS_2
+ */
+__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));
+}
+
+/**
+ * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits)
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Data Width configuration using @ref LL_USART_SetDataWidth() function
+ * - Parity Control and mode configuration using @ref LL_USART_SetParity() function
+ * - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function
+ * @rmtoll CR1 PS LL_USART_ConfigCharacter\n
+ * CR1 PCE LL_USART_ConfigCharacter\n
+ * CR1 M0 LL_USART_ConfigCharacter\n
+ * CR1 M1 LL_USART_ConfigCharacter\n
+ * CR2 STOP LL_USART_ConfigCharacter
+ * @param USARTx USART Instance
+ * @param DataWidth This parameter can be one of the following values:
+ * @arg @ref LL_USART_DATAWIDTH_7B (*)
+ * @arg @ref LL_USART_DATAWIDTH_8B
+ * @arg @ref LL_USART_DATAWIDTH_9B
+ * @param Parity This parameter can be one of the following values:
+ * @arg @ref LL_USART_PARITY_NONE
+ * @arg @ref LL_USART_PARITY_EVEN
+ * @arg @ref LL_USART_PARITY_ODD
+ * @param StopBits This parameter can be one of the following values:
+ * @arg @ref LL_USART_STOPBITS_0_5
+ * @arg @ref LL_USART_STOPBITS_1
+ * @arg @ref LL_USART_STOPBITS_1_5
+ * @arg @ref LL_USART_STOPBITS_2
+ *
+ * (*) Values not available on all devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity,
+ uint32_t StopBits)
+{
+ MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
+ MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+ * @brief Configure TX/RX pins swapping setting.
+ * @rmtoll CR2 SWAP LL_USART_SetTXRXSwap
+ * @param USARTx USART Instance
+ * @param SwapConfig This parameter can be one of the following values:
+ * @arg @ref LL_USART_TXRX_STANDARD
+ * @arg @ref LL_USART_TXRX_SWAPPED
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig);
+}
+
+/**
+ * @brief Retrieve TX/RX pins swapping configuration.
+ * @rmtoll CR2 SWAP LL_USART_GetTXRXSwap
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_TXRX_STANDARD
+ * @arg @ref LL_USART_TXRX_SWAPPED
+ */
+__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP));
+}
+
+/**
+ * @brief Configure RX pin active level logic
+ * @rmtoll CR2 RXINV LL_USART_SetRXPinLevel
+ * @param USARTx USART Instance
+ * @param PinInvMethod This parameter can be one of the following values:
+ * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
+ * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod);
+}
+
+/**
+ * @brief Retrieve RX pin active level logic configuration
+ * @rmtoll CR2 RXINV LL_USART_GetRXPinLevel
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
+ * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
+ */
+__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV));
+}
+
+/**
+ * @brief Configure TX pin active level logic
+ * @rmtoll CR2 TXINV LL_USART_SetTXPinLevel
+ * @param USARTx USART Instance
+ * @param PinInvMethod This parameter can be one of the following values:
+ * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
+ * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod);
+}
+
+/**
+ * @brief Retrieve TX pin active level logic configuration
+ * @rmtoll CR2 TXINV LL_USART_GetTXPinLevel
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
+ * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
+ */
+__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV));
+}
+
+/**
+ * @brief Configure Binary data logic.
+ * @note Allow to define how Logical data from the data register are send/received :
+ * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
+ * @rmtoll CR2 DATAINV LL_USART_SetBinaryDataLogic
+ * @param USARTx USART Instance
+ * @param DataLogic This parameter can be one of the following values:
+ * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
+ * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic);
+}
+
+/**
+ * @brief Retrieve Binary data configuration
+ * @rmtoll CR2 DATAINV LL_USART_GetBinaryDataLogic
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
+ * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
+ */
+__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV));
+}
+
+/**
+ * @brief Configure transfer bit order (either Less or Most Significant Bit First)
+ * @note MSB First means data is transmitted/received with the MSB first, following the start bit.
+ * LSB First means data is transmitted/received with data bit 0 first, following the start bit.
+ * @rmtoll CR2 MSBFIRST LL_USART_SetTransferBitOrder
+ * @param USARTx USART Instance
+ * @param BitOrder This parameter can be one of the following values:
+ * @arg @ref LL_USART_BITORDER_LSBFIRST
+ * @arg @ref LL_USART_BITORDER_MSBFIRST
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
+}
+
+/**
+ * @brief Return transfer bit order (either Less or Most Significant Bit First)
+ * @note MSB First means data is transmitted/received with the MSB first, following the start bit.
+ * LSB First means data is transmitted/received with data bit 0 first, following the start bit.
+ * @rmtoll CR2 MSBFIRST LL_USART_GetTransferBitOrder
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_BITORDER_LSBFIRST
+ * @arg @ref LL_USART_BITORDER_MSBFIRST
+ */
+__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST));
+}
+
+/**
+ * @brief Enable Auto Baud-Rate Detection
+ * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * Auto Baud Rate detection feature is supported by the USARTx instance.
+ * @rmtoll CR2 ABREN LL_USART_EnableAutoBaudRate
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR2, USART_CR2_ABREN);
+}
+
+/**
+ * @brief Disable Auto Baud-Rate Detection
+ * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * Auto Baud Rate detection feature is supported by the USARTx instance.
+ * @rmtoll CR2 ABREN LL_USART_DisableAutoBaudRate
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN);
+}
+
+/**
+ * @brief Indicate if Auto Baud-Rate Detection mechanism is enabled
+ * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * Auto Baud Rate detection feature is supported by the USARTx instance.
+ * @rmtoll CR2 ABREN LL_USART_IsEnabledAutoBaud
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN));
+}
+
+/**
+ * @brief Set Auto Baud-Rate mode bits
+ * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * Auto Baud Rate detection feature is supported by the USARTx instance.
+ * @rmtoll CR2 ABRMODE LL_USART_SetAutoBaudRateMode
+ * @param USARTx USART Instance
+ * @param AutoBaudRateMode This parameter can be one of the following values:
+ * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
+ * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
+ * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
+ * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode);
+}
+
+/**
+ * @brief Return Auto Baud-Rate mode
+ * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * Auto Baud Rate detection feature is supported by the USARTx instance.
+ * @rmtoll CR2 ABRMODE LL_USART_GetAutoBaudRateMode
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
+ * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
+ * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
+ * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
+ */
+__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE));
+}
+
+/**
+ * @brief Enable Receiver Timeout
+ * @rmtoll CR2 RTOEN LL_USART_EnableRxTimeout
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR2, USART_CR2_RTOEN);
+}
+
+/**
+ * @brief Disable Receiver Timeout
+ * @rmtoll CR2 RTOEN LL_USART_DisableRxTimeout
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN);
+}
+
+/**
+ * @brief Indicate if Receiver Timeout feature is enabled
+ * @rmtoll CR2 RTOEN LL_USART_IsEnabledRxTimeout
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN));
+}
+
+/**
+ * @brief Set Address of the USART node.
+ * @note This is used in multiprocessor communication during Mute mode or Stop mode,
+ * for wake up with address mark detection.
+ * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7.
+ * (b7-b4 should be set to 0)
+ * 8bits address node is used when 7-bit Address Detection is selected in ADDM7.
+ * (This is used in multiprocessor communication during Mute mode or Stop mode,
+ * for wake up with 7-bit address mark detection.
+ * The MSB of the character sent by the transmitter should be equal to 1.
+ * It may also be used for character detection during normal reception,
+ * Mute mode inactive (for example, end of block detection in ModBus protocol).
+ * In this case, the whole received character (8-bit) is compared to the ADD[7:0]
+ * value and CMF flag is set on match)
+ * @rmtoll CR2 ADD LL_USART_ConfigNodeAddress\n
+ * CR2 ADDM7 LL_USART_ConfigNodeAddress
+ * @param USARTx USART Instance
+ * @param AddressLen This parameter can be one of the following values:
+ * @arg @ref LL_USART_ADDRESS_DETECT_4B
+ * @arg @ref LL_USART_ADDRESS_DETECT_7B
+ * @param NodeAddress 4 or 7 bit Address of the USART node.
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
+ (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
+}
+
+/**
+ * @brief Return 8 bit Address of the USART node as set in ADD field of CR2.
+ * @note If 4-bit Address Detection is selected in ADDM7,
+ * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
+ * If 7-bit Address Detection is selected in ADDM7,
+ * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
+ * @rmtoll CR2 ADD LL_USART_GetNodeAddress
+ * @param USARTx USART Instance
+ * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255)
+ */
+__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
+}
+
+/**
+ * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
+ * @rmtoll CR2 ADDM7 LL_USART_GetNodeAddressLen
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_ADDRESS_DETECT_4B
+ * @arg @ref LL_USART_ADDRESS_DETECT_7B
+ */
+__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7));
+}
+
+/**
+ * @brief Enable RTS HW Flow Control
+ * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+ * @brief Disable RTS HW Flow Control
+ * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+ * @brief Enable CTS HW Flow Control
+ * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+ * @brief Disable CTS HW Flow Control
+ * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+ * @brief Configure HW Flow Control mode (both CTS and RTS)
+ * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n
+ * CR3 CTSE LL_USART_SetHWFlowCtrl
+ * @param USARTx USART Instance
+ * @param HardwareFlowControl This parameter can be one of the following values:
+ * @arg @ref LL_USART_HWCONTROL_NONE
+ * @arg @ref LL_USART_HWCONTROL_RTS
+ * @arg @ref LL_USART_HWCONTROL_CTS
+ * @arg @ref LL_USART_HWCONTROL_RTS_CTS
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
+{
+ MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
+}
+
+/**
+ * @brief Return HW Flow Control configuration (both CTS and RTS)
+ * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n
+ * CR3 CTSE LL_USART_GetHWFlowCtrl
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_HWCONTROL_NONE
+ * @arg @ref LL_USART_HWCONTROL_RTS
+ * @arg @ref LL_USART_HWCONTROL_CTS
+ * @arg @ref LL_USART_HWCONTROL_RTS_CTS
+ */
+__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
+}
+
+/**
+ * @brief Enable One bit sampling method
+ * @rmtoll CR3 ONEBIT LL_USART_EnableOneBitSamp
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_ONEBIT);
+}
+
+/**
+ * @brief Disable One bit sampling method
+ * @rmtoll CR3 ONEBIT LL_USART_DisableOneBitSamp
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT);
+}
+
+/**
+ * @brief Indicate if One bit sampling method is enabled
+ * @rmtoll CR3 ONEBIT LL_USART_IsEnabledOneBitSamp
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT));
+}
+
+/**
+ * @brief Enable Overrun detection
+ * @rmtoll CR3 OVRDIS LL_USART_EnableOverrunDetect
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS);
+}
+
+/**
+ * @brief Disable Overrun detection
+ * @rmtoll CR3 OVRDIS LL_USART_DisableOverrunDetect
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_OVRDIS);
+}
+
+/**
+ * @brief Indicate if Overrun detection is enabled
+ * @rmtoll CR3 OVRDIS LL_USART_IsEnabledOverrunDetect
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS);
+}
+
+/**
+ * @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+ * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * Wake-up from Stop mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 WUS LL_USART_SetWKUPType
+ * @param USARTx USART Instance
+ * @param Type This parameter can be one of the following values:
+ * @arg @ref LL_USART_WAKEUP_ON_ADDRESS
+ * @arg @ref LL_USART_WAKEUP_ON_STARTBIT
+ * @arg @ref LL_USART_WAKEUP_ON_RXNE
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type)
+{
+ MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type);
+}
+
+/**
+ * @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+ * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * Wake-up from Stop mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 WUS LL_USART_GetWKUPType
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_WAKEUP_ON_ADDRESS
+ * @arg @ref LL_USART_WAKEUP_ON_STARTBIT
+ * @arg @ref LL_USART_WAKEUP_ON_RXNE
+ */
+__STATIC_INLINE uint32_t LL_USART_GetWKUPType(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS));
+}
+
+/**
+ * @brief Configure USART BRR register for achieving expected Baud Rate value.
+ * @note Compute and set USARTDIV value in BRR Register (full BRR content)
+ * according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
+ * @note Peripheral clock and Baud rate values provided as function parameters should be valid
+ * (Baud rate value != 0)
+ * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
+ * @rmtoll BRR BRR LL_USART_SetBaudRate
+ * @param USARTx USART Instance
+ * @param PeriphClk Peripheral Clock
+ * @param OverSampling This parameter can be one of the following values:
+ * @arg @ref LL_USART_OVERSAMPLING_16
+ * @arg @ref LL_USART_OVERSAMPLING_8
+ * @param BaudRate Baud Rate
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling,
+ uint32_t BaudRate)
+{
+ register uint32_t usartdiv = 0x0U;
+ register uint32_t brrtemp = 0x0U;
+
+ if (OverSampling == LL_USART_OVERSAMPLING_8)
+ {
+ usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate));
+ brrtemp = usartdiv & 0xFFF0U;
+ brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+ USARTx->BRR = brrtemp;
+ }
+ else
+ {
+ USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate));
+ }
+}
+
+/**
+ * @brief Return current Baud Rate value, according to USARTDIV present in BRR register
+ * (full BRR content), and to used Peripheral Clock and Oversampling mode values
+ * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
+ * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
+ * @rmtoll BRR BRR LL_USART_GetBaudRate
+ * @param USARTx USART Instance
+ * @param PeriphClk Peripheral Clock
+ * @param OverSampling This parameter can be one of the following values:
+ * @arg @ref LL_USART_OVERSAMPLING_16
+ * @arg @ref LL_USART_OVERSAMPLING_8
+ * @retval Baud Rate
+ */
+__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling)
+{
+ register uint32_t usartdiv = 0x0U;
+ register uint32_t brrresult = 0x0U;
+
+ usartdiv = USARTx->BRR;
+
+ if (OverSampling == LL_USART_OVERSAMPLING_8)
+ {
+ if ((usartdiv & 0xFFF7U) != 0U)
+ {
+ usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;
+ brrresult = (PeriphClk * 2U) / usartdiv;
+ }
+ }
+ else
+ {
+ if ((usartdiv & 0xFFFFU) != 0U)
+ {
+ brrresult = PeriphClk / usartdiv;
+ }
+ }
+ return (brrresult);
+}
+
+/**
+ * @brief Set Receiver Time Out Value (expressed in nb of bits duration)
+ * @rmtoll RTOR RTO LL_USART_SetRxTimeout
+ * @param USARTx USART Instance
+ * @param Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeout)
+{
+ MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout);
+}
+
+/**
+ * @brief Get Receiver Time Out Value (expressed in nb of bits duration)
+ * @rmtoll RTOR RTO LL_USART_GetRxTimeout
+ * @param USARTx USART Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
+ */
+__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO));
+}
+
+/**
+ * @brief Set Block Length value in reception
+ * @rmtoll RTOR BLEN LL_USART_SetBlockLength
+ * @param USARTx USART Instance
+ * @param BlockLength Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength)
+{
+ MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos);
+}
+
+/**
+ * @brief Get Block Length value in reception
+ * @rmtoll RTOR BLEN LL_USART_GetBlockLength
+ * @param USARTx USART Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_USART_GetBlockLength(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature
+ * @{
+ */
+
+/**
+ * @brief Enable IrDA mode
+ * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @rmtoll CR3 IREN LL_USART_EnableIrda
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+ * @brief Disable IrDA mode
+ * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @rmtoll CR3 IREN LL_USART_DisableIrda
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+ * @brief Indicate if IrDA mode is enabled
+ * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @rmtoll CR3 IREN LL_USART_IsEnabledIrda
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN));
+}
+
+/**
+ * @brief Configure IrDA Power Mode (Normal or Low Power)
+ * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode
+ * @param USARTx USART Instance
+ * @param PowerMode This parameter can be one of the following values:
+ * @arg @ref LL_USART_IRDA_POWER_NORMAL
+ * @arg @ref LL_USART_IRDA_POWER_LOW
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode)
+{
+ MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode);
+}
+
+/**
+ * @brief Retrieve IrDA Power Mode configuration (Normal or Low Power)
+ * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_IRDA_POWER_NORMAL
+ * @arg @ref LL_USART_PHASE_2EDGE
+ */
+__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP));
+}
+
+/**
+ * @brief Set Irda prescaler value, used for dividing the USART clock source
+ * to achieve the Irda Low Power frequency (8 bits value)
+ * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler
+ * @param USARTx USART Instance
+ * @param PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
+{
+ MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue);
+}
+
+/**
+ * @brief Return Irda prescaler value, used for dividing the USART clock source
+ * to achieve the Irda Low Power frequency (8 bits value)
+ * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler
+ * @param USARTx USART Instance
+ * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)
+ */
+__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature
+ * @{
+ */
+
+/**
+ * @brief Enable Smartcard NACK transmission
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_NACK);
+}
+
+/**
+ * @brief Disable Smartcard NACK transmission
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_NACK);
+}
+
+/**
+ * @brief Indicate if Smartcard NACK transmission is enabled
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK));
+}
+
+/**
+ * @brief Enable Smartcard mode
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 SCEN LL_USART_EnableSmartcard
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+ * @brief Disable Smartcard mode
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 SCEN LL_USART_DisableSmartcard
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+ * @brief Indicate if Smartcard mode is enabled
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN));
+}
+
+/**
+ * @brief Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @note This bit-field specifies the number of retries in transmit and receive, in Smartcard mode.
+ * In transmission mode, it specifies the number of automatic retransmission retries, before
+ * generating a transmission error (FE bit set).
+ * In reception mode, it specifies the number or erroneous reception trials, before generating a
+ * reception error (RXNE and PE bits set)
+ * @rmtoll CR3 SCARCNT LL_USART_SetSmartcardAutoRetryCount
+ * @param USARTx USART Instance
+ * @param AutoRetryCount Value between Min_Data=0 and Max_Data=7
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryCount)
+{
+ MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos);
+}
+
+/**
+ * @brief Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 SCARCNT LL_USART_GetSmartcardAutoRetryCount
+ * @param USARTx USART Instance
+ * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7)
+ */
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos);
+}
+
+/**
+ * @brief Set Smartcard prescaler value, used for dividing the USART clock
+ * source to provide the SMARTCARD Clock (5 bits value)
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler
+ * @param USARTx USART Instance
+ * @param PrescalerValue Value between Min_Data=0 and Max_Data=31
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
+{
+ MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue);
+}
+
+/**
+ * @brief Return Smartcard prescaler value, used for dividing the USART clock
+ * source to provide the SMARTCARD Clock (5 bits value)
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler
+ * @param USARTx USART Instance
+ * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)
+ */
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
+}
+
+/**
+ * @brief Set Smartcard Guard time value, expressed in nb of baud clocks periods
+ * (GT[7:0] bits : Guard time value)
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime
+ * @param USARTx USART Instance
+ * @param GuardTime Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)
+{
+ MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, GuardTime << USART_GTPR_GT_Pos);
+}
+
+/**
+ * @brief Return Smartcard Guard time value, expressed in nb of baud clocks periods
+ * (GT[7:0] bits : Guard time value)
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime
+ * @param USARTx USART Instance
+ * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)
+ */
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
+ * @{
+ */
+
+/**
+ * @brief Enable Single Wire Half-Duplex mode
+ * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+ * Half-Duplex mode is supported by the USARTx instance.
+ * @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+ * @brief Disable Single Wire Half-Duplex mode
+ * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+ * Half-Duplex mode is supported by the USARTx instance.
+ * @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+ * @brief Indicate if Single Wire Half-Duplex mode is enabled
+ * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+ * Half-Duplex mode is supported by the USARTx instance.
+ * @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature
+ * @{
+ */
+
+/**
+ * @brief Set LIN Break Detection Length
+ * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen
+ * @param USARTx USART Instance
+ * @param LINBDLength This parameter can be one of the following values:
+ * @arg @ref LL_USART_LINBREAK_DETECT_10B
+ * @arg @ref LL_USART_LINBREAK_DETECT_11B
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength);
+}
+
+/**
+ * @brief Return LIN Break Detection Length
+ * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_LINBREAK_DETECT_10B
+ * @arg @ref LL_USART_LINBREAK_DETECT_11B
+ */
+__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL));
+}
+
+/**
+ * @brief Enable LIN mode
+ * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LINEN LL_USART_EnableLIN
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+ * @brief Disable LIN mode
+ * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LINEN LL_USART_DisableLIN
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+ * @brief Indicate if LIN mode is enabled
+ * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LINEN LL_USART_IsEnabledLIN
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
+ * @{
+ */
+
+/**
+ * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
+ * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * Driver Enable feature is supported by the USARTx instance.
+ * @rmtoll CR1 DEDT LL_USART_SetDEDeassertionTime
+ * @param USARTx USART Instance
+ * @param Time Value between Min_Data=0 and Max_Data=31
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time)
+{
+ MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
+}
+
+/**
+ * @brief Return DEDT (Driver Enable De-Assertion Time)
+ * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * Driver Enable feature is supported by the USARTx instance.
+ * @rmtoll CR1 DEDT LL_USART_GetDEDeassertionTime
+ * @param USARTx USART Instance
+ * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
+ */
+__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
+}
+
+/**
+ * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
+ * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * Driver Enable feature is supported by the USARTx instance.
+ * @rmtoll CR1 DEAT LL_USART_SetDEAssertionTime
+ * @param USARTx USART Instance
+ * @param Time Value between Min_Data=0 and Max_Data=31
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time)
+{
+ MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
+}
+
+/**
+ * @brief Return DEAT (Driver Enable Assertion Time)
+ * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * Driver Enable feature is supported by the USARTx instance.
+ * @rmtoll CR1 DEAT LL_USART_GetDEAssertionTime
+ * @param USARTx USART Instance
+ * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
+ */
+__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
+}
+
+/**
+ * @brief Enable Driver Enable (DE) Mode
+ * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * Driver Enable feature is supported by the USARTx instance.
+ * @rmtoll CR3 DEM LL_USART_EnableDEMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_DEM);
+}
+
+/**
+ * @brief Disable Driver Enable (DE) Mode
+ * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * Driver Enable feature is supported by the USARTx instance.
+ * @rmtoll CR3 DEM LL_USART_DisableDEMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_DEM);
+}
+
+/**
+ * @brief Indicate if Driver Enable (DE) Mode is enabled
+ * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * Driver Enable feature is supported by the USARTx instance.
+ * @rmtoll CR3 DEM LL_USART_IsEnabledDEMode
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM));
+}
+
+/**
+ * @brief Select Driver Enable Polarity
+ * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * Driver Enable feature is supported by the USARTx instance.
+ * @rmtoll CR3 DEP LL_USART_SetDESignalPolarity
+ * @param USARTx USART Instance
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_USART_DE_POLARITY_HIGH
+ * @arg @ref LL_USART_DE_POLARITY_LOW
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_t Polarity)
+{
+ MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity);
+}
+
+/**
+ * @brief Return Driver Enable Polarity
+ * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * Driver Enable feature is supported by the USARTx instance.
+ * @rmtoll CR3 DEP LL_USART_GetDESignalPolarity
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_DE_POLARITY_HIGH
+ * @arg @ref LL_USART_DE_POLARITY_LOW
+ */
+__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services
+ * @{
+ */
+
+/**
+ * @brief Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
+ * @note In UART mode, the following bits must be kept cleared:
+ * - LINEN bit in the USART_CR2 register,
+ * - CLKEN bit in the USART_CR2 register,
+ * - SCEN bit in the USART_CR3 register,
+ * - IREN bit in the USART_CR3 register,
+ * - HDSEL bit in the USART_CR3 register.
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+ * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+ * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+ * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+ * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+ * @note Other remaining configurations items related to Asynchronous Mode
+ * (as Baud Rate, Word length, Parity, ...) should be set using
+ * dedicated functions
+ * @rmtoll CR2 LINEN LL_USART_ConfigAsyncMode\n
+ * CR2 CLKEN LL_USART_ConfigAsyncMode\n
+ * CR3 SCEN LL_USART_ConfigAsyncMode\n
+ * CR3 IREN LL_USART_ConfigAsyncMode\n
+ * CR3 HDSEL LL_USART_ConfigAsyncMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)
+{
+ /* In Asynchronous mode, the following bits must be kept cleared:
+ - LINEN, CLKEN bits in the USART_CR2 register,
+ - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
+ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
+}
+
+/**
+ * @brief Perform basic configuration of USART for enabling use in Synchronous Mode
+ * @note In Synchronous mode, the following bits must be kept cleared:
+ * - LINEN bit in the USART_CR2 register,
+ * - SCEN bit in the USART_CR3 register,
+ * - IREN bit in the USART_CR3 register,
+ * - HDSEL bit in the USART_CR3 register.
+ * This function also sets the USART in Synchronous mode.
+ * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+ * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+ * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+ * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+ * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
+ * @note Other remaining configurations items related to Synchronous Mode
+ * (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using
+ * dedicated functions
+ * @rmtoll CR2 LINEN LL_USART_ConfigSyncMode\n
+ * CR2 CLKEN LL_USART_ConfigSyncMode\n
+ * CR3 SCEN LL_USART_ConfigSyncMode\n
+ * CR3 IREN LL_USART_ConfigSyncMode\n
+ * CR3 HDSEL LL_USART_ConfigSyncMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)
+{
+ /* In Synchronous mode, the following bits must be kept cleared:
+ - LINEN bit in the USART_CR2 register,
+ - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
+ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
+ CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
+ /* set the UART/USART in Synchronous mode */
+ SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+ * @brief Perform basic configuration of USART for enabling use in LIN Mode
+ * @note In LIN mode, the following bits must be kept cleared:
+ * - STOP and CLKEN bits in the USART_CR2 register,
+ * - SCEN bit in the USART_CR3 register,
+ * - IREN bit in the USART_CR3 register,
+ * - HDSEL bit in the USART_CR3 register.
+ * This function also set the UART/USART in LIN mode.
+ * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+ * - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+ * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+ * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+ * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+ * - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function
+ * @note Other remaining configurations items related to LIN Mode
+ * (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using
+ * dedicated functions
+ * @rmtoll CR2 CLKEN LL_USART_ConfigLINMode\n
+ * CR2 STOP LL_USART_ConfigLINMode\n
+ * CR2 LINEN LL_USART_ConfigLINMode\n
+ * CR3 IREN LL_USART_ConfigLINMode\n
+ * CR3 SCEN LL_USART_ConfigLINMode\n
+ * CR3 HDSEL LL_USART_ConfigLINMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)
+{
+ /* In LIN mode, the following bits must be kept cleared:
+ - STOP and CLKEN bits in the USART_CR2 register,
+ - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
+ CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
+ CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
+ /* Set the UART/USART in LIN mode */
+ SET_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+ * @brief Perform basic configuration of USART for enabling use in Half Duplex Mode
+ * @note In Half Duplex mode, the following bits must be kept cleared:
+ * - LINEN bit in the USART_CR2 register,
+ * - CLKEN bit in the USART_CR2 register,
+ * - SCEN bit in the USART_CR3 register,
+ * - IREN bit in the USART_CR3 register,
+ * This function also sets the UART/USART in Half Duplex mode.
+ * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+ * Half-Duplex mode is supported by the USARTx instance.
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+ * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+ * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+ * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+ * - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function
+ * @note Other remaining configurations items related to Half Duplex Mode
+ * (as Baud Rate, Word length, Parity, ...) should be set using
+ * dedicated functions
+ * @rmtoll CR2 LINEN LL_USART_ConfigHalfDuplexMode\n
+ * CR2 CLKEN LL_USART_ConfigHalfDuplexMode\n
+ * CR3 HDSEL LL_USART_ConfigHalfDuplexMode\n
+ * CR3 SCEN LL_USART_ConfigHalfDuplexMode\n
+ * CR3 IREN LL_USART_ConfigHalfDuplexMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)
+{
+ /* In Half Duplex mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - SCEN and IREN bits in the USART_CR3 register.*/
+ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));
+ /* set the UART/USART in Half Duplex mode */
+ SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+ * @brief Perform basic configuration of USART for enabling use in Smartcard Mode
+ * @note In Smartcard mode, the following bits must be kept cleared:
+ * - LINEN bit in the USART_CR2 register,
+ * - IREN bit in the USART_CR3 register,
+ * - HDSEL bit in the USART_CR3 register.
+ * This function also configures Stop bits to 1.5 bits and
+ * sets the USART in Smartcard mode (SCEN bit).
+ * Clock Output is also enabled (CLKEN).
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+ * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+ * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+ * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+ * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
+ * - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function
+ * @note Other remaining configurations items related to Smartcard Mode
+ * (as Baud Rate, Word length, Parity, ...) should be set using
+ * dedicated functions
+ * @rmtoll CR2 LINEN LL_USART_ConfigSmartcardMode\n
+ * CR2 STOP LL_USART_ConfigSmartcardMode\n
+ * CR2 CLKEN LL_USART_ConfigSmartcardMode\n
+ * CR3 HDSEL LL_USART_ConfigSmartcardMode\n
+ * CR3 SCEN LL_USART_ConfigSmartcardMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)
+{
+ /* In Smartcard mode, the following bits must be kept cleared:
+ - LINEN bit in the USART_CR2 register,
+ - IREN and HDSEL bits in the USART_CR3 register.*/
+ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
+ CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
+ /* Configure Stop bits to 1.5 bits */
+ /* Synchronous mode is activated by default */
+ SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN));
+ /* set the UART/USART in Smartcard mode */
+ SET_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+ * @brief Perform basic configuration of USART for enabling use in Irda Mode
+ * @note In IRDA mode, the following bits must be kept cleared:
+ * - LINEN bit in the USART_CR2 register,
+ * - STOP and CLKEN bits in the USART_CR2 register,
+ * - SCEN bit in the USART_CR3 register,
+ * - HDSEL bit in the USART_CR3 register.
+ * This function also sets the UART/USART in IRDA mode (IREN bit).
+ * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+ * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+ * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+ * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+ * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+ * - Set IREN in CR3 using @ref LL_USART_EnableIrda() function
+ * @note Other remaining configurations items related to Irda Mode
+ * (as Baud Rate, Word length, Power mode, ...) should be set using
+ * dedicated functions
+ * @rmtoll CR2 LINEN LL_USART_ConfigIrdaMode\n
+ * CR2 CLKEN LL_USART_ConfigIrdaMode\n
+ * CR2 STOP LL_USART_ConfigIrdaMode\n
+ * CR3 SCEN LL_USART_ConfigIrdaMode\n
+ * CR3 HDSEL LL_USART_ConfigIrdaMode\n
+ * CR3 IREN LL_USART_ConfigIrdaMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx)
+{
+ /* In IRDA mode, the following bits must be kept cleared:
+ - LINEN, STOP and CLKEN bits in the USART_CR2 register,
+ - SCEN and HDSEL bits in the USART_CR3 register.*/
+ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
+ CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
+ /* set the UART/USART in IRDA mode */
+ SET_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+ * @brief Perform basic configuration of USART for enabling use in Multi processor Mode
+ * (several USARTs connected in a network, one of the USARTs can be the master,
+ * its TX output connected to the RX inputs of the other slaves USARTs).
+ * @note In MultiProcessor mode, the following bits must be kept cleared:
+ * - LINEN bit in the USART_CR2 register,
+ * - CLKEN bit in the USART_CR2 register,
+ * - SCEN bit in the USART_CR3 register,
+ * - IREN bit in the USART_CR3 register,
+ * - HDSEL bit in the USART_CR3 register.
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+ * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+ * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+ * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+ * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+ * @note Other remaining configurations items related to Multi processor Mode
+ * (as Baud Rate, Wake Up Method, Node address, ...) should be set using
+ * dedicated functions
+ * @rmtoll CR2 LINEN LL_USART_ConfigMultiProcessMode\n
+ * CR2 CLKEN LL_USART_ConfigMultiProcessMode\n
+ * CR3 SCEN LL_USART_ConfigMultiProcessMode\n
+ * CR3 HDSEL LL_USART_ConfigMultiProcessMode\n
+ * CR3 IREN LL_USART_ConfigMultiProcessMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)
+{
+ /* In Multi Processor mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
+ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+
+/**
+ * @brief Check if the USART Parity Error Flag is set or not
+ * @rmtoll ISR PE LL_USART_IsActiveFlag_PE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE));
+}
+
+/**
+ * @brief Check if the USART Framing Error Flag is set or not
+ * @rmtoll ISR FE LL_USART_IsActiveFlag_FE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE));
+}
+
+/**
+ * @brief Check if the USART Noise error detected Flag is set or not
+ * @rmtoll ISR NF LL_USART_IsActiveFlag_NE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE));
+}
+
+/**
+ * @brief Check if the USART OverRun Error Flag is set or not
+ * @rmtoll ISR ORE LL_USART_IsActiveFlag_ORE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE));
+}
+
+/**
+ * @brief Check if the USART IDLE line detected Flag is set or not
+ * @rmtoll ISR IDLE LL_USART_IsActiveFlag_IDLE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE));
+}
+
+/**
+ * @brief Check if the USART Read Data Register Not Empty Flag is set or not
+ * @rmtoll ISR RXNE LL_USART_IsActiveFlag_RXNE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE));
+}
+
+/**
+ * @brief Check if the USART Transmission Complete Flag is set or not
+ * @rmtoll ISR TC LL_USART_IsActiveFlag_TC
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC));
+}
+
+/**
+ * @brief Check if the USART Transmit Data Register Empty Flag is set or not
+ * @rmtoll ISR TXE LL_USART_IsActiveFlag_TXE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE));
+}
+
+/**
+ * @brief Check if the USART LIN Break Detection Flag is set or not
+ * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll ISR LBDF LL_USART_IsActiveFlag_LBD
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF));
+}
+
+/**
+ * @brief Check if the USART CTS interrupt Flag is set or not
+ * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll ISR CTSIF LL_USART_IsActiveFlag_nCTS
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF));
+}
+
+/**
+ * @brief Check if the USART CTS Flag is set or not
+ * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll ISR CTS LL_USART_IsActiveFlag_CTS
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS));
+}
+
+/**
+ * @brief Check if the USART Receiver Time Out Flag is set or not
+ * @rmtoll ISR RTOF LL_USART_IsActiveFlag_RTO
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF));
+}
+
+/**
+ * @brief Check if the USART End Of Block Flag is set or not
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll ISR EOBF LL_USART_IsActiveFlag_EOB
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF));
+}
+
+/**
+ * @brief Check if the USART Auto-Baud Rate Error Flag is set or not
+ * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * Auto Baud Rate detection feature is supported by the USARTx instance.
+ * @rmtoll ISR ABRE LL_USART_IsActiveFlag_ABRE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE));
+}
+
+/**
+ * @brief Check if the USART Auto-Baud Rate Flag is set or not
+ * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * Auto Baud Rate detection feature is supported by the USARTx instance.
+ * @rmtoll ISR ABRF LL_USART_IsActiveFlag_ABR
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF));
+}
+
+/**
+ * @brief Check if the USART Busy Flag is set or not
+ * @rmtoll ISR BUSY LL_USART_IsActiveFlag_BUSY
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY));
+}
+
+/**
+ * @brief Check if the USART Character Match Flag is set or not
+ * @rmtoll ISR CMF LL_USART_IsActiveFlag_CM
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF));
+}
+
+/**
+ * @brief Check if the USART Send Break Flag is set or not
+ * @rmtoll ISR SBKF LL_USART_IsActiveFlag_SBK
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF));
+}
+
+/**
+ * @brief Check if the USART Receive Wake Up from mute mode Flag is set or not
+ * @rmtoll ISR RWU LL_USART_IsActiveFlag_RWU
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU));
+}
+
+/**
+ * @brief Check if the USART Wake Up from stop mode Flag is set or not
+ * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * Wake-up from Stop mode feature is supported by the USARTx instance.
+ * @rmtoll ISR WUF LL_USART_IsActiveFlag_WKUP
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF));
+}
+
+/**
+ * @brief Check if the USART Transmit Enable Acknowledge Flag is set or not
+ * @rmtoll ISR TEACK LL_USART_IsActiveFlag_TEACK
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK));
+}
+
+/**
+ * @brief Check if the USART Receive Enable Acknowledge Flag is set or not
+ * @rmtoll ISR REACK LL_USART_IsActiveFlag_REACK
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK));
+}
+
+
+/**
+ * @brief Clear Parity Error Flag
+ * @rmtoll ICR PECF LL_USART_ClearFlag_PE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_PECF);
+}
+
+/**
+ * @brief Clear Framing Error Flag
+ * @rmtoll ICR FECF LL_USART_ClearFlag_FE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_FECF);
+}
+
+/**
+ * @brief Clear Noise detected Flag
+ * @rmtoll ICR NCF LL_USART_ClearFlag_NE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_NCF);
+}
+
+/**
+ * @brief Clear OverRun Error Flag
+ * @rmtoll ICR ORECF LL_USART_ClearFlag_ORE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_ORECF);
+}
+
+/**
+ * @brief Clear IDLE line detected Flag
+ * @rmtoll ICR IDLECF LL_USART_ClearFlag_IDLE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_IDLECF);
+}
+
+/**
+ * @brief Clear Transmission Complete Flag
+ * @rmtoll ICR TCCF LL_USART_ClearFlag_TC
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_TCCF);
+}
+
+
+/**
+ * @brief Clear LIN Break Detection Flag
+ * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll ICR LBDCF LL_USART_ClearFlag_LBD
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_LBDCF);
+}
+
+/**
+ * @brief Clear CTS Interrupt Flag
+ * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll ICR CTSCF LL_USART_ClearFlag_nCTS
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_CTSCF);
+}
+
+/**
+ * @brief Clear Receiver Time Out Flag
+ * @rmtoll ICR RTOCF LL_USART_ClearFlag_RTO
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_RTOCF);
+}
+
+/**
+ * @brief Clear End Of Block Flag
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll ICR EOBCF LL_USART_ClearFlag_EOB
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_EOBCF);
+}
+
+/**
+ * @brief Clear Character Match Flag
+ * @rmtoll ICR CMCF LL_USART_ClearFlag_CM
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_CMCF);
+}
+
+/**
+ * @brief Clear Wake Up from stop mode Flag
+ * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * Wake-up from Stop mode feature is supported by the USARTx instance.
+ * @rmtoll ICR WUCF LL_USART_ClearFlag_WKUP
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_WUCF);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_IT_Management IT_Management
+ * @{
+ */
+
+/**
+ * @brief Enable IDLE Interrupt
+ * @rmtoll CR1 IDLEIE LL_USART_EnableIT_IDLE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);
+}
+
+/**
+ * @brief Enable RX Not Empty Interrupt
+ * @rmtoll CR1 RXNEIE LL_USART_EnableIT_RXNE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_RXNEIE);
+}
+
+/**
+ * @brief Enable Transmission Complete Interrupt
+ * @rmtoll CR1 TCIE LL_USART_EnableIT_TC
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_TCIE);
+}
+
+/**
+ * @brief Enable TX Empty Interrupt
+ * @rmtoll CR1 TXEIE LL_USART_EnableIT_TXE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_TXEIE);
+}
+
+/**
+ * @brief Enable Parity Error Interrupt
+ * @rmtoll CR1 PEIE LL_USART_EnableIT_PE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+ * @brief Enable Character Match Interrupt
+ * @rmtoll CR1 CMIE LL_USART_EnableIT_CM
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_CMIE);
+}
+
+/**
+ * @brief Enable Receiver Timeout Interrupt
+ * @rmtoll CR1 RTOIE LL_USART_EnableIT_RTO
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_RTOIE);
+}
+
+/**
+ * @brief Enable End Of Block Interrupt
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR1 EOBIE LL_USART_EnableIT_EOB
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_EOBIE);
+}
+
+/**
+ * @brief Enable LIN Break Detection Interrupt
+ * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR2, USART_CR2_LBDIE);
+}
+
+/**
+ * @brief Enable Error Interrupt
+ * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+ * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
+ * 0: Interrupt is inhibited
+ * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
+ * @rmtoll CR3 EIE LL_USART_EnableIT_ERROR
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+ * @brief Enable CTS Interrupt
+ * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+ * @brief Enable Wake Up from Stop Mode Interrupt
+ * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * Wake-up from Stop mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 WUFIE LL_USART_EnableIT_WKUP
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_WUFIE);
+}
+
+
+/**
+ * @brief Disable IDLE Interrupt
+ * @rmtoll CR1 IDLEIE LL_USART_DisableIT_IDLE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);
+}
+
+/**
+ * @brief Disable RX Not Empty Interrupt
+ * @rmtoll CR1 RXNEIE LL_USART_DisableIT_RXNE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE);
+}
+
+/**
+ * @brief Disable Transmission Complete Interrupt
+ * @rmtoll CR1 TCIE LL_USART_DisableIT_TC
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);
+}
+
+/**
+ * @brief Disable TX Empty Interrupt
+ * @rmtoll CR1 TXEIE LL_USART_DisableIT_TXE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE);
+}
+
+/**
+ * @brief Disable Parity Error Interrupt
+ * @rmtoll CR1 PEIE LL_USART_DisableIT_PE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+ * @brief Disable Character Match Interrupt
+ * @rmtoll CR1 CMIE LL_USART_DisableIT_CM
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE);
+}
+
+/**
+ * @brief Disable Receiver Timeout Interrupt
+ * @rmtoll CR1 RTOIE LL_USART_DisableIT_RTO
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE);
+}
+
+/**
+ * @brief Disable End Of Block Interrupt
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR1 EOBIE LL_USART_DisableIT_EOB
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE);
+}
+
+/**
+ * @brief Disable LIN Break Detection Interrupt
+ * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE);
+}
+
+/**
+ * @brief Disable Error Interrupt
+ * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+ * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
+ * 0: Interrupt is inhibited
+ * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
+ * @rmtoll CR3 EIE LL_USART_DisableIT_ERROR
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+ * @brief Disable CTS Interrupt
+ * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+ * @brief Disable Wake Up from Stop Mode Interrupt
+ * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * Wake-up from Stop mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 WUFIE LL_USART_DisableIT_WKUP
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE);
+}
+
+
+/**
+ * @brief Check if the USART IDLE Interrupt source is enabled or disabled.
+ * @rmtoll CR1 IDLEIE LL_USART_IsEnabledIT_IDLE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE));
+}
+
+/**
+ * @brief Check if the USART RX Not Empty Interrupt is enabled or disabled.
+ * @rmtoll CR1 RXNEIE LL_USART_IsEnabledIT_RXNE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE));
+}
+
+/**
+ * @brief Check if the USART Transmission Complete Interrupt is enabled or disabled.
+ * @rmtoll CR1 TCIE LL_USART_IsEnabledIT_TC
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE));
+}
+
+/**
+ * @brief Check if the USART TX Empty Interrupt is enabled or disabled.
+ * @rmtoll CR1 TXEIE LL_USART_IsEnabledIT_TXE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE));
+}
+
+/**
+ * @brief Check if the USART Parity Error Interrupt is enabled or disabled.
+ * @rmtoll CR1 PEIE LL_USART_IsEnabledIT_PE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE));
+}
+
+/**
+ * @brief Check if the USART Character Match Interrupt is enabled or disabled.
+ * @rmtoll CR1 CMIE LL_USART_IsEnabledIT_CM
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE));
+}
+
+/**
+ * @brief Check if the USART Receiver Timeout Interrupt is enabled or disabled.
+ * @rmtoll CR1 RTOIE LL_USART_IsEnabledIT_RTO
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE));
+}
+
+/**
+ * @brief Check if the USART End Of Block Interrupt is enabled or disabled.
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR1 EOBIE LL_USART_IsEnabledIT_EOB
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE));
+}
+
+/**
+ * @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled.
+ * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE));
+}
+
+/**
+ * @brief Check if the USART Error Interrupt is enabled or disabled.
+ * @rmtoll CR3 EIE LL_USART_IsEnabledIT_ERROR
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE));
+}
+
+/**
+ * @brief Check if the USART CTS Interrupt is enabled or disabled.
+ * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE));
+}
+
+/**
+ * @brief Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.
+ * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * Wake-up from Stop mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 WUFIE LL_USART_IsEnabledIT_WKUP
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE));
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_DMA_Management DMA_Management
+ * @{
+ */
+
+/**
+ * @brief Enable DMA Mode for reception
+ * @rmtoll CR3 DMAR LL_USART_EnableDMAReq_RX
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+ * @brief Disable DMA Mode for reception
+ * @rmtoll CR3 DMAR LL_USART_DisableDMAReq_RX
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+ * @brief Check if DMA Mode is enabled for reception
+ * @rmtoll CR3 DMAR LL_USART_IsEnabledDMAReq_RX
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR));
+}
+
+/**
+ * @brief Enable DMA Mode for transmission
+ * @rmtoll CR3 DMAT LL_USART_EnableDMAReq_TX
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+ * @brief Disable DMA Mode for transmission
+ * @rmtoll CR3 DMAT LL_USART_DisableDMAReq_TX
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+ * @brief Check if DMA Mode is enabled for transmission
+ * @rmtoll CR3 DMAT LL_USART_IsEnabledDMAReq_TX
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT));
+}
+
+/**
+ * @brief Enable DMA Disabling on Reception Error
+ * @rmtoll CR3 DDRE LL_USART_EnableDMADeactOnRxErr
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_DDRE);
+}
+
+/**
+ * @brief Disable DMA Disabling on Reception Error
+ * @rmtoll CR3 DDRE LL_USART_DisableDMADeactOnRxErr
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE);
+}
+
+/**
+ * @brief Indicate if DMA Disabling on Reception Error is disabled
+ * @rmtoll CR3 DDRE LL_USART_IsEnabledDMADeactOnRxErr
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE));
+}
+
+/**
+ * @brief Get the data register address used for DMA transfer
+ * @rmtoll RDR RDR LL_USART_DMA_GetRegAddr\n
+ * @rmtoll TDR TDR LL_USART_DMA_GetRegAddr
+ * @param USARTx USART Instance
+ * @param Direction This parameter can be one of the following values:
+ * @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT
+ * @arg @ref LL_USART_DMA_REG_DATA_RECEIVE
+ * @retval Address of data register
+ */
+__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t Direction)
+{
+ register uint32_t data_reg_addr = 0U;
+
+ if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT)
+ {
+ /* return address of TDR register */
+ data_reg_addr = (uint32_t) &(USARTx->TDR);
+ }
+ else
+ {
+ /* return address of RDR register */
+ data_reg_addr = (uint32_t) &(USARTx->RDR);
+ }
+
+ return data_reg_addr;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_Data_Management Data_Management
+ * @{
+ */
+
+/**
+ * @brief Read Receiver Data register (Receive Data value, 8 bits)
+ * @rmtoll RDR RDR LL_USART_ReceiveData8
+ * @param USARTx USART Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx)
+{
+ return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));
+}
+
+/**
+ * @brief Read Receiver Data register (Receive Data value, 9 bits)
+ * @rmtoll RDR RDR LL_USART_ReceiveData9
+ * @param USARTx USART Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x1FF
+ */
+__STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx)
+{
+ return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));
+}
+
+/**
+ * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits)
+ * @rmtoll TDR TDR LL_USART_TransmitData8
+ * @param USARTx USART Instance
+ * @param Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value)
+{
+ USARTx->TDR = Value;
+}
+
+/**
+ * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits)
+ * @rmtoll TDR TDR LL_USART_TransmitData9
+ * @param USARTx USART Instance
+ * @param Value between Min_Data=0x00 and Max_Data=0x1FF
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value)
+{
+ USARTx->TDR = Value & 0x1FFU;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_Execution Execution
+ * @{
+ */
+
+/**
+ * @brief Request an Automatic Baud Rate measurement on next received data frame
+ * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * Auto Baud Rate detection feature is supported by the USARTx instance.
+ * @rmtoll RQR ABRRQ LL_USART_RequestAutoBaudRate
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->RQR, USART_RQR_ABRRQ);
+}
+
+/**
+ * @brief Request Break sending
+ * @rmtoll RQR SBKRQ LL_USART_RequestBreakSending
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->RQR, USART_RQR_SBKRQ);
+}
+
+/**
+ * @brief Put USART in mute mode and set the RWU flag
+ * @rmtoll RQR MMRQ LL_USART_RequestEnterMuteMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->RQR, USART_RQR_MMRQ);
+}
+
+/**
+ * @brief Request a Receive Data flush
+ * @rmtoll RQR RXFRQ LL_USART_RequestRxDataFlush
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->RQR, USART_RQR_RXFRQ);
+}
+
+/**
+ * @brief Request a Transmit data flush
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll RQR TXFRQ LL_USART_RequestTxDataFlush
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->RQR, USART_RQR_TXFRQ);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx);
+ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct);
+void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct);
+ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
+void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* USART1 || USART2|| USART3 || UART4 || UART5 */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_LL_USART_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_ll_utils.h b/Inc/stm32f3xx_ll_utils.h
new file mode 100644
index 0000000..0d15f65
--- /dev/null
+++ b/Inc/stm32f3xx_ll_utils.h
@@ -0,0 +1,295 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_utils.h
+ * @author MCD Application Team
+ * @brief Header file of UTILS LL module.
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The LL UTILS driver contains a set of generic APIs that can be
+ used by user:
+ (+) Device electronic signature
+ (+) Timing functions
+ (+) PLL configuration functions
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_LL_UTILS_H
+#define __STM32F3xx_LL_UTILS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx.h"
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+/** @defgroup UTILS_LL UTILS
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
+ * @{
+ */
+
+/* Max delay can be used in LL_mDelay */
+#define LL_MAX_DELAY 0xFFFFFFFFU
+
+/**
+ * @brief Unique device ID register base address
+ */
+#define UID_BASE_ADDRESS UID_BASE
+
+/**
+ * @brief Flash size data register base address
+ */
+#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
+
+/**
+ * @brief Package data register base address
+ */
+#define PACKAGE_BASE_ADDRESS PACKAGE_BASE
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
+ * @{
+ */
+/**
+ * @brief UTILS PLL structure definition
+ */
+typedef struct
+{
+ uint32_t PLLMul; /*!< Multiplication factor for PLL VCO input clock.
+ This parameter can be a value of @ref RCC_LL_EC_PLL_MUL
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RCC_PLL_ConfigDomain_SYS(). */
+
+#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
+ uint32_t PLLDiv; /*!< Division factor for PLL VCO output clock.
+ This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RCC_PLL_ConfigDomain_SYS(). */
+#else
+ uint32_t Prediv; /*!< Division factor for HSE used as PLL clock source.
+ This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RCC_PLL_ConfigDomain_SYS(). */
+#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
+} LL_UTILS_PLLInitTypeDef;
+
+/**
+ * @brief UTILS System, AHB and APB buses clock configuration structure definition
+ */
+typedef struct
+{
+ uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
+ This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RCC_SetAHBPrescaler(). */
+
+ uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
+ This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RCC_SetAPB1Prescaler(). */
+
+ uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
+ This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RCC_SetAPB2Prescaler(). */
+
+} LL_UTILS_ClkInitTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
+ * @{
+ */
+
+/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
+ * @{
+ */
+#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */
+#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
+ * @{
+ */
+
+/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
+ * @{
+ */
+
+/**
+ * @brief Get Word0 of the unique device identifier (UID based on 96 bits)
+ * @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format
+ */
+__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
+{
+ return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
+}
+
+/**
+ * @brief Get Word1 of the unique device identifier (UID based on 96 bits)
+ * @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40])
+ */
+__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
+{
+ return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
+}
+
+/**
+ * @brief Get Word2 of the unique device identifier (UID based on 96 bits)
+ * @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24]
+ */
+__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
+{
+ return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
+}
+
+/**
+ * @brief Get Flash memory size
+ * @note This bitfield indicates the size of the device Flash memory expressed in
+ * Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
+ * @retval FLASH_SIZE[15:0]: Flash memory size
+ */
+__STATIC_INLINE uint32_t LL_GetFlashSize(void)
+{
+ return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)));
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup UTILS_LL_EF_DELAY DELAY
+ * @{
+ */
+
+/**
+ * @brief This function configures the Cortex-M SysTick source of the time base.
+ * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
+ * @note When a RTOS is used, it is recommended to avoid changing the SysTick
+ * configuration by calling this function, for a delay use rather osDelay RTOS service.
+ * @param Ticks Number of ticks
+ * @retval None
+ */
+__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
+{
+ /* Configure the SysTick to have interrupt in 1ms time base */
+ SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
+}
+
+void LL_Init1msTick(uint32_t HCLKFrequency);
+void LL_mDelay(uint32_t Delay);
+
+/**
+ * @}
+ */
+
+/** @defgroup UTILS_EF_SYSTEM SYSTEM
+ * @{
+ */
+
+void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
+ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
+ LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
+ LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_LL_UTILS_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f3xx_ll_wwdg.h b/Inc/stm32f3xx_ll_wwdg.h
new file mode 100644
index 0000000..df52fd1
--- /dev/null
+++ b/Inc/stm32f3xx_ll_wwdg.h
@@ -0,0 +1,340 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_wwdg.h
+ * @author MCD Application Team
+ * @brief Header file of WWDG LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_LL_WWDG_H
+#define __STM32F3xx_LL_WWDG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx.h"
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined (WWDG)
+
+/** @defgroup WWDG_LL WWDG
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants
+ * @{
+ */
+
+
+/** @defgroup WWDG_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions
+ * @{
+ */
+#define LL_WWDG_CFR_EWI WWDG_CFR_EWI
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_LL_EC_PRESCALER PRESCALER
+* @{
+*/
+#define LL_WWDG_PRESCALER_1 0x00000000U /*!< WWDG counter clock = (PCLK1/4096)/1 */
+#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
+#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
+#define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros
+ * @{
+ */
+/** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros
+ * @{
+ */
+/**
+ * @brief Write a value in WWDG register
+ * @param __INSTANCE__ WWDG Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in WWDG register
+ * @param __INSTANCE__ WWDG Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions
+ * @{
+ */
+
+/** @defgroup WWDG_LL_EF_Configuration Configuration
+ * @{
+ */
+/**
+ * @brief Enable Window Watchdog. The watchdog is always disabled after a reset.
+ * @note It is enabled by setting the WDGA bit in the WWDG_CR register,
+ * then it cannot be disabled again except by a reset.
+ * This bit is set by software and only cleared by hardware after a reset.
+ * When WDGA = 1, the watchdog can generate a reset.
+ * @rmtoll CR WDGA LL_WWDG_Enable
+ * @param WWDGx WWDG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx)
+{
+ SET_BIT(WWDGx->CR, WWDG_CR_WDGA);
+}
+
+/**
+ * @brief Checks if Window Watchdog is enabled
+ * @rmtoll CR WDGA LL_WWDG_IsEnabled
+ * @param WWDGx WWDG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx)
+{
+ return (READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA));
+}
+
+/**
+ * @brief Set the Watchdog counter value to provided value (7-bits T[6:0])
+ * @note When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset
+ * This counter is decremented every (4096 x 2expWDGTB) PCLK cycles
+ * A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared)
+ * Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
+ * @rmtoll CR T LL_WWDG_SetCounter
+ * @param WWDGx WWDG Instance
+ * @param Counter 0..0x7F (7 bit counter value)
+ * @retval None
+ */
+__STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter)
+{
+ MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter);
+}
+
+/**
+ * @brief Return current Watchdog Counter Value (7 bits counter value)
+ * @rmtoll CR T LL_WWDG_GetCounter
+ * @param WWDGx WWDG Instance
+ * @retval 7 bit Watchdog Counter value
+ */
+__STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)
+{
+ return (uint32_t)(READ_BIT(WWDGx->CR, WWDG_CR_T));
+}
+
+/**
+ * @brief Set the time base of the prescaler (WDGTB).
+ * @note Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter
+ * is decremented every (4096 x 2expWDGTB) PCLK cycles
+ * @rmtoll CFR WDGTB LL_WWDG_SetPrescaler
+ * @param WWDGx WWDG Instance
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_WWDG_PRESCALER_1
+ * @arg @ref LL_WWDG_PRESCALER_2
+ * @arg @ref LL_WWDG_PRESCALER_4
+ * @arg @ref LL_WWDG_PRESCALER_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
+{
+ MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler);
+}
+
+/**
+ * @brief Return current Watchdog Prescaler Value
+ * @rmtoll CFR WDGTB LL_WWDG_GetPrescaler
+ * @param WWDGx WWDG Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_WWDG_PRESCALER_1
+ * @arg @ref LL_WWDG_PRESCALER_2
+ * @arg @ref LL_WWDG_PRESCALER_4
+ * @arg @ref LL_WWDG_PRESCALER_8
+ */
+__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx)
+{
+ return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
+}
+
+/**
+ * @brief Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
+ * @note This window value defines when write in the WWDG_CR register
+ * to program Watchdog counter is allowed.
+ * Watchdog counter value update must occur only when the counter value
+ * is lower than the Watchdog window register value.
+ * Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value
+ * (in the control register) is refreshed before the downcounter has reached
+ * the watchdog window register value.
+ * Physically is possible to set the Window lower then 0x40 but it is not recommended.
+ * To generate an immediate reset, it is possible to set the Counter lower than 0x40.
+ * @rmtoll CFR W LL_WWDG_SetWindow
+ * @param WWDGx WWDG Instance
+ * @param Window 0x00..0x7F (7 bit Window value)
+ * @retval None
+ */
+__STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window)
+{
+ MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window);
+}
+
+/**
+ * @brief Return current Watchdog Window Value (7 bits value)
+ * @rmtoll CFR W LL_WWDG_GetWindow
+ * @param WWDGx WWDG Instance
+ * @retval 7 bit Watchdog Window value
+ */
+__STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
+{
+ return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_W));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+/**
+ * @brief Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
+ * @note This bit is set by hardware when the counter has reached the value 0x40.
+ * It must be cleared by software by writing 0.
+ * A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
+ * @rmtoll SR EWIF LL_WWDG_IsActiveFlag_EWKUP
+ * @param WWDGx WWDG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx)
+{
+ return (READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF));
+}
+
+/**
+ * @brief Clear WWDG Early Wakeup Interrupt Flag (EWIF)
+ * @rmtoll SR EWIF LL_WWDG_ClearFlag_EWKUP
+ * @param WWDGx WWDG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx)
+{
+ WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_LL_EF_IT_Management IT_Management
+ * @{
+ */
+/**
+ * @brief Enable the Early Wakeup Interrupt.
+ * @note When set, an interrupt occurs whenever the counter reaches value 0x40.
+ * This interrupt is only cleared by hardware after a reset
+ * @rmtoll CFR EWI LL_WWDG_EnableIT_EWKUP
+ * @param WWDGx WWDG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx)
+{
+ SET_BIT(WWDGx->CFR, WWDG_CFR_EWI);
+}
+
+/**
+ * @brief Check if Early Wakeup Interrupt is enabled
+ * @rmtoll CFR EWI LL_WWDG_IsEnabledIT_EWKUP
+ * @param WWDGx WWDG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx)
+{
+ return (READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI));
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* WWDG */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_LL_WWDG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/License.md b/License.md
new file mode 100644
index 0000000..d95c1db
--- /dev/null
+++ b/License.md
@@ -0,0 +1,3 @@
+# Copyright (c) 2017 STMicroelectronics
+
+This software component is licensed by STMicroelectronics under the **BSD 3-Clause** license. You may not use this file except in compliance with this license. You may obtain a copy of the license [here](https://opensource.org/licenses/BSD-3-Clause).
diff --git a/README.md b/README.md
index 9a6d1ee..f57b218 100644
--- a/README.md
+++ b/README.md
@@ -1,2 +1,45 @@
-# stm32f3xx_hal_driver
-Provides the STM32Cube MCU Component "hal_driver" of the STM32F3 series.
+# STM32CubeF3 HAL Driver MCU Component
+
+## Overview
+
+**STM32Cube** is an STMicroelectronics original initiative to ease the developers life by reducing efforts, time and cost.
+
+**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform, delivered for each STM32 series.
+ * The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product
+ * The STM32 HAL-LL drivers : an abstraction drivers layer, the API ensuring maximized portability across the STM32 portfolio
+ * The BSP Drivers of each evaluation or demonstration board provided by this STM32 series
+ * A consistent set of middlewares components such as RTOS, USB, FatFS, Graphics, STM32_TouchSensing_Library ...
+ * A full set of software projects (basic examples, applications or demonstrations) for each board provided by this STM32 series
+
+Two models of publication are proposed for the STM32Cube embedded software:
+ * The monolithic **MCU Package** : all STM32Cube software modules of one STM32 series are present (Drivers, Middlewares, Projects, Utilities) in the repo (usual name **STM32Cubexx**, xx corresponding to the STM32 series)
+ * The **MCU component** : progressively from November 2019, each STM32Cube software module being part of the STM32Cube MCU Package, will be delivered as an individual repo, allowing the user to select and get only the required software functions.
+
+## Description
+
+This **stm32f3xx_hal_driver** MCU component repo is one element of the STM32CubeF3 MCU embedded software package, providing the **HAL-LL Drivers** part.
+
+## License
+
+Copyright (c) 2017 STMicroelectronics.
+
+This software component is licensed by STMicroelectronics under BSD 3-Clause license. You may not use this file except in compliance with the License.
+You may obtain a copy of the License [here](https://opensource.org/licenses/BSD-3-Clause).
+
+## Compatibility information
+
+In this table, you can find the successive versions of this HAL-LL Driver component, in line with the corresponding versions of the full MCU package:
+
+It is **crucial** that you use a consistent set of versions for the CMSIS Core - CMSIS Device - HAL, as mentioned in this table.
+
+HAL Driver F3 | CMSIS Device F3 | CMSIS Core | Was delivered in the full MCU package
+------------- | --------------- | ---------- | -------------------------------------
+Tag v1.5.2 | Tag v2.3.3 | Tag v4.5_cm4 | Tag v1.10.0 (and following, if any, till next new tag)
+
+The full **STM32CubeF3** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeF3).
+
+## Troubleshooting
+
+If you have any issue with the **Software content** of this repo, you can [file an issue on Github](https://github.com/STMicroelectronics/stm32f3xx_hal_driver/issues/new).
+
+For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus).
diff --git a/Release_Notes.html b/Release_Notes.html
new file mode 100644
index 0000000..0a04f5e
--- /dev/null
+++ b/Release_Notes.html
@@ -0,0 +1,1133 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns:m="http://schemas.microsoft.com/office/2004/12/omml" xmlns="http://www.w3.org/TR/REC-html40"><head>
+<meta http-equiv="Content-Type" content="text/html; charset=windows-1252">
+<link rel="File-List" href="Release_Notes_for_STM32F45x_StdPeriph_Driver_files/filelist.xml">
+<link rel="Edit-Time-Data" href="Release_Notes_for_STM32F45x_StdPeriph_Driver_files/editdata.mso"><!--[if !mso]> <style> v\:* {behavior:url(#default#VML);} o\:* {behavior:url(#default#VML);} w\:* {behavior:url(#default#VML);} .shape {behavior:url(#default#VML);} </style> <![endif]-->
+
+
+
+<title>Release Notes for STM32F3xx HAL Drivers</title><!--[if gte mso 9]><xml> <o:DocumentProperties> <o:Author>STMicroelectronics</o:Author> <o:LastAuthor>Raouf Hosni</o:LastAuthor> <o:Revision>39</o:Revision> <o:TotalTime>137</o:TotalTime> <o:Created>2009-02-27T19:26:00Z</o:Created> <o:LastSaved>2010-10-15T11:07:00Z</o:LastSaved> <o:Pages>3</o:Pages> <o:Words>973</o:Words> <o:Characters>5548</o:Characters> <o:Company>STMicroelectronics</o:Company> <o:Lines>46</o:Lines> <o:Paragraphs>13</o:Paragraphs> <o:CharactersWithSpaces>6508</o:CharactersWithSpaces> <o:Version>12.00</o:Version> </o:DocumentProperties> </xml><![endif]--><link rel="themeData" href="Release_Notes_for_STM32F45x_StdPeriph_Driver_files/themedata.thmx">
+<link rel="colorSchemeMapping" href="Release_Notes_for_STM32F45x_StdPeriph_Driver_files/colorschememapping.xml"><!--[if gte mso 9]><xml> <w:WordDocument> <w:Zoom>110</w:Zoom> <w:TrackMoves>false</w:TrackMoves> <w:TrackFormatting/> <w:ValidateAgainstSchemas/> <w:SaveIfXMLInvalid>false</w:SaveIfXMLInvalid> <w:IgnoreMixedContent>false</w:IgnoreMixedContent> <w:AlwaysShowPlaceholderText>false</w:AlwaysShowPlaceholderText> <w:DoNotPromoteQF/> <w:LidThemeOther>EN-US</w:LidThemeOther> <w:LidThemeAsian>X-NONE</w:LidThemeAsian> <w:LidThemeComplexScript>X-NONE</w:LidThemeComplexScript> <w:Compatibility> <w:BreakWrappedTables/> <w:SnapToGridInCell/> <w:WrapTextWithPunct/> <w:UseAsianBreakRules/> <w:DontGrowAutofit/> <w:SplitPgBreakAndParaMark/> <w:DontVertAlignCellWithSp/> <w:DontBreakConstrainedForcedTables/> <w:DontVertAlignInTxbx/> <w:Word11KerningPairs/> <w:CachedColBalance/> </w:Compatibility> <w:BrowserLevel>MicrosoftInternetExplorer4</w:BrowserLevel> <m:mathPr> <m:mathFont m:val="Cambria Math"/> <m:brkBin m:val="before"/> <m:brkBinSub m:val="--"/> <m:smallFrac m:val="off"/> <m:dispDef/> <m:lMargin m:val="0"/> <m:rMargin m:val="0"/> <m:defJc m:val="centerGroup"/> <m:wrapIndent m:val="1440"/> <m:intLim m:val="subSup"/> <m:naryLim m:val="undOvr"/> </m:mathPr></w:WordDocument> </xml><![endif]--><!--[if gte mso 9]><xml> <w:LatentStyles DefLockedState="false" DefUnhideWhenUsed="false" DefSemiHidden="false" DefQFormat="false" LatentStyleCount="267"> <w:LsdException Locked="false" QFormat="true" Name="Normal"/> <w:LsdException Locked="false" QFormat="true" Name="heading 1"/> <w:LsdException Locked="false" QFormat="true" Name="heading 2"/> <w:LsdException Locked="false" QFormat="true" Name="heading 3"/> <w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true" QFormat="true" Name="heading 4"/> <w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true" QFormat="true" Name="heading 5"/> <w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true" QFormat="true" Name="heading 6"/> <w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true" QFormat="true" Name="heading 7"/> <w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true" QFormat="true" Name="heading 8"/> <w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true" QFormat="true" Name="heading 9"/> <w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true" QFormat="true" Name="caption"/> <w:LsdException Locked="false" QFormat="true" Name="Title"/> <w:LsdException Locked="false" Priority="1" Name="Default Paragraph Font"/> <w:LsdException Locked="false" QFormat="true" Name="Subtitle"/> <w:LsdException Locked="false" QFormat="true" Name="Strong"/> <w:LsdException Locked="false" QFormat="true" Name="Emphasis"/> <w:LsdException Locked="false" Priority="99" Name="No List"/> <w:LsdException Locked="false" Priority="99" SemiHidden="true" Name="Placeholder Text"/> <w:LsdException Locked="false" Priority="1" QFormat="true" Name="No Spacing"/> <w:LsdException Locked="false" Priority="60" Name="Light Shading"/> <w:LsdException Locked="false" Priority="61" Name="Light List"/> <w:LsdException Locked="false" Priority="62" Name="Light Grid"/> <w:LsdException Locked="false" Priority="63" Name="Medium Shading 1"/> <w:LsdException Locked="false" Priority="64" Name="Medium Shading 2"/> <w:LsdException Locked="false" Priority="65" Name="Medium List 1"/> <w:LsdException Locked="false" Priority="66" Name="Medium List 2"/> <w:LsdException Locked="false" Priority="67" Name="Medium Grid 1"/> <w:LsdException Locked="false" Priority="68" Name="Medium Grid 2"/> <w:LsdException Locked="false" Priority="69" Name="Medium Grid 3"/> <w:LsdException Locked="false" Priority="70" Name="Dark List"/> <w:LsdException Locked="false" Priority="71" Name="Colorful Shading"/> <w:LsdException Locked="false" Priority="72" Name="Colorful List"/> <w:LsdException Locked="false" Priority="73" Name="Colorful Grid"/> <w:LsdException Locked="false" Priority="60" Name="Light Shading Accent 1"/> <w:LsdException Locked="false" Priority="61" Name="Light List Accent 1"/> <w:LsdException Locked="false" Priority="62" Name="Light Grid Accent 1"/> <w:LsdException Locked="false" Priority="63" Name="Medium Shading 1 Accent 1"/> <w:LsdException Locked="false" Priority="64" Name="Medium Shading 2 Accent 1"/> <w:LsdException Locked="false" Priority="65" Name="Medium List 1 Accent 1"/> <w:LsdException Locked="false" Priority="99" SemiHidden="true" Name="Revision"/> <w:LsdException Locked="false" Priority="34" QFormat="true" Name="List Paragraph"/> <w:LsdException Locked="false" Priority="29" QFormat="true" Name="Quote"/> <w:LsdException Locked="false" Priority="30" QFormat="true" Name="Intense Quote"/> <w:LsdException Locked="false" Priority="66" Name="Medium List 2 Accent 1"/> <w:LsdException Locked="false" Priority="67" Name="Medium Grid 1 Accent 1"/> <w:LsdException Locked="false" Priority="68" Name="Medium Grid 2 Accent 1"/> <w:LsdException Locked="false" Priority="69" Name="Medium Grid 3 Accent 1"/> <w:LsdException Locked="false" Priority="70" Name="Dark List Accent 1"/> <w:LsdException Locked="false" Priority="71" Name="Colorful Shading Accent 1"/> <w:LsdException Locked="false" Priority="72" Name="Colorful List Accent 1"/> <w:LsdException Locked="false" Priority="73" Name="Colorful Grid Accent 1"/> <w:LsdException Locked="false" Priority="60" Name="Light Shading Accent 2"/> <w:LsdException Locked="false" Priority="61" Name="Light List Accent 2"/> <w:LsdException Locked="false" Priority="62" Name="Light Grid Accent 2"/> <w:LsdException Locked="false" Priority="63" Name="Medium Shading 1 Accent 2"/> <w:LsdException Locked="false" Priority="64" Name="Medium Shading 2 Accent 2"/> <w:LsdException Locked="false" Priority="65" Name="Medium List 1 Accent 2"/> <w:LsdException Locked="false" Priority="66" Name="Medium List 2 Accent 2"/> <w:LsdException Locked="false" Priority="67" Name="Medium Grid 1 Accent 2"/> <w:LsdException Locked="false" Priority="68" Name="Medium Grid 2 Accent 2"/> <w:LsdException Locked="false" Priority="69" Name="Medium Grid 3 Accent 2"/> <w:LsdException Locked="false" Priority="70" Name="Dark List Accent 2"/> <w:LsdException Locked="false" Priority="71" Name="Colorful Shading Accent 2"/> <w:LsdException Locked="false" Priority="72" Name="Colorful List Accent 2"/> <w:LsdException Locked="false" Priority="73" Name="Colorful Grid Accent 2"/> <w:LsdException Locked="false" Priority="60" Name="Light Shading Accent 3"/> <w:LsdException Locked="false" Priority="61" Name="Light List Accent 3"/> <w:LsdException Locked="false" Priority="62" Name="Light Grid Accent 3"/> <w:LsdException Locked="false" Priority="63" Name="Medium Shading 1 Accent 3"/> <w:LsdException Locked="false" Priority="64" Name="Medium Shading 2 Accent 3"/> <w:LsdException Locked="false" Priority="65" Name="Medium List 1 Accent 3"/> <w:LsdException Locked="false" Priority="66" Name="Medium List 2 Accent 3"/> <w:LsdException Locked="false" Priority="67" Name="Medium Grid 1 Accent 3"/> <w:LsdException Locked="false" Priority="68" Name="Medium Grid 2 Accent 3"/> <w:LsdException Locked="false" Priority="69" Name="Medium Grid 3 Accent 3"/> <w:LsdException Locked="false" Priority="70" Name="Dark List Accent 3"/> <w:LsdException Locked="false" Priority="71" Name="Colorful Shading Accent 3"/> <w:LsdException Locked="false" Priority="72" Name="Colorful List Accent 3"/> <w:LsdException Locked="false" Priority="73" Name="Colorful Grid Accent 3"/> <w:LsdException Locked="false" Priority="60" Name="Light Shading Accent 4"/> <w:LsdException Locked="false" Priority="61" Name="Light List Accent 4"/> <w:LsdException Locked="false" Priority="62" Name="Light Grid Accent 4"/> <w:LsdException Locked="false" Priority="63" Name="Medium Shading 1 Accent 4"/> <w:LsdException Locked="false" Priority="64" Name="Medium Shading 2 Accent 4"/> <w:LsdException Locked="false" Priority="65" Name="Medium List 1 Accent 4"/> <w:LsdException Locked="false" Priority="66" Name="Medium List 2 Accent 4"/> <w:LsdException Locked="false" Priority="67" Name="Medium Grid 1 Accent 4"/> <w:LsdException Locked="false" Priority="68" Name="Medium Grid 2 Accent 4"/> <w:LsdException Locked="false" Priority="69" Name="Medium Grid 3 Accent 4"/> <w:LsdException Locked="false" Priority="70" Name="Dark List Accent 4"/> <w:LsdException Locked="false" Priority="71" Name="Colorful Shading Accent 4"/> <w:LsdException Locked="false" Priority="72" Name="Colorful List Accent 4"/> <w:LsdException Locked="false" Priority="73" Name="Colorful Grid Accent 4"/> <w:LsdException Locked="false" Priority="60" Name="Light Shading Accent 5"/> <w:LsdException Locked="false" Priority="61" Name="Light List Accent 5"/> <w:LsdException Locked="false" Priority="62" Name="Light Grid Accent 5"/> <w:LsdException Locked="false" Priority="63" Name="Medium Shading 1 Accent 5"/> <w:LsdException Locked="false" Priority="64" Name="Medium Shading 2 Accent 5"/> <w:LsdException Locked="false" Priority="65" Name="Medium List 1 Accent 5"/> <w:LsdException Locked="false" Priority="66" Name="Medium List 2 Accent 5"/> <w:LsdException Locked="false" Priority="67" Name="Medium Grid 1 Accent 5"/> <w:LsdException Locked="false" Priority="68" Name="Medium Grid 2 Accent 5"/> <w:LsdException Locked="false" Priority="69" Name="Medium Grid 3 Accent 5"/> <w:LsdException Locked="false" Priority="70" Name="Dark List Accent 5"/> <w:LsdException Locked="false" Priority="71" Name="Colorful Shading Accent 5"/> <w:LsdException Locked="false" Priority="72" Name="Colorful List Accent 5"/> <w:LsdException Locked="false" Priority="73" Name="Colorful Grid Accent 5"/> <w:LsdException Locked="false" Priority="60" Name="Light Shading Accent 6"/> <w:LsdException Locked="false" Priority="61" Name="Light List Accent 6"/> <w:LsdException Locked="false" Priority="62" Name="Light Grid Accent 6"/> <w:LsdException Locked="false" Priority="63" Name="Medium Shading 1 Accent 6"/> <w:LsdException Locked="false" Priority="64" Name="Medium Shading 2 Accent 6"/> <w:LsdException Locked="false" Priority="65" Name="Medium List 1 Accent 6"/> <w:LsdException Locked="false" Priority="66" Name="Medium List 2 Accent 6"/> <w:LsdException Locked="false" Priority="67" Name="Medium Grid 1 Accent 6"/> <w:LsdException Locked="false" Priority="68" Name="Medium Grid 2 Accent 6"/> <w:LsdException Locked="false" Priority="69" Name="Medium Grid 3 Accent 6"/> <w:LsdException Locked="false" Priority="70" Name="Dark List Accent 6"/> <w:LsdException Locked="false" Priority="71" Name="Colorful Shading Accent 6"/> <w:LsdException Locked="false" Priority="72" Name="Colorful List Accent 6"/> <w:LsdException Locked="false" Priority="73" Name="Colorful Grid Accent 6"/> <w:LsdException Locked="false" Priority="19" QFormat="true" Name="Subtle Emphasis"/> <w:LsdException Locked="false" Priority="21" QFormat="true" Name="Intense Emphasis"/> <w:LsdException Locked="false" Priority="31" QFormat="true" Name="Subtle Reference"/> <w:LsdException Locked="false" Priority="32" QFormat="true" Name="Intense Reference"/> <w:LsdException Locked="false" Priority="33" QFormat="true" Name="Book Title"/> <w:LsdException Locked="false" Priority="37" SemiHidden="true" UnhideWhenUsed="true" Name="Bibliography"/> <w:LsdException Locked="false" Priority="39" SemiHidden="true" UnhideWhenUsed="true" QFormat="true" Name="TOC Heading"/> </w:LatentStyles> </xml><![endif]-->
+
+<style>
+<!--
+/* Font Definitions */
+@font-face
+{font-family:"Cambria Math";
+panose-1:2 4 5 3 5 4 6 3 2 4;
+mso-font-charset:1;
+mso-generic-font-family:roman;
+mso-font-format:other;
+mso-font-pitch:variable;
+mso-font-signature:0 0 0 0 0 0;}
+@font-face
+{font-family:Calibri;
+panose-1:2 15 5 2 2 2 4 3 2 4;
+mso-font-charset:0;
+mso-generic-font-family:swiss;
+mso-font-pitch:variable;
+mso-font-signature:-1610611985 1073750139 0 0 159 0;}
+@font-face
+{font-family:Tahoma;
+panose-1:2 11 6 4 3 5 4 4 2 4;
+mso-font-charset:0;
+mso-generic-font-family:swiss;
+mso-font-pitch:variable;
+mso-font-signature:1627400839 -2147483648 8 0 66047 0;}
+@font-face
+{font-family:Verdana;
+panose-1:2 11 6 4 3 5 4 4 2 4;
+mso-font-charset:0;
+mso-generic-font-family:swiss;
+mso-font-pitch:variable;
+mso-font-signature:536871559 0 0 0 415 0;}
+/* Style Definitions */
+p.MsoNormal, li.MsoNormal, div.MsoNormal
+{mso-style-unhide:no;
+mso-style-qformat:yes;
+mso-style-parent:"";
+margin:0in;
+margin-bottom:.0001pt;
+mso-pagination:widow-orphan;
+font-size:12.0pt;
+font-family:"Times New Roman","serif";
+mso-fareast-font-family:"Times New Roman";}
+h1
+{mso-style-unhide:no;
+mso-style-qformat:yes;
+mso-style-link:"Heading 1 Char";
+mso-margin-top-alt:auto;
+margin-right:0in;
+mso-margin-bottom-alt:auto;
+margin-left:0in;
+mso-pagination:widow-orphan;
+mso-outline-level:1;
+font-size:24.0pt;
+font-family:"Times New Roman","serif";
+mso-fareast-font-family:"Times New Roman";
+mso-fareast-theme-font:minor-fareast;
+font-weight:bold;}
+h2
+{mso-style-unhide:no;
+mso-style-qformat:yes;
+mso-style-link:"Heading 2 Char";
+mso-style-next:Normal;
+margin-top:12.0pt;
+margin-right:0in;
+margin-bottom:3.0pt;
+margin-left:0in;
+mso-pagination:widow-orphan;
+page-break-after:avoid;
+mso-outline-level:2;
+font-size:14.0pt;
+font-family:"Arial","sans-serif";
+mso-fareast-font-family:"Times New Roman";
+mso-fareast-theme-font:minor-fareast;
+font-weight:bold;
+font-style:italic;}
+h3
+{mso-style-unhide:no;
+mso-style-qformat:yes;
+mso-style-link:"Heading 3 Char";
+mso-margin-top-alt:auto;
+margin-right:0in;
+mso-margin-bottom-alt:auto;
+margin-left:0in;
+mso-pagination:widow-orphan;
+mso-outline-level:3;
+font-size:13.5pt;
+font-family:"Times New Roman","serif";
+mso-fareast-font-family:"Times New Roman";
+mso-fareast-theme-font:minor-fareast;
+font-weight:bold;}
+a:link, span.MsoHyperlink
+{mso-style-unhide:no;
+color:blue;
+text-decoration:underline;
+text-underline:single;}
+a:visited, span.MsoHyperlinkFollowed
+{mso-style-unhide:no;
+color:blue;
+text-decoration:underline;
+text-underline:single;}
+p
+{mso-style-unhide:no;
+mso-margin-top-alt:auto;
+margin-right:0in;
+mso-margin-bottom-alt:auto;
+margin-left:0in;
+mso-pagination:widow-orphan;
+font-size:12.0pt;
+font-family:"Times New Roman","serif";
+mso-fareast-font-family:"Times New Roman";}
+p.MsoAcetate, li.MsoAcetate, div.MsoAcetate
+{mso-style-unhide:no;
+mso-style-link:"Balloon Text Char";
+margin:0in;
+margin-bottom:.0001pt;
+mso-pagination:widow-orphan;
+font-size:8.0pt;
+font-family:"Tahoma","sans-serif";
+mso-fareast-font-family:"Times New Roman";}
+span.Heading1Char
+{mso-style-name:"Heading 1 Char";
+mso-style-unhide:no;
+mso-style-locked:yes;
+mso-style-link:"Heading 1";
+mso-ansi-font-size:14.0pt;
+mso-bidi-font-size:14.0pt;
+font-family:"Cambria","serif";
+mso-ascii-font-family:Cambria;
+mso-ascii-theme-font:major-latin;
+mso-fareast-font-family:"Times New Roman";
+mso-fareast-theme-font:major-fareast;
+mso-hansi-font-family:Cambria;
+mso-hansi-theme-font:major-latin;
+mso-bidi-font-family:"Times New Roman";
+mso-bidi-theme-font:major-bidi;
+color:#365F91;
+mso-themecolor:accent1;
+mso-themeshade:191;
+font-weight:bold;}
+span.Heading2Char
+{mso-style-name:"Heading 2 Char";
+mso-style-unhide:no;
+mso-style-locked:yes;
+mso-style-link:"Heading 2";
+mso-ansi-font-size:13.0pt;
+mso-bidi-font-size:13.0pt;
+font-family:"Cambria","serif";
+mso-ascii-font-family:Cambria;
+mso-ascii-theme-font:major-latin;
+mso-fareast-font-family:"Times New Roman";
+mso-fareast-theme-font:major-fareast;
+mso-hansi-font-family:Cambria;
+mso-hansi-theme-font:major-latin;
+mso-bidi-font-family:"Times New Roman";
+mso-bidi-theme-font:major-bidi;
+color:#4F81BD;
+mso-themecolor:accent1;
+font-weight:bold;}
+span.Heading3Char
+{mso-style-name:"Heading 3 Char";
+mso-style-unhide:no;
+mso-style-locked:yes;
+mso-style-link:"Heading 3";
+mso-ansi-font-size:12.0pt;
+mso-bidi-font-size:12.0pt;
+font-family:"Cambria","serif";
+mso-ascii-font-family:Cambria;
+mso-ascii-theme-font:major-latin;
+mso-fareast-font-family:"Times New Roman";
+mso-fareast-theme-font:major-fareast;
+mso-hansi-font-family:Cambria;
+mso-hansi-theme-font:major-latin;
+mso-bidi-font-family:"Times New Roman";
+mso-bidi-theme-font:major-bidi;
+color:#4F81BD;
+mso-themecolor:accent1;
+font-weight:bold;}
+span.BalloonTextChar
+{mso-style-name:"Balloon Text Char";
+mso-style-unhide:no;
+mso-style-locked:yes;
+mso-style-link:"Balloon Text";
+mso-ansi-font-size:8.0pt;
+mso-bidi-font-size:8.0pt;
+font-family:"Tahoma","sans-serif";
+mso-ascii-font-family:Tahoma;
+mso-hansi-font-family:Tahoma;
+mso-bidi-font-family:Tahoma;}
+.MsoChpDefault
+{mso-style-type:export-only;
+mso-default-props:yes;
+font-size:10.0pt;
+mso-ansi-font-size:10.0pt;
+mso-bidi-font-size:10.0pt;}
+@page WordSection1
+{size:8.5in 11.0in;
+margin:1.0in 1.25in 1.0in 1.25in;
+mso-header-margin:.5in;
+mso-footer-margin:.5in;
+mso-paper-source:0;}
+div.WordSection1
+{page:WordSection1;}
+/* List Definitions */
+@list l0
+{mso-list-id:62067358;
+mso-list-template-ids:-174943062;}
+@list l0:level1
+{mso-level-number-format:bullet;
+mso-level-text:\F0B7;
+mso-level-tab-stop:.5in;
+mso-level-number-position:left;
+text-indent:-.25in;
+mso-ansi-font-size:10.0pt;
+font-family:Symbol;}
+@list l0:level2
+{mso-level-tab-stop:1.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l0:level3
+{mso-level-tab-stop:1.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l0:level4
+{mso-level-tab-stop:2.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l0:level5
+{mso-level-tab-stop:2.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l0:level6
+{mso-level-tab-stop:3.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l0:level7
+{mso-level-tab-stop:3.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l0:level8
+{mso-level-tab-stop:4.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l0:level9
+{mso-level-tab-stop:4.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l1
+{mso-list-id:128015942;
+mso-list-template-ids:-90681214;}
+@list l1:level1
+{mso-level-tab-stop:.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l1:level2
+{mso-level-tab-stop:1.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l1:level3
+{mso-level-tab-stop:1.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l1:level4
+{mso-level-tab-stop:2.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l1:level5
+{mso-level-tab-stop:2.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l1:level6
+{mso-level-tab-stop:3.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l1:level7
+{mso-level-tab-stop:3.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l1:level8
+{mso-level-tab-stop:4.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l1:level9
+{mso-level-tab-stop:4.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l2
+{mso-list-id:216556000;
+mso-list-template-ids:925924412;}
+@list l2:level1
+{mso-level-number-format:bullet;
+mso-level-text:\F0B7;
+mso-level-tab-stop:.5in;
+mso-level-number-position:left;
+text-indent:-.25in;
+mso-ansi-font-size:10.0pt;
+font-family:Symbol;}
+@list l2:level2
+{mso-level-number-format:bullet;
+mso-level-text:\F0B7;
+mso-level-tab-stop:1.0in;
+mso-level-number-position:left;
+text-indent:-.25in;
+mso-ansi-font-size:10.0pt;
+font-family:Symbol;}
+@list l2:level3
+{mso-level-tab-stop:1.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l2:level4
+{mso-level-tab-stop:2.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l2:level5
+{mso-level-tab-stop:2.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l2:level6
+{mso-level-tab-stop:3.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l2:level7
+{mso-level-tab-stop:3.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l2:level8
+{mso-level-tab-stop:4.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l2:level9
+{mso-level-tab-stop:4.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l3
+{mso-list-id:562446694;
+mso-list-template-ids:913898366;}
+@list l3:level1
+{mso-level-number-format:bullet;
+mso-level-text:\F0B7;
+mso-level-tab-stop:.5in;
+mso-level-number-position:left;
+text-indent:-.25in;
+mso-ansi-font-size:10.0pt;
+font-family:Symbol;}
+@list l3:level2
+{mso-level-tab-stop:1.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l3:level3
+{mso-level-tab-stop:1.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l3:level4
+{mso-level-tab-stop:2.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l3:level5
+{mso-level-tab-stop:2.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l3:level6
+{mso-level-tab-stop:3.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l3:level7
+{mso-level-tab-stop:3.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l3:level8
+{mso-level-tab-stop:4.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l3:level9
+{mso-level-tab-stop:4.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l4
+{mso-list-id:797802132;
+mso-list-template-ids:-1971191336;}
+@list l4:level1
+{mso-level-tab-stop:.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l4:level2
+{mso-level-tab-stop:1.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l4:level3
+{mso-level-tab-stop:1.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l4:level4
+{mso-level-tab-stop:2.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l4:level5
+{mso-level-tab-stop:2.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l4:level6
+{mso-level-tab-stop:3.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l4:level7
+{mso-level-tab-stop:3.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l4:level8
+{mso-level-tab-stop:4.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l4:level9
+{mso-level-tab-stop:4.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l5
+{mso-list-id:907304066;
+mso-list-template-ids:1969781532;}
+@list l5:level1
+{mso-level-tab-stop:.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l5:level2
+{mso-level-tab-stop:1.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l5:level3
+{mso-level-tab-stop:1.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l5:level4
+{mso-level-tab-stop:2.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l5:level5
+{mso-level-tab-stop:2.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l5:level6
+{mso-level-tab-stop:3.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l5:level7
+{mso-level-tab-stop:3.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l5:level8
+{mso-level-tab-stop:4.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l5:level9
+{mso-level-tab-stop:4.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l6
+{mso-list-id:1050613616;
+mso-list-template-ids:-1009886748;}
+@list l6:level1
+{mso-level-number-format:bullet;
+mso-level-text:\F0B7;
+mso-level-tab-stop:.5in;
+mso-level-number-position:left;
+text-indent:-.25in;
+mso-ansi-font-size:10.0pt;
+font-family:Symbol;}
+@list l6:level2
+{mso-level-number-format:bullet;
+mso-level-text:\F0B7;
+mso-level-tab-stop:1.0in;
+mso-level-number-position:left;
+text-indent:-.25in;
+mso-ansi-font-size:10.0pt;
+font-family:Symbol;}
+@list l6:level3
+{mso-level-tab-stop:1.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l6:level4
+{mso-level-tab-stop:2.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l6:level5
+{mso-level-tab-stop:2.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l6:level6
+{mso-level-tab-stop:3.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l6:level7
+{mso-level-tab-stop:3.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l6:level8
+{mso-level-tab-stop:4.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l6:level9
+{mso-level-tab-stop:4.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l7
+{mso-list-id:1234970193;
+mso-list-template-ids:2055904002;}
+@list l7:level1
+{mso-level-number-format:bullet;
+mso-level-text:\F0B7;
+mso-level-tab-stop:.5in;
+mso-level-number-position:left;
+text-indent:-.25in;
+mso-ansi-font-size:10.0pt;
+font-family:Symbol;}
+@list l7:level2
+{mso-level-number-format:bullet;
+mso-level-text:\F0B7;
+mso-level-tab-stop:1.0in;
+mso-level-number-position:left;
+text-indent:-.25in;
+mso-ansi-font-size:10.0pt;
+font-family:Symbol;}
+@list l7:level3
+{mso-level-tab-stop:1.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l7:level4
+{mso-level-tab-stop:2.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l7:level5
+{mso-level-tab-stop:2.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l7:level6
+{mso-level-tab-stop:3.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l7:level7
+{mso-level-tab-stop:3.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l7:level8
+{mso-level-tab-stop:4.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l7:level9
+{mso-level-tab-stop:4.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l8
+{mso-list-id:1846092290;
+mso-list-template-ids:-768590846;}
+@list l8:level1
+{mso-level-start-at:2;
+mso-level-tab-stop:.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l8:level2
+{mso-level-tab-stop:1.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l8:level3
+{mso-level-tab-stop:1.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l8:level4
+{mso-level-tab-stop:2.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l8:level5
+{mso-level-tab-stop:2.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l8:level6
+{mso-level-tab-stop:3.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l8:level7
+{mso-level-tab-stop:3.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l8:level8
+{mso-level-tab-stop:4.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l8:level9
+{mso-level-tab-stop:4.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l9
+{mso-list-id:1894656566;
+mso-list-template-ids:1199983812;}
+@list l9:level1
+{mso-level-start-at:2;
+mso-level-tab-stop:.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l9:level2
+{mso-level-tab-stop:1.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l9:level3
+{mso-level-tab-stop:1.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l9:level4
+{mso-level-tab-stop:2.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l9:level5
+{mso-level-tab-stop:2.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l9:level6
+{mso-level-tab-stop:3.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l9:level7
+{mso-level-tab-stop:3.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l9:level8
+{mso-level-tab-stop:4.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l9:level9
+{mso-level-tab-stop:4.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+ol
+{margin-bottom:0in;}
+ul
+{margin-bottom:0in;}
+-->
+</style><!--[if gte mso 10]> <style> /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-priority:99; mso-style-qformat:yes; mso-style-parent:""; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin:0in; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:10.0pt; font-family:"Times New Roman","serif";} </style> <![endif]--><!--[if gte mso 9]><xml> <o:shapedefaults v:ext="edit" spidmax="7170"/> </xml><![endif]--><!--[if gte mso 9]><xml> <o:shapelayout v:ext="edit"> <o:idmap v:ext="edit" data="1"/> </o:shapelayout></xml><![endif]-->
+<meta content="MCD Application Team" name="author"></head>
+<body style="" link="blue" vlink="blue">
+<div class="WordSection1">
+<p class="MsoNormal"><span style="font-family: "Arial","sans-serif";"><o:p> </o:p></span></p>
+<div align="center">
+<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
+<tbody>
+<tr style="">
+<td style="padding: 0in;" valign="top">
+<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
+<tbody>
+<tr style="">
+<td style="padding: 0in 5.4pt;" valign="top">
+<p class="MsoNormal"><span style="font-size: 8pt; font-family: "Arial","sans-serif"; color: blue;"><a href="../../Release_Notes.html">Back to Release page</a></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
+</td>
+</tr>
+<tr style="">
+<td style="padding: 1.5pt;">
+<h1 style="margin-bottom: 0.25in; text-align: center;" align="center"><span style="font-size: 20pt; font-family: "Verdana","sans-serif"; color: rgb(51, 102, 255);">Release
+Notes for STM32F3xx HAL Drivers</span><span style="font-size: 20pt; font-family: "Verdana","sans-serif";"><o:p></o:p></span></h1>
+<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: "Arial","sans-serif"; color: black;">Copyright
+2016 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
+<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: "Arial","sans-serif"; color: black;"><img id="_x0000_i1026" src="_htmresc/st_logo.png" border="0" height="65" width="86"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
+</td>
+</tr>
+</tbody>
+</table>
+<p class="MsoNormal"><span style="font-family: "Arial","sans-serif"; display: none;"><o:p> </o:p></span></p>
+<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">
+<tbody>
+<tr style="">
+<td style="padding: 0in;" valign="top">
+<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">Update History</span></h2>
+<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.5.2
+/ 12-June-2018</span></h3><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b><span style="font-size: 8pt; font-family: "Arial","sans-serif"; color: blue;"></span><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; color: black;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana;">Main changes</span></u></b></p><ul style="color: black;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">Maintenance release to fix known defects and
+enhancements implementation</span></span></li></ul><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; color: black;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana;">Generic drivers changes</span></u></b></p><ul style="margin-bottom: 0in; font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm; color: red;" type="square"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Some global variables on stm32xxx_hal.c updated to be declared as extern</span></li></ul><b style=""><span style="font-size: 10pt; font-family: Verdana;"> </span><u><span style="font-size: 10pt; font-family: Verdana;"></span></u></b><b style=""><u><span style="font-size: 10pt; font-family: Verdana;">HAL drivers changes</span></u></b><ul style="color: black;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">The following changes done on the HAL drivers require an update on the application code based on older HAL versions</span></span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black; font-weight: bold;"><span style="font-size: 10pt; font-family: Verdana;">Rework of HAL CAN driver (compatibility break) </span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana;">A
+new HAL CAN driver has been redesigned with new APIs, to bypass
+limitations on CAN Tx/Rx FIFO management present with previous HAL CAN
+driver version.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana;">The
+new HAL CAN driver is the recommended version. It is located as usual
+in Drivers/STM32F3xx_HAL_Driver/Src and
+Drivers/STM32F3xx_HAL_Driver/Inc folders. It can be enabled through
+switch HAL_CAN_MODULE_ENABLED in stm32f3xx_hal_conf.h</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana;">The
+legacy HAL CAN driver is also present in the release in
+Drivers/STM32F3xx_HAL_Driver/Src/Legacy and
+Drivers/STM32F3xx_HAL_Driver/Inc/Legacy folders for software
+compatibility reasons. Its usage is not recommended as
+deprecated. It can however be enabled through switch
+HAL_CAN_LEGACY_MODULE_ENABLED in stm32f3xx_hal_conf.h</span></li></ul></ul></ul><ul style="margin-bottom: 0in; font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm; color: red;" type="square"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">HAL </span>update</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add definiton of </span><span style="font-size: 10pt; font-family: Verdana;">HAL_CAN_LEGACY_MODULE_ENABLED swith in stm32f3xx_hal_conf_template.h</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">HAL CAN<span> </span></span>update</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Fields of CAN_InitTypeDef structure are reworked:</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana;">SJW
+to SyncJumpWidth, BS1 to TimeSeg1, BS2 to TimeSeg2, TTCM to
+TimeTriggeredMode, ABOM to AutoBusOff, AWUM to AutoWakeUp, NART to
+AutoRetransmission (inversed), RFLM to ReceiveFifoLocked and TXFP to
+TransmitFifoPriority</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_CAN_Init() is split into both HAL_CAN_Init() and HAL_CAN_Start() API's</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_CAN_Transmit()
+is replaced by HAL_CAN_AddTxMessage() to place Tx Request, then
+HAL_CAN_GetTxMailboxesFreeLevel() for polling until completion.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_CAN_Transmit_IT() is replaced by HAL_CAN_ActivateNotification() to enable transmit IT, then HAL_CAN_</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">AddTxMessage</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">() for place Tx request.</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US"></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_CAN_Receive() is replaced by HAL_CAN_GetRxFifoFillLevel() for polling until reception, then HAL_CAN_GetRxMessage()<span> </span><br>to get Rx message.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US"></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_CAN_Receive_IT() is replaced by HAL_CAN_</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">ActivateNotification</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">() </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">to enable receive IT, then HAL_CAN</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">_GetRxMessage()<br></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">in the receivecallback to get Rx message</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_CAN_Slepp() is renamed as HAL_CAN_RequestSleep()</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_CAN_TxCpltCallback() is split into HAL_CAN_TxMailbox0CompleteCallback(),<span> </span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_CAN_TxMailbox1CompleteCallback() and </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_CAN_TxMailbox2CompleteCallback().</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_CAN_RxCpltCallback is split into HAL_CAN_RxFifo0MsgPendingCallback() and<span> </span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_CAN_RxFifo1MsgPendingCallback().</span></li></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">More complete "How to use the new driver" is detailed in the driver header section itself.</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US"><span style="font-weight: bold;">HAL COMP</span> update</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Fix wrong configuration of Comparator 4 inverting input for stm32f301x8 device</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US"><span style="font-weight: bold;">HAL DMA </span>update</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Add clean of callbacks in HAL_DMA_DeInit() API</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US"><span style="font-weight: bold;">HAL HRTIM</span> update</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Add more flexibility on GetTimerIdxFromDMAHandle() static function</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US"><span style="font-weight: bold;">HAL RCC</span> update</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">Update HAL_RCC_ClockConfig() API to:</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">check on null pointer</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">optimize code size by updating the handling method of the SWS bits</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">update
+to use __HAL_FLASH_GET_LATENCY() flash macro instead of using
+direct register access to LATENCY bits in FLASH ACR register.</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;" lang="EN-US">Update HAL_RCC_DeInit() API to</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;" lang="EN-US">Be able to return HAL</span></li></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;" lang="EN-US">Add checks for HSI and PLL ready before modifying RCC CFGR registers</span></li></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;" lang="EN-US">Clear all interrupt falgs</span></li></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: "Courier New"; color: black;" lang="EN-US"><span><span style="font-family: "Times New Roman"; font-style: normal; font-variant: normal; font-weight: normal; font-size: 7pt; line-height: normal; font-stretch: normal;"></span></span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;" lang="EN-US">Initialize systick interrupt period</span></li></ul></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US"><span style="font-weight: bold;">HAL RTC</span> update</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Fix warning with static analysis: remove unused variables</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">HAL TIM<span> </span></span>update</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update HAL_TIMEx_OCN_xxxx() and HAL_TIMEx_PWMN_xxx() API description to remove support of TIM_CHANNEL_4</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add
+a note in functions header to perform timer reset when switching
+from Aligned counter mode to Edge counter mode (or reverse)</span></li></ul></ul><b style=""><u><span style="font-size: 10pt; font-family: Verdana;"></span></u></b><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; color: black;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana;">LL Drivers changes</span></u></b></p><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL TIM</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span></li><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add
+a note in macros header to perform timer reset when switching from
+Aligned counter mode to Edge counter mode (or reverse)</span></li></ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL UTILS</span></span></li><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Remove the</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"> set of SysTick_CTRL_TICKINT bit in SysTick->CTRL from </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">LL_InitTick()</span></li></ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL RCC</span></span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;" lang="EN-US">Update LL_RCC_DeInit() API to</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;" lang="EN-US">Be able to return LL status</span></li></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;" lang="EN-US">Add checks for HSI and PLL ready before modifying RCC CFGR registers</span></li></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;" lang="EN-US">Clear all interrupt falgs</span></li></ul></ul></ul><b style=""><u><span style="font-size: 10pt; font-family: Verdana;"></span></u></b><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.5.1
+/ 11-May-2018</span></h3><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b><span style="font-size: 8pt; font-family: "Arial","sans-serif"; color: blue;"></span><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; color: black;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana;">Main changes</span></u></b></p><ul style="color: black;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">General updates to fix known defects and enhancements implementation</span></li></ul><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; color: black;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana;">HAL Drivers changes</span></u></b></p><ul style="margin-bottom: 0in; font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm; color: red;" type="square"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">HAL </span>update</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update HAL driver to allow user to change systick period to 1ms, 10 ms or 100 ms :</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add the following API's : </span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_GetTickPrio(): Returns a tick priority.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_SetTickFreq(): Sets new tick </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">frequency.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_GetTickFreq(): Returns tick frequency.</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add HAL_TickFreqTypeDef enumeration for the different Tick Frequencies: 10 Hz, 100 Hz and 1KHz (default).</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update UNUSED() macro implementation to avoid GCC warning</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">The warning is detected when the UNUSED() macro is called from C++ file</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update __weak and __packed defined values for ARM compiler</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update __ALIGN_BEGIN and __ALIGN_END defined values for ARM compiler</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><b><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL I2C<span> </span></span></b><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">update</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">Update Interface APIs headers to remove confusing message about device address</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">Update<span> </span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">I2C_WaitOnRXNEFlagUntilTimeout() to resolve a race condition between STOPF and RXNE Flags</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">Update I2C_TransferConfig() to fix wrong bit management</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><b><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL SMBUS<span> </span></span></b><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">update</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">Update conditions on HAL SMBUS slave transfer APIs to avoid block on read or write operations</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">HAL FLASH<span> </span></span>update</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_FLASH_Unlock() update to return state error when the FLASH is already unlocked</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">HAL PCD<span> </span></span>update</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update
+redefinition of registers with adjusted address by adding volatile
+keyword to avoid unexpected change of Memory-mapped peripheral registers</span></li></ul></ul><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; color: black;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana;">LL Drivers changes</span></u></b></p><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL ADC</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span></li><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update
+redefinition of registers with adjusted address by adding volatile
+keyword to avoid unexpected change of Memory-mapped peripheral registers</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL DAC</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span></li><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update
+redefinition of registers with adjusted address by adding volatile
+keyword to avoid unexpected change of Memory-mapped peripheral registers</span></li></ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black; font-weight: bold;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">LL HRTIM</span></li><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; display: inline ! important; float: none;"></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update
+redefinition of registers with adjusted address by adding volatile
+keyword to avoid unexpected change of Memory-mapped peripheral registers</span></li></ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">LL I2C</span> </span></li><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update LL_I2C_HandleTransfer() to fix wrong bit management</span></li></ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black; font-weight: bold;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">LL RCC</span></li><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; display: inline ! important; float: none;">Fix wrong defined value of LSI</span></li></ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black; font-weight: bold;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">LL RTC</span></li><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; display: inline ! important; float: none;">LL RTC macros optimization:</span></li><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; display: inline ! important; float: none;">LL_RTC_TIME_GetHour()</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; display: inline ! important; float: none;">LL_RTC_TIME_GetMinute()</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; display: inline ! important; float: none;">LL_RTC_TIME_GetSecond()</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; display: inline ! important; float: none;">LL_RTC_DATE_GetYear()</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; display: inline ! important; float: none;">LL_RTC_DATE_GetMonth()</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; display: inline ! important; float: none;">LL_RTC_DATE_GetDay()</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; display: inline ! important; float: none;">LL_RTC_ALMA_GetDay()</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; display: inline ! important; float: none;">LL_RTC_ALMA_GetHour()</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; display: inline ! important; float: none;">LL_RTC_ALMA_GetMinute()</span></li></ul><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; display: inline ! important; float: none;">LL_RTC_ALMA_GetSecond()</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; display: inline ! important; float: none;">LL_RTC_ALMB_GetDay()</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; display: inline ! important; float: none;">LL_RTC_ALMB_GetHour()</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; display: inline ! important; float: none;">LL_RTC_ALMB_GetMinute()</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; display: inline ! important; float: none;">LL_RTC_ALMB_GetSecond()</span></li></ul></ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black; font-weight: bold;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">LL SPI</span></li><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; display: inline ! important; float: none;">Update LL_SPI_TransmitData8() and LL_SPI_TransmitData16() to fix compilation issues with GCC</span></li></ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black; font-weight: bold;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">LL TIM</span></li><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; display: inline ! important; float: none;"></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update
+redefinition of registers with adjusted address by adding volatile
+keyword to avoid unexpected change of Memory-mapped peripheral registers</span></li></ul><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Fix behavior of LL_TIM_IsEnabledUpdateEvent() </span></li></ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black; font-weight: bold;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">LL UTILS</span></li><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; display: inline ! important; float: none;"></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update LL_InitTick() to set SysTick_CTRL_TICKINT bit in SysTick->CTRL </span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.5.0
+/ 23-June-2017</span></h3><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b><span style="font-size: 8pt; font-family: "Arial","sans-serif"; color: blue;"></span><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; color: black;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana;">Main changes</span></u></b></p><ul style="color: black;"><li><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">Maintenance release to fix known defects and
+enhancements implementation<span style="text-decoration: underline;"></span></span></span></li></ul><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; color: black;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana;"></span></u></b></p><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; color: black;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana;">Generic drivers changes</span></u></b></p><ul style="margin-bottom: 0in; font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm; color: red;" type="square"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: Verdana; font-size: 10pt;">MISRA C 2004 rule 11.4 (A cast should not be performed between a pointer to object type and a different pointer to object type).</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: Verdana; font-size: 10pt;">MISRA C 2004 rule 12.4 (The right-hand operand of a logical or I I operator shall not <br>contain side effects).</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: Verdana; font-size: 10pt;">MISRA C 2004 rule 17.4 (Array indexing shall be the only allowed form of pointer arithmetic).</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: "Verdana",sans-serif; font-size: 10pt;">Remove uselesss cast (uint32_t ) cast in case of 'U' suffix.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: "Verdana",sans-serif; font-size: 10pt;">Fix Code Sonar warnings (useless assignment, cast alters value, empty while statement ...).</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: Verdana,sans-serif; font-style: normal; font-variant: normal; font-weight: normal; font-size: 13.33px; line-height: normal; font-size-adjust: none; font-stretch: normal; text-align: left; text-transform: none; text-indent: 0px; letter-spacing: normal; word-spacing: 0px; float: none; display: inline ! important; white-space: normal; widows: 1;">Minor </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">improvement of
+ Doxygen Tags for CHM UM generation</span><span style="font-family: Verdana,sans-serif; font-style: normal; font-variant: normal; font-weight: normal; font-size: 13.33px; line-height: normal; font-size-adjust: none; font-stretch: normal; text-align: left; text-transform: none; text-indent: 0px; letter-spacing: normal; word-spacing: 0px; float: none; display: inline ! important; white-space: normal; widows: 1;">.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Replace POSITION_VAL(xxx) macro by corresponding CMSIS_Pos definitions.</span></li></ul><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; color: red;"></p><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; color: black;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana;">HAL Drivers changes</span></u></b></p><ul style="margin-bottom: 0in; font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm; color: black;" type="square"><li style="margin-top: 4.5pt; margin-bottom: 4.5pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana",sans-serif; font-weight: bold;">The following changes done on the HAL drivers require an update on the application code based on HAL V1.4.0</span></li></ul><ul style="margin-bottom: 0in; font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm; color: red;" type="square"><ul style="color: black;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US"><span style="font-style: italic;">HAL NAND </span>driver:<span class="Apple-converted-space"> </span>Overall driver rework with compatibility break versus previous HAL version (see below).</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;"></span></span><br><br></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL</span></span></li><ul style="color: black;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: Verdana,sans-serif; font-style: normal; font-variant: normal; font-weight: normal; font-size: 13.33px; line-height: normal; font-size-adjust: none; font-stretch: normal; text-align: left; text-transform: none; text-indent: 0px; letter-spacing: normal; word-spacing: 0px; float: none; display: inline ! important; white-space: normal; widows: 1;">Correct RTC_PREDIV values (for LSI clock) in hal_timebase_rtc_alam_template.c and </span><span style="font-family: Verdana,sans-serif; font-style: normal; font-variant: normal; font-weight: normal; font-size: 13.33px; line-height: normal; font-size-adjust: none; font-stretch: normal; text-align: left; text-transform: none; text-indent: 0px; letter-spacing: normal; word-spacing: 0px; float: none; display: inline ! important; white-space: normal; widows: 1;">hal_timebase_rtc_wakeup_template.c</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: Verdana,sans-serif; font-style: normal; font-variant: normal; font-weight: normal; font-size: 13.33px; line-height: normal; font-size-adjust: none; font-stretch: normal; text-align: left; text-transform: none; text-indent: 0px; letter-spacing: normal; word-spacing: 0px; float: none; display: inline ! important; white-space: normal; widows: 1;">Add definition of USE_SPI_CRC in hal_conf_template.h</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-style: normal; font-variant: normal; font-weight: normal; font-size: 13.33px; line-height: normal; font-size-adjust: none; font-stretch: normal; text-align: left; color: rgb(0, 0, 0); text-transform: none; text-indent: 0px; letter-spacing: normal; word-spacing: 0px; float: none; display: inline ! important; white-space: normal; widows: 1;">Modify HAL_Delay() function to garantee minimum delay.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">New API : HAL_GetUIDwx() read the unique device identifier word x.</span></li></ul></ul><ul style="margin-bottom: 0in; font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm; color: red;" type="square"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL ADC</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span></li><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Remove unused litteral ADC_EOC_SINGLE_SEQ_CONV.</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Correct name of one ADC external trigger of regular group : ADC_EXTERNALTRIGCONV_T4_CC4.</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL CAN</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-family: "Times New Roman",serif; font-size: 12pt; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add transmission abort when timeout is reached in HAL_CAN_Transmit().</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-family: "Times New Roman",serif; font-size: 12pt; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add managment of overrun error. </span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-family: "Times New Roman",serif; font-size: 12pt; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Store missing FIFO number in received message.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-family: "Times New Roman",serif; font-size: 12pt; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Extend SET_BIT, CLEAR_BIT macro usage.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-family: "Times New Roman",serif; font-size: 12pt; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Allow possibility to receive messages from the 2 RX FIFOs in parallel via interrupt.</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Fix message lost issue with specific sequence of transmit requests.</span><span style="font-size: 10pt; font-family: Verdana;"></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL COMP</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-family: "Times New Roman",serif; font-size: 12pt; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">COMP_WINDOWMODE litterals clean-up according to family diversity.</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL NAND</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-family: "Times New Roman",serif; font-size: 12pt; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Overall driver rework in order to support NAND flash memories with higher capacities. </span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-family: "Times New Roman",serif; font-size: 12pt; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add support of 16 bits adressing mode<br></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-family: "Times New Roman",serif; font-size: 12pt; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">API changes :</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-family: "Times New Roman",serif; font-size: 12pt; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add HAL_NAND_ConfigDevice() function</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-family: "Times New Roman",serif; font-size: 12pt; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Split HAL_NAND_Read_Page(),
+HAL_NAND_Write_Page(), HAL_NAND_Read_SpareArea(),
+HAL_NAND_Write_SpareArea() in _8b and _ 16b functions to select
+the proper adressing mode.</span></li></ul></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL HRTIM</span></span></li></ul><ul style="margin-bottom: 0in; font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm; color: red;" type="square"><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Modify __HAL_HRTIM_SETCLOCKPRESCALER macro to clear CKPSC and CKPSCx bits before setting new prescaler value.</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Correct HRTIM_EVENTFASTMODE_DISABLE and HRTIM_EVENTFASTMODE_ENABLE defines.</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL I2C</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Editorial modification : astyle clean-up</span></li></ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL SMBUS</span></span><span style="font-family: Verdana; font-size: 10pt;"></span></li><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="font-family: Verdana; font-size: 10pt;">New API : Digital/Analog filter configuration with HAL_SMBUS_ConfigAnalogFilter() and HAL_SMBUS_ConfigDigitalFilter().</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif; font-weight: bold;" lang="EN-US">HAL
+ PCD </span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Fix and Improve PCD_ReadPMA() API to prevent corrupting user buffer.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Minor changes in HAL_PCD_CLEAR_FLAG, PCD_CLEAR_TX/RX_EP_CTR macros</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Fix USB device remote wakeup issue.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">USB PCD interrupt handler: remove useless usb device interrupts enable, already set during the pcd init.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Remove lock/unlock from USB receive and transmit endpoints.</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL RTC</span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul style="color: black;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Correct RTC Time register initialization.</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif; font-weight: bold;" lang="EN-US">HAL SPI </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span></li><ul style="color: black;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Empty RXFIFO in case of end of MASTER transmission 2 lines.</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif; font-weight: bold;" lang="EN-US">HAL I2S </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span></li><ul style="color: black;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Fix full duplex I2S with circular DMA issues :</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Don't stop DMA at end of transfert</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Solve synchroniszation issues between RX and TX.<br></span></li></ul></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif; font-weight: bold;" lang="EN-US">HAL TIM</span></li><ul style="color: black;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif; font-weight: bold;" lang="EN-US"></span><span style="font-size: 10pt; font-family: Verdana;">Fix typo in __HAL_TIM_SET_PRESCALER macro.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Improvment of TIM DMA burst mode. Add 2 new API :</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">HAL_TIM_DMABurst_MultiWriteStart()</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">HAL_TIM_DMABurst_MultiReadStart()</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add BRK2 (Break input 2 event) interrupt handler.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update IRQ handler to use correct defines (TIM_FLAG_xxxx instead of TIM_IT_xxxx)</span><span style="font-size: 10pt; font-family: Verdana;"> to clear flag.<br></span></li></ul></ul>
+<span style="font-size: 10pt; font-family: Verdana; color: red;"></span><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; color: red;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana;"></span></u></b></p><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; color: black;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana;">LL Drivers changes</span></u></b></p><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL ADC</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span></li><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Set TEMPSENSOR_CAL1_TEMP value to 30°C as specified in datasheet.</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL DMA</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span></li><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Replace SET_BIT macro by WRITE_REG in LL_DMA_ClearFlag_xxx() as DMA IFCR register is read only.</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">For better performances, CPAR and CMAR regsiters are updated by WRITE_REG macro instead of MODIFY_REG.</span></li></ul></ul><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">LL I2C</span></span><span style="font-family: Verdana; font-size: 10pt;"></span></li><ul style="color: black;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">OA1EN bit of OAR1 register should be set only when own address different from 0 (0 reserved for General Call address).</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL RTC</span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul style="color: black;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update LL_RTC_DATE_Get() function for better performances.</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL SPI</span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul style="color: red;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Remove LL_SPI_SR_UDR (available only for I2S feature).</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL_TIM</span></span></li><ul style="color: red;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Add AutomaticOutput field initialization in LL_TIM_BDTR_StructInit().</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Fix typo in __HAL_TIM_SET_PRESCALER macro.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Ensure
+write operation of BKE and BKP bits is effective by adding fake read
+operation to garantee 1 APB clock cycle before function exit.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Exchange behavior between LL_TIM_EnableUpdateEvent() and LL_TIM_DisableUpdateEvent().<br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL UTILS</span></span></li><ul style="color: black;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update function UTILS_EnablePLLAndSwitchSystem() to use current AHB prescaler for sysclk frequency calculation.</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.4.0
+/ 16-December-2016</span></h3><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b><span style="font-size: 8pt; font-family: "Arial","sans-serif"; color: blue;"></span><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main changes</span></u></b>
+</p><ul><li><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">Maintenance release to fix known defects and
+enhancements implementation</span></span></li></ul><span style="font-size: 8pt; font-family: "Arial","sans-serif"; color: blue;"></span><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL Drivers changes</span></u></b></p><ul style="color: black;"><li style="margin-top: 4.5pt; margin-bottom: 4.5pt;" class="MsoNormal">
+
+<span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Enhance HAL delay and time base implementation</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">:</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;"></span></span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add
+new templates
+stm32f0xx_hal_timebase_rtc_alarm_template.c, stm32f0xx_hal_timebase_rtc_wakeup_template.c
+and stm32f0xx_hal_timebase_tim_template.c which can be used to override
+the native
+HAL time base functions (defined as weak) to use either RTC or
+Timer as time
+base tick source. For more details about the usage of these drivers,
+please refer to HAL\HAL_TimeBase examples </span><span style="font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;">and FreeRTOS-based applications</span></li></ul></ul><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black; font-weight: bold;">The following changes done on the HAL drivers require an update on the application code based on HAL V1.3.0</span></li></ul><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US"><span style="font-style: italic;">HAL CEC </span>driver:<span class="Apple-converted-space"> </span> Overall driver rework with compatibility break versus previous HAL version</span><br><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Remove HAL CEC polling Process functions: HAL_CEC_Transmit() and HAL_CEC_Receive()</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US"></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Remove
+HAL CEC receive interrupt process function HAL_CEC_Receive_IT()
+and enable the "receive" mode during the Init phase</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Rename HAL_CEC_GetReceivedFrameSize() funtion to HAL_CEC_GetLastReceivedFrameSize()<br></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Add new HAL APIs: HAL_CEC_SetDeviceAddress() and HAL_CEC_ChangeRxBuffer()</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Remove the <span></span>'InitiatorAddress'
+field from the CEC_InitTypeDef structure and manage
+it as a parameter in the HAL_CEC_Transmit_IT() function</span><span style="font-family: 'Times New Roman',serif; font-size: 12pt;" lang="EN-US"><o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Add new parameter 'RxFrameSize' in HAL_CEC_RxCpltCallback() function</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Move CEC Rx buffer pointer from CEC_HandleTypeDef structure to CEC_InitTypeDef structure</span></li></ul></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana; color: black;"><span style="font-style: italic;">HAL TIM driver </span>: add one field (AutoReloadPreload) in TIM_Base_InitTypeDef structure</span><br><br></li></ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL Generic</span></span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Update HAL Driver compliancy with:</span></li><ul style="color: black;"><li><span style="font-size: 10pt; font-family: Verdana;">MISRA C 2004 rule 10.6 ('U' suffix applied to all constants of 'unsigned' type)</span></li></ul></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL CEC</span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span></li><ul style="color: black;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Overall driver rework with break of compatibility with HAL V1.3.0<br></span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Remove the HAL CEC polling Process: HAL_CEC_Transmit() and HAL_CEC_Receive()</span><span style="font-family: 'Times New Roman',serif; font-size: 12pt;" lang="EN-US"><o:p></o:p></span></li></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Remove the HAL CEC receive interrupt process (HAL_CEC_Receive_IT()) and manage the "Receive" mode enable within the Init phase</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Rename HAL_CEC_GetReceivedFrameSize() function to HAL_CEC_GetLastReceivedFrameSize() function<br></span></li></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Add new HAL APIs: HAL_CEC_SetDeviceAddress() and HAL_CEC_ChangeRxBuffer()</span></li></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Remove the <span></span>'InitiatorAddress'
+field from the CEC_InitTypeDef structure and manage
+it as a parameter in the HAL_CEC_Transmit_IT() function</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US"></span></li></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Add new parameter 'RxFrameSize' in HAL_CEC_RxCpltCallback() function</span><span style="font-family: 'Times New Roman',serif; font-size: 12pt;" lang="EN-US"><o:p></o:p></span></li></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Move CEC Rx buffer pointer from CEC_HandleTypeDef structure to CEC_InitTypeDef structure</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US"><o:p></o:p></span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update driver to implement the new CEC state machine:</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add new </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">"rxState"</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span class="Apple-converted-space"> </span>field in CEC_HandleTypeDef structure to provide the<span class="Apple-converted-space"> </span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">CEC<span class="Apple-converted-space"> </span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">state information related to Rx Operations</span></li></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Rename "state" field in CEC_HandleTypeDef structure to "gstate": CEC<span class="Apple-converted-space"> </span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">state information related to global Handle management and Tx Operations</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update CEC process to manage the new CEC states.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Update __HAL_CEC_RESET_HANDLE_STATE() macro to handle the new CEC state parameters (gState, rxState)</span></li></ul></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL </span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">UART/USART</span></span><span style="font-size: 10pt; font-family: Verdana;">/</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">IRDA/SMARTCARD</span></span></li><ul style="color: black;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="FR">IRQ Handler global optimization </span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="FR">New abort API: HAL_PPP_Abort(), HAL_PPP_Abort_IT()<br></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Add error management in case of DMA transfer through
+ </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL_DMA_Abort_IT() and DMA </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">XferAbortCallback()</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="FR"></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="FR">Polling management update:</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">The user Timeout value must be estimated for the overall process
+duration</span></li></ul></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><b><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL SPI</span></b><b><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US"><span class="Apple-converted-space"></span></span></b><span style="font-size: 10pt; font-family: Verdana,sans-serif;"></span></li><ul style="margin-bottom: 0in; color: black;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Overall driver optimization to improve performance in polling/interrupt mode to reach maximum peripheral frequency</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Polling mode:</span></li><ul style="margin-bottom: 0in;"><li><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Replace the use of SPI_WaitOnFlagUnitTimeout() function by "if" statement to check on RXNE/TXE flage while transferring data</span></li></ul></ul></ul><ul style="margin-bottom: 0in; color: black;"><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"> Interrupt mode:</span></li><ul style="margin-bottom: 0in;"><li><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Minimize access on SPI registers</span></li></ul></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">All modes:</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add the USE_SPI_CRC switch to minimize the number of statements when CRC calculation is disabled</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update timeout management to check on global processes</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update error code management in all processes</span></li></ul></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Fix regression in polling mode:<o:p></o:p></span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Add preparing data to transmit in case of slave mode in HAL_SPI_TransmitReceive() and HAL_SPI_Transmit()<o:p></o:p></span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Fix regression in interrupt mode:<o:p></o:p></span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Add a wait on TXE flag in SPI_CloseTx_ISR() and in SPI_CloseTxRx_ISR()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Add to manage properly the overrun flag in SPI_CloseRxTx_ISR() and SPI_CloseRx_ISR()</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Prevent data packing mode
+in reception for </span><span style="font-size: 10pt; font-family: "Arial",sans-serif;" lang="EN-US">STM32F302xC, STM32F303xC, STM32F373xC, STM32F358xx, STM32F378xx</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-size: 10pt; font-family: "Arial",sans-serif;" lang="EN-US">Add check of DMA handle definition before calling HAL_SPI_Receive_DMA, HAL_SPI_Transmit_DMA, HAL_SPI_TransmitReceive_DMA</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated HAL Driver compliancy with </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">MISRA C 2004 rules</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">:</span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">MISRA C 2004 rule 14.3 </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">(a null statement shall only occur on a line by itself).</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">MISRA C 2004 rule 14.8 </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">(statement forming the body of a switch, while, do Â… while or for statement shall be a compound statement).</span></li></ul></ul></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL DMA</span></b></li><ul style="color: black;"><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Global
+ driver code optimization to reduce memory footprint </span></li><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add
+ new APIs HAL_DMA_RegisterCallback() and HAL_DMA_UnRegisterCallback to
+ register/unregister the different callbacks identified by the enum
+ typedef HAL_DMA_CallbackIDTypeDef</span></li><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add
+ new Error Code HAL_DMA_ERROR_NOT_SUPPORTED</span></li><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Remove
+ DMA HAL_DMA_STATE_READY_HALF & HAL_DMA_STATE_ERROR states in
+ HAL_DMA_StateTypeDef</span></li></ul></ul><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HA<span style="color: black;">L I2C</span></span></span><span style="font-size: 10pt; font-family: Verdana; color: rgb(51, 102, 255);"><span style="font-weight: bold;"></span></span></li><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Disable I2C_OARx_EN bit before any configuration in OAR1 or 2 in HAL_I2C_Init()</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Move I2C_NO_OPTION_FRAME in private section</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: rgb(51, 102, 255);" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;"><span style="color: black;">Update IS_I2C_FASTMODEPLUS macro. Add I2C_FMP_NOT_SUPPORTED definition</span><br></span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Update HAL_I2C_Master_Sequential_Transmit_IT() function (wrong state check)</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Add I2C_FIRST_AND_NEXT_FRAME option for I2C Sequential Transfer</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">On slave, reset LISTEN_TX state in case of direction change</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;"><span style="color: black;">Remove GCC warnings</span><br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL TIM</span></span></li></ul><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">API update : add one field (AutoReloadPreload) in TIM_Base_InitTypeDef structure in order to set ARPE
+bit from TIMx_CR1 register</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">New
+API : add 2 macros (__HAL_TIM_ENABLE_OCxPRELOAD() and
+__HAL_TIM_DISABLE_OCxPRELOAD()) in order to set OCxPE bit
+from TIMx_CCMR1, TIMx_CCMR2 and TIMx_CCMR3 registers</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Use MODIFY_REG macro to avoid wrong initialisation in ConfigBreakDeadTime()</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Add TIM1 ETR remap enums for STM32F334xx devices</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">HAL_TIMEx_RemapConfig() prototype changed for STM32F334x8 device<br></span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana; color: black;">Remove
+TIM_CR2_OIS2N, TIM_CR2_OIS3, TIM_CR2_OIS3N, TIM_CR2_OIS4 managment for STM32F373xC and STM32F378xx devices</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-family: Verdana; font-size: 10pt;">API update : Add __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY() function to disable MOE bit without condition</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL SMBUS</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Remove useless XferSize field initialisation in HAL_SMBUS_Slave_Transmit_IT()</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="font-family: "Verdana",sans-serif; font-size: 10pt;">Add
+support of Zone read/write feature thanks to new XferOptions parameter
+values SMBUS_OTHER_FRAME_NO_PEC, SMBUS_OTHER_FRAME_WITH_PEC,
+SMBUS_OTHER_AND_LAST_FRAME_NO_PEC and
+SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif; font-weight: bold;" lang="EN-US">HAL
+ PCD </span></li><ul style="color: red;"><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated HAL Driver compliancy with </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">MISRA C 2004 rules : (10.3, 105) </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">MISRA C 2004 rule 10.3 (illegal explicit conversion from underlying MISRA type "unsigned int" to "uint32_t *").</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">MISRA C 2004 rule 10.5 (bitwise operators ~ and <<).</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">MISRA C 2004 rule 12.7 (bitwise operations not performed on signed integer types).</span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL PWR</span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul style="color: black;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Rename PWR_CR register defines to be aligned with </span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">STM32F3xx Reference Manual </span><span style="font-size: 10pt; font-family: Verdana;">: SDADCxEN ==> ENSDx</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL RCC</span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul style="color: black;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Rename RCC_CFGR register defines </span><span style="font-size: 10pt; font-family: Verdana;">to be aligned with </span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">STM32F3xx Reference Manual </span><span style="font-size: 10pt; font-family: Verdana;">: SDADCPRE ==> SDPRE</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif; font-weight: bold;" lang="EN-US">HAL CORTEX </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span></li><ul style="color: black;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update HAL_MPU_Disable() to clear the whole control register. Also remove STATIC INLINE and move function to c file</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif; font-weight: bold;" lang="EN-US">HAL CAN </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span></li><ul style="color: black;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add __HAL_UNLOCK() call when all mailboxes are busy</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add __HAL_CAN_CANCEL_TRANSMIT() call to abort transmission when timeout is reached<br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif; font-weight: bold;" lang="EN-US">HAL ADC </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span></li><ul style="color: black;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add ADC_EXTERNALTRIGINJECCONV_T2_CC1 and ADC_EXTERNALTRIGINJECCONV_T2_TRGO definitions</span></li></ul></ul>
+<span style="font-size: 10pt; font-family: Verdana;"></span><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">LL Drivers changes</span></u></b></p><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL COMP</span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul style="color: rgb(51, 102, 255);"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Creation of generic defines for defines specific to COMP instances</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Modify definition of LL_COMP_OUTPUT_TIM4_IC2_COMP4, LL_COMP_OUTPUT_TIM4_IC3_COMP5 and LL_COMP_OUTPUT_TIM4_IC4_COMP6 literals</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="color: black;">Rename
+LL_COMP_OUTPUT_TIM1_IC4_COMP2 and LL_COMP_OUTPUT_TIM1_IC4_COMP1_2 in
+LL_COMP_OUTPUT_TIM2_IC4_COMP2 and LL_COMP_OUTPUT_TIM2_IC4_COMP1_2</span></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="color: black;"></span></span><span style="font-family: Verdana; font-size: 10pt; color: black;">Correct COMP inputs definition</span><span style="font-size: 10pt; font-family: Verdana;"><span style="color: black;"></span><br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL EXTI</span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul style="color: rgb(51, 102, 255);"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana; color: black;">Move
+LL_EXTI_LINE_18, LL_EXTI_LINE_33, LL_EXTI_LINE_34, LL_EXTI_LINE_35,
+LL_EXTI_LINE_36, LL_EXTI_LINE_37, LL_EXTI_LINE_38 and LL_EXTI_LINE_39
+defines under compilation switch (</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;">availability depends on devices)</span><span style="font-size: 10pt; font-family: Verdana;"></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL PWR</span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul style="color: black;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Rename PWR_CR register defines to be aligned with </span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">STM32F3xx Reference Manual </span><span style="font-size: 10pt; font-family: Verdana;">: SDADCxEN ==> ENSDx</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL RCC</span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul style="color: black;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Rename RCC_CFGR register defines </span><span style="font-size: 10pt; font-family: Verdana;">to be aligned with </span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">STM32F3xx Reference Manual</span><span style="font-size: 10pt; font-family: Verdana;"> : SDADCPRE ==> SDPRE</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL SYSTEM</span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul style="color: rgb(51, 102, 255);"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Add LL_SYSCFG_EnableIT_FPU_xxx functions</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="color: black;">Replace
+LL_SYSCFG_TIM18_RMP_DMA2_CH4 and LL_SYSCFG_TIM18_RMP_DMA1_CH4 by
+LL_SYSCFG_TIM18_RMP_DMA2_CH5 and LL_SYSCFG_TIM18_RMP_DMA1_CH5</span><br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL GPIO</span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul style="color: black;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Remove LL_GPIO_SPEED_FREQ_VERY_HIGH (GPIO_SPEED_FREQ_VERY_HIGH does not exist for STM32F3xx serie)</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL_TIM</span></span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Rename
+LL_TIM_TIM16_TI1_RMP defines : LL_TIM_TIM16_TI1_RMP_GPIO,
+LL_TIM_TIM16_TI1_RMP_RTC, LL_TIM_TIM16_TI1_RMP_HSE_32,
+LL_TIM_TIM16_TI1_RMP_MCO</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana; color: black;">Remove
+TIM_CR2_OIS2N, TIM_CR2_OIS3, TIM_CR2_OIS3N, TIM_CR2_OIS4 managment for STM32F373xC and STM32F378xx devices</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: rgb(51, 102, 255);"></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana; color: black;">Move
+LL_TIM_OCREF_CLR_INT_OCREF_CLR and LL_TIM_OCREF_CLR_INT_ETR
+defines under compilation switch (</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;">availability depends on devices)</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: Verdana; font-size: 10pt;">New APIs to insure BDTR register initialization in a single write operation </span></li><ul style="color: black;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">LL_TIM_BDTR_StructInit()</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">LL_TIM_BDTR_Init()</span></li></ul></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL USART</span></span></li><ul style="color: black;"><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Replace POSITION_VAL(xxx) macro by corresponding CMSIS_Pos definitions</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL HRTIM</span></span></li><ul style="color: black;"><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Replace POSITION_VAL(xxx) macro by corresponding CMSIS_Pos definitions</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt;" class="MsoNormal"><span style="font-family: Verdana; font-size: 10pt;">Add shift operation in HRTIM_TIM_SetCompareMode()</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL_I2C</span></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Replace POSITION_VAL(xxx) macro by corresponding CMSIS_Pos definitions</span></li></ul></ul><br><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.3.0
+/ 01-July-2016</span></h3>
+<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes</span></u></b></p><ul style="margin-top: 0cm; list-style-type: square;"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">First official release supporting the Low Level drivers for the STM32F3xx serie:</span></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Low Layer drivers APIs provide register level programming:</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US"></span><br><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">they require deep knowledge of peripherals described in STM32F3xx Reference Manual.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Low Layer drivers are available for</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US"> ADC, COMP, Cortex, CRC, DAC, DMA, EXTI, GPIO, HRTIM, I2C, IWDG, OPAMP, PWR,<br>RCC, RTC, SPI, TIM, USART and WWDG peripherals</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"> and additional Low Level Bus, System and Utilities APIs.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Low
+Layer drivers APIs are implemented as static inline function in new
+Inc/stm32f3xx_ll_ppp.h files for PPP peripherals, there is no
+configuration file and each stm32f3xx_ll_ppp.h file must be included in
+user code.</span></li></ul></ul><ul style="margin-top: 0cm; list-style-type: square;"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">Maintenance release to fix known defects and enhancements implementation.<br></span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL generic</span></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated.</span></li></ul></ul><ul style="margin-top: 0cm; list-style-type: square;"><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal; font-weight: bold;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL ADC</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Updated
+assert_param within HAL_ADCEx_MultiModeConfigChannel() function to
+avoid issue during ADC configuration change from multimode to
+independent mode.</span></li></ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal; font-weight: bold;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL CRC</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Updated HAL_CRC_DeInit() function (restored IDR Register to Reset value).</span></li></ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal; font-weight: bold;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL GPIO</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">definition of </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">IS_GPIO_PIN private macro to cover full u32 bits</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">.</span></li></ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal; font-weight: bold;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL HRTIM</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated HAL HRTIM Driver compliancy with </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">MISRA C 2004 rules</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">:</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"></span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">MISRA C 2004 rule 12.5 </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">(operands of a logical && or || shall be primary-expressions).</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">MISRA C 2004 rule 15.3 </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">(final clause of a switch statement shall be the default clause).</span></li></ul></ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal; font-weight: bold;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL I2C</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated I2C driver documentation concerning I2C address management</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">.</span></li></ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal; font-weight: bold;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL IWDG</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana;">New simplified HAL IWDG driver: r</span><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;">emoved HAL_IWDG_Start(), HAL_IWDG_MspInit() and HAL_IWDG_GetState() APIs.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana;">The API functions are: </span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana;">HAL_IWDG_Init(): </span><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;">this function insures the configuration and the start of the IWDG counter.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana;">HAL_IWDG_Refresh(): </span><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;">this function insures the reload of the IWDG counter.</span></li></ul></ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal; font-weight: bold;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL PWR</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Aligned Power Wake-Up </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">pins</span><span style="font-size: 10pt; font-family: Verdana;"> </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">EWUPx definitions on CMSIS definitions.</span></li></ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal; font-weight: bold;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL RTC</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated HAL_RTCEx_SetWakeUpTimer_IT() function by adding clear of Wake-Up flag before enabling the interrupt.</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"></span></li></ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal; font-weight: bold;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL SMBUS</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated SMBUS driver documentation concerning SMBUS address management</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">.</span></li></ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal; font-weight: bold;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL SDADC</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated HAL SDADC Driver compliancy with </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">MISRA C 2004 rules</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">:</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"></span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">MISRA C 2004 rule 10.3 (illegal explicit conversion from type "unsigned int" to "uint16_t *)</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">.</span></li></ul></ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal; font-weight: bold;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL SPI</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated __SPI_HandleTypeDef </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">definition by using __IO uint16_t type for TxXferCount and RxXferCount.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: windowtext; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Updated
+SPI_2linesTxISR_8BIT() and SPI_2linesTxISR_16BIT() functions: added
+return so that SPI_2linesTxISR_8BITCRC() or SPI_2linesTxISR_16BITCRC()
+function is called from HAL_SPI_TransmitReceive_IT()<br>when CRC is activated.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated SPI</span><span style="color: rgb(0, 0, 0); font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US"> Driver compliancy with<span class="Apple-converted-space"> </span></span><span style="color: rgb(0, 0, 0); font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">MISRA C 2004 rule 5.2 (identifiers in an inner scope shall not<br>use the same name as an identifier in an outer scope)</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">.</span></li></ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal; font-weight: bold;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL WWDG</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana;">New simplified HAL WWDG driver: removed </span><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;">HAL_WWDG_Start(), HAL_WWDG_Start_IT(), HAL_WWDG_MspDeInit() and HAL_WWDG_GetState() APIs.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Updated </span><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;"></span><span style="font-size: 11pt; font-family: Calibri,sans-serif; color: black;">HAL_WWDG_Refresh</span><span style="font-size: 10pt; font-family: Verdana;">() API to remove counter parameter.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana;">New field EWIMode in WWDG_InitTypeDef to specify need for Early Wakeup Interrupt.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana;">The
+API functions are: HAL_WWDG_Init(), HAL_WWDG_MspInit(),
+HAL_WWDG_Refresh(), HAL_WWDG_IRQHandler() and
+HAL_WWDG_EarlyWakeupCallback().</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.1
+/ 29-April-2016</span></h3>
+<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes</span></u></b></p><ul style="margin-top: 0cm; list-style-type: square;"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">Maintenance release to fix known defects and enhancements implementation.<br></span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL generic</span></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated HAL Driver compliancy with </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">MISRA C 2004 rules</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">:</span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">MISRA C 2004 rule 10.6 ('U' suffix applied to all constants of 'unsigned' type).</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">MISRA C 2004 rule 10.5 (bitwise operators ~ and <<).</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">MISRA C 2004 rule 12.6 </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">(operands of logical operators (&&, || and !) should be effectively Boolean).<br></span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">MISRA C 2004 rule 12.7 (bitwise operations not performed on signed integer types).</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">MISRA C 2004 rule 14.3 </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">(a null statement shall only occur on a line by itself).</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">MISRA C 2004 rule 14.8 </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">(statement forming the body of a switch, while, do Â… while or for statement shall be a compound statement).</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">MISRA C 2004 rule 15.3 </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">(final clause of a switch statement shall be the default clause).<br></span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">MISRA C 2004 rule 16.4 </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">(identifiers used in the declaration and definition of a function shall be identical).<br></span></li></ul></ul><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated HAL weak empty callbacks to prevent unused argument compilation warnings.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated stm32f3xx_hal_conf.h files:</span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Set HSE_STARTUP_TIMEOUT value to 100ms instead of 5000ms.</span></li></ul></ul></ul><ul style="margin-top: 0cm; list-style-type: square;"><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal; font-weight: bold;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Changed uwTick to global to allow overwrite of HAL_IncTick().</span></li></ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal; font-weight: bold;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL COMP</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Added delay in COMP startup time required to reach propagation delay specification</span><span style="font-size: 10pt; font-family: Verdana;">.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Added missing __HAL_UNLOCK, __HAL_LOCK in HAL_COMP_Start().</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Modified COMP_INVERTINGINPUT_SELECTION() macro as COMP inverting inputs selection, depends on COMPx instance.<br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL DAC</span></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Updated DAC functions after DAC_CR_BOFFx/DAC_CR_OUTENx bit definition updates.</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"></span></li></ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal; font-weight: bold;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL DMA</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Added __HAL_DMA_GET_COUNTER</span><span style="font-size: 10pt; font-family: Verdana;">() macro returning the number of remaining data units in the current DMA Channel transfer.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Provided
+new function HAL_DMA_Abort_IT() to abort current DMA transfer
+under interrupt mode without polling for DMA enable bit.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL GPIO</span></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Added macros to manage Fast Mode Plus on GPIOs.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL FMC</span></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Removed private macro IS_FMC_PAGESIZE not supported by STM32F3xx serie.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL I2C</span></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Aligned I2C driver with new state machine definition.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated __HAL_I2C_DISABLE_IT macro.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Used macro definition for I2C instances supporting Wakeup from Stop mode</span><span style="font-size: 10pt; font-family: Verdana;">.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Added support of repeated start feature in case of multimaster mode (allow master to keep I2C communication with slave).</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Updated WaitOnFlag management (timeout measurement should be always cumulative).</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Optimized HAL_I2C_XX_IRQHandler() functions (read status registers only once).</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Reworked DMA end process and I2C error management during DMA transfer.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Modified HAL_I2C_Master_Transmit to handle sending data of size 0.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Updated
+DMA Abort management: used new HAL_DMA_Abort() function and called
+HAL_I2C_ErrorCallback() when errors occur during DMA transfer.<br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL I2S</span></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Removed support of I2S full-duplex feature on STM32F301x8 device.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL IRDA</span></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Reviewed IRDA state machine to avoid cases where IRDA state is overwritten by IRDA IRQ</span><span style="font-size: 10pt; font-family: Verdana;">.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Modified EIE bit setting in Tx and Rx transfers (Interrupt mode).</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Modified IRDA_Receive_IT() to execute the RX flush request only in case no data is read from RDR.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Updated IRDA_SetConfig() function following UART Baudrate calculation update.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL FMC</span></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Updated FMC_NORSRAM_Init() function (BurstAccessMode field configuration).</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Added FMC_BCR1_CCLKEN in the BCR register clear mask used for FMC_NORSRAM_Init().<br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL OPAMP</span></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Updated definitions of OPAMP Non Inverting Input constants.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL RCC</span></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Performed optimizations for internal oscillators and PLL startup time.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Performed optimizations for HAL_RCC_ClockConfig(), HAL_RCCEx_PeriphCLKConfig functions.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Modified reset of Backup domain only if the RTC Clock source selection is modified from reset value.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Updated HAL_RCC_OscConfig() function (Reset HSEON/LSEON and HSEBYP/LSEBYP bits before configuring the HSE/LSE).</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Corrected updates of SystemCoreClock variable within the HAL drivers.<br></span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Corrected invertion in LSE drive capability Bit definition.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Modified AHBPrescTable and APBPrescTable in HAL.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Removed RCC_CFGR_PLLNODIV bit definition from STM32F358xx, STM32F303xC and STM32F302xC devices.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Removed RCC_CSR_VREGRSTF bit definition in RCC_CSR register for STM32F303xC and STM32F303xE devices.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Removed USART2 and USART3 clock switch in RCC_CFGR3 register not supported by STM32F303x8, STM32F334x8<br>and STM32F328xx devices and for STM32F301x8, STM32F302x8 and STM32F318xx devices.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Removed
+RCC_CSR_V18PWRRSTF bit definition in RCC_CSR register not supported by
+STM32F318xx, STM32F328xx, STM32F358xx, STM32F378xx and STM32F398xx
+devices.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Removed flag RCC_FLAG_RMV which is write only.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Added RCC_CFGR_xxxx_BITNUMBER definitions for portability between </span><span style="font-size: 10pt; font-family: Verdana;">STM32 series</span><span style="font-size: 10pt; font-family: Verdana;">.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Updated HAL_RCC_OscConfig() function to enable PWR only if necessary for LSE configuration.<br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL RTC</span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Added missing Tamper definitions (RTC_TAFCR register).</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL SMARTCARD</span></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Reviewed SMARTCARD state machine to avoid cases where SMARTCARD state is overwritten by SMARTCARD IRQ</span><span style="font-size: 10pt; font-family: Verdana;">.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Modified SMARTCARD_Receive_IT() to execute the RX flush request only in case no data is read from RDR.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Added SMARTCARD_STOPBITS_0_5 definition used for smartcard mode.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Updated SMARTCARD_SetConfig() function following UART Baudrate calculation update.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL SPI</span></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Updated HAL_SPI_TransmitReceive() function </span><span style="font-size: 10pt; font-family: Verdana;">in slave mode </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">to </span><span style="font-size: 10pt; font-family: Verdana;">receive correctly the CRC when NSS pulse activated.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Added missing __IO in SPI_HandleTypeDef definition.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Updated IS_SPI_CRC_POLYNOMIAL macro definition as polynomial value should be odd only.<br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL TIM</span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Updated HAL_TIM_ConfigOCrefClear() function to manage correctly TIM state (BUSY, READY).</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Used </span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">IS_TIM_HALL_INTERFACE_INSTANCE </span><span style="font-size: 10pt; font-family: Verdana;">macro instead of </span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">IS_TIM_XOR_INSTANCE </span><span style="font-size: 10pt; font-family: Verdana;">macro in<br>HAL_TIMEx_HallSensor_xxx() functions.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Updated TIM_SLAVEMODE constants definitions using CMSIS bit definitions.<br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL TSC</span></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Updated IO default state management</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL UART-USART</span></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Updated UART Baudrate calculation (UART_DIV_SAMPLING8() and UART_DIV_SAMPLING16() macros).</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Updated USART_SetConfig() function following UART Baudrate calculation update.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span><span style="font-size: 10pt; font-family: Verdana;">Reviewed UART state machine to avoid cases where UART state is overwritten by UART IRQ</span><span style="font-size: 10pt; font-family: Verdana;">.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Removed USART2 and USART3 clock switch, not supported by STM32F303x8, STM32F334x8 and STM32F328xx devices<br>and for STM32F301x8, STM32F302x8 and STM32F318xx devices.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Modified UART_Receive_IT() to execute the RX flush request only in case no data is read from RDR.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Corrected macro used in assert_param of HAL_LIN_SendBreak() function.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Added UART_STOPBITS_0_5/USART_STOPBITS_0_5 definitions used for synchronous mode.<br></span></li></ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal; font-weight: bold;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">USB</span></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Corrected double buffer implementation in PCD_SET_EP_DBUF1_CNT() macro.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL WWDG</span></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Aligned WWDG registers bits naming between all STM32 series.</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"></span></li></ul></ul><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US"><span style="color: red;"></span></span></b><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"><o:p></o:p></span></u></b></p>
+
+
+
+ <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.0
+/ 13-November-2015<o:p></o:p></span></h3><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes</span></u></b></p>
+
+
+
+<span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><ul style="margin-top: 0cm; list-style-type: square;"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">Performed HAL API alignment (macros/functions/constants renaming).<br></span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL generic</span></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Provided/updated User Manual CHM files for STM32F334x8, STM32F373xC, STM32F303xC devices.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated HAL drivers to ensure compliancy w/ C++.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Made corrections for MISRA rule: bitwise operators ~ and << (MISRA C 2004 rule 10.5).</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Used CMSIS mask definitions instead of hardcoded values.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Removed all the unused FLAG and IT assert macros.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Initialized Handle lock to HAL_UNLOCKED in HAL_PPP_Init() when state == HAL_PPP_STATE_RESET.<br></span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated stm32f3xx_hal_msp.c files:</span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Removed reference to MicroXplorer.</span></li></ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated stm32f3xx_hal_conf.h files:</span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Added LSE_STARTUP_TIMEOUT definition.</span></li></ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated stm32f3xx_hal_def.h file:</span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Added some generic defines (__NOINLINE).</span></li></ul><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Removed NULL redefinition.<br><br></span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL ADC</span></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated HAL ADC state machine updated. States changed from fixed literals to bitfields.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Added
+3 new HAL ADC functions: HAL_ADCEx_RegularStop(),
+HAL_ADCEx_RegularStop_IT(), HAL_ADCEx_RegularStop_DMA(), to
+perform a ADC group regular conversion stop<br>while ADC group injected can remain with conversion on going.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Added 2 new HAL ADC functions: HAL_ADCEx_LevelOutOfWindow2Callback(), HAL_ADCEx_LevelOutOfWindow3Callback().<br>The
+3 analog watchdog has its own callback function (AWD1 callback function
+is unchanged with HAL_ADC_LevelOutOfWindowCallback()).</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated ADC multimode (for devices with several ADC instances).<br>Now
+takes into account mixed configuration: ADC group regular in multimode,
+ADC group injected in independent mode (and the opposite).</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated ADC group injected use case when used with feature low power "auto-wait":<br>updated function HAL_ADCEx_InjectedGetValue() which donÂ’t clear anymore ADC flag EOS,<br>and could cause some issues when using ADC group injected with high sampling rate.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL CAN</span></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Added __HAL_UNLOCK(hcan) macro.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Modified CanTxMsgTypeDef/CanRxMsgTypeDef structures Data field.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Removed assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber)) from HAL_CAN_ConfigFilter().</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL CEC</span></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Changed the HAL_CEC_ErrorTypeDef structure by separate defines.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Added CEC Flags Definitions(CEC_FLAG_TXACKE,Â…).</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Add CEC Interrupts Definitions(CEC_IT_TXACKE,Â…).</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Renamed CEC_ISR_XXX to CEC_FLAG_XXX.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Renamed CEC_IER_XXX to CEC_IT_XXX.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Added missing assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance)); in In HAL_CEC_Init().</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Added devices that supports CEC in device.h files.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated CEC Ready To Receive State in CEC_Transmit_IT().</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Added new API HAL_CEC_GetReceivedFrameSize to get size of the received frame.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL COMP</span></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated COMPEx_Output comment description and added test on instances.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated HAL_COMP_DeInit() to handle LOCKED state.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Added missing defines for COMP window mode (Sunfish).</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL CORTEX</span></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Removed __HAL_CORTEX_SYSTICKCLK_CONFIG macro, replaced by HAL_SYSTICK_CLKSourceConfig() function.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Added new CORTEX MPU APIs: HAL_MPU_ConfigRegion(), HAL_MPU_Disable(),HAL_MPU_Enable().</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Added APIs to manage set/reset of SLEEPONEXIT and SEVONPEND bits in SCR register.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Added a check on negative parameter values for HAL_NVIC_DisableIRQ()/HAL_NVIC_EnableIRQ() functions.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL CRC</span></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated CRC APIs comments.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Fixed MISRA C 2004 warnings (except 114, 12.4 and 14.7).</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated __HAL_CRC_SET_IDR macro.<br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL DAC</span></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Update HAL_DACEx_NoiseWaveGenerate() and HAL_DACEx_TriangleWaveGenerate()<br>to reset DAC CR register before setting the new DAC config.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Added DAC_OUTPUTSWITCH_ENABLE constant.<br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL DMA</span></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Reviewed HAL_DMA_PollForTransfer(). Added error code.<br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL FLASH/FMC</span></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Added FLASH API HAL_FLASHEx_OBGetUserData() to get the value saved in User data option byte.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Aligned Return value of HAL_FLASH_EndOfOperationCallback function (0xFFFFFFF) when process is finished.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated function FLASH_OB_GetRDP() return value (FlagStatus (RESET,SET)).</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Corrected way to set Flash read protection by performing an automatic option byte erase<br>in FLASH_OB_RDP_LevelConfig function.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated Disable WRP to be compliant with other families.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Removed double definition of IS_OB_SDACD_VDD_MONITOR.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Added missing macro __HAL_FLASH_GET_LATENCY.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Corrected IS_OPTIONBYTE() macro in the case all option_OB are selected.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated HAL_NOR_GetStatus() (missing exit from waiting loop when timeout occurred).</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Reviewed __ARRAY_ADDRESS macro and adapted tests to detect bad blocks.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated FMC_NORSRAM_Init()/FSMC_NORSRAM_Init() in order to not modify the default values<br>for the reserved bits in the BTCR register.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL GPIO</span></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated GPIO Output Speed literals naming to ensure HAL full compatibility.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Added only one define BSRR for BSRRH/BSRRL register.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Fixed issue to ensure interrupt mode is reset.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Reworked GPIO_GET_SOURCE() in order to check only existing GPIO bank.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Add new macro IS_GPIO_AF_INSTANCE to protect GPIO banks without alternate function register<br>from being initialized as AF.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL HRTIM</span></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Corrected bit definition for HRTIM_MCMPxR registers.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Corrected naming for delayed protection related constants.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Added missing assert in HAL_HRTIM_BurstModeConfig().</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Added missing macros __HAL_FREEZE_ HRTIM1_DBGMCU(), __HAL_UNFREEZE_ HRTIM1_DBGMCU ()<br>to stop the HRTIM when the core is halted (to control the DBGMCU_APB2_FZ.DBG_HRTIM1_STOP bitfield).</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL I2C</span></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Corrected wrong management of AF after NACK.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Renamed I2C_CR1_DFN to I2C_CR1_DNF.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Corrected management of I2C state in the function I2C_MasterTransmit_ISR().</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Re-introduced the MACROs to manage the FM+ capapbility on some GPIOs.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL I2S</span></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Added DMA circular mode support for the communication peripherals.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated I2S HAL_I2S_Transmit() API on busy flag.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL IRDA</span></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Added DMA circular mode support for the communication peripherals.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Implemented __HAL_UART_FLUSH_DRREGISTER macro, required by the In-Application Programming (IAP)<br>using the USART application.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Used new macro IS_UART_DMA_INSTANCE in assert_param() calls for IRDA DMA related primitives.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Changed UART TX-IT implementation to remove WaitOnFlag in ISR.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Fixed issue in IRDA DMA implementation: missed clear of the TC bit in the SR register.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Corrected definition of IS_IRDA_REQUEST_PARAMETER macro.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Modified Time Out management: report state READY instead of TIMEOUT.<br>Time-out information is reported by function output parameter.<br></span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Corrected PCLK source for USART1.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL OPAMP</span></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated HAL_OPAMP_DeInit() to handle LOCKED state.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Added __HAL_UNLOCK in HAL_OPAMP_DeInit.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Removed InvertingInput ASSERT in HAL_OPAMP_Init() as it is not needed in PGA mode.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated definition of OPAMP_CSR_UPDATE_PARAMETERS_INIT_MASK in OPAMP Init.<br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL PWR</span></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Fixed MISRA C 2004 warnings, resort to reference SET_BIT, CLEAR_BIT macros.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated Device information when missing, systematically added USE_FULL_ASSERT compilation switch.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Added local variables addition to suppress warnings.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Removed useless regulator parameter setting in HAL_PWR_EnterSLEEPMode().</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL RCC</span></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Renamed RCC_CFGR3_USART1SW_PCLK to RCC_CFGR3_USART1SW_PCLKx according to devices.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Added missing flag for RCC_CSR_VREGRSTF bit.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Added missing flag for RCC_CFGR_MCOF feature.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Added missing macro __HAL_RCC_LSEDRIVE_CONFIG.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Renamed IS_RCC_PERIPHCLK to IS_RCC_PERIPHCLOCK.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Renamed __HAL_RCC_MCO_CONFIG to __HAL_RCC_MCO1_CONFIG.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated RCC APIs to add interface HAL_RCCEx_GetPeriphCLKFreq.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Implemented workaround to cover RCC limitation regarding Peripheral enable delay.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Modified HAL_RCCEx_PeriphCLKConfig to reset backup domain only if RTC clock source has been changed.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Reworked __HAL_RCC_LSE_CONFIG macro to manage correctly LSE_Bypass.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Followed specific procedure to enable HSE.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated HAL_RCC_OscConfig() to modify check on LSEState.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Added PLL_DIV1 define missing from the RCC_MCO_Clock_Source defgroup.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Added new macro __HAL_RCC_IS_PWR_CLOCK_ENABLED() to replace condition on Peripheral Clock enable status.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Added new macro __HAL_RCC_SYSCLK_CONFIG() to configure the SYSCLK clock source.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Fixed issue in HAL_RCC_OscConfig when RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL RTC(BKP)</span></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated list of backup registers definition.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated Bits mask literals used in macros definition.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Renamed RTC_OUTPUT_REMAP_XX and RTC_TIMESTAMPPIN_XX macros.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated definition of __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Aligned different implementations of HAL_RTC_XXIRQHandler().</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Check the behavior of flag WUTWF and corrected update of wakeup counter registers.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Added subsecond fration formula in HAL_RTC_GetTime() function.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL SDADC</span></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Applied ReferenceVoltage parameter in HAL_SDADC_Init() wathever instance.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Added new macros __HAL_SDADC_ENABLE_IT(), __HAL_SDADC_GET_IT_SOURCE(), __HAL_SDADC_GET_FLAG().</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL SMARTCARD</span></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Implemented __HAL_UART_FLUSH_DRREGISTER macro, required by the In-Application Programming (IAP)<br>using the USART application.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Changed UART TX-IT implementation to remove WaitOnFlag in ISR.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Added missing IDLE flag management.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Modified Time Out management: report state READY instead of TIMEOUT.<br>Time-out information is reported by function output parameter.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Corrected PCLK source for USART1.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL SPI</span></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Improved SPI performances.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Added Fit Bit feedback (with BSY flag check) for all the process.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated function descriptions.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Fixed issue on Rx 2line with DataSize8bit, even buffer size and CRC 8bit.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Added DMA circular mode support for the communication peripherals.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Removed DMA Tx Callback in case of RxOnly mode from HAL_SPI_TransmitReceive_DMA().</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Added HAL_SPI_GetError().<br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL TIM</span></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Corrected assert checks in HAL_TIM_ConfigClockSource() when setting internal clock source.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Removed useless assert() in TIM functions.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated implementation of __HAL_TIM_SET_COMPARE macro.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated Repetition counter bits definition.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Modified HAL_TIM_ConfigOCrefClear() to avoid possible overwrite of SMCR register.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Removed assert on trigger polarity in the case TIM_TS_TI1F_ED.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Removed HAL_TIM_SlaveConfigSynchronization_DMA() from HAL_TIM APIs.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Added TIM edge modification macros: TIM_SET_CAPTUREPOLARITY(), TIM_RESET_CAPTUREPOLARITY(), __HAL_TIM_SET_CAPTUREPOLARITY.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Added URS_ENABLE, URS_DISABLE macros.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Changed Time Out management: report state READY instead of TIMEOUT.<br>Time-out information is reported by function output parameter.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Added new function HAL_TIM_SlaveConfigSynchronization_IT() to handle the trigger interrupt activation.<br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL TSC</span></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Recovered IS_TSC_SS and IS_TSC_SSD macro definitions.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL UART-USART</span></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Added DMA circular mode support for the communication peripherals.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Modified Time Out management: report state READY instead of TIMEOUT.<br>Time-out information is reported by function output parameter.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Changed UART_DMATransmitCplt() implementation to remove WaitOnFlag in ISR.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Implemented __HAL_UART_FLUSH_DRREGISTER macro, required by the In-Application Programming (IAP)<br>using the USART application.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Corrected behavior of HAL_UART_IRQ_Handler() (removed enabling/disabling of ERR IT source).</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Added IS_UART_DMA_INSTANCE macro to sort UART instances supporting DMA communication.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Used new macro IS_UART_DMA_INSTANCE in assert_param() calls for UART DMA related primitives.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Changed UART TX-IT implementation to remove WaitOnFlag in ISR.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Added MACRO to UART HAL to control CTS and RTS from the customer application.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Renamed HAL_UART_WakeupCallback() in HAL_UARTEx_WakeupCallback().</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Corrected setting of BRR register bit[3:0] when OVER8 sampling mode is used.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Corrected values used as parameter of __HAL_USART_CLEAR_IT() in HAL_USART_IRQHandler().</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated HAL_USART_Init() to reach max frequencies (enable oversampling by 8).</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Fixed issue in UART DMA implementation: missed clear of the TC bit in the SR register.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Added test in HAL_LIN_Init() as only 8-bit data length is available with USART Lin mode Data length.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated USART_IT_CM defined value.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Corrected PCLK source for USART1.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL USB/PCD</span></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Corrected products define supporting USB feature.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated call to Double Buffering Counter Function.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated HAL PCD clear flag macros configuration.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Corrected issue in HAL_PCD_EP_Transmit() function, regarding the double-buffering mode for IN endpoints.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL WWDG</span></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated IT macro management.</span></li></ul></ul><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"><br></span><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.1
+/ 19-June-2015<o:p></o:p></span></h3><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes</span></u></b></p>
+
+
+
+<span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><ul style="margin-top: 0cm; list-style-type: square;"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Fixed compilation warnings reported by TrueSTUDIO and SW4STM32 toolchains.</span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.0
+/ 12-Sept-2014<o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes</span></u></b></p>
+
+
+
+<ul style="margin-top: 0cm; list-style-type: square;"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">First official
+release of STM32F3xx HAL drivers for </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; font-weight: bold;">STM32F303xE,
+</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; font-weight: bold;">STM32F302xE</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; font-weight: bold;"> </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">and</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; font-weight: bold;"> </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; font-weight: bold;">STM32F398xx
+</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; font-weight: bold;">devices.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL generic</span> update</span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Add support of new
+ devices <b>STM32F302xE</b> and<b> STM32F398xx</b> in STM32F3xx HAL drivers<o:p></o:p></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: windowtext;" lang="EN-US"><span style=""></span></span></li></ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: windowtext;" lang="EN-US"><span style=""></span><b>HAL ADC</b><o:p></o:p></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Empty weak function
+ return HAL_ERROR<o:p></o:p></span></li></ul></ul><ul style="margin-top: 0cm; list-style-type: square;"><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Misra error
+ corrections</span></li></ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: windowtext;" lang="EN-US"><b>HAL CORTEX</b><o:p></o:p></span></li></ul>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<ul style="margin-top: 0cm; list-style-type: square;"><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Macro IS_SYSTICK_CLKSOURCE
+ renamed IS_SYSTICK_CLK_SOURCE</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: windowtext;" lang="EN-US"></span></li></ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: windowtext;" lang="EN-US"><b>HAL DAC</b><o:p></o:p></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Empty weak function
+ return HAL_ERROR</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: windowtext;" lang="EN-US"></span></li></ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: windowtext;" lang="EN-US"><b>HAL IWDG</b><o:p></o:p></span><span style="font-family: "Helvetica","sans-serif";" lang="EN-US"></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Minor updates (HAL coding rules)</span><span class="MsoNormal" style="font-family: "Helvetica","sans-serif";" lang="EN-US"></span></li></ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: windowtext;" lang="EN-US"><b>HAL PCD</b><o:p></o:p></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Changed </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">IN/OUT
+ EndPoint parameter array size (PCD Handle Structure)</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"><o:p></o:p></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: windowtext;" lang="EN-US"></span></li></ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: windowtext;" lang="EN-US"><b>HAL RCC</b><o:p></o:p></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">RCC_MCOSOURCE_PLLCLK_DIV1
+ define added to RCC_MCO_Clock_Source defgroup for the following devices: STM32F302xE,
+ STM32F303xE, STM32F398xx, STM32F303x8, STM32F328xx, STM32F301x8, STM32F302x8
+ and STM32F318xx</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"><o:p></o:p></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: windowtext;" lang="EN-US"></span></li></ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: windowtext;" lang="EN-US"><b>HAL SPI</b><o:p></o:p></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Removed HAL_
+ prefix from static function names</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"><o:p></o:p></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: windowtext;" lang="EN-US"></span></li></ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: windowtext;" lang="EN-US"><b>HAL TIM</b><o:p></o:p></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Checked
+ DeadTime value in debug mode</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Add new macros __HAL_TIM_URS_ENABLE() and </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">__HAL_TIM_URS_DISABLE()</span></li></ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: windowtext;" lang="EN-US"><b>HAL WWDG</b><o:p></o:p></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Minor updates (HAL coding
+ rules)</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Added macro __HAL_WWDG_CLEAR_IT()</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Use MODIFY_REG() macro to set Prescaler, Window and Counter registers within HAL_WWDG_Init()</span><span style="font-family: "Helvetica","sans-serif";" lang="EN-US"> </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"><o:p></o:p></span></li></ul></ul>
+
+
+
+
+
+
+
+
+
+<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.0RC2
+/ 25-August-2014<o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes</span></u></b></p>
+
+
+
+
+
+
+
+
+<ul style="list-style-type: square;"><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL generic</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">General improvement of
+ Doxygen Tags for CHM UM generation</span><span style="font-size: 12pt; font-family: "Times New Roman","serif";" lang="EN-US"><o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Add support of new
+ devices <b>STM32F303xE</b> in STM32F3xx HAL driver</span><span style="font-weight: bold;"></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-weight: bold;"></span><b><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL </span></b><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">update (for </span><b><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">STM32F303xE</span></b><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">)<o:p></o:p></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Add new defines for ADC
+ trigger remapping (HAL_REMAPADCTRIGGER_x)</span><span style="font-size: 12pt; font-family: "Times New Roman","serif";" lang="EN-US"><o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Add new defines for CCM
+ RAM page write protection (up to 16 pages can be write protected)</span><span style="font-size: 12pt; font-family: "Times New Roman","serif";" lang="EN-US"><o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Add new macro IS_HAL_REMAPADCTRIGGER()</span><span style="font-size: 12pt; font-family: "Times New Roman","serif";" lang="EN-US"><o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated macro IS_HAL_SYSCFG_WP_PAGE
+ ()</span><span style="font-size: 12pt; font-family: "Times New Roman","serif";" lang="EN-US"><o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Add new macros to
+ freeze/unfreeze TIM20 in debug mode: __HAL_FREEZE_TIM20_DBGMCU() and __HAL_UNFREEZE_TIM20_DBGMCU()</span><span style="font-size: 12pt; font-family: "Times New Roman","serif";" lang="EN-US"><o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Add new macro to remap
+ the FMC banks 1 and 2 at 0x00000000 : __HAL_FMC_BANK()</span><span style="font-size: 12pt; font-family: "Times New Roman","serif";" lang="EN-US"><o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Add new macros to
+ enable/disable ADC trigger remapping: __HAL_REMAPADCTRIGGER_ENABLE() and __HAL_REMAPADCTRIGGER_DISABLE</span>()<b><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"></span></b></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><b><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL ADC </span></b><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">update (for </span><b><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">STM32F303xE</span></b><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">)<o:p></o:p></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Add new defines for TIM20
+ related ADC external triggers for regular groups (ADC_EXTERNALTRIGCONV_T20_x)</span><span style="font-size: 12pt; font-family: "Times New Roman","serif";" lang="EN-US"><o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Add new defines for TIM20
+ related ADC external triggers for injected groups (ADC_EXTERNALTRIGINJECCONV_T20_x)</span><span style="font-size: 12pt; font-family: "Times New Roman","serif";" lang="EN-US"><o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated macro __HAL_ADC_CFGR_EXTSEL() to take into account </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">TIM20 related ADC
+ triggers for regular channels</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"><o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated macro __HAL_ADC_JSQR_JEXTSEL() to take into account </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">TIM20 related ADC
+ triggers for injected channels</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"><o:p></o:p></span></li></ul></ul><ul style="list-style-type: square;"><li><b><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL COMP </span></b><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">update</span></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Defect correction:</span></li></ul><ul><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: windowtext;" lang="EN-US">Missing assert param IS_COMP_TRIGGERMODE</span></li></ul></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: windowtext;" lang="EN-US">STM32F303xE:</span><span style="font-size: 10pt;" lang="EN-US"></span></li></ul><ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Add new defines for comparator output redirection: COMP_OUTPUT_TIM20BKIN,
+ COMP_OUTPUT_TIM20BKIN2, COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2_TIM20BKIN2 and COMP_OUTPUT_TIM20OCREFCLR<o:p></o:p></span></li></ul></ul><li><span style="font-size: 10pt;" lang="EN-US"><span class="MsoNormal"></span></span><b><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL FLASH </span></b><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">update (for </span><b><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">STM32F303xE</span></b><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">)<o:p></o:p></span></li></ul>
+
+
+
+
+
+
+<ul style="margin-top: 0cm;" type="disc"><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; line-height: 115%; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">Add
+new defines for write protection of pages 32 to 61 and 62-263 (OB_WRP_PAGESxxTOyy)</span></li></ul></ul>
+
+<ul style="list-style-type: square;"><li><span style="font-family: Symbol;"></span><span style="" lang="EN-US"><span style=""></span></span><b><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL GPIO </span></b><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">update (for </span><b><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">STM32F303xE</span></b><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">)<o:p></o:p></span></li></ul>
+
+<ul style="margin-top: 0cm;" type="disc"><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; line-height: 115%; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">Add
+new defines for TIM20 and FMC related AF: GPIO_AF2_TIM20, GPIO_AF3_TIM20, GPIO_AF6_TIM20 and
+GPIO_AF12_FMC</span></li></ul></ul>
+
+<ul style="list-style-type: square;"><li><span style="font-family: Symbol;"></span><span style="" lang="EN-US"><span style=""></span></span><b><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL IRDA </span></b><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">update<o:p></o:p></span></li></ul>
+
+<ul style="margin-top: 0cm;" type="disc"><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; line-height: 115%; font-family: "Verdana","sans-serif"; color: windowtext;" lang="EN-US">TC enabled and TXE disabled at the end of TX in IT
+mode</span><span style="font-size: 10pt;" lang="EN-US"><o:p></o:p></span></li></ul></ul>
+
+<ul style="list-style-type: square;"><li><span style="font-family: Symbol;"></span><span style="" lang="EN-US"><span style=""></span></span><b><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL HAL NAND</span></b><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"> (</span><b><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">STM32F303xE specific</span></b><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">)<o:p></o:p></span></li></ul>
+
+<ul style="margin-top: 0cm;" type="disc"><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; line-height: 115%; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">FMC: generic
+firmware to drive NAND memories mounted as external device</span></li></ul></ul>
+
+<ul style="list-style-type: square;"><li><span style="font-family: Symbol;"></span><span style="" lang="EN-US"><span style=""></span></span><b><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL NOR</span></b><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"> (</span><b><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">STM32F303xE specific</span></b><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">)<o:p></o:p></span></li></ul>
+
+<ul style="margin-top: 0cm;" type="disc"><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; line-height: 115%; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">FMC: generic
+firmware to drive NOR memories mounted as external device</span></li></ul></ul>
+
+<ul style="list-style-type: square;"><li><span style="font-family: Symbol;"></span><span style="" lang="EN-US"><span style=""></span></span><b><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL PCCARD</span></b><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"> (</span><b><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">STM32F303xE specific</span></b><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">)<o:p></o:p></span></li></ul>
+
+<ul style="margin-top: 0cm;" type="disc"><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; line-height: 115%; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">FMC: generic
+firmware to drive PCCARD memories mounted as external device</span></li></ul></ul>
+
+<ul style="list-style-type: square;"><li><span style="font-family: Symbol;"></span><span style="" lang="EN-US"><span style=""></span></span><b><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL PCD </span></b><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">update <o:p></o:p></span></li></ul>
+
+<ul style="margin-top: 0cm;" type="disc"><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; line-height: 115%; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">Add
+new macros __HAL_USB_EXTI_GET_FLAG() , __HAL_USB_EXTI_CLEAR_FLAG(), __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER(),
+__HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER() and _HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER()</span></li></ul></ul>
+
+<ul style="list-style-type: square;"><li><span style="font-family: Symbol;"></span><span style="" lang="EN-US"><span style=""></span></span><b><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL PWR </span></b><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">update <o:p></o:p></span></li></ul>
+
+<ul style="margin-top: 0cm;" type="disc"><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; line-height: 115%; font-family: "Verdana","sans-serif"; color: windowtext;" lang="EN-US">PVD feature need falling/rising Event modes</span></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: rgb(127, 127, 127);" lang="EN-US"><span style="color: windowtext;">Rename <span style=""> </span>defines: </span></span></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: rgb(127, 127, 127);" lang="EN-US"><span style="color: windowtext;">PWR_MODE_EVT to PWR_PVD_MODE_NORMAL</span></span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: rgb(127, 127, 127);" lang="EN-US"><span style="color: windowtext;">PWR_MODE_IT_RISING to PWR_PVD_MODE_IT_RISING<o:p></o:p></span></span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: rgb(127, 127, 127);" lang="EN-US"><span style="color: windowtext;">PWR_MODE_IT_FALLING to PWR_PVD_MODE_IT_FALLING<o:p></o:p></span></span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: rgb(127, 127, 127);" lang="EN-US"><span style="color: windowtext;">PWR_MODE_IT_RISING_FALLING to PWR_PVD_MODE_IT_RISING_FALLING<o:p></o:p></span></span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: rgb(127, 127, 127);" lang="EN-US"><span style="color: windowtext;">PWR_MODE_IT_RISING to PWR_PVD_MODE_IT_RISING<o:p></o:p></span></span></li></ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: rgb(127, 127, 127);" lang="EN-US"><span style="color: windowtext;">Add new
+ defines: PWR_PVD_MODE_EVENT_RISING, PWR_PVD_MODE_EVENT_FALLING and
+ PWR_PVD_MODE_EVENT_RISING_FALLING<o:p></o:p></span></span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: rgb(127, 127, 127);" lang="EN-US"><span style="color: windowtext;">Changed
+ __HAL_PVD_EXTI_ENABLE_IT() macro<span style="">
+ </span>definition: __EXTILINE__ argument no longer needed
+ (PWR_EXTI_LINE_PVD is used implicitly)<o:p></o:p></span></span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: rgb(127, 127, 127);" lang="EN-US"><span style="color: windowtext;">Changed
+ __HAL_PVD_EXTI_DISABLE_IT() macro definition: __EXTILINE__ argument no
+ longer needed (PWR_EXTI_LINE_PVD is used implicitly)<o:p></o:p></span></span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: rgb(127, 127, 127);" lang="EN-US"><span style="color: windowtext;">Changed
+ __HAL_PVD_EXTI_GET_FLAG () macro definition: __EXTILINE__ argument no
+ longer needed (PWR_EXTI_LINE_PVD is used implicitly)<o:p></o:p></span></span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: rgb(127, 127, 127);" lang="EN-US"><span style="color: windowtext;">Changed
+ _HAL_PVD_EXTI_CLEAR_FLAG () macro definition: __EXTILINE__ argument no
+ longer needed (PWR_EXTI_LINE_PVD is used implicitly)</span></span></li><li><span style="font-size: 10pt; line-height: 115%; font-family: "Verdana","sans-serif"; color: windowtext;" lang="EN-US">Add
+new macros __HAL_PWR_PVD_EXTI_ENABLE_EVENT(),
+__HAL_PWR_PVD_EXTI_DISABLE_EVENT(),<span style="">
+</span>__HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER(),
+__HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER() and
+__HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER()</span></li></ul></ul></ul>
+
+
+
+
+
+<span style="font-size: 10pt; line-height: 115%; font-family: "Verdana","sans-serif"; color: rgb(127, 127, 127);" lang="EN-US"></span><ul style="list-style-type: square;"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><b><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL RCC </span></b><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">update (for </span><b><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">STM32F303xE</span></b><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">)<o:p></o:p></span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">RCC_OcsInitTypeDef and RCC_PLLInitTypeDef definitions are now product dependent: </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"></span></li><ul style="color: black;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">STM32F303xE:</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Added PREDIV field to RCC_PLLInitTypeDef: used to set the
+ desired pre-division factor whatever the PLL clock source is (HSI or HSE)</span><span class="MsoNormal" style="font-size: 10pt; font-family: "Courier New";" lang="EN-US"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Removed field HSEPredivValue from RCC_OscInitTypeDef (replaced by </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">PREDIV field in </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">RCC_PLLInitTypeDef)</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Other F3 products: no change in </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">RCC_OcsInitTypeDef and RCC_PLLInitTypeDef definitions</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Add new definition of RCC_PeriphCLKInitTypeDef<span style=""> </span>to fit STM32F303xE <span style=""> </span>clock selection capabilities (e.g select TIM20
+ clock source)</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Add new defines to select the pre-division factor (RCC_PREDIV_DIVx)</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Add new defines to set TIM20 clock source (RCC_PERIPHCLK_TIM20, RCC_TIM20CLK_HCLK and
+ RCC_TIM20CLK_PLLCLK)</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Add new defnes to set </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">TIM3 & TIM4</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"> clock source (</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">RCC_PERIPHCLK_TIM34</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">, RCC_TIM34CLK_HCLK, RCC_TIM34CLK_PCLK)<br></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Add FMC related macros: __FMC_CLK_ENABLE(), __FMC_CLK_DISABLE(), __FMC_FORCE_RESET() and __FMC_RELEASE_RESET()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Add GPIO port G related macros: __GPIOG_CLK_ENABLE(), __GPIOG_CLK_DISABLE(),
+ __ GPIOG _FORCE_RESET() and __GPIOG _RELEASE_RESET()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Add GPIO port H related macros:_ __GPIOH_CLK_ENABLE(), __GPIOH_CLK_DISABLE(),
+ __FMC_ GPIOH _RESET() and __GPIOH _RELEASE_RESET()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Add SPI4 related macros: <span style=""> </span>__SPI4_CLK_ENABLE(),
+ __SPI4_CLK_DISABLE(), __ SPI4_FORCE_RESET() and __SPI4_RELEASE_RESET()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; line-height: 115%; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">Add TIM20 related macros: __TIM20_CLK_ENABLE(), __TIM20_CLK_DISABLE(),
+__ TIM20_FORCE_RESET() and __TIM20_RELEASE_RESET(), __HAL_RCC_TIM20_CONFIG() , __HAL_RCC_GET_TIM20_SOURCE()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; line-height: 115%; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">Add new macro to set/get the clock source of TIM3 & TIM4: __HAL_RCC_TIM34_CONFIG() and __HAL_RCC_GET_TIM34_SOURCE()<br></span></li></ul></ul><ul style="list-style-type: square;"><li><b><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL SMARTCARD
+</span></b><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">update</span></li><ul><li><span style="font-size: 10pt; line-height: 115%; font-family: "Verdana","sans-serif"; color: windowtext;" lang="EN-US">Change SMARTCARD_AdvFeatureConfig()
+from exported to static private function</span></li></ul><ul><li><span style="font-size: 10pt; color: windowtext;" lang="EN-US"></span><span style="font-size: 10pt; line-height: 115%; font-family: "Verdana","sans-serif"; color: windowtext;" lang="EN-US">TC enabled and TXE disabled at the end of TX in IT
+mode</span></li></ul></ul>
+
+
+
+<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 53.4pt; text-indent: -18pt; line-height: normal;"><span style="font-size: 10pt; font-family: Symbol; color: windowtext;" lang="EN-US"><span style=""><span style="font-family: "Times New Roman"; font-style: normal; font-variant: normal; font-weight: normal; font-size: 7pt; line-height: normal; font-size-adjust: none; font-stretch: normal;"></span></span></span><span style="font-size: 10pt; color: windowtext;" lang="EN-US"></span><span style="font-size: 10pt; color: windowtext;" lang="EN-US"><o:p></o:p></span></p>
+
+<ul style="list-style-type: square;"><li><span style="font-family: Symbol;"></span><span style="" lang="EN-US"><span style=""></span></span><b><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL SMBUS </span></b><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">update</span></li><ul><li><span style="font-size: 10pt; line-height: 115%; font-family: "Verdana","sans-serif"; color: windowtext;" lang="EN-US">Fix wrong State after a PEC failed</span></li><li><span style="font-size: 10pt; line-height: 115%; font-family: "Verdana","sans-serif"; color: windowtext;">Fix slave acknowledge issue</span></li></ul></ul><p class="MsoListParagraphCxSpLast" style="margin: 4.5pt 0cm 4.5pt 53.4pt; text-indent: -18pt; line-height: normal;"><span style="font-size: 10pt; color: windowtext;"></span><span style="font-size: 10pt; color: windowtext;" lang="EN-US"><o:p></o:p></span></p>
+
+<ul style="list-style-type: square;"><li><span style="font-family: Symbol;"></span><span style="" lang="EN-US"><span style=""></span></span><b><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL SPI </span></b><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">update</span></li><ul><li><span style="font-size: 10pt; line-height: 115%; font-family: "Verdana","sans-serif"; color: windowtext;" lang="EN-US">Fix CodeSonar warning: unreachable Call in
+SPI_CloseRxTx_ISR()</span></li></ul></ul><p class="MsoListParagraph" style="margin: 4.5pt 0cm 4.5pt 83.16pt; text-indent: -18pt; line-height: normal;"><span style="font-size: 10pt; font-family: Symbol; color: windowtext;" lang="EN-US"><span style=""><span style="font-family: "Times New Roman"; font-style: normal; font-variant: normal; font-weight: normal; font-size: 7pt; line-height: normal; font-size-adjust: none; font-stretch: normal;"></span></span></span><span style="font-size: 10pt; color: windowtext;" lang="EN-US"><o:p></o:p></span></p>
+
+<ul style="list-style-type: square;"><li><span style="font-family: Symbol;"></span><span style="" lang="EN-US"><span style=""></span></span><b><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL SRAM</span></b><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"> (</span><b><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">STM32F303xE specific</span></b><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">)</span></li><ul><li><span style="font-size: 10pt; line-height: 115%; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">FMC: generic
+firmware to drive SRAM memories mounted as external device</span></li></ul></ul>
+
+
+
+<ul style="list-style-type: square;"><li><span style="font-family: Symbol;"></span><span style="" lang="EN-US"><span style=""></span></span><b><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL TIM </span></b><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">update (for </span><b><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">STM32F303xE</span></b><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">)</span></li><ul><li><span style="font-size: 10pt; line-height: 115%; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">Add
+defines to set TIM20 option register (link from analog watchdog and TIM20 ETR)</span></li></ul></ul><ul style="list-style-type: square;"><li><b><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL UART </span></b><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">update</span></li><ul><li><span style="font-size: 10pt; line-height: 115%; font-family: "Verdana","sans-serif"; color: windowtext;" lang="EN-US">TC enabled and TXE disabled at the end of TX in IT
+mode</span></li></ul></ul><ul style="list-style-type: square;"><li><b><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL USART </span></b><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">update</span></li><ul><li><span style="font-size: 10pt; line-height: 115%; font-family: "Verdana","sans-serif"; color: windowtext;" lang="EN-US">TC enabled and TXE disabled at the end of TX in IT
+mode</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.1
+/ 18-June-2014<o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes</span></u></b></p>
+<ul style="margin-top: 0cm; list-style-type: square;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
+
+
+
+
+
+
+
+<p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL generic</span> update<br></span></p><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Fix flag clear procedure: use atomic write operation </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">"=" </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">instead of ready-modify-write operation "|=" or "&="</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Fix
+on Timeout management, Timeout value set to 0 passed to API
+automatically exits the function after checking the flag without any
+wait.</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add
+new macro __HAL_RESET_HANDLE_STATE to reset a given handle state.</span></li></ul></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
+
+
+
+
+
+
+
+<p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL ADC</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Rename defines:</span></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">ADC_EXTERNALTRIGCONV_Ext_IT11 to ADC_EXTERNALTRIGCONV_EXT_IT11</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">ADC_EXTERNALTRIGCONV_Ext_IT12 to ADC_EXTERNALTRIGCONV_EXT_IT12</span></li></ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Fix define ADC_SOFTWARE_START</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Update external trigger defines to remove HRTIM triggers for STM32F328xx and TIM8 triggers for STM32F302xC</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add ADC1_2_EXTERNALTRIG_T4_CC4 for </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">STM32F303x8 and </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">STM32F328xx</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL CEC</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Process no more locked during the transmission in interrupt mode.</span> </li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL COMP</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Fix on 32-bit register COMP CSR accesses for </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">STM32F373xC and STM32F378xx devices.</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add new defines </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">for STM32F373xC and STM32F378xx comparators: </span></li></ul></ul><div style="margin-left: 120px;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-style: italic;">COMP_OUTPUT_TIM3IC1,
+COMP_OUTPUT_TIM3OCREFCLR, COMP_OUTPUT_TIM2IC4</span> and
+<span style="font-style: italic;">COMP_OUTPUT_TIM2OCREFCLR </span></span><br></div><div style="margin-left: 80px;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">instead of previous defines </span><br></div><div style="font-style: italic; margin-left: 120px;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">COMP_OUTPUT_COMP1_TIM3IC1,
+COMP_OUTPUT_COMP1_TIM3OCREFCLR, COMP_OUTPUT_COMP1_TIM2IC4,
+COMP_OUTPUT_COMP1_TIM2OCREFCLR, <br></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">COMP_OUTPUT_COMP2_TIM3IC1, COMP_OUTPUT_COMP2_TIM3OCREFCLR, COMP_OUTPUT_COMP2_TIM2IC4, COMP_OUTPUT_COMP2_TIM2OCREFCLR.</span></div><ul style="margin-top: 0cm; list-style-type: square;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL DMA</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Fix in <span style="font-style: italic;">HAL_DMA_PollForTransfer()</span> to set error code <span style="font-style: italic;">HAL_DMA_ERROR_TE </span>in case of <span style="font-style: italic;">HAL_ERROR</span> status</span> </li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL GPIO</span> update<br></span></p><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Fix <span style="font-style: italic;">GPIO_AF5_SPI1</span> define instead of </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">GPIO_AF5_SPI1</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"> for STM32F303x8 device.</span> </li></ul><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;"></span></span></li></ul><ul style="margin-top: 0cm; list-style-type: square;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
+
+
+
+
+
+
+
+<p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL HRTIM</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HRTIM peripheral not available for STM32F328xx device.</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Fix macros __HAL_HRTIM_CLEAR_FLAG, __HAL_HRTIM_MASTER_CLEAR_FLAG and __HAL_HRTIM_TIMER_CLEAR_FLAG</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
+
+
+
+
+
+
+
+<p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL I2C</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add
+management of NACK event in Master transmitter mode and Slave
+transmitter/receiver modes (only in polling mode), in that case the
+current transfer is stopped.</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL IRDA</span> update<br></span></p><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add new enum typedef <span style="font-style: italic;">IRDA_ClockSourceTypeDef</span></span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add new macro __HAL_IRDA_GETCLOCKSOURCE</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Change in <span style="font-style: italic;">HAL_IRDA_Transmit_IT()</span> to enable IRDA_IT_TXE instead of IRDA_IT_TC.</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Process no more locked during the transmission in interrupt mode.</span></li></ul></li></ul><ul style="margin-top: 0cm; list-style-type: square;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
+
+
+
+
+
+
+
+<p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL OPAMP</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__SYSCFG_CLK_ENABLE() is now handled internally in HAL_OPAMP_Init() and no more in user HAL_OPAMP_MspInit().</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
+ <p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL PCD </span>update</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></p>
+ </li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
+ <p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add new macro <span style="font-style: italic;">__HAL_USB_EXTI_GENERATE_SWIT</span></span></p>
+ </li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL PWR</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Fix in <span style="font-style: italic;">HAL_PWR_EnterSTANDBYMode()</span> to not clear Wakeup flag (WUF), which need to be cleared at application level before to call this function</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL RCC</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Change for </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">STM32F303x8, STM32F334x8 and STM32F328xx devices:</span></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add missing macro __DAC2_FORCE_RESET</span></li></ul><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Rename <span style="font-style: italic;">RCC_USART1CLKSOURCE_PCLK2</span> into <span style="font-style: italic;">RCC_USART1CLKSOURCE_PCLK1</span></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></li></ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Remove HRTIM1 peripheral and clocking macros for </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">STM32F328xx device.</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Fix HSI Calibration issue when selected as SYSCLK <br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
+
+
+
+
+
+
+
+<p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL SMARTCARD</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Change in <span style="font-style: italic;">HAL_SMARTCARD_Transmit_IT()</span> to enable SMARTCARD_IT_TXE instead of SMARTCARD_IT_TC.</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Process no more locked during the transmission in interrupt mode.</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL SMBUS</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Fix Slave acknowledge issue: Slave should ack each bit and so stretch the line till the bit is not ack</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL TIM</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Fix macro __HAL_TIM_PRESCALER</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL TSC</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Fix define <span style="font-style: italic;">TSC_ACQ_MODE_SYNCHRO</span></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
+
+
+
+
+
+
+
+<p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL UART</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Change in <span style="font-style: italic;">HAL_LIN_Init()</span> parameter BreakDetectLength to uint32_t</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Change in <span style="font-style: italic;">HAL_UART_Transmit_IT()</span> to enable UART_IT_TXE instead of UART_IT_TC.</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Process no more locked during the transmission in interrupt mode.</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
+
+
+
+
+
+
+
+<p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL USART</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Change <span style="font-style: italic;">USART_InitTypeDef</span> fields to uint32_t type</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Rename __USART_ENABLE and __USART_DISABLE macros to respectively </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_USART_ENABLE and __HAL_USART_DISABLE</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Change in <span style="font-style: italic;">HAL_USART_Transmit_IT()</span> to enable USART_IT_TXE instead of USART_IT_TC.</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Process no more locked during the transmission in interrupt mode.</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Change in <span style="font-style: italic;">HAL_USART_TransmitReceive_DMA()</span> to manage DMA half transfer mode<br></span></li></ul></ul><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; font-weight: bold;"> </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; font-weight: bold;"></span><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0
+/ 06-May-2014<o:p></o:p></span></h3>
+<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes</span></u></b></p>
+<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">First official
+release of STM32F3xx HAL drivers for </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; font-weight: bold;">STM32F301x6/x8,
+</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; font-weight: bold;">STM32F302x6/x8, </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; font-weight: bold;">STM32F302xB/xC,
+</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; font-weight: bold;">STM32F303x6/x8, </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; font-weight: bold;"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; font-weight: bold;">STM32F373xB/xC,
+</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; font-weight: bold;"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; font-weight: bold;">STM32F334x4/x6/x8</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; font-weight: bold;">, </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; font-weight: bold;">STM32F318xx, STM32F328xx, STM32F358xx and STM32F378xx
+</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; font-weight: bold;">devices.</span></li></ul><h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2><div style="text-align: justify;"><font size="-1"><span style="font-family: "Verdana","sans-serif";">
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are
+met:</span><br>
+ </font>
+ <ol><li><font size="-1"><span style="font-family: "Verdana","sans-serif";">Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.</span><span style="font-family: "Verdana","sans-serif";"></span></font></li><li><font size="-1"><span style="font-family: "Verdana","sans-serif";">Redistributions
+in binary form must reproduce the above copyright notice, this list of
+conditions and the following disclaimer in </span><span style="font-family: "Verdana","sans-serif";">the documentation and/or other materials provided with the distribution.</span><span style="font-family: "Verdana","sans-serif";"></span></font></li><li><font size="-1"><span style="font-family: "Verdana","sans-serif";">Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived </span><br>
+ </font>
+ </li></ol>
+ <font size="-1"><span style="font-family: "Verdana","sans-serif";"> from this software without specific prior written permission.</span><br>
+ <span style="font-family: "Verdana","sans-serif";"></span><br>
+ <span style="font-family: "Verdana","sans-serif";">THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED</span><span style="font-family: "Verdana","sans-serif";"> WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A </span><span style="font-family: "Verdana","sans-serif";">PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY </span><span style="font-family: "Verdana","sans-serif";">DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, </span><span style="font-family: "Verdana","sans-serif";">PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER</span><span style="font-family: "Verdana","sans-serif";"> CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR </span><span style="font-family: "Verdana","sans-serif";">OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.</span></font>
+
+ </div><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;"></span>
+<div class="MsoNormal" style="text-align: center; margin-left: 40px;" align="center"><span style="color: black;">
+<hr align="center" size="2" width="100%"></span></div>
+<p class="MsoNormal" style="margin: 4.5pt 0in 4.5pt 0.6634in; text-align: center;" align="center"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;">For
+complete documentation on </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">STM32<span style="color: black;"> Microcontrollers visit </span><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/family/141.jsp" target="_blank">www.st.com/STM32</a></span></u></span><span style="color: black;"><o:p></o:p></span></p>
+</td>
+</tr>
+</tbody>
+</table>
+<p style="margin-left: 40px;" class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>
+</td>
+</tr>
+</tbody>
+</table>
+</div>
+<p class="MsoNormal"><o:p> </o:p></p>
+</div>
+</body></html>
\ No newline at end of file
diff --git a/Src/Legacy/stm32f3xx_hal_can.c b/Src/Legacy/stm32f3xx_hal_can.c
new file mode 100644
index 0000000..ac192d5
--- /dev/null
+++ b/Src/Legacy/stm32f3xx_hal_can.c
@@ -0,0 +1,1700 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_can.c
+ * @author MCD Application Team
+ * @brief CAN HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Controller Area Network (CAN) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State and Error functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Enable the CAN controller interface clock using __HAL_RCC_CAN1_CLK_ENABLE();
+
+ (#) CAN pins configuration
+ (++) Enable the clock for the CAN GPIOs using the following function:
+ __HAL_RCC_GPIOx_CLK_ENABLE();
+ (++) Connect and configure the involved CAN pins to AF9 using the
+ following function HAL_GPIO_Init();
+
+ (#) Initialise and configure the CAN using HAL_CAN_Init() function.
+
+ (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function.
+
+ (#) Or transmit the desired CAN frame using HAL_CAN_Transmit_IT() function.
+
+ (#) Receive a CAN frame using HAL_CAN_Receive() function.
+
+ (#) Or receive a CAN frame using HAL_CAN_Receive_IT() function.
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Start the CAN peripheral transmission and wait the end of this operation
+ using HAL_CAN_Transmit(), at this stage user can specify the value of timeout
+ according to his end application
+ (+) Start the CAN peripheral reception and wait the end of this operation
+ using HAL_CAN_Receive(), at this stage user can specify the value of timeout
+ according to his end application
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT()
+ (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT()
+ (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine
+ (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_CAN_TxCpltCallback
+ (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_CAN_ErrorCallback
+
+ *** CAN HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in CAN HAL driver.
+
+ (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts
+ (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts
+ (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled
+ (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags
+ (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status
+
+ [..]
+ (@) You can refer to the CAN HAL driver header file for more useful macros
+
+ @endverbatim
+
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup CAN CAN
+ * @brief CAN driver modules
+ * @{
+ */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F302x8) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup CAN_Private_Constants CAN Private Constants
+ * @{
+ */
+#define CAN_TIMEOUT_VALUE 10U
+/**
+ * @}
+ */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup CAN_Private_Functions CAN Private Functions
+ * @{
+ */
+static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber);
+static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup CAN_Exported_Functions CAN Exported Functions
+ * @{
+ */
+
+/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de-initialization functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize and configure the CAN.
+ (+) De-initialize the CAN.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the CAN peripheral according to the specified
+ * parameters in the CAN_InitStruct.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
+{
+ uint32_t status = CAN_INITSTATUS_FAILED; /* Default init status */
+ uint32_t tickstart = 0U;
+
+ /* Check CAN handle */
+ if(hcan == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP));
+ assert_param(IS_CAN_MODE(hcan->Init.Mode));
+ assert_param(IS_CAN_SJW(hcan->Init.SJW));
+ assert_param(IS_CAN_BS1(hcan->Init.BS1));
+ assert_param(IS_CAN_BS2(hcan->Init.BS2));
+ assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));
+
+ if(hcan->State == HAL_CAN_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hcan->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware */
+ HAL_CAN_MspInit(hcan);
+ }
+
+ /* Initialize the CAN state*/
+ hcan->State = HAL_CAN_STATE_BUSY;
+
+ /* Exit from sleep mode */
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
+
+ /* Request initialisation */
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait the acknowledge */
+ while(HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_INAK))
+ {
+ if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
+ {
+ hcan->State= HAL_CAN_STATE_TIMEOUT;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Check acknowledge */
+ if (HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK))
+ {
+ /* Set the time triggered communication mode */
+ if (hcan->Init.TTCM == ENABLE)
+ {
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
+ }
+ else
+ {
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
+ }
+
+ /* Set the automatic bus-off management */
+ if (hcan->Init.ABOM == ENABLE)
+ {
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
+ }
+ else
+ {
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
+ }
+
+ /* Set the automatic wake-up mode */
+ if (hcan->Init.AWUM == ENABLE)
+ {
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
+ }
+ else
+ {
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
+ }
+
+ /* Set the no automatic retransmission */
+ if (hcan->Init.NART == ENABLE)
+ {
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_NART);
+ }
+ else
+ {
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART);
+ }
+
+ /* Set the receive FIFO locked mode */
+ if (hcan->Init.RFLM == ENABLE)
+ {
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
+ }
+ else
+ {
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
+ }
+
+ /* Set the transmit FIFO priority */
+ if (hcan->Init.TXFP == ENABLE)
+ {
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
+ }
+ else
+ {
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
+ }
+
+ /* Set the bit timing register */
+ WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode |
+ hcan->Init.SJW |
+ hcan->Init.BS1 |
+ hcan->Init.BS2 |
+ (hcan->Init.Prescaler - 1U) ));
+
+ /* Request leave initialisation */
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait the acknowledge */
+ while(HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK))
+ {
+ if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
+ {
+ hcan->State= HAL_CAN_STATE_TIMEOUT;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Check acknowledged */
+ if(HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_INAK))
+ {
+ status = CAN_INITSTATUS_SUCCESS;
+ }
+ }
+
+ if(status == CAN_INITSTATUS_SUCCESS)
+ {
+ /* Set CAN error code to none */
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+
+ /* Initialize the CAN state */
+ hcan->State = HAL_CAN_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Initialize the CAN state */
+ hcan->State = HAL_CAN_STATE_ERROR;
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Configures the CAN reception filter according to the specified
+ * parameters in the CAN_FilterInitStruct.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param sFilterConfig pointer to a CAN_FilterConfTypeDef structure that
+ * contains the filter configuration information.
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig)
+{
+ uint32_t filternbrbitpos = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber));
+ assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
+ assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));
+ assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));
+ assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));
+
+ filternbrbitpos = (1U) << sFilterConfig->FilterNumber;
+
+ /* Initialisation mode for the filter */
+ SET_BIT(hcan->Instance->FMR, CAN_FMR_FINIT);
+
+ /* Filter Deactivation */
+ CLEAR_BIT(hcan->Instance->FA1R, filternbrbitpos);
+
+ /* Filter Scale */
+ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
+ {
+ /* 16-bit scale for the filter */
+ CLEAR_BIT(hcan->Instance->FS1R, filternbrbitpos);
+
+ /* First 16-bit identifier and First 16-bit mask */
+ /* Or First 16-bit identifier and Second 16-bit identifier */
+ hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
+
+ /* Second 16-bit identifier and Second 16-bit mask */
+ /* Or Third 16-bit identifier and Fourth 16-bit identifier */
+ hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh);
+ }
+
+ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
+ {
+ /* 32-bit scale for the filter */
+ SET_BIT(hcan->Instance->FS1R, filternbrbitpos);
+
+ /* 32-bit identifier or First 32-bit identifier */
+ hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
+
+ /* 32-bit mask or Second 32-bit identifier */
+ hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow);
+ }
+
+ /* Filter Mode */
+ if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
+ {
+ /*Id/Mask mode for the filter*/
+ CLEAR_BIT(hcan->Instance->FM1R, filternbrbitpos);
+ }
+ else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
+ {
+ /*Identifier list mode for the filter*/
+ SET_BIT(hcan->Instance->FM1R, filternbrbitpos);
+ }
+
+ /* Filter FIFO assignment */
+ if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
+ {
+ /* FIFO 0 assignation for the filter */
+ CLEAR_BIT(hcan->Instance->FFA1R, filternbrbitpos);
+ }
+ else
+ {
+ /* FIFO 1 assignation for the filter */
+ SET_BIT(hcan->Instance->FFA1R, filternbrbitpos);
+ }
+
+ /* Filter activation */
+ if (sFilterConfig->FilterActivation == ENABLE)
+ {
+ SET_BIT(hcan->Instance->FA1R, filternbrbitpos);
+ }
+
+ /* Leave the initialisation mode for the filter */
+ CLEAR_BIT(hcan->Instance->FMR, ((uint32_t)CAN_FMR_FINIT));
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Deinitializes the CANx peripheral registers to their default reset values.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan)
+{
+ /* Check CAN handle */
+ if(hcan == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY;
+
+ /* DeInit the low level hardware */
+ HAL_CAN_MspDeInit(hcan);
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CAN MSP.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the CAN MSP.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Exported_Functions_Group2 Input and Output operation functions
+ * @brief IO operation functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Transmit a CAN frame message.
+ (+) Receive a CAN frame message.
+ (+) Enter CAN peripheral in sleep mode.
+ (+) Wake up the CAN peripheral from sleep mode.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initiates and transmits a CAN frame message.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param Timeout Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
+{
+ uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
+ uint32_t tickstart = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
+ assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
+ assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
+
+ if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
+ ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
+ ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
+ {
+ /* Process locked */
+ __HAL_LOCK(hcan);
+
+ /* Change CAN state */
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_READY */
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ break;
+ }
+
+ /* Select one empty transmit mailbox */
+ if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0))
+ {
+ transmitmailbox = CAN_TXMAILBOX_0;
+ }
+ else if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1))
+ {
+ transmitmailbox = CAN_TXMAILBOX_1;
+ }
+ else
+ {
+ transmitmailbox = CAN_TXMAILBOX_2;
+ }
+
+ /* Set up the Id */
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
+ if (hcan->pTxMsg->IDE == CAN_ID_STD)
+ {
+ assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_Pos) | \
+ hcan->pTxMsg->RTR);
+ }
+ else
+ {
+ assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_Pos) | \
+ hcan->pTxMsg->IDE | \
+ hcan->pTxMsg->RTR);
+ }
+
+ /* Set up the DLC */
+ hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU;
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= 0xFFFFFFF0U;
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
+
+ /* Set up the data field */
+ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3] << CAN_TDL0R_DATA3_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[2] << CAN_TDL0R_DATA2_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[1] << CAN_TDL0R_DATA1_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[0] << CAN_TDL0R_DATA0_Pos));
+ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7] << CAN_TDL0R_DATA3_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[6] << CAN_TDL0R_DATA2_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[5] << CAN_TDL0R_DATA1_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[4] << CAN_TDL0R_DATA0_Pos));
+
+ /* Request transmission */
+ SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Check End of transmission flag */
+ while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox)))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ hcan->State = HAL_CAN_STATE_TIMEOUT;
+
+ /* Cancel transmission */
+ __HAL_CAN_CANCEL_TRANSMIT(hcan, transmitmailbox);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Change CAN state */
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_BUSY_TX */
+ hcan->State = HAL_CAN_STATE_READY;
+ break;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_ERROR;
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Initiates and transmits a CAN frame message.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
+{
+ uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
+ assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
+ assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
+
+ if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
+ ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
+ ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcan);
+
+ /* Select one empty transmit mailbox */
+ if(HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0))
+ {
+ transmitmailbox = CAN_TXMAILBOX_0;
+ }
+ else if(HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1))
+ {
+ transmitmailbox = CAN_TXMAILBOX_1;
+ }
+ else
+ {
+ transmitmailbox = CAN_TXMAILBOX_2;
+ }
+
+ /* Set up the Id */
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
+ if(hcan->pTxMsg->IDE == CAN_ID_STD)
+ {
+ assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_Pos) | \
+ hcan->pTxMsg->RTR);
+ }
+ else
+ {
+ assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_Pos) | \
+ hcan->pTxMsg->IDE | \
+ hcan->pTxMsg->RTR);
+ }
+
+ /* Set up the DLC */
+ hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU;
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= 0xFFFFFFF0U;
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
+
+ /* Set up the data field */
+ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3] << CAN_TDL0R_DATA3_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[2] << CAN_TDL0R_DATA2_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[1] << CAN_TDL0R_DATA1_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[0] << CAN_TDL0R_DATA0_Pos));
+ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7] << CAN_TDL0R_DATA3_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[6] << CAN_TDL0R_DATA2_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[5] << CAN_TDL0R_DATA1_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[4] << CAN_TDL0R_DATA0_Pos));
+
+ /* Change CAN state */
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_READY */
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ break;
+ }
+
+ /* Set CAN error code to none */
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Request transmission */
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
+
+ /* Enable interrupts: */
+ /* - Enable Error warning Interrupt */
+ /* - Enable Error passive Interrupt */
+ /* - Enable Bus-off Interrupt */
+ /* - Enable Last error code Interrupt */
+ /* - Enable Error Interrupt */
+ /* - Enable Transmit mailbox empty Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
+ CAN_IT_EPV |
+ CAN_IT_BOF |
+ CAN_IT_LEC |
+ CAN_IT_ERR |
+ CAN_IT_TME );
+ }
+ else
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_ERROR;
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Receives a correct CAN frame.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param FIFONumber FIFO number.
+ * @param Timeout Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+ CanRxMsgTypeDef* pRxMsg = NULL;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_FIFO(FIFONumber));
+
+ /* Process locked */
+ __HAL_LOCK(hcan);
+
+ /* Check if CAN state is not busy for RX FIFO0 */
+ if ((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ return HAL_BUSY;
+ }
+
+ /* Check if CAN state is not busy for RX FIFO1 */
+ if ((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ return HAL_BUSY;
+ }
+
+ /* Change CAN state */
+ if (FIFONumber == CAN_FIFO0)
+ {
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_READY */
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
+ break;
+ }
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_READY */
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
+ break;
+ }
+ }
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Check pending message */
+ while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0U)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ hcan->State = HAL_CAN_STATE_TIMEOUT;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Set RxMsg pointer */
+ if(FIFONumber == CAN_FIFO0)
+ {
+ pRxMsg = hcan->pRxMsg;
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ pRxMsg = hcan->pRx1Msg;
+ }
+
+ /* Get the Id */
+ pRxMsg->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+ if (pRxMsg->IDE == CAN_ID_STD)
+ {
+ pRxMsg->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_TI0R_STID_Pos;
+ }
+ else
+ {
+ pRxMsg->ExtId = (0xFFFFFFF8U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_RI0R_EXID_Pos;
+ }
+ pRxMsg->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_RI0R_RTR_Pos;
+ /* Get the DLC */
+ pRxMsg->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR) >> CAN_RDT0R_DLC_Pos;
+ /* Get the FMI */
+ pRxMsg->FMI = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR) >> CAN_RDT0R_FMI_Pos;
+ /* Get the FIFONumber */
+ pRxMsg->FIFONumber = FIFONumber;
+ /* Get the data field */
+ pRxMsg->Data[0] = (CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA0_Pos;
+ pRxMsg->Data[1] = (CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA1_Pos;
+ pRxMsg->Data[2] = (CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA2_Pos;
+ pRxMsg->Data[3] = (CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA3_Pos;
+ pRxMsg->Data[4] = (CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA4_Pos;
+ pRxMsg->Data[5] = (CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA5_Pos;
+ pRxMsg->Data[6] = (CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA6_Pos;
+ pRxMsg->Data[7] = (CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA7_Pos;
+
+ /* Release the FIFO */
+ if(FIFONumber == CAN_FIFO0)
+ {
+ /* Release FIFO0 */
+ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ /* Release FIFO1 */
+ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
+ }
+
+ /* Change CAN state */
+ if (FIFONumber == CAN_FIFO0)
+ {
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+ break;
+ default: /* HAL_CAN_STATE_BUSY_RX0 */
+ hcan->State = HAL_CAN_STATE_READY;
+ break;
+ }
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+ break;
+ default: /* HAL_CAN_STATE_BUSY_RX1 */
+ hcan->State = HAL_CAN_STATE_READY;
+ break;
+ }
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Receives a correct CAN frame.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param FIFONumber FIFO number.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_FIFO(FIFONumber));
+
+ /* Process locked */
+ __HAL_LOCK(hcan);
+
+ /* Check if CAN state is not busy for RX FIFO0 */
+ if ((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ return HAL_BUSY;
+ }
+
+ /* Check if CAN state is not busy for RX FIFO1 */
+ if ((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ return HAL_BUSY;
+ }
+
+ /* Change CAN state */
+ if (FIFONumber == CAN_FIFO0)
+ {
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_READY */
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
+ break;
+ }
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_READY */
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
+ break;
+ }
+ }
+
+ /* Set CAN error code to none */
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+
+ /* Enable interrupts: */
+ /* - Enable Error warning Interrupt */
+ /* - Enable Error passive Interrupt */
+ /* - Enable Bus-off Interrupt */
+ /* - Enable Last error code Interrupt */
+ /* - Enable Error Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
+ CAN_IT_EPV |
+ CAN_IT_BOF |
+ CAN_IT_LEC |
+ CAN_IT_ERR);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ if(FIFONumber == CAN_FIFO0)
+ {
+ /* Enable FIFO 0 overrun and message pending Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0);
+ }
+ else
+ {
+ /* Enable FIFO 1 overrun and message pending Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Enters the Sleep (low power) mode.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)
+{
+ uint32_t tickstart = 0U;
+
+ /* Process locked */
+ __HAL_LOCK(hcan);
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY;
+
+ /* Request Sleep mode */
+ MODIFY_REG(hcan->Instance->MCR,
+ CAN_MCR_INRQ ,
+ CAN_MCR_SLEEP );
+
+ /* Sleep mode status */
+ if (HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_SLAK) ||
+ HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK) )
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait the acknowledge */
+ while (HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_SLAK) ||
+ HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK) )
+ {
+ if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
+ {
+ hcan->State = HAL_CAN_STATE_TIMEOUT;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral
+ * is in the normal mode.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan)
+{
+ uint32_t tickstart = 0U;
+
+ /* Process locked */
+ __HAL_LOCK(hcan);
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY;
+
+ /* Wake up request */
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Sleep mode status */
+ while(HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_SLAK))
+ {
+ if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
+ {
+ hcan->State= HAL_CAN_STATE_TIMEOUT;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ if(HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_SLAK))
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Handles CAN interrupt request
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
+{
+ uint32_t errorcode = HAL_CAN_ERROR_NONE;
+
+ /* Check Overrun flag for FIFO0 */
+ if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV0)) &&
+ (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV0)))
+ {
+ /* Set CAN error code to FOV0 error */
+ errorcode |= HAL_CAN_ERROR_FOV0;
+
+ /* Clear FIFO0 Overrun Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0);
+ }
+
+ /* Check Overrun flag for FIFO1 */
+ if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV1)) &&
+ (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV1)))
+ {
+ /* Set CAN error code to FOV1 error */
+ errorcode |= HAL_CAN_ERROR_FOV1;
+
+ /* Clear FIFO1 Overrun Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1);
+ }
+
+ /* Check End of transmission flag */
+ if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME))
+ {
+ /* Check Transmit request completion status */
+ if((__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0)) ||
+ (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1)) ||
+ (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2)))
+ {
+ /* Check Transmit success */
+ if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK0)) ||
+ (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK1)) ||
+ (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK2)))
+ {
+ /* Call transmit function */
+ CAN_Transmit_IT(hcan);
+ }
+ else /* Transmit failure */
+ {
+ /* Set CAN error code to TXFAIL error */
+ errorcode |= HAL_CAN_ERROR_TXFAIL;
+ }
+
+ /* Clear transmission status flags (RQCPx and TXOKx) */
+ SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP0 | CAN_TSR_RQCP1 | CAN_TSR_RQCP2 | \
+ CAN_FLAG_TXOK0 | CAN_FLAG_TXOK1 | CAN_FLAG_TXOK2);
+ }
+ }
+
+ /* Check End of reception flag for FIFO0 */
+ if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0)) &&
+ (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0) != 0U))
+ {
+ /* Call receive function */
+ CAN_Receive_IT(hcan, CAN_FIFO0);
+ }
+
+ /* Check End of reception flag for FIFO1 */
+ if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1)) &&
+ (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1) != 0U))
+ {
+ /* Call receive function */
+ CAN_Receive_IT(hcan, CAN_FIFO1);
+ }
+
+ /* Set error code in handle */
+ hcan->ErrorCode |= errorcode;
+
+ /* Check Error Warning Flag */
+ if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG)) &&
+ (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG)) &&
+ (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
+ {
+ /* Set CAN error code to EWG error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_EWG;
+ /* No need for clear of Error Warning Flag as read-only */
+ }
+
+ /* Check Error Passive Flag */
+ if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV)) &&
+ (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV)) &&
+ (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
+ {
+ /* Set CAN error code to EPV error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_EPV;
+ /* No need for clear of Error Passive Flag as read-only */
+ }
+
+ /* Check Bus-Off Flag */
+ if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF)) &&
+ (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF)) &&
+ (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
+ {
+ /* Set CAN error code to BOF error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_BOF;
+ /* No need for clear of Bus-Off Flag as read-only */
+ }
+
+ /* Check Last error code Flag */
+ if((!HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC)) &&
+ (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC)) &&
+ (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
+ {
+ switch(hcan->Instance->ESR & CAN_ESR_LEC)
+ {
+ case(CAN_ESR_LEC_0):
+ /* Set CAN error code to STF error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_STF;
+ break;
+ case(CAN_ESR_LEC_1):
+ /* Set CAN error code to FOR error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_FOR;
+ break;
+ case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0):
+ /* Set CAN error code to ACK error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_ACK;
+ break;
+ case(CAN_ESR_LEC_2):
+ /* Set CAN error code to BR error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_BR;
+ break;
+ case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0):
+ /* Set CAN error code to BD error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_BD;
+ break;
+ case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
+ /* Set CAN error code to CRC error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_CRC;
+ break;
+ default:
+ break;
+ }
+
+ /* Clear Last error code Flag */
+ CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC);
+ }
+
+ /* Call the Error call Back in case of Errors */
+ if(hcan->ErrorCode != HAL_CAN_ERROR_NONE)
+ {
+ /* Clear ERRI Flag */
+ SET_BIT(hcan->Instance->MSR, CAN_MSR_ERRI);
+
+ /* Set the CAN state ready to be able to start again the process */
+ hcan->State = HAL_CAN_STATE_READY;
+
+ /* Disable interrupts: */
+ /* - Disable Error warning Interrupt */
+ /* - Disable Error passive Interrupt */
+ /* - Disable Bus-off Interrupt */
+ /* - Disable Last error code Interrupt */
+ /* - Disable Error Interrupt */
+ /* - Disable FIFO 0 message pending Interrupt */
+ /* - Disable FIFO 0 Overrun Interrupt */
+ /* - Disable FIFO 1 message pending Interrupt */
+ /* - Disable FIFO 1 Overrun Interrupt */
+ /* - Disable Transmit mailbox empty Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
+ CAN_IT_EPV |
+ CAN_IT_BOF |
+ CAN_IT_LEC |
+ CAN_IT_ERR |
+ CAN_IT_FMP0|
+ CAN_IT_FOV0|
+ CAN_IT_FMP1|
+ CAN_IT_FOV1|
+ CAN_IT_TME );
+
+ /* Call Error callback function */
+ HAL_CAN_ErrorCallback(hcan);
+ }
+}
+
+/**
+ * @brief Transmission complete callback in non blocking mode
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Transmission complete callback in non blocking mode
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_RxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Error CAN callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
+ * @brief CAN Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State and Error functions #####
+ ==============================================================================
+ [..]
+ This subsection provides functions allowing to :
+ (+) Check the CAN state.
+ (+) Check CAN Errors detected during interrupt process
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief return the CAN state
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL state
+ */
+HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan)
+{
+ /* Return CAN state */
+ return hcan->State;
+}
+
+/**
+ * @brief Return the CAN error code
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval CAN Error Code
+ */
+uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)
+{
+ return hcan->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Private_Functions CAN Private Functions
+ * @brief CAN Frame message Rx/Tx functions
+ *
+ * @{
+ */
+
+/**
+ * @brief Initiates and transmits a CAN frame message.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
+{
+ /* Disable Transmit mailbox empty Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME);
+
+ if(hcan->State == HAL_CAN_STATE_BUSY_TX)
+ {
+ /* Disable interrupts: */
+ /* - Disable Error warning Interrupt */
+ /* - Disable Error passive Interrupt */
+ /* - Disable Bus-off Interrupt */
+ /* - Disable Last error code Interrupt */
+ /* - Disable Error Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
+ CAN_IT_EPV |
+ CAN_IT_BOF |
+ CAN_IT_LEC |
+ CAN_IT_ERR );
+ }
+
+ /* Change CAN state */
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_BUSY_TX */
+ hcan->State = HAL_CAN_STATE_READY;
+ break;
+ }
+
+ /* Transmission complete callback */
+ HAL_CAN_TxCpltCallback(hcan);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Receives a correct CAN frame.
+ * @param hcan Pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param FIFONumber Specify the FIFO number
+ * @retval HAL status
+ * @retval None
+ */
+static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
+{
+ CanRxMsgTypeDef* pRxMsg = NULL;
+
+ /* Set RxMsg pointer */
+ if(FIFONumber == CAN_FIFO0)
+ {
+ pRxMsg = hcan->pRxMsg;
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ pRxMsg = hcan->pRx1Msg;
+ }
+
+ /* Get the Id */
+ pRxMsg->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+ if (pRxMsg->IDE == CAN_ID_STD)
+ {
+ pRxMsg->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_TI0R_STID_Pos;
+ }
+ else
+ {
+ pRxMsg->ExtId = (0xFFFFFFF8U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_RI0R_EXID_Pos;
+ }
+ pRxMsg->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_RI0R_RTR_Pos;
+ /* Get the DLC */
+ pRxMsg->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR) >> CAN_RDT0R_DLC_Pos;
+ /* Get the FMI */
+ pRxMsg->FMI = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR) >> CAN_RDT0R_FMI_Pos;
+ /* Get the FIFONumber */
+ pRxMsg->FIFONumber = FIFONumber;
+ /* Get the data field */
+ pRxMsg->Data[0] = (CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA0_Pos;
+ pRxMsg->Data[1] = (CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA1_Pos;
+ pRxMsg->Data[2] = (CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA2_Pos;
+ pRxMsg->Data[3] = (CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA3_Pos;
+ pRxMsg->Data[4] = (CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA4_Pos;
+ pRxMsg->Data[5] = (CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA5_Pos;
+ pRxMsg->Data[6] = (CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA6_Pos;
+ pRxMsg->Data[7] = (CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA7_Pos;
+
+ /* Release the FIFO */
+ /* Release FIFO0 */
+ if (FIFONumber == CAN_FIFO0)
+ {
+ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
+
+ /* Disable FIFO 0 overrun and message pending Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0);
+ }
+ /* Release FIFO1 */
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
+
+ /* Disable FIFO 1 overrun and message pending Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1);
+ }
+
+ if((hcan->State == HAL_CAN_STATE_BUSY_RX0) || (hcan->State == HAL_CAN_STATE_BUSY_RX1))
+ {
+ /* Disable interrupts: */
+ /* - Disable Error warning Interrupt */
+ /* - Disable Error passive Interrupt */
+ /* - Disable Bus-off Interrupt */
+ /* - Disable Last error code Interrupt */
+ /* - Disable Error Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
+ CAN_IT_EPV |
+ CAN_IT_BOF |
+ CAN_IT_LEC |
+ CAN_IT_ERR );
+ }
+
+ /* Change CAN state */
+ if (FIFONumber == CAN_FIFO0)
+ {
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+ break;
+ default: /* HAL_CAN_STATE_BUSY_RX0 */
+ hcan->State = HAL_CAN_STATE_READY;
+ break;
+ }
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+ break;
+ default: /* HAL_CAN_STATE_BUSY_RX1 */
+ hcan->State = HAL_CAN_STATE_READY;
+ break;
+ }
+ }
+
+ /* Receive complete callback */
+ HAL_CAN_RxCpltCallback(hcan);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F302x8 || */
+ /* STM32F373xC || STM32F378xx */
+
+#endif /* HAL_CAN_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal.c b/Src/stm32f3xx_hal.c
new file mode 100644
index 0000000..56697d7
--- /dev/null
+++ b/Src/stm32f3xx_hal.c
@@ -0,0 +1,535 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal.c
+ * @author MCD Application Team
+ * @brief HAL module driver.
+ * This is the common part of the HAL initialization
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The common HAL driver contains a set of generic and common APIs that can be
+ used by the PPP peripheral drivers and the user to start using the HAL.
+ [..]
+ The HAL contains two APIs categories:
+ (+) HAL Initialization and de-initialization functions
+ (+) HAL Control functions
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup HAL HAL
+ * @brief HAL module driver.
+ * @{
+ */
+
+#ifdef HAL_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup HAL_Private Constants
+ * @{
+ */
+/**
+ * @brief STM32F3xx HAL Driver version number V1.5.2
+ */
+#define __STM32F3xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
+#define __STM32F3xx_HAL_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */
+#define __STM32F3xx_HAL_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
+#define __STM32F3xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
+#define __STM32F3xx_HAL_VERSION ((__STM32F3xx_HAL_VERSION_MAIN << 24U)\
+ |(__STM32F3xx_HAL_VERSION_SUB1 << 16U)\
+ |(__STM32F3xx_HAL_VERSION_SUB2 << 8U )\
+ |(__STM32F3xx_HAL_VERSION_RC))
+
+#define IDCODE_DEVID_MASK (0x00000FFFU)
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Exported variables --------------------------------------------------------*/
+/** @defgroup HAL_Exported_Variables HAL Exported Variables
+ * @{
+ */
+__IO uint32_t uwTick;
+uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
+HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
+/**
+ * @}
+ */
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup HAL_Exported_Functions HAL Exported Functions
+ * @{
+ */
+
+/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
+ * @brief Initialization and de-initialization functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initializes the Flash interface, the NVIC allocation and initial clock
+ configuration. It initializes the systick also when timeout is needed
+ and the backup domain when enabled.
+ (+) de-Initializes common part of the HAL.
+ (+) Configure The time base source to have 1ms time base with a dedicated
+ Tick interrupt priority.
+ (++) SysTick timer is used by default as source of time base, but user
+ can eventually implement his proper time base source (a general purpose
+ timer for example or other time source), keeping in mind that Time base
+ duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
+ handled in milliseconds basis.
+ (++) Time base configuration function (HAL_InitTick ()) is called automatically
+ at the beginning of the program after reset by HAL_Init() or at any time
+ when clock is configured, by HAL_RCC_ClockConfig().
+ (++) Source of time base is configured to generate interrupts at regular
+ time intervals. Care must be taken if HAL_Delay() is called from a
+ peripheral ISR process, the Tick interrupt line must have higher priority
+ (numerically lower) than the peripheral interrupt. Otherwise the caller
+ ISR process will be blocked.
+ (++) functions affecting time base configurations are declared as __Weak
+ to make override possible in case of other implementations in user file.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function configures the Flash prefetch,
+ * Configures time base source, NVIC and Low level hardware
+ * @note This function is called at the beginning of program after reset and before
+ * the clock configuration
+ *
+ * @note The Systick configuration is based on HSI clock, as HSI is the clock
+ * used after a system Reset and the NVIC configuration is set to Priority group 4
+ *
+ * @note The time base configuration is based on MSI clock when exting from Reset.
+ * Once done, time base tick start incrementing.
+ * In the default implementation,Systick is used as source of time base.
+ * The tick variable is incremented each 1ms in its ISR.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_Init(void)
+{
+ /* Configure Flash prefetch */
+#if (PREFETCH_ENABLE != 0U)
+ __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
+#endif /* PREFETCH_ENABLE */
+
+ /* Set Interrupt Group Priority */
+ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+ /* Enable systick and configure 1ms tick (default clock after Reset is HSI) */
+ HAL_InitTick(TICK_INT_PRIORITY);
+
+ /* Init the low level hardware */
+ HAL_MspInit();
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief This function de-Initializes common part of the HAL and stops the systick.
+ * @note This function is optional.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DeInit(void)
+{
+ /* Reset of all peripherals */
+ __HAL_RCC_APB1_FORCE_RESET();
+ __HAL_RCC_APB1_RELEASE_RESET();
+
+ __HAL_RCC_APB2_FORCE_RESET();
+ __HAL_RCC_APB2_RELEASE_RESET();
+
+ __HAL_RCC_AHB_FORCE_RESET();
+ __HAL_RCC_AHB_RELEASE_RESET();
+
+ /* De-Init the low level hardware */
+ HAL_MspDeInit();
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the MSP.
+ * @retval None
+ */
+__weak void HAL_MspInit(void)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the MSP.
+ * @retval None
+ */
+__weak void HAL_MspDeInit(void)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief This function configures the source of the time base.
+ * The time source is configured to have 1ms time base with a dedicated
+ * Tick interrupt priority.
+ * @note This function is called automatically at the beginning of program after
+ * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
+ * @note In the default implementation , SysTick timer is the source of time base.
+ * It is used to generate interrupts at regular time intervals.
+ * Care must be taken if HAL_Delay() is called from a peripheral ISR process,
+ * The SysTick interrupt must have higher priority (numerically lower)
+ * than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+ * The function is declared as __Weak to be overwritten in case of other
+ * implementation in user file.
+ * @param TickPriority Tick interrupt priority.
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+ /* Configure the SysTick to have interrupt in 1ms time basis*/
+ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Configure the SysTick IRQ priority */
+ if (TickPriority < (1UL << __NVIC_PRIO_BITS))
+ {
+ HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
+ uwTickPrio = TickPriority;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
+ * @brief HAL Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### HAL Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Provide a tick value in millisecond
+ (+) Provide a blocking delay in millisecond
+ (+) Suspend the time base source interrupt
+ (+) Resume the time base source interrupt
+ (+) Get the HAL API driver version
+ (+) Get the device identifier
+ (+) Get the device revision identifier
+ (+) Enable/Disable Debug module during Sleep mode
+ (+) Enable/Disable Debug module during STOP mode
+ (+) Enable/Disable Debug module during STANDBY mode
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function is called to increment a global variable "uwTick"
+ * used as application time base.
+ * @note In the default implementation, this variable is incremented each 1ms
+ * in SysTick ISR.
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval None
+ */
+__weak void HAL_IncTick(void)
+{
+ uwTick += uwTickFreq;
+}
+
+/**
+ * @brief Povides a tick value in millisecond.
+ * @note The function is declared as __Weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval tick value
+ */
+__weak uint32_t HAL_GetTick(void)
+{
+ return uwTick;
+}
+
+/**
+ * @brief This function returns a tick priority.
+ * @retval tick priority
+ */
+uint32_t HAL_GetTickPrio(void)
+{
+ return uwTickPrio;
+}
+
+/**
+ * @brief Set new tick Freq.
+ * @retval Status
+ */
+HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ assert_param(IS_TICKFREQ(Freq));
+
+ if (uwTickFreq != Freq)
+ {
+ uwTickFreq = Freq;
+
+ /* Apply the new tick Freq */
+ status = HAL_InitTick(uwTickPrio);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Return tick frequency.
+ * @retval tick period in Hz
+ */
+HAL_TickFreqTypeDef HAL_GetTickFreq(void)
+{
+ return uwTickFreq;
+}
+
+/**
+ * @brief This function provides accurate delay (in milliseconds) based
+ * on variable incremented.
+ * @note In the default implementation , SysTick timer is the source of time base.
+ * It is used to generate interrupts at regular time intervals where uwTick
+ * is incremented.
+ * The function is declared as __Weak to be overwritten in case of other
+ * implementations in user file.
+ * @param Delay specifies the delay time length, in milliseconds.
+ * @retval None
+ */
+__weak void HAL_Delay(uint32_t Delay)
+{
+ uint32_t tickstart = HAL_GetTick();
+ uint32_t wait = Delay;
+
+ /* Add freq to guarantee minimum wait */
+ if (wait < HAL_MAX_DELAY)
+ {
+ wait += (uint32_t)(uwTickFreq);
+ }
+
+ while((HAL_GetTick() - tickstart) < wait)
+ {
+ }
+}
+
+/**
+ * @brief Suspend Tick increment.
+ * @note In the default implementation , SysTick timer is the source of time base. It is
+ * used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
+ * is called, the the SysTick interrupt will be disabled and so Tick increment
+ * is suspended.
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval None
+ */
+__weak void HAL_SuspendTick(void)
+
+{
+ /* Disable SysTick Interrupt */
+ SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
+
+}
+
+/**
+ * @brief Resume Tick increment.
+ * @note In the default implementation , SysTick timer is the source of time base. It is
+ * used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
+ * is called, the the SysTick interrupt will be enabled and so Tick increment
+ * is resumed.
+ * The function is declared as __Weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval None
+ */
+__weak void HAL_ResumeTick(void)
+{
+ /* Enable SysTick Interrupt */
+ SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
+
+}
+
+/**
+ * @brief This function returns the HAL revision
+ * @retval version 0xXYZR (8bits for each decimal, R for RC)
+ */
+uint32_t HAL_GetHalVersion(void)
+{
+ return __STM32F3xx_HAL_VERSION;
+}
+
+/**
+ * @brief Returns the device revision identifier.
+ * @retval Device revision identifier
+ */
+uint32_t HAL_GetREVID(void)
+{
+ return((DBGMCU->IDCODE) >> 16U);
+}
+
+/**
+ * @brief Returns the device identifier.
+ * @retval Device identifier
+ */
+uint32_t HAL_GetDEVID(void)
+{
+ return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
+}
+
+/**
+ * @brief Returns first word of the unique device identifier (UID based on 96 bits)
+ * @retval Device identifier
+ */
+uint32_t HAL_GetUIDw0(void)
+{
+ return(READ_REG(*((uint32_t *)UID_BASE)));
+}
+
+/**
+ * @brief Returns second word of the unique device identifier (UID based on 96 bits)
+ * @retval Device identifier
+ */
+uint32_t HAL_GetUIDw1(void)
+{
+ return(READ_REG(*((uint32_t *)(UID_BASE + 4U))));
+}
+
+/**
+ * @brief Returns third word of the unique device identifier (UID based on 96 bits)
+ * @retval Device identifier
+ */
+uint32_t HAL_GetUIDw2(void)
+{
+ return(READ_REG(*((uint32_t *)(UID_BASE + 8U))));
+}
+
+/**
+ * @brief Enable the Debug Module during SLEEP mode
+ * @retval None
+ */
+void HAL_DBGMCU_EnableDBGSleepMode(void)
+{
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+ * @brief Disable the Debug Module during SLEEP mode
+ * @retval None
+ */
+void HAL_DBGMCU_DisableDBGSleepMode(void)
+{
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+ * @brief Enable the Debug Module during STOP mode
+ * @retval None
+ */
+void HAL_DBGMCU_EnableDBGStopMode(void)
+{
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+ * @brief Disable the Debug Module during STOP mode
+ * @retval None
+ */
+void HAL_DBGMCU_DisableDBGStopMode(void)
+{
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+ * @brief Enable the Debug Module during STANDBY mode
+ * @retval None
+ */
+void HAL_DBGMCU_EnableDBGStandbyMode(void)
+{
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+ * @brief Disable the Debug Module during STANDBY mode
+ * @retval None
+ */
+void HAL_DBGMCU_DisableDBGStandbyMode(void)
+{
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_adc.c b/Src/stm32f3xx_hal_adc.c
new file mode 100644
index 0000000..14e733e
--- /dev/null
+++ b/Src/stm32f3xx_hal_adc.c
@@ -0,0 +1,961 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_adc.c
+ * @author MCD Application Team
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Analog to Digital Convertor (ADC)
+ * peripheral:
+ * + Initialization and de-initialization functions
+ * ++ Initialization and Configuration of ADC
+ * + Operation functions
+ * ++ Start, stop, get result of conversions of regular
+ * group, using 3 possible modes: polling, interruption or DMA.
+ * + Control functions
+ * ++ Channels configuration on regular group
+ * ++ Channels configuration on injected group
+ * ++ Analog Watchdog configuration
+ * + State functions
+ * ++ ADC state machine management
+ * ++ Interrupts and flags management
+ * Other functions (extended functions) are available in file
+ * "stm32f3xx_hal_adc_ex.c".
+ *
+ @verbatim
+ ==============================================================================
+ ##### ADC peripheral features #####
+ ==============================================================================
+ [..]
+ (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution (available only on
+ STM32F30xxC devices).
+
+ (+) Interrupt generation at the end of regular conversion, end of injected
+ conversion, and in case of analog watchdog or overrun events.
+
+ (+) Single and continuous conversion modes.
+
+ (+) Scan mode for conversion of several channels sequentially.
+
+ (+) Data alignment with in-built data coherency.
+
+ (+) Programmable sampling time (channel wise)
+
+ (+) ADC conversion of regular group and injected group.
+
+ (+) External trigger (timer or EXTI) with configurable polarity
+ for both regular and injected groups.
+
+ (+) DMA request generation for transfer of conversions data of regular group.
+
+ (+) Multimode dual mode (available on devices with 2 ADCs or more).
+
+ (+) Configurable DMA data storage in Multimode Dual mode (available on devices
+ with 2 DCs or more).
+
+ (+) Configurable delay between conversions in Dual interleaved mode (available
+ on devices with 2 DCs or more).
+
+ (+) ADC calibration
+
+ (+) ADC channels selectable single/differential input (available only on
+ STM32F30xxC devices)
+
+ (+) ADC Injected sequencer&channels configuration context queue (available
+ only on STM32F30xxC devices)
+
+ (+) ADC offset on injected and regular groups (offset on regular group
+ available only on STM32F30xxC devices)
+
+ (+) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
+ slower speed.
+
+ (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
+ Vdda or to an external voltage reference).
+
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+
+ *** Configuration of top level parameters related to ADC ***
+ ============================================================
+ [..]
+
+ (#) Enable the ADC interface
+ (++) As prerequisite, ADC clock must be configured at RCC top level.
+
+ (++) For STM32F30x/STM32F33x devices:
+ Two possible clock sources: synchronous clock derived from AHB clock
+ or asynchronous clock derived from ADC dedicated PLL 72MHz.
+ - Synchronous clock is mandatory since used as ADC core clock.
+ Synchronous clock can be used optionally as ADC conversion clock, depending on ADC init structure clock setting.
+ Synchronous clock is configured using macro __ADCx_CLK_ENABLE().
+ - Asynchronous can be used optionally as ADC conversion clock, depending on ADC init structure clock setting.
+ Asynchronous clock is configured using function HAL_RCCEx_PeriphCLKConfig().
+ (+++) For example, in case of device with a single ADC:
+ Into HAL_ADC_MspInit() (recommended code location) or with
+ other device clock parameters configuration:
+ (+++) __HAL_RCC_ADC1_CLK_ENABLE() (mandatory)
+ (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC (optional, if ADC conversion from asynchronous clock)
+ (+++) PeriphClkInit.Adc1ClockSelection = RCC_ADC1PLLCLK_DIV1 (optional, if ADC conversion from asynchronous clock)
+ (+++) HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStructure) (optional, if ADC conversion from asynchronous clock)
+
+ (+++) For example, in case of device with 4 ADCs:
+
+ (+++) if((hadc->Instance == ADC1) || (hadc->Instance == ADC2))
+ (+++) {
+ (+++) __HAL_RCC_ADC12_CLK_ENABLE() (mandatory)
+ (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC (optional, if ADC conversion from asynchronous clock)
+ (+++) PeriphClkInit.Adc12ClockSelection = RCC_ADC12PLLCLK_DIV1 (optional, if ADC conversion from asynchronous clock)
+ (+++) HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStructure) (optional, if ADC conversion from asynchronous clock)
+ (+++) }
+ (+++) else
+ (+++) {
+ (+++) __HAL_RCC_ADC34_CLK_ENABLE() (mandatory)
+ (+++) PeriphClkInit.Adc34ClockSelection = RCC_ADC34PLLCLK_DIV1; (optional, if ADC conversion from asynchronous clock)
+ (+++) HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStructure); (optional, if ADC conversion from asynchronous clock)
+ (+++) }
+
+ (++) For STM32F37x devices:
+ One clock setting is mandatory:
+ ADC clock (core and conversion clock) from APB2 clock.
+ (+++) Example:
+ Into HAL_ADC_MspInit() (recommended code location) or with
+ other device clock parameters configuration:
+ (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC
+ (+++) PeriphClkInit.AdcClockSelection = RCC_ADCPLLCLK_DIV2
+ (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit)
+
+ (#) ADC pins configuration
+ (++) Enable the clock for the ADC GPIOs
+ using macro __HAL_RCC_GPIOx_CLK_ENABLE()
+ (++) Configure these ADC pins in analog mode
+ using function HAL_GPIO_Init()
+
+ (#) Optionally, in case of usage of ADC with interruptions:
+ (++) Configure the NVIC for ADC
+ using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
+ (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
+ into the function of corresponding ADC interruption vector
+ ADCx_IRQHandler().
+
+ (#) Optionally, in case of usage of DMA:
+ (++) Configure the DMA (DMA channel, mode normal or circular, ...)
+ using function HAL_DMA_Init().
+ (++) Configure the NVIC for DMA
+ using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
+ (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
+ into the function of corresponding DMA interruption vector
+ DMAx_Channelx_IRQHandler().
+
+ *** Configuration of ADC, groups regular/injected, channels parameters ***
+ ==========================================================================
+ [..]
+
+ (#) Configure the ADC parameters (resolution, data alignment, ...)
+ and regular group parameters (conversion trigger, sequencer, ...)
+ using function HAL_ADC_Init().
+
+ (#) Configure the channels for regular group parameters (channel number,
+ channel rank into sequencer, ..., into regular group)
+ using function HAL_ADC_ConfigChannel().
+
+ (#) Optionally, configure the injected group parameters (conversion trigger,
+ sequencer, ..., of injected group)
+ and the channels for injected group parameters (channel number,
+ channel rank into sequencer, ..., into injected group)
+ using function HAL_ADCEx_InjectedConfigChannel().
+
+ (#) Optionally, configure the analog watchdog parameters (channels
+ monitored, thresholds, ...)
+ using function HAL_ADC_AnalogWDGConfig().
+
+ (#) Optionally, for devices with several ADC instances: configure the
+ multimode parameters
+ using function HAL_ADCEx_MultiModeConfigChannel().
+
+ *** Execution of ADC conversions ***
+ ====================================
+ [..]
+
+ (#) Optionally, perform an automatic ADC calibration to improve the
+ conversion accuracy
+ using function HAL_ADCEx_Calibration_Start().
+
+ (#) ADC driver can be used among three modes: polling, interruption,
+ transfer by DMA.
+
+ (++) ADC conversion by polling:
+ (+++) Activate the ADC peripheral and start conversions
+ using function HAL_ADC_Start()
+ (+++) Wait for ADC conversion completion
+ using function HAL_ADC_PollForConversion()
+ (or for injected group: HAL_ADCEx_InjectedPollForConversion() )
+ (+++) Retrieve conversion results
+ using function HAL_ADC_GetValue()
+ (or for injected group: HAL_ADCEx_InjectedGetValue() )
+ (+++) Stop conversion and disable the ADC peripheral
+ using function HAL_ADC_Stop()
+
+ (++) ADC conversion by interruption:
+ (+++) Activate the ADC peripheral and start conversions
+ using function HAL_ADC_Start_IT()
+ (+++) Wait for ADC conversion completion by call of function
+ HAL_ADC_ConvCpltCallback()
+ (this function must be implemented in user program)
+ (or for injected group: HAL_ADCEx_InjectedConvCpltCallback() )
+ (+++) Retrieve conversion results
+ using function HAL_ADC_GetValue()
+ (or for injected group: HAL_ADCEx_InjectedGetValue() )
+ (+++) Stop conversion and disable the ADC peripheral
+ using function HAL_ADC_Stop_IT()
+
+ (++) ADC conversion with transfer by DMA:
+ (+++) Activate the ADC peripheral and start conversions
+ using function HAL_ADC_Start_DMA()
+ (+++) Wait for ADC conversion completion by call of function
+ HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
+ (these functions must be implemented in user program)
+ (+++) Conversion results are automatically transferred by DMA into
+ destination variable address.
+ (+++) Stop conversion and disable the ADC peripheral
+ using function HAL_ADC_Stop_DMA()
+
+ (++) For devices with several ADCs: ADC multimode conversion
+ with transfer by DMA:
+ (+++) Activate the ADC peripheral (slave)
+ using function HAL_ADC_Start()
+ (conversion start pending ADC master)
+ (+++) Activate the ADC peripheral (master) and start conversions
+ using function HAL_ADCEx_MultiModeStart_DMA()
+ (+++) Wait for ADC conversion completion by call of function
+ HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
+ (these functions must be implemented in user program)
+ (+++) Conversion results are automatically transferred by DMA into
+ destination variable address.
+ (+++) Stop conversion and disable the ADC peripheral (master)
+ using function HAL_ADCEx_MultiModeStop_DMA()
+ (+++) Stop conversion and disable the ADC peripheral (slave)
+ using function HAL_ADC_Stop_IT()
+
+ [..]
+
+ (@) Callback functions must be implemented in user program:
+ (+@) HAL_ADC_ErrorCallback()
+ (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
+ (+@) HAL_ADC_ConvCpltCallback()
+ (+@) HAL_ADC_ConvHalfCpltCallback
+ (+@) HAL_ADCEx_InjectedConvCpltCallback()
+ (+@) HAL_ADCEx_InjectedQueueOverflowCallback() (for STM32F30x/STM32F33x devices)
+
+ *** Deinitialization of ADC ***
+ ============================================================
+ [..]
+
+ (#) Disable the ADC interface
+ (++) ADC clock can be hard reset and disabled at RCC top level.
+ (++) Hard reset of ADC peripherals
+ using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
+ (++) ADC clock disable
+ using the equivalent macro/functions as configuration step.
+
+ (++) For STM32F30x/STM32F33x devices:
+ Caution: For devices with several ADCs:
+ These settings impact both ADC of common group: ADC1&ADC2, ADC3&ADC4
+ if available (ADC2, ADC3, ADC4 availability depends on STM32 product)
+
+ (+++) For example, in case of device with a single ADC:
+ Into HAL_ADC_MspDeInit() (recommended code location) or with
+ other device clock parameters configuration:
+ (+++) __HAL_RCC_ADC1_FORCE_RESET() (optional)
+ (+++) __HAL_RCC_ADC1_RELEASE_RESET() (optional)
+ (+++) __HAL_RCC_ADC1_CLK_DISABLE() (mandatory)
+ (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC (optional, if configured before)
+ (+++) PeriphClkInit.Adc1ClockSelection = RCC_ADC1PLLCLK_OFF (optional, if configured before)
+ (+++) HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStructure) (optional, if configured before)
+
+ (+++) For example, in case of device with 4 ADCs:
+ (+++) if((hadc->Instance == ADC1) || (hadc->Instance == ADC2))
+ (+++) {
+ (+++) __HAL_RCC_ADC12_FORCE_RESET() (optional)
+ (+++) __HAL_RCC_ADC12_RELEASE_RESET() (optional)
+ (+++) __HAL_RCC_ADC12_CLK_DISABLE() (mandatory)
+ (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC (optional, if configured before)
+ (+++) PeriphClkInit.Adc12ClockSelection = RCC_ADC12PLLCLK_OFF (optional, if configured before)
+ (+++) HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStructure) (optional, if configured before)
+ (+++) }
+ (+++) else
+ (+++) {
+ (+++) __HAL_RCC_ADC32_FORCE_RESET() (optional)
+ (+++) __HAL_RCC_ADC32_RELEASE_RESET() (optional)
+ (+++) __HAL_RCC_ADC34_CLK_DISABLE() (mandatory)
+ (+++) PeriphClkInit.Adc34ClockSelection = RCC_ADC34PLLCLK_OFF (optional, if configured before)
+ (+++) HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStructure) (optional, if configured before)
+ (+++) }
+
+ (++) For STM32F37x devices:
+ (+++) Example:
+ Into HAL_ADC_MspDeInit() (recommended code location) or with
+ other device clock parameters configuration:
+ (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC
+ (+++) PeriphClkInit.AdcClockSelection = RCC_ADCPLLCLK_OFF
+ (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit)
+
+ (#) ADC pins configuration
+ (++) Disable the clock for the ADC GPIOs
+ using macro __HAL_RCC_GPIOx_CLK_DISABLE()
+
+ (#) Optionally, in case of usage of ADC with interruptions:
+ (++) Disable the NVIC for ADC
+ using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
+
+ (#) Optionally, in case of usage of DMA:
+ (++) Deinitialize the DMA
+ using function HAL_DMA_Init().
+ (++) Disable the NVIC for DMA
+ using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
+
+ [..]
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup ADC ADC
+ * @brief ADC HAL module driver
+ * @{
+ */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Functions ADC Exported Functions
+ * @{
+ */
+
+/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize and configure the ADC.
+ (+) De-initialize the ADC.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the ADC peripheral and regular group according to
+ * parameters specified in structure "ADC_InitTypeDef".
+ * @note As prerequisite, ADC clock must be configured at RCC top level
+ * depending on both possible clock sources: PLL clock or AHB clock.
+ * See commented example code below that can be copied and uncommented
+ * into HAL_ADC_MspInit().
+ * @note Possibility to update parameters on the fly:
+ * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
+ * coming from ADC state reset. Following calls to this function can
+ * be used to reconfigure some parameters of ADC_InitTypeDef
+ * structure on the fly, without modifying MSP configuration. If ADC
+ * MSP has to be modified again, HAL_ADC_DeInit() must be called
+ * before HAL_ADC_Init().
+ * The setting of these parameters is conditioned to ADC state.
+ * For parameters constraints, see comments of structure
+ * "ADC_InitTypeDef".
+ * @note This function configures the ADC within 2 scopes: scope of entire
+ * ADC and scope of regular group. For parameters details, see comments
+ * of structure "ADC_InitTypeDef".
+ * @note For devices with several ADCs: parameters related to common ADC
+ * registers (ADC clock mode) are set only if all ADCs sharing the
+ * same common group are disabled.
+ * If this is not the case, these common parameters setting are
+ * bypassed without error reporting: it can be the intended behaviour in
+ * case of update of a parameter of ADC_InitTypeDef on the fly,
+ * without disabling the other ADCs sharing the same common group.
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* Note : This function is defined into this file for library reference. */
+ /* Function content is located into file stm32f3xx_hal_adc_ex.c */
+
+ /* Return function status */
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Deinitialize the ADC peripheral registers to their default reset
+ * values, with deinitialization of the ADC MSP.
+ * @note For devices with several ADCs: reset of ADC common registers is done
+ * only if all ADCs sharing the same common group are disabled.
+ * If this is not the case, reset of these common parameters reset is
+ * bypassed without error reporting: it can be the intended behaviour in
+ * case of reset of a single ADC while the other ADCs sharing the same
+ * common group is still running.
+ * @note For devices with several ADCs: Global reset of all ADCs sharing a
+ * common group is possible.
+ * As this function is intended to reset a single ADC, to not impact
+ * other ADCs, instructions for global reset of multiple ADCs have been
+ * let commented below.
+ * If needed, the example code can be copied and uncommented into
+ * function HAL_ADC_MspDeInit().
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* Note : This function is defined into this file for library reference. */
+ /* Function content is located into file stm32f3xx_hal_adc_ex.c */
+
+ /* Return function status */
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Initializes the ADC MSP.
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_MspInit must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief DeInitializes the ADC MSP.
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_MspDeInit must be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Exported_Functions_Group2 Input and Output operation functions
+ * @brief IO operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Start conversion of regular group.
+ (+) Stop conversion of regular group.
+ (+) Poll for conversion complete on regular group.
+ (+) Poll for conversion event.
+ (+) Get result of regular channel conversion.
+ (+) Start conversion of regular group and enable interruptions.
+ (+) Stop conversion of regular group and disable interruptions.
+ (+) Handle ADC interrupt request
+ (+) Start conversion of regular group and enable DMA transfer.
+ (+) Stop conversion of regular group and disable ADC DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Enables ADC, starts conversion of regular group.
+ * Interruptions enabled in this function: None.
+ * @note: Case of multimode enabled (for devices with several ADCs): This
+ * function must be called for ADC slave first, then ADC master.
+ * For ADC slave, ADC is enabled only (conversion is not started).
+ * For ADC master, ADC is enabled and multimode conversion is started.
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* Return function status */
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Stop ADC conversion of regular group (and injected group in
+ * case of auto_injection mode), disable ADC peripheral.
+ * @note: ADC peripheral disable is forcing stop of potential
+ * conversion on injected group. If injected group is under use, it
+ * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
+ * @note: Case of multimode enabled (for devices with several ADCs): This
+ * function must be called for ADC master first, then ADC slave.
+ * For ADC master, converson is stopped and ADC is disabled.
+ * For ADC slave, ADC is disabled only (conversion stop of ADC master
+ * has already stopped conversion of ADC slave).
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+__weak HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* Note : This function is defined into this file for library reference. */
+ /* Function content is located into file stm32f3xx_hal_adc_ex.c */
+
+ /* Return function status */
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Wait for regular group conversion to be completed.
+ * @param hadc ADC handle
+ * @param Timeout Timeout value in millisecond.
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+ UNUSED(Timeout);
+
+ /* Note : This function is defined into this file for library reference. */
+ /* Function content is located into file stm32f3xx_hal_adc_ex.c */
+
+ /* Return function status */
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Poll for conversion event.
+ * @param hadc ADC handle
+ * @param EventType the ADC event type.
+ * This parameter can be one of the following values:
+ * @arg ADC_AWD_EVENT: ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices)
+ * @arg ADC_AWD2_EVENT: ADC Analog watchdog 2 event (additional analog watchdog, present only on STM32F3 devices)
+ * @arg ADC_AWD3_EVENT: ADC Analog watchdog 3 event (additional analog watchdog, present only on STM32F3 devices)
+ * @arg ADC_OVR_EVENT: ADC Overrun event
+ * @arg ADC_JQOVF_EVENT: ADC Injected context queue overflow event
+ * @param Timeout Timeout value in millisecond.
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+ UNUSED(EventType);
+ UNUSED(Timeout);
+
+ /* Note : This function is defined into this file for library reference. */
+ /* Function content is located into file stm32f3xx_hal_adc_ex.c */
+
+ /* Return function status */
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Enables ADC, starts conversion of regular group with interruption.
+ * Interruptions enabled in this function:
+ * - EOC (end of conversion of regular group) or EOS (end of
+ * sequence of regular group) depending on ADC initialization
+ * parameter "EOCSelection" (if available)
+ * - overrun (if available)
+ * Each of these interruptions has its dedicated callback function.
+ * @note: Case of multimode enabled (for devices with several ADCs): This
+ * function must be called for ADC slave first, then ADC master.
+ * For ADC slave, ADC is enabled only (conversion is not started).
+ * For ADC master, ADC is enabled and multimode conversion is started.
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* Note : This function is defined into this file for library reference. */
+ /* Function content is located into file stm32f3xx_hal_adc_ex.c */
+
+ /* Return function status */
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Stop ADC conversion of regular group (and injected group in
+ * case of auto_injection mode), disable interruption of
+ * end-of-conversion, disable ADC peripheral.
+ * @note: ADC peripheral disable is forcing stop of potential
+ * conversion on injected group. If injected group is under use, it
+ * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
+ * @note: Case of multimode enabled (for devices with several ADCs): This
+ * function must be called for ADC master first, then ADC slave.
+ * For ADC master, conversion is stopped and ADC is disabled.
+ * For ADC slave, ADC is disabled only (conversion stop of ADC master
+ * has already stopped conversion of ADC slave).
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+__weak HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* Note : This function is defined into this file for library reference. */
+ /* Function content is located into file stm32f3xx_hal_adc_ex.c */
+
+ /* Return function status */
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Enables ADC, starts conversion of regular group and transfers result
+ * through DMA.
+ * Interruptions enabled in this function:
+ * - DMA transfer complete
+ * - DMA half transfer
+ * - overrun (if available)
+ * Each of these interruptions has its dedicated callback function.
+ * @note: Case of multimode enabled (for devices with several ADCs): This
+ * function is for single-ADC mode only. For multimode, use the
+ * dedicated MultimodeStart function.
+ * @param hadc ADC handle
+ * @param pData The destination Buffer address.
+ * @param Length The length of data to be transferred from ADC peripheral to memory.
+ * @retval None
+ */
+__weak HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+ UNUSED(pData);
+ UNUSED(Length);
+
+ /* Note : This function is defined into this file for library reference. */
+ /* Function content is located into file stm32f3xx_hal_adc_ex.c */
+
+ /* Return function status */
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Stop ADC conversion of regular group (and injected group in
+ * case of auto_injection mode), disable ADC DMA transfer, disable
+ * ADC peripheral.
+ * @note: ADC peripheral disable is forcing stop of potential
+ * conversion on injected group. If injected group is under use, it
+ * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
+ * @note: Case of multimode enabled (for devices with several ADCs): This
+ * function is for single-ADC mode only. For multimode, use the
+ * dedicated MultimodeStop function.
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+__weak HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* Note : This function is defined into this file for library reference. */
+ /* Function content is located into file stm32f3xx_hal_adc_ex.c */
+
+ /* Return function status */
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Get ADC regular group conversion result.
+ * @note Reading DR register automatically clears EOC (end of conversion of
+ * regular group) flag.
+ * Additionally, this functions clears EOS (end of sequence of
+ * regular group) flag, in case of the end of the sequence is reached.
+ * @param hadc ADC handle
+ * @retval Converted value
+ */
+__weak uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
+{
+ /* Note : This function is defined into this file for library reference. */
+ /* Function content is located into file stm32f3xx_hal_adc_ex.c */
+
+ /* Return ADC converted value */
+ return hadc->Instance->DR;
+}
+
+/**
+ * @brief Handles ADC interrupt request.
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* Note : This function is defined into this file for library reference. */
+ /* Function content is located into file stm32f3xx_hal_adc_ex.c */
+}
+
+/**
+ * @brief Conversion complete callback in non blocking mode
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_ConvCpltCallback must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Conversion DMA half-transfer callback in non blocking mode
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Analog watchdog callback in non blocking mode.
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_LevelOoutOfWindowCallback must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief ADC error callback in non blocking mode
+ * (ADC conversion with interruption or transfer by DMA)
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_ErrorCallback must be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure channels on regular group
+ (+) Configure the analog watchdog
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the the selected channel to be linked to the regular
+ * group.
+ * @note In case of usage of internal measurement channels:
+ * Vbat/VrefInt/TempSensor.
+ * The recommended sampling time is at least:
+ * - For devices STM32F37x: 17.1us for temperature sensor
+ * - For the other STM32F3 devices: 2.2us for each of channels
+ * Vbat/VrefInt/TempSensor.
+ * These internal paths can be be disabled using function
+ * HAL_ADC_DeInit().
+ * @note Possibility to update parameters on the fly:
+ * This function initializes channel into regular group, following
+ * calls to this function can be used to reconfigure some parameters
+ * of structure "ADC_ChannelConfTypeDef" on the fly, without reseting
+ * the ADC.
+ * The setting of these parameters is conditioned to ADC state.
+ * For parameters constraints, see comments of structure
+ * "ADC_ChannelConfTypeDef".
+ * @param hadc ADC handle
+ * @param sConfig Structure of ADC channel for regular group.
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+ UNUSED(sConfig);
+
+ /* Note : This function is defined into this file for library reference. */
+ /* Function content is located into file stm32f3xx_hal_adc_ex.c */
+
+ /* Return function status */
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Configures the analog watchdog.
+ * @note Possibility to update parameters on the fly:
+ * This function initializes the selected analog watchdog, following
+ * calls to this function can be used to reconfigure some parameters
+ * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without reseting
+ * the ADC.
+ * The setting of these parameters is conditioned to ADC state.
+ * For parameters constraints, see comments of structure
+ * "ADC_AnalogWDGConfTypeDef".
+ * @param hadc ADC handle
+ * @param AnalogWDGConfig Structure of ADC analog watchdog configuration
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+ UNUSED(AnalogWDGConfig);
+
+ /* Note : This function is defined into this file for library reference. */
+ /* Function content is located into file stm32f3xx_hal_adc_ex.c */
+
+ /* Return function status */
+ return HAL_ERROR;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
+ * @brief ADC Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral state and errors functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions to get in run-time the status of the
+ peripheral.
+ (+) Check the ADC state
+ (+) Check the ADC error code
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief return the ADC state
+ * @note ADC state machine is managed by bitfield, state must be compared
+ * with bit by bit.
+ * For example:
+ * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) "
+ * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) "
+ * @param hadc ADC handle
+ * @retval HAL state
+ */
+uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Return ADC state */
+ return hadc->State;
+}
+
+/**
+ * @brief Return the ADC error code
+ * @param hadc ADC handle
+ * @retval ADC Error Code
+ */
+uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
+{
+ return hadc->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_ADC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_adc_ex.c b/Src/stm32f3xx_hal_adc_ex.c
new file mode 100644
index 0000000..cd93581
--- /dev/null
+++ b/Src/stm32f3xx_hal_adc_ex.c
@@ -0,0 +1,7474 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_adc_ex.c
+ * @author MCD Application Team
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Analog to Digital Convertor (ADC)
+ * peripheral:
+ * + Operation functions
+ * ++ Start, stop, get result of conversions of injected
+ * group, using 2 possible modes: polling, interruption.
+ * ++ Multimode feature (available on devices with 2 ADCs or more)
+ * ++ Calibration (ADC automatic self-calibration)
+ * + Control functions
+ * ++ Channels configuration on injected group
+ * Other functions (generic functions) are available in file
+ * "stm32f3xx_hal_adc.c".
+ *
+ @verbatim
+ [..]
+ (@) Sections "ADC peripheral features" and "How to use this driver" are
+ available in file of generic functions "stm32f3xx_hal_adc.c".
+ [..]
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup ADCEx ADCEx
+ * @brief ADC Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup ADCEx_Private_Constants ADCEx Private Constants
+ * @{
+ */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+ /* Fixed timeout values for ADC calibration, enable settling time, disable */
+ /* settling time. */
+ /* Values defined to be higher than worst cases: low clock frequency, */
+ /* maximum prescalers. */
+ /* Ex of profile low frequency : Clock source at 0.5 MHz, ADC clock */
+ /* prescaler 256 (devices STM32F30xx), sampling time 7.5 ADC clock cycles, */
+ /* resolution 12 bits. */
+ /* Unit: ms */
+ #define ADC_CALIBRATION_TIMEOUT ( 10U)
+ #define ADC_ENABLE_TIMEOUT ( 2U)
+ #define ADC_DISABLE_TIMEOUT ( 2U)
+ #define ADC_STOP_CONVERSION_TIMEOUT ( 11U)
+
+ /* Timeout to wait for current conversion on going to be completed. */
+ /* Timeout fixed to worst case, for 1 channel. */
+ /* - maximum sampling time (601.5 adc_clk) */
+ /* - ADC resolution (Tsar 12 bits= 12.5 adc_clk) */
+ /* - ADC clock (from PLL with prescaler 256 (devices STM32F30xx)) */
+ /* Unit: cycles of CPU clock. */
+ #define ADC_CONVERSION_TIME_MAX_CPU_CYCLES ( 156928U)
+
+ /* Delay for ADC stabilization time (ADC voltage regulator start-up time) */
+ /* Maximum delay is 10us (refer to device datasheet, param. TADCVREG_STUP). */
+ /* Unit: us */
+ #define ADC_STAB_DELAY_US ( 10U)
+
+ /* Delay for temperature sensor stabilization time. */
+ /* Maximum delay is 10us (refer device datasheet, parameter tSTART). */
+ /* Unit: us */
+ #define ADC_TEMPSENSOR_DELAY_US ( 10U)
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+ /* Timeout values for ADC enable and disable settling time. */
+ /* Values defined to be higher than worst cases: low clocks freq, */
+ /* maximum prescaler. */
+ /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */
+ /* prescaler 4U, sampling time 12.5 ADC clock cycles, resolution 12 bits. */
+ /* Unit: ms */
+ #define ADC_ENABLE_TIMEOUT ( 2U)
+ #define ADC_DISABLE_TIMEOUT ( 2U)
+
+ /* Delay for ADC calibration: */
+ /* Hardware prerequisite before starting a calibration: the ADC must have */
+ /* been in power-on state for at least two ADC clock cycles. */
+ /* Unit: ADC clock cycles */
+ #define ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES ( 2U)
+
+ /* Timeout value for ADC calibration */
+ /* Value defined to be higher than worst cases: low clocks freq, */
+ /* maximum prescaler. */
+ /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */
+ /* prescaler 4U, sampling time 12.5 ADC clock cycles, resolution 12 bits. */
+ /* Unit: ms */
+ #define ADC_CALIBRATION_TIMEOUT ( 10U)
+
+ /* Delay for ADC stabilization time. */
+ /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */
+ /* Unit: us */
+ #define ADC_STAB_DELAY_US ( 1U)
+
+ /* Delay for temperature sensor stabilization time. */
+ /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
+ /* Unit: us */
+ #define ADC_TEMPSENSOR_DELAY_US ( 10U)
+
+ /* Maximum number of CPU cycles corresponding to 1 ADC cycle */
+ /* Value fixed to worst case: clock prescalers slowing down ADC clock to */
+ /* minimum frequency */
+ /* - AHB prescaler: 16 */
+ /* - ADC prescaler: 8 */
+ /* Unit: cycles of CPU clock. */
+ #define ADC_CYCLE_WORST_CASE_CPU_CYCLES ( 128U)
+
+ /* ADC conversion cycles (unit: ADC clock cycles) */
+ /* (selected sampling time + conversion time of 12.5 ADC clock cycles, with */
+ /* resolution 12 bits) */
+ #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5 ( 14U)
+ #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 ( 20U)
+ #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5 ( 26U)
+ #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5 ( 41U)
+ #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5 ( 54U)
+ #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5 ( 68U)
+ #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 ( 84U)
+ #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 (252U)
+#endif /* STM32F373xC || STM32F378xx */
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
+static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc);
+static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup);
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
+static HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc);
+#endif /* STM32F373xC || STM32F378xx */
+
+static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
+static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
+static void ADC_DMAError(DMA_HandleTypeDef *hdma);
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup ADCEx_Exported_Functions ADCEx Exported Functions
+ * @{
+ */
+
+/** @defgroup ADCEx_Exported_Functions_Group1 ADCEx Initialization and de-initialization functions
+ * @brief ADC Extended Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize and configure the ADC.
+ (+) De-initialize the ADC.
+
+@endverbatim
+ * @{
+ */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Initializes the ADC peripheral and regular group according to
+ * parameters specified in structure "ADC_InitTypeDef".
+ * @note As prerequisite, ADC clock must be configured at RCC top level
+ * depending on possible clock sources: AHB clock or PLL clock.
+ * See commented example code below that can be copied and uncommented
+ * into HAL_ADC_MspInit().
+ * @note Possibility to update parameters on the fly:
+ * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
+ * coming from ADC state reset. Following calls to this function can
+ * be used to reconfigure some parameters of ADC_InitTypeDef
+ * structure on the fly, without modifying MSP configuration. If ADC
+ * MSP has to be modified again, HAL_ADC_DeInit() must be called
+ * before HAL_ADC_Init().
+ * The setting of these parameters is conditioned by ADC state.
+ * For parameters constraints, see comments of structure
+ * "ADC_InitTypeDef".
+ * @note This function configures the ADC within 2 scopes: scope of entire
+ * ADC and scope of regular group. For parameters details, see comments
+ * of structure "ADC_InitTypeDef".
+ * @note For devices with several ADCs: parameters related to common ADC
+ * registers (ADC clock mode) are set only if all ADCs sharing the
+ * same common group are disabled.
+ * If this is not the case, these common parameters setting are
+ * bypassed without error reporting: it can be the intended behaviour in
+ * case of update of a parameter of ADC_InitTypeDef on the fly,
+ * without disabling the other ADCs sharing the same common group.
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ ADC_Common_TypeDef *tmpADC_Common;
+ ADC_HandleTypeDef tmphadcSharingSameCommonRegister;
+ uint32_t tmpCFGR = 0U;
+ __IO uint32_t wait_loop_index = 0U;
+
+ /* Check ADC handle */
+ if(hadc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
+ assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
+ assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
+ assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+ assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
+ assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
+ assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
+ assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
+
+ if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
+ {
+ assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
+ if(hadc->Init.DiscontinuousConvMode != DISABLE)
+ {
+ assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
+ }
+ }
+
+ /* Configuration of ADC core parameters and ADC MSP related parameters */
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
+ {
+ /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */
+ /* at RCC top level. */
+ /* Refer to header of this file for more details on clock enabling */
+ /* procedure. */
+
+ /* Actions performed only if ADC is coming from state reset: */
+ /* - Initialization of ADC MSP */
+ /* - ADC voltage regulator enable */
+ if (hadc->State == HAL_ADC_STATE_RESET)
+ {
+ /* Initialize ADC error code */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Initialize HAL ADC API internal variables */
+ hadc->InjectionConfig.ChannelCount = 0U;
+ hadc->InjectionConfig.ContextQueue = 0U;
+
+ /* Allocate lock resource and initialize it */
+ hadc->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware */
+ HAL_ADC_MspInit(hadc);
+
+ /* Enable voltage regulator (if disabled at this step) */
+ if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN_0))
+ {
+ /* Note: The software must wait for the startup time of the ADC */
+ /* voltage regulator before launching a calibration or */
+ /* enabling the ADC. This temporization must be implemented by */
+ /* software and is equal to 10 us in the worst case */
+ /* process/temperature/power supply. */
+
+ /* Disable the ADC (if not already disabled) */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ /* Configuration of ADC parameters if previous preliminary actions */
+ /* are correctly completed. */
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
+ (tmp_hal_status == HAL_OK) )
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_BUSY_INTERNAL);
+
+ /* Set the intermediate state before moving the ADC voltage */
+ /* regulator to state enable. */
+ CLEAR_BIT(hadc->Instance->CR, (ADC_CR_ADVREGEN_1 | ADC_CR_ADVREGEN_0));
+ /* Set ADVREGEN bits to 0x01U */
+ SET_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN_0);
+
+ /* Delay for ADC stabilization time. */
+ /* Compute number of CPU cycles to wait for */
+ wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
+ while(wait_loop_index != 0U)
+ {
+ wait_loop_index--;
+ }
+ }
+ }
+ }
+
+ /* Verification that ADC voltage regulator is correctly enabled, whether */
+ /* or not ADC is coming from state reset (if any potential problem of */
+ /* clocking, voltage regulator would not be enabled). */
+ if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN_0) ||
+ HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADVREGEN_1) )
+ {
+ /* Update ADC state machine to error */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_BUSY_INTERNAL,
+ HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC IP internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+ }
+
+
+ /* Configuration of ADC parameters if previous preliminary actions are */
+ /* correctly completed and if there is no conversion on going on regular */
+ /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */
+ /* called to update a parameter on the fly). */
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
+ (tmp_hal_status == HAL_OK) &&
+ (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) )
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY,
+ HAL_ADC_STATE_BUSY_INTERNAL);
+
+ /* Configuration of common ADC parameters */
+
+ /* Pointer to the common control register to which is belonging hadc */
+ /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
+ /* control registers) */
+ tmpADC_Common = ADC_COMMON_REGISTER(hadc);
+
+ /* Set handle of the other ADC sharing the same common register */
+ ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister);
+
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated only when ADC is disabled: */
+ /* - Multimode clock configuration */
+ if ((ADC_IS_ENABLE(hadc) == RESET) &&
+ ((tmphadcSharingSameCommonRegister.Instance == NULL) ||
+ (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) )
+ {
+ /* Reset configuration of ADC common register CCR: */
+ /* - ADC clock mode: CKMODE */
+ /* Some parameters of this register are not reset, since they are set */
+ /* by other functions and must be kept in case of usage of this */
+ /* function on the fly (update of a parameter of ADC_InitTypeDef */
+ /* without needing to reconfigure all other ADC groups/channels */
+ /* parameters): */
+ /* - multimode related parameters: MDMA, DMACFG, DELAY, MULTI (set */
+ /* into HAL_ADCEx_MultiModeConfigChannel() ) */
+ /* - internal measurement paths: Vbat, temperature sensor, Vref */
+ /* (set into HAL_ADC_ConfigChannel() or */
+ /* HAL_ADCEx_InjectedConfigChannel() ) */
+
+ MODIFY_REG(tmpADC_Common->CCR ,
+ ADC_CCR_CKMODE ,
+ hadc->Init.ClockPrescaler );
+ }
+
+
+ /* Configuration of ADC: */
+ /* - resolution */
+ /* - data alignment */
+ /* - external trigger to start conversion */
+ /* - external trigger polarity */
+ /* - continuous conversion mode */
+ /* - overrun */
+ /* - discontinuous mode */
+ SET_BIT(tmpCFGR, ADC_CFGR_CONTINUOUS(hadc->Init.ContinuousConvMode) |
+ ADC_CFGR_OVERRUN(hadc->Init.Overrun) |
+ hadc->Init.DataAlign |
+ hadc->Init.Resolution );
+
+ /* Enable discontinuous mode only if continuous mode is disabled */
+ if (hadc->Init.DiscontinuousConvMode == ENABLE)
+ {
+ if (hadc->Init.ContinuousConvMode == DISABLE)
+ {
+ /* Enable the selected ADC regular discontinuous mode */
+ /* Set the number of channels to be converted in discontinuous mode */
+ SET_BIT(tmpCFGR, ADC_CFGR_DISCEN |
+ ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion) );
+ }
+ else
+ {
+ /* ADC regular group discontinuous was intended to be enabled, */
+ /* but ADC regular group modes continuous and sequencer discontinuous */
+ /* cannot be enabled simultaneously. */
+
+ /* Update ADC state machine to error */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_BUSY_INTERNAL,
+ HAL_ADC_STATE_ERROR_CONFIG);
+
+ /* Set ADC error code to ADC IP internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ }
+ }
+
+ /* Enable external trigger if trigger selection is different of software */
+ /* start. */
+ /* Note: This configuration keeps the hardware feature of parameter */
+ /* ExternalTrigConvEdge "trigger edge none" equivalent to */
+ /* software start. */
+ if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
+ {
+ SET_BIT(tmpCFGR, ADC_CFGR_EXTSEL_SET(hadc, hadc->Init.ExternalTrigConv) |
+ hadc->Init.ExternalTrigConvEdge );
+ }
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated when ADC is disabled or enabled without */
+ /* conversion on going on regular and injected groups: */
+ /* - DMA continuous request */
+ /* - LowPowerAutoWait feature */
+ if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
+ {
+ CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_AUTDLY |
+ ADC_CFGR_DMACFG );
+
+ SET_BIT(tmpCFGR, ADC_CFGR_AUTOWAIT(hadc->Init.LowPowerAutoWait) |
+ ADC_CFGR_DMACONTREQ(hadc->Init.DMAContinuousRequests) );
+ }
+
+ /* Update ADC configuration register with previous settings */
+ MODIFY_REG(hadc->Instance->CFGR,
+ ADC_CFGR_DISCNUM |
+ ADC_CFGR_DISCEN |
+ ADC_CFGR_CONT |
+ ADC_CFGR_OVRMOD |
+ ADC_CFGR_EXTSEL |
+ ADC_CFGR_EXTEN |
+ ADC_CFGR_ALIGN |
+ ADC_CFGR_RES ,
+ tmpCFGR );
+
+
+ /* Configuration of regular group sequencer: */
+ /* - if scan mode is disabled, regular channels sequence length is set to */
+ /* 0x00: 1 channel converted (channel on regular rank 1U) */
+ /* Parameter "NbrOfConversion" is discarded. */
+ /* Note: Scan mode is not present by hardware on this device, but */
+ /* emulated by software for alignment over all STM32 devices. */
+ /* - if scan mode is enabled, regular channels sequence length is set to */
+ /* parameter "NbrOfConversion" */
+ if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
+ {
+ /* Set number of ranks in regular group sequencer */
+ MODIFY_REG(hadc->Instance->SQR1 ,
+ ADC_SQR1_L ,
+ (hadc->Init.NbrOfConversion - (uint8_t)1U) );
+ }
+ else
+ {
+ CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
+ }
+
+ /* Set ADC error code to none */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Set the ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_BUSY_INTERNAL,
+ HAL_ADC_STATE_READY);
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_BUSY_INTERNAL,
+ HAL_ADC_STATE_ERROR_INTERNAL);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Initializes the ADC peripheral and regular group according to
+ * parameters specified in structure "ADC_InitTypeDef".
+ * @note As prerequisite, ADC clock must be configured at RCC top level
+ * (clock source APB2).
+ * See commented example code below that can be copied and uncommented
+ * into HAL_ADC_MspInit().
+ * @note Possibility to update parameters on the fly:
+ * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
+ * coming from ADC state reset. Following calls to this function can
+ * be used to reconfigure some parameters of ADC_InitTypeDef
+ * structure on the fly, without modifying MSP configuration. If ADC
+ * MSP has to be modified again, HAL_ADC_DeInit() must be called
+ * before HAL_ADC_Init().
+ * The setting of these parameters is conditioned to ADC state.
+ * For parameters constraints, see comments of structure
+ * "ADC_InitTypeDef".
+ * @note This function configures the ADC within 2 scopes: scope of entire
+ * ADC and scope of regular group. For parameters details, see comments
+ * of structure "ADC_InitTypeDef".
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ uint32_t tmp_cr1 = 0U;
+ uint32_t tmp_cr2 = 0U;
+ uint32_t tmp_sqr1 = 0U;
+
+ /* Check ADC handle */
+ if(hadc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
+ assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+ assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
+
+ if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
+ {
+ assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
+ if(hadc->Init.DiscontinuousConvMode != DISABLE)
+ {
+ assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
+ }
+ }
+
+ /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */
+ /* at RCC top level. */
+ /* Refer to header of this file for more details on clock enabling */
+ /* procedure. */
+
+ /* Actions performed only if ADC is coming from state reset: */
+ /* - Initialization of ADC MSP */
+ if (hadc->State == HAL_ADC_STATE_RESET)
+ {
+ /* Initialize ADC error code */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Allocate lock resource and initialize it */
+ hadc->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware */
+ HAL_ADC_MspInit(hadc);
+ }
+
+ /* Stop potential conversion on going, on regular and injected groups */
+ /* Disable ADC peripheral */
+ /* Note: In case of ADC already enabled, precaution to not launch an */
+ /* unwanted conversion while modifying register CR2 by writing 1 to */
+ /* bit ADON. */
+ tmp_hal_status = ADC_ConversionStop_Disable(hadc);
+
+
+ /* Configuration of ADC parameters if previous preliminary actions are */
+ /* correctly completed. */
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
+ (tmp_hal_status == HAL_OK) )
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_BUSY_INTERNAL);
+
+ /* Set ADC parameters */
+
+ /* Configuration of ADC: */
+ /* - data alignment */
+ /* - external trigger to start conversion */
+ /* - external trigger polarity (always set to 1U, because needed for all */
+ /* triggers: external trigger of SW start) */
+ /* - continuous conversion mode */
+ /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */
+ /* HAL_ADC_Start_xxx functions because if set in this function, */
+ /* a conversion on injected group would start a conversion also on */
+ /* regular group after ADC enabling. */
+ tmp_cr2 |= (hadc->Init.DataAlign |
+ hadc->Init.ExternalTrigConv |
+ ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode) );
+
+ /* Configuration of ADC: */
+ /* - scan mode */
+ /* - discontinuous mode disable/enable */
+ /* - discontinuous mode number of conversions */
+ tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode));
+
+ /* Enable discontinuous mode only if continuous mode is disabled */
+ /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */
+ /* discontinuous is set anyway, but will have no effect on ADC HW. */
+ if (hadc->Init.DiscontinuousConvMode == ENABLE)
+ {
+ if (hadc->Init.ContinuousConvMode == DISABLE)
+ {
+ /* Enable the selected ADC regular discontinuous mode */
+ /* Set the number of channels to be converted in discontinuous mode */
+ tmp_cr1 |= (ADC_CR1_DISCEN |
+ ADC_CR1_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion) );
+ }
+ else
+ {
+ /* ADC regular group discontinuous was intended to be enabled, */
+ /* but ADC regular group modes continuous and sequencer discontinuous */
+ /* cannot be enabled simultaneously. */
+
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ /* Set ADC error code to ADC IP internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ }
+ }
+
+ /* Update ADC configuration register CR1 with previous settings */
+ MODIFY_REG(hadc->Instance->CR1,
+ ADC_CR1_SCAN |
+ ADC_CR1_DISCEN |
+ ADC_CR1_DISCNUM ,
+ tmp_cr1 );
+
+ /* Update ADC configuration register CR2 with previous settings */
+ MODIFY_REG(hadc->Instance->CR2,
+ ADC_CR2_ALIGN |
+ ADC_CR2_EXTSEL |
+ ADC_CR2_EXTTRIG |
+ ADC_CR2_CONT ,
+ tmp_cr2 );
+
+ /* Configuration of regular group sequencer: */
+ /* - if scan mode is disabled, regular channels sequence length is set to */
+ /* 0x00: 1 channel converted (channel on regular rank 1U) */
+ /* Parameter "NbrOfConversion" is discarded. */
+ /* Note: Scan mode is present by hardware on this device and, if */
+ /* disabled, discards automatically nb of conversions. Anyway, nb of */
+ /* conversions is forced to 0x00 for alignment over all STM32 devices. */
+ /* - if scan mode is enabled, regular channels sequence length is set to */
+ /* parameter "NbrOfConversion" */
+ if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE)
+ {
+ tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion);
+ }
+
+ MODIFY_REG(hadc->Instance->SQR1,
+ ADC_SQR1_L ,
+ tmp_sqr1 );
+
+ /* Check back that ADC registers have effectively been configured to */
+ /* ensure of no potential problem of ADC core IP clocking. */
+ /* Check through register CR2 (excluding bits set in other functions: */
+ /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */
+ /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */
+ /* measurement path bit (TSVREFE). */
+ if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
+ ADC_CR2_SWSTART | ADC_CR2_JSWSTART |
+ ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL |
+ ADC_CR2_TSVREFE ))
+ == tmp_cr2)
+ {
+ /* Set ADC error code to none */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Set the ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_BUSY_INTERNAL,
+ HAL_ADC_STATE_READY);
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_BUSY_INTERNAL,
+ HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC IP internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Deinitialize the ADC peripheral registers to their default reset
+ * values, with deinitialization of the ADC MSP.
+ * @note For devices with several ADCs: reset of ADC common registers is done
+ * only if all ADCs sharing the same common group are disabled.
+ * If this is not the case, reset of these common parameters reset is
+ * bypassed without error reporting: it can be the intended behaviour in
+ * case of reset of a single ADC while the other ADCs sharing the same
+ * common group is still running.
+ * @note For devices with several ADCs: Global reset of all ADCs sharing a
+ * common group is possible.
+ * As this function is intended to reset a single ADC, to not impact
+ * other ADCs, instructions for global reset of multiple ADCs have been
+ * let commented below.
+ * If needed, the example code can be copied and uncommented into
+ * function HAL_ADC_MspDeInit().
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ ADC_Common_TypeDef *tmpADC_Common;
+ ADC_HandleTypeDef tmphadcSharingSameCommonRegister;
+
+ /* Check ADC handle */
+ if(hadc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
+
+ /* Stop potential conversion on going, on regular and injected groups */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+
+ /* Disable ADC peripheral if conversions are effectively stopped */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Flush register JSQR: queue sequencer reset when injected queue */
+ /* sequencer is enabled and ADC disabled. */
+ /* Enable injected queue sequencer after injected conversion stop */
+ SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM);
+
+ /* Disable the ADC peripheral */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_READY;
+ }
+ else
+ {
+ tmp_hal_status = HAL_ERROR;
+ }
+ }
+
+
+ /* Configuration of ADC parameters if previous preliminary actions are */
+ /* correctly completed. */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* ========== Reset ADC registers ========== */
+ /* Reset register IER */
+ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 | ADC_IT_AWD1 |
+ ADC_IT_JQOVF | ADC_IT_OVR |
+ ADC_IT_JEOS | ADC_IT_JEOC |
+ ADC_IT_EOS | ADC_IT_EOC |
+ ADC_IT_EOSMP | ADC_IT_RDY ) );
+
+ /* Reset register ISR */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 |
+ ADC_FLAG_JQOVF | ADC_FLAG_OVR |
+ ADC_FLAG_JEOS | ADC_FLAG_JEOC |
+ ADC_FLAG_EOS | ADC_FLAG_EOC |
+ ADC_FLAG_EOSMP | ADC_FLAG_RDY ) );
+
+ /* Reset register CR */
+ /* Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART are */
+ /* in access mode "read-set": no direct reset applicable. */
+ /* Reset Calibration mode to default setting (single ended): */
+ /* Disable voltage regulator: */
+ /* Note: Voltage regulator disable is conditioned to ADC state disabled: */
+ /* already done above. */
+ /* Note: Voltage regulator disable is intended for power saving. */
+ /* Sequence to disable voltage regulator: */
+ /* 1. Set the intermediate state before moving the ADC voltage regulator */
+ /* to disable state. */
+ CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN_1 | ADC_CR_ADVREGEN_0 | ADC_CR_ADCALDIF);
+ /* 2. Set ADVREGEN bits to 0x10U */
+ SET_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN_1);
+
+ /* Reset register CFGR */
+ CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |
+ ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |
+ ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |
+ ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |
+ ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN |
+ ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN );
+
+ /* Reset register SMPR1 */
+ CLEAR_BIT(hadc->Instance->SMPR1, ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |
+ ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |
+ ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 );
+
+ /* Reset register SMPR2 */
+ CLEAR_BIT(hadc->Instance->SMPR2, ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 |
+ ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 |
+ ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10 );
+
+ /* Reset register TR1 */
+ CLEAR_BIT(hadc->Instance->TR1, ADC_TR1_HT1 | ADC_TR1_LT1);
+
+ /* Reset register TR2 */
+ CLEAR_BIT(hadc->Instance->TR2, ADC_TR2_HT2 | ADC_TR2_LT2);
+
+ /* Reset register TR3 */
+ CLEAR_BIT(hadc->Instance->TR3, ADC_TR3_HT3 | ADC_TR3_LT3);
+
+ /* Reset register SQR1 */
+ CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 |
+ ADC_SQR1_SQ1 | ADC_SQR1_L);
+
+ /* Reset register SQR2 */
+ CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 |
+ ADC_SQR2_SQ6 | ADC_SQR2_SQ5);
+
+ /* Reset register SQR3 */
+ CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 |
+ ADC_SQR3_SQ11 | ADC_SQR3_SQ10);
+
+ /* Reset register SQR4 */
+ CLEAR_BIT(hadc->Instance->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
+
+ /* Reset register DR */
+ /* bits in access mode read only, no direct reset applicable*/
+
+ /* Reset register OFR1 */
+ CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1);
+ /* Reset register OFR2 */
+ CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2);
+ /* Reset register OFR3 */
+ CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3);
+ /* Reset register OFR4 */
+ CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4);
+
+ /* Reset registers JDR1, JDR2, JDR3, JDR4 */
+ /* bits in access mode read only, no direct reset applicable*/
+
+ /* Reset register AWD2CR */
+ CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH);
+
+ /* Reset register AWD3CR */
+ CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH);
+
+ /* Reset register DIFSEL */
+ CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_DIFSEL);
+
+ /* Reset register CALFACT */
+ CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
+
+
+
+
+
+
+ /* ========== Reset common ADC registers ========== */
+
+ /* Pointer to the common control register to which is belonging hadc */
+ /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
+ /* control registers) */
+ tmpADC_Common = ADC_COMMON_REGISTER(hadc);
+
+ /* Set handle of the other ADC sharing the same common register */
+ ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister);
+
+ /* Software is allowed to change common parameters only when all ADCs of */
+ /* the common group are disabled. */
+ if ((ADC_IS_ENABLE(hadc) == RESET) &&
+ ( (tmphadcSharingSameCommonRegister.Instance == NULL) ||
+ (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) )
+ {
+ /* Reset configuration of ADC common register CCR:
+ - clock mode: CKMODE
+ - multimode related parameters: MDMA, DMACFG, DELAY, MULTI (set into
+ HAL_ADCEx_MultiModeConfigChannel() )
+ - internal measurement paths: Vbat, temperature sensor, Vref (set into
+ HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() )
+ */
+ CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_CKMODE |
+ ADC_CCR_VBATEN |
+ ADC_CCR_TSEN |
+ ADC_CCR_VREFEN |
+ ADC_CCR_MDMA |
+ ADC_CCR_DMACFG |
+ ADC_CCR_DELAY |
+ ADC_CCR_MULTI );
+
+ /* Other ADC common registers (CSR, CDR) are in access mode read only,
+ no direct reset applicable */
+ }
+
+
+ /* ========== Hard reset and clock disable of ADC peripheral ========== */
+ /* Into HAL_ADC_MspDeInit(), ADC clock can be hard reset and disabled */
+ /* at RCC top level. */
+ /* Refer to header of this file for more details on clock disabling */
+ /* procedure. */
+
+
+ /* DeInit the low level hardware */
+ HAL_ADC_MspDeInit(hadc);
+
+ /* Set ADC error code to none */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Set ADC state */
+ hadc->State = HAL_ADC_STATE_RESET;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Deinitialize the ADC peripheral registers to its default reset values.
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check ADC handle */
+ if(hadc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
+
+ /* Stop potential conversion on going, on regular and injected groups */
+ /* Disable ADC peripheral */
+ tmp_hal_status = ADC_ConversionStop_Disable(hadc);
+
+
+ /* Configuration of ADC parameters if previous preliminary actions are */
+ /* correctly completed. */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* ========== Reset ADC registers ========== */
+ /* Reset register SR */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD | ADC_FLAG_JEOC | ADC_FLAG_EOC |
+ ADC_FLAG_JSTRT | ADC_FLAG_STRT));
+
+ /* Reset register CR1 */
+ CLEAR_BIT(hadc->Instance->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_DISCNUM |
+ ADC_CR1_JDISCEN | ADC_CR1_DISCEN | ADC_CR1_JAUTO |
+ ADC_CR1_AWDSGL | ADC_CR1_SCAN | ADC_CR1_JEOCIE |
+ ADC_CR1_AWDIE | ADC_CR1_EOCIE | ADC_CR1_AWDCH ));
+
+ /* Reset register CR2 */
+ CLEAR_BIT(hadc->Instance->CR2, (ADC_CR2_TSVREFE | ADC_CR2_SWSTART | ADC_CR2_JSWSTART |
+ ADC_CR2_EXTTRIG | ADC_CR2_EXTSEL | ADC_CR2_JEXTTRIG |
+ ADC_CR2_JEXTSEL | ADC_CR2_ALIGN | ADC_CR2_DMA |
+ ADC_CR2_RSTCAL | ADC_CR2_CAL | ADC_CR2_CONT |
+ ADC_CR2_ADON ));
+
+ /* Reset register SMPR1 */
+ CLEAR_BIT(hadc->Instance->SMPR1, (ADC_SMPR1_SMP18 | ADC_SMPR1_SMP17 | ADC_SMPR1_SMP15 |
+ ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13 |
+ ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10 ));
+
+ /* Reset register SMPR2 */
+ CLEAR_BIT(hadc->Instance->SMPR2, (ADC_SMPR2_SMP9 | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 |
+ ADC_SMPR2_SMP6 | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 |
+ ADC_SMPR2_SMP3 | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 |
+ ADC_SMPR2_SMP0 ));
+
+ /* Reset register JOFR1 */
+ CLEAR_BIT(hadc->Instance->JOFR1, ADC_JOFR1_JOFFSET1);
+ /* Reset register JOFR2 */
+ CLEAR_BIT(hadc->Instance->JOFR2, ADC_JOFR2_JOFFSET2);
+ /* Reset register JOFR3 */
+ CLEAR_BIT(hadc->Instance->JOFR3, ADC_JOFR3_JOFFSET3);
+ /* Reset register JOFR4 */
+ CLEAR_BIT(hadc->Instance->JOFR4, ADC_JOFR4_JOFFSET4);
+
+ /* Reset register HTR */
+ CLEAR_BIT(hadc->Instance->HTR, ADC_HTR_HT);
+ /* Reset register LTR */
+ CLEAR_BIT(hadc->Instance->LTR, ADC_LTR_LT);
+
+ /* Reset register SQR1 */
+ CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L |
+ ADC_SQR1_SQ16 | ADC_SQR1_SQ15 |
+ ADC_SQR1_SQ14 | ADC_SQR1_SQ13 );
+
+ /* Reset register SQR1 */
+ CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L |
+ ADC_SQR1_SQ16 | ADC_SQR1_SQ15 |
+ ADC_SQR1_SQ14 | ADC_SQR1_SQ13 );
+
+ /* Reset register SQR2 */
+ CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10 |
+ ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 );
+
+ /* Reset register SQR3 */
+ CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ6 | ADC_SQR3_SQ5 | ADC_SQR3_SQ4 |
+ ADC_SQR3_SQ3 | ADC_SQR3_SQ2 | ADC_SQR3_SQ1 );
+
+ /* Reset register JSQR */
+ CLEAR_BIT(hadc->Instance->JSQR, ADC_JSQR_JL |
+ ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 |
+ ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 );
+
+ /* Reset register JSQR */
+ CLEAR_BIT(hadc->Instance->JSQR, ADC_JSQR_JL |
+ ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 |
+ ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 );
+
+ /* Reset register DR */
+ /* bits in access mode read only, no direct reset applicable*/
+
+ /* Reset registers JDR1, JDR2, JDR3, JDR4 */
+ /* bits in access mode read only, no direct reset applicable*/
+
+ /* Reset VBAT measurement path, in case of enabled before by selecting */
+ /* channel ADC_CHANNEL_VBAT. */
+ SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_VBAT);
+
+
+ /* ========== Hard reset ADC peripheral ========== */
+ /* Performs a global reset of the entire ADC peripheral: ADC state is */
+ /* forced to a similar state after device power-on. */
+ /* If needed, copy-paste and uncomment the following reset code into */
+ /* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)": */
+ /* */
+ /* __HAL_RCC_ADC1_FORCE_RESET() */
+ /* __HAL_RCC_ADC1_RELEASE_RESET() */
+
+ /* DeInit the low level hardware */
+ HAL_ADC_MspDeInit(hadc);
+
+ /* Set ADC error code to none */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Set ADC state */
+ hadc->State = HAL_ADC_STATE_RESET;
+
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F373xC || STM32F378xx */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_Exported_Functions_Group2 ADCEx Input and Output operation functions
+ * @brief ADC Extended IO operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Start conversion of regular group.
+ (+) Stop conversion of regular group.
+ (+) Poll for conversion complete on regular group.
+ (+) Poll for conversion event.
+ (+) Get result of regular channel conversion.
+ (+) Start conversion of regular group and enable interruptions.
+ (+) Stop conversion of regular group and disable interruptions.
+ (+) Handle ADC interrupt request
+ (+) Start conversion of regular group and enable DMA transfer.
+ (+) Stop conversion of regular group and disable ADC DMA transfer.
+
+ (+) Start conversion of injected group.
+ (+) Stop conversion of injected group.
+ (+) Poll for conversion complete on injected group.
+ (+) Get result of injected channel conversion.
+ (+) Start conversion of injected group and enable interruptions.
+ (+) Stop conversion of injected group and disable interruptions.
+
+ (+) Start multimode and enable DMA transfer.
+ (+) Stop multimode and disable ADC DMA transfer.
+ (+) Get result of multimode conversion.
+
+ (+) Perform the ADC self-calibration for single or differential ending.
+ (+) Get calibration factors for single or differential ending.
+ (+) Set calibration factors for single or differential ending.
+
+@endverbatim
+ * @{
+ */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Enables ADC, starts conversion of regular group.
+ * Interruptions enabled in this function: None.
+ * @note Case of multimode enabled (for devices with several ADCs):
+ * if ADC is slave, ADC is enabled only (conversion is not started).
+ * if ADC is master, ADC is enabled and multimode conversion is started.
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Perform ADC enable and conversion start if no conversion is on going */
+ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+ {
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Enable the ADC peripheral */
+ tmp_hal_status = ADC_Enable(hadc);
+
+ /* Start conversion if ADC is effectively enabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ /* - Clear state bitfield related to regular group conversion results */
+ /* - Set state bitfield related to regular operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
+ HAL_ADC_STATE_REG_BUSY);
+
+ /* Set group injected state (from auto-injection) and multimode state */
+ /* for all cases of multimode: independent mode, multimode ADC master */
+ /* or multimode ADC slave (for devices with several ADCs): */
+ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
+ {
+ /* Set ADC state (ADC independent or master) */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+
+ /* If conversions on group regular are also triggering group injected,*/
+ /* update ADC state. */
+ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET)
+ {
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+ }
+ }
+ else
+ {
+ /* Set ADC state (ADC slave) */
+ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+
+ /* If conversions on group regular are also triggering group injected,*/
+ /* update ADC state. */
+ if (ADC_MULTIMODE_AUTO_INJECTED(hadc))
+ {
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+ }
+ }
+
+ /* State machine update: Check if an injected conversion is ongoing */
+ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ {
+ /* Reset ADC error code fields related to conversions on group regular*/
+ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
+ }
+ else
+ {
+ /* Reset ADC all error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Clear regular group conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC */
+ /* operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+
+ /* Enable conversion of regular group. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ /* Case of multimode enabled (for devices with several ADCs): */
+ /* - if ADC is slave, ADC is enabled only (conversion is not started). */
+ /* - if ADC is master, ADC is enabled and conversion is started. */
+ if (ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(hadc))
+ {
+ SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
+ }
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+ }
+ }
+ else
+ {
+ tmp_hal_status = HAL_BUSY;
+ }
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Enables ADC, starts conversion of regular group.
+ * Interruptions enabled in this function: None.
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Enable the ADC peripheral */
+ tmp_hal_status = ADC_Enable(hadc);
+
+ /* Start conversion if ADC is effectively enabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ /* - Clear state bitfield related to regular group conversion results */
+ /* - Set state bitfield related to regular operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC,
+ HAL_ADC_STATE_REG_BUSY);
+
+ /* Set group injected state (from auto-injection) */
+ /* If conversions on group regular are also triggering group injected, */
+ /* update ADC state. */
+ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
+ {
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+ }
+
+ /* State machine update: Check if an injected conversion is ongoing */
+ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ {
+ /* Reset ADC error code fields related to conversions on group regular */
+ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
+ }
+ else
+ {
+ /* Reset ADC all error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Clear regular group conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
+
+ /* Enable conversion of regular group. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ /* Note: Alternate trigger for single conversion could be to force an */
+ /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/
+ if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
+ {
+ /* Start ADC conversion on regular group with SW start */
+ SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
+ }
+ else
+ {
+ /* Start ADC conversion on regular group with external trigger */
+ SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
+ }
+ }
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Stop ADC conversion of both groups regular and injected,
+ * disable ADC peripheral.
+ * @note ADC peripheral disable is forcing interruption of potential
+ * conversion on injected group. If injected group is under use,
+ * it should be preliminarily stopped using function
+ * @ref HAL_ADCEx_InjectedStop().
+ * To stop ADC conversion only on ADC group regular
+ * while letting ADC group injected conversions running,
+ * use function @ref HAL_ADCEx_RegularStop().
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* 1. Stop potential conversion on going, on regular and injected groups */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+
+ /* Disable ADC peripheral if conversions are effectively stopped */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* 2. Disable the ADC peripheral */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Stop ADC conversion of regular group (and injected channels in
+ * case of auto_injection mode), disable ADC peripheral.
+ * @note ADC peripheral disable is forcing interruption of potential
+ * conversion on injected group. If injected group is under use, it
+ * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Stop potential conversion on going, on regular and injected groups */
+ /* Disable ADC peripheral */
+ tmp_hal_status = ADC_ConversionStop_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Wait for regular group conversion to be completed.
+ * @note ADC conversion flags EOS (end of sequence) and EOC (end of
+ * conversion) are cleared by this function, with an exception:
+ * if low power feature "LowPowerAutoWait" is enabled, flags are
+ * not cleared to not interfere with this feature until data register
+ * is read using function HAL_ADC_GetValue().
+ * @note This function cannot be used in a particular setup: ADC configured
+ * in DMA mode and polling for end of each conversion (ADC init
+ * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
+ * In this case, DMA resets the flag EOC and polling cannot be
+ * performed on each conversion. Nevertheless, polling can still
+ * be performed on the complete sequence (ADC init
+ * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV).
+ * @param hadc ADC handle
+ * @param Timeout Timeout value in millisecond.
+ * @note Depending on init parameter "EOCSelection", flags EOS or EOC is
+ * checked and cleared depending on autodelay status (bit AUTDLY).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
+{
+ uint32_t tickstart;
+ uint32_t tmp_Flag_EOC;
+ ADC_Common_TypeDef *tmpADC_Common;
+ uint32_t tmp_cfgr = 0x0U;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+/* If end of conversion selected to end of sequence */
+ if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
+ {
+ tmp_Flag_EOC = ADC_FLAG_EOS;
+ }
+ /* If end of conversion selected to end of each conversion */
+ else /* ADC_EOC_SINGLE_CONV */
+ {
+ /* Verification that ADC configuration is compliant with polling for */
+ /* each conversion: */
+ /* Particular case is ADC configured in DMA mode and ADC sequencer with */
+ /* several ranks and polling for end of each conversion. */
+ /* For code simplicity sake, this particular case is generalized to */
+ /* ADC configured in DMA mode and and polling for end of each conversion. */
+
+ /* Pointer to the common control register to which is belonging hadc */
+ /* (Depending on STM32F3 product, there may have up to 4 ADC and 2 common */
+ /* control registers) */
+ tmpADC_Common = ADC_COMMON_REGISTER(hadc);
+
+ /* Check DMA configuration, depending on MultiMode set or not */
+ if (READ_BIT(tmpADC_Common->CCR, ADC_CCR_MULTI) == ADC_MODE_INDEPENDENT)
+ {
+ if (HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_DMAEN))
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* MultiMode is enabled, Common Control Register MDMA bits must be checked */
+ if (READ_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA) != RESET)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+ }
+
+ tmp_Flag_EOC = (ADC_FLAG_EOC | ADC_FLAG_EOS);
+
+ }
+
+ /* Get relevant register CFGR in ADC instance of ADC master or slave */
+ /* in function of multimode state (for devices with multimode */
+ /* available). */
+ if(ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
+ {
+ tmp_cfgr = READ_REG(hadc->Instance->CFGR);
+ }
+ else
+ {
+ tmp_cfgr = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR);
+ }
+
+ /* Get tick count */
+ tickstart = HAL_GetTick();
+
+ /* Wait until End of Conversion or End of Sequence flag is raised */
+ while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC))
+ {
+ /* Check if timeout is disabled (set to infinite wait) */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ /* Update ADC state machine to timeout */
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Update ADC state machine */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+
+ /* Determine whether any further conversion upcoming on group regular */
+ /* by external trigger, continuous mode or scan sequence on going. */
+ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+ (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == RESET) )
+ {
+ /* If End of Sequence is reached, disable interrupts */
+ if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
+ {
+ /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
+ /* ADSTART==0 (no conversion on going) */
+ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+ {
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+ else
+ {
+ /* Change ADC state to error state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ /* Set ADC error code to ADC IP internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ }
+ }
+ }
+
+ /* Clear end of conversion flag of regular group if low power feature */
+ /* "LowPowerAutoWait " is disabled, to not interfere with this feature */
+ /* until data register is read using function HAL_ADC_GetValue(). */
+ if (READ_BIT (tmp_cfgr, ADC_CFGR_AUTDLY) == RESET)
+ {
+ /* Clear regular group conversion flag */
+ /* (EOC or EOS depending on HAL ADC initialization parameter) */
+ __HAL_ADC_CLEAR_FLAG(hadc, tmp_Flag_EOC);
+ }
+
+ /* Return ADC state */
+ return HAL_OK;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Wait for regular group conversion to be completed.
+ * @note This function cannot be used in a particular setup: ADC configured
+ * in DMA mode.
+ * In this case, DMA resets the flag EOC and polling cannot be
+ * performed on each conversion.
+ * @note On STM32F37x devices, limitation in case of sequencer enabled
+ * (several ranks selected): polling cannot be done on each
+ * conversion inside the sequence. In this case, polling is replaced by
+ * wait for maximum conversion time.
+ * @param hadc ADC handle
+ * @param Timeout Timeout value in millisecond.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
+{
+ uint32_t tickstart;
+
+ /* Variables for polling in case of scan mode enabled */
+ uint32_t Conversion_Timeout_CPU_cycles_max = 0U;
+ uint32_t Conversion_Timeout_CPU_cycles = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Verification that ADC configuration is compliant with polling for */
+ /* each conversion: */
+ /* Particular case is ADC configured in DMA mode */
+ if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA))
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+
+ /* Get tick count */
+ tickstart = HAL_GetTick();
+
+ /* Polling for end of conversion: differentiation if single/sequence */
+ /* conversion. */
+ /* - If single conversion for regular group (Scan mode disabled or enabled */
+ /* with NbrOfConversion =1U), flag EOC is used to determine the */
+ /* conversion completion. */
+ /* - If sequence conversion for regular group (scan mode enabled and */
+ /* NbrOfConversion >=2U), flag EOC is set only at the end of the */
+ /* sequence. */
+ /* To poll for each conversion, the maximum conversion time is computed */
+ /* from ADC conversion time (selected sampling time + conversion time of */
+ /* 12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on */
+ /* settings, conversion time range can be from 28 to 32256 CPU cycles). */
+ /* As flag EOC is not set after each conversion, no timeout status can */
+ /* be set. */
+ if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) &&
+ HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) )
+ {
+ /* Wait until End of Conversion flag is raised */
+ while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC))
+ {
+ /* Check if timeout is disabled (set to infinite wait) */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ /* Update ADC state machine to timeout */
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else
+ {
+ /* Replace polling by wait for maximum conversion time */
+ /* Calculation of CPU cycles corresponding to ADC conversion cycles. */
+ /* Retrieve ADC clock prescaler and ADC maximum conversion cycles on all */
+ /* channels. */
+ Conversion_Timeout_CPU_cycles_max = ADC_CLOCK_PRESCALER_RANGE() ;
+ Conversion_Timeout_CPU_cycles_max *= ADC_CONVCYCLES_MAX_RANGE(hadc);
+
+ /* Poll with maximum conversion time */
+ while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max)
+ {
+ /* Check if timeout is disabled (set to infinite wait) */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Update ADC state machine to timeout */
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ Conversion_Timeout_CPU_cycles ++;
+ }
+ }
+
+ /* Clear regular group conversion flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
+
+ /* Update ADC state machine */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+
+ /* Determine whether any further conversion upcoming on group regular */
+ /* by external trigger, continuous mode or scan sequence on going. */
+ /* Note: On STM32F37x devices, in case of sequencer enabled */
+ /* (several ranks selected), end of conversion flag is raised */
+ /* at the end of the sequence. */
+ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+ (hadc->Init.ContinuousConvMode == DISABLE) )
+ {
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+
+ /* Return ADC state */
+ return HAL_OK;
+}
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Poll for conversion event.
+ * @param hadc ADC handle
+ * @param EventType the ADC event type.
+ * This parameter can be one of the following values:
+ * @arg ADC_AWD1_EVENT: ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices)
+ * @arg ADC_AWD2_EVENT: ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 families)
+ * @arg ADC_AWD3_EVENT: ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families)
+ * @arg ADC_OVR_EVENT: ADC Overrun event
+ * @arg ADC_JQOVF_EVENT: ADC Injected context queue overflow event
+ * @param Timeout Timeout value in millisecond.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
+{
+ uint32_t tickstart;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_EVENT_TYPE(EventType));
+
+ /* Get start tick count */
+ tickstart = HAL_GetTick();
+
+ /* Check selected event flag */
+ while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
+ {
+ /* Check if timeout is disabled (set to infinite wait) */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Update ADC state machine to timeout */
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+
+ switch(EventType)
+ {
+ /* Analog watchdog (level out of window) event */
+ /* Note: In case of several analog watchdog enabled, if needed to know */
+ /* which one triggered and on which ADCx, test ADC state of analog watchdog */
+ /* flags HAL_ADC_STATE_AWD1/2U/3 using function "HAL_ADC_GetState()". */
+ /* For example: */
+ /* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1)) " */
+ /* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD2)) " */
+ /* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD3)) " */
+ /* Check analog watchdog 1 flag */
+ case ADC_AWD_EVENT:
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+
+ /* Clear ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
+ break;
+
+ /* Check analog watchdog 2 flag */
+ case ADC_AWD2_EVENT:
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
+
+ /* Clear ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
+ break;
+
+ /* Check analog watchdog 3 flag */
+ case ADC_AWD3_EVENT:
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
+
+ /* Clear ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
+ break;
+
+ /* Injected context queue overflow event */
+ case ADC_JQOVF_EVENT:
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
+
+ /* Set ADC error code to Injected context queue overflow */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
+
+ /* Clear ADC Injected context queue overflow flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
+ break;
+
+ /* Overrun event */
+ default: /* Case ADC_OVR_EVENT */
+ /* If overrun is set to overwrite previous data, overrun event is not */
+ /* considered as an error. */
+ /* (cf ref manual "Managing conversions without using the DMA and without */
+ /* overrun ") */
+ if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
+
+ /* Set ADC error code to overrun */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
+ }
+
+ /* Clear ADC Overrun flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+ break;
+ }
+
+ /* Return ADC state */
+ return HAL_OK;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Poll for conversion event.
+ * @param hadc ADC handle
+ * @param EventType the ADC event type.
+ * This parameter can be one of the following values:
+ * @arg ADC_AWD_EVENT: ADC Analog watchdog event.
+ * @param Timeout Timeout value in millisecond.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
+{
+ uint32_t tickstart;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_EVENT_TYPE(EventType));
+
+ tickstart = HAL_GetTick();
+
+ /* Check selected event flag */
+ while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
+ {
+ /* Check if timeout is disabled (set to infinite wait) */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ /* Update ADC state machine to timeout */
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /* Analog watchdog (level out of window) event */
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+
+ /* Clear ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
+
+ /* Return ADC state */
+ return HAL_OK;
+}
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Enables ADC, starts conversion of regular group with interruption.
+ * Interruptions enabled in this function:
+ * - EOC (end of conversion of regular group) or EOS (end of
+ * sequence of regular group) depending on ADC initialization
+ * parameter "EOCSelection"
+ * - overrun, depending on ADC initialization parameter "Overrun"
+ * Each of these interruptions has its dedicated callback function.
+ * @note Case of multimode enabled (for devices with several ADCs): This
+ * function must be called for ADC slave first, then ADC master.
+ * For ADC slave, ADC is enabled only (conversion is not started).
+ * For ADC master, ADC is enabled and multimode conversion is started.
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Perform ADC enable and conversion start if no conversion is on going */
+ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+ {
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Enable the ADC peripheral */
+ tmp_hal_status = ADC_Enable(hadc);
+
+ /* Start conversion if ADC is effectively enabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ /* - Clear state bitfield related to regular group conversion results */
+ /* - Set state bitfield related to regular operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
+ HAL_ADC_STATE_REG_BUSY);
+
+ /* Set group injected state (from auto-injection) and multimode state */
+ /* for all cases of multimode: independent mode, multimode ADC master */
+ /* or multimode ADC slave (for devices with several ADCs): */
+ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
+ {
+ /* Set ADC state (ADC independent or master) */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+
+ /* If conversions on group regular are also triggering group injected,*/
+ /* update ADC state. */
+ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET)
+ {
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+ }
+ }
+ else
+ {
+ /* Set ADC state (ADC slave) */
+ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+
+ /* If conversions on group regular are also triggering group injected,*/
+ /* update ADC state. */
+ if (ADC_MULTIMODE_AUTO_INJECTED(hadc))
+ {
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+ }
+ }
+
+ /* State machine update: Check if an injected conversion is ongoing */
+ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ {
+ /* Reset ADC error code fields related to conversions on group regular*/
+ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
+ }
+ else
+ {
+ /* Reset ADC all error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Clear regular group conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC */
+ /* operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+
+ /* Enable ADC end of conversion interrupt */
+ /* Enable ADC overrun interrupt */
+ switch(hadc->Init.EOCSelection)
+ {
+ case ADC_EOC_SEQ_CONV:
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
+ __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOS));
+ break;
+ /* case ADC_EOC_SINGLE_CONV */
+ default:
+ __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS));
+ break;
+ }
+
+ /* If overrun is set to overwrite previous data (default setting), */
+ /* overrun interrupt is not activated (overrun event is not considered */
+ /* as an error). */
+ /* (cf ref manual "Managing conversions without using the DMA and */
+ /* without overrun ") */
+ if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
+ {
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+ }
+
+ /* Enable conversion of regular group. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ /* Case of multimode enabled (for devices with several ADCs): */
+ /* - if ADC is slave, ADC is enabled only (conversion is not started). */
+ /* - if ADC is master, ADC is enabled and conversion is started. */
+ if (ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(hadc))
+ {
+ SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
+ }
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+ }
+ }
+ else
+ {
+ tmp_hal_status = HAL_BUSY;
+ }
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Enables ADC, starts conversion of regular group with interruption.
+ * Interruptions enabled in this function:
+ * - EOC (end of conversion of regular group)
+ * Each of these interruptions has its dedicated callback function.
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Enable the ADC peripheral */
+ tmp_hal_status = ADC_Enable(hadc);
+
+ /* Start conversion if ADC is effectively enabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ /* - Clear state bitfield related to regular group conversion results */
+ /* - Set state bitfield related to regular operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC,
+ HAL_ADC_STATE_REG_BUSY);
+
+ /* Set group injected state (from auto-injection) */
+ /* If conversions on group regular are also triggering group injected, */
+ /* update ADC state. */
+ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
+ {
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+ }
+
+ /* State machine update: Check if an injected conversion is ongoing */
+ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ {
+ /* Reset ADC error code fields related to conversions on group regular */
+ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
+ }
+ else
+ {
+ /* Reset ADC all error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Clear regular group conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
+
+ /* Enable end of conversion interrupt for regular group */
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
+
+ /* Enable conversion of regular group. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
+ {
+ /* Start ADC conversion on regular group with SW start */
+ SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
+ }
+ else
+ {
+ /* Start ADC conversion on regular group with external trigger */
+ SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
+ }
+ }
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Stop ADC conversion of both groups regular and injected,
+ * disable ADC peripheral.
+ * Interruptions disabled in this function:
+ * - EOC (end of conversion of regular group) and EOS (end of
+ * sequence of regular group)
+ * - overrun
+ * @note ADC peripheral disable is forcing interruption of potential
+ * conversion on injected group. If injected group is under use,
+ * it should be preliminarily stopped using function
+ * @ref HAL_ADCEx_InjectedStop().
+ * To stop ADC conversion only on ADC group regular
+ * while letting ADC group injected conversions running,
+ * use function @ref HAL_ADCEx_RegularStop_IT().
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* 1. Stop potential conversion on going, on regular and injected groups */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+
+ /* Disable ADC peripheral if conversions are effectively stopped */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Disable ADC end of conversion interrupt for regular group */
+ /* Disable ADC overrun interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
+
+ /* 2. Disable the ADC peripheral */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Stop ADC conversion of regular group (and injected group in
+ * case of auto_injection mode), disable interrution of
+ * end-of-conversion, disable ADC peripheral.
+ * @param hadc ADC handle
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Stop potential conversion on going, on regular and injected groups */
+ /* Disable ADC peripheral */
+ tmp_hal_status = ADC_ConversionStop_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Disable ADC end of conversion interrupt for regular group */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
+
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Enables ADC, starts conversion of regular group and transfers result
+ * through DMA.
+ * Interruptions enabled in this function:
+ * - DMA transfer complete
+ * - DMA half transfer
+ * - overrun
+ * Each of these interruptions has its dedicated callback function.
+ * @note Case of multimode enabled (for devices with several ADCs): This
+ * function is for single-ADC mode only. For multimode, use the
+ * dedicated MultimodeStart function.
+ * @param hadc ADC handle
+ * @param pData The destination Buffer address.
+ * @param Length The length of data to be transferred from ADC peripheral to memory.
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Perform ADC enable and conversion start if no conversion is on going */
+ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+ {
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Verification if multimode is disabled (for devices with several ADC) */
+ /* If multimode is enabled, dedicated function multimode conversion */
+ /* start DMA must be used. */
+ if(ADC_COMMON_CCR_MULTI(hadc) == RESET)
+ {
+ /* Enable the ADC peripheral */
+ tmp_hal_status = ADC_Enable(hadc);
+
+ /* Start conversion if ADC is effectively enabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ /* - Clear state bitfield related to regular group conversion results */
+ /* - Set state bitfield related to regular operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
+ HAL_ADC_STATE_REG_BUSY);
+
+ /* Set group injected state (from auto-injection) and multimode state */
+ /* for all cases of multimode: independent mode, multimode ADC master */
+ /* or multimode ADC slave (for devices with several ADCs): */
+ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
+ {
+ /* Set ADC state (ADC independent or master) */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+
+ /* If conversions on group regular are also triggering group injected,*/
+ /* update ADC state. */
+ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET)
+ {
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+ }
+ }
+ else
+ {
+ /* Set ADC state (ADC slave) */
+ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+
+ /* If conversions on group regular are also triggering group injected,*/
+ /* update ADC state. */
+ if (ADC_MULTIMODE_AUTO_INJECTED(hadc))
+ {
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+ }
+ }
+
+ /* State machine update: Check if an injected conversion is ongoing */
+ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ {
+ /* Reset ADC error code fields related to conversions on group regular*/
+ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
+ }
+ else
+ {
+ /* Reset ADC all error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+
+ /* Set the DMA transfer complete callback */
+ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
+
+ /* Set the DMA half transfer complete callback */
+ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
+
+ /* Set the DMA error callback */
+ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
+
+
+ /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
+ /* start (in case of SW start): */
+
+ /* Clear regular group conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC */
+ /* operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+
+ /* Enable ADC overrun interrupt */
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+
+ /* Enable ADC DMA mode */
+ SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
+
+ /* Start the DMA channel */
+ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
+
+ /* Enable conversion of regular group. */
+ /* If software start has been selected, conversion starts immediately.*/
+ /* If external trigger has been selected, conversion will start at */
+ /* next trigger event. */
+ SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
+
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+ }
+ }
+ else
+ {
+ tmp_hal_status = HAL_ERROR;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+ }
+ }
+ else
+ {
+ tmp_hal_status = HAL_BUSY;
+ }
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Enables ADC, starts conversion of regular group and transfers result
+ * through DMA.
+ * Interruptions enabled in this function:
+ * - DMA transfer complete
+ * - DMA half transfer
+ * Each of these interruptions has its dedicated callback function.
+ * @note For devices with several ADCs: This function is for single-ADC mode
+ * only. For multimode, use the dedicated MultimodeStart function.
+ * @param hadc ADC handle
+ * @param pData The destination Buffer address.
+ * @param Length The length of data to be transferred from ADC peripheral to memory.
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Enable the ADC peripheral */
+ tmp_hal_status = ADC_Enable(hadc);
+
+ /* Start conversion if ADC is effectively enabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ /* - Clear state bitfield related to regular group conversion results */
+ /* - Set state bitfield related to regular operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC,
+ HAL_ADC_STATE_REG_BUSY);
+
+ /* Set group injected state (from auto-injection) */
+ /* If conversions on group regular are also triggering group injected, */
+ /* update ADC state. */
+ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
+ {
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+ }
+
+ /* State machine update: Check if an injected conversion is ongoing */
+ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ {
+ /* Reset ADC error code fields related to conversions on group regular */
+ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
+ }
+ else
+ {
+ /* Reset ADC all error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Set the DMA transfer complete callback */
+ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
+
+ /* Set the DMA half transfer complete callback */
+ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
+
+ /* Set the DMA error callback */
+ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
+
+
+ /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
+ /* start (in case of SW start): */
+
+ /* Clear regular group conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
+
+ /* Enable ADC DMA mode */
+ hadc->Instance->CR2 |= ADC_CR2_DMA;
+
+ /* Start the DMA channel */
+ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
+
+ /* Enable conversion of regular group. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ /* Note: Alternate trigger for single conversion could be to force an */
+ /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/
+ if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
+ {
+ /* Start ADC conversion on regular group with SW start */
+ SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
+ }
+ else
+ {
+ /* Start ADC conversion on regular group with external trigger */
+ SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
+ }
+ }
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Stop ADC conversion of both groups regular and injected,
+ * disable ADC DMA transfer, disable ADC peripheral.
+ * Interruptions disabled in this function:
+ * - DMA transfer complete
+ * - DMA half transfer
+ * - overrun
+ * @note ADC peripheral disable is forcing interruption of potential
+ * conversion on injected group. If injected group is under use,
+ * it should be preliminarily stopped using function
+ * @ref HAL_ADCEx_InjectedStop().
+ * To stop ADC conversion only on ADC group regular
+ * while letting ADC group injected conversions running,
+ * use function @ref HAL_ADCEx_RegularStop_DMA().
+ * @note Case of multimode enabled (for devices with several ADCs): This
+ * function is for single-ADC mode only. For multimode, use the
+ * dedicated MultimodeStop function.
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* 1. Stop potential conversion on going, on regular and injected groups */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+
+ /* Disable ADC peripheral if conversions are effectively stopped */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
+ CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
+
+ /* Disable the DMA channel (in case of DMA in circular mode or stop while */
+ /* while DMA transfer is on going) */
+ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+
+ /* Check if DMA channel effectively disabled */
+ if (tmp_hal_status != HAL_OK)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+ }
+
+ /* Disable ADC overrun interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+
+ /* 2. Disable the ADC peripheral */
+ /* Update "tmp_hal_status" only if DMA channel disabling passed, */
+ /* to retain a potential failing status. */
+ if (tmp_hal_status == HAL_OK)
+ {
+ tmp_hal_status = ADC_Disable(hadc);
+ }
+ else
+ {
+ ADC_Disable(hadc);
+ }
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Stop ADC conversion of regular group (and injected group in
+ * case of auto_injection mode), disable ADC DMA transfer, disable
+ * ADC peripheral.
+ * @note ADC peripheral disable is forcing interruption of potential
+ * conversion on injected group. If injected group is under use, it
+ * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
+ * @note For devices with several ADCs: This function is for single-ADC mode
+ * only. For multimode, use the dedicated MultimodeStop function.
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Stop potential conversion on going, on regular and injected groups */
+ /* Disable ADC peripheral */
+ tmp_hal_status = ADC_ConversionStop_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Disable ADC DMA mode */
+ hadc->Instance->CR2 &= ~ADC_CR2_DMA;
+
+ /* Disable the DMA channel (in case of DMA in circular mode or stop while */
+ /* while DMA transfer is on going) */
+ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+
+ /* Check if DMA channel effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+ }
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Get ADC regular group conversion result.
+ * @note Reading register DR automatically clears ADC flag EOC
+ * (ADC group regular end of unitary conversion).
+ * @note This function does not clear ADC flag EOS
+ * (ADC group regular end of sequence conversion).
+ * Occurrence of flag EOS rising:
+ * - If sequencer is composed of 1 rank, flag EOS is equivalent
+ * to flag EOC.
+ * - If sequencer is composed of several ranks, during the scan
+ * sequence flag EOC only is raised, at the end of the scan sequence
+ * both flags EOC and EOS are raised.
+ * To clear this flag, either use function:
+ * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
+ * model polling: @ref HAL_ADC_PollForConversion()
+ * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
+ * @param hadc ADC handle
+ * @retval ADC group regular conversion data
+ */
+uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Note: ADC flag EOC is not cleared here by software because */
+ /* automatically cleared by hardware when reading register DR. */
+
+ /* Return ADC converted value */
+ return hadc->Instance->DR;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Get ADC regular group conversion result.
+ * @note Reading register DR automatically clears ADC flag EOC
+ * (ADC group regular end of unitary conversion).
+ * @note This function does not clear ADC flag EOS
+ * (ADC group regular end of sequence conversion).
+ * Occurrence of flag EOS rising:
+ * - If sequencer is composed of 1 rank, flag EOS is equivalent
+ * to flag EOC.
+ * - If sequencer is composed of several ranks, during the scan
+ * sequence flag EOC only is raised, at the end of the scan sequence
+ * both flags EOC and EOS are raised.
+ * To clear this flag, either use function:
+ * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
+ * model polling: @ref HAL_ADC_PollForConversion()
+ * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
+ * @param hadc ADC handle
+ * @retval ADC group regular conversion data
+ */
+uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Note: EOC flag is not cleared here by software because automatically */
+ /* cleared by hardware when reading register DR. */
+
+ /* Return ADC converted value */
+ return hadc->Instance->DR;
+}
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Handles ADC interrupt request.
+ * @param hadc ADC handle
+ * @retval None
+ */
+void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
+{
+ uint32_t overrun_error = 0U; /* flag set if overrun occurrence has to be considered as an error */
+ ADC_Common_TypeDef *tmpADC_Common;
+ uint32_t tmp_cfgr = 0x0U;
+ uint32_t tmp_cfgr_jqm = 0x0U;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+ assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
+
+ /* ========== Check End of Conversion flag for regular group ========== */
+ if( (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC)) ||
+ (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOS)) )
+ {
+ /* Update state machine on conversion status if not in error state */
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+ }
+
+ /* Get relevant register CFGR in ADC instance of ADC master or slave */
+ /* in function of multimode state (for devices with multimode */
+ /* available). */
+ if (ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(hadc))
+ {
+ tmp_cfgr = READ_REG(hadc->Instance->CFGR);
+ }
+ else
+ {
+ tmp_cfgr = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR);
+ }
+
+ /* Disable interruption if no further conversion upcoming by regular */
+ /* external trigger or by continuous mode, */
+ /* and if scan sequence if completed. */
+ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+ (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == RESET) )
+ {
+ /* If End of Sequence is reached, disable interrupts */
+ if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
+ {
+ /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
+ /* ADSTART==0 (no conversion on going) */
+ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+ {
+ /* Disable ADC end of sequence conversion interrupt */
+ /* Note: Overrun interrupt was enabled with EOC interrupt in */
+ /* HAL_Start_IT(), but is not disabled here because can be used */
+ /* by overrun IRQ process below. */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
+
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC IP internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ }
+ }
+ }
+
+ /* Conversion complete callback */
+ /* Note: into callback, to determine if conversion has been triggered */
+ /* from EOC or EOS, possibility to use: */
+ /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */
+ HAL_ADC_ConvCpltCallback(hadc);
+
+
+ /* Clear regular group conversion flag */
+ /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */
+ /* conversion flags clear induces the release of the preserved */
+ /* data. */
+ /* Therefore, if the preserved data value is needed, it must be */
+ /* read preliminarily into HAL_ADC_ConvCpltCallback(). */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS) );
+ }
+
+
+ /* ========== Check End of Conversion flag for injected group ========== */
+ if( (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC)) ||
+ (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOS)) )
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
+
+ /* Get relevant register CFGR in ADC instance of ADC master or slave */
+ /* in function of multimode state (for devices with multimode */
+ /* available). */
+ if (ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(hadc))
+ {
+ tmp_cfgr = READ_REG(hadc->Instance->CFGR);
+ }
+ else
+ {
+ tmp_cfgr = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR);
+ }
+
+ /* Disable interruption if no further conversion upcoming by injected */
+ /* external trigger or by automatic injected conversion with regular */
+ /* group having no further conversion upcoming (same conditions as */
+ /* regular group interruption disabling above), */
+ /* and if injected scan sequence is completed. */
+ if(ADC_IS_SOFTWARE_START_INJECTED(hadc) ||
+ ((READ_BIT (tmp_cfgr, ADC_CFGR_JAUTO) == RESET) &&
+ (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+ (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == RESET) ) ) )
+ {
+ /* If End of Sequence is reached, disable interrupts */
+ if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
+ {
+
+ /* Get relevant register CFGR in ADC instance of ADC master or slave */
+ /* in function of multimode state (for devices with multimode */
+ /* available). */
+ if (ADC_NONMULTIMODE_INJ_OR_MULTIMODEMASTER(hadc))
+ {
+ tmp_cfgr_jqm = READ_REG(hadc->Instance->CFGR);
+ }
+ else
+ {
+ tmp_cfgr_jqm = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR);
+ }
+
+ /* Particular case if injected contexts queue is enabled: */
+ /* when the last context has been fully processed, JSQR is reset */
+ /* by the hardware. Even if no injected conversion is planned to come */
+ /* (queue empty, triggers are ignored), it can start again */
+ /* immediately after setting a new context (JADSTART is still set). */
+ /* Therefore, state of HAL ADC injected group is kept to busy. */
+ if(READ_BIT(tmp_cfgr_jqm, ADC_CFGR_JQM) == RESET)
+ {
+ /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */
+ /* JADSTART==0 (no conversion on going) */
+ if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
+ {
+ /* Disable ADC end of sequence conversion interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
+
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC IP internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ }
+ }
+ }
+ }
+
+ /* Conversion complete callback */
+ /* Note: into callback, to determine if conversion has been triggered */
+ /* from JEOC or JEOS, possibility to use: */
+ /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) " */
+ HAL_ADCEx_InjectedConvCpltCallback(hadc);
+
+ /* Clear injected group conversion flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS);
+ }
+
+ /* ========== Check analog watchdog 1 flag ========== */
+ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD1) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD1))
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+
+ /* Level out of window 1 callback */
+ HAL_ADC_LevelOutOfWindowCallback(hadc);
+ /* Clear ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
+ }
+
+ /* ========== Check analog watchdog 2 flag ========== */
+ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD2) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD2))
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
+
+ /* Level out of window 2 callback */
+ HAL_ADCEx_LevelOutOfWindow2Callback(hadc);
+ /* Clear ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
+ }
+
+ /* ========== Check analog watchdog 3 flag ========== */
+ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD3) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD3))
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
+
+ /* Level out of window 3 callback */
+ HAL_ADCEx_LevelOutOfWindow3Callback(hadc);
+ /* Clear ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
+ }
+
+ /* ========== Check Overrun flag ========== */
+ if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR))
+ {
+ /* If overrun is set to overwrite previous data (default setting), */
+ /* overrun event is not considered as an error. */
+ /* (cf ref manual "Managing conversions without using the DMA and */
+ /* without overrun ") */
+ /* Exception for usage with DMA overrun event always considered as an */
+ /* error. */
+ if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
+ {
+ overrun_error = 1U;
+ }
+ else
+ {
+ /* Pointer to the common control register to which is belonging hadc */
+ /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
+ /* control registers) */
+ tmpADC_Common = ADC_COMMON_REGISTER(hadc);
+
+ /* Check DMA configuration, depending on MultiMode set or not */
+ if (READ_BIT(tmpADC_Common->CCR, ADC_CCR_MULTI) == ADC_MODE_INDEPENDENT)
+ {
+ if (HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_DMAEN))
+ {
+ overrun_error = 1U;
+ }
+ }
+ else
+ {
+ /* MultiMode is enabled, Common Control Register MDMA bits must be checked */
+ if (READ_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA) != RESET)
+ {
+ overrun_error = 1U;
+ }
+ }
+ }
+
+ if (overrun_error == 1U)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
+
+ /* Set ADC error code to ADC IP internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
+
+ /* Error callback */
+ HAL_ADC_ErrorCallback(hadc);
+ }
+
+ /* Clear the Overrun flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+
+ }
+
+
+ /* ========== Check Injected context queue overflow flag ========== */
+ if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JQOVF) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JQOVF))
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
+
+ /* Set ADC error code to ADC IP internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
+
+ /* Clear the Injected context queue overflow flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
+
+ /* Error callback */
+ HAL_ADCEx_InjectedQueueOverflowCallback(hadc);
+ }
+
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Handles ADC interrupt request
+ * @param hadc ADC handle
+ * @retval None
+ */
+void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+ assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
+
+
+ /* ========== Check End of Conversion flag for regular group ========== */
+ if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC))
+ {
+ if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) )
+ {
+ /* Update state machine on conversion status if not in error state */
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+ }
+
+ /* Determine whether any further conversion upcoming on group regular */
+ /* by external trigger, continuous mode or scan sequence on going. */
+ /* Note: On STM32F37x devices, in case of sequencer enabled */
+ /* (several ranks selected), end of conversion flag is raised */
+ /* at the end of the sequence. */
+ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+ (hadc->Init.ContinuousConvMode == DISABLE) )
+ {
+ /* Disable ADC end of single conversion interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
+
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+
+ /* Conversion complete callback */
+ HAL_ADC_ConvCpltCallback(hadc);
+
+ /* Clear regular group conversion flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
+ }
+ }
+
+ /* ========== Check End of Conversion flag for injected group ========== */
+ if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC))
+ {
+ if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC))
+ {
+ /* Update state machine on conversion status if not in error state */
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
+ }
+
+ /* Determine whether any further conversion upcoming on group injected */
+ /* by external trigger, scan sequence on going or by automatic injected */
+ /* conversion from group regular (same conditions as group regular */
+ /* interruption disabling above). */
+ /* Note: On STM32F37x devices, in case of sequencer enabled */
+ /* (several ranks selected), end of conversion flag is raised */
+ /* at the end of the sequence. */
+ if(ADC_IS_SOFTWARE_START_INJECTED(hadc) ||
+ (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
+ (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+ (hadc->Init.ContinuousConvMode == DISABLE) ) ) )
+ {
+ /* Disable ADC end of single conversion interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+
+ /* Conversion complete callback */
+ HAL_ADCEx_InjectedConvCpltCallback(hadc);
+
+ /* Clear injected group conversion flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC));
+ }
+ }
+
+ /* ========== Check Analog watchdog flags ========== */
+ if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD))
+ {
+ if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD))
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+
+ /* Level out of window callback */
+ HAL_ADC_LevelOutOfWindowCallback(hadc);
+
+ /* Clear the ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
+ }
+ }
+
+}
+#endif /* STM32F373xC || STM32F378xx */
+
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Perform an ADC automatic self-calibration
+ * Calibration prerequisite: ADC must be disabled (execute this
+ * function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
+ * @param hadc ADC handle
+ * @param SingleDiff Selection of single-ended or differential input
+ * This parameter can be one of the following values:
+ * @arg ADC_SINGLE_ENDED: Channel in mode input single ended
+ * @arg ADC_DIFFERENTIAL_ENDED: Channel in mode input differential ended
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ uint32_t tickstart;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Calibration prerequisite: ADC must be disabled. */
+
+ /* Disable the ADC (if not already disabled) */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_READY;
+
+ /* Select calibration mode single ended or differential ended */
+ hadc->Instance->CR &= (~ADC_CR_ADCALDIF);
+ if (SingleDiff == ADC_DIFFERENTIAL_ENDED)
+ {
+ hadc->Instance->CR |= ADC_CR_ADCALDIF;
+ }
+
+ /* Start ADC calibration */
+ hadc->Instance->CR |= ADC_CR_ADCAL;
+
+ tickstart = HAL_GetTick();
+
+ /* Wait for calibration completion */
+ while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADCAL))
+ {
+ if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
+ {
+ /* Update ADC state machine to error */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_BUSY_INTERNAL,
+ HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_BUSY_INTERNAL,
+ HAL_ADC_STATE_READY);
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Perform an ADC automatic self-calibration
+ * Calibration prerequisite: ADC must be disabled (execute this
+ * function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
+ * During calibration process, ADC is enabled. ADC is let enabled at
+ * the completion of this function.
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ uint32_t tickstart;
+ __IO uint32_t wait_loop_index = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* 1. Calibration prerequisite: */
+ /* - ADC must be disabled for at least two ADC clock cycles in disable */
+ /* mode before ADC enable */
+ /* Stop potential conversion on going, on regular and injected groups */
+ /* Disable ADC peripheral */
+ tmp_hal_status = ADC_ConversionStop_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_BUSY_INTERNAL);
+
+ /* Wait two ADC clock cycles */
+ while(wait_loop_index < ADC_CYCLE_WORST_CASE_CPU_CYCLES *2U)
+ {
+ wait_loop_index++;
+ }
+
+ /* 2. Enable the ADC peripheral */
+ ADC_Enable(hadc);
+
+
+ /* 3. Resets ADC calibration registers */
+ SET_BIT(hadc->Instance->CR2, ADC_CR2_RSTCAL);
+
+ tickstart = HAL_GetTick();
+
+ /* Wait for calibration reset completion */
+ while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL))
+ {
+ if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
+ {
+ /* Update ADC state machine to error */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_BUSY_INTERNAL,
+ HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+ }
+
+
+ /* 4. Start ADC calibration */
+ SET_BIT(hadc->Instance->CR2, ADC_CR2_CAL);
+
+ tickstart = HAL_GetTick();
+
+ /* Wait for calibration completion */
+ while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL))
+ {
+ if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
+ {
+ /* Update ADC state machine to error */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_BUSY_INTERNAL,
+ HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_BUSY_INTERNAL,
+ HAL_ADC_STATE_READY);
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Get the calibration factor from automatic conversion result
+ * @param hadc ADC handle
+ * @param SingleDiff Selection of single-ended or differential input
+ * This parameter can be one of the following values:
+ * @arg ADC_SINGLE_ENDED: Channel in mode input single ended
+ * @arg ADC_DIFFERENTIAL_ENDED: Channel in mode input differential ended
+ * @retval Converted value
+ */
+uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
+
+ /* Return the selected ADC calibration value */
+ if (SingleDiff == ADC_DIFFERENTIAL_ENDED)
+ {
+ return ADC_CALFACT_DIFF_GET(hadc->Instance->CALFACT);
+ }
+ else
+ {
+ return ((hadc->Instance->CALFACT) & ADC_CALFACT_CALFACT_S);
+ }
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Set the calibration factor to overwrite automatic conversion result. ADC must be enabled and no conversion on going.
+ * @param hadc ADC handle
+ * @param SingleDiff Selection of single-ended or differential input
+ * This parameter can be one of the following values:
+ * @arg ADC_SINGLE_ENDED: Channel in mode input single ended
+ * @arg ADC_DIFFERENTIAL_ENDED: Channel in mode input differential ended
+ * @param CalibrationFactor Calibration factor (coded on 7 bits maximum)
+ * @retval HAL state
+ */
+HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
+ assert_param(IS_ADC_CALFACT(CalibrationFactor));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Verification of hardware constraints before modifying the calibration */
+ /* factors register: ADC must be enabled, no conversion on going. */
+ if ( (ADC_IS_ENABLE(hadc) != RESET) &&
+ (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) )
+ {
+ /* Set the selected ADC calibration value */
+ if (SingleDiff == ADC_DIFFERENTIAL_ENDED)
+ {
+ MODIFY_REG(hadc->Instance->CALFACT ,
+ ADC_CALFACT_CALFACT_D ,
+ ADC_CALFACT_DIFF_SET(CalibrationFactor) );
+ }
+ else
+ {
+ MODIFY_REG(hadc->Instance->CALFACT,
+ ADC_CALFACT_CALFACT_S ,
+ CalibrationFactor );
+ }
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ /* Set ADC error code to ADC IP internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Enables ADC, starts conversion of injected group.
+ * Interruptions enabled in this function: None.
+ * @note Case of multimode enabled (for devices with several ADCs): This
+ * function must be called for ADC slave first, then ADC master.
+ * For ADC slave, ADC is enabled only (conversion is not started).
+ * For ADC master, ADC is enabled and multimode conversion is started.
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Perform ADC enable and conversion start if no conversion is on going */
+ if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
+ {
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Enable the ADC peripheral */
+ tmp_hal_status = ADC_Enable(hadc);
+
+ /* Start conversion if ADC is effectively enabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ /* - Clear state bitfield related to injected group conversion results */
+ /* - Set state bitfield related to injected operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
+ HAL_ADC_STATE_INJ_BUSY);
+
+ /* Case of independent mode or multimode(for devices with several ADCs):*/
+ /* Set multimode state. */
+ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
+ {
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+ }
+ else
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+ }
+
+ /* Check if a regular conversion is ongoing */
+ /* Note: On this device, there is no ADC error code fields related to */
+ /* conversions on group injected only. In case of conversion on */
+ /* going on group regular, no error code is reset. */
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
+ {
+ /* Reset ADC all error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Clear injected group conversion flag */
+ /* (To ensure of no unknown state from potential previous ADC */
+ /* operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
+
+ /* Enable conversion of injected group, if automatic injected */
+ /* conversion is disabled. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ /* Case of multimode enabled (for devices with several ADCs): */
+ /* - if ADC is slave, ADC is enabled only (conversion is not started). */
+ /* - if ADC is master, ADC is enabled and conversion is started. */
+ if (HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO) &&
+ ADC_NONMULTIMODE_INJ_OR_MULTIMODEMASTER(hadc) )
+ {
+ SET_BIT(hadc->Instance->CR, ADC_CR_JADSTART);
+ }
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+ }
+ }
+ else
+ {
+ tmp_hal_status = HAL_BUSY;
+ }
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Enables ADC, starts conversion of injected group.
+ * Interruptions enabled in this function: None.
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Enable the ADC peripheral */
+ tmp_hal_status = ADC_Enable(hadc);
+
+ /* Start conversion if ADC is effectively enabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ /* - Clear state bitfield related to injected group conversion results */
+ /* - Set state bitfield related to injected operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
+ HAL_ADC_STATE_INJ_BUSY);
+
+ /* Check if a regular conversion is ongoing */
+ /* Note: On this device, there is no ADC error code fields related to */
+ /* conversions on group injected only. In case of conversion on */
+ /* going on group regular, no error code is reset. */
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
+ {
+ /* Reset ADC all error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Clear injected group conversion flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
+
+ /* Enable conversion of injected group. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ /* If automatic injected conversion is enabled, conversion will start */
+ /* after next regular group conversion. */
+ if (ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
+ HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
+ {
+ /* Start ADC conversion on injected group with SW start */
+ SET_BIT(hadc->Instance->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG));
+ }
+ else
+ {
+ /* Start ADC conversion on injected group with external trigger */
+ SET_BIT(hadc->Instance->CR2, ADC_CR2_JEXTTRIG);
+ }
+ }
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Stop ADC group injected conversion (potential conversion on going
+ * on ADC group regular is not impacted), disable ADC peripheral
+ * if no conversion is on going on group regular.
+ * @note To stop ADC conversion of both groups regular and injected and to
+ * to disable ADC peripheral, instead of using 2 functions
+ * @ref HAL_ADCEx_RegularStop() and @ref HAL_ADCEx_InjectedStop(),
+ * use function @ref HAL_ADC_Stop().
+ * @note If injected group mode auto-injection is enabled,
+ * function HAL_ADC_Stop must be used.
+ * @note Case of multimode enabled (for devices with several ADCs): This
+ * function must be called for ADC master first, then ADC slave.
+ * For ADC master, conversion is stopped and ADC is disabled.
+ * For ADC slave, ADC is disabled only (conversion stop of ADC master
+ * has already stopped conversion of ADC slave).
+ * @note In case of auto-injection mode, HAL_ADC_Stop must be used.
+ * @param hadc ADC handle
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Stop potential ADC conversion on going and disable ADC peripheral */
+ /* conditioned to: */
+ /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
+ /* - For ADC injected group conversion stop: */
+ /* On this STM32 family, conversion on the other group */
+ /* (group regular) can continue (groups regular and injected */
+ /* conversion stop commands are independent) */
+ /* - For ADC disable: */
+ /* No conversion on the other group (group regular) must be intended to */
+ /* continue (groups regular and injected are both impacted by */
+ /* ADC disable) */
+ if(HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO))
+ {
+ /* 1. Stop potential conversion on going on injected group only. */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
+
+ /* Disable ADC peripheral if conversion on ADC group injected is */
+ /* effectively stopped and if no conversion on the other group */
+ /* (ADC group regular) is intended to continue. */
+ if (tmp_hal_status == HAL_OK)
+ {
+ if((ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) &&
+ ((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) )
+ {
+ /* 2. Disable the ADC peripheral */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+ /* Conversion on ADC group injected group is stopped, but ADC is not */
+ /* disabled since conversion on ADC group regular is still on going. */
+ else
+ {
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+ }
+ }
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Stop conversion of injected channels. Disable ADC peripheral if
+ * no regular conversion is on going.
+ * @note If ADC must be disabled and if conversion is on going on
+ * regular group, function HAL_ADC_Stop must be used to stop both
+ * injected and regular groups, and disable the ADC.
+ * @note In case of auto-injection mode, HAL_ADC_Stop must be used.
+ * @param hadc ADC handle
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Stop potential conversion and disable ADC peripheral */
+ /* Conditioned to: */
+ /* - No conversion on the other group (regular group) is intended to */
+ /* continue (injected and regular groups stop conversion and ADC disable */
+ /* are common) */
+ /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
+ if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) &&
+ HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
+ {
+ /* Stop potential conversion on going, on regular and injected groups */
+ /* Disable ADC peripheral */
+ tmp_hal_status = ADC_ConversionStop_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Wait for injected group conversion to be completed.
+ * @param hadc ADC handle
+ * @param Timeout Timeout value in millisecond.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
+{
+ uint32_t tickstart;
+ uint32_t tmp_Flag_EOC;
+ uint32_t tmp_cfgr = 0x00000000U;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* If end of conversion selected to end of sequence */
+ if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
+ {
+ tmp_Flag_EOC = ADC_FLAG_JEOS;
+ }
+ /* If end of conversion selected to end of each conversion */
+ else /* ADC_EOC_SINGLE_CONV */
+ {
+ tmp_Flag_EOC = (ADC_FLAG_JEOC | ADC_FLAG_JEOS);
+ }
+
+ /* Get relevant register CFGR in ADC instance of ADC master or slave */
+ /* in function of multimode state (for devices with multimode */
+ /* available). */
+ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
+ {
+ tmp_cfgr = READ_REG(hadc->Instance->CFGR);
+ }
+ else
+ {
+ tmp_cfgr = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR);
+ }
+
+ /* Get tick count */
+ tickstart = HAL_GetTick();
+
+ /* Wait until End of Conversion flag is raised */
+ while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC))
+ {
+ /* Check if timeout is disabled (set to infinite wait) */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ /* Update ADC state machine to timeout */
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Update ADC state machine */
+ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
+
+ /* Determine whether any further conversion upcoming on group injected */
+ /* by external trigger or by automatic injected conversion */
+ /* from group regular. */
+ if(ADC_IS_SOFTWARE_START_INJECTED(hadc) ||
+ ((READ_BIT (tmp_cfgr, ADC_CFGR_JAUTO) == RESET) &&
+ (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+ (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == RESET) ) ) )
+ {
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+
+ /* Clear end of conversion flag of injected group if low power feature */
+ /* "Auto Wait" is disabled, to not interfere with this feature until data */
+ /* register is read using function HAL_ADC_GetValue(). */
+ if (READ_BIT (tmp_cfgr, ADC_CFGR_AUTDLY) == RESET)
+ {
+ /* Clear injected group conversion flag */
+ /* (JEOC or JEOS depending on HAL ADC initialization parameter) */
+ __HAL_ADC_CLEAR_FLAG(hadc, tmp_Flag_EOC);
+ }
+
+ /* Return ADC state */
+ return HAL_OK;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Wait for injected group conversion to be completed.
+ * @param hadc ADC handle
+ * @param Timeout Timeout value in millisecond.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ /* Variables for polling in case of scan mode enabled */
+ uint32_t Conversion_Timeout_CPU_cycles_max =0U;
+ uint32_t Conversion_Timeout_CPU_cycles =0U;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Get tick count */
+ tickstart = HAL_GetTick();
+
+ /* Polling for end of conversion: differentiation if single/sequence */
+ /* conversion. */
+ /* For injected group, flag JEOC is set only at the end of the sequence, */
+ /* not for each conversion within the sequence. */
+ /* - If single conversion for injected group (scan mode disabled or */
+ /* InjectedNbrOfConversion ==1U), flag JEOC is used to determine the */
+ /* conversion completion. */
+ /* - If sequence conversion for injected group (scan mode enabled and */
+ /* InjectedNbrOfConversion >=2U), flag JEOC is set only at the end of the */
+ /* sequence. */
+ /* To poll for each conversion, the maximum conversion time is computed */
+ /* from ADC conversion time (selected sampling time + conversion time of */
+ /* 12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on */
+ /* settings, conversion time range can be from 28 to 32256 CPU cycles). */
+ /* As flag JEOC is not set after each conversion, no timeout status can */
+ /* be set. */
+ if ((hadc->Instance->JSQR & ADC_JSQR_JL) == RESET)
+ {
+ /* Wait until End of Conversion flag is raised */
+ while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_JEOC))
+ {
+ /* Check if timeout is disabled (set to infinite wait) */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ /* Update ADC state machine to timeout */
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else
+ {
+ /* Replace polling by wait for maximum conversion time */
+ /* Calculation of CPU cycles corresponding to ADC conversion cycles. */
+ /* Retrieve ADC clock prescaler and ADC maximum conversion cycles on all */
+ /* channels. */
+ Conversion_Timeout_CPU_cycles_max = ADC_CLOCK_PRESCALER_RANGE();
+ Conversion_Timeout_CPU_cycles_max *= ADC_CONVCYCLES_MAX_RANGE(hadc);
+
+ /* Poll with maximum conversion time */
+ while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max)
+ {
+ /* Check if timeout is disabled (set to infinite wait) */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ /* Update ADC state machine to timeout */
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ Conversion_Timeout_CPU_cycles ++;
+ }
+ }
+
+
+ /* Clear injected group conversion flag (and regular conversion flag raised simultaneously) */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC | ADC_FLAG_EOC);
+
+ /* Update ADC state machine */
+ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
+
+ /* Determine whether any further conversion upcoming on group injected */
+ /* by external trigger or by automatic injected conversion */
+ /* from group regular. */
+ if(ADC_IS_SOFTWARE_START_INJECTED(hadc) ||
+ (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
+ (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+ (hadc->Init.ContinuousConvMode == DISABLE) ) ) )
+ {
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+
+ /* Return ADC state */
+ return HAL_OK;
+}
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Enables ADC, starts conversion of injected group with interruption.
+ * Interruptions enabled in this function:
+ * - JEOC (end of conversion of injected group) or JEOS (end of
+ * sequence of injected group) depending on ADC initialization
+ * parameter "EOCSelection"
+ * Each of these interruptions has its dedicated callback function.
+ * @note Case of multimode enabled (for devices with several ADCs): This
+ * function must be called for ADC slave first, then ADC master.
+ * For ADC slave, ADC is enabled only (conversion is not started).
+ * For ADC master, ADC is enabled and multimode conversion is started.
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Perform ADC enable and conversion start if no conversion is on going */
+ if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
+ {
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Enable the ADC peripheral */
+ tmp_hal_status = ADC_Enable(hadc);
+
+ /* Start conversion if ADC is effectively enabled */
+ /* Start conversion if ADC is effectively enabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ /* - Clear state bitfield related to injected group conversion results */
+ /* - Set state bitfield related to injected operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
+ HAL_ADC_STATE_INJ_BUSY);
+
+ /* Case of independent mode or multimode(for devices with several ADCs):*/
+ /* Set multimode state. */
+ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
+ {
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+ }
+ else
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+ }
+
+ /* Check if a regular conversion is ongoing */
+ /* Note: On this device, there is no ADC error code fields related to */
+ /* conversions on group injected only. In case of conversion on */
+ /* going on group regular, no error code is reset. */
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
+ {
+ /* Reset ADC all error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Clear injected group conversion flag */
+ /* (To ensure of no unknown state from potential previous ADC */
+ /* operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
+
+ /* Enable ADC Injected context queue overflow interrupt if this feature */
+ /* is enabled. */
+ if ((hadc->Instance->CFGR & ADC_CFGR_JQM) != RESET)
+ {
+ __HAL_ADC_ENABLE_IT(hadc, ADC_FLAG_JQOVF);
+ }
+
+ /* Enable ADC end of conversion interrupt */
+ switch(hadc->Init.EOCSelection)
+ {
+ case ADC_EOC_SEQ_CONV:
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
+ break;
+ /* case ADC_EOC_SINGLE_CONV */
+ default:
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
+ break;
+ }
+
+ /* Enable conversion of injected group, if automatic injected */
+ /* conversion is disabled. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ /* Case of multimode enabled (for devices with several ADCs): */
+ /* - if ADC is slave, ADC is enabled only (conversion is not started). */
+ /* - if ADC is master, ADC is enabled and conversion is started. */
+ if (HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO) &&
+ ADC_NONMULTIMODE_INJ_OR_MULTIMODEMASTER(hadc) )
+ {
+ SET_BIT(hadc->Instance->CR, ADC_CR_JADSTART);
+ }
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+ }
+ }
+ else
+ {
+ tmp_hal_status = HAL_BUSY;
+ }
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Enables ADC, starts conversion of injected group with interruption.
+ * Interruptions enabled in this function:
+ * - JEOC (end of conversion of injected group)
+ * Each of these interruptions has its dedicated callback function.
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Enable the ADC peripheral */
+ tmp_hal_status = ADC_Enable(hadc);
+
+ /* Start conversion if ADC is effectively enabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ /* - Clear state bitfield related to injected group conversion results */
+ /* - Set state bitfield related to injected operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
+ HAL_ADC_STATE_INJ_BUSY);
+
+ /* Check if a regular conversion is ongoing */
+ /* Note: On this device, there is no ADC error code fields related to */
+ /* conversions on group injected only. In case of conversion on */
+ /* going on group regular, no error code is reset. */
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
+ {
+ /* Reset ADC all error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Set ADC error code to none */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Clear injected group conversion flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
+
+ /* Enable end of conversion interrupt for injected channels */
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
+
+ /* Enable conversion of injected group. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ /* If automatic injected conversion is enabled, conversion will start */
+ /* after next regular group conversion. */
+ if (ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
+ HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
+ {
+ /* Start ADC conversion on injected group with SW start */
+ SET_BIT(hadc->Instance->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG));
+ }
+ else
+ {
+ /* Start ADC conversion on injected group with external trigger */
+ SET_BIT(hadc->Instance->CR2, ADC_CR2_JEXTTRIG);
+ }
+ }
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Stop ADC group injected conversion (potential conversion on going
+ * on ADC group regular is not impacted), disable ADC peripheral
+ * if no conversion is on going on group regular.
+ * Interruptions disabled in this function:
+ * - JEOC (end of conversion of injected group) and JEOS (end of
+ * sequence of injected group)
+ * @note To stop ADC conversion of both groups regular and injected and to
+ * to disable ADC peripheral, instead of using 2 functions
+ * @ref HAL_ADCEx_RegularStop() and @ref HAL_ADCEx_InjectedStop(),
+ * use function @ref HAL_ADC_Stop().
+ * @note If injected group mode auto-injection is enabled,
+ * function HAL_ADC_Stop must be used.
+ * @note Case of multimode enabled (for devices with several ADCs): This
+ * function must be called for ADC master first, then ADC slave.
+ * For ADC master, conversion is stopped and ADC is disabled.
+ * For ADC slave, ADC is disabled only (conversion stop of ADC master
+ * has already stopped conversion of ADC slave).
+ * @note In case of auto-injection mode, HAL_ADC_Stop must be used.
+ * @param hadc ADC handle
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Stop potential ADC conversion on going and disable ADC peripheral */
+ /* conditioned to: */
+ /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
+ /* - For ADC injected group conversion stop: */
+ /* On this STM32 family, conversion on the other group */
+ /* (group regular) can continue (groups regular and injected */
+ /* conversion stop commands are independent) */
+ /* - For ADC disable: */
+ /* No conversion on the other group (group regular) must be intended to */
+ /* continue (groups regular and injected are both impacted by */
+ /* ADC disable) */
+ if(HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO))
+ {
+ /* 1. Stop potential conversion on going on injected group only. */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
+
+ /* Disable ADC peripheral if conversion on ADC group injected is */
+ /* effectively stopped and if no conversion on the other group */
+ /* (ADC group regular) is intended to continue. */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Disable ADC end of conversion interrupt for injected channels */
+ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS | ADC_IT_JQOVF));
+
+ if((ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) &&
+ ((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) )
+ {
+ /* 2. Disable the ADC peripheral */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+ /* Conversion on ADC group injected group is stopped, but ADC is not */
+ /* disabled since conversion on ADC group regular is still on going. */
+ else
+ {
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+ }
+ }
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Stop conversion of injected channels, disable interruption of
+ * end-of-conversion. Disable ADC peripheral if no regular conversion
+ * is on going.
+ * @note If ADC must be disabled and if conversion is on going on
+ * regular group, function HAL_ADC_Stop must be used to stop both
+ * injected and regular groups, and disable the ADC.
+ * @param hadc ADC handle
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Stop potential conversion and disable ADC peripheral */
+ /* Conditioned to: */
+ /* - No conversion on the other group (regular group) is intended to */
+ /* continue (injected and regular groups stop conversion and ADC disable */
+ /* are common) */
+ /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
+ if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) &&
+ HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
+ {
+ /* Stop potential conversion on going, on regular and injected groups */
+ /* Disable ADC peripheral */
+ tmp_hal_status = ADC_ConversionStop_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Disable ADC end of conversion interrupt for injected channels */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+/**
+ * @brief With ADC configured in multimode, for ADC master:
+ * Enables ADC, starts conversion of regular group and transfers result
+ * through DMA.
+ * Multimode must have been previously configured using
+ * HAL_ADCEx_MultiModeConfigChannel() function.
+ * Interruptions enabled in this function:
+ * - DMA transfer complete
+ * - DMA half transfer
+ * - overrun
+ * Each of these interruptions has its dedicated callback function.
+ * @note ADC slave must be preliminarily enabled using single-mode
+ * HAL_ADC_Start() function.
+ * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
+ * @param pData The destination Buffer address.
+ * @param Length The length of data to be transferred from ADC peripheral to memory.
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ ADC_HandleTypeDef tmphadcSlave;
+ ADC_Common_TypeDef *tmpADC_Common;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+ assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Perform ADC enable and conversion start if no conversion is on going */
+ /* (check on ADC master only) */
+ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+ {
+ /* Set a temporary handle of the ADC slave associated to the ADC master */
+ /* (Depending on STM32F3 product, there may be up to 2 ADC slaves) */
+ ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
+
+ if (tmphadcSlave.Instance == NULL)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+
+
+ /* Enable the ADC peripherals: master and slave (in case if not already */
+ /* enabled previously) */
+ tmp_hal_status = ADC_Enable(hadc);
+ if (tmp_hal_status == HAL_OK)
+ {
+ tmp_hal_status = ADC_Enable(&tmphadcSlave);
+ }
+
+ /* Start conversion all ADCs of multimode are effectively enabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state (ADC master) */
+ /* - Clear state bitfield related to regular group conversion results */
+ /* - Set state bitfield related to regular operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP | HAL_ADC_STATE_MULTIMODE_SLAVE,
+ HAL_ADC_STATE_REG_BUSY);
+
+ /* If conversions on group regular are also triggering group injected, */
+ /* update ADC state. */
+ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET)
+ {
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+ }
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Set ADC error code to none */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+
+ /* Set the DMA transfer complete callback */
+ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
+
+ /* Set the DMA half transfer complete callback */
+ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
+
+ /* Set the DMA error callback */
+ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ;
+
+ /* Pointer to the common control register to which is belonging hadc */
+ /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
+ /* control registers) */
+ tmpADC_Common = ADC_COMMON_REGISTER(hadc);
+
+
+ /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
+ /* start (in case of SW start): */
+
+ /* Clear regular group conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+
+ /* Enable ADC overrun interrupt */
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+
+ /* Start the DMA channel */
+ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length);
+
+ /* Enable conversion of regular group. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
+
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+ }
+ }
+ else
+ {
+ tmp_hal_status = HAL_BUSY;
+ }
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief With ADC configured in multimode, for ADC master:
+ * Stop ADC group regular conversion (potential conversion on going
+ * on ADC group injected is not impacted),
+ * disable ADC DMA transfer, disable ADC peripheral
+ * if no conversion is on going on group injected.
+ * Interruptions disabled in this function:
+ * - DMA transfer complete
+ * - DMA half transfer
+ * - overrun
+ * @note In case of auto-injection mode, this function also stop conversion
+ * on ADC group injected.
+ * @note Multimode is kept enabled after this function. To disable multimode
+ * (set with HAL_ADCEx_MultiModeConfigChannel() ), ADC must be
+ * reinitialized using HAL_ADC_Init() or HAL_ADC_ReInit().
+ * @note In case of DMA configured in circular mode, function
+ * HAL_ADC_Stop_DMA must be called after this function with handle of
+ * ADC slave, to properly disable the DMA channel of ADC slave.
+ * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ uint32_t tickstart;
+ ADC_HandleTypeDef tmphadcSlave;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* 1. Stop potential multimode conversion on going, on regular and */
+ /* injected groups. */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+
+ /* Disable ADC peripheral if conversions are effectively stopped */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set a temporary handle of the ADC slave associated to the ADC master */
+ /* (Depending on STM32F3 product, there may be up to 2 ADC slaves) */
+ ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
+
+ if (tmphadcSlave.Instance == NULL)
+ {
+ /* Update ADC state machine (ADC master) to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+
+ /* Procedure to disable the ADC peripheral: wait for conversions */
+ /* effectively stopped (ADC master and ADC slave), then disable ADC */
+
+ /* 1. Wait until ADSTP=0 for ADC master and ADC slave */
+ tickstart = HAL_GetTick();
+
+ while(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) ||
+ ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave) )
+ {
+ if((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
+ {
+ /* Update ADC state machine (ADC master) to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Disable the DMA channel (in case of DMA in circular mode or stop while */
+ /* while DMA transfer is on going) */
+ /* Note: In case of ADC slave using its own DMA channel (multimode */
+ /* parameter "DMAAccessMode" set to disabled): */
+ /* DMA channel of ADC slave should stopped after this function with */
+ /* function HAL_ADC_Stop_DMA. */
+ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+
+ /* Check if DMA channel effectively disabled */
+ if (tmp_hal_status != HAL_OK)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+ }
+
+ /* Disable ADC overrun interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+
+
+
+ /* 2. Disable the ADC peripherals: master and slave */
+ /* Update "tmp_hal_status" only if DMA channel disabling passed, */
+ /* to retain a potential failing status. */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Check if ADC are effectively disabled */
+ if ((ADC_Disable(hadc) != HAL_ERROR) &&
+ (ADC_Disable(&tmphadcSlave) != HAL_ERROR) )
+ {
+ tmp_hal_status = HAL_OK;
+
+ /* Change ADC state (ADC master) */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+ else
+ {
+ /* In case of error, attempt to disable ADC instances anyway */
+ ADC_Disable(hadc);
+ ADC_Disable(&tmphadcSlave);
+
+ /* Update ADC state machine (ADC master) to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+ }
+
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Returns the last ADC Master&Slave regular conversions results data
+ * in the selected multi mode.
+ * @note Reading register CDR does not clear flag ADC flag EOC
+ * (ADC group regular end of unitary conversion),
+ * as it is the case for independent mode data register.
+ * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
+ * @retval The converted data value.
+ */
+uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
+{
+ ADC_Common_TypeDef *tmpADC_Common;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+
+ /* Pointer to the common control register to which is belonging hadc */
+ /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
+ /* control registers) */
+ tmpADC_Common = ADC_COMMON_REGISTER(hadc);
+
+ /* Return the multi mode conversion value */
+ return tmpADC_Common->CDR;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Get ADC injected group conversion result.
+ * @note Reading register JDRx automatically clears ADC flag JEOC
+ * (ADC group injected end of unitary conversion).
+ * @note This function does not clear ADC flag JEOS
+ * (ADC group injected end of sequence conversion)
+ * Occurrence of flag JEOS rising:
+ * - If sequencer is composed of 1 rank, flag JEOS is equivalent
+ * to flag JEOC.
+ * - If sequencer is composed of several ranks, during the scan
+ * sequence flag JEOC only is raised, at the end of the scan sequence
+ * both flags JEOC and EOS are raised.
+ * Flag JEOS must not be cleared by this function because
+ * it would not be compliant with low power features
+ * (feature low power auto-wait, not available on all STM32 families).
+ * To clear this flag, either use function:
+ * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
+ * model polling: @ref HAL_ADCEx_InjectedPollForConversion()
+ * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
+ * @param hadc ADC handle
+ * @param InjectedRank the converted ADC injected rank.
+ * This parameter can be one of the following values:
+ * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected
+ * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected
+ * @arg ADC_INJECTED_RANK_3: Injected Channel3 selected
+ * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected
+ * @retval ADC group injected conversion data
+ */
+uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
+{
+ uint32_t tmp_jdr = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
+
+ /* Note: ADC flag JEOC is not cleared here by software because */
+ /* automatically cleared by hardware when reading register JDRx. */
+
+ /* Get ADC converted value */
+ switch(InjectedRank)
+ {
+ case ADC_INJECTED_RANK_4:
+ tmp_jdr = hadc->Instance->JDR4;
+ break;
+ case ADC_INJECTED_RANK_3:
+ tmp_jdr = hadc->Instance->JDR3;
+ break;
+ case ADC_INJECTED_RANK_2:
+ tmp_jdr = hadc->Instance->JDR2;
+ break;
+ case ADC_INJECTED_RANK_1:
+ default:
+ tmp_jdr = hadc->Instance->JDR1;
+ break;
+ }
+
+ /* Return ADC converted value */
+ return tmp_jdr;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Get ADC injected group conversion result.
+ * @note Reading register JDRx automatically clears ADC flag JEOC
+ * (ADC group injected end of unitary conversion).
+ * @note This function does not clear ADC flag JEOS
+ * (ADC group injected end of sequence conversion)
+ * Occurrence of flag JEOS rising:
+ * - If sequencer is composed of 1 rank, flag JEOS is equivalent
+ * to flag JEOC.
+ * - If sequencer is composed of several ranks, during the scan
+ * sequence flag JEOC only is raised, at the end of the scan sequence
+ * both flags JEOC and EOS are raised.
+ * Flag JEOS must not be cleared by this function because
+ * it would not be compliant with low power features
+ * (feature low power auto-wait, not available on all STM32 families).
+ * To clear this flag, either use function:
+ * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
+ * model polling: @ref HAL_ADCEx_InjectedPollForConversion()
+ * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
+ * @param hadc ADC handle
+ * @param InjectedRank the converted ADC injected rank.
+ * This parameter can be one of the following values:
+ * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected
+ * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected
+ * @arg ADC_INJECTED_RANK_3: Injected Channel3 selected
+ * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected
+ * @retval ADC group injected conversion data
+ */
+uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
+{
+ uint32_t tmp_jdr = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
+
+ /* Get ADC converted value */
+ switch(InjectedRank)
+ {
+ case ADC_INJECTED_RANK_4:
+ tmp_jdr = hadc->Instance->JDR4;
+ break;
+ case ADC_INJECTED_RANK_3:
+ tmp_jdr = hadc->Instance->JDR3;
+ break;
+ case ADC_INJECTED_RANK_2:
+ tmp_jdr = hadc->Instance->JDR2;
+ break;
+ case ADC_INJECTED_RANK_1:
+ default:
+ tmp_jdr = hadc->Instance->JDR1;
+ break;
+ }
+
+ /* Return ADC converted value */
+ return tmp_jdr;
+}
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Stop ADC group regular conversion (potential conversion on going
+ * on ADC group injected is not impacted), disable ADC peripheral
+ * if no conversion is on going on group injected.
+ * @note To stop ADC conversion of both groups regular and injected and to
+ * to disable ADC peripheral, instead of using 2 functions
+ * @ref HAL_ADCEx_RegularStop() and @ref HAL_ADCEx_InjectedStop(),
+ * use function @ref HAL_ADC_Stop().
+ * @note In case of auto-injection mode, this function also stop conversion
+ * on ADC group injected.
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Stop potential ADC conversion on going and disable ADC peripheral */
+ /* conditioned to: */
+ /* - For ADC regular group conversion stop: */
+ /* On this STM32 family, conversion on the other group */
+ /* (group injected) can continue (groups regular and injected */
+ /* conversion stop commands are independent) */
+ /* - For ADC disable: */
+ /* No conversion on the other group (group injected) must be intended to */
+ /* continue (groups regular and injected are both impacted by */
+ /* ADC disable) */
+
+ /* 1. Stop potential conversion on going, on regular group only */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+
+ /* Disable ADC peripheral if conversion on ADC group regular is */
+ /* effectively stopped and if no conversion on the other group */
+ /* (ADC group injected) is intended to continue. */
+ if((ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) &&
+ ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == RESET) )
+ {
+ /* 2. Disable the ADC peripheral */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+ /* Conversion on ADC group regular group is stopped, but ADC is not */
+ /* disabled since conversion on ADC group injected is still on going. */
+ else
+ {
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Stop ADC group regular conversion (potential conversion on going
+ * on ADC group injected is not impacted), disable ADC peripheral
+ * if no conversion is on going on group injected.
+ * Interruptions disabled in this function:
+ * - EOC (end of conversion of regular group) and EOS (end of
+ * sequence of regular group)
+ * - overrun
+ * @note To stop ADC conversion of both groups regular and injected and to
+ * to disable ADC peripheral, instead of using 2 functions
+ * @ref HAL_ADCEx_RegularStop() and @ref HAL_ADCEx_InjectedStop(),
+ * use function @ref HAL_ADC_Stop().
+ * @note In case of auto-injection mode, this function also stop conversion
+ * on ADC group injected.
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Stop potential ADC conversion on going and disable ADC peripheral */
+ /* conditioned to: */
+ /* - For ADC regular group conversion stop: */
+ /* On this STM32 family, conversion on the other group */
+ /* (group injected) can continue (groups regular and injected */
+ /* conversion stop commands are independent) */
+ /* - For ADC disable: */
+ /* No conversion on the other group (group injected) must be intended to */
+ /* continue (groups regular and injected are both impacted by */
+ /* ADC disable) */
+
+ /* 1. Stop potential conversion on going, on regular group only */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+
+ /* Disable ADC peripheral if conversion on ADC group regular is */
+ /* effectively stopped and if no conversion on the other group */
+ /* (ADC group injected) is intended to continue. */
+ if((ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) &&
+ ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == RESET) )
+ {
+ /* Disable ADC end of conversion interrupt for regular group */
+ /* Disable ADC overrun interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
+
+ /* 2. Disable the ADC peripheral */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+ /* Conversion on ADC group regular group is stopped, but ADC is not */
+ /* disabled since conversion on ADC group injected is still on going. */
+ else
+ {
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Stop ADC group regular conversion (potential conversion on going
+ * on ADC group injected is not impacted),
+ * disable ADC DMA transfer, disable ADC peripheral
+ * if no conversion is on going on group injected.
+ * Interruptions disabled in this function:
+ * - DMA transfer complete
+ * - DMA half transfer
+ * - overrun
+ * @note To stop ADC conversion of both groups regular and injected and to
+ * to disable ADC peripheral, instead of using 2 functions
+ * @ref HAL_ADCEx_RegularStop() and @ref HAL_ADCEx_InjectedStop(),
+ * use function @ref HAL_ADC_Stop().
+ * @note Case of multimode enabled (for devices with several ADCs): This
+ * function is for single-ADC mode only. For multimode, use the
+ * dedicated MultimodeStop function.
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Stop potential ADC conversion on going and disable ADC peripheral */
+ /* conditioned to: */
+ /* - For ADC regular group conversion stop: */
+ /* On this STM32 family, conversion on the other group */
+ /* (group injected) can continue (groups regular and injected */
+ /* conversion stop commands are independent) */
+ /* - For ADC disable: */
+ /* No conversion on the other group (group injected) must be intended to */
+ /* continue (groups regular and injected are both impacted by */
+ /* ADC disable) */
+
+ /* 1. Stop potential conversion on going, on regular group only */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+
+ /* Disable ADC peripheral if conversion on ADC group regular is */
+ /* effectively stopped and if no conversion on the other group */
+ /* (ADC group injected) is intended to continue. */
+ if((ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) &&
+ ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == RESET) )
+ {
+ /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
+ CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
+
+ /* Disable the DMA channel (in case of DMA in circular mode or stop while */
+ /* while DMA transfer is on going) */
+ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+
+ /* Check if DMA channel effectively disabled */
+ if (tmp_hal_status != HAL_OK)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+ }
+
+ /* Disable ADC overrun interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+
+ /* 2. Disable the ADC peripheral */
+ /* Update "tmp_hal_status" only if DMA channel disabling passed, */
+ /* to retain a potential failing status. */
+ if (tmp_hal_status == HAL_OK)
+ {
+ tmp_hal_status = ADC_Disable(hadc);
+ }
+ else
+ {
+ ADC_Disable(hadc);
+ }
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+ /* Conversion on ADC group regular group is stopped, but ADC is not */
+ /* disabled since conversion on ADC group injected is still on going. */
+ else
+ {
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+/**
+ * @brief With ADC configured in multimode, for ADC master:
+ * Stop ADC group regular conversion (potential conversion on going
+ * on ADC group injected is not impacted),
+ * disable ADC DMA transfer, disable ADC peripheral
+ * if no conversion is on going on group injected.
+ * Interruptions disabled in this function:
+ * - DMA transfer complete
+ * - DMA half transfer
+ * - overrun
+ * @note To stop ADC conversion of both groups regular and injected and to
+ * to disable ADC peripheral, instead of using 2 functions
+ * @ref HAL_ADCEx_RegularMultiModeStop_DMA() and
+ * @ref HAL_ADCEx_InjectedStop(), use function
+ * @ref HAL_ADCEx_MultiModeStop_DMA.
+ * @note In case of auto-injection mode, this function also stop conversion
+ * on ADC group injected.
+ * @note Multimode is kept enabled after this function. To disable multimode
+ * (set with HAL_ADCEx_MultiModeConfigChannel() ), ADC must be
+ * reinitialized using HAL_ADC_Init() or HAL_ADC_ReInit().
+ * @note In case of DMA configured in circular mode, function
+ * HAL_ADC_Stop_DMA must be called after this function with handle of
+ * ADC slave, to properly disable the DMA channel of ADC slave.
+ * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ uint32_t tickstart;
+ ADC_HandleTypeDef tmphadcSlave;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Stop potential ADC conversion on going and disable ADC peripheral */
+ /* conditioned to: */
+ /* - For ADC regular group conversion stop: */
+ /* On this STM32 family, conversion on the other group */
+ /* (group injected) can continue (groups regular and injected */
+ /* conversion stop commands are independent) */
+ /* - For ADC disable: */
+ /* No conversion on the other group (group injected) must be intended to */
+ /* continue (groups regular and injected are both impacted by */
+ /* ADC disable) */
+
+ /* 1. Stop potential conversion on going, on regular group only */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+
+ /* Disable ADC peripheral if conversion on ADC group regular is */
+ /* effectively stopped and if no conversion on the other group */
+ /* (ADC group injected) is intended to continue. */
+ if((ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) &&
+ ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == RESET) )
+ {
+ /* Set a temporary handle of the ADC slave associated to the ADC master */
+ /* (Depending on STM32F3 product, there may be up to 2 ADC slaves) */
+ ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
+
+ if (tmphadcSlave.Instance == NULL)
+ {
+ /* Update ADC state machine (ADC master) to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+
+ /* Procedure to disable the ADC peripheral: wait for conversions */
+ /* effectively stopped (ADC master and ADC slave), then disable ADC */
+
+ /* 1. Wait until ADSTP=0 for ADC master and ADC slave*/
+ tickstart = HAL_GetTick();
+
+ while(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) ||
+ ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave) )
+ {
+ if((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
+ {
+ /* Update ADC state machine (ADC master) to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Disable the DMA channel (in case of DMA in circular mode or stop while */
+ /* while DMA transfer is on going) */
+ /* Note: In case of ADC slave using its own DMA channel (multimode */
+ /* parameter "DMAAccessMode" set to disabled): */
+ /* DMA channel of ADC slave should stopped after this function with */
+ /* function HAL_ADC_Stop_DMA. */
+ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+
+ /* Check if DMA channel effectively disabled */
+ if (tmp_hal_status != HAL_OK)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+ }
+
+ /* Disable ADC overrun interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+
+
+
+ /* 2. Disable the ADC peripherals: master and slave */
+ /* Update "tmp_hal_status" only if DMA channel disabling passed, */
+ /* to retain a potential failing status. */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Check if ADC are effectively disabled */
+ if ((ADC_Disable(hadc) != HAL_ERROR) &&
+ (ADC_Disable(&tmphadcSlave) != HAL_ERROR) )
+ {
+ tmp_hal_status = HAL_OK;
+
+ /* Change ADC state (ADC master) */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+ else
+ {
+ /* In case of error, attempt to disable ADC instances anyway */
+ ADC_Disable(hadc);
+ ADC_Disable(&tmphadcSlave);
+
+ /* Update ADC state machine (ADC master) to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+ }
+
+ }
+ /* Conversion on ADC group regular group is stopped, but ADC is not */
+ /* disabled since conversion on ADC group injected is still on going. */
+ else
+ {
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+/**
+ * @brief Injected conversion complete callback in non blocking mode
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_ADCEx_InjectedConvCpltCallback could be implemented in the user file
+ */
+}
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Injected context queue overflow flag callback.
+ * @note This callback is called if injected context queue is enabled
+ (parameter "QueueInjectedContext" in injected channel configuration)
+ and if a new injected context is set when queue is full (maximum 2
+ contexts).
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented
+ in the user file.
+ */
+}
+
+/**
+ * @brief Analog watchdog 2 callback in non blocking mode.
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_LevelOoutOfWindow2Callback must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Analog watchdog 3 callback in non blocking mode.
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_LevelOoutOfWindow3Callback must be implemented in the user file.
+ */
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_Exported_Functions_Group3 ADCEx Peripheral Control functions
+ * @brief ADC Extended Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure channels on regular group
+ (+) Configure channels on injected group
+ (+) Configure multimode
+ (+) Configure the analog watchdog
+
+@endverbatim
+ * @{
+ */
+
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Configures the the selected channel to be linked to the regular
+ * group.
+ * @note In case of usage of internal measurement channels:
+ * Vbat/VrefInt/TempSensor.
+ * The recommended sampling time is at least:
+ * - For devices STM32F37x: 17.1us for temperature sensor
+ * - For the other STM32F3 devices: 2.2us for each of channels
+ * Vbat/VrefInt/TempSensor.
+ * These internal paths can be be disabled using function
+ * HAL_ADC_DeInit().
+ * @note Possibility to update parameters on the fly:
+ * This function initializes channel into regular group, following
+ * calls to this function can be used to reconfigure some parameters
+ * of structure "ADC_ChannelConfTypeDef" on the fly, without reseting
+ * the ADC.
+ * The setting of these parameters is conditioned to ADC state.
+ * For parameters constraints, see comments of structure
+ * "ADC_ChannelConfTypeDef".
+ * @param hadc ADC handle
+ * @param sConfig Structure ADC channel for regular group.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ ADC_Common_TypeDef *tmpADC_Common;
+ ADC_HandleTypeDef tmphadcSharingSameCommonRegister;
+ uint32_t tmpOffsetShifted;
+ __IO uint32_t wait_loop_index = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
+ assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
+ assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfig->SingleDiff));
+ assert_param(IS_ADC_OFFSET_NUMBER(sConfig->OffsetNumber));
+ assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset));
+
+
+ /* Verification of channel number: Channels 1 to 14 are available in */
+ /* differential mode. Channels 15U, 16U, 17U, 18 can be used only in */
+ /* single-ended mode. */
+ if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
+ {
+ assert_param(IS_ADC_CHANNEL(sConfig->Channel));
+ }
+ else
+ {
+ assert_param(IS_ADC_DIFF_CHANNEL(sConfig->Channel));
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated when ADC is disabled or enabled without */
+ /* conversion on going on regular group: */
+ /* - Channel number */
+ /* - Channel rank */
+ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+ {
+ /* Regular sequence configuration */
+ /* For Rank 1 to 4U */
+ if (sConfig->Rank < 5U)
+ {
+ MODIFY_REG(hadc->Instance->SQR1,
+ ADC_SQR1_RK(ADC_SQR2_SQ5, sConfig->Rank) ,
+ ADC_SQR1_RK(sConfig->Channel, sConfig->Rank) );
+ }
+ /* For Rank 5 to 9U */
+ else if (sConfig->Rank < 10U)
+ {
+ MODIFY_REG(hadc->Instance->SQR2,
+ ADC_SQR2_RK(ADC_SQR2_SQ5, sConfig->Rank) ,
+ ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) );
+ }
+ /* For Rank 10 to 14U */
+ else if (sConfig->Rank < 15U)
+ {
+ MODIFY_REG(hadc->Instance->SQR3 ,
+ ADC_SQR3_RK(ADC_SQR3_SQ10, sConfig->Rank) ,
+ ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) );
+ }
+ /* For Rank 15 to 16U */
+ else
+ {
+ MODIFY_REG(hadc->Instance->SQR4 ,
+ ADC_SQR4_RK(ADC_SQR4_SQ15, sConfig->Rank) ,
+ ADC_SQR4_RK(sConfig->Channel, sConfig->Rank) );
+ }
+
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated when ADC is disabled or enabled without */
+ /* conversion on going on regular group: */
+ /* - Channel sampling time */
+ /* - Channel offset */
+ if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
+ {
+ /* Channel sampling time configuration */
+ /* For channels 10 to 18U */
+ if (sConfig->Channel >= ADC_CHANNEL_10)
+ {
+ MODIFY_REG(hadc->Instance->SMPR2 ,
+ ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel) ,
+ ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) );
+ }
+ else /* For channels 1 to 9U */
+ {
+ MODIFY_REG(hadc->Instance->SMPR1 ,
+ ADC_SMPR1(ADC_SMPR1_SMP0, sConfig->Channel) ,
+ ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) );
+ }
+
+
+ /* Configure the offset: offset enable/disable, channel, offset value */
+
+ /* Shift the offset in function of the selected ADC resolution. */
+ /* Offset has to be left-aligned on bit 11U, the LSB (right bits) are set */
+ /* to 0. */
+ tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfig->Offset);
+
+ /* Configure the selected offset register: */
+ /* - Enable offset */
+ /* - Set channel number */
+ /* - Set offset value */
+ switch (sConfig->OffsetNumber)
+ {
+ case ADC_OFFSET_1:
+ /* Configure offset register 1U */
+ MODIFY_REG(hadc->Instance->OFR1 ,
+ ADC_OFR1_OFFSET1_CH |
+ ADC_OFR1_OFFSET1 ,
+ ADC_OFR1_OFFSET1_EN |
+ ADC_OFR_CHANNEL(sConfig->Channel) |
+ tmpOffsetShifted );
+ break;
+
+ case ADC_OFFSET_2:
+ /* Configure offset register 2U */
+ MODIFY_REG(hadc->Instance->OFR2 ,
+ ADC_OFR2_OFFSET2_CH |
+ ADC_OFR2_OFFSET2 ,
+ ADC_OFR2_OFFSET2_EN |
+ ADC_OFR_CHANNEL(sConfig->Channel) |
+ tmpOffsetShifted );
+ break;
+
+ case ADC_OFFSET_3:
+ /* Configure offset register 3U */
+ MODIFY_REG(hadc->Instance->OFR3 ,
+ ADC_OFR3_OFFSET3_CH |
+ ADC_OFR3_OFFSET3 ,
+ ADC_OFR3_OFFSET3_EN |
+ ADC_OFR_CHANNEL(sConfig->Channel) |
+ tmpOffsetShifted );
+ break;
+
+ case ADC_OFFSET_4:
+ /* Configure offset register 4U */
+ MODIFY_REG(hadc->Instance->OFR4 ,
+ ADC_OFR4_OFFSET4_CH |
+ ADC_OFR4_OFFSET4 ,
+ ADC_OFR4_OFFSET4_EN |
+ ADC_OFR_CHANNEL(sConfig->Channel) |
+ tmpOffsetShifted );
+ break;
+
+ /* Case ADC_OFFSET_NONE */
+ default :
+ /* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is */
+ /* enabled. If this is the case, offset OFRx is disabled. */
+ if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
+ {
+ /* Disable offset OFR1*/
+ CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN);
+ }
+ if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
+ {
+ /* Disable offset OFR2*/
+ CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN);
+ }
+ if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
+ {
+ /* Disable offset OFR3*/
+ CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN);
+ }
+ if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
+ {
+ /* Disable offset OFR4*/
+ CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN);
+ }
+ break;
+ }
+
+ }
+
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated only when ADC is disabled: */
+ /* - Single or differential mode */
+ /* - Internal measurement channels: Vbat/VrefInt/TempSensor */
+ if (ADC_IS_ENABLE(hadc) == RESET)
+ {
+ /* Configuration of differential mode */
+ if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
+ {
+ /* Disable differential mode (default mode: single-ended) */
+ CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel));
+ }
+ else
+ {
+ /* Enable differential mode */
+ SET_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel));
+
+ /* Channel sampling time configuration (channel ADC_INx +1 */
+ /* corresponding to differential negative input). */
+ /* For channels 10 to 18U */
+ if (sConfig->Channel >= ADC_CHANNEL_10)
+ {
+ MODIFY_REG(hadc->Instance->SMPR2,
+ ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel +1U) ,
+ ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel +1U) );
+ }
+ else /* For channels 1 to 9U */
+ {
+ MODIFY_REG(hadc->Instance->SMPR1,
+ ADC_SMPR1(ADC_SMPR1_SMP0, sConfig->Channel +1U) ,
+ ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel +1U) );
+ }
+ }
+
+
+ /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */
+ /* internal measurement paths enable: If internal channel selected, */
+ /* enable dedicated internal buffers and path. */
+ /* Note: these internal measurement paths can be disabled using */
+ /* HAL_ADC_DeInit(). */
+
+ /* Configuration of common ADC parameters */
+ /* Pointer to the common control register to which is belonging hadc */
+ /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
+ /* control registers) */
+ tmpADC_Common = ADC_COMMON_REGISTER(hadc);
+
+ /* If the requested internal measurement path has already been enabled, */
+ /* bypass the configuration processing. */
+ if (( (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) &&
+ (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN)) ) ||
+ ( (sConfig->Channel == ADC_CHANNEL_VBAT) &&
+ (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN)) ) ||
+ ( (sConfig->Channel == ADC_CHANNEL_VREFINT) &&
+ (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VREFEN)))
+ )
+ {
+ /* Configuration of common ADC parameters (continuation) */
+ /* Set handle of the other ADC sharing the same common register */
+ ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister);
+
+ /* Software is allowed to change common parameters only when all ADCs */
+ /* of the common group are disabled. */
+ if ((ADC_IS_ENABLE(hadc) == RESET) &&
+ ( (tmphadcSharingSameCommonRegister.Instance == NULL) ||
+ (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) )
+ {
+ /* If Channel_16 is selected, enable Temp. sensor measurement path */
+ /* Note: Temp. sensor internal channels available on ADC1 only */
+ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && (hadc->Instance == ADC1))
+ {
+ SET_BIT(tmpADC_Common->CCR, ADC_CCR_TSEN);
+
+ /* Delay for temperature sensor stabilization time */
+ /* Compute number of CPU cycles to wait for */
+ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
+ while(wait_loop_index != 0U)
+ {
+ wait_loop_index--;
+ }
+ }
+ /* If Channel_17 is selected, enable VBAT measurement path */
+ /* Note: VBAT internal channels available on ADC1 only */
+ else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && (hadc->Instance == ADC1))
+ {
+ SET_BIT(tmpADC_Common->CCR, ADC_CCR_VBATEN);
+ }
+ /* If Channel_18 is selected, enable VREFINT measurement path */
+ /* Note: VrefInt internal channels available on all ADCs, but only */
+ /* one ADC is allowed to be connected to VrefInt at the same */
+ /* time. */
+ else if (sConfig->Channel == ADC_CHANNEL_VREFINT)
+ {
+ SET_BIT(tmpADC_Common->CCR, ADC_CCR_VREFEN);
+ }
+ }
+ /* If the requested internal measurement path has already been */
+ /* enabled and other ADC of the common group are enabled, internal */
+ /* measurement paths cannot be enabled. */
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+ }
+
+ }
+
+ }
+ /* If a conversion is on going on regular group, no update on regular */
+ /* channel could be done on neither of the channel configuration structure */
+ /* parameters. */
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Configures the the selected channel to be linked to the regular
+ * group.
+ * @note In case of usage of internal measurement channels:
+ * Vbat/VrefInt/TempSensor.
+ * The recommended sampling time is at least:
+ * - For devices STM32F37x: 17.1us for temperature sensor
+ * - For the other STM32F3 devices: 2.2us for each of channels
+ * Vbat/VrefInt/TempSensor.
+ * These internal paths can be be disabled using function
+ * HAL_ADC_DeInit().
+ * @note Possibility to update parameters on the fly:
+ * This function initializes channel into regular group, following
+ * calls to this function can be used to reconfigure some parameters
+ * of structure "ADC_ChannelConfTypeDef" on the fly, without reseting
+ * the ADC.
+ * The setting of these parameters is conditioned to ADC state.
+ * For parameters constraints, see comments of structure
+ * "ADC_ChannelConfTypeDef".
+ * @param hadc ADC handle
+ * @param sConfig Structure of ADC channel for regular group.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ __IO uint32_t wait_loop_index = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_CHANNEL(sConfig->Channel));
+ assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
+ assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+
+ /* Regular sequence configuration */
+ /* For Rank 1 to 6U */
+ if (sConfig->Rank < 7U)
+ {
+ MODIFY_REG(hadc->Instance->SQR3 ,
+ ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) ,
+ ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) );
+ }
+ /* For Rank 7 to 12U */
+ else if (sConfig->Rank < 13U)
+ {
+ MODIFY_REG(hadc->Instance->SQR2 ,
+ ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank) ,
+ ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) );
+ }
+ /* For Rank 13 to 16U */
+ else
+ {
+ MODIFY_REG(hadc->Instance->SQR1 ,
+ ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank) ,
+ ADC_SQR1_RK(sConfig->Channel, sConfig->Rank) );
+ }
+
+
+ /* Channel sampling time configuration */
+ /* For channels 10 to 18U */
+ if (sConfig->Channel > ADC_CHANNEL_10)
+ {
+ MODIFY_REG(hadc->Instance->SMPR1 ,
+ ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) ,
+ ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) );
+ }
+ else /* For channels 0 to 9U */
+ {
+ MODIFY_REG(hadc->Instance->SMPR2 ,
+ ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel) ,
+ ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) );
+ }
+
+ /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */
+ /* and VREFINT measurement path. */
+ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
+ (sConfig->Channel == ADC_CHANNEL_VREFINT) )
+ {
+ SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
+
+ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))
+ {
+ /* Delay for temperature sensor stabilization time */
+ /* Compute number of CPU cycles to wait for */
+ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
+ while(wait_loop_index != 0U)
+ {
+ wait_loop_index--;
+ }
+ }
+ }
+ /* if ADC1 Channel_18 is selected, enable VBAT measurement path */
+ else if (sConfig->Channel == ADC_CHANNEL_VBAT)
+ {
+ SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_VBAT);
+ }
+
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Configures the ADC injected group and the selected channel to be
+ * linked to the injected group.
+ * @note Possibility to update parameters on the fly:
+ * This function initializes injected group, following calls to this
+ * function can be used to reconfigure some parameters of structure
+ * "ADC_InjectionConfTypeDef" on the fly, without reseting the ADC.
+ * The setting of these parameters is conditioned to ADC state.
+ * For parameters constraints, see comments of structure
+ * "ADC_InjectionConfTypeDef".
+ * @note In case of usage of internal measurement channels:
+ * Vbat/VrefInt/TempSensor.
+ * The recommended sampling time is at least:
+ * - For devices STM32F37x: 17.1us for temperature sensor
+ * - For the other STM32F3 devices: 2.2us for each of channels
+ * Vbat/VrefInt/TempSensor.
+ * These internal paths can be be disabled using function
+ * HAL_ADC_DeInit().
+ * @note To reset injected sequencer, function HAL_ADCEx_InjectedStop() can
+ * be used.
+ * @note Caution: For Injected Context Queue use: a context must be fully
+ * defined before start of injected conversion: all channels configured
+ * consecutively for the same ADC instance. Therefore, Number of calls of
+ * HAL_ADCEx_InjectedConfigChannel() must correspond to value of parameter
+ * InjectedNbrOfConversion for each context.
+ * - Example 1: If 1 context intended to be used (or not use of this feature:
+ * QueueInjectedContext=DISABLE) and usage of the 3 first injected ranks
+ * (InjectedNbrOfConversion=3), HAL_ADCEx_InjectedConfigChannel() must be
+ * called once for each channel (3 times) before launching a conversion.
+ * This function must not be called to configure the 4th injected channel:
+ * it would start a new context into context queue.
+ * - Example 2: If 2 contexts intended to be used and usage of the 3 first
+ * injected ranks (InjectedNbrOfConversion=3),
+ * HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and
+ * for each context (3 channels x 2 contexts = 6 calls). Conversion can
+ * start once the 1st context is set. The 2nd context can be set on the fly.
+ * @param hadc ADC handle
+ * @param sConfigInjected Structure of ADC injected group and ADC channel for
+ * injected group.
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ ADC_Common_TypeDef *tmpADC_Common;
+ ADC_HandleTypeDef tmphadcSharingSameCommonRegister;
+ uint32_t tmpOffsetShifted;
+ __IO uint32_t wait_loop_index = 0U;
+
+ /* Injected context queue feature: temporary JSQR variables defined in */
+ /* static to be passed over calls of this function */
+ uint32_t tmp_JSQR_ContextQueueBeingBuilt = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
+ assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfigInjected->InjectedSingleDiff));
+ assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
+ assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->QueueInjectedContext));
+ assert_param(IS_ADC_EXTTRIGINJEC_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
+ assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv));
+ assert_param(IS_ADC_OFFSET_NUMBER(sConfigInjected->InjectedOffsetNumber));
+ assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset));
+
+ if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
+ {
+ assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
+ assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
+ assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
+ }
+
+ /* Verification of channel number: Channels 1 to 14 are available in */
+ /* differential mode. Channels 15U, 16U, 17U, 18 can be used only in */
+ /* single-ended mode. */
+ if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
+ {
+ assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));
+ }
+ else
+ {
+ assert_param(IS_ADC_DIFF_CHANNEL(sConfigInjected->InjectedChannel));
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Configuration of Injected group sequencer. */
+ /* Hardware constraint: Must fully define injected context register JSQR */
+ /* before make it entering into injected sequencer queue. */
+ /* */
+ /* - if scan mode is disabled: */
+ /* * Injected channels sequence length is set to 0x00: 1 channel */
+ /* converted (channel on injected rank 1U) */
+ /* Parameter "InjectedNbrOfConversion" is discarded. */
+ /* * Injected context register JSQR setting is simple: register is fully */
+ /* defined on one call of this function (for injected rank 1U) and can */
+ /* be entered into queue directly. */
+ /* - if scan mode is enabled: */
+ /* * Injected channels sequence length is set to parameter */
+ /* "InjectedNbrOfConversion". */
+ /* * Injected context register JSQR setting more complex: register is */
+ /* fully defined over successive calls of this function, for each */
+ /* injected channel rank. It is entered into queue only when all */
+ /* injected ranks have been set. */
+ /* Note: Scan mode is not present by hardware on this device, but used */
+ /* by software for alignment over all STM32 devices. */
+
+ if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) ||
+ (sConfigInjected->InjectedNbrOfConversion == 1U) )
+ {
+ /* Configuration of context register JSQR: */
+ /* - number of ranks in injected group sequencer: fixed to 1st rank */
+ /* (scan mode disabled, only rank 1 used) */
+ /* - external trigger to start conversion */
+ /* - external trigger polarity */
+ /* - channel set to rank 1 (scan mode disabled, only rank 1 used) */
+
+ if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
+ {
+ /* Enable external trigger if trigger selection is different of */
+ /* software start. */
+ /* Note: This configuration keeps the hardware feature of parameter */
+ /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
+ /* software start. */
+ if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
+ {
+ SET_BIT(tmp_JSQR_ContextQueueBeingBuilt, ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) |
+ ADC_JSQR_JEXTSEL_SET(hadc, sConfigInjected->ExternalTrigInjecConv) |
+ sConfigInjected->ExternalTrigInjecConvEdge );
+ }
+ else
+ {
+ SET_BIT(tmp_JSQR_ContextQueueBeingBuilt, ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) );
+ }
+
+ /* Update ADC register JSQR */
+ MODIFY_REG(hadc->Instance->JSQR ,
+ ADC_JSQR_JSQ4 |
+ ADC_JSQR_JSQ3 |
+ ADC_JSQR_JSQ2 |
+ ADC_JSQR_JSQ1 |
+ ADC_JSQR_JEXTEN |
+ ADC_JSQR_JEXTSEL |
+ ADC_JSQR_JL ,
+ tmp_JSQR_ContextQueueBeingBuilt );
+
+ /* For debug and informative reasons, hadc handle saves JSQR setting */
+ hadc->InjectionConfig.ContextQueue = tmp_JSQR_ContextQueueBeingBuilt;
+ }
+ /* If another injected rank than rank1 was intended to be set, and could */
+ /* not due to ScanConvMode disabled, error is reported. */
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ }
+ else
+ {
+ /* Case of scan mode enabled, several channels to set into injected group */
+ /* sequencer. */
+ /* Procedure to define injected context register JSQR over successive */
+ /* calls of this function, for each injected channel rank: */
+
+ /* 1. Start new context and set parameters related to all injected */
+ /* channels: injected sequence length and trigger */
+ if (hadc->InjectionConfig.ChannelCount == 0U)
+ {
+ /* Initialize number of channels that will be configured on the context */
+ /* being built */
+ hadc->InjectionConfig.ChannelCount = sConfigInjected->InjectedNbrOfConversion;
+ /* Initialize value that will be set into register JSQR */
+ hadc->InjectionConfig.ContextQueue = 0x00000000U;
+
+ /* Configuration of context register JSQR: */
+ /* - number of ranks in injected group sequencer */
+ /* - external trigger to start conversion */
+ /* - external trigger polarity */
+
+ /* Enable external trigger if trigger selection is different of */
+ /* software start. */
+ /* Note: This configuration keeps the hardware feature of parameter */
+ /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
+ /* software start. */
+ if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
+ {
+ SET_BIT(hadc->InjectionConfig.ContextQueue, (sConfigInjected->InjectedNbrOfConversion - 1U) |
+ ADC_JSQR_JEXTSEL_SET(hadc, sConfigInjected->ExternalTrigInjecConv) |
+ sConfigInjected->ExternalTrigInjecConvEdge );
+ }
+ else
+ {
+ SET_BIT(hadc->InjectionConfig.ContextQueue, (sConfigInjected->InjectedNbrOfConversion - 1U) );
+ }
+
+ }
+
+ /* 2. Continue setting of context under definition with parameter */
+ /* related to each channel: channel rank sequence */
+
+ /* Set the JSQx bits for the selected rank */
+ MODIFY_REG(hadc->InjectionConfig.ContextQueue ,
+ ADC_JSQR_RK(ADC_SQR3_SQ10, sConfigInjected->InjectedRank) ,
+ ADC_JSQR_RK(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank) );
+
+ /* Decrease channel count after setting into temporary JSQR variable */
+ hadc->InjectionConfig.ChannelCount --;
+
+ /* 3. End of context setting: If last channel set, then write context */
+ /* into register JSQR and make it enter into queue */
+ if (hadc->InjectionConfig.ChannelCount == 0U)
+ {
+ /* Update ADC register JSQR */
+ MODIFY_REG(hadc->Instance->JSQR ,
+ ADC_JSQR_JSQ4 |
+ ADC_JSQR_JSQ3 |
+ ADC_JSQR_JSQ2 |
+ ADC_JSQR_JSQ1 |
+ ADC_JSQR_JEXTEN |
+ ADC_JSQR_JEXTSEL |
+ ADC_JSQR_JL ,
+ hadc->InjectionConfig.ContextQueue );
+ }
+
+ }
+
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated when ADC is disabled or enabled without */
+ /* conversion on going on injected group: */
+ /* - Injected context queue: Queue disable (active context is kept) or */
+ /* enable (context decremented, up to 2 contexts queued) */
+ /* - Injected discontinuous mode: can be enabled only if auto-injected */
+ /* mode is disabled. */
+ if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
+ {
+ /* If auto-injected mode is disabled: no constraint */
+ if (sConfigInjected->AutoInjectedConv == DISABLE)
+ {
+ MODIFY_REG(hadc->Instance->CFGR ,
+ ADC_CFGR_JQM |
+ ADC_CFGR_JDISCEN ,
+ ADC_CFGR_INJECT_CONTEXT_QUEUE(sConfigInjected->QueueInjectedContext) |
+ ADC_CFGR_INJECT_DISCCONTINUOUS(sConfigInjected->InjectedDiscontinuousConvMode) );
+ }
+ /* If auto-injected mode is enabled: Injected discontinuous setting is */
+ /* discarded. */
+ else
+ {
+ MODIFY_REG(hadc->Instance->CFGR ,
+ ADC_CFGR_JQM |
+ ADC_CFGR_JDISCEN ,
+ ADC_CFGR_INJECT_CONTEXT_QUEUE(sConfigInjected->QueueInjectedContext) );
+
+ /* If injected discontinuous mode was intended to be set and could not */
+ /* due to auto-injected enabled, error is reported. */
+ if (sConfigInjected->InjectedDiscontinuousConvMode == ENABLE)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+ }
+
+ }
+
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated when ADC is disabled or enabled without */
+ /* conversion on going on regular and injected groups: */
+ /* - Automatic injected conversion: can be enabled if injected group */
+ /* external triggers are disabled. */
+ /* - Channel sampling time */
+ /* - Channel offset */
+ if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
+ {
+ /* If injected group external triggers are disabled (set to injected */
+ /* software start): no constraint */
+ if (sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
+ {
+ MODIFY_REG(hadc->Instance->CFGR ,
+ ADC_CFGR_JAUTO ,
+ ADC_CFGR_INJECT_AUTO_CONVERSION(sConfigInjected->AutoInjectedConv) );
+ }
+ /* If Automatic injected conversion was intended to be set and could not */
+ /* due to injected group external triggers enabled, error is reported. */
+ else
+ {
+ /* Disable Automatic injected conversion */
+ CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
+
+ if (sConfigInjected->AutoInjectedConv == ENABLE)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+ }
+
+
+ /* Channel sampling time configuration */
+ /* For channels 10 to 18U */
+ if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_10)
+ {
+ MODIFY_REG(hadc->Instance->SMPR2 ,
+ ADC_SMPR2(ADC_SMPR2_SMP10, sConfigInjected->InjectedChannel) ,
+ ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
+ }
+ else /* For channels 1 to 9U */
+ {
+ MODIFY_REG(hadc->Instance->SMPR1 ,
+ ADC_SMPR1(ADC_SMPR1_SMP0, sConfigInjected->InjectedChannel) ,
+ ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
+ }
+
+ /* Configure the offset: offset enable/disable, channel, offset value */
+
+ /* Shift the offset in function of the selected ADC resolution. */
+ /* Offset has to be left-aligned on bit 11U, the LSB (right bits) are set */
+ /* to 0. */
+ tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset);
+
+ /* Configure the selected offset register: */
+ /* - Enable offset */
+ /* - Set channel number */
+ /* - Set offset value */
+ switch (sConfigInjected->InjectedOffsetNumber)
+ {
+ case ADC_OFFSET_1:
+ /* Configure offset register 1U */
+ MODIFY_REG(hadc->Instance->OFR1 ,
+ ADC_OFR1_OFFSET1_CH |
+ ADC_OFR1_OFFSET1 ,
+ ADC_OFR1_OFFSET1_EN |
+ ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) |
+ tmpOffsetShifted );
+ break;
+
+ case ADC_OFFSET_2:
+ /* Configure offset register 2U */
+ MODIFY_REG(hadc->Instance->OFR2 ,
+ ADC_OFR2_OFFSET2_CH |
+ ADC_OFR2_OFFSET2 ,
+ ADC_OFR2_OFFSET2_EN |
+ ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) |
+ tmpOffsetShifted );
+ break;
+
+ case ADC_OFFSET_3:
+ /* Configure offset register 3U */
+ MODIFY_REG(hadc->Instance->OFR3 ,
+ ADC_OFR3_OFFSET3_CH |
+ ADC_OFR3_OFFSET3 ,
+ ADC_OFR3_OFFSET3_EN |
+ ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) |
+ tmpOffsetShifted );
+ break;
+
+ case ADC_OFFSET_4:
+ /* Configure offset register 4U */
+ MODIFY_REG(hadc->Instance->OFR4 ,
+ ADC_OFR4_OFFSET4_CH |
+ ADC_OFR4_OFFSET4 ,
+ ADC_OFR4_OFFSET4_EN |
+ ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) |
+ tmpOffsetShifted );
+ break;
+
+ /* Case ADC_OFFSET_NONE */
+ default :
+ /* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is */
+ /* enabled. If this is the case, offset OFRx is disabled. */
+ if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
+ {
+ /* Disable offset OFR1*/
+ CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN);
+ }
+ if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
+ {
+ /* Disable offset OFR2*/
+ CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN);
+ }
+ if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
+ {
+ /* Disable offset OFR3*/
+ CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN);
+ }
+ if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
+ {
+ /* Disable offset OFR4*/
+ CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN);
+ }
+ break;
+ }
+
+ }
+
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated only when ADC is disabled: */
+ /* - Single or differential mode */
+ /* - Internal measurement channels: Vbat/VrefInt/TempSensor */
+ if (ADC_IS_ENABLE(hadc) == RESET)
+ {
+ /* Configuration of differential mode */
+ if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
+ {
+ /* Disable differential mode (default mode: single-ended) */
+ CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfigInjected->InjectedChannel));
+ }
+ else
+ {
+ /* Enable differential mode */
+ SET_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfigInjected->InjectedChannel));
+
+ /* Channel sampling time configuration (channel ADC_INx +1 */
+ /* corresponding to differential negative input). */
+ /* For channels 10 to 18U */
+ if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_10)
+ {
+ MODIFY_REG(hadc->Instance->SMPR2,
+ ADC_SMPR2(ADC_SMPR2_SMP10, sConfigInjected->InjectedChannel +1U),
+ ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel +1U) );
+ }
+ else /* For channels 1 to 9U */
+ {
+ MODIFY_REG(hadc->Instance->SMPR1,
+ ADC_SMPR1(ADC_SMPR1_SMP0, sConfigInjected->InjectedChannel +1U),
+ ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel +1U) );
+ }
+ }
+
+
+ /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */
+ /* internal measurement paths enable: If internal channel selected, */
+ /* enable dedicated internal buffers and path. */
+ /* Note: these internal measurement paths can be disabled using */
+ /* HAL_ADC_deInit(). */
+
+ /* Configuration of common ADC parameters */
+ /* Pointer to the common control register to which is belonging hadc */
+ /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
+ /* control registers) */
+ tmpADC_Common = ADC_COMMON_REGISTER(hadc);
+
+ /* If the requested internal measurement path has already been enabled, */
+ /* bypass the configuration processing. */
+ if (( (sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) &&
+ (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN)) ) ||
+ ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) &&
+ (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN)) ) ||
+ ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) &&
+ (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VREFEN)))
+ )
+ {
+ /* Configuration of common ADC parameters (continuation) */
+ /* Set handle of the other ADC sharing the same common register */
+ ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister);
+
+ /* Software is allowed to change common parameters only when all ADCs */
+ /* of the common group are disabled. */
+ if ((ADC_IS_ENABLE(hadc) == RESET) &&
+ ( (tmphadcSharingSameCommonRegister.Instance == NULL) ||
+ (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) )
+ {
+ /* If Channel_16 is selected, enable Temp. sensor measurement path */
+ /* Note: Temp. sensor internal channels available on ADC1 only */
+ if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) && (hadc->Instance == ADC1))
+ {
+ SET_BIT(tmpADC_Common->CCR, ADC_CCR_TSEN);
+
+ /* Delay for temperature sensor stabilization time */
+ /* Compute number of CPU cycles to wait for */
+ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
+ while(wait_loop_index != 0U)
+ {
+ wait_loop_index--;
+ }
+ }
+ /* If Channel_17 is selected, enable VBAT measurement path */
+ /* Note: VBAT internal channels available on ADC1 only */
+ else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) && (hadc->Instance == ADC1))
+ {
+ SET_BIT(tmpADC_Common->CCR, ADC_CCR_VBATEN);
+ }
+ /* If Channel_18 is selected, enable VREFINT measurement path */
+ /* Note: VrefInt internal channels available on all ADCs, but only */
+ /* one ADC is allowed to be connected to VrefInt at the same */
+ /* time. */
+ else if (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)
+ {
+ SET_BIT(tmpADC_Common->CCR, ADC_CCR_VREFEN);
+ }
+ }
+ /* If the requested internal measurement path has already been enabled */
+ /* and other ADC of the common group are enabled, internal */
+ /* measurement paths cannot be enabled. */
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+ }
+
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Configures the ADC injected group and the selected channel to be
+ * linked to the injected group.
+ * @note Possibility to update parameters on the fly:
+ * This function initializes injected group, following calls to this
+ * function can be used to reconfigure some parameters of structure
+ * "ADC_InjectionConfTypeDef" on the fly, without reseting the ADC.
+ * The setting of these parameters is conditioned to ADC state:
+ * this function must be called when ADC is not under conversion.
+ * @note In case of usage of internal measurement channels:
+ * Vbat/VrefInt/TempSensor.
+ * The recommended sampling time is at least:
+ * - For devices STM32F37x: 17.1us for temperature sensor
+ * - For the other STM32F3 devices: 2.2us for each of channels
+ * Vbat/VrefInt/TempSensor.
+ * These internal paths can be be disabled using function
+ * HAL_ADC_DeInit().
+ * @param hadc ADC handle
+ * @param sConfigInjected Structure of ADC injected group and ADC channel for
+ * injected group.
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ __IO uint32_t wait_loop_index = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));
+ assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
+ assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
+ assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv));
+ assert_param(IS_ADC_RANGE(sConfigInjected->InjectedOffset));
+
+ if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
+ {
+ assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
+ assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
+ assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Configuration of injected group sequencer: */
+ /* - if scan mode is disabled, injected channels sequence length is set to */
+ /* 0x00: 1 channel converted (channel on regular rank 1U) */
+ /* Parameter "InjectedNbrOfConversion" is discarded. */
+ /* Note: Scan mode is present by hardware on this device and, if */
+ /* disabled, discards automatically nb of conversions. Anyway, nb of */
+ /* conversions is forced to 0x00 for alignment over all STM32 devices. */
+ /* - if scan mode is enabled, injected channels sequence length is set to */
+ /* parameter "InjectedNbrOfConversion". */
+ if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE)
+ {
+ if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
+ {
+ /* Clear the old SQx bits for all injected ranks */
+ MODIFY_REG(hadc->Instance->JSQR ,
+ ADC_JSQR_JL |
+ ADC_JSQR_JSQ4 |
+ ADC_JSQR_JSQ3 |
+ ADC_JSQR_JSQ2 |
+ ADC_JSQR_JSQ1 ,
+ ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel,
+ ADC_INJECTED_RANK_1,
+ 0x01U) );
+ }
+ /* If another injected rank than rank1 was intended to be set, and could */
+ /* not due to ScanConvMode disabled, error is reported. */
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Since injected channels rank conv. order depends on total number of */
+ /* injected conversions, selected rank must be below or equal to total */
+ /* number of injected conversions to be updated. */
+ if (sConfigInjected->InjectedRank <= sConfigInjected->InjectedNbrOfConversion)
+ {
+ /* Clear the old SQx bits for the selected rank */
+ /* Set the SQx bits for the selected rank */
+ MODIFY_REG(hadc->Instance->JSQR ,
+
+ ADC_JSQR_JL |
+ ADC_JSQR_RK_JL(ADC_JSQR_JSQ1,
+ sConfigInjected->InjectedRank,
+ sConfigInjected->InjectedNbrOfConversion) ,
+
+ ADC_JSQR_JL_SHIFT(sConfigInjected->InjectedNbrOfConversion) |
+ ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel,
+ sConfigInjected->InjectedRank,
+ sConfigInjected->InjectedNbrOfConversion) );
+ }
+ else
+ {
+ /* Clear the old SQx bits for the selected rank */
+ MODIFY_REG(hadc->Instance->JSQR ,
+
+ ADC_JSQR_JL |
+ ADC_JSQR_RK_JL(ADC_JSQR_JSQ1,
+ sConfigInjected->InjectedRank,
+ sConfigInjected->InjectedNbrOfConversion) ,
+
+ 0x00000000 );
+ }
+ }
+
+ /* Configuration of injected group */
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated only when ADC is disabled: */
+ /* - external trigger to start conversion */
+ /* Parameters update not conditioned to ADC state: */
+ /* - Automatic injected conversion */
+ /* - Injected discontinuous mode */
+ /* Note: In case of ADC already enabled, caution to not launch an unwanted */
+ /* conversion while modifying register CR2 by writing 1 to bit ADON. */
+ if (ADC_IS_ENABLE(hadc) == RESET)
+ {
+ MODIFY_REG(hadc->Instance->CR2 ,
+ ADC_CR2_JEXTSEL |
+ ADC_CR2_ADON ,
+ sConfigInjected->ExternalTrigInjecConv );
+ }
+
+ /* Configuration of injected group */
+ /* - Automatic injected conversion */
+ /* - Injected discontinuous mode */
+
+ /* Automatic injected conversion can be enabled if injected group */
+ /* external triggers are disabled. */
+ if (sConfigInjected->AutoInjectedConv == ENABLE)
+ {
+ if (sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
+ {
+ SET_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO);
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+ }
+
+ /* Injected discontinuous can be enabled only if auto-injected mode is */
+ /* disabled. */
+ if (sConfigInjected->InjectedDiscontinuousConvMode == ENABLE)
+ {
+ if (sConfigInjected->AutoInjectedConv == DISABLE)
+ {
+ SET_BIT(hadc->Instance->CR1, ADC_CR1_JDISCEN);
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+ }
+
+
+ /* InjectedChannel sampling time configuration */
+ /* For channels 10 to 18 */
+ if (sConfigInjected->InjectedChannel > ADC_CHANNEL_10)
+ {
+ MODIFY_REG(hadc->Instance->SMPR1,
+ ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel),
+ ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
+ }
+ else /* For channels 1 to 9 */
+ {
+ MODIFY_REG(hadc->Instance->SMPR2,
+ ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel),
+ ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
+ }
+
+
+ /* Configure the offset: offset enable/disable, InjectedChannel, offset value */
+ switch(sConfigInjected->InjectedRank)
+ {
+ case 1:
+ /* Set injected channel 1 offset */
+ MODIFY_REG(hadc->Instance->JOFR1,
+ ADC_JOFR1_JOFFSET1,
+ sConfigInjected->InjectedOffset);
+ break;
+ case 2:
+ /* Set injected channel 2 offset */
+ MODIFY_REG(hadc->Instance->JOFR2,
+ ADC_JOFR2_JOFFSET2,
+ sConfigInjected->InjectedOffset);
+ break;
+ case 3:
+ /* Set injected channel 3 offset */
+ MODIFY_REG(hadc->Instance->JOFR3,
+ ADC_JOFR3_JOFFSET3,
+ sConfigInjected->InjectedOffset);
+ break;
+ case 4:
+ default:
+ MODIFY_REG(hadc->Instance->JOFR4,
+ ADC_JOFR4_JOFFSET4,
+ sConfigInjected->InjectedOffset);
+ break;
+ }
+
+ /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */
+ /* and VREFINT measurement path. */
+ if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) ||
+ (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) )
+ {
+ if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET)
+ {
+ SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
+
+ if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR))
+ {
+ /* Delay for temperature sensor stabilization time */
+ /* Compute number of CPU cycles to wait for */
+ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
+ while(wait_loop_index != 0U)
+ {
+ wait_loop_index--;
+ }
+ }
+ }
+ }
+ /* if ADC1 Channel_18 is selected, enable VBAT measurement path */
+ else if (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT)
+ {
+ SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_VBAT);
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Configures the analog watchdog.
+ * @note Possibility to update parameters on the fly:
+ * This function initializes the selected analog watchdog, following
+ * calls to this function can be used to reconfigure some parameters
+ * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without reseting
+ * the ADC.
+ * The setting of these parameters is conditioned to ADC state.
+ * For parameters constraints, see comments of structure
+ * "ADC_AnalogWDGConfTypeDef".
+ * @param hadc ADC handle
+ * @param AnalogWDGConfig Structure of ADC analog watchdog configuration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ uint32_t tmpAWDHighThresholdShifted;
+ uint32_t tmpAWDLowThresholdShifted;
+
+ uint32_t tmpADCFlagAWD2orAWD3;
+ uint32_t tmpADCITAWD2orAWD3;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(AnalogWDGConfig->WatchdogNumber));
+ assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
+ assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
+
+ /* Verify if threshold is within the selected ADC resolution */
+ assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
+ assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
+
+ if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) ||
+ (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) ||
+ (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) )
+ {
+ assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated when ADC is disabled or enabled without */
+ /* conversion on going on regular and injected groups: */
+ /* - Analog watchdog channels */
+ /* - Analog watchdog thresholds */
+ if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
+ {
+
+ /* Analog watchdogs configuration */
+ if(AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
+ {
+ /* Configuration of analog watchdog: */
+ /* - Set the analog watchdog enable mode: regular and/or injected */
+ /* groups, one or overall group of channels. */
+ /* - Set the Analog watchdog channel (is not used if watchdog */
+ /* mode "all channels": ADC_CFGR_AWD1SGL=0U). */
+ MODIFY_REG(hadc->Instance->CFGR ,
+ ADC_CFGR_AWD1SGL |
+ ADC_CFGR_JAWD1EN |
+ ADC_CFGR_AWD1EN |
+ ADC_CFGR_AWD1CH ,
+ AnalogWDGConfig->WatchdogMode |
+ ADC_CFGR_AWD1CH_SHIFT(AnalogWDGConfig->Channel) );
+
+ /* Shift the offset in function of the selected ADC resolution: */
+ /* Thresholds have to be left-aligned on bit 11U, the LSB (right bits) */
+ /* are set to 0 */
+ tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
+ tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
+
+ /* Set the high and low thresholds */
+ MODIFY_REG(hadc->Instance->TR1 ,
+ ADC_TR1_HT1 |
+ ADC_TR1_LT1 ,
+ ADC_TRX_HIGHTHRESHOLD(tmpAWDHighThresholdShifted) |
+ tmpAWDLowThresholdShifted );
+
+ /* Clear the ADC Analog watchdog flag (in case of left enabled by */
+ /* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */
+ /* or HAL_ADC_PollForEvent(). */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_IT_AWD1);
+
+ /* Configure ADC Analog watchdog interrupt */
+ if(AnalogWDGConfig->ITMode == ENABLE)
+ {
+ /* Enable the ADC Analog watchdog interrupt */
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD1);
+ }
+ else
+ {
+ /* Disable the ADC Analog watchdog interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD1);
+ }
+
+ }
+ /* Case of ADC_ANALOGWATCHDOG_2 and ADC_ANALOGWATCHDOG_3 */
+ else
+ {
+ /* Shift the threshold in function of the selected ADC resolution */
+ /* have to be left-aligned on bit 7U, the LSB (right bits) are set to 0 */
+ tmpAWDHighThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
+ tmpAWDLowThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
+
+ if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
+ {
+ /* Set the Analog watchdog channel or group of channels. This also */
+ /* enables the watchdog. */
+ /* Note: Conditional register reset, because several channels can be */
+ /* set by successive calls of this function. */
+ if (AnalogWDGConfig->WatchdogMode != ADC_ANALOGWATCHDOG_NONE)
+ {
+ /* Set the high and low thresholds */
+ MODIFY_REG(hadc->Instance->TR2 ,
+ ADC_TR2_HT2 |
+ ADC_TR2_LT2 ,
+ ADC_TRX_HIGHTHRESHOLD(tmpAWDHighThresholdShifted) |
+ tmpAWDLowThresholdShifted );
+
+ SET_BIT(hadc->Instance->AWD2CR, ADC_CFGR_AWD23CR(AnalogWDGConfig->Channel));
+ }
+ else
+ {
+ CLEAR_BIT(hadc->Instance->TR2, ADC_TR2_HT2 | ADC_TR2_LT2);
+ CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH);
+ }
+
+ /* Set temporary variable to flag and IT of AWD2 or AWD3 for further */
+ /* settings. */
+ tmpADCFlagAWD2orAWD3 = ADC_FLAG_AWD2;
+ tmpADCITAWD2orAWD3 = ADC_IT_AWD2;
+ }
+ /* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */
+ else
+ {
+ /* Set the Analog watchdog channel or group of channels. This also */
+ /* enables the watchdog. */
+ /* Note: Conditionnal register reset, because several channels can be */
+ /* set by successive calls of this function. */
+ if (AnalogWDGConfig->WatchdogMode != ADC_ANALOGWATCHDOG_NONE)
+ {
+ /* Set the high and low thresholds */
+ MODIFY_REG(hadc->Instance->TR3 ,
+ ADC_TR3_HT3 |
+ ADC_TR3_LT3 ,
+ ADC_TRX_HIGHTHRESHOLD(tmpAWDHighThresholdShifted) |
+ tmpAWDLowThresholdShifted );
+
+ SET_BIT(hadc->Instance->AWD3CR, ADC_CFGR_AWD23CR(AnalogWDGConfig->Channel));
+ }
+ else
+ {
+ CLEAR_BIT(hadc->Instance->TR3, ADC_TR3_HT3 | ADC_TR3_LT3);
+ CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH);
+ }
+
+ /* Set temporary variable to flag and IT of AWD2 or AWD3 for further */
+ /* settings. */
+ tmpADCFlagAWD2orAWD3 = ADC_FLAG_AWD3;
+ tmpADCITAWD2orAWD3 = ADC_IT_AWD3;
+ }
+
+ /* Clear the ADC Analog watchdog flag (in case of left enabled by */
+ /* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */
+ /* or HAL_ADC_PollForEvent(). */
+ __HAL_ADC_CLEAR_FLAG(hadc, tmpADCFlagAWD2orAWD3);
+
+ /* Configure ADC Analog watchdog interrupt */
+ if(AnalogWDGConfig->ITMode == ENABLE)
+ {
+ __HAL_ADC_ENABLE_IT(hadc, tmpADCITAWD2orAWD3);
+ }
+ else
+ {
+ __HAL_ADC_DISABLE_IT(hadc, tmpADCITAWD2orAWD3);
+ }
+ }
+
+ }
+ /* If a conversion is on going on regular or injected groups, no update */
+ /* could be done on neither of the AWD configuration structure parameters. */
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Configures the analog watchdog.
+ * @note Analog watchdog thresholds can be modified while ADC conversion
+ * is on going.
+ * In this case, some constraints must be taken into account:
+ * the programmed threshold values are effective from the next
+ * ADC EOC (end of unitary conversion).
+ * Considering that registers write delay may happen due to
+ * bus activity, this might cause an uncertainty on the
+ * effective timing of the new programmed threshold values.
+ * @param hadc ADC handle
+ * @param AnalogWDGConfig Structure of ADC analog watchdog configuration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
+ assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
+ assert_param(IS_ADC_RANGE(AnalogWDGConfig->HighThreshold));
+ assert_param(IS_ADC_RANGE(AnalogWDGConfig->LowThreshold));
+
+ if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) ||
+ (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) ||
+ (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) )
+ {
+ assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Analog watchdog configuration */
+
+ /* Configure ADC Analog watchdog interrupt */
+ if(AnalogWDGConfig->ITMode == ENABLE)
+ {
+ /* Enable the ADC Analog watchdog interrupt */
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);
+ }
+ else
+ {
+ /* Disable the ADC Analog watchdog interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);
+ }
+
+ /* Configuration of analog watchdog: */
+ /* - Set the analog watchdog enable mode: regular and/or injected groups, */
+ /* one or all channels. */
+ /* - Set the Analog watchdog channel (is not used if watchdog */
+ /* mode "all channels": ADC_CFGR_AWD1SGL=0U). */
+ MODIFY_REG(hadc->Instance->CR1 ,
+ ADC_CR1_AWDSGL |
+ ADC_CR1_JAWDEN |
+ ADC_CR1_AWDEN |
+ ADC_CR1_AWDCH ,
+ AnalogWDGConfig->WatchdogMode |
+ AnalogWDGConfig->Channel );
+
+ /* Set the high threshold */
+ WRITE_REG(hadc->Instance->HTR, AnalogWDGConfig->HighThreshold);
+
+ /* Set the low threshold */
+ WRITE_REG(hadc->Instance->LTR, AnalogWDGConfig->LowThreshold);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+#endif /* STM32F373xC || STM32F378xx */
+
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+/**
+ * @brief Enable ADC multimode and configure multimode parameters
+ * @note Possibility to update parameters on the fly:
+ * This function initializes multimode parameters, following
+ * calls to this function can be used to reconfigure some parameters
+ * of structure "ADC_MultiModeTypeDef" on the fly, without reseting
+ * the ADCs (both ADCs of the common group).
+ * The setting of these parameters is conditioned to ADC state.
+ * For parameters constraints, see comments of structure
+ * "ADC_MultiModeTypeDef".
+ * @note To change back configuration from multimode to single mode, ADC must
+ * be reset (using function HAL_ADC_Init() ).
+ * @param hadc ADC handle
+ * @param multimode Structure of ADC multimode configuration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ ADC_Common_TypeDef *tmpADC_Common;
+ ADC_HandleTypeDef tmphadcSharingSameCommonRegister;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_MODE(multimode->Mode));
+ if(multimode->Mode != ADC_MODE_INDEPENDENT)
+ {
+ assert_param(IS_ADC_DMA_ACCESS_MODE(multimode->DMAAccessMode));
+ assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
+ }
+
+ /* Set handle of the other ADC sharing the same common register */
+ ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister);
+ if (tmphadcSharingSameCommonRegister.Instance == NULL)
+ {
+ /* Return function status */
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated when ADC is disabled or enabled without */
+ /* conversion on going on regular group: */
+ /* - Multimode DMA configuration */
+ /* - Multimode DMA mode */
+ if ( (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+ && (ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSharingSameCommonRegister) == RESET) )
+ {
+ /* Pointer to the common control register to which is belonging hadc */
+ /* (Depending on STM32F3 product, there may have up to 4 ADC and 2 common */
+ /* control registers) */
+ tmpADC_Common = ADC_COMMON_REGISTER(hadc);
+
+ /* If multimode is selected, configure all multimode paramaters. */
+ /* Otherwise, reset multimode parameters (can be used in case of */
+ /* transition from multimode to independent mode). */
+ if(multimode->Mode != ADC_MODE_INDEPENDENT)
+ {
+ /* Configuration of ADC common group ADC1&ADC2, ADC3&ADC4 if available */
+ /* (ADC2, ADC3, ADC4 availability depends on STM32 product) */
+ /* - DMA access mode */
+ MODIFY_REG(tmpADC_Common->CCR ,
+ ADC_CCR_MDMA |
+ ADC_CCR_DMACFG ,
+ multimode->DMAAccessMode |
+ ADC_CCR_MULTI_DMACONTREQ(hadc->Init.DMAContinuousRequests) );
+
+ /* Parameters that can be updated only when ADC is disabled: */
+ /* - Multimode mode selection */
+ /* - Set delay between two sampling phases */
+ /* Note: Delay range depends on selected resolution: */
+ /* from 1 to 12 clock cycles for 12 bits */
+ /* from 1 to 10 clock cycles for 10 bits, */
+ /* from 1 to 8 clock cycles for 8 bits */
+ /* from 1 to 6 clock cycles for 6 bits */
+ /* If a higher delay is selected, it will be clamped to maximum delay */
+ /* range */
+ /* Note: If ADC is not in the appropriate state to modify these */
+ /* parameters, their setting is bypassed without error reporting */
+ /* (as it can be the expected behaviour in case of intended action */
+ /* to update parameter above (which fulfills the ADC state */
+ /* condition: no conversion on going on group regular) */
+ /* on the fly). */
+ if ((ADC_IS_ENABLE(hadc) == RESET) &&
+ (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) )
+ {
+ MODIFY_REG(tmpADC_Common->CCR ,
+ ADC_CCR_MULTI |
+ ADC_CCR_DELAY ,
+ multimode->Mode |
+ multimode->TwoSamplingDelay );
+ }
+ }
+ else /* ADC_MODE_INDEPENDENT */
+ {
+ CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG);
+
+ /* Parameters that can be updated only when ADC is disabled: */
+ /* - Multimode mode selection */
+ /* - Multimode delay */
+ if ((ADC_IS_ENABLE(hadc) == RESET) &&
+ (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) )
+ {
+ CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MULTI | ADC_CCR_DELAY);
+ }
+ }
+ }
+ /* If one of the ADC sharing the same common group is enabled, no update */
+ /* could be done on neither of the multimode structure parameters. */
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F328xx || STM32F334x8 */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_Private_Functions ADCEx Private Functions
+ * @{
+ */
+/**
+ * @brief DMA transfer complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
+{
+ /* Retrieve ADC handle corresponding to current DMA handle */
+ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Update state machine on conversion status if not in error state */
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
+ {
+ /* Update ADC state machine */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+
+ /* Determine whether any further conversion upcoming on group regular */
+ /* by external trigger, continuous mode or scan sequence on going. */
+ /* Note: On STM32F3 devices, in case of sequencer enabled */
+ /* (several ranks selected), end of conversion flag is raised */
+ /* at the end of the sequence. */
+ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+ (hadc->Init.ContinuousConvMode == DISABLE) )
+ {
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+
+ /* Conversion complete callback */
+ HAL_ADC_ConvCpltCallback(hadc);
+ }
+ else
+ {
+ /* Call DMA error callback */
+ hadc->DMA_Handle->XferErrorCallback(hdma);
+ }
+}
+
+/**
+ * @brief DMA half transfer complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
+{
+ /* Retrieve ADC handle corresponding to current DMA handle */
+ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Half conversion callback */
+ HAL_ADC_ConvHalfCpltCallback(hadc);
+}
+
+/**
+ * @brief DMA error callback
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void ADC_DMAError(DMA_HandleTypeDef *hdma)
+{
+ /* Retrieve ADC handle corresponding to current DMA handle */
+ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+
+ /* Set ADC error code to DMA error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
+
+ /* Error callback */
+ HAL_ADC_ErrorCallback(hadc);
+}
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Enable the selected ADC.
+ * @note Prerequisite condition to use this function: ADC must be disabled
+ * and voltage regulator must be enabled (done into HAL_ADC_Init()).
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
+{
+ uint32_t tickstart = 0U;
+
+ /* ADC enable and wait for ADC ready (in case of ADC is disabled or */
+ /* enabling phase not yet completed: flag ADC ready not yet set). */
+ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
+ /* causes: ADC clock not running, ...). */
+ if (ADC_IS_ENABLE(hadc) == RESET)
+ {
+ /* Check if conditions to enable the ADC are fulfilled */
+ if (ADC_ENABLING_CONDITIONS(hadc) == RESET)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC IP internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
+
+ /* Enable the ADC peripheral */
+ __HAL_ADC_ENABLE(hadc);
+
+ /* Wait for ADC effectively enabled */
+ tickstart = HAL_GetTick();
+
+ while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC IP internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /* Return HAL status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the selected ADC.
+ * @note Prerequisite condition to use this function: ADC conversions must be
+ * stopped.
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc)
+{
+ uint32_t tickstart = 0U;
+
+ /* Verification if ADC is not already disabled: */
+ /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */
+ /* disabled. */
+ if (ADC_IS_ENABLE(hadc) != RESET )
+ {
+ /* Check if conditions to disable the ADC are fulfilled */
+ if (ADC_DISABLING_CONDITIONS(hadc) != RESET)
+ {
+ /* Disable the ADC peripheral */
+ __HAL_ADC_DISABLE(hadc);
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC IP internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
+
+ /* Wait for ADC effectively disabled */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN))
+ {
+ if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC IP internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /* Return HAL status */
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Stop ADC conversion.
+ * @param hadc ADC handle
+ * @param ConversionGroup ADC group regular and/or injected.
+ * This parameter can be one of the following values:
+ * @arg ADC_REGULAR_GROUP: ADC regular conversion type.
+ * @arg ADC_INJECTED_GROUP: ADC injected conversion type.
+ * @arg ADC_REGULAR_INJECTED_GROUP: ADC regular and injected conversion type.
+ * @retval HAL status.
+ */
+static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup)
+{
+ uint32_t tmp_ADC_CR_ADSTART_JADSTART = 0U;
+ uint32_t tickstart = 0U;
+ uint32_t Conversion_Timeout_CPU_cycles = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup));
+
+ /* Verification if ADC is not already stopped (on regular and injected */
+ /* groups) to bypass this function if not needed. */
+ if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc))
+ {
+ /* Particular case of continuous auto-injection mode combined with */
+ /* auto-delay mode. */
+ /* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not */
+ /* injected group stop ADC_CR_JADSTP). */
+ /* Procedure to be followed: Wait until JEOS=1U, clear JEOS, set ADSTP=1 */
+ /* (see reference manual). */
+ if ((HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_JAUTO)) &&
+ (hadc->Init.ContinuousConvMode==ENABLE) &&
+ (hadc->Init.LowPowerAutoWait==ENABLE) )
+ {
+ /* Use stop of regular group */
+ ConversionGroup = ADC_REGULAR_GROUP;
+
+ /* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */
+ while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == RESET)
+ {
+ if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES *4U))
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC IP internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
+ Conversion_Timeout_CPU_cycles ++;
+ }
+
+ /* Clear JEOS */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS);
+ }
+
+ /* Stop potential conversion on going on regular group */
+ if (ConversionGroup != ADC_INJECTED_GROUP)
+ {
+ /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0U */
+ if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) &&
+ HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) )
+ {
+ /* Stop conversions on regular group */
+ hadc->Instance->CR |= ADC_CR_ADSTP;
+ }
+ }
+
+ /* Stop potential conversion on going on injected group */
+ if (ConversionGroup != ADC_REGULAR_GROUP)
+ {
+ /* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0U */
+ if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_JADSTART) &&
+ HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) )
+ {
+ /* Stop conversions on injected group */
+ hadc->Instance->CR |= ADC_CR_JADSTP;
+ }
+ }
+
+ /* Selection of start and stop bits in function of regular or injected group */
+ switch(ConversionGroup)
+ {
+ case ADC_REGULAR_INJECTED_GROUP:
+ tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART | ADC_CR_JADSTART);
+ break;
+ case ADC_INJECTED_GROUP:
+ tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART;
+ break;
+ /* Case ADC_REGULAR_GROUP */
+ default:
+ tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART;
+ break;
+ }
+
+ /* Wait for conversion effectively stopped */
+ tickstart = HAL_GetTick();
+
+ while((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != RESET)
+ {
+ if((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC IP internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
+ }
+
+ }
+
+ /* Return HAL status */
+ return HAL_OK;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Enable the selected ADC.
+ * @note Prerequisite condition to use this function: ADC must be disabled
+ * and voltage regulator must be enabled (done into HAL_ADC_Init()).
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
+{
+ uint32_t tickstart = 0U;
+ __IO uint32_t wait_loop_index = 0U;
+
+ /* ADC enable and wait for ADC ready (in case of ADC is disabled or */
+ /* enabling phase not yet completed: flag ADC ready not yet set). */
+ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
+ /* causes: ADC clock not running, ...). */
+ if (ADC_IS_ENABLE(hadc) == RESET)
+ {
+ /* Enable the Peripheral */
+ __HAL_ADC_ENABLE(hadc);
+
+ /* Delay for ADC stabilization time */
+ /* Compute number of CPU cycles to wait for */
+ wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
+ while(wait_loop_index != 0U)
+ {
+ wait_loop_index--;
+ }
+
+ /* Get tick count */
+ tickstart = HAL_GetTick();
+
+ /* Wait for ADC effectively enabled */
+ while(ADC_IS_ENABLE(hadc) == RESET)
+ {
+ if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC IP internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /* Return HAL status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop ADC conversion and disable the selected ADC
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+static HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc)
+{
+ uint32_t tickstart = 0U;
+
+ /* Verification if ADC is not already disabled: */
+ if (ADC_IS_ENABLE(hadc) != RESET)
+ {
+ /* Disable the ADC peripheral */
+ __HAL_ADC_DISABLE(hadc);
+
+ /* Get tick count */
+ tickstart = HAL_GetTick();
+
+ /* Wait for ADC effectively disabled */
+ while(ADC_IS_ENABLE(hadc) != RESET)
+ {
+ if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC IP internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /* Return HAL status */
+ return HAL_OK;
+}
+#endif /* STM32F373xC || STM32F378xx */
+/**
+ * @}
+ */
+
+#endif /* HAL_ADC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_can.c b/Src/stm32f3xx_hal_can.c
new file mode 100644
index 0000000..80de00c
--- /dev/null
+++ b/Src/stm32f3xx_hal_can.c
@@ -0,0 +1,1985 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_can.c
+ * @author MCD Application Team
+ * @brief CAN HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Controller Area Network (CAN) peripheral:
+ * + Initialization and de-initialization functions
+ * + Configuration functions
+ * + Control functions
+ * + Interrupts management
+ * + Callbacks functions
+ * + Peripheral State and Error functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Initialize the CAN low level resources by implementing the
+ HAL_CAN_MspInit():
+ (++) Enable the CAN interface clock using __HAL_RCC_CANx_CLK_ENABLE()
+ (++) Configure CAN pins
+ (+++) Enable the clock for the CAN GPIOs
+ (+++) Configure CAN pins as alternate function open-drain
+ (++) In case of using interrupts (e.g. HAL_CAN_ActivateNotification())
+ (+++) Configure the CAN interrupt priority using
+ HAL_NVIC_SetPriority()
+ (+++) Enable the CAN IRQ handler using HAL_NVIC_EnableIRQ()
+ (+++) In CAN IRQ handler, call HAL_CAN_IRQHandler()
+
+ (#) Initialize the CAN peripheral using HAL_CAN_Init() function. This
+ function resorts to HAL_CAN_MspInit() for low-level initialization.
+
+ (#) Configure the reception filters using the following configuration
+ functions:
+ (++) HAL_CAN_ConfigFilter()
+
+ (#) Start the CAN module using HAL_CAN_Start() function. At this level
+ the node is active on the bus: it receive messages, and can send
+ messages.
+
+ (#) To manage messages transmission, the following Tx control functions
+ can be used:
+ (++) HAL_CAN_AddTxMessage() to request transmission of a new
+ message.
+ (++) HAL_CAN_AbortTxRequest() to abort transmission of a pending
+ message.
+ (++) HAL_CAN_GetTxMailboxesFreeLevel() to get the number of free Tx
+ mailboxes.
+ (++) HAL_CAN_IsTxMessagePending() to check if a message is pending
+ in a Tx mailbox.
+ (++) HAL_CAN_GetTxTimestamp() to get the timestamp of Tx message
+ sent, if time triggered communication mode is enabled.
+
+ (#) When a message is received into the CAN Rx FIFOs, it can be retrieved
+ using the HAL_CAN_GetRxMessage() function. The function
+ HAL_CAN_GetRxFifoFillLevel() allows to know how many Rx message are
+ stored in the Rx Fifo.
+
+ (#) Calling the HAL_CAN_Stop() function stops the CAN module.
+
+ (#) The deinitialization is achieved with HAL_CAN_DeInit() function.
+
+
+ *** Polling mode operation ***
+ ==============================
+ [..]
+ (#) Reception:
+ (++) Monitor reception of message using HAL_CAN_GetRxFifoFillLevel()
+ until at least one message is received.
+ (++) Then get the message using HAL_CAN_GetRxMessage().
+
+ (#) Transmission:
+ (++) Monitor the Tx mailboxes availability until at least one Tx
+ mailbox is free, using HAL_CAN_GetTxMailboxesFreeLevel().
+ (++) Then request transmission of a message using
+ HAL_CAN_AddTxMessage().
+
+
+ *** Interrupt mode operation ***
+ ================================
+ [..]
+ (#) Notifications are activated using HAL_CAN_ActivateNotification()
+ function. Then, the process can be controlled through the
+ available user callbacks: HAL_CAN_xxxCallback(), using same APIs
+ HAL_CAN_GetRxMessage() and HAL_CAN_AddTxMessage().
+
+ (#) Notifications can be deactivated using
+ HAL_CAN_DeactivateNotification() function.
+
+ (#) Special care should be taken for CAN_IT_RX_FIFO0_MSG_PENDING and
+ CAN_IT_RX_FIFO1_MSG_PENDING notifications. These notifications trig
+ the callbacks HAL_CAN_RxFIFO0MsgPendingCallback() and
+ HAL_CAN_RxFIFO1MsgPendingCallback(). User has two possible options
+ here.
+ (++) Directly get the Rx message in the callback, using
+ HAL_CAN_GetRxMessage().
+ (++) Or deactivate the notification in the callback without
+ getting the Rx message. The Rx message can then be got later
+ using HAL_CAN_GetRxMessage(). Once the Rx message have been
+ read, the notification can be activated again.
+
+
+ *** Sleep mode ***
+ ==================
+ [..]
+ (#) The CAN peripheral can be put in sleep mode (low power), using
+ HAL_CAN_RequestSleep(). The sleep mode will be entered as soon as the
+ current CAN activity (transmission or reception of a CAN frame) will
+ be completed.
+
+ (#) A notification can be activated to be informed when the sleep mode
+ will be entered.
+
+ (#) It can be checked if the sleep mode is entered using
+ HAL_CAN_IsSleepActive().
+ Note that the CAN state (accessible from the API HAL_CAN_GetState())
+ is HAL_CAN_STATE_SLEEP_PENDING as soon as the sleep mode request is
+ submitted (the sleep mode is not yet entered), and become
+ HAL_CAN_STATE_SLEEP_ACTIVE when the sleep mode is effective.
+
+ (#) The wake-up from sleep mode can be trigged by two ways:
+ (++) Using HAL_CAN_WakeUp(). When returning from this function,
+ the sleep mode is exited (if return status is HAL_OK).
+ (++) When a start of Rx CAN frame is detected by the CAN peripheral,
+ if automatic wake up mode is enabled.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+#if defined(CAN)
+
+/** @defgroup CAN CAN
+ * @brief CAN driver modules
+ * @{
+ */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+
+#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
+ #error "The CAN driver cannot be used with its legacy, Please enable only one CAN module at once"
+#endif
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup CAN_Private_Constants CAN Private Constants
+ * @{
+ */
+#define CAN_TIMEOUT_VALUE 10U
+/**
+ * @}
+ */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup CAN_Exported_Functions CAN Exported Functions
+ * @{
+ */
+
+/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de-initialization functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) HAL_CAN_Init : Initialize and configure the CAN.
+ (+) HAL_CAN_DeInit : De-initialize the CAN.
+ (+) HAL_CAN_MspInit : Initialize the CAN MSP.
+ (+) HAL_CAN_MspDeInit : DeInitialize the CAN MSP.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the CAN peripheral according to the specified
+ * parameters in the CAN_InitStruct.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan)
+{
+ uint32_t tickstart;
+
+ /* Check CAN handle */
+ if (hcan == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TimeTriggeredMode));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoBusOff));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoWakeUp));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoRetransmission));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ReceiveFifoLocked));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TransmitFifoPriority));
+ assert_param(IS_CAN_MODE(hcan->Init.Mode));
+ assert_param(IS_CAN_SJW(hcan->Init.SyncJumpWidth));
+ assert_param(IS_CAN_BS1(hcan->Init.TimeSeg1));
+ assert_param(IS_CAN_BS2(hcan->Init.TimeSeg2));
+ assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));
+
+ if (hcan->State == HAL_CAN_STATE_RESET)
+ {
+ /* Init the low level hardware: CLOCK, NVIC */
+ HAL_CAN_MspInit(hcan);
+ }
+
+ /* Exit from sleep mode */
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Check Sleep mode leave acknowledge */
+ while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Request initialisation */
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait initialisation acknowledge */
+ while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Set the time triggered communication mode */
+ if (hcan->Init.TimeTriggeredMode == ENABLE)
+ {
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
+ }
+ else
+ {
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
+ }
+
+ /* Set the automatic bus-off management */
+ if (hcan->Init.AutoBusOff == ENABLE)
+ {
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
+ }
+ else
+ {
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
+ }
+
+ /* Set the automatic wake-up mode */
+ if (hcan->Init.AutoWakeUp == ENABLE)
+ {
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
+ }
+ else
+ {
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
+ }
+
+ /* Set the automatic retransmission */
+ if (hcan->Init.AutoRetransmission == ENABLE)
+ {
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART);
+ }
+ else
+ {
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_NART);
+ }
+
+ /* Set the receive FIFO locked mode */
+ if (hcan->Init.ReceiveFifoLocked == ENABLE)
+ {
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
+ }
+ else
+ {
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
+ }
+
+ /* Set the transmit FIFO priority */
+ if (hcan->Init.TransmitFifoPriority == ENABLE)
+ {
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
+ }
+ else
+ {
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
+ }
+
+ /* Set the bit timing register */
+ WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode |
+ hcan->Init.SyncJumpWidth |
+ hcan->Init.TimeSeg1 |
+ hcan->Init.TimeSeg2 |
+ (hcan->Init.Prescaler - 1U)));
+
+ /* Initialize the error code */
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+
+ /* Initialize the CAN state */
+ hcan->State = HAL_CAN_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Deinitializes the CAN peripheral registers to their default
+ * reset values.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan)
+{
+ /* Check CAN handle */
+ if (hcan == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
+
+ /* Stop the CAN module */
+ (void)HAL_CAN_Stop(hcan);
+
+ /* DeInit the low level hardware: CLOCK, NVIC */
+ HAL_CAN_MspDeInit(hcan);
+
+ /* Reset the CAN peripheral */
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET);
+
+ /* Reset the CAN ErrorCode */
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_RESET;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CAN MSP.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the CAN MSP.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_MspDeInit could be implemented in the user file
+ */
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Exported_Functions_Group2 Configuration functions
+ * @brief Configuration functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Configuration functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) HAL_CAN_ConfigFilter : Configure the CAN reception filters
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the CAN reception filter according to the specified
+ * parameters in the CAN_FilterInitStruct.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param sFilterConfig pointer to a CAN_FilterTypeDef structure that
+ * contains the filter configuration information.
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig)
+{
+ uint32_t filternbrbitpos;
+ CAN_TypeDef *can_ip = hcan->Instance;
+ HAL_CAN_StateTypeDef state = hcan->State;
+
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
+ {
+ /* Check the parameters */
+ assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdHigh));
+ assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdLow));
+ assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdHigh));
+ assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdLow));
+ assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
+ assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));
+ assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));
+ assert_param(IS_CAN_FILTER_ACTIVATION(sFilterConfig->FilterActivation));
+
+ /* CAN is single instance with 14 dedicated filters banks */
+
+ /* Check the parameters */
+ assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank));
+
+ /* Initialisation mode for the filter */
+ SET_BIT(can_ip->FMR, CAN_FMR_FINIT);
+
+ /* Convert filter number into bit position */
+ filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU);
+
+ /* Filter Deactivation */
+ CLEAR_BIT(can_ip->FA1R, filternbrbitpos);
+
+ /* Filter Scale */
+ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
+ {
+ /* 16-bit scale for the filter */
+ CLEAR_BIT(can_ip->FS1R, filternbrbitpos);
+
+ /* First 16-bit identifier and First 16-bit mask */
+ /* Or First 16-bit identifier and Second 16-bit identifier */
+ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
+
+ /* Second 16-bit identifier and Second 16-bit mask */
+ /* Or Third 16-bit identifier and Fourth 16-bit identifier */
+ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh);
+ }
+
+ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
+ {
+ /* 32-bit scale for the filter */
+ SET_BIT(can_ip->FS1R, filternbrbitpos);
+
+ /* 32-bit identifier or First 32-bit identifier */
+ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
+
+ /* 32-bit mask or Second 32-bit identifier */
+ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow);
+ }
+
+ /* Filter Mode */
+ if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
+ {
+ /* Id/Mask mode for the filter*/
+ CLEAR_BIT(can_ip->FM1R, filternbrbitpos);
+ }
+ else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
+ {
+ /* Identifier list mode for the filter*/
+ SET_BIT(can_ip->FM1R, filternbrbitpos);
+ }
+
+ /* Filter FIFO assignment */
+ if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
+ {
+ /* FIFO 0 assignation for the filter */
+ CLEAR_BIT(can_ip->FFA1R, filternbrbitpos);
+ }
+ else
+ {
+ /* FIFO 1 assignation for the filter */
+ SET_BIT(can_ip->FFA1R, filternbrbitpos);
+ }
+
+ /* Filter activation */
+ if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE)
+ {
+ SET_BIT(can_ip->FA1R, filternbrbitpos);
+ }
+
+ /* Leave the initialisation mode for the filter */
+ CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Exported_Functions_Group3 Control functions
+ * @brief Control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Control functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) HAL_CAN_Start : Start the CAN module
+ (+) HAL_CAN_Stop : Stop the CAN module
+ (+) HAL_CAN_RequestSleep : Request sleep mode entry.
+ (+) HAL_CAN_WakeUp : Wake up from sleep mode.
+ (+) HAL_CAN_IsSleepActive : Check is sleep mode is active.
+ (+) HAL_CAN_AddTxMessage : Add a message to the Tx mailboxes
+ and activate the corresponding
+ transmission request
+ (+) HAL_CAN_AbortTxRequest : Abort transmission request
+ (+) HAL_CAN_GetTxMailboxesFreeLevel : Return Tx mailboxes free level
+ (+) HAL_CAN_IsTxMessagePending : Check if a transmission request is
+ pending on the selected Tx mailbox
+ (+) HAL_CAN_GetRxMessage : Get a CAN frame from the Rx FIFO
+ (+) HAL_CAN_GetRxFifoFillLevel : Return Rx FIFO fill level
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Start the CAN module.
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan)
+{
+ uint32_t tickstart;
+
+ if (hcan->State == HAL_CAN_STATE_READY)
+ {
+ /* Change CAN peripheral state */
+ hcan->State = HAL_CAN_STATE_LISTENING;
+
+ /* Request leave initialisation */
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait the acknowledge */
+ while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U)
+ {
+ /* Check for the Timeout */
+ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Reset the CAN ErrorCode */
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Stop the CAN module and enable access to configuration registers.
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan)
+{
+ uint32_t tickstart;
+
+ if (hcan->State == HAL_CAN_STATE_LISTENING)
+ {
+ /* Request initialisation */
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait the acknowledge */
+ while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U)
+ {
+ /* Check for the Timeout */
+ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Exit from sleep mode */
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
+
+ /* Change CAN peripheral state */
+ hcan->State = HAL_CAN_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_STARTED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Request the sleep mode (low power) entry.
+ * When returning from this function, Sleep mode will be entered
+ * as soon as the current CAN activity (transmission or reception
+ * of a CAN frame) has been completed.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan)
+{
+ HAL_CAN_StateTypeDef state = hcan->State;
+
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
+ {
+ /* Request Sleep mode */
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Wake up from sleep mode.
+ * When returning with HAL_OK status from this function, Sleep mode
+ * is exited.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan)
+{
+ __IO uint32_t count = 0;
+ uint32_t timeout = 1000000U;
+ HAL_CAN_StateTypeDef state = hcan->State;
+
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
+ {
+ /* Wake up request */
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
+
+ /* Wait sleep mode is exited */
+ do
+ {
+ /* Increment counter */
+ count++;
+
+ /* Check if timeout is reached */
+ if (count > timeout)
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
+
+ return HAL_ERROR;
+ }
+ }
+ while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Check is sleep mode is active.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval Status
+ * - 0 : Sleep mode is not active.
+ * - 1 : Sleep mode is active.
+ */
+uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan)
+{
+ uint32_t status = 0U;
+ HAL_CAN_StateTypeDef state = hcan->State;
+
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
+ {
+ /* Check Sleep mode */
+ if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
+ {
+ status = 1U;
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Add a message to the first free Tx mailbox and activate the
+ * corresponding transmission request.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param pHeader pointer to a CAN_TxHeaderTypeDef structure.
+ * @param aData array containing the payload of the Tx frame.
+ * @param pTxMailbox pointer to a variable where the function will return
+ * the TxMailbox used to store the Tx message.
+ * This parameter can be a value of @arg CAN_Tx_Mailboxes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox)
+{
+ uint32_t transmitmailbox;
+ HAL_CAN_StateTypeDef state = hcan->State;
+ uint32_t tsr = READ_REG(hcan->Instance->TSR);
+
+ /* Check the parameters */
+ assert_param(IS_CAN_IDTYPE(pHeader->IDE));
+ assert_param(IS_CAN_RTR(pHeader->RTR));
+ assert_param(IS_CAN_DLC(pHeader->DLC));
+ if (pHeader->IDE == CAN_ID_STD)
+ {
+ assert_param(IS_CAN_STDID(pHeader->StdId));
+ }
+ else
+ {
+ assert_param(IS_CAN_EXTID(pHeader->ExtId));
+ }
+ assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime));
+
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
+ {
+ /* Check that all the Tx mailboxes are not full */
+ if (((tsr & CAN_TSR_TME0) != 0U) ||
+ ((tsr & CAN_TSR_TME1) != 0U) ||
+ ((tsr & CAN_TSR_TME2) != 0U))
+ {
+ /* Select an empty transmit mailbox */
+ transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos;
+
+ /* Check transmit mailbox value */
+ if (transmitmailbox > 2U)
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_INTERNAL;
+
+ return HAL_ERROR;
+ }
+
+ /* Store the Tx mailbox */
+ *pTxMailbox = (uint32_t)1 << transmitmailbox;
+
+ /* Set up the Id */
+ if (pHeader->IDE == CAN_ID_STD)
+ {
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) |
+ pHeader->RTR);
+ }
+ else
+ {
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
+ pHeader->IDE |
+ pHeader->RTR);
+ }
+
+ /* Set up the DLC */
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC);
+
+ /* Set up the Transmit Global Time mode */
+ if (pHeader->TransmitGlobalTime == ENABLE)
+ {
+ SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT);
+ }
+
+ /* Set up the data field */
+ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR,
+ ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) |
+ ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) |
+ ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) |
+ ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos));
+ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR,
+ ((uint32_t)aData[3] << CAN_TDL0R_DATA3_Pos) |
+ ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) |
+ ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) |
+ ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos));
+
+ /* Request transmission */
+ SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Abort transmission requests
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param TxMailboxes List of the Tx Mailboxes to abort.
+ * This parameter can be any combination of @arg CAN_Tx_Mailboxes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes)
+{
+ HAL_CAN_StateTypeDef state = hcan->State;
+
+ /* Check function parameters */
+ assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes));
+
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
+ {
+ /* Check Tx Mailbox 0 */
+ if ((TxMailboxes & CAN_TX_MAILBOX0) != 0U)
+ {
+ /* Add cancellation request for Tx Mailbox 0 */
+ SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ0);
+ }
+
+ /* Check Tx Mailbox 1 */
+ if ((TxMailboxes & CAN_TX_MAILBOX1) != 0U)
+ {
+ /* Add cancellation request for Tx Mailbox 1 */
+ SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ1);
+ }
+
+ /* Check Tx Mailbox 2 */
+ if ((TxMailboxes & CAN_TX_MAILBOX2) != 0U)
+ {
+ /* Add cancellation request for Tx Mailbox 2 */
+ SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ2);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Return Tx Mailboxes free level: number of free Tx Mailboxes.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval Number of free Tx Mailboxes.
+ */
+uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan)
+{
+ uint32_t freelevel = 0U;
+ HAL_CAN_StateTypeDef state = hcan->State;
+
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
+ {
+ /* Check Tx Mailbox 0 status */
+ if ((hcan->Instance->TSR & CAN_TSR_TME0) != 0U)
+ {
+ freelevel++;
+ }
+
+ /* Check Tx Mailbox 1 status */
+ if ((hcan->Instance->TSR & CAN_TSR_TME1) != 0U)
+ {
+ freelevel++;
+ }
+
+ /* Check Tx Mailbox 2 status */
+ if ((hcan->Instance->TSR & CAN_TSR_TME2) != 0U)
+ {
+ freelevel++;
+ }
+ }
+
+ /* Return Tx Mailboxes free level */
+ return freelevel;
+}
+
+/**
+ * @brief Check if a transmission request is pending on the selected Tx
+ * Mailboxes.
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param TxMailboxes List of Tx Mailboxes to check.
+ * This parameter can be any combination of @arg CAN_Tx_Mailboxes.
+ * @retval Status
+ * - 0 : No pending transmission request on any selected Tx Mailboxes.
+ * - 1 : Pending transmission request on at least one of the selected
+ * Tx Mailbox.
+ */
+uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes)
+{
+ uint32_t status = 0U;
+ HAL_CAN_StateTypeDef state = hcan->State;
+
+ /* Check function parameters */
+ assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes));
+
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
+ {
+ /* Check pending transmission request on the selected Tx Mailboxes */
+ if ((hcan->Instance->TSR & (TxMailboxes << CAN_TSR_TME0_Pos)) != (TxMailboxes << CAN_TSR_TME0_Pos))
+ {
+ status = 1U;
+ }
+ }
+
+ /* Return status */
+ return status;
+}
+
+/**
+ * @brief Return timestamp of Tx message sent, if time triggered communication
+ mode is enabled.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param TxMailbox Tx Mailbox where the timestamp of message sent will be
+ * read.
+ * This parameter can be one value of @arg CAN_Tx_Mailboxes.
+ * @retval Timestamp of message sent from Tx Mailbox.
+ */
+uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox)
+{
+ uint32_t timestamp = 0U;
+ uint32_t transmitmailbox;
+ HAL_CAN_StateTypeDef state = hcan->State;
+
+ /* Check function parameters */
+ assert_param(IS_CAN_TX_MAILBOX(TxMailbox));
+
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
+ {
+ /* Select the Tx mailbox */
+ transmitmailbox = POSITION_VAL(TxMailbox);
+
+ /* Get timestamp */
+ timestamp = (hcan->Instance->sTxMailBox[transmitmailbox].TDTR & CAN_TDT0R_TIME) >> CAN_TDT0R_TIME_Pos;
+ }
+
+ /* Return the timestamp */
+ return timestamp;
+}
+
+/**
+ * @brief Get an CAN frame from the Rx FIFO zone into the message RAM.
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param RxFifo Fifo number of the received message to be read.
+ * This parameter can be a value of @arg CAN_receive_FIFO_number.
+ * @param pHeader pointer to a CAN_RxHeaderTypeDef structure where the header
+ * of the Rx frame will be stored.
+ * @param aData array where the payload of the Rx frame will be stored.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[])
+{
+ HAL_CAN_StateTypeDef state = hcan->State;
+
+ assert_param(IS_CAN_RX_FIFO(RxFifo));
+
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
+ {
+ /* Check the Rx FIFO */
+ if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */
+ {
+ /* Check that the Rx FIFO 0 is not empty */
+ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U)
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
+
+ return HAL_ERROR;
+ }
+ }
+ else /* Rx element is assigned to Rx FIFO 1 */
+ {
+ /* Check that the Rx FIFO 1 is not empty */
+ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U)
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Get the header */
+ pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR;
+ if (pHeader->IDE == CAN_ID_STD)
+ {
+ pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos;
+ }
+ else
+ {
+ pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos;
+ }
+ pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_RTR_Pos;
+ pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos;
+ pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos;
+ pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos;
+
+ /* Get the data */
+ aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos);
+ aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos);
+ aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos);
+ aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos);
+ aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos);
+ aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos);
+ aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos);
+ aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos);
+
+ /* Release the FIFO */
+ if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */
+ {
+ /* Release RX FIFO 0 */
+ SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0);
+ }
+ else /* Rx element is assigned to Rx FIFO 1 */
+ {
+ /* Release RX FIFO 1 */
+ SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Return Rx FIFO fill level.
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param RxFifo Rx FIFO.
+ * This parameter can be a value of @arg CAN_receive_FIFO_number.
+ * @retval Number of messages available in Rx FIFO.
+ */
+uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo)
+{
+ uint32_t filllevel = 0U;
+ HAL_CAN_StateTypeDef state = hcan->State;
+
+ /* Check function parameters */
+ assert_param(IS_CAN_RX_FIFO(RxFifo));
+
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
+ {
+ if (RxFifo == CAN_RX_FIFO0)
+ {
+ filllevel = hcan->Instance->RF0R & CAN_RF0R_FMP0;
+ }
+ else /* RxFifo == CAN_RX_FIFO1 */
+ {
+ filllevel = hcan->Instance->RF1R & CAN_RF1R_FMP1;
+ }
+ }
+
+ /* Return Rx FIFO fill level */
+ return filllevel;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Exported_Functions_Group4 Interrupts management
+ * @brief Interrupts management
+ *
+@verbatim
+ ==============================================================================
+ ##### Interrupts management #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) HAL_CAN_ActivateNotification : Enable interrupts
+ (+) HAL_CAN_DeactivateNotification : Disable interrupts
+ (+) HAL_CAN_IRQHandler : Handles CAN interrupt request
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enable interrupts.
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param ActiveITs indicates which interrupts will be enabled.
+ * This parameter can be any combination of @arg CAN_Interrupts.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs)
+{
+ HAL_CAN_StateTypeDef state = hcan->State;
+
+ /* Check function parameters */
+ assert_param(IS_CAN_IT(ActiveITs));
+
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
+ {
+ /* Enable the selected interrupts */
+ __HAL_CAN_ENABLE_IT(hcan, ActiveITs);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Disable interrupts.
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param InactiveITs indicates which interrupts will be disabled.
+ * This parameter can be any combination of @arg CAN_Interrupts.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs)
+{
+ HAL_CAN_StateTypeDef state = hcan->State;
+
+ /* Check function parameters */
+ assert_param(IS_CAN_IT(InactiveITs));
+
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
+ {
+ /* Disable the selected interrupts */
+ __HAL_CAN_DISABLE_IT(hcan, InactiveITs);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Handles CAN interrupt request
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
+{
+ uint32_t errorcode = HAL_CAN_ERROR_NONE;
+ uint32_t interrupts = READ_REG(hcan->Instance->IER);
+ uint32_t msrflags = READ_REG(hcan->Instance->MSR);
+ uint32_t tsrflags = READ_REG(hcan->Instance->TSR);
+ uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R);
+ uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R);
+ uint32_t esrflags = READ_REG(hcan->Instance->ESR);
+
+ /* Transmit Mailbox empty interrupt management *****************************/
+ if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U)
+ {
+ /* Transmit Mailbox 0 management *****************************************/
+ if ((tsrflags & CAN_TSR_RQCP0) != 0U)
+ {
+ /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0);
+
+ if ((tsrflags & CAN_TSR_TXOK0) != 0U)
+ {
+ /* Transmission Mailbox 0 complete callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_TxMailbox0CompleteCallback(hcan);
+ }
+ else
+ {
+ if ((tsrflags & CAN_TSR_ALST0) != 0U)
+ {
+ /* Update error code */
+ errorcode |= HAL_CAN_ERROR_TX_ALST0;
+ }
+ else if ((tsrflags & CAN_TSR_TERR0) != 0U)
+ {
+ /* Update error code */
+ errorcode |= HAL_CAN_ERROR_TX_TERR0;
+ }
+ else
+ {
+ /* Transmission Mailbox 0 abort callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_TxMailbox0AbortCallback(hcan);
+ }
+ }
+ }
+
+ /* Transmit Mailbox 1 management *****************************************/
+ if ((tsrflags & CAN_TSR_RQCP1) != 0U)
+ {
+ /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1);
+
+ if ((tsrflags & CAN_TSR_TXOK1) != 0U)
+ {
+ /* Transmission Mailbox 1 complete callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_TxMailbox1CompleteCallback(hcan);
+ }
+ else
+ {
+ if ((tsrflags & CAN_TSR_ALST1) != 0U)
+ {
+ /* Update error code */
+ errorcode |= HAL_CAN_ERROR_TX_ALST1;
+ }
+ else if ((tsrflags & CAN_TSR_TERR1) != 0U)
+ {
+ /* Update error code */
+ errorcode |= HAL_CAN_ERROR_TX_TERR1;
+ }
+ else
+ {
+ /* Transmission Mailbox 1 abort callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_TxMailbox1AbortCallback(hcan);
+ }
+ }
+ }
+
+ /* Transmit Mailbox 2 management *****************************************/
+ if ((tsrflags & CAN_TSR_RQCP2) != 0U)
+ {
+ /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2);
+
+ if ((tsrflags & CAN_TSR_TXOK2) != 0U)
+ {
+ /* Transmission Mailbox 2 complete callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_TxMailbox2CompleteCallback(hcan);
+ }
+ else
+ {
+ if ((tsrflags & CAN_TSR_ALST2) != 0U)
+ {
+ /* Update error code */
+ errorcode |= HAL_CAN_ERROR_TX_ALST2;
+ }
+ else if ((tsrflags & CAN_TSR_TERR2) != 0U)
+ {
+ /* Update error code */
+ errorcode |= HAL_CAN_ERROR_TX_TERR2;
+ }
+ else
+ {
+ /* Transmission Mailbox 2 abort callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_TxMailbox2AbortCallback(hcan);
+ }
+ }
+ }
+ }
+
+ /* Receive FIFO 0 overrun interrupt management *****************************/
+ if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U)
+ {
+ if ((rf0rflags & CAN_RF0R_FOVR0) != 0U)
+ {
+ /* Set CAN error code to Rx Fifo 0 overrun error */
+ errorcode |= HAL_CAN_ERROR_RX_FOV0;
+
+ /* Clear FIFO0 Overrun Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0);
+ }
+ }
+
+ /* Receive FIFO 0 full interrupt management ********************************/
+ if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U)
+ {
+ if ((rf0rflags & CAN_RF0R_FULL0) != 0U)
+ {
+ /* Clear FIFO 0 full Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0);
+
+ /* Receive FIFO 0 full Callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_RxFifo0FullCallback(hcan);
+ }
+ }
+
+ /* Receive FIFO 0 message pending interrupt management *********************/
+ if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U)
+ {
+ /* Check if message is still pending */
+ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U)
+ {
+ /* Receive FIFO 0 mesage pending Callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_RxFifo0MsgPendingCallback(hcan);
+ }
+ }
+
+ /* Receive FIFO 1 overrun interrupt management *****************************/
+ if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U)
+ {
+ if ((rf1rflags & CAN_RF1R_FOVR1) != 0U)
+ {
+ /* Set CAN error code to Rx Fifo 1 overrun error */
+ errorcode |= HAL_CAN_ERROR_RX_FOV1;
+
+ /* Clear FIFO1 Overrun Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1);
+ }
+ }
+
+ /* Receive FIFO 1 full interrupt management ********************************/
+ if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U)
+ {
+ if ((rf1rflags & CAN_RF1R_FULL1) != 0U)
+ {
+ /* Clear FIFO 1 full Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1);
+
+ /* Receive FIFO 1 full Callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_RxFifo1FullCallback(hcan);
+ }
+ }
+
+ /* Receive FIFO 1 message pending interrupt management *********************/
+ if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U)
+ {
+ /* Check if message is still pending */
+ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U)
+ {
+ /* Receive FIFO 1 mesage pending Callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_RxFifo1MsgPendingCallback(hcan);
+ }
+ }
+
+ /* Sleep interrupt management *********************************************/
+ if ((interrupts & CAN_IT_SLEEP_ACK) != 0U)
+ {
+ if ((msrflags & CAN_MSR_SLAKI) != 0U)
+ {
+ /* Clear Sleep interrupt Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI);
+
+ /* Sleep Callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_SleepCallback(hcan);
+ }
+ }
+
+ /* WakeUp interrupt management *********************************************/
+ if ((interrupts & CAN_IT_WAKEUP) != 0U)
+ {
+ if ((msrflags & CAN_MSR_WKUI) != 0U)
+ {
+ /* Clear WakeUp Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU);
+
+ /* WakeUp Callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_WakeUpFromRxMsgCallback(hcan);
+ }
+ }
+
+ /* Error interrupts management *********************************************/
+ if ((interrupts & CAN_IT_ERROR) != 0U)
+ {
+ if ((msrflags & CAN_MSR_ERRI) != 0U)
+ {
+ /* Check Error Warning Flag */
+ if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) &&
+ ((esrflags & CAN_ESR_EWGF) != 0U))
+ {
+ /* Set CAN error code to Error Warning */
+ errorcode |= HAL_CAN_ERROR_EWG;
+
+ /* No need for clear of Error Warning Flag as read-only */
+ }
+
+ /* Check Error Passive Flag */
+ if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) &&
+ ((esrflags & CAN_ESR_EPVF) != 0U))
+ {
+ /* Set CAN error code to Error Passive */
+ errorcode |= HAL_CAN_ERROR_EPV;
+
+ /* No need for clear of Error Passive Flag as read-only */
+ }
+
+ /* Check Bus-off Flag */
+ if (((interrupts & CAN_IT_BUSOFF) != 0U) &&
+ ((esrflags & CAN_ESR_BOFF) != 0U))
+ {
+ /* Set CAN error code to Bus-Off */
+ errorcode |= HAL_CAN_ERROR_BOF;
+
+ /* No need for clear of Error Bus-Off as read-only */
+ }
+
+ /* Check Last Error Code Flag */
+ if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) &&
+ ((esrflags & CAN_ESR_LEC) != 0U))
+ {
+ switch (esrflags & CAN_ESR_LEC)
+ {
+ case (CAN_ESR_LEC_0):
+ /* Set CAN error code to Stuff error */
+ errorcode |= HAL_CAN_ERROR_STF;
+ break;
+ case (CAN_ESR_LEC_1):
+ /* Set CAN error code to Form error */
+ errorcode |= HAL_CAN_ERROR_FOR;
+ break;
+ case (CAN_ESR_LEC_1 | CAN_ESR_LEC_0):
+ /* Set CAN error code to Acknowledgement error */
+ errorcode |= HAL_CAN_ERROR_ACK;
+ break;
+ case (CAN_ESR_LEC_2):
+ /* Set CAN error code to Bit recessive error */
+ errorcode |= HAL_CAN_ERROR_BR;
+ break;
+ case (CAN_ESR_LEC_2 | CAN_ESR_LEC_0):
+ /* Set CAN error code to Bit Dominant error */
+ errorcode |= HAL_CAN_ERROR_BD;
+ break;
+ case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
+ /* Set CAN error code to CRC error */
+ errorcode |= HAL_CAN_ERROR_CRC;
+ break;
+ default:
+ break;
+ }
+
+ /* Clear Last error code Flag */
+ CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC);
+ }
+ }
+
+ /* Clear ERRI Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI);
+ }
+
+ /* Call the Error call Back in case of Errors */
+ if (errorcode != HAL_CAN_ERROR_NONE)
+ {
+ /* Update error code in handle */
+ hcan->ErrorCode |= errorcode;
+
+ /* Call Error callback function */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_ErrorCallback(hcan);
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Exported_Functions_Group5 Callback functions
+ * @brief CAN Callback functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Callback functions #####
+ ==============================================================================
+ [..]
+ This subsection provides the following callback functions:
+ (+) HAL_CAN_TxMailbox0CompleteCallback
+ (+) HAL_CAN_TxMailbox1CompleteCallback
+ (+) HAL_CAN_TxMailbox2CompleteCallback
+ (+) HAL_CAN_TxMailbox0AbortCallback
+ (+) HAL_CAN_TxMailbox1AbortCallback
+ (+) HAL_CAN_TxMailbox2AbortCallback
+ (+) HAL_CAN_RxFifo0MsgPendingCallback
+ (+) HAL_CAN_RxFifo0FullCallback
+ (+) HAL_CAN_RxFifo1MsgPendingCallback
+ (+) HAL_CAN_RxFifo1FullCallback
+ (+) HAL_CAN_SleepCallback
+ (+) HAL_CAN_WakeUpFromRxMsgCallback
+ (+) HAL_CAN_ErrorCallback
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Transmission Mailbox 0 complete callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the
+ user file
+ */
+}
+
+/**
+ * @brief Transmission Mailbox 1 complete callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the
+ user file
+ */
+}
+
+/**
+ * @brief Transmission Mailbox 2 complete callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the
+ user file
+ */
+}
+
+/**
+ * @brief Transmission Mailbox 0 Cancellation callback.
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_TxMailbox0AbortCallback could be implemented in the
+ user file
+ */
+}
+
+/**
+ * @brief Transmission Mailbox 1 Cancellation callback.
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_TxMailbox1AbortCallback could be implemented in the
+ user file
+ */
+}
+
+/**
+ * @brief Transmission Mailbox 2 Cancellation callback.
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_TxMailbox2AbortCallback could be implemented in the
+ user file
+ */
+}
+
+/**
+ * @brief Rx FIFO 0 message pending callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_RxFifo0MsgPendingCallback could be implemented in the
+ user file
+ */
+}
+
+/**
+ * @brief Rx FIFO 0 full callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_RxFifo0FullCallback could be implemented in the user
+ file
+ */
+}
+
+/**
+ * @brief Rx FIFO 1 message pending callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_RxFifo1MsgPendingCallback could be implemented in the
+ user file
+ */
+}
+
+/**
+ * @brief Rx FIFO 1 full callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_RxFifo1FullCallback could be implemented in the user
+ file
+ */
+}
+
+/**
+ * @brief Sleep callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_SleepCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief WakeUp from Rx message callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the
+ user file
+ */
+}
+
+/**
+ * @brief Error CAN callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Exported_Functions_Group6 Peripheral State and Error functions
+ * @brief CAN Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State and Error functions #####
+ ==============================================================================
+ [..]
+ This subsection provides functions allowing to :
+ (+) HAL_CAN_GetState() : Return the CAN state.
+ (+) HAL_CAN_GetError() : Return the CAN error codes if any.
+ (+) HAL_CAN_ResetError(): Reset the CAN error codes if any.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the CAN state.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL state
+ */
+HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan)
+{
+ HAL_CAN_StateTypeDef state = hcan->State;
+
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
+ {
+ /* Check sleep mode acknowledge flag */
+ if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
+ {
+ /* Sleep mode is active */
+ state = HAL_CAN_STATE_SLEEP_ACTIVE;
+ }
+ /* Check sleep mode request flag */
+ else if ((hcan->Instance->MCR & CAN_MCR_SLEEP) != 0U)
+ {
+ /* Sleep mode request is pending */
+ state = HAL_CAN_STATE_SLEEP_PENDING;
+ }
+ else
+ {
+ /* Neither sleep mode request nor sleep mode acknowledge */
+ }
+ }
+
+ /* Return CAN state */
+ return state;
+}
+
+/**
+ * @brief Return the CAN error code.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval CAN Error Code
+ */
+uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)
+{
+ /* Return CAN error code */
+ return hcan->ErrorCode;
+}
+
+/**
+ * @brief Reset the CAN error code.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ HAL_CAN_StateTypeDef state = hcan->State;
+
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
+ {
+ /* Reset CAN error code */
+ hcan->ErrorCode = 0U;
+ }
+ else
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+ status = HAL_ERROR;
+ }
+
+ /* Return the status */
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+#endif /* CAN */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_cec.c b/Src/stm32f3xx_hal_cec.c
new file mode 100644
index 0000000..ec37473
--- /dev/null
+++ b/Src/stm32f3xx_hal_cec.c
@@ -0,0 +1,671 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_cec.c
+ * @author MCD Application Team
+ * @brief CEC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the High Definition Multimedia Interface
+ * Consumer Electronics Control Peripheral (CEC).
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ *
+ *
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ The CEC HAL driver can be used as follow:
+
+ (#) Declare a CEC_HandleTypeDef handle structure.
+ (#) Initialize the CEC low level resources by implementing the HAL_CEC_MspInit ()API:
+ (##) Enable the CEC interface clock.
+ (##) CEC pins configuration:
+ (+) Enable the clock for the CEC GPIOs.
+ (+) Configure these CEC pins as alternate function pull-up.
+ (##) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT()
+ and HAL_CEC_Receive_IT() APIs):
+ (+) Configure the CEC interrupt priority.
+ (+) Enable the NVIC CEC IRQ handle.
+ (@) The specific CEC interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit
+ and receive process.
+
+ (#) Program the Signal Free Time (SFT) and SFT option, Tolerance, reception stop in
+ in case of Bit Rising Error, Error-Bit generation conditions, device logical
+ address and Listen mode in the hcec Init structure.
+
+ (#) Initialize the CEC registers by calling the HAL_CEC_Init() API.
+
+ (@) This API (HAL_CEC_Init()) configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ by calling the customed HAL_CEC_MspInit() API.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/** @defgroup CEC CEC
+ * @brief HAL CEC module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup CEC_Private_Constants CEC Private Constants
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup CEC_Private_Functions CEC Private Functions
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup CEC_Exported_Functions CEC Exported Functions
+ * @{
+ */
+
+/** @defgroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the CEC
+ (+) The following parameters need to be configured:
+ (++) SignalFreeTime
+ (++) Tolerance
+ (++) BRERxStop (RX stopped or not upon Bit Rising Error)
+ (++) BREErrorBitGen (Error-Bit generation in case of Bit Rising Error)
+ (++) LBPEErrorBitGen (Error-Bit generation in case of Long Bit Period Error)
+ (++) BroadcastMsgNoErrorBitGen (Error-bit generation in case of broadcast message error)
+ (++) SignalFreeTimeOption (SFT Timer start definition)
+ (++) OwnAddress (CEC device address)
+ (++) ListenMode
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the CEC mode according to the specified
+ * parameters in the CEC_InitTypeDef and creates the associated handle .
+ * @param hcec CEC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)
+{
+ /* Check the CEC handle allocation */
+ if((hcec == NULL) ||(hcec->Init.RxBuffer == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
+ assert_param(IS_CEC_SIGNALFREETIME(hcec->Init.SignalFreeTime));
+ assert_param(IS_CEC_TOLERANCE(hcec->Init.Tolerance));
+ assert_param(IS_CEC_BRERXSTOP(hcec->Init.BRERxStop));
+ assert_param(IS_CEC_BREERRORBITGEN(hcec->Init.BREErrorBitGen));
+ assert_param(IS_CEC_LBPEERRORBITGEN(hcec->Init.LBPEErrorBitGen));
+ assert_param(IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(hcec->Init.BroadcastMsgNoErrorBitGen));
+ assert_param(IS_CEC_SFTOP(hcec->Init.SignalFreeTimeOption));
+ assert_param(IS_CEC_LISTENING_MODE(hcec->Init.ListenMode));
+ assert_param(IS_CEC_OWN_ADDRESS(hcec->Init.OwnAddress));
+
+ if(hcec->gState == HAL_CEC_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hcec->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_CEC_MspInit(hcec);
+ }
+ hcec->gState = HAL_CEC_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_CEC_DISABLE(hcec);
+
+ /* Write to CEC Control Register */
+ hcec->Instance->CFGR = hcec->Init.SignalFreeTime | hcec->Init.Tolerance | hcec->Init.BRERxStop|\
+ hcec->Init.BREErrorBitGen | hcec->Init.LBPEErrorBitGen | hcec->Init.BroadcastMsgNoErrorBitGen |\
+ hcec->Init.SignalFreeTimeOption |((uint32_t)(hcec->Init.OwnAddress)<<16U) |\
+ hcec->Init.ListenMode;
+
+ /* Enable the following CEC Transmission/Reception interrupts as
+ * well as the following CEC Transmission/Reception Errors interrupts
+ * Rx Byte Received IT
+ * End of Reception IT
+ * Rx overrun
+ * Rx bit rising error
+ * Rx short bit period error
+ * Rx long bit period error
+ * Rx missing acknowledge
+ * Tx Byte Request IT
+ * End of Transmission IT
+ * Tx Missing Acknowledge IT
+ * Tx-Error IT
+ * Tx-Buffer Underrun IT
+ * Tx arbitration lost */
+ __HAL_CEC_ENABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND|CEC_IER_RX_ALL_ERR|CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR);
+
+ /* Enable the CEC Peripheral */
+ __HAL_CEC_ENABLE(hcec);
+
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+ hcec->gState = HAL_CEC_STATE_READY;
+ hcec->RxState = HAL_CEC_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the CEC peripheral
+ * @param hcec CEC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
+{
+ /* Check the CEC handle allocation */
+ if(hcec == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
+
+ hcec->gState = HAL_CEC_STATE_BUSY;
+
+ /* DeInit the low level hardware */
+ HAL_CEC_MspDeInit(hcec);
+ /* Disable the Peripheral */
+ __HAL_CEC_DISABLE(hcec);
+
+ /* Clear Flags */
+ __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXEND|CEC_FLAG_TXBR|CEC_FLAG_RXBR|CEC_FLAG_RXEND|CEC_ISR_ALL_ERROR);
+
+ /* Disable the following CEC Transmission/Reception interrupts as
+ * well as the following CEC Transmission/Reception Errors interrupts
+ * Rx Byte Received IT
+ * End of Reception IT
+ * Rx overrun
+ * Rx bit rising error
+ * Rx short bit period error
+ * Rx long bit period error
+ * Rx missing acknowledge
+ * Tx Byte Request IT
+ * End of Transmission IT
+ * Tx Missing Acknowledge IT
+ * Tx-Error IT
+ * Tx-Buffer Underrun IT
+ * Tx arbitration lost */
+ __HAL_CEC_DISABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND|CEC_IER_RX_ALL_ERR|CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR);
+
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+ hcec->gState = HAL_CEC_STATE_RESET;
+ hcec->RxState = HAL_CEC_STATE_RESET;
+
+ /* Process Unlock */
+ __HAL_UNLOCK(hcec);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the Own Address of the CEC device
+ * @param hcec CEC handle
+ * @param CEC_OwnAddress The CEC own address.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress)
+{
+ /* Check the parameters */
+ assert_param(IS_CEC_OWN_ADDRESS(CEC_OwnAddress));
+
+ if ((hcec->gState == HAL_CEC_STATE_READY) && (hcec->RxState == HAL_CEC_STATE_READY))
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcec);
+
+ hcec->gState = HAL_CEC_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_CEC_DISABLE(hcec);
+
+ if(CEC_OwnAddress != CEC_OWN_ADDRESS_NONE)
+ {
+ hcec->Instance->CFGR |= ((uint32_t)CEC_OwnAddress<<16U);
+ }
+ else
+ {
+ hcec->Instance->CFGR &= ~(CEC_CFGR_OAR);
+ }
+
+ hcec->gState = HAL_CEC_STATE_READY;
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcec);
+
+ /* Enable the Peripheral */
+ __HAL_CEC_ENABLE(hcec);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief CEC MSP Init
+ * @param hcec CEC handle
+ * @retval None
+ */
+ __weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcec);
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CEC_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief CEC MSP DeInit
+ * @param hcec CEC handle
+ * @retval None
+ */
+ __weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcec);
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CEC_MspDeInit can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Exported_Functions_Group2 Input and Output operation functions
+ * @brief CEC Transmit/Receive functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ This subsection provides a set of functions allowing to manage the CEC data transfers.
+
+ (#) The CEC handle must contain the initiator (TX side) and the destination (RX side)
+ logical addresses (4-bit long addresses, 0x0F for broadcast messages destination)
+
+ (#) The communication is performed using Interrupts.
+ These API's return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated CEC IRQ when using Interrupt mode.
+ The HAL_CEC_TxCpltCallback(), HAL_CEC_RxCpltCallback() user callbacks
+ will be executed respectivelly at the end of the transmit or Receive process
+ The HAL_CEC_ErrorCallback()user callback will be executed when a communication
+ error is detected
+
+ (#) API's with Interrupt are :
+ (+) HAL_CEC_Transmit_IT()
+ (+) HAL_CEC_IRQHandler()
+
+ (#) A set of User Callbacks are provided:
+ (+) HAL_CEC_TxCpltCallback()
+ (+) HAL_CEC_RxCpltCallback()
+ (+) HAL_CEC_ErrorCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Send data in interrupt mode
+ * @param hcec CEC handle
+ * @param InitiatorAddress Initiator address
+ * @param DestinationAddress destination logical address
+ * @param pData pointer to input byte data buffer
+ * @param Size amount of data to be sent in bytes (without counting the header).
+ * 0 means only the header is sent (ping operation).
+ * Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size)
+{
+ /* if the IP isn't already busy and if there is no previous transmission
+ already pending due to arbitration lost */
+ if (hcec->gState == HAL_CEC_STATE_READY)
+ {
+ if((pData == NULL ) && (Size > 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ assert_param(IS_CEC_ADDRESS(DestinationAddress));
+ assert_param(IS_CEC_ADDRESS(InitiatorAddress));
+ assert_param(IS_CEC_MSGSIZE(Size));
+
+ /* Process Locked */
+ __HAL_LOCK(hcec);
+ hcec->pTxBuffPtr = pData;
+ hcec->gState = HAL_CEC_STATE_BUSY_TX;
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+
+ /* initialize the number of bytes to send,
+ * 0 means only one header is sent (ping operation) */
+ hcec->TxXferCount = Size;
+
+ /* in case of no payload (Size = 0U), sender is only pinging the system;
+ Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */
+ if (Size == 0U)
+ {
+ __HAL_CEC_LAST_BYTE_TX_SET(hcec);
+ }
+
+ /* send header block */
+ hcec->Instance->TXDR = ((uint8_t)(InitiatorAddress << CEC_INITIATOR_LSB_POS) |(uint8_t) DestinationAddress);
+ /* Set TX Start of Message (TXSOM) bit */
+ __HAL_CEC_FIRST_BYTE_TX_SET(hcec);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcec);
+
+ return HAL_OK;
+
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Get size of the received frame.
+ * @param hcec CEC handle
+ * @retval Frame size
+ */
+uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec)
+{
+ return hcec->RxXferSize;
+}
+
+/**
+ * @brief Change Rx Buffer.
+ * @param hcec CEC handle
+ * @param Rxbuffer Rx Buffer
+ * @note This function can be called only inside the HAL_CEC_RxCpltCallback()
+ * @retval Frame size
+ */
+void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer)
+{
+ hcec->Init.RxBuffer = Rxbuffer;
+}
+
+/**
+ * @brief This function handles CEC interrupt requests.
+ * @param hcec CEC handle
+ * @retval None
+ */
+void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
+{
+
+ /* save interrupts register for further error or interrupts handling purposes */
+ uint32_t reg = 0U;
+ reg = hcec->Instance->ISR;
+
+
+ /* ----------------------------Arbitration Lost Management----------------------------------*/
+ /* CEC TX arbitration error interrupt occurred --------------------------------------*/
+ if((reg & CEC_FLAG_ARBLST) != RESET)
+ {
+ hcec->ErrorCode = HAL_CEC_ERROR_ARBLST;
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_ARBLST);
+ }
+
+ /* ----------------------------Rx Management----------------------------------*/
+ /* CEC RX byte received interrupt ---------------------------------------------------*/
+ if((reg & CEC_FLAG_RXBR) != RESET)
+ {
+ /* reception is starting */
+ hcec->RxState = HAL_CEC_STATE_BUSY_RX;
+ hcec->RxXferSize++;
+ /* read received byte */
+ *hcec->Init.RxBuffer++ = hcec->Instance->RXDR;
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXBR);
+ }
+
+ /* CEC RX end received interrupt ---------------------------------------------------*/
+ if((reg & CEC_FLAG_RXEND) != RESET)
+ {
+ /* clear IT */
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXEND);
+
+ /* Rx process is completed, restore hcec->RxState to Ready */
+ hcec->RxState = HAL_CEC_STATE_READY;
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+ hcec->Init.RxBuffer -= hcec->RxXferSize;
+ HAL_CEC_RxCpltCallback(hcec, hcec->RxXferSize);
+ hcec->RxXferSize = 0U;
+ }
+
+ /* ----------------------------Tx Management----------------------------------*/
+ /* CEC TX byte request interrupt ------------------------------------------------*/
+ if((reg & CEC_FLAG_TXBR) != RESET)
+ {
+ if (hcec->TxXferCount == 0U)
+ {
+ /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */
+ __HAL_CEC_LAST_BYTE_TX_SET(hcec);
+ hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
+ }
+ else
+ {
+ hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
+ hcec->TxXferCount--;
+ }
+ /* clear Tx-Byte request flag */
+ __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR);
+ }
+
+ /* CEC TX end interrupt ------------------------------------------------*/
+ if((reg & CEC_FLAG_TXEND) != RESET)
+ {
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXEND);
+
+ /* Tx process is ended, restore hcec->gState to Ready */
+ hcec->gState = HAL_CEC_STATE_READY;
+ /* Call the Process Unlocked before calling the Tx call back API to give the possibility to
+ start again the Transmission under the Tx call back API */
+ __HAL_UNLOCK(hcec);
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+ HAL_CEC_TxCpltCallback(hcec);
+ }
+
+ /* ----------------------------Rx/Tx Error Management----------------------------------*/
+ if ((reg & (CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)) != 0U)
+ {
+ hcec->ErrorCode = reg;
+ __HAL_CEC_CLEAR_FLAG(hcec, HAL_CEC_ERROR_RXOVR|HAL_CEC_ERROR_BRE|CEC_FLAG_LBPE|CEC_FLAG_SBPE|HAL_CEC_ERROR_RXACKE|HAL_CEC_ERROR_TXUDR|HAL_CEC_ERROR_TXERR|HAL_CEC_ERROR_TXACKE);
+
+
+ if((reg & (CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE)) != RESET)
+ {
+ hcec->Init.RxBuffer-=hcec->RxXferSize;
+ hcec->RxXferSize = 0U;
+ hcec->RxState = HAL_CEC_STATE_READY;
+ }
+ else if (((reg & (CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)) != RESET) && ((reg & CEC_ISR_ARBLST) == RESET))
+ {
+ /* Set the CEC state ready to be able to start again the process */
+ hcec->gState = HAL_CEC_STATE_READY;
+ }
+
+ /* Error Call Back */
+ HAL_CEC_ErrorCallback(hcec);
+ }
+
+}
+
+/**
+ * @brief Tx Transfer completed callback
+ * @param hcec CEC handle
+ * @retval None
+ */
+ __weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcec);
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CEC_TxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callback
+ * @param hcec CEC handle
+ * @param RxFrameSize Size of frame
+ * @retval None
+ */
+__weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcec);
+ UNUSED(RxFrameSize);
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CEC_RxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief CEC error callbacks
+ * @param hcec CEC handle
+ * @retval None
+ */
+ __weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcec);
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CEC_ErrorCallback can be implemented in the user file
+ */
+}
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Exported_Functions_Group3 Peripheral Control function
+ * @brief CEC control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control function #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the CEC.
+ (+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral.
+ (+) HAL_CEC_GetError() API can be helpful to check in run-time the error of the CEC peripheral.
+@endverbatim
+ * @{
+ */
+/**
+ * @brief return the CEC state
+ * @param hcec pointer to a CEC_HandleTypeDef structure that contains
+ * the configuration information for the specified CEC module.
+ * @retval HAL state
+ */
+HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec)
+{
+ uint32_t temp1 = 0x00U, temp2 = 0x00U;
+ temp1 = hcec->gState;
+ temp2 = hcec->RxState;
+
+ return (HAL_CEC_StateTypeDef)(temp1 | temp2);
+}
+
+/**
+ * @brief Return the CEC error code
+ * @param hcec pointer to a CEC_HandleTypeDef structure that contains
+ * the configuration information for the specified CEC.
+ * @retval CEC Error Code
+ */
+uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec)
+{
+ return hcec->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#endif /* defined(STM32F373xC) || defined(STM32F378xx) */
+
+#endif /* HAL_CEC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_comp.c b/Src/stm32f3xx_hal_comp.c
new file mode 100644
index 0000000..aee44f6
--- /dev/null
+++ b/Src/stm32f3xx_hal_comp.c
@@ -0,0 +1,832 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_comp.c
+ * @author MCD Application Team
+ * @brief COMP HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the COMP peripheral:
+ * + Initialization and de-initialization functions
+ * + Start/Stop operation functions in polling mode.
+ * + Start/Stop operation functions in interrupt mode.
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ @verbatim
+================================================================================
+ ##### COMP Peripheral features #####
+================================================================================
+
+ [..]
+ The STM32F3xx device family integrates up to 7 analog comparators COMP1, COMP2...COMP7:
+ (#) The non inverting input and inverting input can be set to GPIO pins.
+ For STM32F3xx devices please refer to the COMP peripheral section in corresponding
+ Reference Manual.
+
+ (#) The COMP output is available using HAL_COMP_GetOutputLevel()
+ and can be set on GPIO pins.
+ For STM32F3xx devices please refer to the COMP peripheral section in corresponding
+ Reference Manual.
+
+ (#) The COMP output can be redirected to embedded timers (TIM1, TIM2, TIM3...).
+ For STM32F3xx devices please refer to the COMP peripheral section in corresponding
+ Reference Manual.
+
+ (#) Each couple of comparators COMP1 and COMP2, COMP3 and COMP4, COMP5 and COMP6 can be combined in window
+ mode and respectively COMP1, COMP3 and COMP5 non inverting input is used as common non-inverting input.
+
+ (#) The seven comparators have interrupt capability with wake-up
+ from Sleep and Stop modes (through the EXTI controller):
+ (++) COMP1 is internally connected to EXTI Line 21
+ (++) COMP2 is internally connected to EXTI Line 22
+ (++) COMP3 is internally connected to EXTI Line 29
+ (++) COMP4 is internally connected to EXTI Line 30
+ (++) COMP5 is internally connected to EXTI Line 31
+ (++) COMP6 is internally connected to EXTI Line 32
+ (++) COMP7 is internally connected to EXTI Line 33.
+
+ From the corresponding IRQ handler, the right interrupt source can be retrieved with the
+ adequate macro __HAL_COMP_COMPx_EXTI_GET_FLAG().
+
+
+ ##### How to use this driver #####
+================================================================================
+ [..]
+ This driver provides functions to configure and program the Comparators of all STM32F3xx devices.
+
+ To use the comparator, perform the following steps:
+
+ (#) Fill in the HAL_COMP_MspInit() to
+ (++) Configure the comparator input in analog mode using HAL_GPIO_Init()
+ (++) Configure the comparator output in alternate function mode using HAL_GPIO_Init() to map the comparator
+ output to the GPIO pin
+ (++) If required enable the COMP interrupt (EXTI line Interrupt): by configuring and enabling EXTI line in Interrupt mode and
+ selecting the desired sensitivity level using HAL_GPIO_Init() function. After that enable the comparator
+ interrupt vector using HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ() functions.
+
+ (#) Configure the comparator using HAL_COMP_Init() function:
+ (++) Select the inverting input (input minus)
+ (++) Select the non-inverting input (input plus)
+ (++) Select the output polarity
+ (++) Select the output redirection
+ (++) Select the hysteresis level
+ (++) Select the power mode
+ (++) Select the event/interrupt mode
+
+ -@@- HAL_COMP_Init() calls internally __HAL_RCC_SYSCFG_CLK_ENABLE() in order
+ to enable the comparator(s).
+
+ (#) On-the-fly reconfiguration of comparator(s) may be done by calling again HAL_COMP_Init(
+ function with new input parameter values; HAL_COMP_MspInit() function shall be adapted
+ to support multi configurations.
+
+ (#) Enable the comparator using HAL_COMP_Start() or HAL_COMP_Start_IT() functions.
+
+ (#) Use HAL_COMP_TriggerCallback() and/or HAL_COMP_GetOutputLevel() functions
+ to manage comparator outputs (events and output level).
+
+ (#) Disable the comparator using HAL_COMP_Stop() or HAL_COMP_Stop_IT()
+ function.
+
+ (#) De-initialize the comparator using HAL_COMP_DeInit() function.
+
+ (#) For safety purposes comparator(s) can be locked using HAL_COMP_Lock() function.
+ Only a MCU reset can reset that protection.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*
+ Additional Tables:
+
+ Table 1. COMP Inputs for the STM32F303xB/STM32F303xC/STM32F303xE devices
+ +------------------------------------------------------------------------------------------+
+ | | | COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 |
+ |-----------------|----------------|---------------|---------------------------------------|
+ | | 1U/4 VREFINT | OK | OK | OK | OK | OK | OK | OK |
+ | | 1U/2 VREFINT | OK | OK | OK | OK | OK | OK | OK |
+ | | 3U/4 VREFINT | OK | OK | OK | OK | OK | OK | OK |
+ | Inverting Input | VREFINT | OK | OK | OK | OK | OK | OK | OK |
+ | | DAC1 OUT (PA4) | OK | OK | OK | OK | OK | OK | OK |
+ | | DAC2 OUT (PA5) | OK | OK | OK | OK | OK | OK | OK |
+ | | IO1 | PA0 | PA2 | PD15U | PE8 | PD13U | PD10U | PC0 |
+ | | IO2 | --- | --- | PB12U | PB2 | PB10U | PB15U | --- |
+ |-----------------|----------------|-------|-------|-------|-------|-------|-------|-------|
+ | Non Inverting | IO1 | PA1 | PA7 | PB14U | PB0 | PD12U | PD11U | PA0 |
+ | Input | IO2 | --- | PA3 | PD14U | PE7 | PB13U | PB11U | PC1 |
+ +------------------------------------------------------------------------------------------+
+
+ Table 2. COMP Outputs for the STM32F303xB/STM32F303xC/STM32F303xE devices
+ +-------------------------------------------------------+
+ | COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 |
+ |-------|-------|-------|-------|-------|-------|-------|
+ | PA0 | PA2 | PB1 | PC8 | PC7 | PA10U | PC2 |
+ | PF4 | PA7 | --- | PA8 | PA9 | PC6 | --- |
+ | PA6 | PA12U | --- | --- | --- | --- | --- |
+ | PA11U | PB9 | --- | --- | --- | --- | --- |
+ | PB8 | --- | --- | --- | --- | --- | --- |
+ +-------------------------------------------------------+
+
+ Table 3. COMP Outputs redirection to embedded timers for the STM32F303xB/STM32F303xC devices
+ +----------------------------------------------------------------------------------------------------------------------+
+ | COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 |
+ |----------------|----------------|----------------|----------------|----------------|----------------|----------------|
+ | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN |
+ | | | | | | | |
+ | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 |
+ | | | | | | | |
+ | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN |
+ | | | | | | | |
+ | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 |
+ | | | | | | | |
+ | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 |
+ | + | + | + | + | + | + | + |
+ | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 |
+ | | | | | | | |
+ | TIM1 OCREFCLR | TIM1 OCREFCLR | TIM1 OCREFCLR | TIM8 OCREFCLR | TIM8 OCREFCLR | TIM8 OCREFCLR | TIM1 OCREFCLR |
+ | | | | | | | |
+ | TIM1 IC1 | TIM1 IC1 | TIM2 OCREFCLR | TIM3 IC3 | TIM2 IC1 | TIM2 IC2 | TIM8 OCREFCLR |
+ | | | | | | | |
+ | TIM2 IC4 | TIM2 IC4 | TIM3 IC2 | TIM3 OCREFCLR | TIM3 OCREFCLR | TIM2 OCREFCLR | TIM2 IC3 |
+ | | | | | | | |
+ | TIM2 OCREFCLR | TIM2 OCREFCLR | TIM4 IC1 | TIM4 IC2 | TIM4 IC3 | TIM16 OCREFCLR| TIM1 IC2 |
+ | | | | | | | |
+ | TIM3 IC1 | TIM3 IC1 | TIM15 IC1 | TIM15 OCREFCLR| TIM16 BKIN | TIM16 IC1 | TIM17 OCREFCLR|
+ | | | | | | | |
+ | TIM3 OCREFCLR | TIM3 OCREFCLR | TIM15 BKIN | TIM15 IC2 | TIM17 IC1 | TIM4 IC4 | TIM17 BKIN |
+ +----------------------------------------------------------------------------------------------------------------------+
+
+ Table 4. COMP Outputs redirection to embedded timers for the STM32F303xE devices
+ +----------------------------------------------------------------------------------------------------------------------+
+ | COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 |
+ |----------------|----------------|----------------|----------------|----------------|----------------|----------------|
+ | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN (1U) | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN (1U) |
+ | | | | | | | |
+ | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 |
+ | | | | | | | |
+ | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN (1U) | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN (1U) |
+ | | | | | | | |
+ | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 |
+ | | | | | | | |
+ | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 |
+ | + | + | + | + | + | + | + |
+ | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 |
+ | | | | | | | |
+ | TIM1 OCREFCLR | TIM1 OCREFCLR | TIM1 OCREFCLR | TIM8 OCREFCLR | TIM8 OCREFCLR | TIM8 OCREFCLR | TIM1 OCREFCLR |
+ | | | | | | | |
+ | TIM1 IC1 | TIM1 IC1 | TIM2 OCREFCLR | TIM3 IC3 | TIM2 IC1 | TIM2 IC2 | TIM8 OCREFCLR |
+ | | | | | | | |
+ | TIM2 IC4 | TIM2 IC4 | TIM3 IC2 | TIM3 OCREFCLR | TIM3 OCREFCLR | TIM2 OCREFCLR | TIM2 IC3 |
+ | | | | | | | |
+ | TIM2 OCREFCLR | TIM2 OCREFCLR | TIM4 IC1 | TIM4 IC2 | TIM4 IC3 | TIM16 OCREFCLR| TIM1 IC2 |
+ | | | | | | | |
+ | TIM3 IC1 | TIM3 IC1 | TIM15 IC1 | TIM15 OCREFCLR| TIM16 BKIN | TIM16 IC1 | TIM17 OCREFCLR|
+ | | | | | | | |
+ | TIM3 OCREFCLR | TIM3 OCREFCLR | TIM15 BKIN | TIM15 IC2 | TIM17 IC1 | TIM4 IC4 | TIM17 BKIN |
+ | | | | | | | |
+ | TIM20 BKIN | TIM20 BKIN | TIM20 BKIN | TIM20 BKIN (1U)| TIM20 BKIN | TIM20 BKIN | TIM20 BKIN (1U)|
+ | | | | | | | |
+ | TIM20 BKIN2 | TIM20 BKIN2 | TIM20 BKIN2 | TIM20 BKIN2 | TIM20 BKIN2 | TIM20 BKIN2 | TIM20 BKIN2 |
+ | | | | | | | |
+ | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 |
+ | + | + | + | + | + | + | + |
+ | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 |
+ | + | + | + | + | + | + | + |
+ | TIM20 BKIN2 | TIM20 BKIN2 | TIM20 BKIN2 | TIM20 BKIN2 | TIM20 BKIN2 | TIM20 BKIN2 | TIM20 BKIN2 |
+ | | | | | | | |
+ +----------------------------------------------------------------------------------------------------------------------+
+ (1U): This connection consists of connecting both GPIO and COMP output to TIM1/8U/20 BRK input through an OR gate, instead
+ of connecting the GPIO to the TIM1/8U/20 BRK input and the COMP output to the TIM1/8U/20 BRK_ACTH input. The aim is to
+ add a digital filter (3 bits) on the COMP output.
+
+ Table 5. COMP Outputs blanking sources for the STM32F303xB/STM32F303xC/STM32F303xE devices
+ +----------------------------------------------------------------------------------------------------------------------+
+ | COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 |
+ |----------------|----------------|----------------|----------------|----------------|----------------|----------------|
+ | TIM1 OC5 | TIM1 OC5 | TIM1 OC5 | TIM3 OC4 | -------- | TIM8 OC5 | TIM1 OC5 |
+ | | | | | | | |
+ | TIM2 OC3 | TIM2 OC3 | -------- | TIM8 OC5 | TIM3 OC3 | TIM2 OC4 | TIM8 OC5 |
+ | | | | | | | |
+ | TIM3 OC3 | TIM3 OC3 | TIM2 OC4 | TIM15 OC1 | TIM8 OC5 | TIM15 OC2 | TIM15 OC2 |
+ | | | | | | | |
+ +----------------------------------------------------------------------------------------------------------------------+
+
+*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup COMP COMP
+ * @brief COMP HAL module driver
+ * @{
+ */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup COMP_Private_Constants COMP Private Constants
+ * @{
+ */
+#define COMP_LOCK_DISABLE (0x00000000U)
+#define COMP_LOCK_ENABLE COMP_CSR_COMPxLOCK
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup COMP_Exported_Functions COMP Exported Functions
+ * @{
+ */
+
+/** @defgroup COMP_Exported_Functions_Group1 Initialization/de-initialization functions
+ * @brief Initialization and de-initialization functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions to initialize and de-initialize comparators.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the COMP peripheral according to the specified
+ * parameters in the COMP_InitTypeDef and initialize the associated handle.
+ * @note If the selected comparator is locked, initialization cannot be performed.
+ * To unlock the configuration, perform a system reset.
+ * @param hcomp COMP handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the COMP handle allocation and lock status */
+ if ((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Check the parameters */
+ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+ assert_param(IS_COMP_INVERTINGINPUT(hcomp->Init.InvertingInput));
+ assert_param(IS_COMP_NONINVERTINGINPUT(hcomp->Init.NonInvertingInput));
+ assert_param(IS_COMP_NONINVERTINGINPUT_INSTANCE(hcomp->Instance, hcomp->Init.NonInvertingInput));
+ assert_param(IS_COMP_OUTPUT(hcomp->Init.Output));
+ assert_param(IS_COMP_OUTPUT_INSTANCE(hcomp->Instance, hcomp->Init.Output));
+ assert_param(IS_COMP_OUTPUTPOL(hcomp->Init.OutputPol));
+ assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis));
+ assert_param(IS_COMP_MODE(hcomp->Init.Mode));
+ assert_param(IS_COMP_BLANKINGSRCE(hcomp->Init.BlankingSrce));
+ assert_param(IS_COMP_BLANKINGSRCE_INSTANCE(hcomp->Instance, hcomp->Init.BlankingSrce));
+ assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode));
+
+ if (hcomp->Init.WindowMode != COMP_WINDOWMODE_DISABLE)
+ {
+ assert_param(IS_COMP_WINDOWMODE_INSTANCE(hcomp->Instance));
+ assert_param(IS_COMP_WINDOWMODE(hcomp->Init.WindowMode));
+ }
+
+ /* Init SYSCFG and the low level hardware to access comparators */
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
+ /* Init the low level hardware : SYSCFG to access comparators */
+ HAL_COMP_MspInit(hcomp);
+
+ if (hcomp->State == HAL_COMP_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hcomp->Lock = HAL_UNLOCKED;
+ }
+
+ /* Manage inverting input comparator inverting input connected to a GPIO */
+ /* for STM32F302x, STM32F32xx, STM32F33x. */
+ hcomp->Init.InvertingInput = COMP_INVERTINGINPUT_SELECTION(hcomp->Instance, hcomp->Init.InvertingInput);
+
+ /* Set COMP parameters */
+ /* Set COMPxINSEL bits according to hcomp->Init.InvertingInput value */
+ /* Set COMPxNONINSEL bits according to hcomp->Init.NonInvertingInput value */
+ /* Set COMPxBLANKING bits according to hcomp->Init.BlankingSrce value */
+ /* Set COMPxOUTSEL bits according to hcomp->Init.Output value */
+ /* Set COMPxPOL bit according to hcomp->Init.OutputPol value */
+ /* Set COMPxHYST bits according to hcomp->Init.Hysteresis value */
+ /* Set COMPxMODE bits according to hcomp->Init.Mode value */
+ COMP_INIT(hcomp);
+
+ /* Initialize the COMP state*/
+ hcomp->State = HAL_COMP_STATE_READY;
+ }
+
+ return status;
+}
+
+/**
+ * @brief DeInitialize the COMP peripheral.
+ * @note If the selected comparator is locked, deinitialization cannot be performed.
+ * To unlock the configuration, perform a system reset.
+ * @param hcomp COMP handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the COMP handle allocation and lock status */
+ if ((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Check the parameter */
+ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+
+ /* Set COMP_CSR register to reset value */
+ COMP_DEINIT(hcomp);
+
+ /* DeInit the low level hardware: SYSCFG, GPIO, CLOCK and NVIC */
+ HAL_COMP_MspDeInit(hcomp);
+
+ hcomp->State = HAL_COMP_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hcomp);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Initialize the COMP MSP.
+ * @param hcomp COMP handle
+ * @retval None
+ */
+__weak void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcomp);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_COMP_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the COMP MSP.
+ * @param hcomp COMP handle
+ * @retval None
+ */
+__weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcomp);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_COMP_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup COMP_Exported_Functions_Group2 Start Stop operation functions
+ * @brief Start-Stop operation functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Start Stop operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Start a comparator without interrupt generation.
+ (+) Stop a comparator without interrupt generation.
+ (+) Start a comparator with interrupt generation.
+ (+) Stop a comparator with interrupt generation.
+ (+) Handle interrupts from a comparator with associated callback function.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Start the comparator.
+ * @param hcomp COMP handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t extiline = 0U;
+
+ /* Check the COMP handle allocation and lock status */
+ if ((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Check the parameter */
+ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+
+ if (hcomp->State == HAL_COMP_STATE_READY)
+ {
+ /* Get the EXTI Line output configuration */
+ extiline = COMP_GET_EXTI_LINE(hcomp->Instance);
+
+ /* Configure the event generation */
+ if ((hcomp->Init.TriggerMode & (COMP_TRIGGERMODE_EVENT_RISING | COMP_TRIGGERMODE_EVENT_FALLING)) != RESET)
+ {
+ /* Configure the event trigger rising edge */
+ if ((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_EVENT_RISING) != RESET)
+ {
+ COMP_EXTI_RISING_ENABLE(extiline);
+ }
+ else
+ {
+ COMP_EXTI_RISING_DISABLE(extiline);
+ }
+
+ /* Configure the trigger falling edge */
+ if ((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_EVENT_FALLING) != RESET)
+ {
+ COMP_EXTI_FALLING_ENABLE(extiline);
+ }
+ else
+ {
+ COMP_EXTI_FALLING_DISABLE(extiline);
+ }
+
+ /* Enable EXTI event generation */
+ COMP_EXTI_ENABLE_EVENT(extiline);
+
+ /* Clear COMP EXTI pending bit */
+ COMP_EXTI_CLEAR_FLAG(extiline);
+ }
+
+ /* Enable the selected comparator */
+ __HAL_COMP_ENABLE(hcomp);
+
+ hcomp->State = HAL_COMP_STATE_BUSY;
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief Stop the comparator.
+ * @param hcomp COMP handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the COMP handle allocation and lock status */
+ if ((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Check the parameter */
+ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+
+ if (hcomp->State == HAL_COMP_STATE_BUSY)
+ {
+ /* Disable the EXTI Line event mode if any */
+ COMP_EXTI_DISABLE_EVENT(COMP_GET_EXTI_LINE(hcomp->Instance));
+
+ /* Disable the selected comparator */
+ __HAL_COMP_DISABLE(hcomp);
+
+ hcomp->State = HAL_COMP_STATE_READY;
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief Start the comparator in Interrupt mode.
+ * @param hcomp COMP handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t extiline = 0U;
+
+ /* Check the COMP handle allocation and lock status */
+ if ((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Check the parameter */
+ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+
+ if (hcomp->State == HAL_COMP_STATE_READY)
+ {
+ /* Configure the EXTI event generation */
+ if ((hcomp->Init.TriggerMode & (COMP_TRIGGERMODE_IT_RISING | COMP_TRIGGERMODE_IT_FALLING)) != RESET)
+ {
+ /* Get the EXTI Line output configuration */
+ extiline = COMP_GET_EXTI_LINE(hcomp->Instance);
+
+ /* Configure the trigger rising edge */
+ if ((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_IT_RISING) != RESET)
+ {
+ COMP_EXTI_RISING_ENABLE(extiline);
+ }
+ else
+ {
+ COMP_EXTI_RISING_DISABLE(extiline);
+ }
+ /* Configure the trigger falling edge */
+ if ((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_IT_FALLING) != RESET)
+ {
+ COMP_EXTI_FALLING_ENABLE(extiline);
+ }
+ else
+ {
+ COMP_EXTI_FALLING_DISABLE(extiline);
+ }
+
+ /* Clear COMP EXTI pending bit if any */
+ COMP_EXTI_CLEAR_FLAG(extiline);
+
+ /* Enable EXTI interrupt mode */
+ COMP_EXTI_ENABLE_IT(extiline);
+
+ /* Enable the selected comparator */
+ __HAL_COMP_ENABLE(hcomp);
+
+ hcomp->State = HAL_COMP_STATE_BUSY;
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief Stop the comparator in Interrupt mode.
+ * @param hcomp COMP handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Disable the EXTI Line interrupt mode */
+ COMP_EXTI_DISABLE_IT(COMP_GET_EXTI_LINE(hcomp->Instance));
+
+ status = HAL_COMP_Stop(hcomp);
+
+ return status;
+}
+
+/**
+ * @brief Comparator IRQ Handler.
+ * @param hcomp COMP handle
+ * @retval HAL status
+ */
+void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
+{
+ uint32_t extiline = COMP_GET_EXTI_LINE(hcomp->Instance);
+
+ /* Check COMP EXTI flag */
+ if (COMP_EXTI_GET_FLAG(extiline) != RESET)
+ {
+ /* Clear COMP EXTI pending bit */
+ COMP_EXTI_CLEAR_FLAG(extiline);
+
+ /* COMP trigger user callback */
+ HAL_COMP_TriggerCallback(hcomp);
+ }
+}
+
+/**
+ * @brief Comparator callback.
+ * @param hcomp COMP handle
+ * @retval None
+ */
+__weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcomp);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_COMP_TriggerCallback should be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup COMP_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Management functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the comparators.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Lock the selected comparator configuration.
+ * @note A system reset is required to unlock the comparator configuration.
+ * @param hcomp COMP handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the COMP handle allocation and lock status */
+ if ((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Check the parameter */
+ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+
+ /* Set lock flag on state */
+ switch (hcomp->State)
+ {
+ case HAL_COMP_STATE_BUSY:
+ hcomp->State = HAL_COMP_STATE_BUSY_LOCKED;
+ break;
+ case HAL_COMP_STATE_READY:
+ hcomp->State = HAL_COMP_STATE_READY_LOCKED;
+ break;
+ default:
+ /* unexpected state */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Set the lock bit corresponding to selected comparator */
+ __HAL_COMP_LOCK(hcomp);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Return the output level (high or low) of the selected comparator.
+ * The output level depends on the selected polarity.
+ * If the polarity is not inverted:
+ * - Comparator output is low when the non-inverting input is at a lower
+ * voltage than the inverting input
+ * - Comparator output is high when the non-inverting input is at a higher
+ * voltage than the inverting input
+ * If the polarity is inverted:
+ * - Comparator output is high when the non-inverting input is at a lower
+ * voltage than the inverting input
+ * - Comparator output is low when the non-inverting input is at a higher
+ * voltage than the inverting input
+ * @param hcomp COMP handle
+ * @retval Returns the selected comparator output level:
+ * @arg @ref COMP_OUTPUTLEVEL_LOW
+ * @arg @ref COMP_OUTPUTLEVEL_HIGH
+ *
+ */
+uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp)
+{
+ uint32_t level = 0U;
+
+ /* Check the parameter */
+ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+
+ level = READ_BIT(hcomp->Instance->CSR, COMP_CSR_COMPxOUT);
+
+ if (level != 0U)
+ {
+ return (COMP_OUTPUTLEVEL_HIGH);
+ }
+ return (COMP_OUTPUTLEVEL_LOW);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup COMP_Exported_Functions_Group4 Peripheral State functions
+ * @brief Peripheral State functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the COMP handle state.
+ * @param hcomp COMP handle
+ * @retval HAL state
+ */
+HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp)
+{
+ /* Check the COMP handle allocation */
+ if (hcomp == NULL)
+ {
+ return HAL_COMP_STATE_RESET;
+ }
+
+ /* Check the parameter */
+ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+
+ /* Return COMP handle state */
+ return hcomp->State;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_COMP_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_cortex.c b/Src/stm32f3xx_hal_cortex.c
new file mode 100644
index 0000000..c12c78b
--- /dev/null
+++ b/Src/stm32f3xx_hal_cortex.c
@@ -0,0 +1,529 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_cortex.c
+ * @author MCD Application Team
+ * @brief CORTEX HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the CORTEX:
+ * + Initialization and de-initialization functions
+ * + Peripheral Control functions
+ *
+ * @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+
+ [..]
+ *** How to configure Interrupts using CORTEX HAL driver ***
+ ===========================================================
+ [..]
+ This section provides functions allowing to configure the NVIC interrupts (IRQ).
+ The Cortex-M4 exceptions are managed by CMSIS functions.
+
+ (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function
+
+ (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()
+
+ (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()
+
+
+ -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
+ The pending IRQ priority will be managed only by the sub priority.
+
+ -@- IRQ priority order (sorted by highest to lowest priority):
+ (+@) Lowest pre-emption priority
+ (+@) Lowest sub priority
+ (+@) Lowest hardware priority (IRQ number)
+
+ [..]
+ *** How to configure Systick using CORTEX HAL driver ***
+ ========================================================
+ [..]
+ Setup SysTick Timer for time base
+
+ (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
+ is a CMSIS function that:
+ (++) Configures the SysTick Reload register with value passed as function parameter.
+ (++) Configures the SysTick IRQ priority to the lowest value (0x0FU).
+ (++) Resets the SysTick Counter register.
+ (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
+ (++) Enables the SysTick Interrupt.
+ (++) Starts the SysTick Counter.
+
+ (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
+ __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
+ HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
+ inside the stm32f3xx_hal_cortex.h file.
+
+ (+) You can change the SysTick IRQ priority by calling the
+ HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
+ call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
+
+ (+) To adjust the SysTick time base, use the following formula:
+
+ Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
+ (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
+ (++) Reload Value should not exceed 0xFFFFFF
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*
+ Additional Tables: CORTEX_NVIC_Priority_Table
+ The table below gives the allowed values of the pre-emption priority and subpriority according
+ to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function
+ ==========================================================================================================================
+ NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
+ ==========================================================================================================================
+ NVIC_PRIORITYGROUP_0 | 0 | 0U-15 | 0 bits for pre-emption priority
+ | | | 4 bits for subpriority
+ --------------------------------------------------------------------------------------------------------------------------
+ NVIC_PRIORITYGROUP_1 | 0U-1 | 0U-7 | 1 bits for pre-emption priority
+ | | | 3 bits for subpriority
+ --------------------------------------------------------------------------------------------------------------------------
+ NVIC_PRIORITYGROUP_2 | 0U-3 | 0U-3 | 2 bits for pre-emption priority
+ | | | 2 bits for subpriority
+ --------------------------------------------------------------------------------------------------------------------------
+ NVIC_PRIORITYGROUP_3 | 0U-7 | 0U-1 | 3 bits for pre-emption priority
+ | | | 1 bits for subpriority
+ --------------------------------------------------------------------------------------------------------------------------
+ NVIC_PRIORITYGROUP_4 | 0U-15 | 0 | 4 bits for pre-emption priority
+ | | | 0 bits for subpriority
+ ==========================================================================================================================
+
+*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup CORTEX CORTEX
+ * @brief CORTEX CORTEX HAL module driver
+ * @{
+ */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
+ * @{
+ */
+
+
+/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de-initialization functions #####
+ ==============================================================================
+ [..]
+ This section provides the CORTEX HAL driver functions allowing to configure Interrupts
+ Systick functionalities
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Sets the priority grouping field (pre-emption priority and subpriority)
+ * using the required unlock sequence.
+ * @param PriorityGroup The priority grouping bits length.
+ * This parameter can be one of the following values:
+ * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
+ * 4 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
+ * 3 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
+ * 2 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
+ * 1 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
+ * 0 bits for subpriority
+ * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
+ * The pending IRQ priority will be managed only by the subpriority.
+ * @retval None
+ */
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+
+ /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
+ NVIC_SetPriorityGrouping(PriorityGroup);
+}
+
+/**
+ * @brief Sets the priority of an interrupt.
+ * @param IRQn External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
+ * @param PreemptPriority The pre-emption priority for the IRQn channel.
+ * This parameter can be a value between 0 and 15 as described in the table CORTEX_NVIC_Priority_Table
+ * A lower priority value indicates a higher priority
+ * @param SubPriority the subpriority level for the IRQ channel.
+ * This parameter can be a value between 0 and 15 as described in the table CORTEX_NVIC_Priority_Table
+ * A lower priority value indicates a higher priority.
+ * @retval None
+ */
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t prioritygroup = 0x00U;
+
+ /* Check the parameters */
+ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
+ assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
+
+ prioritygroup = NVIC_GetPriorityGrouping();
+
+ NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
+}
+
+/**
+ * @brief Enables a device specific interrupt in the NVIC interrupt controller.
+ * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
+ * function should be called before.
+ * @param IRQn External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
+ * @retval None
+ */
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+ /* Enable interrupt */
+ NVIC_EnableIRQ(IRQn);
+}
+
+/**
+ * @brief Disables a device specific interrupt in the NVIC interrupt controller.
+ * @param IRQn External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
+ * @retval None
+ */
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+ /* Disable interrupt */
+ NVIC_DisableIRQ(IRQn);
+}
+
+/**
+ * @brief Initiates a system reset request to reset the MCU.
+ * @retval None
+ */
+void HAL_NVIC_SystemReset(void)
+{
+ /* System Reset */
+ NVIC_SystemReset();
+}
+
+/**
+ * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ * Counter is in free running mode to generate periodic interrupts.
+ * @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
+ * @retval status: - 0 Function succeeded.
+ * - 1 Function failed.
+ */
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
+{
+ return SysTick_Config(TicksNumb);
+}
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
+ * @brief Cortex control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the CORTEX
+ (NVIC, SYSTICK, MPU) functionalities.
+
+
+@endverbatim
+ * @{
+ */
+
+#if (__MPU_PRESENT == 1U)
+
+/**
+ * @brief Disables the MPU also clears the HFNMIENA bit (ARM recommendation)
+ * @retval None
+ */
+void HAL_MPU_Disable(void)
+{
+ /* Disable fault exceptions */
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+
+ /* Disable the MPU */
+ MPU->CTRL = 0U;
+}
+
+/**
+ * @brief Enables the MPU
+ * @param MPU_Control Specifies the control mode of the MPU during hard fault,
+ * NMI, FAULTMASK and privileged access to the default memory
+ * This parameter can be one of the following values:
+ * @arg MPU_HFNMI_PRIVDEF_NONE
+ * @arg MPU_HARDFAULT_NMI
+ * @arg MPU_PRIVILEGED_DEFAULT
+ * @arg MPU_HFNMI_PRIVDEF
+ * @retval None
+ */
+void HAL_MPU_Enable(uint32_t MPU_Control)
+{
+ /* Enable the MPU */
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+
+ /* Enable fault exceptions */
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+}
+
+ /**
+ * @brief Initializes and configures the Region and the memory to be protected.
+ * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
+ * the initialization and configuration information.
+ * @retval None
+ */
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
+{
+ /* Check the parameters */
+ assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
+ assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
+
+ /* Set the Region number */
+ MPU->RNR = MPU_Init->Number;
+
+ if ((MPU_Init->Enable) != RESET)
+ {
+ /* Check the parameters */
+ assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
+ assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
+ assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
+ assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
+ assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
+ assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
+ assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
+ assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
+
+ MPU->RBAR = MPU_Init->BaseAddress;
+ MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
+ ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
+ ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
+ ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
+ ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
+ ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
+ ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
+ ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
+ ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
+ }
+ else
+ {
+ MPU->RBAR = 0x00U;
+ MPU->RASR = 0x00U;
+ }
+}
+#endif /* __MPU_PRESENT */
+
+/**
+ * @brief Gets the priority grouping field from the NVIC Interrupt Controller.
+ * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
+ */
+uint32_t HAL_NVIC_GetPriorityGrouping(void)
+{
+ /* Get the PRIGROUP[10:8] field value */
+ return NVIC_GetPriorityGrouping();
+}
+
+/**
+ * @brief Gets the priority of an interrupt.
+ * @param IRQn External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
+ * @param PriorityGroup: the priority grouping bits length.
+ * This parameter can be one of the following values:
+ * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
+ * 4 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
+ * 3 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
+ * 2 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
+ * 1 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
+ * 0 bits for subpriority
+ * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0).
+ * @param pSubPriority Pointer on the Subpriority value (starting from 0).
+ * @retval None
+ */
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+ /* Get priority for Cortex-M system or device specific interrupts */
+ NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
+}
+
+/**
+ * @brief Sets Pending bit of an external interrupt.
+ * @param IRQn External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
+ * @retval None
+ */
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ /* Set interrupt pending */
+ NVIC_SetPendingIRQ(IRQn);
+}
+
+/**
+ * @brief Gets Pending Interrupt (reads the pending register in the NVIC
+ * and returns the pending bit for the specified interrupt).
+ * @param IRQn External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
+ * @retval status: - 0 Interrupt status is not pending.
+ * - 1 Interrupt status is pending.
+ */
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ /* Return 1 if pending else 0U */
+ return NVIC_GetPendingIRQ(IRQn);
+}
+
+/**
+ * @brief Clears the pending bit of an external interrupt.
+ * @param IRQn External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
+ * @retval None
+ */
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ /* Clear pending interrupt */
+ NVIC_ClearPendingIRQ(IRQn);
+}
+
+/**
+ * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
+ * @param IRQn External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
+ * @retval status: - 0 Interrupt status is not pending.
+ * - 1 Interrupt status is pending.
+ */
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
+{
+ /* Return 1 if active else 0U */
+ return NVIC_GetActive(IRQn);
+}
+
+/**
+ * @brief Configures the SysTick clock source.
+ * @param CLKSource specifies the SysTick clock source.
+ * This parameter can be one of the following values:
+ * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
+ * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
+ * @retval None
+ */
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
+ if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
+ {
+ SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
+ }
+ else
+ {
+ SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
+ }
+}
+
+/**
+ * @brief This function handles SYSTICK interrupt request.
+ * @retval None
+ */
+void HAL_SYSTICK_IRQHandler(void)
+{
+ HAL_SYSTICK_Callback();
+}
+
+/**
+ * @brief SYSTICK callback.
+ * @retval None
+ */
+__weak void HAL_SYSTICK_Callback(void)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SYSTICK_Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_crc.c b/Src/stm32f3xx_hal_crc.c
new file mode 100644
index 0000000..39c600f
--- /dev/null
+++ b/Src/stm32f3xx_hal_crc.c
@@ -0,0 +1,539 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_crc.c
+ * @author MCD Application Team
+ * @brief CRC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Cyclic Redundancy Check (CRC) peripheral:
+ * + Initialization and de-initialization functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ (+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
+ (+) Initialize CRC calculator
+ (++)specify generating polynomial (IP default or non-default one)
+ (++)specify initialization value (IP default or non-default one)
+ (++)specify input data format
+ (++)specify input or output data inversion mode if any
+ (+) Use HAL_CRC_Accumulate() function to compute the CRC value of the
+ input data buffer starting with the previously computed CRC as
+ initialization value
+ (+) Use HAL_CRC_Calculate() function to compute the CRC value of the
+ input data buffer starting with the defined initialization value
+ (default or non-default) to initiate CRC calculation
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup CRC CRC
+ * @brief CRC HAL module driver.
+ * @{
+ */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup CRC_Private_Functions CRC Private Functions
+ * @{
+ */
+static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength);
+static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup CRC_Exported_Functions CRC Exported Functions
+ * @{
+ */
+
+/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize the CRC according to the specified parameters
+ in the CRC_InitTypeDef and create the associated handle
+ (+) DeInitialize the CRC peripheral
+ (+) Initialize the CRC MSP (MCU Specific Package)
+ (+) DeInitialize the CRC MSP
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the CRC according to the specified
+ * parameters in the CRC_InitTypeDef and initialize the associated handle.
+ * @param hcrc CRC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
+{
+ /* Check the CRC handle allocation */
+ if(hcrc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
+
+ if(hcrc->State == HAL_CRC_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hcrc->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware */
+ HAL_CRC_MspInit(hcrc);
+ }
+
+ hcrc->State = HAL_CRC_STATE_BUSY;
+
+ /* check whether or not non-default generating polynomial has been
+ * picked up by user */
+ assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse));
+ if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)
+ {
+ /* initialize IP with default generating polynomial */
+ WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY);
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B);
+ }
+ else
+ {
+ /* initialize CRC IP with generating polynomial defined by user */
+ if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /* check whether or not non-default CRC initial value has been
+ * picked up by user */
+ assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse));
+ if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)
+ {
+ WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE);
+ }
+ else
+ {
+ WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue);
+ }
+
+
+ /* set input data inversion mode */
+ assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode));
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode);
+
+ /* set output data inversion mode */
+ assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode));
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode);
+
+ /* makes sure the input data format (bytes, halfwords or words stream)
+ * is properly specified by user */
+ assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat));
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitialize the CRC peripheral.
+ * @param hcrc CRC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
+{
+ /* Check the CRC handle allocation */
+ if(hcrc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
+
+ /* Check the CRC peripheral state */
+ if(hcrc->State == HAL_CRC_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_BUSY;
+
+ /* Reset CRC calculation unit */
+ __HAL_CRC_DR_RESET(hcrc);
+
+ /* Reset IDR register content */
+ CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR) ;
+
+ /* DeInit the low level hardware */
+ HAL_CRC_MspDeInit(hcrc);
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_RESET;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcrc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRC MSP.
+ * @param hcrc CRC handle
+ * @retval None
+ */
+__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcrc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CRC_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the CRC MSP.
+ * @param hcrc CRC handle
+ * @retval None
+ */
+__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcrc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CRC_MspDeInit can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
+ * @brief management functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) compute the 7U, 8U, 16 or 32-bit CRC value of an 8U, 16 or 32-bit data buffer
+ using the combination of the previous CRC value and the new one
+
+ [..] or
+
+ (+) compute the 7U, 8U, 16 or 32-bit CRC value of an 8U, 16 or 32-bit data buffer
+ independently of the previous CRC value.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
+ * starting with the previously computed CRC as initialization value.
+ * @param hcrc CRC handle
+ * @param pBuffer pointer to the input data buffer, exact input data format is
+ * provided by hcrc->InputDataFormat.
+ * @param BufferLength input data buffer length (number of bytes if pBuffer
+ * type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
+ * number of words if pBuffer type is * uint32_t).
+ * @note By default, the API expects a uint32_t pointer as input buffer parameter.
+ * Input buffer pointers with other types simply need to be cast in uint32_t
+ * and the API will internally adjust its input data processing based on the
+ * handle field hcrc->InputDataFormat.
+ * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
+ */
+uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
+{
+ uint32_t index = 0U; /* CRC input data buffer index */
+ uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */
+
+ /* Process locked */
+ __HAL_LOCK(hcrc);
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_BUSY;
+
+ switch (hcrc->InputDataFormat)
+ {
+ case CRC_INPUTDATA_FORMAT_WORDS:
+ /* Enter Data to the CRC calculator */
+ for(index = 0U; index < BufferLength; index++)
+ {
+ hcrc->Instance->DR = pBuffer[index];
+ }
+ temp = hcrc->Instance->DR;
+ break;
+
+ case CRC_INPUTDATA_FORMAT_BYTES:
+ temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength);
+ break;
+
+ case CRC_INPUTDATA_FORMAT_HALFWORDS:
+ temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength);
+ break;
+
+ default:
+ break;
+ }
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcrc);
+
+ /* Return the CRC computed value */
+ return temp;
+}
+
+
+/**
+ * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
+ * starting with hcrc->Instance->INIT as initialization value.
+ * @param hcrc CRC handle
+ * @param pBuffer pointer to the input data buffer, exact input data format is
+ * provided by hcrc->InputDataFormat.
+ * @param BufferLength input data buffer length (number of bytes if pBuffer
+ * type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
+ * number of words if pBuffer type is * uint32_t).
+ * @note By default, the API expects a uint32_t pointer as input buffer parameter.
+ * Input buffer pointers with other types simply need to be cast in uint32_t
+ * and the API will internally adjust its input data processing based on the
+ * handle field hcrc->InputDataFormat.
+ * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
+ */
+uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
+{
+ uint32_t index = 0U; /* CRC input data buffer index */
+ uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */
+
+ /* Process locked */
+ __HAL_LOCK(hcrc);
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_BUSY;
+
+ /* Reset CRC Calculation Unit (hcrc->Instance->INIT is
+ * written in hcrc->Instance->DR) */
+ __HAL_CRC_DR_RESET(hcrc);
+
+ switch (hcrc->InputDataFormat)
+ {
+ case CRC_INPUTDATA_FORMAT_WORDS:
+ /* Enter 32-bit input data to the CRC calculator */
+ for(index = 0U; index < BufferLength; index++)
+ {
+ hcrc->Instance->DR = pBuffer[index];
+ }
+ temp = hcrc->Instance->DR;
+ break;
+
+ case CRC_INPUTDATA_FORMAT_BYTES:
+ /* Specific 8-bit input data handling */
+ temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength);
+ break;
+
+ case CRC_INPUTDATA_FORMAT_HALFWORDS:
+ /* Specific 16-bit input data handling */
+ temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength);
+ break;
+
+ default:
+ break;
+ }
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcrc);
+
+ /* Return the CRC computed value */
+ return temp;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
+ * @brief Peripheral State functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the CRC handle state.
+ * @param hcrc CRC handle
+ * @retval HAL state
+ */
+HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
+{
+ /* Return CRC handle state */
+ return hcrc->State;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Private_Functions CRC Private Functions
+ * @{
+ */
+
+/**
+ * @brief Enter 8-bit input data to the CRC calculator.
+ * Specific data handling to optimize processing time.
+ * @param hcrc CRC handle
+ * @param pBuffer pointer to the input data buffer
+ * @param BufferLength input data buffer length
+ * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
+ */
+static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
+{
+ uint32_t i = 0U; /* input data buffer index */
+
+ /* Processing time optimization: 4 bytes are entered in a row with a single word write,
+ * last bytes must be carefully fed to the CRC calculator to ensure a correct type
+ * handling by the IP */
+ for(i = 0U; i < (BufferLength/4U); i++)
+ {
+ hcrc->Instance->DR = ((uint32_t)pBuffer[4U*i]<<24U) | ((uint32_t)pBuffer[4U*i+1]<<16U) | ((uint32_t)pBuffer[4U*i+2]<<8U) | (uint32_t)pBuffer[4U*i+3];
+ }
+ /* last bytes specific handling */
+ if ((BufferLength%4U) != 0U)
+ {
+ if (BufferLength%4U == 1U)
+ {
+ *(uint8_t volatile*) (&hcrc->Instance->DR) = pBuffer[4*i];
+ }
+ if (BufferLength%4U == 2U)
+ {
+ *(uint16_t volatile*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4*i]<<8) | (uint32_t)pBuffer[4*i+1];
+ }
+ if (BufferLength%4U == 3U)
+ {
+ *(uint16_t volatile*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4*i]<<8) | (uint32_t)pBuffer[4*i+1];
+ *(uint8_t volatile*) (&hcrc->Instance->DR) = pBuffer[4*i+2];
+ }
+ }
+
+ /* Return the CRC computed value */
+ return hcrc->Instance->DR;
+}
+
+
+
+/**
+ * @brief Enter 16-bit input data to the CRC calculator.
+ * Specific data handling to optimize processing time.
+ * @param hcrc CRC handle
+ * @param pBuffer pointer to the input data buffer
+ * @param BufferLength input data buffer length
+ * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
+ */
+static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
+{
+ uint32_t i = 0U; /* input data buffer index */
+
+ /* Processing time optimization: 2 HalfWords are entered in a row with a single word write,
+ * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure
+ * a correct type handling by the IP */
+ for(i = 0U; i < (BufferLength/2U); i++)
+ {
+ hcrc->Instance->DR = ((uint32_t)pBuffer[2U*i]<<16U) | (uint32_t)pBuffer[2U*i+1];
+ }
+ if ((BufferLength%2U) != 0U)
+ {
+ *(uint16_t volatile*) (&hcrc->Instance->DR) = pBuffer[2*i];
+ }
+
+ /* Return the CRC computed value */
+ return hcrc->Instance->DR;
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_CRC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_crc_ex.c b/Src/stm32f3xx_hal_crc_ex.c
new file mode 100644
index 0000000..c89b975
--- /dev/null
+++ b/Src/stm32f3xx_hal_crc_ex.c
@@ -0,0 +1,235 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_crc_ex.c
+ * @author MCD Application Team
+ * @brief Extended CRC HAL module driver.
+ * This file provides firmware functions to manage the extended
+ * functionalities of the CRC peripheral.
+ *
+ @verbatim
+================================================================================
+ ##### How to use this driver #####
+================================================================================
+ [..]
+ (+) Set user-defined generating polynomial thru HAL_CRCEx_Polynomial_Set()
+ (+) Configure Input or Output data inversion
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup CRCEx CRCEx
+ * @brief CRC Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup CRCEx_Exported_Functions CRC Extended Exported Functions
+ * @{
+ */
+
+/** @defgroup CRCEx_Exported_Functions_Group1 CRC Extended Initialization and de-initialization functions
+ * @brief CRC Extended Initialization and Configuration functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended configuration functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure the generating polynomial
+ (+) Configure the input data inversion
+ (+) Configure the output data inversion
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Initialize the CRC polynomial if different from default one.
+ * @param hcrc CRC handle
+ * @param Pol CRC generating polynomial (7, 8, 16 or 32-bit long).
+ * This parameter is written in normal representation, e.g.
+ * @arg for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
+ * @arg for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021
+ * @param PolyLength CRC polynomial length.
+ * This parameter can be one of the following values:
+ * @arg CRC_POLYLENGTH_7B: 7-bit long CRC (generating polynomial of degree 7)
+ * @arg CRC_POLYLENGTH_8B: 8-bit long CRC (generating polynomial of degree 8)
+ * @arg CRC_POLYLENGTH_16B: 16-bit long CRC (generating polynomial of degree 16)
+ * @arg CRC_POLYLENGTH_32B: 32-bit long CRC (generating polynomial of degree 32)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
+{
+ uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */
+
+ /* Check the parameters */
+ assert_param(IS_CRC_POL_LENGTH(PolyLength));
+
+ /* check polynomial definition vs polynomial size:
+ * polynomial length must be aligned with polynomial
+ * definition. HAL_ERROR is reported if Pol degree is
+ * larger than that indicated by PolyLength.
+ * Look for MSB position: msb will contain the degree of
+ * the second to the largest polynomial member. E.g., for
+ * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
+ while (((Pol & (1U << msb)) == 0U) && (msb-- > 0U)){}
+
+ switch (PolyLength)
+ {
+ case CRC_POLYLENGTH_7B:
+ if (msb >= HAL_CRC_LENGTH_7B)
+ {
+ return HAL_ERROR;
+ }
+ break;
+ case CRC_POLYLENGTH_8B:
+ if (msb >= HAL_CRC_LENGTH_8B)
+ {
+ return HAL_ERROR;
+ }
+ break;
+ case CRC_POLYLENGTH_16B:
+ if (msb >= HAL_CRC_LENGTH_16B)
+ {
+ return HAL_ERROR;
+ }
+ break;
+ case CRC_POLYLENGTH_32B:
+ /* no polynomial definition vs. polynomial length issue possible */
+ break;
+ default:
+ break;
+ }
+
+ /* set generating polynomial */
+ WRITE_REG(hcrc->Instance->POL, Pol);
+
+ /* set generating polynomial size */
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the Reverse Input data mode.
+ * @param hcrc CRC handle
+ * @param InputReverseMode Input Data inversion mode.
+ * This parameter can be one of the following values:
+ * @arg CRC_INPUTDATA_NOINVERSION: no change in bit order (default value)
+ * @arg CRC_INPUTDATA_INVERSION_BYTE: Byte-wise bit reversal
+ * @arg CRC_INPUTDATA_INVERSION_HALFWORD: HalfWord-wise bit reversal
+ * @arg CRC_INPUTDATA_INVERSION_WORD: Word-wise bit reversal
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
+{
+ /* Check the parameters */
+ assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(InputReverseMode));
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_BUSY;
+
+ /* set input data inversion mode */
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, InputReverseMode);
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the Reverse Output data mode.
+ * @param hcrc CRC handle
+ * @param OutputReverseMode Output Data inversion mode.
+ * This parameter can be one of the following values:
+ * @arg CRC_OUTPUTDATA_INVERSION_DISABLE: no CRC inversion (default value)
+ * @arg CRC_OUTPUTDATA_INVERSION_ENABLE: bit-level inversion (e.g. for a 8-bit CRC: 0xB5 becomes 0xAD)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
+{
+ /* Check the parameters */
+ assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(OutputReverseMode));
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_BUSY;
+
+ /* set output data inversion mode */
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, OutputReverseMode);
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+
+
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+
+#endif /* HAL_CRC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_dac.c b/Src/stm32f3xx_hal_dac.c
new file mode 100644
index 0000000..1594168
--- /dev/null
+++ b/Src/stm32f3xx_hal_dac.c
@@ -0,0 +1,772 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_dac.c
+ * @author MCD Application Team
+ * @brief DAC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Digital to Analog Converter (DAC) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State and Errors functions
+ *
+ *
+ @verbatim
+ ==============================================================================
+ ##### DAC Peripheral features #####
+ ==============================================================================
+ [..]
+ *** DAC Channels ***
+ ====================
+ [..]
+ The device integrates up to 3 12-bit Digital Analog Converters that can
+ be used independently or simultaneously (dual mode):
+ (#) DAC1 channel1 with DAC1_OUT1 (PA4) as output
+ (#) DAC1 channel2 with DAC1_OUT2 (PA5) as output
+ (for STM32F3 devices having 2 channels on DAC1)
+ (#) DAC2 channel1 with DAC2_OUT1 (PA6) as output
+ (for STM32F3 devices having 2 DAC)
+
+ *** DAC Triggers ***
+ ====================
+ [..]
+ Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
+ and DAC1_OUT1/DAC1_OUT2/DAC2_OUT1 is available once writing to DHRx register.
+ [..]
+ Digital to Analog conversion can be triggered by:
+ (#) External event: EXTI Line 9 (any GPIOx_PIN_9) using DAC_TRIGGER_EXT_IT9.
+ The used pin (GPIOx_PIN_9) must be configured in input mode.
+
+ (#) Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8
+ (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T4_TRGO...)
+
+ (#) Software using DAC_TRIGGER_SOFTWARE
+
+ *** DAC Buffer mode feature ***
+ ===============================
+ [..]
+ Each DAC channel integrates an output buffer that can be used to
+ reduce the output impedance, and to drive external loads directly
+ without having to add an external operational amplifier.
+ To enable, the output buffer use
+ sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
+ Or
+ An output switch
+ (in STM32F303x4, STM32F303x6, STM32F303x8
+ c, STM32F334x6, STM32F334x8
+ & STM32F334xx).
+ To enable, the output switch
+ sConfig.DAC_OutputSwitch = DAC_OUTPUTSWITCH_ENABLE;
+ [..]
+ (@) Refer to the device datasheet for more details about output
+ impedance value with and without output buffer.
+
+ *** GPIO configurations guidelines ***
+ =====================
+ [..]
+ When a DAC channel is used (ex channel1 on PA4) and the other is not
+ (ex channel2 on PA5 is configured in Analog and disabled).
+ Channel1 may disturb channel2 as coupling effect.
+ Note that there is no coupling on channel2 as soon as channel2 is turned on.
+ Coupling on adjacent channel could be avoided as follows:
+ when unused PA5 is configured as INPUT PULL-UP or DOWN.
+ PA5 is configured in ANALOG just before it is turned on.
+
+
+ *** DAC wave generation feature ***
+ ===================================
+ [..]
+ Both DAC channels of DAC1 can be used to generate
+ note that wave generation is not available in DAC2.
+ (#) Noise wave
+ (#) Triangle wave
+
+ Wave generation is NOT available in DAC2.
+
+ *** DAC data format ***
+ =======================
+ [..]
+ The DAC data format can be:
+ (#) 8-bit right alignment using DAC_ALIGN_8B_R
+ (#) 12-bit left alignment using DAC_ALIGN_12B_L
+ (#) 12-bit right alignment using DAC_ALIGN_12B_R
+
+ *** DAC data value to voltage correspondance ***
+ ================================================
+ [..]
+ The analog output voltage on each DAC channel pin is determined
+ by the following equation:
+ [..]
+ DAC_OUTx = VREF+ * DOR / 4095
+ (+) with DOR is the Data Output Register
+ [..]
+ VEF+ is the input voltage reference (refer to the device datasheet)
+ [..]
+ e.g. To set DAC_OUT1 to 0.7V, use
+ (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3U * 868U) / 4095U = 0.7V
+
+ *** DMA requests ***
+ =====================
+ [..]
+ A DMA1 or DMA2 request can be generated when an external trigger
+ (but not a software trigger) occurs if DMA1 or DMA2 requests are
+ enabled using HAL_DAC_Start_DMA().
+ [..]
+ DMA1 requests are mapped as following:
+ (#) DAC1 channel1: mapped either on
+ (++) DMA1 channel3
+ (++) or DMA2 channel3 (for STM32F3 devices having 2 DMA)
+ which must be already configured
+ (#) DAC1 channel2:
+ (for STM32F3 devices having 2 channels on DAC1)
+ mapped either on
+ (++) DMA1 channel4
+ (++) or DMA2 channel4 (for STM32F3 devices having 2 DMA)
+ which must be already configured
+
+ (#) DAC2 channel1: mapped either on
+ (for STM32F3 devices having 2 DAC)
+ (++) DMA1 channel4
+ (++) or DMA2 channel4 (for STM32F3 devices having 2 DMA)
+ which must be already configured
+
+
+ (@) For Dual mode and specific signal (Triangle and noise) generation please
+ refer to Extended Features Driver description
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (+) DAC APB clock must be enabled to get write access to DAC
+ registers using HAL_DAC_Init()
+ (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
+ (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
+ (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA() functions
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Start the DAC peripheral using HAL_DAC_Start()
+ (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
+ (+) Stop the DAC peripheral using HAL_DAC_Stop()
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
+ of data to be transferred at each end of conversion
+ (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
+ function is executed and user can add his own code by customization of function pointer
+ HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
+ (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
+ function is executed and user can add his own code by customization of function pointer
+ HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
+ (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can
+ add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
+ (+) In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler.
+ HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2()
+ function is executed and user can add his own code by customization of function pointer
+ HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() and
+ add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1()
+ (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
+
+ *** DAC HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in DAC HAL driver.
+
+ (+) __HAL_DAC_ENABLE : Enable the DAC peripheral
+ (+) __HAL_DAC_DISABLE : Disable the DAC peripheral
+ (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags
+ (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status
+
+ [..]
+ (@) You can refer to the DAC HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup DAC DAC
+ * @brief DAC HAL module driver
+ * @{
+ */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup DAC_Private_Macros DAC Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup DAC_Private_Functions DAC Private Functions
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Exported functions -------------------------------------------------------*/
+
+/** @defgroup DAC_Exported_Functions DAC Exported Functions
+ * @{
+ */
+
+/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de-initialization functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize and configure the DAC.
+ (+) De-initialize the DAC.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the DAC peripheral according to the specified parameters
+ * in the DAC_InitStruct and initialize the associated handle.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
+{
+ /* Check DAC handle */
+ if(hdac == NULL)
+ {
+ return HAL_ERROR;
+ }
+ /* Check the parameters */
+ assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
+
+ if(hdac->State == HAL_DAC_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hdac->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware */
+ HAL_DAC_MspInit(hdac);
+ }
+
+ /* Initialize the DAC state*/
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* Set DAC error code to none */
+ hdac->ErrorCode = HAL_DAC_ERROR_NONE;
+
+ /* Initialize the DAC state*/
+ hdac->State = HAL_DAC_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Deinitialize the DAC peripheral registers to their default reset values.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)
+{
+ /* Check DAC handle */
+ if(hdac == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* DeInit the low level hardware */
+ HAL_DAC_MspDeInit(hdac);
+
+ /* Set DAC error code to none */
+ hdac->ErrorCode = HAL_DAC_ERROR_NONE;
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdac);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the DAC MSP.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_DAC_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the DAC MSP.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_DAC_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Exported_Functions_Group2 Input and Output operation functions
+ * @brief IO operation functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Start conversion.
+ (+) Stop conversion.
+ (+) Start conversion and enable DMA transfer.
+ (+) Stop conversion and disable DMA transfer.
+ (+) Get result of conversion.
+ (+) Get result of dual mode conversion.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables DAC and starts conversion of channel.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC1 Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC1 Channel2 selected
+ * @arg DAC_CHANNEL_1: DAC2 Channel1 selected
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+ UNUSED(Channel);
+
+ /* Note : This function is defined into this file for library reference */
+ /* Function content is located into file stm32f3xx_hal_dac_ex.c */
+
+ /* Return function status */
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Disables DAC and stop conversion of channel.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC1 Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC1 Channel2 selected
+ * @arg DAC_CHANNEL_1: DAC2 Channel1 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel));
+
+ /* Disable the Peripheral */
+ __HAL_DAC_DISABLE(hdac, Channel);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables DAC and stop conversion of channel.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC1 Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC1 Channel2 selected
+ * @arg DAC_CHANNEL_1: DAC2 Channel1 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel));
+
+ /* Disable the selected DAC channel DMA request */
+ hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel);
+
+ /* Disable the Peripheral */
+ __HAL_DAC_DISABLE(hdac, Channel);
+
+ /* Disable the DMA channel */
+ /* Channel1 is used */
+ if (Channel == DAC_CHANNEL_1)
+ {
+ /* Disable the DMA channel */
+ status = HAL_DMA_Abort(hdac->DMA_Handle1);
+
+ /* Disable the DAC DMA underrun interrupt */
+ __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
+ }
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+
+ /* For all products including channel 2U */
+ /* DAC channel 2 is available on top of DAC channel 1U */
+ else /* Channel2 is used for */
+ {
+ /* Disable the DMA channel */
+ status = HAL_DMA_Abort(hdac->DMA_Handle2);
+
+ /* Disable the DAC DMA underrun interrupt */
+ __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
+ }
+#endif
+
+ /* Check if DMA Channel effectively disabled */
+ if (status != HAL_OK)
+ {
+ /* Update DAC state machine to error */
+ hdac->State = HAL_DAC_STATE_ERROR;
+ }
+ else
+ {
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Returns the last data output value of the selected DAC channel.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC1 Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC1 Channel2 selected
+ * @arg DAC_CHANNEL_1: DAC2 Channel1 selected
+ * @retval The selected DAC channel data output value.
+ */
+__weak uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+ UNUSED(Channel);
+
+ /* Note : This function is defined into this file for library reference */
+ /* Function content is located into file stm32f3xx_hal_dac_ex.c */
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Returns the last data output value of the selected DAC channel.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval The selected DAC channel data output value.
+ */
+__weak uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+
+ /* Note : This function is defined into this file for library reference */
+ /* Function content is located into file stm32f3xx_hal_dac_ex.c */
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure channels.
+ (+) Configure Triangle wave generation.
+ (+) Configure Noise wave generation.
+ (+) Set the specified data holding register value for DAC channel.
+ (+) Set the specified data holding register value for Dual DAC channels.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the selected DAC channel.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param sConfig DAC configuration structure.
+ * @param Channel The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC1 Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC1 Channel2 selected
+ * @arg DAC_CHANNEL_1: DAC2 Channel1 selected
+ * @retval HAL status
+ */
+
+__weak HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+ UNUSED(sConfig);
+ UNUSED(Channel);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+__weak HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+ UNUSED(Channel);
+ UNUSED(Alignment);
+ UNUSED(Data);
+
+ /* Note : This function is defined into this file for library reference */
+ /* Function content is located into file stm32f3xx_hal_dac_ex.c */
+
+ /* Return function status */
+ return HAL_ERROR;
+}
+
+__weak HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+ UNUSED(Alignment);
+ UNUSED(Data1);
+ UNUSED(Data2);
+
+ /* Note : This function is defined into this file for library reference */
+ /* Function content is located into file stm32f3xx_hal_dac_ex.c */
+
+ /* Return function status */
+ return HAL_ERROR;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Error functions
+ * @brief DAC Peripheral State and Error functions
+ *
+@verbatim
+ ==============================================================================
+ ##### DAC Peripheral State and Error functions #####
+ ==============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Check the DAC state.
+ (+) Check the DAC Errors.
+
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief return the DAC handle state
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval HAL state
+ */
+HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac)
+{
+ /* Return DAC handle state */
+ return hdac->State;
+}
+
+/**
+ * @brief Return the DAC error code
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval DAC Error Code
+ */
+uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
+{
+ return hdac->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Exported_Functions_Group2 Input and Output operation functions
+ * @{
+ */
+
+/**
+ * @brief Conversion complete callback in non blocking mode for Channel1
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DAC_ConvCpltCallback1 could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Conversion half DMA transfer callback in non blocking mode for Channel1
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Error DAC callback for Channel1.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DAC_ErrorCallback could be implemented in the user file
+ */
+}
+
+
+/**
+ * @brief DMA underrun DAC callback for Channel1.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_dac_ex.c b/Src/stm32f3xx_hal_dac_ex.c
new file mode 100644
index 0000000..5536cd2
--- /dev/null
+++ b/Src/stm32f3xx_hal_dac_ex.c
@@ -0,0 +1,1144 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_dac_ex.c
+ * @author MCD Application Team
+ * @brief DACEx HAL module driver.
+ * This file provides firmware functions to manage the extended
+ * functionalities of the DAC peripheral.
+ *
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) :
+ Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
+ HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2.
+ (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
+ (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+
+/** @defgroup DACEx DACEx
+ * @brief DAC HAL module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup DACEx_Private_Functions DACEx Private Functions
+ * @{
+ */
+static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
+static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
+static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+/* DAC channel 2 is available on top of DAC channel 1U */
+static void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
+static void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
+static void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F373xC || STM32F378xx */
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+/** @defgroup DACEx_Exported_Functions DACEx Exported Functions
+ * @{
+ */
+
+/** @defgroup DACEx_Exported_Functions_Group3 DACEx Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Set the specified data holding register value for DAC channel.
+ (+) Set the specified data holding register value for dual DAC channel
+ (when DAC channel 2 is present in DAC 1U)
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Set the specified data holding register value for DAC channel.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel The selected DAC channel.
+ * @param Alignment Specifies the data alignment for DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
+ * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
+ * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
+ * @param Data Data to be loaded in the selected data holding register.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
+{
+ __IO uint32_t tmp = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(Channel));
+ assert_param(IS_DAC_ALIGN(Alignment));
+ assert_param(IS_DAC_DATA(Data));
+
+ tmp = (uint32_t) (hdac->Instance);
+
+/* DAC 1 has 1 or 2 channels - no DAC2 */
+/* DAC 1 has 2 channels 1U & 2U - DAC 2 has one channel 1U */
+
+ if(Channel == DAC_CHANNEL_1)
+ {
+ tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
+ }
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+ else /* channel = DAC_CHANNEL_2 */
+ {
+ tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
+ }
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F373xC || STM32F378xx */
+
+ /* Set the DAC channel1 selected data holding register */
+ *(__IO uint32_t *) tmp = Data;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+/* DAC channel 2 is present in DAC 1U */
+/**
+ * @brief Set the specified data holding register value for dual DAC channel.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Alignment Specifies the data alignment for dual channel DAC.
+ * This parameter can be one of the following values:
+ * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
+ * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
+ * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
+ * @param Data2: Data for DAC Channel2 to be loaded in the selected data holding register.
+ * @param Data1: Data for DAC Channel1 to be loaded in the selected data holding register.
+ * @note In dual mode, a unique register access is required to write in both
+ * DAC channels at the same time.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
+{
+ uint32_t data = 0U, tmp = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_ALIGN(Alignment));
+ assert_param(IS_DAC_DATA(Data1));
+ assert_param(IS_DAC_DATA(Data2));
+
+ /* Calculate and set dual DAC data holding register value */
+ if (Alignment == DAC_ALIGN_8B_R)
+ {
+ data = ((uint32_t)Data2 << 8U) | Data1;
+ }
+ else
+ {
+ data = ((uint32_t)Data2 << 16U) | Data1;
+ }
+
+ tmp = (uint32_t) (hdac->Instance);
+ tmp += DAC_DHR12RD_ALIGNMENT(Alignment);
+
+ /* Set the dual DAC selected data holding register */
+ *(__IO uint32_t *)tmp = data;
+
+ /* Return function status */
+ return HAL_OK;
+}
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F373xC || STM32F378xx */
+
+/**
+ * @}
+ */
+
+/** @defgroup DACEx_Exported_Functions_Group2 DACEx Input and Output operation functions
+ * @brief IO operation functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Start conversion.
+ (+) Start conversion and enable DMA transfer.
+ (+) Get result of conversion.
+ (+) Handle DAC IRQ's.
+ (+) Generate triangular-wave
+ (+) Generate noise-wave
+ (+) Callback functions for DAC1 Channel2 (when supported)
+@endverbatim
+ * @{
+ */
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+
+/* DAC 1 has 2 channels 1U & 2U - DAC 2 has one channel 1U */
+/**
+ * @brief Enables DAC and starts conversion of channel.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC1 Channel1 or DAC2 Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC1 Channel2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel));
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* Enable the Peripheral */
+ __HAL_DAC_ENABLE(hdac, Channel);
+
+ if(Channel == DAC_CHANNEL_1)
+ {
+ /* Check if software trigger enabled */
+ if((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == (DAC_CR_TEN1 | DAC_CR_TSEL1))
+ {
+ /* Enable the selected DAC software conversion */
+ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
+ }
+ }
+ else
+ {
+ /* Check if software trigger enabled */
+ if((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_CR_TEN2 | DAC_CR_TSEL2))
+ {
+ /* Enable the selected DAC software conversion */
+ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
+ }
+ }
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdac);
+
+ /* Return function status */
+ return HAL_OK;
+}
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/* DAC 1 has 1 channels 1U */
+/**
+ * @brief Enables DAC and starts conversion of channel.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC1 Channel1 selected
+ * @retval HAL status
+ */
+
+HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel));
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* Enable the Peripheral */
+ __HAL_DAC_ENABLE(hdac, Channel);
+
+ /* Check if software trigger enabled */
+ if((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == (DAC_CR_TEN1 | DAC_CR_TSEL1))
+ {
+ /* Enable the selected DAC software conversion */
+ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
+ }
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdac);
+
+ /* Return function status */
+ return HAL_OK;
+}
+#endif /* STM32F302xE || */
+ /* STM32F302xC || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+/* DAC 1 has 2 channels 1U & 2U - DAC 2 has one channel 1U */
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+/* DAC 1 has 2 channels 1U & 2U */
+/**
+ * @brief Enables DAC and starts conversion of channel.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC1 Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC1 Channel2 selected
+ * @param pData The destination peripheral Buffer address.
+ * @param Length The length of data to be transferred from memory to DAC peripheral
+ * @param Alignment Specifies the data alignment for DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
+ * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
+ * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
+{
+ uint32_t tmpreg = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel));
+ assert_param(IS_DAC_ALIGN(Alignment));
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ if(Channel == DAC_CHANNEL_1)
+ {
+ /* Set the DMA transfer complete callback for channel1 */
+ hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
+
+ /* Set the DMA half transfer complete callback for channel1 */
+ hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
+
+ /* Set the DMA error callback for channel1 */
+ hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
+
+ /* Enable the selected DAC channel1 DMA request */
+ SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
+
+ /* Case of use of channel 1U */
+ switch(Alignment)
+ {
+ case DAC_ALIGN_12B_R:
+ /* Get DHR12R1 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
+ break;
+ case DAC_ALIGN_12B_L:
+ /* Get DHR12L1 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
+ break;
+ case DAC_ALIGN_8B_R:
+ /* Get DHR8R1 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
+ break;
+ default:
+ break;
+ }
+ }
+ else
+ {
+ /* Set the DMA transfer complete callback for channel2 */
+ hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
+
+ /* Set the DMA half transfer complete callback for channel2 */
+ hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
+
+ /* Set the DMA error callback for channel2 */
+ hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
+
+ /* Enable the selected DAC channel2 DMA request */
+ SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
+
+ /* Case of use of channel 2U */
+ switch(Alignment)
+ {
+ case DAC_ALIGN_12B_R:
+ /* Get DHR12R2 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
+ break;
+ case DAC_ALIGN_12B_L:
+ /* Get DHR12L2 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
+ break;
+ case DAC_ALIGN_8B_R:
+ /* Get DHR8R2 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
+ break;
+ default:
+ break;
+ }
+ }
+
+ /* Enable the DMA Channel */
+ if(Channel == DAC_CHANNEL_1)
+ {
+ /* Enable the DAC DMA underrun interrupt */
+ __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
+
+ /* Enable the DMA Channel */
+ HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
+ }
+ else
+ {
+ /* Enable the DAC DMA underrun interrupt */
+ __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
+
+ /* Enable the DMA Channel */
+ HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdac);
+
+ /* Enable the Peripheral */
+ __HAL_DAC_ENABLE(hdac, Channel);
+
+ /* Return function status */
+ return HAL_OK;
+}
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/* DAC 1 has 1 channel (channel 1U) */
+/**
+ * @brief Enables DAC and starts conversion of channel.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC1 Channel1 selected
+ * @param pData The destination peripheral Buffer address.
+ * @param Length The length of data to be transferred from memory to DAC peripheral
+ * @param Alignment Specifies the data alignment for DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
+ * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
+ * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
+{
+ uint32_t tmpreg = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel));
+ assert_param(IS_DAC_ALIGN(Alignment));
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* Set the DMA transfer complete callback for channel1 */
+ hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
+
+ /* Set the DMA half transfer complete callback for channel1 */
+ hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
+
+ /* Set the DMA error callback for channel1 */
+ hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
+
+ /* Enable the selected DAC channel1 DMA request */
+ SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
+
+ /* Case of use of channel 1U */
+ switch(Alignment)
+ {
+ case DAC_ALIGN_12B_R:
+ /* Get DHR12R1 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
+ break;
+ case DAC_ALIGN_12B_L:
+ /* Get DHR12L1 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
+ break;
+ case DAC_ALIGN_8B_R:
+ /* Get DHR8R1 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
+ break;
+ default:
+ break;
+ }
+
+ /* Enable the DMA Channel */
+ /* Enable the DAC DMA underrun interrupt */
+ __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
+
+ /* Enable the DMA Channel */
+ HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdac);
+
+ /* Enable the Peripheral */
+ __HAL_DAC_ENABLE(hdac, Channel);
+
+ /* Return function status */
+ return HAL_OK;
+}
+#endif /* STM32F302xE || */
+ /* STM32F302xC || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+/* DAC 1 has 2 channels 1U & 2U - DAC 2 has one channel 1U */
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+/* DAC 1 has 2 channels 1U & 2U */
+/**
+ * @brief Returns the last data output value of the selected DAC channel.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC1 Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC1 Channel2 selected
+ * @retval The selected DAC channel data output value.
+ */
+uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel));
+
+ /* Returns the DAC channel data output register value */
+ if(Channel == DAC_CHANNEL_1)
+ {
+ return hdac->Instance->DOR1;
+ }
+ else /* channel = DAC_CHANNEL_2 */
+ {
+ return hdac->Instance->DOR2;
+ }
+}
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/* DAC 1 has 1 channel (channel 1U) */
+/**
+ * @brief Returns the last data output value of the selected DAC channel.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param channel The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC1 Channel1 selected
+ * @retval The selected DAC channel data output value.
+ */
+uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel));
+
+ /* Returns the DAC channel data output register value */
+ return hdac->Instance->DOR1;
+}
+#endif /* STM32F302xE || */
+ /* STM32F302xC || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+/**
+ * @brief Return the last data output value of the selected DAC channel.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval The selected DAC channel data output value.
+ */
+uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
+{
+ uint32_t tmp = 0U;
+
+ tmp |= hdac->Instance->DOR1;
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+/* DAC channel 2 is present in DAC 1U */
+ tmp |= hdac->Instance->DOR2 << 16U;
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F373xC || STM32F378xx */
+
+ /* Returns the DAC channel data output register value */
+ return tmp;
+}
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+/* DAC channel 2 is available on top of DAC channel 1U */
+/**
+ * @brief Handles DAC interrupt request
+ * This function uses the interruption of DMA
+ * underrun.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+void HAL_DAC_IRQHandler(struct __DAC_HandleTypeDef* hdac)
+{
+ if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1))
+ {
+ /* Check underrun flag of DAC channel 1U */
+ if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
+ {
+ /* Change DAC state to error state */
+ hdac->State = HAL_DAC_STATE_ERROR;
+
+ /* Set DAC error code to chanel1 DMA underrun error */
+ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1);
+
+ /* Clear the underrun flag */
+ __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
+
+ /* Disable the selected DAC channel1 DMA request */
+ CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
+
+ /* Error callback */
+ HAL_DAC_DMAUnderrunCallbackCh1(hdac);
+ }
+ }
+
+ if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2))
+ {
+ /* Check underrun flag of DAC channel 1U */
+ if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
+ {
+ /* Change DAC state to error state */
+ hdac->State = HAL_DAC_STATE_ERROR;
+
+ /* Set DAC error code to channel2 DMA underrun error */
+ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2);
+
+ /* Clear the underrun flag */
+ __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2);
+
+ /* Disable the selected DAC channel1 DMA request */
+ CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
+
+ /* Error callback */
+ HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
+ }
+ }
+}
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/* DAC channel 2 is NOT available. Only DAC channel 1 is available */
+/**
+ * @brief Handles DAC interrupt request
+ * This function uses the interruption of DMA
+ * underrun.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+void HAL_DAC_IRQHandler(struct __DAC_HandleTypeDef* hdac)
+{
+ if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1))
+ {
+ /* Check underrun flag of DAC channel 1U */
+ if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
+ {
+ /* Change DAC state to error state */
+ hdac->State = HAL_DAC_STATE_ERROR;
+
+ /* Set DAC error code to chanel1 DMA underrun error */
+ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1);
+
+ /* Clear the underrun flag */
+ __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
+
+ /* Disable the selected DAC channel1 DMA request */
+ CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
+
+ /* Error callback */
+ HAL_DAC_DMAUnderrunCallbackCh1(hdac);
+ }
+ }
+}
+#endif /* STM32F302xE || */
+ /* STM32F302xC || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+/**
+ * @brief Configures the selected DAC channel.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param sConfig DAC configuration structure.
+ * @param Channel The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC1 Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC1 Channel2 selected
+ * @arg DAC_CHANNEL_1: DAC2 Channel1 selected
+ * @retval HAL status
+ */
+
+HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
+{
+ uint32_t tmpreg1 = 0U, tmpreg2 = 0U;
+
+ /* Check the DAC parameters */
+ assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
+
+#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+ if ((hdac->Instance == DAC1) && (Channel == DAC_CHANNEL_1))
+ {
+ /* Output Buffer (BOFF1) control */
+ assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
+ }
+ else /* DAC1 channel 2U & DAC2 channel 1U */
+ {
+ /* Output Switch (OUTEN) control */
+ assert_param(IS_DAC_OUTPUT_SWITCH_STATE(sConfig->DAC_OutputSwitch));
+ }
+#else
+ assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
+#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ assert_param(IS_DAC_CHANNEL(Channel));
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* Get the DAC CR value */
+ tmpreg1 = hdac->Instance->CR;
+
+ /* Clear BOFFx-OUTENx, TENx, TSELx, WAVEx and MAMPx bits */
+
+ /* Configure for the selected DAC channel: buffer output or switch output, trigger */
+ /* Set TSELx and TENx bits according to DAC_Trigger value */
+ /* Set BOFFx bit according to DAC_OutputBuffer value OR */
+ /* Set OUTEN bit according to DAC_OutputSwitch value */
+#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+ if ((hdac->Instance == DAC1) && (Channel == DAC_CHANNEL_1))
+ {
+ /* Output Buffer (BOFF1) control */
+ tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel);
+ tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);
+ }
+ else /* DAC1 channel 2U & DAC2 channel 1U */
+ {
+ /* Output Switch (OUTEN) control */
+ tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_OUTEN1)) << Channel);
+ tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputSwitch);
+ }
+#else
+ tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel);
+ tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);
+#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+
+ /* Calculate CR register value depending on DAC_Channel */
+ tmpreg1 |= tmpreg2 << Channel;
+ /* Write to DAC CR */
+ hdac->Instance->CR = tmpreg1;
+
+ /* Disable wave generation */
+ hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdac);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables or disables the selected DAC channel wave generation.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC1 Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC1 Channel2 selected
+ * @param Amplitude Select max triangle amplitude.
+ * This parameter can be one of the following values:
+ * @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
+ * @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
+ * @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
+ * @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
+ * @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
+ * @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
+ * @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
+ * @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
+ * @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
+ * @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
+ * @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
+ * @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
+ * @note Wave generation is not available in DAC2.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(Channel));
+ assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* Enable the selected wave generation for the selected DAC channel */
+ MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<<Channel, (DAC_CR_WAVE1_1 | Amplitude) << Channel);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdac);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables or disables the selected DAC channel wave generation.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC1 Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC1 Channel2 selected
+ * @param Amplitude Unmask DAC channel LFSR for noise wave generation.
+ * This parameter can be one of the following values:
+ * @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(Channel));
+ assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* Enable the selected wave generation for the selected DAC channel */
+ MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<<Channel, (DAC_CR_WAVE1_0 | Amplitude) << Channel);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdac);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+/* DAC channel 2 is available on top of DAC channel 1U */
+/**
+ * @brief Conversion complete callback in non blocking mode for Channel2
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Conversion half DMA transfer callback in non blocking mode for Channel2
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Error DAC callback for Channel2.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DMA underrun DAC callback for channel2.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file
+ */
+}
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F373xC || STM32F378xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DACEx_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief DMA conversion complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
+{
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ HAL_DAC_ConvCpltCallbackCh1(hdac);
+
+ hdac->State= HAL_DAC_STATE_READY;
+}
+
+/**
+ * @brief DMA half transfer complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
+{
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ /* Conversion complete callback */
+ HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
+}
+
+/**
+ * @brief DMA error callback
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
+{
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Set DAC error code to DMA error */
+ hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
+
+ HAL_DAC_ErrorCallbackCh1(hdac);
+
+ hdac->State= HAL_DAC_STATE_READY;
+}
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+/* DAC channel 2 is available on top of DAC channel 1U */
+/**
+ * @brief DMA conversion complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
+{
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ HAL_DACEx_ConvCpltCallbackCh2(hdac);
+
+ hdac->State= HAL_DAC_STATE_READY;
+}
+
+/**
+ * @brief DMA half transfer complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
+{
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ /* Conversion complete callback */
+ HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
+}
+
+/**
+ * @brief DMA error callback
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
+{
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Set DAC error code to DMA error */
+ hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
+
+ HAL_DACEx_ErrorCallbackCh2(hdac);
+
+ hdac->State= HAL_DAC_STATE_READY;
+}
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F373xC || STM32F378xx */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_DAC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_dma.c b/Src/stm32f3xx_hal_dma.c
new file mode 100644
index 0000000..dc9e9a7
--- /dev/null
+++ b/Src/stm32f3xx_hal_dma.c
@@ -0,0 +1,904 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_dma.c
+ * @author MCD Application Team
+ * @brief DMA HAL module driver.
+ *
+ * This file provides firmware functions to manage the following
+ * functionalities of the Direct Memory Access (DMA) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral State and errors functions
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Enable and configure the peripheral to be connected to the DMA Channel
+ (except for internal SRAM / FLASH memories: no initialization is
+ necessary). Please refer to Reference manual for connection between peripherals
+ and DMA requests .
+
+ (#) For a given Channel, program the required configuration through the following parameters:
+ Transfer Direction, Source and Destination data formats,
+ Circular or Normal mode, Channel Priority level, Source and Destination Increment mode,
+ using HAL_DMA_Init() function.
+
+ (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
+ detection.
+
+ (#) Use HAL_DMA_Abort() function to abort the current transfer
+
+ -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
+ address and destination address and the Length of data to be transferred
+ (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
+ case a fixed Timeout can be configured by User depending from his application.
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
+ (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
+ (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
+ Source address and destination address and the Length of data to be transferred.
+ In this case the DMA interrupt is configured
+ (+) Use HAL_DMA_Channel_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
+ (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
+ add his own function by customization of function pointer XferCpltCallback and
+ XferErrorCallback (i.e a member of DMA handle structure).
+
+ *** DMA HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in DMA HAL driver.
+
+ [..]
+ (@) You can refer to the DMA HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup DMA DMA
+ * @brief DMA HAL module driver
+ * @{
+ */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup DMA_Private_Functions DMA Private Functions
+ * @{
+ */
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Functions DMA Exported Functions
+ * @{
+ */
+
+/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and de-initialization functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..]
+ This section provides functions allowing to initialize the DMA Channel source
+ and destination addresses, incrementation and data sizes, transfer direction,
+ circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
+ [..]
+ The HAL_DMA_Init() function follows the DMA configuration procedures as described in
+ reference manual.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the DMA according to the specified
+ * parameters in the DMA_InitTypeDef and initialize the associated handle.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
+{
+ uint32_t tmp = 0U;
+
+ /* Check the DMA handle allocation */
+ if(NULL == hdma)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+ assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
+ assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
+ assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
+ assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
+ assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
+ assert_param(IS_DMA_MODE(hdma->Init.Mode));
+ assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
+
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_BUSY;
+
+ /* Get the CR register value */
+ tmp = hdma->Instance->CCR;
+
+ /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */
+ tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
+ DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
+ DMA_CCR_DIR));
+
+ /* Prepare the DMA Channel configuration */
+ tmp |= hdma->Init.Direction |
+ hdma->Init.PeriphInc | hdma->Init.MemInc |
+ hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
+ hdma->Init.Mode | hdma->Init.Priority;
+
+ /* Write to DMA Channel CR register */
+ hdma->Instance->CCR = tmp;
+
+ /* Initialize DmaBaseAddress and ChannelIndex parameters used
+ by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
+ DMA_CalcBaseAndBitshift(hdma);
+
+ /* Initialise the error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ /* Initialize the DMA state*/
+ hdma->State = HAL_DMA_STATE_READY;
+
+ /* Allocate lock resource and initialize it */
+ hdma->Lock = HAL_UNLOCKED;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitialize the DMA peripheral
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
+{
+ /* Check the DMA handle allocation */
+ if(NULL == hdma)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+
+ /* Disable the selected DMA Channelx */
+ hdma->Instance->CCR &= ~DMA_CCR_EN;
+
+ /* Reset DMA Channel control register */
+ hdma->Instance->CCR = 0U;
+
+ /* Reset DMA Channel Number of Data to Transfer register */
+ hdma->Instance->CNDTR = 0U;
+
+ /* Reset DMA Channel peripheral address register */
+ hdma->Instance->CPAR = 0U;
+
+ /* Reset DMA Channel memory address register */
+ hdma->Instance->CMAR = 0U;
+
+ /* Get DMA Base Address */
+ DMA_CalcBaseAndBitshift(hdma);
+
+ /* Clear all flags */
+ hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
+
+ /* Clean callbacks */
+ hdma->XferCpltCallback = NULL;
+ hdma->XferHalfCpltCallback = NULL;
+ hdma->XferErrorCallback = NULL;
+ hdma->XferAbortCallback = NULL;
+
+ /* Reset the error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ /* Reset the DMA state */
+ hdma->State = HAL_DMA_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
+ * @brief I/O operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure the source, destination address and data length and Start DMA transfer
+ (+) Configure the source, destination address and data length and
+ Start DMA transfer with interrupt
+ (+) Abort DMA transfer
+ (+) Poll for transfer complete
+ (+) Handle DMA interrupt request
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Start the DMA Transfer.
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @param SrcAddress The source memory Buffer address
+ * @param DstAddress The destination memory Buffer address
+ * @param DataLength The length of data to be transferred from source to destination
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+ /* Process locked */
+ __HAL_LOCK(hdma);
+
+ if(HAL_DMA_STATE_READY == hdma->State)
+ {
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_BUSY;
+
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ /* Disable the peripheral */
+ hdma->Instance->CCR &= ~DMA_CCR_EN;
+
+ /* Configure the source, destination address and the data length */
+ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+ /* Enable the Peripheral */
+ hdma->Instance->CCR |= DMA_CCR_EN;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ /* Remain BUSY */
+ status = HAL_BUSY;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Start the DMA Transfer with interrupt enabled.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @param SrcAddress The source memory Buffer address
+ * @param DstAddress The destination memory Buffer address
+ * @param DataLength The length of data to be transferred from source to destination
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+ /* Process locked */
+ __HAL_LOCK(hdma);
+
+ if(HAL_DMA_STATE_READY == hdma->State)
+ {
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_BUSY;
+
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ /* Disable the peripheral */
+ hdma->Instance->CCR &= ~DMA_CCR_EN;
+
+ /* Configure the source, destination address and the data length */
+ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+ /* Enable the transfer complete, & transfer error interrupts */
+ /* Half transfer interrupt is optional: enable it only if associated callback is available */
+ if(NULL != hdma->XferHalfCpltCallback )
+ {
+ hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
+ }
+ else
+ {
+ hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_TE);
+ hdma->Instance->CCR &= ~DMA_IT_HT;
+ }
+
+ /* Enable the Peripheral */
+ hdma->Instance->CCR |= DMA_CCR_EN;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ /* Remain BUSY */
+ status = HAL_BUSY;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Abort the DMA Transfer.
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
+{
+ /* Disable DMA IT */
+ hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
+
+ /* Disable the channel */
+ hdma->Instance->CCR &= ~DMA_CCR_EN;
+
+ /* Clear all flags */
+ hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex);
+
+ /* Change the DMA state*/
+ hdma->State = HAL_DMA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort the DMA Transfer in Interrupt mode.
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if(HAL_DMA_STATE_BUSY != hdma->State)
+ {
+ /* no transfer ongoing */
+ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+
+ status = HAL_ERROR;
+ }
+ else
+ {
+
+ /* Disable DMA IT */
+ hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
+
+ /* Disable the channel */
+ hdma->Instance->CCR &= ~DMA_CCR_EN;
+
+ /* Clear all flags */
+ hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ /* Call User Abort callback */
+ if(hdma->XferAbortCallback != NULL)
+ {
+ hdma->XferAbortCallback(hdma);
+ }
+ }
+ return status;
+}
+
+/**
+ * @brief Polling for transfer complete.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @param CompleteLevel Specifies the DMA level complete.
+ * @param Timeout Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
+{
+ uint32_t temp;
+ uint32_t tickstart = 0U;
+
+ if(HAL_DMA_STATE_BUSY != hdma->State)
+ {
+ /* no transfer ongoing */
+ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+ __HAL_UNLOCK(hdma);
+ return HAL_ERROR;
+ }
+
+ /* Polling mode not supported in circular mode */
+ if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC))
+ {
+ hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+ return HAL_ERROR;
+ }
+
+ /* Get the level transfer complete flag */
+ if(HAL_DMA_FULL_TRANSFER == CompleteLevel)
+ {
+ /* Transfer Complete flag */
+ temp = DMA_FLAG_TC1 << hdma->ChannelIndex;
+ }
+ else
+ {
+ /* Half Transfer Complete flag */
+ temp = DMA_FLAG_HT1 << hdma->ChannelIndex;
+ }
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(RESET == (hdma->DmaBaseAddress->ISR & temp))
+ {
+ if(RESET != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << hdma->ChannelIndex)))
+ {
+ /* When a DMA transfer error occurs */
+ /* A hardware clear of its EN bits is performed */
+ /* Clear all flags */
+ hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
+
+ /* Update error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_TE;
+
+ /* Change the DMA state */
+ hdma->State= HAL_DMA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_ERROR;
+ }
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ /* Update error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ if(HAL_DMA_FULL_TRANSFER == CompleteLevel)
+ {
+ /* Clear the transfer complete flag */
+ hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex;
+
+ /* The selected Channelx EN bit is cleared (DMA is disabled and
+ all transfers are complete) */
+ hdma->State = HAL_DMA_STATE_READY;
+ }
+ else
+ {
+ /* Clear the half transfer complete flag */
+ hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle DMA interrupt request.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @retval None
+ */
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
+{
+ uint32_t flag_it = hdma->DmaBaseAddress->ISR;
+ uint32_t source_it = hdma->Instance->CCR;
+
+ /* Half Transfer Complete Interrupt management ******************************/
+ if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_HT)))
+ {
+ /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
+ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
+ {
+ /* Disable the half transfer interrupt */
+ hdma->Instance->CCR &= ~DMA_IT_HT;
+ }
+
+ /* Clear the half transfer complete flag */
+ hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex;
+
+ /* DMA peripheral state is not updated in Half Transfer */
+ /* State is updated only in Transfer Complete case */
+
+ if(hdma->XferHalfCpltCallback != NULL)
+ {
+ /* Half transfer callback */
+ hdma->XferHalfCpltCallback(hdma);
+ }
+ }
+
+ /* Transfer Complete Interrupt management ***********************************/
+ else if ((RESET != (flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TC)))
+ {
+ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
+ {
+ /* Disable the transfer complete & transfer error interrupts */
+ /* if the DMA mode is not CIRCULAR */
+ hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_TE);
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_READY;
+ }
+
+ /* Clear the transfer complete flag */
+ hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ if(hdma->XferCpltCallback != NULL)
+ {
+ /* Transfer complete callback */
+ hdma->XferCpltCallback(hdma);
+ }
+ }
+
+ /* Transfer Error Interrupt management ***************************************/
+ else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE)))
+ {
+ /* When a DMA transfer error occurs */
+ /* A hardware clear of its EN bits is performed */
+ /* Then, disable all DMA interrupts */
+ hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
+
+ /* Clear all flags */
+ hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
+
+ /* Update error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_TE;
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ if(hdma->XferErrorCallback != NULL)
+ {
+ /* Transfer error callback */
+ hdma->XferErrorCallback(hdma);
+ }
+ }
+}
+
+/**
+ * @brief Register callbacks
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @param CallbackID User Callback identifer
+ * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
+ * @param pCallback pointer to private callback function which has pointer to
+ * a DMA_HandleTypeDef structure as parameter.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma))
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hdma);
+
+ if(HAL_DMA_STATE_READY == hdma->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DMA_XFER_CPLT_CB_ID:
+ hdma->XferCpltCallback = pCallback;
+ break;
+
+ case HAL_DMA_XFER_HALFCPLT_CB_ID:
+ hdma->XferHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_DMA_XFER_ERROR_CB_ID:
+ hdma->XferErrorCallback = pCallback;
+ break;
+
+ case HAL_DMA_XFER_ABORT_CB_ID:
+ hdma->XferAbortCallback = pCallback;
+ break;
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdma);
+
+ return status;
+}
+
+/**
+ * @brief UnRegister callbacks
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @param CallbackID User Callback identifer
+ * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hdma);
+
+ if(HAL_DMA_STATE_READY == hdma->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DMA_XFER_CPLT_CB_ID:
+ hdma->XferCpltCallback = NULL;
+ break;
+
+ case HAL_DMA_XFER_HALFCPLT_CB_ID:
+ hdma->XferHalfCpltCallback = NULL;
+ break;
+
+ case HAL_DMA_XFER_ERROR_CB_ID:
+ hdma->XferErrorCallback = NULL;
+ break;
+
+ case HAL_DMA_XFER_ABORT_CB_ID:
+ hdma->XferAbortCallback = NULL;
+ break;
+
+ case HAL_DMA_XFER_ALL_CB_ID:
+ hdma->XferCpltCallback = NULL;
+ hdma->XferHalfCpltCallback = NULL;
+ hdma->XferErrorCallback = NULL;
+ hdma->XferAbortCallback = NULL;
+ break;
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdma);
+
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Check the DMA state
+ (+) Get error code
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns the DMA state.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @retval HAL state
+ */
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
+{
+ return hdma->State;
+}
+
+/**
+ * @brief Return the DMA error code
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @retval DMA Error Code
+ */
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
+{
+ return hdma->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Set the DMA Transfer parameters.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @param SrcAddress The source memory Buffer address
+ * @param DstAddress The destination memory Buffer address
+ * @param DataLength The length of data to be transferred from source to destination
+ * @retval HAL status
+ */
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+ /* Clear all flags */
+ hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex);
+
+ /* Configure DMA Channel data length */
+ hdma->Instance->CNDTR = DataLength;
+
+ /* Peripheral to Memory */
+ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+ {
+ /* Configure DMA Channel destination address */
+ hdma->Instance->CPAR = DstAddress;
+
+ /* Configure DMA Channel source address */
+ hdma->Instance->CMAR = SrcAddress;
+ }
+ /* Memory to Peripheral */
+ else
+ {
+ /* Configure DMA Channel source address */
+ hdma->Instance->CPAR = SrcAddress;
+
+ /* Configure DMA Channel destination address */
+ hdma->Instance->CMAR = DstAddress;
+ }
+}
+
+/**
+ * @brief Set the DMA base address and channel index depending on DMA instance
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @retval None
+ */
+static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
+{
+#if defined (DMA2)
+ /* calculation of the channel index */
+ if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
+ {
+ /* DMA1 */
+ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
+ hdma->DmaBaseAddress = DMA1;
+ }
+ else
+ {
+ /* DMA2 */
+ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;
+ hdma->DmaBaseAddress = DMA2;
+ }
+#else
+ /* calculation of the channel index */
+ /* DMA1 */
+ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
+ hdma->DmaBaseAddress = DMA1;
+#endif
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_flash.c b/Src/stm32f3xx_hal_flash.c
new file mode 100644
index 0000000..791dc69
--- /dev/null
+++ b/Src/stm32f3xx_hal_flash.c
@@ -0,0 +1,711 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_flash.c
+ * @author MCD Application Team
+ * @brief FLASH HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the internal FLASH memory:
+ * + Program operations functions
+ * + Memory Control functions
+ * + Peripheral State functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### FLASH peripheral features #####
+ ==============================================================================
+ [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
+ to the Flash memory. It implements the erase and program Flash memory operations
+ and the read and write protection mechanisms.
+
+ [..] The Flash memory interface accelerates code execution with a system of instruction
+ prefetch.
+
+ [..] The FLASH main features are:
+ (+) Flash memory read operations
+ (+) Flash memory program/erase operations
+ (+) Read / write protections
+ (+) Prefetch on I-Code
+ (+) Option Bytes programming
+
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ This driver provides functions and macros to configure and program the FLASH
+ memory of all STM32F3xx devices.
+
+ (#) FLASH Memory I/O Programming functions: this group includes all needed
+ functions to erase and program the main memory:
+ (++) Lock and Unlock the FLASH interface
+ (++) Erase function: Erase page, erase all pages
+ (++) Program functions: half word, word and doubleword
+ (#) FLASH Option Bytes Programming functions: this group includes all needed
+ functions to manage the Option Bytes:
+ (++) Lock and Unlock the Option Bytes
+ (++) Set/Reset the write protection
+ (++) Set the Read protection Level
+ (++) Program the user Option Bytes
+ (++) Launch the Option Bytes loader
+ (++) Erase Option Bytes
+ (++) Program the data Option Bytes
+ (++) Get the Write protection.
+ (++) Get the user option bytes.
+
+ (#) Interrupts and flags management functions : this group
+ includes all needed functions to:
+ (++) Handle FLASH interrupts
+ (++) Wait for last FLASH operation according to its status
+ (++) Get error flag status
+
+ [..] In addition to these function, this driver includes a set of macros allowing
+ to handle the following operations:
+
+ (+) Set/Get the latency
+ (+) Enable/Disable the prefetch buffer
+ (+) Enable/Disable the half cycle access
+ (+) Enable/Disable the FLASH interrupts
+ (+) Monitor the FLASH flags status
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+
+/** @defgroup FLASH FLASH
+ * @brief FLASH HAL module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup FLASH_Private_Constants FLASH Private Constants
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private macro ---------------------------- ---------------------------------*/
+/** @defgroup FLASH_Private_Macros FLASH Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup FLASH_Private_Variables FLASH Private Variables
+ * @{
+ */
+/* Variables used for Erase pages under interruption*/
+FLASH_ProcessTypeDef pFlash;
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup FLASH_Private_Functions FLASH Private Functions
+ * @{
+ */
+static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data);
+static void FLASH_SetErrorCode(void);
+extern void FLASH_PageErase(uint32_t PageAddress);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
+ * @{
+ */
+
+/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
+ * @brief Programming operation functions
+ *
+@verbatim
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Program halfword, word or double word at a specified address
+ * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
+ * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface
+ *
+ * @note If an erase and a program operations are requested simultaneously,
+ * the erase operation is performed before the program one.
+ *
+ * @note FLASH should be previously erased before new programming (only exception to this
+ * is when 0x0000 is programmed)
+ *
+ * @param TypeProgram Indicate the way to program at a specified address.
+ * This parameter can be a value of @ref FLASH_Type_Program
+ * @param Address Specifie the address to be programmed.
+ * @param Data Specifie the data to be programmed
+ *
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+ uint8_t index = 0U;
+ uint8_t nbiterations = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
+ {
+ /* Program halfword (16-bit) at a specified address. */
+ nbiterations = 1U;
+ }
+ else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
+ {
+ /* Program word (32-bit = 2*16-bit) at a specified address. */
+ nbiterations = 2U;
+ }
+ else
+ {
+ /* Program double word (64-bit = 4*16-bit) at a specified address. */
+ nbiterations = 4U;
+ }
+
+ for (index = 0U; index < nbiterations; index++)
+ {
+ FLASH_Program_HalfWord((Address + (2U*index)), (uint16_t)(Data >> (16U*index)));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
+
+ /* If the program operation is completed, disable the PG Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
+ /* In case of error, stop programming procedure */
+ if (status != HAL_OK)
+ {
+ break;
+ }
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+
+ return status;
+}
+
+/**
+ * @brief Program halfword, word or double word at a specified address with interrupt enabled.
+ * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
+ * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface
+ *
+ * @note If an erase and a program operations are requested simultaneously,
+ * the erase operation is performed before the program one.
+ *
+ * @param TypeProgram Indicate the way to program at a specified address.
+ * This parameter can be a value of @ref FLASH_Type_Program
+ * @param Address Specifie the address to be programmed.
+ * @param Data Specifie the data to be programmed
+ *
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
+
+ /* Enable End of FLASH Operation and Error source interrupts */
+ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
+
+ pFlash.Address = Address;
+ pFlash.Data = Data;
+
+ if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
+ {
+ pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMHALFWORD;
+ /* Program halfword (16-bit) at a specified address. */
+ pFlash.DataRemaining = 1U;
+ }
+ else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
+ {
+ pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMWORD;
+ /* Program word (32-bit : 2*16-bit) at a specified address. */
+ pFlash.DataRemaining = 2U;
+ }
+ else
+ {
+ pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMDOUBLEWORD;
+ /* Program double word (64-bit : 4*16-bit) at a specified address. */
+ pFlash.DataRemaining = 4U;
+ }
+
+ /* Program halfword (16-bit) at a specified address. */
+ FLASH_Program_HalfWord(Address, (uint16_t)Data);
+
+ return status;
+}
+
+/**
+ * @brief This function handles FLASH interrupt request.
+ * @retval None
+ */
+void HAL_FLASH_IRQHandler(void)
+{
+ uint32_t addresstmp = 0U;
+
+ /* Check FLASH operation error flags */
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
+ {
+ /* Return the faulty address */
+ addresstmp = pFlash.Address;
+ /* Reset address */
+ pFlash.Address = 0xFFFFFFFFU;
+
+ /* Save the Error code */
+ FLASH_SetErrorCode();
+
+ /* FLASH error interrupt user callback */
+ HAL_FLASH_OperationErrorCallback(addresstmp);
+
+ /* Stop the procedure ongoing */
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ }
+
+ /* Check FLASH End of Operation flag */
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
+ {
+ /* Clear FLASH End of Operation pending bit */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+
+ /* Process can continue only if no error detected */
+ if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
+ {
+ if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE)
+ {
+ /* Nb of pages to erased can be decreased */
+ pFlash.DataRemaining--;
+
+ /* Check if there are still pages to erase */
+ if(pFlash.DataRemaining != 0U)
+ {
+ addresstmp = pFlash.Address;
+ /*Indicate user which sector has been erased */
+ HAL_FLASH_EndOfOperationCallback(addresstmp);
+
+ /*Increment sector number*/
+ addresstmp = pFlash.Address + FLASH_PAGE_SIZE;
+ pFlash.Address = addresstmp;
+
+ /* If the erase operation is completed, disable the PER Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
+
+ FLASH_PageErase(addresstmp);
+ }
+ else
+ {
+ /* No more pages to Erase, user callback can be called. */
+ /* Reset Sector and stop Erase pages procedure */
+ pFlash.Address = addresstmp = 0xFFFFFFFFU;
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ /* FLASH EOP interrupt user callback */
+ HAL_FLASH_EndOfOperationCallback(addresstmp);
+ }
+ }
+ else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
+ {
+ /* Operation is completed, disable the MER Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
+
+ /* MassErase ended. Return the selected bank */
+ /* FLASH EOP interrupt user callback */
+ HAL_FLASH_EndOfOperationCallback(0U);
+
+ /* Stop Mass Erase procedure*/
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ }
+ else
+ {
+ /* Nb of 16-bit data to program can be decreased */
+ pFlash.DataRemaining--;
+
+ /* Check if there are still 16-bit data to program */
+ if(pFlash.DataRemaining != 0U)
+ {
+ /* Increment address to 16-bit */
+ pFlash.Address += 2U;
+ addresstmp = pFlash.Address;
+
+ /* Shift to have next 16-bit data */
+ pFlash.Data = (pFlash.Data >> 16U);
+
+ /* Operation is completed, disable the PG Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
+
+ /*Program halfword (16-bit) at a specified address.*/
+ FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data);
+ }
+ else
+ {
+ /* Program ended. Return the selected address */
+ /* FLASH EOP interrupt user callback */
+ if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD)
+ {
+ HAL_FLASH_EndOfOperationCallback(pFlash.Address);
+ }
+ else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD)
+ {
+ HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2U);
+ }
+ else
+ {
+ HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6U);
+ }
+
+ /* Reset Address and stop Program procedure */
+ pFlash.Address = 0xFFFFFFFFU;
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ }
+ }
+ }
+ }
+
+
+ if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
+ {
+ /* Operation is completed, disable the PG, PER and MER Bits */
+ CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER));
+
+ /* Disable End of FLASH Operation and Error source interrupts */
+ __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+ }
+}
+
+/**
+ * @brief FLASH end of operation interrupt callback
+ * @param ReturnValue The value saved in this parameter depends on the ongoing procedure
+ * - Mass Erase: No return value expected
+ * - Pages Erase: Address of the page which has been erased
+ * (if 0xFFFFFFFF, it means that all the selected pages have been erased)
+ * - Program: Address which was selected for data program
+ * @retval none
+ */
+__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(ReturnValue);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief FLASH operation error interrupt callback
+ * @param ReturnValue The value saved in this parameter depends on the ongoing procedure
+ * - Mass Erase: No return value expected
+ * - Pages Erase: Address of the page which returned an error
+ * - Program: Address which was selected for data program
+ * @retval none
+ */
+__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(ReturnValue);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FLASH_OperationErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
+ * @brief management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the FLASH
+ memory operations.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Unlock the FLASH control register access
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_Unlock(void)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
+ {
+ /* Authorize the FLASH Registers access */
+ WRITE_REG(FLASH->KEYR, FLASH_KEY1);
+ WRITE_REG(FLASH->KEYR, FLASH_KEY2);
+
+ /* Verify Flash is unlocked */
+ if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
+ {
+ status = HAL_ERROR;
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief Locks the FLASH control register access
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_Lock(void)
+{
+ /* Set the LOCK Bit to lock the FLASH Registers access */
+ SET_BIT(FLASH->CR, FLASH_CR_LOCK);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Unlock the FLASH Option Control Registers access.
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
+{
+ if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_OPTWRE))
+ {
+ /* Authorizes the Option Byte register programming */
+ WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);
+ WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Lock the FLASH Option Control Registers access.
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
+{
+ /* Clear the OPTWRE Bit to lock the FLASH Option Byte Registers access */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTWRE);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Launch the option byte loading.
+ * @note This function will reset automatically the MCU.
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
+{
+ /* Set the OBL_Launch bit to launch the option byte loading */
+ SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH);
+
+ /* Wait for last operation to be completed */
+ return(FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Exported_Functions_Group3 Peripheral errors functions
+ * @brief Peripheral errors functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection permit to get in run-time errors of the FLASH peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Get the specific FLASH error flag.
+ * @retval FLASH_ErrorCode The returned value can be:
+ * @ref FLASH_Error_Codes
+ */
+uint32_t HAL_FLASH_GetError(void)
+{
+ return pFlash.ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Program a half-word (16-bit) at a specified address.
+ * @param Address specify the address to be programmed.
+ * @param Data specify the data to be programmed.
+ * @retval None
+ */
+static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
+{
+ /* Clean the error context */
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+ /* Proceed to program the new data */
+ SET_BIT(FLASH->CR, FLASH_CR_PG);
+
+ /* Write data in the address */
+ *(__IO uint16_t*)Address = Data;
+}
+
+/**
+ * @brief Wait for a FLASH operation to complete.
+ * @param Timeout maximum flash operation timeout
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
+{
+ /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
+ Even if the FLASH operation fails, the BUSY flag will be reset and an error
+ flag will be set */
+
+ uint32_t tickstart = HAL_GetTick();
+
+ while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
+ {
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Check FLASH End of Operation flag */
+ if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
+ {
+ /* Clear FLASH End of Operation pending bit */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+ }
+
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||
+ __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
+ {
+ /*Save the error code*/
+ FLASH_SetErrorCode();
+ return HAL_ERROR;
+ }
+
+ /* There is no error flag set */
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Set the specific FLASH error flag.
+ * @retval None
+ */
+static void FLASH_SetErrorCode(void)
+{
+ uint32_t flags = 0U;
+
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
+ {
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
+ flags |= FLASH_FLAG_WRPERR;
+ }
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
+ {
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG;
+ flags |= FLASH_FLAG_PGERR;
+ }
+ /* Clear FLASH error pending bits */
+ __HAL_FLASH_CLEAR_FLAG(flags);
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_flash_ex.c b/Src/stm32f3xx_hal_flash_ex.c
new file mode 100644
index 0000000..f0a4284
--- /dev/null
+++ b/Src/stm32f3xx_hal_flash_ex.c
@@ -0,0 +1,1005 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_flash_ex.c
+ * @author MCD Application Team
+ * @brief Extended FLASH HAL module driver.
+ *
+ * This file provides firmware functions to manage the following
+ * functionalities of the FLASH peripheral:
+ * + Extended Initialization/de-initialization functions
+ * + Extended I/O operation functions
+ * + Extended Peripheral Control functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### Flash peripheral extended features #####
+ ==============================================================================
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..] This driver provides functions to configure and program the FLASH memory
+ of all STM32F3xxx devices. It includes
+
+ (++) Set/Reset the write protection
+ (++) Program the user Option Bytes
+ (++) Get the Read protection Level
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+#ifdef HAL_FLASH_MODULE_ENABLED
+
+/** @addtogroup FLASH
+ * @{
+ */
+/** @addtogroup FLASH_Private_Variables
+ * @{
+ */
+/* Variables used for Erase pages under interruption*/
+extern FLASH_ProcessTypeDef pFlash;
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx FLASHEx
+ * @brief FLASH HAL Extension module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants
+ * @{
+ */
+#define FLASH_POSITION_IWDGSW_BIT (uint32_t)POSITION_VAL(FLASH_OBR_IWDG_SW)
+#define FLASH_POSITION_OB_USERDATA0_BIT (uint32_t)POSITION_VAL(FLASH_OBR_DATA0)
+#define FLASH_POSITION_OB_USERDATA1_BIT (uint32_t)POSITION_VAL(FLASH_OBR_DATA1)
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
+ * @{
+ */
+/* Erase operations */
+static void FLASH_MassErase(void);
+void FLASH_PageErase(uint32_t PageAddress);
+
+/* Option bytes control */
+static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage);
+static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage);
+static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel);
+static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig);
+static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data);
+static uint32_t FLASH_OB_GetWRP(void);
+static uint32_t FLASH_OB_GetRDP(void);
+static uint8_t FLASH_OB_GetUser(void);
+
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
+ * @{
+ */
+
+/** @defgroup FLASHEx_Exported_Functions_Group1 FLASHEx Memory Erasing functions
+ * @brief FLASH Memory Erasing functions
+ *
+@verbatim
+ ==============================================================================
+ ##### FLASH Erasing Programming functions #####
+ ==============================================================================
+
+ [..] The FLASH Memory Erasing functions, includes the following functions:
+ (+) @ref HAL_FLASHEx_Erase: return only when erase has been done
+ (+) @ref HAL_FLASHEx_Erase_IT: end of erase is done when @ref HAL_FLASH_EndOfOperationCallback
+ is called with parameter 0xFFFFFFFF
+
+ [..] Any operation of erase should follow these steps:
+ (#) Call the @ref HAL_FLASH_Unlock() function to enable the flash control register and
+ program memory access.
+ (#) Call the desired function to erase page.
+ (#) Call the @ref HAL_FLASH_Lock() to disable the flash program memory access
+ (recommended to protect the FLASH memory against possible unwanted operation).
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Perform a mass erase or erase the specified FLASH memory pages
+ * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function
+ * must be called before.
+ * Call the @ref HAL_FLASH_Lock() to disable the flash memory access
+ * (recommended to protect the FLASH memory against possible unwanted operation)
+ * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
+ * contains the configuration information for the erasing.
+ *
+ * @param[out] PageError pointer to variable that
+ * contains the configuration information on faulty page in case of error
+ * (0xFFFFFFFF means that all the pages have been correctly erased)
+ *
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+ uint32_t address = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
+
+ if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
+ {
+ /* Mass Erase requested for Bank1 */
+ /* Wait for last operation to be completed */
+ if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
+ {
+ /*Mass erase to be done*/
+ FLASH_MassErase();
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ /* If the erase operation is completed, disable the MER Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
+ }
+ }
+ else
+ {
+ /* Page Erase is requested */
+ /* Check the parameters */
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
+ assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages));
+
+ /* Page Erase requested on address located on bank1 */
+ /* Wait for last operation to be completed */
+ if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
+ {
+ /*Initialization of PageError variable*/
+ *PageError = 0xFFFFFFFFU;
+
+ /* Erase page by page to be done*/
+ for(address = pEraseInit->PageAddress;
+ address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress);
+ address += FLASH_PAGE_SIZE)
+ {
+ FLASH_PageErase(address);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ /* If the erase operation is completed, disable the PER Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
+
+ if (status != HAL_OK)
+ {
+ /* In case of error, stop erase procedure and return the faulty address */
+ *PageError = address;
+ break;
+ }
+ }
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+
+ return status;
+}
+
+/**
+ * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled
+ * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function
+ * must be called before.
+ * Call the @ref HAL_FLASH_Lock() to disable the flash memory access
+ * (recommended to protect the FLASH memory against possible unwanted operation)
+ * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
+ * contains the configuration information for the erasing.
+ *
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* If procedure already ongoing, reject the next one */
+ if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
+
+ /* Enable End of FLASH Operation and Error source interrupts */
+ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
+
+ if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
+ {
+ /*Mass erase to be done*/
+ pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE;
+ FLASH_MassErase();
+ }
+ else
+ {
+ /* Erase by page to be done*/
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
+ assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages));
+
+ pFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE;
+ pFlash.DataRemaining = pEraseInit->NbPages;
+ pFlash.Address = pEraseInit->PageAddress;
+
+ /*Erase 1st page and wait for IT*/
+ FLASH_PageErase(pEraseInit->PageAddress);
+ }
+
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Exported_Functions_Group2 Option Bytes Programming functions
+ * @brief Option Bytes Programming functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Option Bytes Programming functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the FLASH
+ option bytes operations.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Erases the FLASH option bytes.
+ * @note This functions erases all option bytes except the Read protection (RDP).
+ * The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
+ * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
+ * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
+ * (system reset will occur)
+ * @retval HAL status
+ */
+
+HAL_StatusTypeDef HAL_FLASHEx_OBErase(void)
+{
+ uint8_t rdptmp = OB_RDP_LEVEL_0;
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Get the actual read protection Option Byte value */
+ rdptmp = FLASH_OB_GetRDP();
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ /* Clean the error context */
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+ /* If the previous operation is completed, proceed to erase the option bytes */
+ SET_BIT(FLASH->CR, FLASH_CR_OPTER);
+ SET_BIT(FLASH->CR, FLASH_CR_STRT);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ /* If the erase operation is completed, disable the OPTER Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER);
+
+ if(status == HAL_OK)
+ {
+ /* Restore the last read protection Option Byte value */
+ status = FLASH_OB_RDP_LevelConfig(rdptmp);
+ }
+ }
+
+ /* Return the erase status */
+ return status;
+}
+
+/**
+ * @brief Program option bytes
+ * @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
+ * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
+ * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
+ * (system reset will occur)
+ *
+ * @param pOBInit pointer to an FLASH_OBInitStruct structure that
+ * contains the configuration information for the programming.
+ *
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* Check the parameters */
+ assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
+
+ /* Write protection configuration */
+ if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
+ {
+ assert_param(IS_WRPSTATE(pOBInit->WRPState));
+ if (pOBInit->WRPState == OB_WRPSTATE_ENABLE)
+ {
+ /* Enable of Write protection on the selected page */
+ status = FLASH_OB_EnableWRP(pOBInit->WRPPage);
+ }
+ else
+ {
+ /* Disable of Write protection on the selected page */
+ status = FLASH_OB_DisableWRP(pOBInit->WRPPage);
+ }
+ if (status != HAL_OK)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+ return status;
+ }
+ }
+
+ /* Read protection configuration */
+ if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP)
+ {
+ status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel);
+ if (status != HAL_OK)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+ return status;
+ }
+ }
+
+ /* USER configuration */
+ if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER)
+ {
+ status = FLASH_OB_UserConfig(pOBInit->USERConfig);
+ if (status != HAL_OK)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+ return status;
+ }
+ }
+
+ /* DATA configuration*/
+ if((pOBInit->OptionType & OPTIONBYTE_DATA) == OPTIONBYTE_DATA)
+ {
+ status = FLASH_OB_ProgramData(pOBInit->DATAAddress, pOBInit->DATAData);
+ if (status != HAL_OK)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+ return status;
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+
+ return status;
+}
+
+/**
+ * @brief Get the Option byte configuration
+ * @param pOBInit pointer to an FLASH_OBInitStruct structure that
+ * contains the configuration information for the programming.
+ *
+ * @retval None
+ */
+void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
+{
+ pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER;
+
+ /*Get WRP*/
+ pOBInit->WRPPage = FLASH_OB_GetWRP();
+
+ /*Get RDP Level*/
+ pOBInit->RDPLevel = FLASH_OB_GetRDP();
+
+ /*Get USER*/
+ pOBInit->USERConfig = FLASH_OB_GetUser();
+}
+
+/**
+ * @brief Get the Option byte user data
+ * @param DATAAdress Address of the option byte DATA
+ * This parameter can be one of the following values:
+ * @arg @ref OB_DATA_ADDRESS_DATA0
+ * @arg @ref OB_DATA_ADDRESS_DATA1
+ * @retval Value programmed in USER data
+ */
+uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress)
+{
+ uint32_t value = 0U;
+
+ if (DATAAdress == OB_DATA_ADDRESS_DATA0)
+ {
+ /* Get value programmed in OB USER Data0 */
+ value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA0) >> FLASH_POSITION_OB_USERDATA0_BIT;
+ }
+ else
+ {
+ /* Get value programmed in OB USER Data1 */
+ value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA1) >> FLASH_POSITION_OB_USERDATA1_BIT;
+ }
+
+ return value;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASHEx_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Full erase of FLASH memory Bank
+ *
+ * @retval None
+ */
+static void FLASH_MassErase(void)
+{
+ /* Clean the error context */
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+ /* Only bank1 will be erased*/
+ SET_BIT(FLASH->CR, FLASH_CR_MER);
+ SET_BIT(FLASH->CR, FLASH_CR_STRT);
+}
+
+/**
+ * @brief Enable the write protection of the desired pages
+ * @note An option byte erase is done automatically in this function.
+ * @note When the memory read protection level is selected (RDP level = 1),
+ * it is not possible to program or erase the flash page i if
+ * debug features are connected or boot code is executed in RAM, even if nWRPi = 1
+ *
+ * @param WriteProtectPage specifies the page(s) to be write protected.
+ * The value of this parameter depend on device used within the same series
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint16_t WRP0_Data = 0xFFFFU;
+#if defined(OB_WRP1_WRP1)
+ uint16_t WRP1_Data = 0xFFFFU;
+#endif /* OB_WRP1_WRP1 */
+#if defined(OB_WRP2_WRP2)
+ uint16_t WRP2_Data = 0xFFFFU;
+#endif /* OB_WRP2_WRP2 */
+#if defined(OB_WRP3_WRP3)
+ uint16_t WRP3_Data = 0xFFFFU;
+#endif /* OB_WRP3_WRP3 */
+
+ /* Check the parameters */
+ assert_param(IS_OB_WRP(WriteProtectPage));
+
+ /* Get current write protected pages and the new pages to be protected ******/
+ WriteProtectPage = (uint32_t)(~((~FLASH_OB_GetWRP()) | WriteProtectPage));
+
+#if defined(OB_WRP_PAGES0TO15MASK)
+ WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK);
+#endif /* OB_WRP_PAGES0TO31MASK */
+
+#if defined(OB_WRP_PAGES16TO31MASK)
+ WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U);
+#endif /* OB_WRP_PAGES32TO63MASK */
+
+#if defined(OB_WRP_PAGES32TO47MASK)
+ WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U);
+#endif /* OB_WRP_PAGES32TO47MASK */
+
+#if defined(OB_WRP_PAGES48TO127MASK)
+ WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U);
+#elif defined(OB_WRP_PAGES48TO255MASK)
+ WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U);
+#endif /* OB_WRP_PAGES48TO63MASK */
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ /* Clean the error context */
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+ /* To be able to write again option byte, need to perform a option byte erase */
+ status = HAL_FLASHEx_OBErase();
+ if (status == HAL_OK)
+ {
+ /* Enable write protection */
+ SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
+
+#if defined(OB_WRP0_WRP0)
+ if(WRP0_Data != 0xFFU)
+ {
+ OB->WRP0 &= WRP0_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ }
+#endif /* OB_WRP0_WRP0 */
+
+#if defined(OB_WRP1_WRP1)
+ if((status == HAL_OK) && (WRP1_Data != 0xFFU))
+ {
+ OB->WRP1 &= WRP1_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ }
+#endif /* OB_WRP1_WRP1 */
+
+#if defined(OB_WRP2_WRP2)
+ if((status == HAL_OK) && (WRP2_Data != 0xFFU))
+ {
+ OB->WRP2 &= WRP2_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ }
+#endif /* OB_WRP2_WRP2 */
+
+#if defined(OB_WRP3_WRP3)
+ if((status == HAL_OK) && (WRP3_Data != 0xFFU))
+ {
+ OB->WRP3 &= WRP3_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ }
+#endif /* OB_WRP3_WRP3 */
+
+ /* if the program operation is completed, disable the OPTPG Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief Disable the write protection of the desired pages
+ * @note An option byte erase is done automatically in this function.
+ * @note When the memory read protection level is selected (RDP level = 1),
+ * it is not possible to program or erase the flash page i if
+ * debug features are connected or boot code is executed in RAM, even if nWRPi = 1
+ *
+ * @param WriteProtectPage specifies the page(s) to be write unprotected.
+ * The value of this parameter depend on device used within the same series
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint16_t WRP0_Data = 0xFFFFU;
+#if defined(OB_WRP1_WRP1)
+ uint16_t WRP1_Data = 0xFFFFU;
+#endif /* OB_WRP1_WRP1 */
+#if defined(OB_WRP2_WRP2)
+ uint16_t WRP2_Data = 0xFFFFU;
+#endif /* OB_WRP2_WRP2 */
+#if defined(OB_WRP3_WRP3)
+ uint16_t WRP3_Data = 0xFFFFU;
+#endif /* OB_WRP3_WRP3 */
+
+ /* Check the parameters */
+ assert_param(IS_OB_WRP(WriteProtectPage));
+
+ /* Get current write protected pages and the new pages to be unprotected ******/
+ WriteProtectPage = (FLASH_OB_GetWRP() | WriteProtectPage);
+
+#if defined(OB_WRP_PAGES0TO15MASK)
+ WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK);
+#endif /* OB_WRP_PAGES0TO31MASK */
+
+#if defined(OB_WRP_PAGES16TO31MASK)
+ WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U);
+#endif /* OB_WRP_PAGES32TO63MASK */
+
+#if defined(OB_WRP_PAGES32TO47MASK)
+ WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U);
+#endif /* OB_WRP_PAGES32TO47MASK */
+
+#if defined(OB_WRP_PAGES48TO127MASK)
+ WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U);
+#elif defined(OB_WRP_PAGES48TO255MASK)
+ WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U);
+#endif /* OB_WRP_PAGES48TO63MASK */
+
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ /* Clean the error context */
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+ /* To be able to write again option byte, need to perform a option byte erase */
+ status = HAL_FLASHEx_OBErase();
+ if (status == HAL_OK)
+ {
+ SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
+
+#if defined(OB_WRP0_WRP0)
+ if(WRP0_Data != 0xFFU)
+ {
+ OB->WRP0 |= WRP0_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ }
+#endif /* OB_WRP0_WRP0 */
+
+#if defined(OB_WRP1_WRP1)
+ if((status == HAL_OK) && (WRP1_Data != 0xFFU))
+ {
+ OB->WRP1 |= WRP1_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ }
+#endif /* OB_WRP1_WRP1 */
+
+#if defined(OB_WRP2_WRP2)
+ if((status == HAL_OK) && (WRP2_Data != 0xFFU))
+ {
+ OB->WRP2 |= WRP2_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ }
+#endif /* OB_WRP2_WRP2 */
+
+#if defined(OB_WRP3_WRP3)
+ if((status == HAL_OK) && (WRP3_Data != 0xFFU))
+ {
+ OB->WRP3 |= WRP3_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ }
+#endif /* OB_WRP3_WRP3 */
+
+ /* if the program operation is completed, disable the OPTPG Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
+ }
+ }
+ return status;
+}
+
+/**
+ * @brief Set the read protection level.
+ * @param ReadProtectLevel specifies the read protection level.
+ * This parameter can be one of the following values:
+ * @arg @ref OB_RDP_LEVEL_0 No protection
+ * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory
+ * @arg @ref OB_RDP_LEVEL_2 Full chip protection
+ * @note Warning: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_OB_RDP_LEVEL(ReadProtectLevel));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ /* Clean the error context */
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+ /* If the previous operation is completed, proceed to erase the option bytes */
+ SET_BIT(FLASH->CR, FLASH_CR_OPTER);
+ SET_BIT(FLASH->CR, FLASH_CR_STRT);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ /* If the erase operation is completed, disable the OPTER Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER);
+
+ if(status == HAL_OK)
+ {
+ /* Enable the Option Bytes Programming operation */
+ SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
+
+ WRITE_REG(OB->RDP, ReadProtectLevel);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ /* if the program operation is completed, disable the OPTPG Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief Program the FLASH User Option Byte.
+ * @note Programming of the OB should be performed only after an erase (otherwise PGERR occurs)
+ * @param UserConfig The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), nBOOT1(Bit4),
+ * VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6).
+ * And SDADC12_VDD_MONITOR(Bit7) for STM32F373 or STM32F378 .
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_OB_IWDG_SOURCE((UserConfig&OB_IWDG_SW)));
+ assert_param(IS_OB_STOP_SOURCE((UserConfig&OB_STOP_NO_RST)));
+ assert_param(IS_OB_STDBY_SOURCE((UserConfig&OB_STDBY_NO_RST)));
+ assert_param(IS_OB_BOOT1((UserConfig&OB_BOOT1_SET)));
+ assert_param(IS_OB_VDDA_ANALOG((UserConfig&OB_VDDA_ANALOG_ON)));
+ assert_param(IS_OB_SRAM_PARITY((UserConfig&OB_SRAM_PARITY_RESET)));
+#if defined(FLASH_OBR_SDADC12_VDD_MONITOR)
+ assert_param(IS_OB_SDACD_VDD_MONITOR((UserConfig&OB_SDACD_VDD_MONITOR_SET)));
+#endif /* FLASH_OBR_SDADC12_VDD_MONITOR */
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ /* Clean the error context */
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+ /* Enable the Option Bytes Programming operation */
+ SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
+
+#if defined(FLASH_OBR_SDADC12_VDD_MONITOR)
+ OB->USER = (UserConfig | 0x08U);
+#else
+ OB->USER = (UserConfig | 0x88U);
+#endif
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ /* if the program operation is completed, disable the OPTPG Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Programs a half word at a specified Option Byte Data address.
+ * @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
+ * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
+ * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
+ * (system reset will occur)
+ * Programming of the OB should be performed only after an erase (otherwise PGERR occurs)
+ * @param Address specifies the address to be programmed.
+ * This parameter can be 0x1FFFF804 or 0x1FFFF806.
+ * @param Data specifies the data to be programmed.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_OB_DATA_ADDRESS(Address));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ /* Clean the error context */
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+ /* Enables the Option Bytes Programming operation */
+ SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
+ *(__IO uint16_t*)Address = Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ /* If the program operation is completed, disable the OPTPG Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
+ }
+ /* Return the Option Byte Data Program Status */
+ return status;
+}
+
+/**
+ * @brief Return the FLASH Write Protection Option Bytes value.
+ * @retval The FLASH Write Protection Option Bytes value
+ */
+static uint32_t FLASH_OB_GetWRP(void)
+{
+ /* Return the FLASH write protection Register value */
+ return (uint32_t)(READ_REG(FLASH->WRPR));
+}
+
+/**
+ * @brief Returns the FLASH Read Protection level.
+ * @retval FLASH RDP level
+ * This parameter can be one of the following values:
+ * @arg @ref OB_RDP_LEVEL_0 No protection
+ * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory
+ * @arg @ref OB_RDP_LEVEL_2 Full chip protection
+ */
+static uint32_t FLASH_OB_GetRDP(void)
+{
+ uint32_t tmp_reg = 0U;
+
+ /* Read RDP level bits */
+#if defined(FLASH_OBR_RDPRT)
+ tmp_reg = READ_BIT(FLASH->OBR, FLASH_OBR_RDPRT);
+#endif
+#if defined(FLASH_OBR_LEVEL1_PROT)
+ tmp_reg = READ_BIT(FLASH->OBR, (FLASH_OBR_LEVEL1_PROT | FLASH_OBR_LEVEL2_PROT));
+#endif /* FLASH_OBR_LEVEL1_PROT */
+
+#if defined(FLASH_OBR_RDPRT)
+ if (tmp_reg == FLASH_OBR_RDPRT_1)
+#endif
+#if defined(FLASH_OBR_LEVEL1_PROT)
+ if (tmp_reg == FLASH_OBR_LEVEL1_PROT)
+#endif /* FLASH_OBR_LEVEL1_PROT */
+ {
+ return OB_RDP_LEVEL_1;
+ }
+#if defined(FLASH_OBR_RDPRT)
+ else if (tmp_reg == FLASH_OBR_RDPRT_2)
+#elif defined(FLASH_OBR_LEVEL2_PROT)
+ else if (tmp_reg == FLASH_OBR_LEVEL2_PROT)
+#endif
+ {
+ return OB_RDP_LEVEL_2;
+ }
+ else
+ {
+ return OB_RDP_LEVEL_0;
+ }
+}
+
+/**
+ * @brief Return the FLASH User Option Byte value.
+ * @retval The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), nBOOT1(Bit4),
+ * VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6).
+ * And SDADC12_VDD_MONITOR(Bit7) for STM32F373 or STM32F378 .
+ */
+static uint8_t FLASH_OB_GetUser(void)
+{
+ /* Return the User Option Byte */
+ return (uint8_t)((READ_REG(FLASH->OBR) & FLASH_OBR_USER) >> FLASH_POSITION_IWDGSW_BIT);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH
+ * @{
+ */
+
+/** @addtogroup FLASH_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Erase the specified FLASH memory page
+ * @param PageAddress FLASH page to erase
+ * The value of this parameter depend on device used within the same series
+ *
+ * @retval None
+ */
+void FLASH_PageErase(uint32_t PageAddress)
+{
+ /* Clean the error context */
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+ /* Proceed to erase the page */
+ SET_BIT(FLASH->CR, FLASH_CR_PER);
+ WRITE_REG(FLASH->AR, PageAddress);
+ SET_BIT(FLASH->CR, FLASH_CR_STRT);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_FLASH_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_gpio.c b/Src/stm32f3xx_hal_gpio.c
new file mode 100644
index 0000000..d205d19
--- /dev/null
+++ b/Src/stm32f3xx_hal_gpio.c
@@ -0,0 +1,547 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_gpio.c
+ * @author MCD Application Team
+ * @brief GPIO HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the General Purpose Input/Output (GPIO) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### GPIO Peripheral features #####
+ ==============================================================================
+ [..]
+ (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
+ configured by software in several modes:
+ (++) Input mode
+ (++) Analog mode
+ (++) Output mode
+ (++) Alternate function mode
+ (++) External interrupt/event lines
+
+ (+) During and just after reset, the alternate functions and external interrupt
+ lines are not active and the I/O ports are configured in input floating mode.
+
+ (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
+ activated or not.
+
+ (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
+ type and the IO speed can be selected depending on the VDD value.
+
+ (+) The microcontroller IO pins are connected to onboard peripherals/modules through a
+ multiplexer that allows only one peripheral alternate function (AF) connected
+ to an IO pin at a time. In this way, there can be no conflict between peripherals
+ sharing the same IO pin.
+
+ (+) All ports have external interrupt/event capability. To use external interrupt
+ lines, the port must be configured in input mode. All available GPIO pins are
+ connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
+
+ (+) The external interrupt/event controller consists of up to 23 edge detectors
+ (16 lines are connected to GPIO) for generating event/interrupt requests (each
+ input line can be independently configured to select the type (interrupt or event)
+ and the corresponding trigger event (rising or falling or both). Each line can
+ also be masked independently.
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
+
+ (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
+ (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
+ (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
+ structure.
+ (++) In case of Output or alternate function mode selection: the speed is
+ configured through "Speed" member from GPIO_InitTypeDef structure.
+ (++) In alternate mode is selection, the alternate function connected to the IO
+ is configured through "Alternate" member from GPIO_InitTypeDef structure.
+ (++) Analog mode is required when a pin is to be used as ADC channel
+ or DAC output.
+ (++) In case of external interrupt/event selection the "Mode" member from
+ GPIO_InitTypeDef structure select the type (interrupt or event) and
+ the corresponding trigger event (rising or falling or both).
+
+ (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
+ mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
+ HAL_NVIC_EnableIRQ().
+
+ (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
+
+ (#) To set/reset the level of a pin configured in output mode use
+ HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
+
+ (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
+
+ (#) During and just after reset, the alternate functions are not
+ active and the GPIO pins are configured in input floating mode (except JTAG
+ pins).
+
+ (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
+ (PC14 and PC15U, respectively) when the LSE oscillator is off. The LSE has
+ priority over the GPIO function.
+
+ (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
+ general purpose PF0 and PF1, respectively, when the HSE oscillator is off.
+ The HSE has priority over the GPIO function.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup GPIO GPIO
+ * @brief GPIO HAL module driver
+ * @{
+ */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup GPIO_Private_Defines GPIO Private Defines
+ * @{
+ */
+#define GPIO_MODE (0x00000003U)
+#define EXTI_MODE (0x10000000U)
+#define GPIO_MODE_IT (0x00010000U)
+#define GPIO_MODE_EVT (0x00020000U)
+#define RISING_EDGE (0x00100000U)
+#define FALLING_EDGE (0x00200000U)
+#define GPIO_OUTPUT_TYPE (0x00000010U)
+
+#define GPIO_NUMBER (16U)
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup GPIO_Private_Macros GPIO Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
+ * @{
+ */
+
+/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
+ * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F3 family devices
+ * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
+ * the configuration information for the specified GPIO peripheral.
+ * @retval None
+ */
+void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
+{
+ uint32_t position = 0x00U;
+ uint32_t iocurrent = 0x00U;
+ uint32_t temp = 0x00U;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
+ assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
+ assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
+
+ /* Configure the port pins */
+ while (((GPIO_Init->Pin) >> position) != RESET)
+ {
+ /* Get current io position */
+ iocurrent = (GPIO_Init->Pin) & (1U << position);
+
+ if(iocurrent)
+ {
+ /*--------------------- GPIO Mode Configuration ------------------------*/
+ /* In case of Alternate function mode selection */
+ if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+ {
+ /* Check the Alternate function parameters */
+ assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
+ assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
+
+ /* Configure Alternate function mapped with the current IO */
+ temp = GPIOx->AFR[position >> 3];
+ temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
+ temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
+ GPIOx->AFR[position >> 3] = temp;
+ }
+
+ /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
+ temp = GPIOx->MODER;
+ temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
+ temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
+ GPIOx->MODER = temp;
+
+ /* In case of Output or Alternate function mode selection */
+ if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
+ (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+ {
+ /* Check the Speed parameter */
+ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
+ /* Configure the IO Speed */
+ temp = GPIOx->OSPEEDR;
+ temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
+ temp |= (GPIO_Init->Speed << (position * 2U));
+ GPIOx->OSPEEDR = temp;
+
+ /* Configure the IO Output Type */
+ temp = GPIOx->OTYPER;
+ temp &= ~(GPIO_OTYPER_OT_0 << position) ;
+ temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
+ GPIOx->OTYPER = temp;
+ }
+
+ /* Activate the Pull-up or Pull down resistor for the current IO */
+ temp = GPIOx->PUPDR;
+ temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
+ temp |= ((GPIO_Init->Pull) << (position * 2U));
+ GPIOx->PUPDR = temp;
+
+ /*--------------------- EXTI Mode Configuration ------------------------*/
+ /* Configure the External Interrupt or event for the current IO */
+ if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
+ {
+ /* Enable SYSCFG Clock */
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+ temp = SYSCFG->EXTICR[position >> 2];
+ temp &= ~((0x0FU) << (4U * (position & 0x03U)));
+ temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
+ SYSCFG->EXTICR[position >> 2] = temp;
+
+ /* Clear EXTI line configuration */
+ temp = EXTI->IMR;
+ temp &= ~((uint32_t)iocurrent);
+ if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
+ {
+ temp |= iocurrent;
+ }
+ EXTI->IMR = temp;
+
+ temp = EXTI->EMR;
+ temp &= ~((uint32_t)iocurrent);
+ if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
+ {
+ temp |= iocurrent;
+ }
+ EXTI->EMR = temp;
+
+ /* Clear Rising Falling edge configuration */
+ temp = EXTI->RTSR;
+ temp &= ~((uint32_t)iocurrent);
+ if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
+ {
+ temp |= iocurrent;
+ }
+ EXTI->RTSR = temp;
+
+ temp = EXTI->FTSR;
+ temp &= ~((uint32_t)iocurrent);
+ if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
+ {
+ temp |= iocurrent;
+ }
+ EXTI->FTSR = temp;
+ }
+ }
+
+ position++;
+ }
+}
+
+/**
+ * @brief De-initialize the GPIOx peripheral registers to their default reset values.
+ * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F30X device or STM32F37X device
+ * @param GPIO_Pin specifies the port bit to be written.
+ * This parameter can be one of GPIO_PIN_x where x can be (0..15).
+ * @retval None
+ */
+void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
+{
+ uint32_t position = 0x00U;
+ uint32_t iocurrent = 0x00U;
+ uint32_t tmp = 0x00U;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ /* Configure the port pins */
+ while ((GPIO_Pin >> position) != RESET)
+ {
+ /* Get current io position */
+ iocurrent = GPIO_Pin & (1U << position);
+
+ if (iocurrent)
+ {
+ /*------------------------- GPIO Mode Configuration --------------------*/
+ /* Configure IO Direction in Input Floting Mode */
+ GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2U));
+
+ /* Configure the default Alternate Function in current IO */
+ GPIOx->AFR[position >> 3] &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
+
+ /* Configure the default value for IO Speed */
+ GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
+
+ /* Configure the default value IO Output Type */
+ GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ;
+
+ /* Deactivate the Pull-up and Pull-down resistor for the current IO */
+ GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
+
+
+ /*------------------------- EXTI Mode Configuration --------------------*/
+ /* Clear the External Interrupt or Event for the current IO */
+
+ tmp = SYSCFG->EXTICR[position >> 2];
+ tmp &= ((0x0FU) << (4U * (position & 0x03U)));
+ if(tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))))
+ {
+ tmp = (0x0FU) << (4U * (position & 0x03U));
+ SYSCFG->EXTICR[position >> 2] &= ~tmp;
+
+ /* Clear EXTI line configuration */
+ EXTI->IMR &= ~((uint32_t)iocurrent);
+ EXTI->EMR &= ~((uint32_t)iocurrent);
+
+ /* Clear Rising Falling edge configuration */
+ EXTI->RTSR &= ~((uint32_t)iocurrent);
+ EXTI->FTSR &= ~((uint32_t)iocurrent);
+ }
+ }
+
+ position++;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
+ * @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Read the specified input port pin.
+ * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F3 family
+ * @param GPIO_Pin specifies the port bit to read.
+ * This parameter can be GPIO_PIN_x where x can be (0..15).
+ * @retval The input port pin value.
+ */
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ GPIO_PinState bitstatus;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
+ {
+ bitstatus = GPIO_PIN_SET;
+ }
+ else
+ {
+ bitstatus = GPIO_PIN_RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Set or clear the selected data port bit.
+ *
+ * @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify
+ * accesses. In this way, there is no risk of an IRQ occurring between
+ * the read and the modify access.
+ *
+ * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F3 family
+ * @param GPIO_Pin specifies the port bit to be written.
+ * This parameter can be one of GPIO_PIN_x where x can be (0..15).
+ * @param PinState specifies the value to be written to the selected bit.
+ * This parameter can be one of the GPIO_PinState enum values:
+ * @arg GPIO_PIN_RESET: to clear the port pin
+ * @arg GPIO_PIN_SET: to set the port pin
+ * @retval None
+ */
+void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+ assert_param(IS_GPIO_PIN_ACTION(PinState));
+
+ if(PinState != GPIO_PIN_RESET)
+ {
+ GPIOx->BSRR = (uint32_t)GPIO_Pin;
+ }
+ else
+ {
+ GPIOx->BRR = (uint32_t)GPIO_Pin;
+ }
+}
+
+/**
+ * @brief Toggle the specified GPIO pin.
+ * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F3 family
+ * @param GPIO_Pin specifies the pin to be toggled.
+ * @retval None
+ */
+void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ GPIOx->ODR ^= GPIO_Pin;
+}
+
+/**
+* @brief Lock GPIO Pins configuration registers.
+ * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
+ * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
+ * @note The configuration of the locked GPIO pins can no longer be modified
+ * until the next reset.
+ * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F3 family
+ * @param GPIO_Pin specifies the port bits to be locked.
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ __IO uint32_t tmp = GPIO_LCKR_LCKK;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ /* Apply lock key write sequence */
+ tmp |= GPIO_Pin;
+ /* Set LCKx bit(s): LCKK='1' + LCK[15U-0] */
+ GPIOx->LCKR = tmp;
+ /* Reset LCKx bit(s): LCKK='0' + LCK[15U-0] */
+ GPIOx->LCKR = GPIO_Pin;
+ /* Set LCKx bit(s): LCKK='1' + LCK[15U-0] */
+ GPIOx->LCKR = tmp;
+ /* Read LCKK bit*/
+ tmp = GPIOx->LCKR;
+
+ if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)
+ {
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Handle EXTI interrupt request.
+ * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
+ * @retval None
+ */
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
+{
+ /* EXTI line interrupt detected */
+ if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
+ {
+ __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
+ HAL_GPIO_EXTI_Callback(GPIO_Pin);
+ }
+}
+
+/**
+ * @brief EXTI line detection callback.
+ * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
+ * @retval None
+ */
+__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(GPIO_Pin);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_GPIO_EXTI_Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+#endif /* HAL_GPIO_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_hrtim.c b/Src/stm32f3xx_hal_hrtim.c
new file mode 100644
index 0000000..cf27e67
--- /dev/null
+++ b/Src/stm32f3xx_hal_hrtim.c
@@ -0,0 +1,8240 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_hrtim.c
+ * @author MCD Application Team
+ * @brief TIM HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the High Resolution Timer (HRTIM) peripheral:
+ * + HRTIM Initialization
+ * + DLL Calibration Start
+ * + Timer Time Base Unit Configuration
+ * + Simple Time Base Start/Stop
+ * + Simple Time Base Start/Stop Interrupt
+ * + Simple Time Base Start/Stop DMA Request
+ * + Simple Output Compare/PWM Channel Configuration
+ * + Simple Output Compare/PWM Channel Start/Stop Interrupt
+ * + Simple Output Compare/PWM Channel Start/Stop DMA Request
+ * + Simple Input Capture Channel Configuration
+ * + Simple Input Capture Channel Start/Stop Interrupt
+ * + Simple Input Capture Channel Start/Stop DMA Request
+ * + Simple One Pulse Channel Configuration
+ * + Simple One Pulse Channel Start/Stop Interrupt
+ * + HRTIM External Synchronization Configuration
+ * + HRTIM Burst Mode Controller Configuration
+ * + HRTIM Burst Mode Controller Enabling
+ * + HRTIM External Events Conditioning Configuration
+ * + HRTIM Faults Conditioning Configuration
+ * + HRTIM Faults Enabling
+ * + HRTIM ADC trigger Configuration
+ * + Waveform Timer Configuration
+ * + Waveform Event Filtering Configuration
+ * + Waveform Dead Time Insertion Configuration
+ * + Waveform Chopper Mode Configuration
+ * + Waveform Compare Unit Configuration
+ * + Waveform Capture Unit Configuration
+ * + Waveform Output Configuration
+ * + Waveform Counter Start/Stop
+ * + Waveform Counter Start/Stop Interrupt
+ * + Waveform Counter Start/Stop DMA Request
+ * + Waveform Output Enabling
+ * + Waveform Output Level Set/Get
+ * + Waveform Output State Get
+ * + Waveform Burst DMA Operation Configuration
+ * + Waveform Burst DMA Operation Start
+ * + Waveform Timer Counter Software Reset
+ * + Waveform Capture Software Trigger
+ * + Waveform Burst Mode Controller Software Trigger
+ * + Waveform Timer Pre-loadable Registers Update Enabling
+ * + Waveform Timer Pre-loadable Registers Software Update
+ * + Waveform Timer Delayed Protection Status Get
+ * + Waveform Timer Burst Status Get
+ * + Waveform Timer Push-Pull Status Get
+ * + Peripheral State Get
+ @verbatim
+==============================================================================
+ ##### Simple mode v.s. waveform mode #####
+==============================================================================
+ [..] The HRTIM HAL API is split into 2 categories:
+ (#)Simple functions: these functions allow for using a HRTIM timer as a
+ general purpose timer with high resolution capabilities.
+ HRTIM simple modes are managed through the set of functions named
+ HAL_HRTIM_Simple<Function>. These functions are similar in name and usage
+ to the one defined for the TIM peripheral. When a HRTIM timer operates in
+ simple mode, only a very limited set of HRTIM features are used.
+ Following simple modes are proposed:
+ (++)Output compare mode,
+ (++)PWM output mode,
+ (++)Input capture mode,
+ (++)One pulse mode.
+ (#)Waveform functions: These functions allow taking advantage of the HRTIM
+ flexibility to produce numerous types of control signal. When a HRTIM timer
+ operates in waveform mode, all the HRTIM features are accessible without
+ any restriction. HRTIM waveform modes are managed through the set of
+ functions named HAL_HRTIM_Waveform<Function>
+ ##### How to use this driver #####
+==============================================================================
+ [..]
+ (#)Initialize the HRTIM low level resources by implementing the
+ HAL_HRTIM_MspInit() function:
+ (##)Enable the HRTIM clock source using __HRTIMx_CLK_ENABLE()
+ (##)Connect HRTIM pins to MCU I/Os
+ (+++) Enable the clock for the HRTIM GPIOs using the following
+ function: __HAL_RCC_GPIOx_CLK_ENABLE()
+ (+++) Configure these GPIO pins in Alternate Function mode using
+ HAL_GPIO_Init()
+ (##)When using DMA to control data transfer (e.g HAL_HRTIM_SimpleBaseStart_DMA())
+ (+++)Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
+ (+++)Initialize the DMA handle
+ (+++)Associate the initialized DMA handle to the appropriate DMA
+ handle of the HRTIM handle using __HAL_LINKDMA()
+ (+++)Initialize the DMA channel using HAL_DMA_Init()
+ (+++)Configure the priority and enable the NVIC for the transfer
+ complete interrupt on the DMA channel using HAL_NVIC_SetPriority()
+ and HAL_NVIC_EnableIRQ()
+ (##)In case of using interrupt mode (e.g HAL_HRTIM_SimpleBaseStart_IT())
+ (+++)Configure the priority and enable the NVIC for the concerned
+ HRTIM interrupt using HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
+
+ (#)Initialize the HRTIM HAL using HAL_HRTIM_Init(). The HRTIM configuration
+ structure (field of the HRTIM handle) specifies which global interrupt of
+ whole HRTIM must be enabled (Burst mode period, System fault, Faults).
+ It also contains the HRTIM external synchronization configuration. HRTIM
+ can act as a master (generating a synchronization signal) or as a slave
+ (waiting for a trigger to be synchronized).
+
+ (#)Start the high resolution unit using HAL_HRTIM_DLLCalibrationStart(). DLL
+ calibration is executed periodically and compensate for potential voltage
+ and temperature drifts. DLL calibration period is specified by the
+ CalibrationRate argument.
+
+ (#)HRTIM timers cannot be used until the high resolution unit is ready. This
+ can be checked using HAL_HRTIM_PollForDLLCalibration(): this function returns
+ HAL_OK if DLL calibration is completed or HAL_TIMEOUT if the DLL calibration
+ is still going on when timeout given as argument expires. DLL calibration
+ can also be started in interrupt mode using HAL_HRTIM_DLLCalibrationStart_IT().
+ In that case an interrupt is generated when the DLL calibration is completed.
+ Note that as DLL calibration is executed on a periodic basis an interrupt
+ will be generated at the end of every DLL calibration operation
+ (worst case: one interrupt every 14 micro seconds !).
+
+ (#) Configure HRTIM resources shared by all HRTIM timers
+ (##)Burst Mode Controller:
+ (+++)HAL_HRTIM_BurstModeConfig(): configures the HRTIM burst mode
+ controller: operating mode (continuous or one-shot mode), clock
+ (source, prescaler) , trigger(s), period, idle duration.
+ (##)External Events Conditionning:
+ (+++)HAL_HRTIM_EventConfig(): configures the conditioning of an
+ external event channel: source, polarity, edge-sensitivity.
+ External event can be used as triggers (timer reset, input
+ capture, burst mode, ADC triggers, delayed protection)
+ They can also be used to set or reset timer outputs. Up to
+ 10 event channels are available.
+ (+++)HAL_HRTIM_EventPrescalerConfig(): configures the external
+ event sampling clock (used for digital filtering).
+ (##)Fault Conditionning:
+ (+++)HAL_HRTIM_FaultConfig(): configures the conditioning of a
+ fault channel: source, polarity, edge-sensitivity. Fault
+ channels are used to disable the outputs in case of an
+ abnormal operation. Up to 5 fault channels are available.
+ (+++)HAL_HRTIM_FaultPrescalerConfig(): configures the fault
+ sampling clock (used for digital filtering).
+ (+++)HAL_HRTIM_FaultModeCtl(): Enables or disables fault input(s)
+ circuitry. By default all fault inputs are disabled.
+ (##)ADC trigger:
+ (+++)HAL_HRTIM_ADCTriggerConfig(): configures the source triggering
+ the update of the ADC trigger register and the ADC trigger.
+ 4 independent triggers are available to start both the regular
+ and the injected sequencers of the 2 ADCs
+
+ (#) Configure HRTIM timer time base using HAL_HRTIM_TimeBaseConfig(). This
+ function must be called whatever the HRTIM timer operating mode is
+ (simple v.s. waveform). It configures mainly:
+ (##)The HRTIM timer counter operating mode (continuous v.s. one shot)
+ (##)The HRTIM timer clock prescaler
+ (##)The HRTIM timer period
+ (##)The HRTIM timer repetition counter
+
+ *** If the HRTIM timer operates in simple mode ***
+ ===================================================
+ [..]
+ (#) Start or Stop simple timers
+ (++)Simple time base: HAL_HRTIM_SimpleBaseStart(),HAL_HRTIM_SimpleBaseStop(),
+ HAL_HRTIM_SimpleBaseStart_IT(),HAL_HRTIM_SimpleBaseStop_IT(),
+ HAL_HRTIM_SimpleBaseStart_DMA(),HAL_HRTIM_SimpleBaseStop_DMA().
+ (++)Simple output compare: HAL_HRTIM_SimpleOCChannelConfig(),
+ HAL_HRTIM_SimpleOCStart(),HAL_HRTIM_SimpleOCStop(),
+ HAL_HRTIM_SimpleOCStart_IT(),HAL_HRTIM_SimpleOCStop_IT(),
+ HAL_HRTIM_SimpleOCStart_DMA(),HAL_HRTIM_SimpleOCStop_DMA(),
+ (++)Simple PWM output: HAL_HRTIM_SimplePWMChannelConfig(),
+ HAL_HRTIM_SimplePWMStart(),HAL_HRTIM_SimplePWMStop(),
+ HAL_HRTIM_SimplePWMStart_IT(),HAL_HRTIM_SimplePWMStop_IT(),
+ HAL_HRTIM_SimplePWMStart_DMA(),HAL_HRTIM_SimplePWMStop_DMA(),
+ (++)Simple input capture: HAL_HRTIM_SimpleCaptureChannelConfig(),
+ HAL_HRTIM_SimpleCaptureStart(),HAL_HRTIM_SimpleCaptureStop(),
+ HAL_HRTIM_SimpleCaptureStart_IT(),HAL_HRTIM_SimpleCaptureStop_IT(),
+ HAL_HRTIM_SimpleCaptureStart_DMA(),HAL_HRTIM_SimpleCaptureStop_DMA().
+ (++)Simple one pulse: HAL_HRTIM_SimpleOnePulseChannelConfig(),
+ HAL_HRTIM_SimpleOnePulseStart(),HAL_HRTIM_SimpleOnePulseStop(),
+ HAL_HRTIM_SimpleOnePulseStart_IT(),HAL_HRTIM_SimpleOnePulseStop_It().
+
+ *** If the HRTIM timer operates in waveform mode ***
+ ====================================================
+ [..]
+ (#) Completes waveform timer configuration
+ (++)HAL_HRTIM_WaveformTimerConfig(): configuration of a HRTIM timer
+ operating in wave form mode mainly consists in:
+ (+++)Enabling the HRTIM timer interrupts and DMA requests.
+ (+++)Enabling the half mode for the HRTIM timer.
+ (+++)Defining how the HRTIM timer reacts to external synchronization input.
+ (+++)Enabling the push-pull mode for the HRTIM timer.
+ (+++)Enabling the fault channels for the HRTIM timer.
+ (+++)Enabling the dead-time insertion for the HRTIM timer.
+ (+++)Setting the delayed protection mode for the HRTIM timer (source and outputs
+ on which the delayed protection are applied).
+ (+++)Specifying the HRTIM timer update and reset triggers.
+ (+++)Specifying the HRTIM timer registers update policy (e.g. pre-load enabling).
+ (++)HAL_HRTIM_TimerEventFilteringConfig(): configures external
+ event blanking and windowing circuitry of a HRTIM timer:
+ (+++)Blanking: to mask external events during a defined time period a defined time period
+ (+++)Windowing, to enable external events only during a defined time period
+ (++)HAL_HRTIM_DeadTimeConfig(): configures the dead-time insertion
+ unit for a HRTIM timer. Allows to generate a couple of
+ complementary signals from a single reference waveform,
+ with programmable delays between active state.
+ (++)HAL_HRTIM_ChopperModeConfig(): configures the parameters of
+ the high-frequency carrier signal added on top of the timing
+ unit output. Chopper mode can be enabled or disabled for each
+ timer output separately (see HAL_HRTIM_WaveformOutputConfig()).
+ (++)HAL_HRTIM_BurstDMAConfig(): configures the burst DMA burst
+ controller. Allows having multiple HRTIM registers updated
+ with a single DMA request. The burst DMA operation is started
+ by calling HAL_HRTIM_BurstDMATransfer().
+ (++)HAL_HRTIM_WaveformCompareConfig():configures the compare unit
+ of a HRTIM timer. This operation consists in setting the
+ compare value and possibly specifying the auto delayed mode
+ for compare units 2 and 4 (allows to have compare events
+ generated relatively to capture events). Note that when auto
+ delayed mode is needed, the capture unit associated to the
+ compare unit must be configured separately.
+ (++)HAL_HRTIM_WaveformCaptureConfig(): configures the capture unit
+ of a HRTIM timer. This operation consists in specifying the
+ source(s) triggering the capture (timer register update event,
+ external event, timer output set/reset event, other HRTIM
+ timer related events).
+ (++)HAL_HRTIM_WaveformOutputConfig(): configuration of a HRTIM timer
+ output mainly consists in:
+ (+++)Setting the output polarity (active high or active low),
+ (+++)Defining the set/reset crossbar for the output,
+ (+++)Specifying the fault level (active or inactive) in IDLE and FAULT states.,
+
+ (#) Set waveform timer output(s) level
+ (++)HAL_HRTIM_WaveformSetOutputLevel(): forces the output to its
+ active or inactive level. For example, when deadtime insertion
+ is enabled it is necessary to force the output level by software
+ to have the outputs in a complementary state as soon as the RUN mode is entered.
+
+ (#) Enable or Disable waveform timer output(s)
+ (++)HAL_HRTIM_WaveformOutputStart(),HAL_HRTIM_WaveformOutputStop().
+
+ (#) Start or Stop waveform HRTIM timer(s).
+ (++)HAL_HRTIM_WaveformCounterStart(),HAL_HRTIM_WaveformCounterStop(),
+ (++)HAL_HRTIM_WaveformCounterStart_IT(),HAL_HRTIM_WaveformCounterStop_IT(),
+ (++)HAL_HRTIM_WaveformCounterStart()_DMA,HAL_HRTIM_WaveformCounterStop_DMA(),
+ (#) Burst mode controller enabling:
+ (++)HAL_HRTIM_BurstModeCtl(): activates or de-activates the
+ burst mode controller.
+
+ (#) Some HRTIM operations can be triggered by software:
+ (++)HAL_HRTIM_BurstModeSoftwareTrigger(): calling this function
+ trigs the burst operation.
+ (++)HAL_HRTIM_SoftwareCapture(): calling this function trigs the
+ capture of the HRTIM timer counter.
+ (++)HAL_HRTIM_SoftwareUpdate(): calling this function trigs the
+ update of the pre-loadable registers of the HRTIM timer
+ (++)HAL_HRTIM_SoftwareReset():calling this function resets the
+ HRTIM timer counter.
+
+ (#) Some functions can be used any time to retrieve HRTIM timer related
+ information
+ (++)HAL_HRTIM_GetCapturedValue(): returns actual value of the
+ capture register of the designated capture unit.
+ (++)HAL_HRTIM_WaveformGetOutputLevel(): returns actual level
+ (ACTIVE/INACTIVE) of the designated timer output.
+ (++)HAL_HRTIM_WaveformGetOutputState():returns actual state
+ (IDLE/RUN/FAULT) of the designated timer output.
+ (++)HAL_HRTIM_GetDelayedProtectionStatus():returns actual level
+ (ACTIVE/INACTIVE) of the designated output when the delayed
+ protection was triggered.
+ (++)HAL_HRTIM_GetBurstStatus(): returns the actual status
+ (ACTIVE/INACTIVE) of the burst mode controller.
+ (++)HAL_HRTIM_GetCurrentPushPullStatus(): when the push-pull mode
+ is enabled for the HRTIM timer (see HAL_HRTIM_WaveformTimerConfig()),
+ the push-pull status indicates on which output the signal is currently
+ active (e.g signal applied on output 1 and output 2 forced
+ inactive or vice versa).
+ (++)HAL_HRTIM_GetIdlePushPullStatus(): when the push-pull mode
+ is enabled for the HRTIM timer (see HAL_HRTIM_WaveformTimerConfig()),
+ the idle push-pull status indicates during which period the
+ delayed protection request occurred (e.g. protection occurred
+ when the output 1 was active and output 2 forced inactive or
+ vice versa).
+
+ (#) Some functions can be used any time to retrieve actual HRTIM status
+ (++)HAL_HRTIM_GetState(): returns actual HRTIM instance HAL state.
+
+ @endverbatim
+
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_HRTIM_MODULE_ENABLED
+
+#if defined(HRTIM1)
+
+/** @defgroup HRTIM HRTIM
+ * @brief HRTIM HAL module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup HRTIM_Private_Defines HRTIM Private Define
+ * @{
+ */
+#define HRTIM_FLTR_FLTxEN (HRTIM_FLTR_FLT1EN |\
+ HRTIM_FLTR_FLT2EN |\
+ HRTIM_FLTR_FLT3EN |\
+ HRTIM_FLTR_FLT4EN | \
+ HRTIM_FLTR_FLT5EN)
+
+#define HRTIM_TIMCR_TIMUPDATETRIGGER (HRTIM_TIMUPDATETRIGGER_MASTER |\
+ HRTIM_TIMUPDATETRIGGER_TIMER_A |\
+ HRTIM_TIMUPDATETRIGGER_TIMER_B |\
+ HRTIM_TIMUPDATETRIGGER_TIMER_C |\
+ HRTIM_TIMUPDATETRIGGER_TIMER_D |\
+ HRTIM_TIMUPDATETRIGGER_TIMER_E)
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup HRTIM_Private_Variables HRTIM Private Variables
+ * @{
+ */
+static uint32_t TimerIdxToTimerId[] =
+{
+ HRTIM_TIMERID_TIMER_A,
+ HRTIM_TIMERID_TIMER_B,
+ HRTIM_TIMERID_TIMER_C,
+ HRTIM_TIMERID_TIMER_D,
+ HRTIM_TIMERID_TIMER_E,
+ HRTIM_TIMERID_MASTER,
+};
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup HRTIM_Private_Functions HRTIM Private Functions
+ * @{
+ */
+static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim,
+ HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
+
+static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
+
+static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
+ HRTIM_TimerCfgTypeDef * pTimerCfg);
+
+static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ HRTIM_TimerCfgTypeDef * pTimerCfg);
+
+static void HRTIM_CompareUnitConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CompareUnit,
+ HRTIM_CompareCfgTypeDef * pCompareCfg);
+
+static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureUnit,
+ uint32_t Event);
+
+static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t Output,
+ HRTIM_OutputCfgTypeDef * pOutputCfg);
+
+static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t Event,
+ HRTIM_EventCfgTypeDef * pEventCfg);
+
+static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t Event);
+
+static uint32_t HRTIM_GetITFromOCMode(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OCChannel);
+
+static uint32_t HRTIM_GetDMAFromOCMode(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OCChannel);
+
+static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx);
+
+static uint32_t GetTimerIdxFromDMAHandle(HRTIM_HandleTypeDef * hhrtim,
+ DMA_HandleTypeDef * hdma);
+
+static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx);
+
+static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim);
+
+static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim);
+
+static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx);
+
+static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma);
+
+static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma);
+
+static void HRTIM_DMAError(DMA_HandleTypeDef *hdma);
+
+static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+/** @defgroup HRTIM_Exported_Functions HRTIM Exported Functions
+ * @{
+ */
+
+/** @defgroup HRTIM_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+@verbatim
+ ===============================================================================
+ ##### Initialization and Time Base Configuration functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize a HRTIM instance
+ (+) De-initialize a HRTIM instance
+ (+) Initialize the HRTIM MSP
+ (+) De-initialize the HRTIM MSP
+ (+) Start the high-resolution unit (start DLL calibration)
+ (+) Check that the high resolution unit is ready (DLL calibration done)
+ (+) Configure the time base unit of a HRTIM timer
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes a HRTIM instance
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef * hhrtim)
+{
+ uint8_t timer_idx;
+ uint32_t hrtim_mcr;
+
+ /* Check the HRTIM handle allocation */
+ if(hhrtim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_HRTIM_ALL_INSTANCE(hhrtim->Instance));
+ assert_param(IS_HRTIM_IT(hhrtim->Init.HRTIMInterruptResquests));
+
+ /* Set the HRTIM state */
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Initialize the DMA handles */
+ hhrtim->hdmaMaster = (DMA_HandleTypeDef *)NULL;
+ hhrtim->hdmaTimerA = (DMA_HandleTypeDef *)NULL;
+ hhrtim->hdmaTimerB = (DMA_HandleTypeDef *)NULL;
+ hhrtim->hdmaTimerC = (DMA_HandleTypeDef *)NULL;
+ hhrtim->hdmaTimerD = (DMA_HandleTypeDef *)NULL;
+ hhrtim->hdmaTimerE = (DMA_HandleTypeDef *)NULL;
+
+ /* HRTIM output synchronization configuration (if required) */
+ if ((hhrtim->Init.SyncOptions & HRTIM_SYNCOPTION_MASTER) != RESET)
+ {
+ /* Check parameters */
+ assert_param(IS_HRTIM_SYNCOUTPUTSOURCE(hhrtim->Init.SyncOutputSource));
+ assert_param(IS_HRTIM_SYNCOUTPUTPOLARITY(hhrtim->Init.SyncOutputPolarity));
+
+ /* The synchronization output initialization procedure must be done prior
+ to the configuration of the MCU outputs (done within HAL_HRTIM_MspInit)
+ */
+ if (hhrtim->Instance == HRTIM1)
+ {
+ /* Enable the HRTIM peripheral clock */
+ __HAL_RCC_HRTIM1_CLK_ENABLE();
+ }
+
+ hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
+
+ /* Set the event to be sent on the synchronization output */
+ hrtim_mcr &= ~(HRTIM_MCR_SYNC_SRC);
+ hrtim_mcr |= (hhrtim->Init.SyncOutputSource & HRTIM_MCR_SYNC_SRC);
+
+ /* Set the polarity of the synchronization output */
+ hrtim_mcr &= ~(HRTIM_MCR_SYNC_OUT);
+ hrtim_mcr |= (hhrtim->Init.SyncOutputPolarity & HRTIM_MCR_SYNC_OUT);
+
+ /* Update the HRTIM registers */
+ hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
+ }
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_HRTIM_MspInit(hhrtim);
+
+ /* HRTIM input synchronization configuration (if required) */
+ if ((hhrtim->Init.SyncOptions & HRTIM_SYNCOPTION_SLAVE) != RESET)
+ {
+ /* Check parameters */
+ assert_param(IS_HRTIM_SYNCINPUTSOURCE(hhrtim->Init.SyncInputSource));
+
+ hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
+
+ /* Set the synchronization input source */
+ hrtim_mcr &= ~(HRTIM_MCR_SYNC_IN);
+ hrtim_mcr |= (hhrtim->Init.SyncInputSource & HRTIM_MCR_SYNC_IN);
+
+ /* Update the HRTIM registers */
+ hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
+ }
+
+ /* Initialize the HRTIM state*/
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Initialize the lock status of the HRTIM HAL API */
+ __HAL_UNLOCK(hhrtim);
+
+ /* Initialize timer related parameters */
+ for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
+ timer_idx <= HRTIM_TIMERINDEX_MASTER ;
+ timer_idx++)
+ {
+ hhrtim->TimerParam[timer_idx].CaptureTrigger1 = HRTIM_CAPTURETRIGGER_NONE;
+ hhrtim->TimerParam[timer_idx].CaptureTrigger2 = HRTIM_CAPTURETRIGGER_NONE;
+ hhrtim->TimerParam[timer_idx].InterruptRequests = HRTIM_IT_NONE;
+ hhrtim->TimerParam[timer_idx].DMARequests = HRTIM_IT_NONE;
+ hhrtim->TimerParam[timer_idx].DMASrcAddress = 0U;
+ hhrtim->TimerParam[timer_idx].DMASize = 0U;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief De-initializes a HRTIM instance
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef * hhrtim)
+{
+ /* Check the HRTIM handle allocation */
+ if(hhrtim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_HRTIM_ALL_INSTANCE(hhrtim->Instance));
+
+ /* Set the HRTIM state */
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* DeInit the low level hardware */
+ HAL_HRTIM_MspDeInit(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief MSP initialization for a HRTIM instance
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @retval None
+ */
+__weak void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef * hhrtim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhrtim);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief MSP de-initialization of a HRTIM instance
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @retval None
+ */
+__weak void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef * hhrtim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhrtim);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the DLL calibration
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param CalibrationRate DLL calibration period
+ * This parameter can be one of the following values:
+ * @arg HRTIM_SINGLE_CALIBRATION: One shot DLL calibration
+ * @arg HRTIM_CALIBRATIONRATE_7300: Periodic DLL calibration. T=7.3 ms
+ * @arg HRTIM_CALIBRATIONRATE_910: Periodic DLL calibration. T=910 us
+ * @arg HRTIM_CALIBRATIONRATE_114: Periodic DLL calibration. T=114 us
+ * @arg HRTIM_CALIBRATIONRATE_14: Periodic DLL calibration. T=14 us
+ * @retval HAL status
+ * @note This function locks the HRTIM instance. HRTIM instance is unlocked
+ * within the HAL_HRTIM_PollForDLLCalibration function, just before
+ * exiting the function.
+ */
+HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t CalibrationRate)
+{
+ uint32_t hrtim_dllcr;
+
+ /* Check the parameters */
+ assert_param(IS_HRTIM_CALIBRATIONRATE(CalibrationRate));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Configure DLL Calibration */
+ hrtim_dllcr = hhrtim->Instance->sCommonRegs.DLLCR;
+
+ if (CalibrationRate == HRTIM_SINGLE_CALIBRATION)
+ {
+ /* One shot DLL calibration */
+ hrtim_dllcr &= ~(HRTIM_DLLCR_CALEN);
+ hrtim_dllcr |= HRTIM_DLLCR_CAL;
+ }
+ else
+ {
+ /* Periodic DLL calibration */
+ hrtim_dllcr &= ~(HRTIM_DLLCR_CALRTE | HRTIM_DLLCR_CAL);
+ hrtim_dllcr |= (CalibrationRate | HRTIM_DLLCR_CALEN);
+ }
+
+ /* Update HRTIM register */
+ hhrtim->Instance->sCommonRegs.DLLCR = hrtim_dllcr;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the DLL calibration.
+ * DLL ready interrupt is enabled
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param CalibrationRate DLL calibration period
+ * This parameter can be one of the following values:
+ * @arg HRTIM_SINGLE_CALIBRATION: One shot DLL calibration
+ * @arg HRTIM_CALIBRATIONRATE_7300: Periodic DLL calibration. T=7.3 ms
+ * @arg HRTIM_CALIBRATIONRATE_910: Periodic DLL calibration. T=910 us
+ * @arg HRTIM_CALIBRATIONRATE_114: Periodic DLL calibration. T=114 us
+ * @arg HRTIM_CALIBRATIONRATE_14: Periodic DLL calibration. T=14 us
+ * @retval HAL status
+ * @note This function locks the HRTIM instance. HRTIM instance is unlocked
+ * within the IRQ processing function when processing the DLL ready
+ * interrupt.
+ * @note If this function is called for periodic calibration, the DLLRDY
+ * interrupt is generated every time the calibration completes which
+ * will significantly increases the overall interrupt rate.
+ */
+HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart_IT(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t CalibrationRate)
+{
+ uint32_t hrtim_dllcr;
+
+ /* Check the parameters */
+ assert_param(IS_HRTIM_CALIBRATIONRATE(CalibrationRate));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Enable DLL Ready interrupt flag */
+ __HAL_HRTIM_ENABLE_IT(hhrtim, HRTIM_IT_DLLRDY);
+
+ /* Configure DLL Calibration */
+ hrtim_dllcr = hhrtim->Instance->sCommonRegs.DLLCR;
+
+ if (CalibrationRate == HRTIM_SINGLE_CALIBRATION)
+ {
+ /* One shot DLL calibration */
+ hrtim_dllcr &= ~(HRTIM_DLLCR_CALEN);
+ hrtim_dllcr |= HRTIM_DLLCR_CAL;
+ }
+ else
+ {
+ /* Periodic DLL calibration */
+ hrtim_dllcr &= ~(HRTIM_DLLCR_CALRTE | HRTIM_DLLCR_CAL);
+ hrtim_dllcr |= (CalibrationRate | HRTIM_DLLCR_CALEN);
+ }
+
+ /* Update HRTIM register */
+ hhrtim->Instance->sCommonRegs.DLLCR = hrtim_dllcr;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Polls the DLL calibration ready flag and returns when the flag is
+ * set (DLL calibration completed) or upon timeout expiration
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param Timeout Timeout duration in millisecond
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t Timeout)
+{
+ uint32_t tickstart=0U;
+
+ tickstart = HAL_GetTick();
+
+ /* Check End of conversion flag */
+ while(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_IT_DLLRDY) == RESET)
+ {
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ hhrtim->State = HAL_HRTIM_STATE_ERROR;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Set HRTIM State */
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the time base unit of a timer
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_MASTER for master timer
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param pTimeBaseCfg pointer to the time base configuration structure
+ * @note This function must be called prior starting the timer
+ * @note The time-base unit initialization parameters specify:
+ * The timer counter operating mode (continuous, one shot),
+ * The timer clock prescaler,
+ * The timer period,
+ * The timer repetition counter.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
+ assert_param(IS_HRTIM_PRESCALERRATIO(pTimeBaseCfg->PrescalerRatio));
+ assert_param(IS_HRTIM_MODE(pTimeBaseCfg->Mode));
+
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Set the HRTIM state */
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
+ {
+ /* Configure master timer time base unit */
+ HRTIM_MasterBase_Config(hhrtim, pTimeBaseCfg);
+ }
+ else
+ {
+ /* Configure timing unit time base unit */
+ HRTIM_TimingUnitBase_Config(hhrtim, TimerIdx, pTimeBaseCfg);
+ }
+
+ /* Set HRTIM state */
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Exported_Functions_Group2 Simple time base mode functions
+ * @brief Simple time base mode functions.
+@verbatim
+ ===============================================================================
+ ##### Simple time base mode functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Start simple time base
+ (+) Stop simple time base
+ (+) Start simple time base and enable interrupt
+ (+) Stop simple time base and disable interrupt
+ (+) Start simple time base and enable DMA transfer
+ (+) Stop simple time base and disable DMA transfer
+ -@- When a HRTIM timer operates in simple time base mode, the timer
+ counter counts from 0 to the period value.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Starts the counter of a timer operating in simple time base mode.
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index.
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_MASTER for master timer
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Enable the timer counter */
+ __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the counter of a timer operating in simple time base mode.
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index.
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_MASTER for master timer
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Disable the timer counter */
+ __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the counter of a timer operating in simple time base mode
+ * (Timer repetition interrupt is enabled).
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index.
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_MASTER for master timer
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Enable the repetition interrupt */
+ if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
+ {
+ __HAL_HRTIM_MASTER_ENABLE_IT(hhrtim, HRTIM_MASTER_IT_MREP);
+ }
+ else
+ {
+ __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
+ }
+
+ /* Enable the timer counter */
+ __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the counter of a timer operating in simple time base mode
+ * (Timer repetition interrupt is disabled).
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index.
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_MASTER for master timer
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Disable the repetition interrupt */
+ if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
+ {
+ __HAL_HRTIM_MASTER_DISABLE_IT(hhrtim, HRTIM_MASTER_IT_MREP);
+ }
+ else
+ {
+ __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
+ }
+
+ /* Disable the timer counter */
+ __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the counter of a timer operating in simple time base mode
+ * (Timer repetition DMA request is enabled).
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index.
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_MASTER for master timer
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param SrcAddr DMA transfer source address
+ * @param DestAddr DMA transfer destination address
+ * @param Length The length of data items (data size) to be transferred
+ * from source to destination
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t SrcAddr,
+ uint32_t DestAddr,
+ uint32_t Length)
+{
+ DMA_HandleTypeDef * hdma;
+
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
+
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ if(hhrtim->State == HAL_HRTIM_STATE_READY)
+ {
+ if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+ }
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ /* Get the timer DMA handler */
+ hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
+
+ if (hdma == NULL)
+ {
+ hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_ERROR;
+ }
+
+ /* Set the DMA transfer completed callback */
+ if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
+ {
+ hdma->XferCpltCallback = HRTIM_DMAMasterCplt;
+ }
+ else
+ {
+ hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
+ }
+
+ /* Set the DMA error callback */
+ hdma->XferErrorCallback = HRTIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length);
+
+ /* Enable the timer repetition DMA request */
+ if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
+ {
+ __HAL_HRTIM_MASTER_ENABLE_DMA(hhrtim, HRTIM_MASTER_DMA_MREP);
+ }
+ else
+ {
+ __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP);
+ }
+
+ /* Enable the timer counter */
+ __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the counter of a timer operating in simple time base mode
+ * (Timer repetition DMA request is disabled).
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index.
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_MASTER for master timer
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ DMA_HandleTypeDef * hdma;
+
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
+ {
+ /* Disable the DMA */
+ HAL_DMA_Abort(hhrtim->hdmaMaster);
+
+ /* Disable the timer repetition DMA request */
+ __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim, HRTIM_MASTER_DMA_MREP);
+ }
+ else
+ {
+ /* Get the timer DMA handler */
+ hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
+
+ if (hdma == NULL)
+ {
+ /* Disable the timer repetition DMA request */
+ __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP);
+
+ /* Disable the timer counter */
+ __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Disable the DMA */
+ HAL_DMA_Abort(hdma);
+
+ /* Disable the timer repetition DMA request */
+ __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP);
+ }
+ }
+
+ /* Disable the timer counter */
+ __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Exported_Functions_Group3 Simple output compare mode functions
+ * @brief Simple output compare functions
+@verbatim
+ ===============================================================================
+ ##### Simple output compare functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure simple output channel
+ (+) Start simple output compare
+ (+) Stop simple output compare
+ (+) Start simple output compare and enable interrupt
+ (+) Stop simple output compare and disable interrupt
+ (+) Start simple output compare and enable DMA transfer
+ (+) Stop simple output compare and disable DMA transfer
+ -@- When a HRTIM timer operates in simple output compare mode
+ the output level is set to a programmable value when a match
+ is found between the compare register and the counter.
+ Compare unit 1 is automatically associated to output 1
+ Compare unit 2 is automatically associated to output 2
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures an output in simple output compare mode
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param OCChannel Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @param pSimpleOCChannelCfg pointer to the simple output compare output configuration structure
+ * @note When the timer operates in simple output compare mode:
+ * Output 1 is implicitly controlled by the compare unit 1
+ * Output 2 is implicitly controlled by the compare unit 2
+ * Output Set/Reset crossbar is set according to the selected output compare mode:
+ * Toggle: SETxyR = RSTxyR = CMPy
+ * Active: SETxyR = CMPy, RSTxyR = 0
+ * Inactive: SETxy =0, RSTxy = CMPy
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OCChannel,
+ HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg)
+{
+ uint32_t CompareUnit = 0xFFFFFFFFU;
+ HRTIM_CompareCfgTypeDef CompareCfg = {0};
+ HRTIM_OutputCfgTypeDef OutputCfg = {0};
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
+ assert_param(IS_HRTIM_BASICOCMODE(pSimpleOCChannelCfg->Mode));
+ assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimpleOCChannelCfg->Polarity));
+ assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimpleOCChannelCfg->IdleLevel));
+
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Set HRTIM state */
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Configure timer compare unit */
+ switch (OCChannel)
+ {
+ case HRTIM_OUTPUT_TA1:
+ case HRTIM_OUTPUT_TB1:
+ case HRTIM_OUTPUT_TC1:
+ case HRTIM_OUTPUT_TD1:
+ case HRTIM_OUTPUT_TE1:
+ {
+ CompareUnit = HRTIM_COMPAREUNIT_1;
+ }
+ break;
+ case HRTIM_OUTPUT_TA2:
+ case HRTIM_OUTPUT_TB2:
+ case HRTIM_OUTPUT_TC2:
+ case HRTIM_OUTPUT_TD2:
+ case HRTIM_OUTPUT_TE2:
+ {
+ CompareUnit = HRTIM_COMPAREUNIT_2;
+ }
+ break;
+ default:
+ break;
+ }
+
+ CompareCfg.CompareValue = pSimpleOCChannelCfg->Pulse;
+ CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR;
+ CompareCfg.AutoDelayedTimeout = 0U;
+
+ HRTIM_CompareUnitConfig(hhrtim,
+ TimerIdx,
+ CompareUnit,
+ &CompareCfg);
+
+ /* Configure timer output */
+ OutputCfg.Polarity = pSimpleOCChannelCfg->Polarity;
+ OutputCfg.IdleLevel = pSimpleOCChannelCfg->IdleLevel;
+ OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
+ OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
+ OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
+ OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
+
+ switch (pSimpleOCChannelCfg->Mode)
+ {
+ case HRTIM_BASICOCMODE_TOGGLE:
+ {
+ if (CompareUnit == HRTIM_COMPAREUNIT_1)
+ {
+ OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
+ }
+ else
+ {
+ OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
+ }
+ OutputCfg.ResetSource = OutputCfg.SetSource;
+ }
+ break;
+ case HRTIM_BASICOCMODE_ACTIVE:
+ {
+ if (CompareUnit == HRTIM_COMPAREUNIT_1)
+ {
+ OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
+ }
+ else
+ {
+ OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
+ }
+ OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
+ }
+ break;
+ case HRTIM_BASICOCMODE_INACTIVE:
+ {
+ if (CompareUnit == HRTIM_COMPAREUNIT_1)
+ {
+ OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP1;
+ }
+ else
+ {
+ OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP2;
+ }
+ OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
+ }
+ break;
+ default:
+ break;
+ }
+
+ HRTIM_OutputConfig(hhrtim,
+ TimerIdx,
+ OCChannel,
+ &OutputCfg);
+
+ /* Set HRTIM state */
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the output compare signal generation on the designed timer output
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param OCChannel Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OCChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Enable the timer output */
+ hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
+
+ /* Enable the timer counter */
+ __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the output compare signal generation on the designed timer output
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param OCChannel Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OCChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Disable the timer output */
+ hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
+
+ /* Disable the timer counter */
+ __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the output compare signal generation on the designed timer output
+ * (Interrupt is enabled (see note note below)).
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param OCChannel Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @note Interrupt enabling depends on the chosen output compare mode
+ * Output toggle: compare match interrupt is enabled
+ * Output set active: output set interrupt is enabled
+ * Output set inactive: output reset interrupt is enabled
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OCChannel)
+{
+ uint32_t interrupt;
+
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Get the interrupt to enable (depends on the output compare mode) */
+ interrupt = HRTIM_GetITFromOCMode(hhrtim, TimerIdx, OCChannel);
+
+ /* Enable the timer output */
+ hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
+
+ /* Enable the timer interrupt (depends on the output compare mode) */
+ __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, interrupt);
+
+ /* Enable the timer counter */
+ __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the output compare signal generation on the designed timer output
+ * (Interrupt is disabled).
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param OCChannel Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OCChannel)
+{
+ uint32_t interrupt;
+
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Disable the timer output */
+ hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
+
+ /* Get the interrupt to disable (depends on the output compare mode) */
+ interrupt = HRTIM_GetITFromOCMode(hhrtim, TimerIdx, OCChannel);
+
+ /* Disable the timer interrupt */
+ __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, interrupt);
+
+ /* Disable the timer counter */
+ __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the output compare signal generation on the designed timer output
+ * (DMA request is enabled (see note below)).
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param OCChannel Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @param SrcAddr DMA transfer source address
+ * @param DestAddr DMA transfer destination address
+ * @param Length The length of data items (data size) to be transferred
+ * from source to destination
+ * @note DMA request enabling depends on the chosen output compare mode
+ * Output toggle: compare match DMA request is enabled
+ * Output set active: output set DMA request is enabled
+ * Output set inactive: output reset DMA request is enabled
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OCChannel,
+ uint32_t SrcAddr,
+ uint32_t DestAddr,
+ uint32_t Length)
+{
+ DMA_HandleTypeDef * hdma;
+ uint32_t dma_request;
+
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
+
+ if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ if((hhrtim->State == HAL_HRTIM_STATE_READY))
+ {
+ if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+ }
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ /* Enable the timer output */
+ hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
+
+ /* Get the DMA request to enable */
+ dma_request = HRTIM_GetDMAFromOCMode(hhrtim, TimerIdx, OCChannel);
+
+ /* Get the timer DMA handler */
+ hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
+
+ if (hdma == NULL)
+ {
+ hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_ERROR;
+ }
+
+ /* Set the DMA error callback */
+ hdma->XferErrorCallback = HRTIM_DMAError ;
+
+ /* Set the DMA transfer completed callback */
+ hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length);
+
+ /* Enable the timer DMA request */
+ __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, dma_request);
+
+ /* Enable the timer counter */
+ __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the output compare signal generation on the designed timer output
+ * (DMA request is disabled).
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param OCChannel Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OCChannel)
+{
+ DMA_HandleTypeDef * hdma;
+ uint32_t dma_request;
+
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Disable the timer output */
+ hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
+
+ /* Get the timer DMA handler */
+ hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
+
+ if (hdma == NULL)
+ {
+ hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_ERROR;
+ }
+
+ /* Disable the DMA */
+ HAL_DMA_Abort(hdma);
+
+ /* Get the DMA request to disable */
+ dma_request = HRTIM_GetDMAFromOCMode(hhrtim, TimerIdx, OCChannel);
+
+ /* Disable the timer DMA request */
+ __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, dma_request);
+
+ /* Disable the timer counter */
+ __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Exported_Functions_Group4 Simple PWM output mode functions
+ * @brief Simple PWM output functions
+@verbatim
+ ===============================================================================
+ ##### Simple PWM output functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure simple PWM output channel
+ (+) Start simple PWM output
+ (+) Stop simple PWM output
+ (+) Start simple PWM output and enable interrupt
+ (+) Stop simple PWM output and disable interrupt
+ (+) Start simple PWM output and enable DMA transfer
+ (+) Stop simple PWM output and disable DMA transfer
+ -@- When a HRTIM timer operates in simple PWM output mode
+ the output level is set to a programmable value when a match is
+ found between the compare register and the counter and reset when
+ the timer period is reached. Duty cycle is determined by the
+ comparison value.
+ Compare unit 1 is automatically associated to output 1
+ Compare unit 2 is automatically associated to output 2
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures an output in simple PWM mode
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param PWMChannel Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @param pSimplePWMChannelCfg pointer to the simple PWM output configuration structure
+ * @note When the timer operates in simple PWM output mode:
+ * Output 1 is implicitly controlled by the compare unit 1
+ * Output 2 is implicitly controlled by the compare unit 2
+ * Output Set/Reset crossbar is set as follows:
+ * Output 1: SETx1R = CMP1, RSTx1R = PER
+ * Output 2: SETx2R = CMP2, RST2R = PER
+ * @note When Simple PWM mode is used the registers preload mechanism is
+ * enabled (otherwise the behavior is not guaranteed).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t PWMChannel,
+ HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg)
+{
+ uint32_t CompareUnit = 0xFFFFFFFFU;
+ HRTIM_CompareCfgTypeDef CompareCfg;
+ HRTIM_OutputCfgTypeDef OutputCfg;
+ uint32_t hrtim_timcr;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
+ assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimplePWMChannelCfg->Polarity));
+ assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimplePWMChannelCfg->IdleLevel));
+
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Configure timer compare unit */
+ switch (PWMChannel)
+ {
+ case HRTIM_OUTPUT_TA1:
+ case HRTIM_OUTPUT_TB1:
+ case HRTIM_OUTPUT_TC1:
+ case HRTIM_OUTPUT_TD1:
+ case HRTIM_OUTPUT_TE1:
+ {
+ CompareUnit = HRTIM_COMPAREUNIT_1;
+ }
+ break;
+ case HRTIM_OUTPUT_TA2:
+ case HRTIM_OUTPUT_TB2:
+ case HRTIM_OUTPUT_TC2:
+ case HRTIM_OUTPUT_TD2:
+ case HRTIM_OUTPUT_TE2:
+ {
+ CompareUnit = HRTIM_COMPAREUNIT_2;
+ }
+ break;
+ default:
+ break;
+ }
+
+ CompareCfg.CompareValue = pSimplePWMChannelCfg->Pulse;
+ CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR;
+ CompareCfg.AutoDelayedTimeout = 0U;
+
+ HRTIM_CompareUnitConfig(hhrtim,
+ TimerIdx,
+ CompareUnit,
+ &CompareCfg);
+
+ /* Configure timer output */
+ OutputCfg.Polarity = pSimplePWMChannelCfg->Polarity;
+ OutputCfg.IdleLevel = pSimplePWMChannelCfg->IdleLevel;
+ OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
+ OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
+ OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
+ OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
+
+ if (CompareUnit == HRTIM_COMPAREUNIT_1)
+ {
+ OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
+ }
+ else
+ {
+ OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
+ }
+ OutputCfg.ResetSource = HRTIM_OUTPUTSET_TIMPER;
+
+ HRTIM_OutputConfig(hhrtim,
+ TimerIdx,
+ PWMChannel,
+ &OutputCfg);
+
+ /* Enable the registers preload mechanism */
+ hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
+ hrtim_timcr |= HRTIM_TIMCR_PREEN;
+ hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the PWM output signal generation on the designed timer output
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param PWMChannel Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t PWMChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Enable the timer output */
+ hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
+
+ /* Enable the timer counter */
+ __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the PWM output signal generation on the designed timer output
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param PWMChannel Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t PWMChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Disable the timer output */
+ hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
+
+ /* Disable the timer counter */
+ __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the PWM output signal generation on the designed timer output
+ * (The compare interrupt is enabled).
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param PWMChannel Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t PWMChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Enable the timer output */
+ hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
+
+ /* Enable the timer interrupt (depends on the PWM output) */
+ switch (PWMChannel)
+ {
+ case HRTIM_OUTPUT_TA1:
+ case HRTIM_OUTPUT_TB1:
+ case HRTIM_OUTPUT_TC1:
+ case HRTIM_OUTPUT_TD1:
+ case HRTIM_OUTPUT_TE1:
+ {
+ __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
+ }
+ break;
+ case HRTIM_OUTPUT_TA2:
+ case HRTIM_OUTPUT_TB2:
+ case HRTIM_OUTPUT_TC2:
+ case HRTIM_OUTPUT_TD2:
+ case HRTIM_OUTPUT_TE2:
+ {
+ __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* Enable the timer counter */
+ __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the PWM output signal generation on the designed timer output
+ * (The compare interrupt is disabled).
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param PWMChannel Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t PWMChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Disable the timer output */
+ hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
+
+ /* Disable the timer interrupt (depends on the PWM output) */
+ switch (PWMChannel)
+ {
+ case HRTIM_OUTPUT_TA1:
+ case HRTIM_OUTPUT_TB1:
+ case HRTIM_OUTPUT_TC1:
+ case HRTIM_OUTPUT_TD1:
+ case HRTIM_OUTPUT_TE1:
+ {
+ __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
+ }
+ break;
+ case HRTIM_OUTPUT_TA2:
+ case HRTIM_OUTPUT_TB2:
+ case HRTIM_OUTPUT_TC2:
+ case HRTIM_OUTPUT_TD2:
+ case HRTIM_OUTPUT_TE2:
+ {
+ __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* Disable the timer counter */
+ __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the PWM output signal generation on the designed timer output
+ * (The compare DMA request is enabled).
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param PWMChannel Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @param SrcAddr DMA transfer source address
+ * @param DestAddr DMA transfer destination address
+ * @param Length The length of data items (data size) to be transferred
+ * from source to destination
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t PWMChannel,
+ uint32_t SrcAddr,
+ uint32_t DestAddr,
+ uint32_t Length)
+{
+ DMA_HandleTypeDef * hdma;
+
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
+
+ if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ if((hhrtim->State == HAL_HRTIM_STATE_READY))
+ {
+ if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+ }
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ /* Enable the timer output */
+ hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
+
+ /* Get the timer DMA handler */
+ hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
+
+ if (hdma == NULL)
+ {
+ hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_ERROR;
+ }
+
+ /* Set the DMA error callback */
+ hdma->XferErrorCallback = HRTIM_DMAError ;
+
+ /* Set the DMA transfer completed callback */
+ hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length);
+
+ /* Enable the timer DMA request */
+ switch (PWMChannel)
+ {
+ case HRTIM_OUTPUT_TA1:
+ case HRTIM_OUTPUT_TB1:
+ case HRTIM_OUTPUT_TC1:
+ case HRTIM_OUTPUT_TD1:
+ case HRTIM_OUTPUT_TE1:
+ {
+ __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP1);
+ }
+ break;
+ case HRTIM_OUTPUT_TA2:
+ case HRTIM_OUTPUT_TB2:
+ case HRTIM_OUTPUT_TC2:
+ case HRTIM_OUTPUT_TD2:
+ case HRTIM_OUTPUT_TE2:
+ {
+ __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2);
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* Enable the timer counter */
+ __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the PWM output signal generation on the designed timer output
+ * (The compare DMA request is disabled).
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param PWMChannel Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t PWMChannel)
+{
+ DMA_HandleTypeDef * hdma;
+
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Disable the timer output */
+ hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
+
+ /* Get the timer DMA handler */
+ hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
+
+ if (hdma == NULL)
+ {
+ hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_ERROR;
+ }
+
+ /* Disable the DMA */
+ HAL_DMA_Abort(hdma);
+
+ /* Disable the timer DMA request */
+ switch (PWMChannel)
+ {
+ case HRTIM_OUTPUT_TA1:
+ case HRTIM_OUTPUT_TB1:
+ case HRTIM_OUTPUT_TC1:
+ case HRTIM_OUTPUT_TD1:
+ case HRTIM_OUTPUT_TE1:
+ {
+ __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP1);
+ }
+ break;
+ case HRTIM_OUTPUT_TA2:
+ case HRTIM_OUTPUT_TB2:
+ case HRTIM_OUTPUT_TC2:
+ case HRTIM_OUTPUT_TD2:
+ case HRTIM_OUTPUT_TE2:
+ {
+ __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2);
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* Disable the timer counter */
+ __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Exported_Functions_Group5 Simple input capture functions
+ * @brief Simple input capture functions
+@verbatim
+ ===============================================================================
+ ##### Simple input capture functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure simple input capture channel
+ (+) Start simple input capture
+ (+) Stop simple input capture
+ (+) Start simple input capture and enable interrupt
+ (+) Stop simple input capture and disable interrupt
+ (+) Start simple input capture and enable DMA transfer
+ (+) Stop simple input capture and disable DMA transfer
+ -@- When a HRTIM timer operates in simple input capture mode
+ the Capture Register (HRTIM_CPT1/2xR) is used to latch the
+ value of the timer counter counter after a transition detected
+ on a given external event input.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures a simple capture
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param CaptureChannel Capture unit
+ * This parameter can be one of the following values:
+ * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
+ * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
+ * @param pSimpleCaptureChannelCfg pointer to the simple capture configuration structure
+ * @note When the timer operates in simple capture mode the capture is trigerred
+ * by the designated external event and GPIO input is implicitly used as event source.
+ * The cature can be triggered by a rising edge, a falling edge or both
+ * edges on event channel.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureChannel,
+ HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg)
+{
+ HRTIM_EventCfgTypeDef EventCfg;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+ assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
+ assert_param(IS_HRTIM_EVENT(pSimpleCaptureChannelCfg->Event));
+ assert_param(IS_HRTIM_EVENTPOLARITY(pSimpleCaptureChannelCfg->EventSensitivity,
+ pSimpleCaptureChannelCfg->EventPolarity));
+ assert_param(IS_HRTIM_EVENTSENSITIVITY(pSimpleCaptureChannelCfg->EventSensitivity));
+ assert_param(IS_HRTIM_EVENTFILTER(pSimpleCaptureChannelCfg->Event,
+ pSimpleCaptureChannelCfg->EventFilter));
+
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Configure external event channel */
+ EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
+ EventCfg.Filter = pSimpleCaptureChannelCfg->EventFilter;
+ EventCfg.Polarity = pSimpleCaptureChannelCfg->EventPolarity;
+ EventCfg.Sensitivity = pSimpleCaptureChannelCfg->EventSensitivity;
+ EventCfg.Source = HRTIM_EVENTSRC_1;
+
+ HRTIM_EventConfig(hhrtim,
+ pSimpleCaptureChannelCfg->Event,
+ &EventCfg);
+
+ /* Memorize capture trigger (will be configured when the capture is started */
+ HRTIM_CaptureUnitConfig(hhrtim,
+ TimerIdx,
+ CaptureChannel,
+ pSimpleCaptureChannelCfg->Event);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables a simple capture on the designed capture unit
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param CaptureChannel Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
+ * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
+ * @retval HAL status
+ * @note The external event triggering the capture is available for all timing
+ * units. It can be used directly and is active as soon as the timing
+ * unit counter is enabled.
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+ assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Set the capture unit trigger */
+ switch (CaptureChannel)
+ {
+ case HRTIM_CAPTUREUNIT_1:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
+ }
+ break;
+ case HRTIM_CAPTUREUNIT_2:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* Enable the timer counter */
+ __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables a simple capture on the designed capture unit
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param CaptureChannel Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
+ * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+ assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Set the capture unit trigger */
+ switch (CaptureChannel)
+ {
+ case HRTIM_CAPTUREUNIT_1:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
+ }
+ break;
+ case HRTIM_CAPTUREUNIT_2:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* Disable the timer counter */
+ if ((hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR == HRTIM_CAPTURETRIGGER_NONE) &&
+ (hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR == HRTIM_CAPTURETRIGGER_NONE))
+ {
+ __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+ }
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables a simple capture on the designed capture unit
+ * (Capture interrupt is enabled).
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param CaptureChannel Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
+ * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+ assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Set the capture unit trigger */
+ switch (CaptureChannel)
+ {
+ case HRTIM_CAPTUREUNIT_1:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
+
+ /* Enable the capture unit 1 interrupt */
+ __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
+ }
+ break;
+ case HRTIM_CAPTUREUNIT_2:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
+
+ /* Enable the capture unit 2 interrupt */
+ __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* Enable the timer counter */
+ __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables a simple capture on the designed capture unit
+ * (Capture interrupt is disabled).
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param CaptureChannel Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
+ * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+ assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Set the capture unit trigger */
+ switch (CaptureChannel)
+ {
+ case HRTIM_CAPTUREUNIT_1:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
+
+ /* Disable the capture unit 1 interrupt */
+ __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
+ }
+ break;
+ case HRTIM_CAPTUREUNIT_2:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
+
+ /* Disable the capture unit 2 interrupt */
+ __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* Disable the timer counter */
+ if ((hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR == HRTIM_CAPTURETRIGGER_NONE) &&
+ (hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR == HRTIM_CAPTURETRIGGER_NONE))
+ {
+ __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+ }
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables a simple capture on the designed capture unit
+ * (Capture DMA request is enabled).
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param CaptureChannel Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
+ * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
+ * @param SrcAddr DMA transfer source address
+ * @param DestAddr DMA transfer destination address
+ * @param Length The length of data items (data size) to be transferred
+ * from source to destination
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureChannel,
+ uint32_t SrcAddr,
+ uint32_t DestAddr,
+ uint32_t Length)
+{
+ DMA_HandleTypeDef * hdma;
+
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+ assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Get the timer DMA handler */
+ hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
+
+ if (hdma == NULL)
+ {
+ hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_ERROR;
+ }
+
+ /* Set the DMA error callback */
+ hdma->XferErrorCallback = HRTIM_DMAError ;
+
+ /* Set the DMA transfer completed callback */
+ hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length);
+
+ switch (CaptureChannel)
+ {
+ case HRTIM_CAPTUREUNIT_1:
+ {
+ /* Set the capture unit trigger */
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
+
+ __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT1);
+ }
+ break;
+ case HRTIM_CAPTUREUNIT_2:
+ {
+ /* Set the capture unit trigger */
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
+
+ /* Enable the timer DMA request */
+ __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT2);
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* Enable the timer counter */
+ __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables a simple capture on the designed capture unit
+ * (Capture DMA request is disabled).
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param CaptureChannel Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
+ * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureChannel)
+{
+ DMA_HandleTypeDef * hdma;
+
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+ assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Get the timer DMA handler */
+ hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
+
+ if (hdma == NULL)
+ {
+ hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_ERROR;
+ }
+
+ /* Disable the DMA */
+ HAL_DMA_Abort(hdma);
+
+ switch (CaptureChannel)
+ {
+ case HRTIM_CAPTUREUNIT_1:
+ {
+ /* Reset the capture unit trigger */
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
+
+ /* Disable the capture unit 1 DMA request */
+ __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT1);
+ }
+ break;
+ case HRTIM_CAPTUREUNIT_2:
+ {
+ /* Reset the capture unit trigger */
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
+
+ /* Disable the capture unit 2 DMA request */
+ __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT2);
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* Disable the timer counter */
+ if ((hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR == HRTIM_CAPTURETRIGGER_NONE) &&
+ (hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR == HRTIM_CAPTURETRIGGER_NONE))
+ {
+ __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+ }
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Exported_Functions_Group6 Simple one pulse functions
+ * @brief Simple one pulse functions
+@verbatim
+ ===============================================================================
+ ##### Simple one pulse functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure one pulse channel
+ (+) Start one pulse generation
+ (+) Stop one pulse generation
+ (+) Start one pulse generation and enable interrupt
+ (+) Stop one pulse generation and disable interrupt
+ -@- When a HRTIM timer operates in simple one pulse mode
+ the timer counter is started in response to transition detected
+ on a given external event input to generate a pulse with a
+ programmable length after a programmable delay.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures an output simple one pulse mode
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param OnePulseChannel Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @param pSimpleOnePulseChannelCfg pointer to the simple one pulse output configuration structure
+ * @note When the timer operates in simple one pulse mode:
+ * the timer counter is implicitly started by the reset event,
+ * the reset of the timer counter is triggered by the designated external event
+ * GPIO input is implicitly used as event source,
+ * Output 1 is implicitly controlled by the compare unit 1,
+ * Output 2 is implicitly controlled by the compare unit 2.
+ * Output Set/Reset crossbar is set as follows:
+ * Output 1: SETx1R = CMP1, RSTx1R = PER
+ * Output 2: SETx2R = CMP2, RST2R = PER
+ * @retval HAL status
+ * @note If HAL_HRTIM_SimpleOnePulseChannelConfig is called for both timer
+ * outputs, the reset event related configuration data provided in the
+ * second call will override the reset event related configuration data
+ * provided in the first call.
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OnePulseChannel,
+ HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg)
+{
+ uint32_t CompareUnit = 0xFFFFFFFFU;
+ HRTIM_CompareCfgTypeDef CompareCfg;
+ HRTIM_OutputCfgTypeDef OutputCfg;
+ HRTIM_EventCfgTypeDef EventCfg;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
+ assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimpleOnePulseChannelCfg->OutputPolarity));
+ assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimpleOnePulseChannelCfg->OutputIdleLevel));
+ assert_param(IS_HRTIM_EVENT(pSimpleOnePulseChannelCfg->Event));
+ assert_param(IS_HRTIM_EVENTPOLARITY(pSimpleOnePulseChannelCfg->EventSensitivity,
+ pSimpleOnePulseChannelCfg->EventPolarity));
+ assert_param(IS_HRTIM_EVENTSENSITIVITY(pSimpleOnePulseChannelCfg->EventSensitivity));
+ assert_param(IS_HRTIM_EVENTFILTER(pSimpleOnePulseChannelCfg->Event,
+ pSimpleOnePulseChannelCfg->EventFilter));
+
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Configure timer compare unit */
+ switch (OnePulseChannel)
+ {
+ case HRTIM_OUTPUT_TA1:
+ case HRTIM_OUTPUT_TB1:
+ case HRTIM_OUTPUT_TC1:
+ case HRTIM_OUTPUT_TD1:
+ case HRTIM_OUTPUT_TE1:
+ {
+ CompareUnit = HRTIM_COMPAREUNIT_1;
+ }
+ break;
+ case HRTIM_OUTPUT_TA2:
+ case HRTIM_OUTPUT_TB2:
+ case HRTIM_OUTPUT_TC2:
+ case HRTIM_OUTPUT_TD2:
+ case HRTIM_OUTPUT_TE2:
+ {
+ CompareUnit = HRTIM_COMPAREUNIT_2;
+ }
+ break;
+ default:
+ break;
+ }
+
+ CompareCfg.CompareValue = pSimpleOnePulseChannelCfg->Pulse;
+ CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR;
+ CompareCfg.AutoDelayedTimeout = 0U;
+
+ HRTIM_CompareUnitConfig(hhrtim,
+ TimerIdx,
+ CompareUnit,
+ &CompareCfg);
+
+ /* Configure timer output */
+ OutputCfg.Polarity = pSimpleOnePulseChannelCfg->OutputPolarity;
+ OutputCfg.IdleLevel = pSimpleOnePulseChannelCfg->OutputIdleLevel;
+ OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
+ OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
+ OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
+ OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
+
+ if (CompareUnit == HRTIM_COMPAREUNIT_1)
+ {
+ OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
+ }
+ else
+ {
+ OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
+ }
+ OutputCfg.ResetSource = HRTIM_OUTPUTSET_TIMPER;
+
+ HRTIM_OutputConfig(hhrtim,
+ TimerIdx,
+ OnePulseChannel,
+ &OutputCfg);
+
+ /* Configure external event channel */
+ EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
+ EventCfg.Filter = pSimpleOnePulseChannelCfg->EventFilter;
+ EventCfg.Polarity = pSimpleOnePulseChannelCfg->EventPolarity;
+ EventCfg.Sensitivity = pSimpleOnePulseChannelCfg->EventSensitivity;
+ EventCfg.Source = HRTIM_EVENTSRC_1;
+
+ HRTIM_EventConfig(hhrtim,
+ pSimpleOnePulseChannelCfg->Event,
+ &EventCfg);
+
+ /* Configure the timer reset register */
+ HRTIM_TIM_ResetConfig(hhrtim,
+ TimerIdx,
+ pSimpleOnePulseChannelCfg->Event);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables the simple one pulse signal generation on the designed output
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param OnePulseChannel Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OnePulseChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Enable the timer output */
+ hhrtim->Instance->sCommonRegs.OENR |= OnePulseChannel;
+
+ /* Enable the timer counter */
+ __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables the simple one pulse signal generation on the designed output
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param OnePulseChannel Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OnePulseChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Disable the timer output */
+ hhrtim->Instance->sCommonRegs.ODISR |= OnePulseChannel;
+
+ /* Disable the timer counter */
+ __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables the simple one pulse signal generation on the designed output
+ * (The compare interrupt is enabled (pulse start)).
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param OnePulseChannel Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OnePulseChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Enable the timer output */
+ hhrtim->Instance->sCommonRegs.OENR |= OnePulseChannel;
+
+ /* Enable the timer interrupt (depends on the OnePulse output) */
+ switch (OnePulseChannel)
+ {
+ case HRTIM_OUTPUT_TA1:
+ case HRTIM_OUTPUT_TB1:
+ case HRTIM_OUTPUT_TC1:
+ case HRTIM_OUTPUT_TD1:
+ case HRTIM_OUTPUT_TE1:
+ {
+ __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
+ }
+ break;
+ case HRTIM_OUTPUT_TA2:
+ case HRTIM_OUTPUT_TB2:
+ case HRTIM_OUTPUT_TC2:
+ case HRTIM_OUTPUT_TD2:
+ case HRTIM_OUTPUT_TE2:
+ {
+ __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* Enable the timer counter */
+ __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables the simple one pulse signal generation on the designed output
+ * (The compare interrupt is disabled).
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param OnePulseChannel Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OnePulseChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Disable the timer output */
+ hhrtim->Instance->sCommonRegs.ODISR |= OnePulseChannel;
+
+ /* Disable the timer interrupt (depends on the OnePulse output) */
+ switch (OnePulseChannel)
+ {
+ case HRTIM_OUTPUT_TA1:
+ case HRTIM_OUTPUT_TB1:
+ case HRTIM_OUTPUT_TC1:
+ case HRTIM_OUTPUT_TD1:
+ case HRTIM_OUTPUT_TE1:
+ {
+ __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
+ }
+ break;
+ case HRTIM_OUTPUT_TA2:
+ case HRTIM_OUTPUT_TB2:
+ case HRTIM_OUTPUT_TC2:
+ case HRTIM_OUTPUT_TD2:
+ case HRTIM_OUTPUT_TE2:
+ {
+ __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* Disable the timer counter */
+ __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Exported_Functions_Group7 Configuration functions
+ * @brief HRTIM configuration functions
+@verbatim
+ ===============================================================================
+ ##### HRTIM configuration functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to configure the HRTIM
+ resources shared by all the HRTIM timers operating in waveform mode:
+ (+) Configure the burst mode controller
+ (+) Configure an external event conditionning
+ (+) Configure the external events sampling clock
+ (+) Configure a fault conditionning
+ (+) Enable or disable fault inputs
+ (+) Configure the faults sampling clock
+ (+) Configure an ADC trigger
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the burst mode feature of the HRTIM
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param pBurstModeCfg pointer to the burst mode configuration structure
+ * @retval HAL status
+ * @note This function must be called before starting the burst mode
+ * controller
+ */
+HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef * hhrtim,
+ HRTIM_BurstModeCfgTypeDef* pBurstModeCfg)
+{
+ uint32_t hrtim_bmcr;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_BURSTMODE(pBurstModeCfg->Mode));
+ assert_param(IS_HRTIM_BURSTMODECLOCKSOURCE(pBurstModeCfg->ClockSource));
+ assert_param(IS_HRTIM_HRTIM_BURSTMODEPRESCALER(pBurstModeCfg->Prescaler));
+ assert_param(IS_HRTIM_BURSTMODEPRELOAD(pBurstModeCfg->PreloadEnable));
+ assert_param(IS_HRTIM_BURSTMODETRIGGER(pBurstModeCfg->Trigger));
+
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
+
+ /* Set the burst mode operating mode */
+ hrtim_bmcr &= ~(HRTIM_BMCR_BMOM);
+ hrtim_bmcr |= pBurstModeCfg->Mode;
+
+ /* Set the burst mode clock source */
+ hrtim_bmcr &= ~(HRTIM_BMCR_BMCLK);
+ hrtim_bmcr |= pBurstModeCfg->ClockSource;
+
+ /* Set the burst mode prescaler */
+ hrtim_bmcr &= ~(HRTIM_BMCR_BMPRSC);
+ hrtim_bmcr |= pBurstModeCfg->Prescaler;
+
+ /* Enable/disable burst mode registers preload */
+ hrtim_bmcr &= ~(HRTIM_BMCR_BMPREN);
+ hrtim_bmcr |= pBurstModeCfg->PreloadEnable;
+
+ /* Set the burst mode trigger */
+ hhrtim->Instance->sCommonRegs.BMTRGR = pBurstModeCfg->Trigger;
+
+ /* Set the burst mode compare value */
+ hhrtim->Instance->sCommonRegs.BMCMPR = pBurstModeCfg->IdleDuration;
+
+ /* Set the burst mode period */
+ hhrtim->Instance->sCommonRegs.BMPER = pBurstModeCfg->Period;
+
+ /* Update the HRTIM registers */
+ hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the conditioning of an external event
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param Event external event to configure
+ * This parameter can be one of the following values:
+ * @arg HRTIM_EVENT_NONE: no external Event
+ * @arg HRTIM_EVENT_1: External event 1
+ * @arg HRTIM_EVENT_2: External event 2
+ * @arg HRTIM_EVENT_3: External event 3
+ * @arg HRTIM_EVENT_4: External event 4
+ * @arg HRTIM_EVENT_5: External event 5
+ * @arg HRTIM_EVENT_6: External event 6
+ * @arg HRTIM_EVENT_7: External event 7
+ * @arg HRTIM_EVENT_8: External event 8
+ * @arg HRTIM_EVENT_9: External event 9
+ * @arg HRTIM_EVENT_10: External event 10
+ * @param pEventCfg pointer to the event conditioning configuration structure
+ * @note This function must be called before starting the timer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t Event,
+ HRTIM_EventCfgTypeDef* pEventCfg)
+{
+ /* Check parameters */
+ assert_param(IS_HRTIM_EVENTSRC(pEventCfg->Source));
+ assert_param(IS_HRTIM_EVENTPOLARITY(pEventCfg->Sensitivity, pEventCfg->Polarity));
+ assert_param(IS_HRTIM_EVENTSENSITIVITY(pEventCfg->Sensitivity));
+ assert_param(IS_HRTIM_EVENTFASTMODE(Event, pEventCfg->FastMode));
+ assert_param(IS_HRTIM_EVENTFILTER(Event, pEventCfg->Filter));
+
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Configure the event channel */
+ HRTIM_EventConfig(hhrtim, Event, pEventCfg);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the external event conditioning block prescaler
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param Prescaler Prescaler value
+ * This parameter can be one of the following values:
+ * @arg HRTIM_EVENTPRESCALER_DIV1: fEEVS=fHRTIM
+ * @arg HRTIM_EVENTPRESCALER_DIV2: fEEVS=fHRTIM / 2
+ * @arg HRTIM_EVENTPRESCALER_DIV4: fEEVS=fHRTIM / 4
+ * @arg HRTIM_EVENTPRESCALER_DIV8: fEEVS=fHRTIM / 8
+ * @note This function must be called before starting the timer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t Prescaler)
+{
+ uint32_t hrtim_eecr3;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_EVENTPRESCALER(Prescaler));
+
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Set the external event prescaler */
+ hrtim_eecr3 = hhrtim->Instance->sCommonRegs.EECR3;
+ hrtim_eecr3 &= ~(HRTIM_EECR3_EEVSD);
+ hrtim_eecr3 |= Prescaler;
+
+ /* Update the HRTIM registers */
+ hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the conditioning of fault input
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param Fault fault input to configure
+ * This parameter can be one of the following values:
+ * @arg HRTIM_FAULT_1: Fault input 1
+ * @arg HRTIM_FAULT_2: Fault input 2
+ * @arg HRTIM_FAULT_3: Fault input 3
+ * @arg HRTIM_FAULT_4: Fault input 4
+ * @arg HRTIM_FAULT_5: Fault input 5
+ * @param pFaultCfg pointer to the fault conditioning configuration structure
+ * @note This function must be called before starting the timer and before
+ * enabling faults inputs
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t Fault,
+ HRTIM_FaultCfgTypeDef* pFaultCfg)
+{
+ uint32_t hrtim_fltinr1;
+ uint32_t hrtim_fltinr2;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_FAULT(Fault));
+ assert_param(IS_HRTIM_FAULTSOURCE(pFaultCfg->Source));
+ assert_param(IS_HRTIM_FAULTPOLARITY(pFaultCfg->Polarity));
+ assert_param(IS_HRTIM_FAULTFILTER(pFaultCfg->Filter));
+ assert_param(IS_HRTIM_FAULTLOCK(pFaultCfg->Lock));
+
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Configure fault channel */
+ hrtim_fltinr1 = hhrtim->Instance->sCommonRegs.FLTINR1;
+ hrtim_fltinr2 = hhrtim->Instance->sCommonRegs.FLTINR2;
+
+ switch (Fault)
+ {
+ case HRTIM_FAULT_1:
+ {
+ hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT1P | HRTIM_FLTINR1_FLT1SRC | HRTIM_FLTINR1_FLT1F | HRTIM_FLTINR1_FLT1LCK);
+ hrtim_fltinr1 |= pFaultCfg->Polarity;
+ hrtim_fltinr1 |= pFaultCfg->Source;
+ hrtim_fltinr1 |= pFaultCfg->Filter;
+ hrtim_fltinr1 |= pFaultCfg->Lock;
+ }
+ break;
+ case HRTIM_FAULT_2:
+ {
+ hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT2P | HRTIM_FLTINR1_FLT2SRC | HRTIM_FLTINR1_FLT2F | HRTIM_FLTINR1_FLT2LCK);
+ hrtim_fltinr1 |= (pFaultCfg->Polarity << 8U);
+ hrtim_fltinr1 |= pFaultCfg->Source << HRTIM_FLTINR1_FLT2SRC_Pos;
+ hrtim_fltinr1 |= (pFaultCfg->Filter << 8U);
+ hrtim_fltinr1 |= (pFaultCfg->Lock << 8U);
+ }
+ break;
+ case HRTIM_FAULT_3:
+ {
+ hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT3P | HRTIM_FLTINR1_FLT3SRC | HRTIM_FLTINR1_FLT3F | HRTIM_FLTINR1_FLT3LCK);
+ hrtim_fltinr1 |= (pFaultCfg->Polarity << 16U);
+ hrtim_fltinr1 |= pFaultCfg->Source << HRTIM_FLTINR1_FLT3SRC_Pos;
+ hrtim_fltinr1 |= (pFaultCfg->Filter << 16U);
+ hrtim_fltinr1 |= (pFaultCfg->Lock << 16U);
+ }
+ break;
+ case HRTIM_FAULT_4:
+ {
+ hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT4P | HRTIM_FLTINR1_FLT4SRC | HRTIM_FLTINR1_FLT4F | HRTIM_FLTINR1_FLT4LCK);
+ hrtim_fltinr1 |= (pFaultCfg->Polarity << 24U);
+ hrtim_fltinr1 |= pFaultCfg->Source << HRTIM_FLTINR1_FLT4SRC_Pos;
+ hrtim_fltinr1 |= (pFaultCfg->Filter << 24U);
+ hrtim_fltinr1 |= (pFaultCfg->Lock << 24U);
+ }
+ break;
+ case HRTIM_FAULT_5:
+ {
+ hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT5P | HRTIM_FLTINR2_FLT5SRC | HRTIM_FLTINR2_FLT5F | HRTIM_FLTINR2_FLT5LCK);
+ hrtim_fltinr2 |= pFaultCfg->Polarity;
+ hrtim_fltinr1 |= pFaultCfg->Source << HRTIM_FLTINR2_FLT5SRC_Pos;
+ hrtim_fltinr2 |= pFaultCfg->Filter;
+ hrtim_fltinr2 |= pFaultCfg->Lock;
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* Update the HRTIM registers */
+ hhrtim->Instance->sCommonRegs.FLTINR1 = hrtim_fltinr1;
+ hhrtim->Instance->sCommonRegs.FLTINR2 = hrtim_fltinr2;
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the fault conditioning block prescaler
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param Prescaler Prescaler value
+ * This parameter can be one of the following values:
+ * @arg HRTIM_FAULTPRESCALER_DIV1: fFLTS=fHRTIM
+ * @arg HRTIM_FAULTPRESCALER_DIV2: fFLTS=fHRTIM / 2
+ * @arg HRTIM_FAULTPRESCALER_DIV4: fFLTS=fHRTIM / 4
+ * @arg HRTIM_FAULTPRESCALER_DIV8: fFLTS=fHRTIM / 8
+ * @retval HAL status
+ * @note This function must be called before starting the timer and before
+ * enabling faults inputs
+ */
+HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t Prescaler)
+{
+ uint32_t hrtim_fltinr2;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_FAULTPRESCALER(Prescaler));
+
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Set the external event prescaler */
+ hrtim_fltinr2 = hhrtim->Instance->sCommonRegs.FLTINR2;
+ hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLTSD);
+ hrtim_fltinr2 |= Prescaler;
+
+ /* Update the HRTIM registers */
+ hhrtim->Instance->sCommonRegs.FLTINR2 = hrtim_fltinr2;
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables or disables the HRTIMx Fault mode.
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param Faults fault input(s) to enable or disable
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_FAULT_1: Fault input 1
+ * @arg HRTIM_FAULT_2: Fault input 2
+ * @arg HRTIM_FAULT_3: Fault input 3
+ * @arg HRTIM_FAULT_4: Fault input 4
+ * @arg HRTIM_FAULT_5: Fault input 5
+ * @param Enable Fault(s) enabling
+ * This parameter can be one of the following values:
+ * @arg HRTIM_FAULTMODECTL_ENABLED: Fault(s) enabled
+ * @arg HRTIM_FAULTMODECTL_DISABLED: Fault(s) disabled
+ * @retval None
+ */
+void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t Faults,
+ uint32_t Enable)
+{
+ uint32_t hrtim_fltinr1;
+ uint32_t hrtim_fltinr2;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_FAULT(Faults));
+ assert_param(IS_HRTIM_FAULTMODECTL(Enable));
+
+ /* Configure fault channel */
+ hrtim_fltinr1 = hhrtim->Instance->sCommonRegs.FLTINR1;
+ hrtim_fltinr2 = hhrtim->Instance->sCommonRegs.FLTINR2;
+
+ if ((Faults & HRTIM_FAULT_1) != RESET)
+ {
+ hrtim_fltinr1 &= ~HRTIM_FLTINR1_FLT1E;
+ hrtim_fltinr1 |= Enable;
+ }
+ if ((Faults & HRTIM_FAULT_2) != RESET)
+ {
+ hrtim_fltinr1 &= ~HRTIM_FLTINR1_FLT2E;
+ hrtim_fltinr1 |= (Enable << 8U);
+ }
+ if ((Faults & HRTIM_FAULT_3) != RESET)
+ {
+ hrtim_fltinr1 &= ~HRTIM_FLTINR1_FLT3E;
+ hrtim_fltinr1 |= (Enable << 16U);
+ }
+ if ((Faults & HRTIM_FAULT_4) != RESET)
+ {
+ hrtim_fltinr1 &= ~HRTIM_FLTINR1_FLT4E;
+ hrtim_fltinr1 |= (Enable << 24U);
+ }
+ if ((Faults & HRTIM_FAULT_5) != RESET)
+ {
+ hrtim_fltinr2 &= ~HRTIM_FLTINR2_FLT5E;
+ hrtim_fltinr2 |= Enable;
+ }
+
+ /* Update the HRTIMx registers */
+ hhrtim->Instance->sCommonRegs.FLTINR1 = hrtim_fltinr1;
+ hhrtim->Instance->sCommonRegs.FLTINR2 = hrtim_fltinr2;
+}
+
+/**
+ * @brief Configures both the ADC trigger register update source and the ADC
+ * trigger source.
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param ADCTrigger ADC trigger to configure
+ * This parameter can be one of the following values:
+ * @arg HRTIM_ADCTRIGGER_1: ADC trigger 1
+ * @arg HRTIM_ADCTRIGGER_2: ADC trigger 2
+ * @arg HRTIM_ADCTRIGGER_3: ADC trigger 3
+ * @arg HRTIM_ADCTRIGGER_4: ADC trigger 4
+ * @param pADCTriggerCfg pointer to the ADC trigger configuration structure
+ * @retval HAL status
+ * @note This function must be called before starting the timer
+ */
+HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t ADCTrigger,
+ HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg)
+{
+ uint32_t hrtim_cr1;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_ADCTRIGGER(ADCTrigger));
+ assert_param(IS_HRTIM_ADCTRIGGERUPDATE(pADCTriggerCfg->UpdateSource));
+
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Set the ADC trigger update source */
+ hrtim_cr1 = hhrtim->Instance->sCommonRegs.CR1;
+
+ switch (ADCTrigger)
+ {
+ case HRTIM_ADCTRIGGER_1:
+ {
+ hrtim_cr1 &= ~(HRTIM_CR1_ADC1USRC);
+ hrtim_cr1 |= (pADCTriggerCfg->UpdateSource & HRTIM_CR1_ADC1USRC);
+
+ /* Set the ADC trigger 1 source */
+ hhrtim->Instance->sCommonRegs.ADC1R = pADCTriggerCfg->Trigger;
+ }
+ break;
+ case HRTIM_ADCTRIGGER_2:
+ {
+ hrtim_cr1 &= ~(HRTIM_CR1_ADC2USRC);
+ hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 3U) & HRTIM_CR1_ADC2USRC);
+
+ /* Set the ADC trigger 2 source */
+ hhrtim->Instance->sCommonRegs.ADC2R = pADCTriggerCfg->Trigger;
+ }
+ break;
+ case HRTIM_ADCTRIGGER_3:
+ {
+ hrtim_cr1 &= ~(HRTIM_CR1_ADC3USRC);
+ hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 6U) & HRTIM_CR1_ADC3USRC);
+
+ /* Set the ADC trigger 3 source */
+ hhrtim->Instance->sCommonRegs.ADC3R = pADCTriggerCfg->Trigger;
+ }
+ break;
+ case HRTIM_ADCTRIGGER_4:
+ {
+ hrtim_cr1 &= ~(HRTIM_CR1_ADC4USRC);
+ hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 9U) & HRTIM_CR1_ADC4USRC);
+
+ /* Set the ADC trigger 4 source */
+ hhrtim->Instance->sCommonRegs.ADC4R = pADCTriggerCfg->Trigger;
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* Update the HRTIM registers */
+ hhrtim->Instance->sCommonRegs.CR1 = hrtim_cr1;
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Exported_Functions_Group8 Timer waveform configuration and functions
+ * @brief HRTIM timer configuration and control functions
+@verbatim
+ ===============================================================================
+ ##### HRTIM timer configuration and control functions #####
+ ===============================================================================
+ [..] This section provides functions used to configure and control a
+ HRTIM timer operating in waveform mode:
+ (+) Configure HRTIM timer general behavior
+ (+) Configure HRTIM timer event filtering
+ (+) Configure HRTIM timer deadtime insertion
+ (+) Configure HRTIM timer chopper mode
+ (+) Configure HRTIM timer burst DMA
+ (+) Configure HRTIM timer compare unit
+ (+) Configure HRTIM timer capture unit
+ (+) Configure HRTIM timer output
+ (+) Set HRTIM timer output level
+ (+) Enable HRTIM timer output
+ (+) Disable HRTIM timer output
+ (+) Start HRTIM timer
+ (+) Stop HRTIM timer
+ (+) Start HRTIM timer and enable interrupt
+ (+) Stop HRTIM timer and disable interrupt
+ (+) Start HRTIM timer and enable DMA transfer
+ (+) Stop HRTIM timer and disable DMA transfer
+ (+) Enable or disable the burst mode controller
+ (+) Start the burst mode controller (by software)
+ (+) Trigger a Capture (by software)
+ (+) Update the HRTIM timer preloadable registers (by software)
+ (+) Reset the HRTIM timer counter (by software)
+ (+) Start a burst DMA transfer
+ (+) Enable timer register update
+ (+) Disable timer register update
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the general behavior of a timer operating in waveform mode
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_MASTER for master timer
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param pTimerCfg pointer to the timer configuration structure
+ * @note When the timer operates in waveform mode, all the features supported by
+ * the HRTIM are available without any limitation.
+ * @retval HAL status
+ * @note This function must be called before starting the timer
+ */
+HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ HRTIM_TimerCfgTypeDef * pTimerCfg)
+{
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
+
+ /* Relevant for all HRTIM timers, including the master */
+ assert_param(IS_HRTIM_HALFMODE(pTimerCfg->HalfModeEnable));
+ assert_param(IS_HRTIM_SYNCSTART(pTimerCfg->StartOnSync));
+ assert_param(IS_HRTIM_SYNCRESET(pTimerCfg->ResetOnSync));
+ assert_param(IS_HRTIM_DACSYNC(pTimerCfg->DACSynchro));
+ assert_param(IS_HRTIM_PRELOAD(pTimerCfg->PreloadEnable));
+ assert_param(IS_HRTIM_TIMERBURSTMODE(pTimerCfg->BurstMode));
+ assert_param(IS_HRTIM_UPDATEONREPETITION(pTimerCfg->RepetitionUpdate));
+
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
+ {
+ /* Check parameters */
+ assert_param(IS_HRTIM_UPDATEGATING_MASTER(pTimerCfg->UpdateGating));
+ assert_param(IS_HRTIM_MASTER_IT(pTimerCfg->InterruptRequests));
+ assert_param(IS_HRTIM_MASTER_DMA(pTimerCfg->DMARequests));
+
+ /* Configure master timer */
+ HRTIM_MasterWaveform_Config(hhrtim, pTimerCfg);
+ }
+ else
+ {
+ /* Check parameters */
+ assert_param(IS_HRTIM_UPDATEGATING_TIM(pTimerCfg->UpdateGating));
+ assert_param(IS_HRTIM_TIM_IT(pTimerCfg->InterruptRequests));
+ assert_param(IS_HRTIM_TIM_DMA(pTimerCfg->DMARequests));
+ assert_param(IS_HRTIM_TIMPUSHPULLMODE(pTimerCfg->PushPull));
+ assert_param(IS_HRTIM_TIMFAULTENABLE(pTimerCfg->FaultEnable));
+ assert_param(IS_HRTIM_TIMFAULTLOCK(pTimerCfg->FaultLock));
+ assert_param(IS_HRTIM_TIMDEADTIMEINSERTION(pTimerCfg->PushPull,
+ pTimerCfg->DeadTimeInsertion));
+ assert_param(IS_HRTIM_TIMDELAYEDPROTECTION(pTimerCfg->PushPull,
+ pTimerCfg->DelayedProtectionMode));
+ assert_param(IS_HRTIM_TIMUPDATETRIGGER(pTimerCfg->UpdateTrigger));
+ assert_param(IS_HRTIM_TIMRESETTRIGGER(pTimerCfg->ResetTrigger));
+ assert_param(IS_HRTIM_TIMUPDATEONRESET(pTimerCfg->ResetUpdate));
+
+ /* Configure timing unit */
+ HRTIM_TimingUnitWaveform_Config(hhrtim, TimerIdx, pTimerCfg);
+ }
+
+ /* Update timer parameters */
+ hhrtim->TimerParam[TimerIdx].InterruptRequests = pTimerCfg->InterruptRequests;
+ hhrtim->TimerParam[TimerIdx].DMARequests = pTimerCfg->DMARequests;
+ hhrtim->TimerParam[TimerIdx].DMASrcAddress = pTimerCfg->DMASrcAddress;
+ hhrtim->TimerParam[TimerIdx].DMADstAddress = pTimerCfg->DMADstAddress;
+ hhrtim->TimerParam[TimerIdx].DMASize = pTimerCfg->DMASize;
+
+ /* Force a software update */
+ HRTIM_ForceRegistersUpdate(hhrtim, TimerIdx);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the event filtering capabilities of a timer (blanking, windowing)
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param Event external event for which timer event filtering must be configured
+ * This parameter can be one of the following values:
+ * @arg HRTIM_EVENT_1: External event 1
+ * @arg HRTIM_EVENT_2: External event 2
+ * @arg HRTIM_EVENT_3: External event 3
+ * @arg HRTIM_EVENT_4: External event 4
+ * @arg HRTIM_EVENT_5: External event 5
+ * @arg HRTIM_EVENT_6: External event 6
+ * @arg HRTIM_EVENT_7: External event 7
+ * @arg HRTIM_EVENT_8: External event 8
+ * @arg HRTIM_EVENT_9: External event 9
+ * @arg HRTIM_EVENT_10: External event 10
+ * @param pTimerEventFilteringCfg pointer to the timer event filtering configuration structure
+ * @note This function must be called before starting the timer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t Event,
+ HRTIM_TimerEventFilteringCfgTypeDef* pTimerEventFilteringCfg)
+{
+ uint32_t hrtim_eefr;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+ assert_param(IS_HRTIM_EVENT(Event));
+ assert_param(IS_HRTIM_TIMEVENTFILTER(pTimerEventFilteringCfg->Filter));
+ assert_param(IS_HRTIM_TIMEVENTLATCH(pTimerEventFilteringCfg->Latch));
+
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Configure timer event filtering capabilities */
+ switch (Event)
+ {
+ case HRTIM_EVENT_NONE:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = 0U;
+ hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = 0U;
+ }
+ break;
+ case HRTIM_EVENT_1:
+ {
+ hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1;
+ hrtim_eefr &= ~(HRTIM_EEFR1_EE1FLTR | HRTIM_EEFR1_EE1LTCH);
+ hrtim_eefr |= (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch);
+ hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = hrtim_eefr;
+ }
+ break;
+ case HRTIM_EVENT_2:
+ {
+ hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1;
+ hrtim_eefr &= ~(HRTIM_EEFR1_EE2FLTR | HRTIM_EEFR1_EE2LTCH);
+ hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U);
+ hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = hrtim_eefr;
+ }
+ break;
+ case HRTIM_EVENT_3:
+ {
+ hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1;
+ hrtim_eefr &= ~(HRTIM_EEFR1_EE3FLTR | HRTIM_EEFR1_EE3LTCH);
+ hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U);
+ hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = hrtim_eefr;
+ }
+ break;
+ case HRTIM_EVENT_4:
+ {
+ hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1;
+ hrtim_eefr &= ~(HRTIM_EEFR1_EE4FLTR | HRTIM_EEFR1_EE4LTCH);
+ hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U);
+ hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = hrtim_eefr;
+ }
+ break;
+ case HRTIM_EVENT_5:
+ {
+ hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1;
+ hrtim_eefr &= ~(HRTIM_EEFR1_EE5FLTR | HRTIM_EEFR1_EE5LTCH);
+ hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U);
+ hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = hrtim_eefr;
+ }
+ break;
+ case HRTIM_EVENT_6:
+ {
+ hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2;
+ hrtim_eefr &= ~(HRTIM_EEFR2_EE6FLTR | HRTIM_EEFR2_EE6LTCH);
+ hrtim_eefr |= (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch);
+ hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = hrtim_eefr;
+ }
+ break;
+ case HRTIM_EVENT_7:
+ {
+ hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2;
+ hrtim_eefr &= ~(HRTIM_EEFR2_EE7FLTR | HRTIM_EEFR2_EE7LTCH);
+ hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U);
+ hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = hrtim_eefr;
+ }
+ break;
+ case HRTIM_EVENT_8:
+ {
+ hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2;
+ hrtim_eefr &= ~(HRTIM_EEFR2_EE8FLTR | HRTIM_EEFR2_EE8LTCH);
+ hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U);
+ hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = hrtim_eefr;
+ }
+ break;
+ case HRTIM_EVENT_9:
+ {
+ hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2;
+ hrtim_eefr &= ~(HRTIM_EEFR2_EE9FLTR | HRTIM_EEFR2_EE9LTCH);
+ hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U);
+ hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = hrtim_eefr;
+ }
+ break;
+ case HRTIM_EVENT_10:
+ {
+ hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2;
+ hrtim_eefr &= ~(HRTIM_EEFR2_EE10FLTR | HRTIM_EEFR2_EE10LTCH);
+ hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U);
+ hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = hrtim_eefr;
+ }
+ break;
+ default:
+ break;
+ }
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the deadtime insertion feature for a timer
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param pDeadTimeCfg pointer to the deadtime insertion configuration structure
+ * @retval HAL status
+ * @note This function must be called before starting the timer
+ */
+HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg)
+{
+ uint32_t hrtim_dtr;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+ assert_param(IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(pDeadTimeCfg->Prescaler));
+ assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGN(pDeadTimeCfg->RisingSign));
+ assert_param(IS_HRTIM_TIMDEADTIME_RISINGLOCK(pDeadTimeCfg->RisingLock));
+ assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(pDeadTimeCfg->RisingSignLock));
+ assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGN(pDeadTimeCfg->FallingSign));
+ assert_param(IS_HRTIM_TIMDEADTIME_FALLINGLOCK(pDeadTimeCfg->FallingLock));
+ assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(pDeadTimeCfg->FallingSignLock));
+
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ hrtim_dtr = hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR;
+
+ /* Clear timer deadtime configuration */
+ hrtim_dtr &= ~(HRTIM_DTR_DTR | HRTIM_DTR_SDTR | HRTIM_DTR_DTPRSC |
+ HRTIM_DTR_DTRSLK | HRTIM_DTR_DTRLK | HRTIM_DTR_DTF |
+ HRTIM_DTR_SDTF | HRTIM_DTR_DTFSLK | HRTIM_DTR_DTFLK);
+
+ /* Set timer deadtime configuration */
+ hrtim_dtr |= pDeadTimeCfg->Prescaler;
+ hrtim_dtr |= pDeadTimeCfg->RisingValue;
+ hrtim_dtr |= pDeadTimeCfg->RisingSign;
+ hrtim_dtr |= pDeadTimeCfg->RisingSignLock;
+ hrtim_dtr |= pDeadTimeCfg->RisingLock;
+ hrtim_dtr |= (pDeadTimeCfg->FallingValue << 16U);
+ hrtim_dtr |= pDeadTimeCfg->FallingSign;
+ hrtim_dtr |= pDeadTimeCfg->FallingSignLock;
+ hrtim_dtr |= pDeadTimeCfg->FallingLock;
+
+ /* Update the HRTIM registers */
+ hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR = hrtim_dtr;
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the chopper mode feature for a timer
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param pChopperModeCfg pointer to the chopper mode configuration structure
+ * @retval HAL status
+ * @note This function must be called before configuring the timer output(s)
+ */
+HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg)
+{
+ uint32_t hrtim_chpr;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+ assert_param(IS_HRTIM_CHOPPER_PRESCALERRATIO(pChopperModeCfg->CarrierFreq));
+ assert_param(IS_HRTIM_CHOPPER_DUTYCYCLE(pChopperModeCfg->DutyCycle));
+ assert_param(IS_HRTIM_CHOPPER_PULSEWIDTH(pChopperModeCfg->StartPulse));
+
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ hrtim_chpr = hhrtim->Instance->sTimerxRegs[TimerIdx].CHPxR;
+
+ /* Clear timer chopper mode configuration */
+ hrtim_chpr &= ~(HRTIM_CHPR_CARFRQ | HRTIM_CHPR_CARDTY | HRTIM_CHPR_STRPW);
+
+ /* Set timer choppe mode configuration */
+ hrtim_chpr |= pChopperModeCfg->CarrierFreq;
+ hrtim_chpr |= (pChopperModeCfg->DutyCycle);
+ hrtim_chpr |= (pChopperModeCfg->StartPulse);
+
+ /* Update the HRTIM registers */
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CHPxR = hrtim_chpr;
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the burst DMA controller for a timer
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_MASTER for master timer
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param RegistersToUpdate registers to be written by DMA
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_BURSTDMA_CR: HRTIM_MCR or HRTIM_TIMxCR
+ * @arg HRTIM_BURSTDMA_ICR: HRTIM_MICR or HRTIM_TIMxICR
+ * @arg HRTIM_BURSTDMA_DIER: HRTIM_MDIER or HRTIM_TIMxDIER
+ * @arg HRTIM_BURSTDMA_CNT: HRTIM_MCNT or HRTIM_TIMxCNT
+ * @arg HRTIM_BURSTDMA_PER: HRTIM_MPER or HRTIM_TIMxPER
+ * @arg HRTIM_BURSTDMA_REP: HRTIM_MREP or HRTIM_TIMxREP
+ * @arg HRTIM_BURSTDMA_CMP1: HRTIM_MCMP1 or HRTIM_TIMxCMP1
+ * @arg HRTIM_BURSTDMA_CMP2: HRTIM_MCMP2 or HRTIM_TIMxCMP2
+ * @arg HRTIM_BURSTDMA_CMP3: HRTIM_MCMP3 or HRTIM_TIMxCMP3
+ * @arg HRTIM_BURSTDMA_CMP4: HRTIM_MCMP4 or HRTIM_TIMxCMP4
+ * @arg HRTIM_BURSTDMA_DTR: HRTIM_TIMxDTR
+ * @arg HRTIM_BURSTDMA_SET1R: HRTIM_TIMxSET1R
+ * @arg HRTIM_BURSTDMA_RST1R: HRTIM_TIMxRST1R
+ * @arg HRTIM_BURSTDMA_SET2R: HRTIM_TIMxSET2R
+ * @arg HRTIM_BURSTDMA_RST2R: HRTIM_TIMxRST2R
+ * @arg HRTIM_BURSTDMA_EEFR1: HRTIM_TIMxEEFR1
+ * @arg HRTIM_BURSTDMA_EEFR2: HRTIM_TIMxEEFR2
+ * @arg HRTIM_BURSTDMA_RSTR: HRTIM_TIMxRSTR
+ * @arg HRTIM_BURSTDMA_CHPR: HRTIM_TIMxCHPR
+ * @arg HRTIM_BURSTDMA_OUTR: HRTIM_TIMxOUTR
+ * @arg HRTIM_BURSTDMA_FLTR: HRTIM_TIMxFLTR
+ * @retval HAL status
+ * @note This function must be called before starting the timer
+ */
+HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t RegistersToUpdate)
+{
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMER_BURSTDMA(TimerIdx, RegistersToUpdate));
+
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Set the burst DMA timer update register */
+ switch (TimerIdx)
+ {
+ case HRTIM_TIMERINDEX_TIMER_A:
+ {
+ hhrtim->Instance->sCommonRegs.BDTAUPR = RegistersToUpdate;
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_B:
+ {
+ hhrtim->Instance->sCommonRegs.BDTBUPR = RegistersToUpdate;
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_C:
+ {
+ hhrtim->Instance->sCommonRegs.BDTCUPR = RegistersToUpdate;
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_D:
+ {
+ hhrtim->Instance->sCommonRegs.BDTDUPR = RegistersToUpdate;
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_E:
+ {
+ hhrtim->Instance->sCommonRegs.BDTEUPR = RegistersToUpdate;
+ }
+ break;
+ case HRTIM_TIMERINDEX_MASTER:
+ {
+ hhrtim->Instance->sCommonRegs.BDMUPR = RegistersToUpdate;
+ }
+ break;
+ default:
+ break;
+ }
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the compare unit of a timer operating in waveform mode
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_MASTER for master timer
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param CompareUnit Compare unit to configure
+ * This parameter can be one of the following values:
+ * @arg HRTIM_COMPAREUNIT_1: Compare unit 1
+ * @arg HRTIM_COMPAREUNIT_2: Compare unit 2
+ * @arg HRTIM_COMPAREUNIT_3: Compare unit 3
+ * @arg HRTIM_COMPAREUNIT_4: Compare unit 4
+ * @param pCompareCfg pointer to the compare unit configuration structure
+ * @note When auto delayed mode is required for compare unit 2 or compare unit 4,
+ * application has to configure separately the capture unit. Capture unit
+ * to configure in that case depends on the compare unit auto delayed mode
+ * is applied to (see below):
+ * Auto delayed on output compare 2: capture unit 1 must be configured
+ * Auto delayed on output compare 4: capture unit 2 must be configured
+ * @retval HAL status
+ * @note This function must be called before starting the timer
+ */
+HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CompareUnit,
+ HRTIM_CompareCfgTypeDef* pCompareCfg)
+{
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
+
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Configure the compare unit */
+ if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
+ {
+ switch (CompareUnit)
+ {
+ case HRTIM_COMPAREUNIT_1:
+ {
+ hhrtim->Instance->sMasterRegs.MCMP1R = pCompareCfg->CompareValue;
+ }
+ break;
+ case HRTIM_COMPAREUNIT_2:
+ {
+ hhrtim->Instance->sMasterRegs.MCMP2R = pCompareCfg->CompareValue;
+ }
+ break;
+ case HRTIM_COMPAREUNIT_3:
+ {
+ hhrtim->Instance->sMasterRegs.MCMP3R = pCompareCfg->CompareValue;
+ }
+ break;
+ case HRTIM_COMPAREUNIT_4:
+ {
+ hhrtim->Instance->sMasterRegs.MCMP4R = pCompareCfg->CompareValue;
+ }
+ break;
+ default:
+ break;
+ }
+ }
+ else
+ {
+ switch (CompareUnit)
+ {
+ case HRTIM_COMPAREUNIT_1:
+ {
+ /* Set the compare value */
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->CompareValue;
+ }
+ break;
+ case HRTIM_COMPAREUNIT_2:
+ {
+ /* Check parameters */
+ assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode));
+
+ /* Set the compare value */
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pCompareCfg->CompareValue;
+
+ if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
+ {
+ /* Configure auto-delayed mode */
+ /* DELCMP2 bitfield must be reset when reprogrammed from one value */
+ /* to the other to reinitialize properly the auto-delayed mechanism */
+ hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~HRTIM_TIMCR_DELCMP2;
+ hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR |= pCompareCfg->AutoDelayedMode;
+
+ /* Set the compare value for timeout compare unit (if any) */
+ if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
+ }
+ else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
+ }
+ }
+ }
+ break;
+ case HRTIM_COMPAREUNIT_3:
+ {
+ /* Set the compare value */
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->CompareValue;
+ }
+ break;
+ case HRTIM_COMPAREUNIT_4:
+ {
+ /* Check parameters */
+ assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode));
+
+ /* Set the compare value */
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CMP4xR = pCompareCfg->CompareValue;
+
+ if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
+ {
+ /* Configure auto-delayed mode */
+ /* DELCMP4 bitfield must be reset when reprogrammed from one value */
+ /* to the other to reinitialize properly the auto-delayed mechanism */
+ hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~HRTIM_TIMCR_DELCMP4;
+ hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR |= (pCompareCfg->AutoDelayedMode << 2U);
+
+ /* Set the compare value for timeout compare unit (if any) */
+ if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
+ }
+ else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
+ }
+ }
+ }
+ break;
+ default:
+ break;
+ }
+ }
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the capture unit of a timer operating in waveform mode
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param CaptureUnit Capture unit to configure
+ * This parameter can be one of the following values:
+ * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
+ * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
+ * @param pCaptureCfg pointer to the compare unit configuration structure
+ * @retval HAL status
+ * @note This function must be called before starting the timer
+ */
+HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureUnit,
+ HRTIM_CaptureCfgTypeDef* pCaptureCfg)
+{
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMER_CAPTURETRIGGER(TimerIdx, pCaptureCfg->Trigger));
+
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Configure the capture unit */
+ switch (CaptureUnit)
+ {
+ case HRTIM_CAPTUREUNIT_1:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = pCaptureCfg->Trigger;
+ }
+ break;
+ case HRTIM_CAPTUREUNIT_2:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = pCaptureCfg->Trigger;
+ }
+ break;
+ default:
+ break;
+ }
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the output of a timer operating in waveform mode
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param Output Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @param pOutputCfg pointer to the timer output configuration structure
+ * @retval HAL status
+ * @note This function must be called before configuring the timer and after
+ * configuring the deadtime insertion feature (if required).
+ */
+HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t Output,
+ HRTIM_OutputCfgTypeDef * pOutputCfg)
+{
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
+ assert_param(IS_HRTIM_OUTPUTPOLARITY(pOutputCfg->Polarity));
+ assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pOutputCfg->IdleLevel));
+ assert_param(IS_HRTIM_OUTPUTIDLEMODE(pOutputCfg->IdleMode));
+ assert_param(IS_HRTIM_OUTPUTFAULTLEVEL(pOutputCfg->FaultLevel));
+ assert_param(IS_HRTIM_OUTPUTCHOPPERMODE(pOutputCfg->ChopperModeEnable));
+ assert_param(IS_HRTIM_OUTPUTBURSTMODEENTRY(pOutputCfg->BurstModeEntryDelayed));
+
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Configure the timer output */
+ HRTIM_OutputConfig(hhrtim,
+ TimerIdx,
+ Output,
+ pOutputCfg);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Forces the timer output to its active or inactive state
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param Output Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @param OutputLevel indicates whether the output is forced to its active or inactive level
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUTLEVEL_ACTIVE: output is forced to its active level
+ * @arg HRTIM_OUTPUTLEVEL_INACTIVE: output is forced to its inactive level
+ * @retval HAL status
+ * @note The 'software set/reset trigger' bit in the output set/reset registers
+ * is automatically reset by hardware
+ */
+HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t Output,
+ uint32_t OutputLevel)
+{
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
+ assert_param(IS_HRTIM_OUTPUTLEVEL(OutputLevel));
+
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Force timer output level */
+ switch (Output)
+ {
+ case HRTIM_OUTPUT_TA1:
+ case HRTIM_OUTPUT_TB1:
+ case HRTIM_OUTPUT_TC1:
+ case HRTIM_OUTPUT_TD1:
+ case HRTIM_OUTPUT_TE1:
+ {
+ if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
+ {
+ /* Force output to its active state */
+ hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R |= HRTIM_SET1R_SST;
+ }
+ else
+ {
+ /* Force output to its inactive state */
+ hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R |= HRTIM_RST1R_SRT;
+ }
+ }
+ break;
+ case HRTIM_OUTPUT_TA2:
+ case HRTIM_OUTPUT_TB2:
+ case HRTIM_OUTPUT_TC2:
+ case HRTIM_OUTPUT_TD2:
+ case HRTIM_OUTPUT_TE2:
+ {
+ if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
+ {
+ /* Force output to its active state */
+ hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R |= HRTIM_SET2R_SST;
+ }
+ else
+ {
+ /* Force output to its inactive state */
+ hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R |= HRTIM_RST2R_SRT;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables the generation of the waveform signal on the designated output(s)
+ * Outputs can be combined (ORed) to allow for simultaneous output enabling.
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param OutputsToStart Timer output(s) to enable
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t OutputsToStart)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_OUTPUT(OutputsToStart));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Enable the HRTIM outputs */
+ hhrtim->Instance->sCommonRegs.OENR |= (OutputsToStart);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables the generation of the waveform signal on the designated output(s)
+ * Outputs can be combined (ORed) to allow for simultaneous output disabling.
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param OutputsToStop Timer output(s) to disable
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t OutputsToStop)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_OUTPUT(OutputsToStop));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Enable the HRTIM outputs */
+ hhrtim->Instance->sCommonRegs.ODISR |= (OutputsToStop);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the counter of the designated timer(s) operating in waveform mode
+ * Timers can be combined (ORed) to allow for simultaneous counter start.
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param Timers Timer counter(s) to start
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_TIMERID_MASTER
+ * @arg HRTIM_TIMERID_TIMER_A
+ * @arg HRTIM_TIMERID_TIMER_B
+ * @arg HRTIM_TIMERID_TIMER_C
+ * @arg HRTIM_TIMERID_TIMER_D
+ * @arg HRTIM_TIMERID_TIMER_E
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t Timers)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMERID(Timers));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Enable timer(s) counter */
+ hhrtim->Instance->sMasterRegs.MCR |= (Timers);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the counter of the designated timer(s) operating in waveform mode
+ * Timers can be combined (ORed) to allow for simultaneous counter stop.
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param Timers Timer counter(s) to stop
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_TIMERID_MASTER
+ * @arg HRTIM_TIMERID_A
+ * @arg HRTIM_TIMERID_B
+ * @arg HRTIM_TIMERID_C
+ * @arg HRTIM_TIMERID_D
+ * @arg HRTIM_TIMERID_E
+ * @retval HAL status
+ * @note The counter of a timer is stopped only if all timer outputs are disabled
+ */
+HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t Timers)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMERID(Timers));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Disable timer(s) counter */
+ hhrtim->Instance->sMasterRegs.MCR &= ~(Timers);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the counter of the designated timer(s) operating in waveform mode
+ * Timers can be combined (ORed) to allow for simultaneous counter start.
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param Timers Timer counter(s) to start
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_TIMERID_MASTER
+ * @arg HRTIM_TIMERID_A
+ * @arg HRTIM_TIMERID_B
+ * @arg HRTIM_TIMERID_C
+ * @arg HRTIM_TIMERID_D
+ * @arg HRTIM_TIMERID_E
+ * @note HRTIM interrupts (e.g. faults interrupts) and interrupts related
+ * to the timers to start are enabled within this function.
+ * Interrupts to enable are selected through HAL_HRTIM_WaveformTimerConfig
+ * function.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart_IT(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t Timers)
+{
+ uint8_t timer_idx;
+
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMERID(Timers));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Enable HRTIM interrupts (if required) */
+ __HAL_HRTIM_ENABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptResquests);
+
+ /* Enable master timer related interrupts (if required) */
+ if ((Timers & HRTIM_TIMERID_MASTER) != RESET)
+ {
+ __HAL_HRTIM_MASTER_ENABLE_IT(hhrtim,
+ hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].InterruptRequests);
+ }
+
+ /* Enable timing unit related interrupts (if required) */
+ for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
+ timer_idx < HRTIM_TIMERINDEX_MASTER ;
+ timer_idx++)
+ {
+ if ((Timers & TimerIdxToTimerId[timer_idx]) != RESET)
+ {
+ __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim,
+ timer_idx,
+ hhrtim->TimerParam[timer_idx].InterruptRequests);
+ }
+ }
+
+ /* Enable timer(s) counter */
+ hhrtim->Instance->sMasterRegs.MCR |= (Timers);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;}
+
+/**
+ * @brief Stops the counter of the designated timer(s) operating in waveform mode
+ * Timers can be combined (ORed) to allow for simultaneous counter stop.
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param Timers Timer counter(s) to stop
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_TIMERID_MASTER
+ * @arg HRTIM_TIMERID_A
+ * @arg HRTIM_TIMERID_B
+ * @arg HRTIM_TIMERID_C
+ * @arg HRTIM_TIMERID_D
+ * @arg HRTIM_TIMERID_E
+ * @retval HAL status
+ * @note The counter of a timer is stopped only if all timer outputs are disabled
+ * @note All enabled timer related interrupts are disabled.
+ */
+HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop_IT(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t Timers)
+{
+ /* ++ WA */
+ __IO uint32_t delai = (uint32_t)(0x17FU);
+ /* -- WA */
+
+ uint8_t timer_idx;
+
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMERID(Timers));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Disable HRTIM interrupts (if required) */
+ __HAL_HRTIM_DISABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptResquests);
+
+ /* Disable master timer related interrupts (if required) */
+ if ((Timers & HRTIM_TIMERID_MASTER) != RESET)
+ {
+ /* Interrupts enable flag must be cleared one by one */
+ __HAL_HRTIM_MASTER_DISABLE_IT(hhrtim, hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].InterruptRequests);
+ }
+
+ /* Disable timing unit related interrupts (if required) */
+ for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
+ timer_idx < HRTIM_TIMERINDEX_MASTER ;
+ timer_idx++)
+ {
+ if ((Timers & TimerIdxToTimerId[timer_idx]) != RESET)
+ {
+ __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, timer_idx, hhrtim->TimerParam[timer_idx].InterruptRequests);
+ }
+ }
+
+ /* ++ WA */
+ do { delai--; } while (delai != 0U);
+ /* -- WA */
+
+ /* Disable timer(s) counter */
+ hhrtim->Instance->sMasterRegs.MCR &= ~(Timers);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the counter of the designated timer(s) operating in waveform mode
+ * Timers can be combined (ORed) to allow for simultaneous counter start.
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param Timers Timer counter(s) to start
+ * This parameter can be any combination of the following values:
+ * HRTIM_TIMERID_MASTER
+ * @arg HRTIM_TIMERID_A
+ * @arg HRTIM_TIMERID_B
+ * @arg HRTIM_TIMERID_C
+ * @arg HRTIM_TIMERID_D
+ * @arg HRTIM_TIMERID_E
+ * @retval HAL status
+ * @note This function enables the dma request(s) mentionned in the timer
+ * configuration data structure for every timers to start.
+ * @note The source memory address, the destination memory address and the
+ * size of each DMA transfer are specified at timer configuration time
+ * (see HAL_HRTIM_WaveformTimerConfig)
+ */
+HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart_DMA(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t Timers)
+{
+ uint8_t timer_idx;
+ DMA_HandleTypeDef * hdma;
+
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMERID(Timers));
+
+ if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ if (((Timers & HRTIM_TIMERID_MASTER) != RESET) &&
+ (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0U))
+ {
+ /* Set the DMA error callback */
+ hhrtim->hdmaMaster->XferErrorCallback = HRTIM_DMAError ;
+
+ /* Set the DMA transfer completed callback */
+ hhrtim->hdmaMaster->XferCpltCallback = HRTIM_DMAMasterCplt;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hhrtim->hdmaMaster,
+ hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASrcAddress,
+ hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMADstAddress,
+ hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASize);
+
+ /* Enable the timer DMA request */
+ __HAL_HRTIM_MASTER_ENABLE_DMA(hhrtim,
+ hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests);
+ }
+
+ for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
+ timer_idx < HRTIM_TIMERINDEX_MASTER ;
+ timer_idx++)
+ {
+ if (((Timers & TimerIdxToTimerId[timer_idx]) != RESET) &&
+ (hhrtim->TimerParam[timer_idx].DMARequests != 0U))
+ {
+ /* Get the timer DMA handler */
+ hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx);
+
+ if (hdma == NULL)
+ {
+ hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_ERROR;
+ }
+
+ /* Set the DMA error callback */
+ hdma->XferErrorCallback = HRTIM_DMAError ;
+
+ /* Set the DMA transfer completed callback */
+ hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hdma,
+ hhrtim->TimerParam[timer_idx].DMASrcAddress,
+ hhrtim->TimerParam[timer_idx].DMADstAddress,
+ hhrtim->TimerParam[timer_idx].DMASize);
+
+ /* Enable the timer DMA request */
+ __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim,
+ timer_idx,
+ hhrtim->TimerParam[timer_idx].DMARequests);
+ }
+ }
+
+ /* Enable the timer counter */
+ __HAL_HRTIM_ENABLE(hhrtim, Timers);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the counter of the designated timer(s) operating in waveform mode
+ * Timers can be combined (ORed) to allow for simultaneous counter stop.
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param Timers Timer counter(s) to stop
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_TIMERID_MASTER
+ * @arg HRTIM_TIMERID_A
+ * @arg HRTIM_TIMERID_B
+ * @arg HRTIM_TIMERID_C
+ * @arg HRTIM_TIMERID_D
+ * @arg HRTIM_TIMERID_E
+ * @retval HAL status
+ * @note The counter of a timer is stopped only if all timer outputs are disabled
+ * @note All enabled timer related DMA requests are disabled.
+ */
+HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop_DMA(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t Timers)
+{
+ uint8_t timer_idx;
+ DMA_HandleTypeDef * hdma;
+
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMERID(Timers));
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ if (((Timers & HRTIM_TIMERID_MASTER) != RESET) &&
+ (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0U))
+ {
+ /* Disable the DMA */
+ HAL_DMA_Abort(hhrtim->hdmaMaster);
+
+ /* Disable the DMA request(s) */
+ __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim,
+ hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests);
+ }
+
+ for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
+ timer_idx < HRTIM_TIMERINDEX_MASTER ;
+ timer_idx++)
+ {
+ if (((Timers & TimerIdxToTimerId[timer_idx]) != RESET) &&
+ (hhrtim->TimerParam[timer_idx].DMARequests != 0U))
+ {
+ /* Get the timer DMA handler */
+ hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx);
+
+ if (hdma == NULL)
+ {
+ /* Disable the DMA request(s) */
+ __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim,
+ timer_idx,
+ hhrtim->TimerParam[timer_idx].DMARequests);
+
+ /* Disable the timer counter */
+ __HAL_HRTIM_DISABLE(hhrtim, Timers);
+
+ hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+
+ /* Disable the DMA */
+ HAL_DMA_Abort(hdma);
+
+ /* Disable the DMA request(s) */
+ __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim,
+ timer_idx,
+ hhrtim->TimerParam[timer_idx].DMARequests);
+ }
+ }
+
+ /* Disable the timer counter */
+ __HAL_HRTIM_DISABLE(hhrtim, Timers);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables or disables the HRTIM burst mode controller.
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param Enable Burst mode controller enabling
+ * This parameter can be one of the following values:
+ * @arg HRTIM_BURSTMODECTL_ENABLED: Burst mode enabled
+ * @arg HRTIM_BURSTMODECTL_DISABLED: Burst mode disabled
+ * @retval HAL status
+ * @note This function must be called after starting the timer(s)
+ */
+HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t Enable)
+{
+ uint32_t hrtim_bmcr;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_BURSTMODECTL(Enable));
+
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Enable/Disable the burst mode controller */
+ hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
+ hrtim_bmcr &= ~(HRTIM_BMCR_BME);
+ hrtim_bmcr |= Enable;
+
+ /* Update the HRTIM registers */
+ hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Triggers the burst mode operation.
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim)
+{
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Software trigger of the burst mode controller */
+ hhrtim->Instance->sCommonRegs.BMTRGR |= HRTIM_BMTRGR_SW;
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Triggers a software capture on the designed capture unit
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param CaptureUnit Capture unit to trig
+ * This parameter can be one of the following values:
+ * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
+ * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
+ * @retval HAL status
+ * @note The 'software capture' bit in the capure configuration register is
+ * automatically reset by hardware
+ */
+HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureUnit)
+{
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+ assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
+
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Force a software capture on concerned capture unit */
+ switch (CaptureUnit)
+ {
+ case HRTIM_CAPTUREUNIT_1:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR |= HRTIM_CPT1CR_SWCPT;
+ }
+ break;
+ case HRTIM_CAPTUREUNIT_2:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR |= HRTIM_CPT2CR_SWCPT;
+ }
+ break;
+ default:
+ break;
+ }
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Triggers the update of the registers of one or several timers
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param Timers timers concerned with the software register update
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_TIMERUPDATE_MASTER
+ * @arg HRTIM_TIMERUPDATE_A
+ * @arg HRTIM_TIMERUPDATE_B
+ * @arg HRTIM_TIMERUPDATE_C
+ * @arg HRTIM_TIMERUPDATE_D
+ * @arg HRTIM_TIMERUPDATE_E
+ * @retval HAL status
+ * @note The 'software update' bits in the HRTIM conrol register 2 register are
+ * automatically reset by hardware
+ */
+HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t Timers)
+{
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMERUPDATE(Timers));
+
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Force timer(s) registers update */
+ hhrtim->Instance->sCommonRegs.CR2 |= Timers;
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Triggers the reset of one or several timers
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param Timers timers concerned with the software counter reset
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_TIMERRESET_MASTER
+ * @arg HRTIM_TIMERRESET_TIMER_A
+ * @arg HRTIM_TIMERRESET_TIMER_B
+ * @arg HRTIM_TIMERRESET_TIMER_C
+ * @arg HRTIM_TIMERRESET_TIMER_D
+ * @arg HRTIM_TIMERRESET_TIMER_E
+ * @retval HAL status
+ * @note The 'software reset' bits in the HRTIM conrol register 2 are
+ * automatically reset by hardware
+ */
+HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t Timers)
+{
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMERRESET(Timers));
+
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Force timer(s) registers reset */
+ hhrtim->Instance->sCommonRegs.CR2 = Timers;
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts a burst DMA operation to update HRTIM control registers content
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_MASTER for master timer
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param BurstBufferAddress address of the buffer the HRTIM control registers
+ * content will be updated from.
+ * @param BurstBufferLength size (in WORDS) of the burst buffer.
+ * @retval HAL status
+ * @note The TimerIdx parameter determines the dma channel to be used by the
+ * DMA burst controller (see below)
+ * HRTIM_TIMERINDEX_MASTER: DMA channel 2 is used by the DMA burst controller
+ * HRTIM_TIMERINDEX_TIMER_A: DMA channel 3 is used by the DMA burst controller
+ * HRTIM_TIMERINDEX_TIMER_B: DMA channel 4 is used by the DMA burst controller
+ * HRTIM_TIMERINDEX_TIMER_C: DMA channel 5 is used by the DMA burst controller
+ * HRTIM_TIMERINDEX_TIMER_D: DMA channel 6 is used by the DMA burst controller
+ * HRTIM_TIMERINDEX_TIMER_E: DMA channel 7 is used by the DMA burst controller
+ */
+HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t BurstBufferAddress,
+ uint32_t BurstBufferLength)
+{
+ DMA_HandleTypeDef * hdma;
+
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
+
+ if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ if((hhrtim->State == HAL_HRTIM_STATE_READY))
+ {
+ if((BurstBufferAddress == 0U ) || (BurstBufferLength == 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+ }
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ /* Get the timer DMA handler */
+ hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
+
+ if (hdma == NULL)
+ {
+ hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_ERROR;
+ }
+
+ /* Set the DMA transfer completed callback */
+ hdma->XferCpltCallback = HRTIM_BurstDMACplt;
+
+ /* Set the DMA error callback */
+ hdma->XferErrorCallback = HRTIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hdma,
+ BurstBufferAddress,
+ (uint32_t)&(hhrtim->Instance->sCommonRegs.BDMADR),
+ BurstBufferLength);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables the transfer from preload to active registers for one
+ * or several timing units (including master timer).
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param Timers Timer(s) concerned by the register preload enabling command
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_TIMERUPDATE_MASTER
+ * @arg HRTIM_TIMERUPDATE_A
+ * @arg HRTIM_TIMERUPDATE_B
+ * @arg HRTIM_TIMERUPDATE_C
+ * @arg HRTIM_TIMERUPDATE_D
+ * @arg HRTIM_TIMERUPDATE_E
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t Timers)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMERUPDATE(Timers));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Enable timer(s) registers update */
+ hhrtim->Instance->sCommonRegs.CR1 &= ~(Timers);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+ }
+
+/**
+ * @brief Disables the transfer from preload to active registers for one
+ * or several timing units (including master timer).
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param Timers Timer(s) concerned by the register preload disabling command
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_TIMERUPDATE_MASTER
+ * @arg HRTIM_TIMERUPDATE_A
+ * @arg HRTIM_TIMERUPDATE_B
+ * @arg HRTIM_TIMERUPDATE_C
+ * @arg HRTIM_TIMERUPDATE_D
+ * @arg HRTIM_TIMERUPDATE_E
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t Timers)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMERUPDATE(Timers));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Enable timer(s) registers update */
+ hhrtim->Instance->sCommonRegs.CR1 |= (Timers);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+ }
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Exported_Functions_Group9 Peripheral state functions
+ * @brief Peripheral State functions
+@verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..] This section provides functions used to get HRTIM or HRTIM timer
+ specific information:
+ (+) Get HRTIM HAL state
+ (+) Get captured value
+ (+) Get HRTIM timer output level
+ (+) Get HRTIM timer output state
+ (+) Get delayed protection status
+ (+) Get burst status
+ (+) Get current push-pull status
+ (+) Get idle push-pull status
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief return the HRTIM HAL state
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @retval HAL state
+ */
+HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(HRTIM_HandleTypeDef* hhrtim)
+{
+ /* Return HRTIM state */
+ return hhrtim->State;
+}
+
+/**
+ * @brief Returns actual value of the capture register of the designated capture unit
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param CaptureUnit Capture unit to trig
+ * This parameter can be one of the following values:
+ * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
+ * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
+ * @retval Captured value
+ */
+uint32_t HAL_HRTIM_GetCapturedValue(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureUnit)
+{
+ uint32_t captured_value = 0U;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+ assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
+
+ /* Read captured value */
+ switch (CaptureUnit)
+ {
+ case HRTIM_CAPTUREUNIT_1:
+ {
+ captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xR;
+ }
+ break;
+ case HRTIM_CAPTUREUNIT_2:
+ {
+ captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xR;
+ }
+ break;
+ default:
+ break;
+ }
+
+ return captured_value;
+}
+
+
+/**
+ * @brief Returns actual level (active or inactive) of the designated output
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param Output Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval Output level
+ * @note Returned output level is taken before the output stage (chopper,
+ * polarity).
+ */
+uint32_t HAL_HRTIM_WaveformGetOutputLevel(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t Output)
+{
+ uint32_t output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
+
+ /* Read the output level */
+ switch (Output)
+ {
+ case HRTIM_OUTPUT_TA1:
+ case HRTIM_OUTPUT_TB1:
+ case HRTIM_OUTPUT_TC1:
+ case HRTIM_OUTPUT_TD1:
+ case HRTIM_OUTPUT_TE1:
+ {
+ if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O1CPY) != RESET)
+ {
+ output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
+ }
+ else
+ {
+ output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
+ }
+ }
+ break;
+ case HRTIM_OUTPUT_TA2:
+ case HRTIM_OUTPUT_TB2:
+ case HRTIM_OUTPUT_TC2:
+ case HRTIM_OUTPUT_TD2:
+ case HRTIM_OUTPUT_TE2:
+ {
+ if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O2CPY) != RESET)
+ {
+ output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
+ }
+ else
+ {
+ output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+
+ return output_level;
+}
+
+/**
+ * @brief Returns actual state (RUN, IDLE, FAULT) of the designated output
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param Output Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval Output state
+ */
+uint32_t HAL_HRTIM_WaveformGetOutputState(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t Output)
+{
+ uint32_t output_bit = 0U;
+ uint32_t output_state = HRTIM_OUTPUTSTATE_IDLE;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
+
+ /* Set output state according to output control status and output disable status */
+ switch (Output)
+ {
+ case HRTIM_OUTPUT_TA1:
+ {
+ output_bit = HRTIM_OENR_TA1OEN;
+ }
+ break;
+ case HRTIM_OUTPUT_TA2:
+ {
+ output_bit = HRTIM_OENR_TA2OEN;
+ }
+ break;
+ case HRTIM_OUTPUT_TB1:
+ {
+ output_bit = HRTIM_OENR_TB1OEN;
+ }
+ break;
+ case HRTIM_OUTPUT_TB2:
+ {
+ output_bit = HRTIM_OENR_TB2OEN;
+ }
+ break;
+ case HRTIM_OUTPUT_TC1:
+ {
+ output_bit = HRTIM_OENR_TC1OEN;
+ }
+ break;
+ case HRTIM_OUTPUT_TC2:
+ {
+ output_bit = HRTIM_OENR_TC2OEN;
+ }
+ break;
+ case HRTIM_OUTPUT_TD1:
+ {
+ output_bit = HRTIM_OENR_TD1OEN;
+ }
+ break;
+ case HRTIM_OUTPUT_TD2:
+ {
+ output_bit = HRTIM_OENR_TD2OEN;
+ }
+ break;
+ case HRTIM_OUTPUT_TE1:
+ {
+ output_bit = HRTIM_OENR_TE1OEN;
+ }
+ break;
+ case HRTIM_OUTPUT_TE2:
+ {
+ output_bit = HRTIM_OENR_TE2OEN;
+ }
+ break;
+ default:
+ break;
+ }
+
+ if ((hhrtim->Instance->sCommonRegs.OENR & output_bit) != RESET)
+ {
+ /* Output is enabled: output in RUN state (whatever ouput disable status is)*/
+ output_state = HRTIM_OUTPUTSTATE_RUN;
+ }
+ else
+ {
+ if ((hhrtim->Instance->sCommonRegs.ODSR & output_bit) != RESET)
+ {
+ /* Output is disabled: output in FAULT state */
+ output_state = HRTIM_OUTPUTSTATE_FAULT;
+ }
+ else
+ {
+ /* Output is disabled: output in IDLE state */
+ output_state = HRTIM_OUTPUTSTATE_IDLE;
+ }
+ }
+
+ return(output_state);
+}
+
+/**
+ * @brief Returns the level (active or inactive) of the designated output
+ * when the delayed protection was triggered.
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param Output Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval Delayed protection status
+ */
+uint32_t HAL_HRTIM_GetDelayedProtectionStatus(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t Output)
+{
+ uint32_t delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
+
+ /* Read the delayed protection status */
+ switch (Output)
+ {
+ case HRTIM_OUTPUT_TA1:
+ case HRTIM_OUTPUT_TB1:
+ case HRTIM_OUTPUT_TC1:
+ case HRTIM_OUTPUT_TD1:
+ case HRTIM_OUTPUT_TE1:
+ {
+ if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O1STAT) != RESET)
+ {
+ /* Output 1 was active when the delayed idle protection was triggered */
+ delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
+ }
+ else
+ {
+ /* Output 1 was inactive when the delayed idle protection was triggered */
+ delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
+ }
+ }
+ break;
+ case HRTIM_OUTPUT_TA2:
+ case HRTIM_OUTPUT_TB2:
+ case HRTIM_OUTPUT_TC2:
+ case HRTIM_OUTPUT_TD2:
+ case HRTIM_OUTPUT_TE2:
+ {
+ if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O2STAT) != RESET)
+ {
+ /* Output 2 was active when the delayed idle protection was triggered */
+ delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
+ }
+ else
+ {
+ /* Output 2 was inactive when the delayed idle protection was triggered */
+ delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+
+ return delayed_protection_status;
+}
+
+/**
+ * @brief Returns the actual status (active or inactive) of the burst mode controller
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @retval Burst mode controller status
+ */
+uint32_t HAL_HRTIM_GetBurstStatus(HRTIM_HandleTypeDef * hhrtim)
+{
+ uint32_t burst_mode_status;
+
+ /* Read burst mode status */
+ burst_mode_status = (hhrtim->Instance->sCommonRegs.BMCR & HRTIM_BMCR_BMSTAT);
+
+ return burst_mode_status;
+}
+
+/**
+ * @brief Indicates on which output the signal is currently active (when the
+ * push pull mode is enabled).
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @retval Burst mode controller status
+ */
+uint32_t HAL_HRTIM_GetCurrentPushPullStatus(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ uint32_t current_pushpull_status;
+
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+
+ /* Read current push pull status */
+ current_pushpull_status = (hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_CPPSTAT);
+
+ return current_pushpull_status;
+}
+
+
+/**
+ * @brief Indicates on which output the signal was applied, in push-pull mode,
+ balanced fault mode or delayed idle mode, when the protection was triggered.
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @retval Idle Push Pull Status
+ */
+uint32_t HAL_HRTIM_GetIdlePushPullStatus(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ uint32_t idle_pushpull_status;
+
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+
+ /* Read current push pull status */
+ idle_pushpull_status = (hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_IPPSTAT);
+
+ return idle_pushpull_status;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Exported_Functions_Group10 Interrupts handling
+ * @brief Functions called when HRTIM generates an interrupt
+ * 7 interrupts can be generated by the master timer:
+ * - Master timer registers update
+ * - Synchronization event received
+ * - Master timer repetition event
+ * - Master Compare 1 to 4 event
+ * 14 interrupts can be generated by each timing unit:
+ * - Delayed protection triggered
+ * - Counter reset or roll-over event
+ * - Output 1 and output 2 reset (transition active to inactive)
+ * - Output 1 and output 2 set (transition inactive to active)
+ * - Capture 1 and 2 events
+ * - Timing unit registers update
+ * - Repetition event
+ * - Compare 1 to 4 event
+ * 8 global interrupts are generated for the whole HRTIM:
+ * - System fault and Fault 1 to 5 (regardless of the timing unit attribution)
+ * - DLL calibration done
+ * - Burst mode period completed
+@verbatim
+ ===============================================================================
+ ##### HRTIM interrupts handling #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the HRTIM
+ interrupts:
+ (+) HRTIM interrupt handler
+ (+) Callback function called when Fault1 interrupt occurs
+ (+) Callback function called when Fault2 interrupt occurs
+ (+) Callback function called when Fault3 interrupt occurs
+ (+) Callback function called when Fault4 interrupt occurs
+ (+) Callback function called when Fault5 interrupt occurs
+ (+) Callback function called when system Fault interrupt occurs
+ (+) Callback function called when DLL ready interrupt occurs
+ (+) Callback function called when burst mode period interrupt occurs
+ (+) Callback function called when synchronization input interrupt occurs
+ (+) Callback function called when a timer register update interrupt occurs
+ (+) Callback function called when a timer repetition interrupt occurs
+ (+) Callback function called when a compare 1 match interrupt occurs
+ (+) Callback function called when a compare 2 match interrupt occurs
+ (+) Callback function called when a compare 3 match interrupt occurs
+ (+) Callback function called when a compare 4 match interrupt occurs
+ (+) Callback function called when a capture 1 interrupt occurs
+ (+) Callback function called when a capture 2 interrupt occurs
+ (+) Callback function called when a delayed protection interrupt occurs
+ (+) Callback function called when a timer counter reset interrupt occurs
+ (+) Callback function called when a timer output 1 set interrupt occurs
+ (+) Callback function called when a timer output 1 reset interrupt occurs
+ (+) Callback function called when a timer output 2 set interrupt occurs
+ (+) Callback function called when a timer output 2 reset interrupt occurs
+ (+) Callback function called when a timer output 2 reset interrupt occurs
+ (+) Callback function called upon completion of a burst DMA transfer
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function handles HRTIM interrupt request.
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be any value of @ref HRTIM_Timer_Index
+ * @retval None
+ */
+void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ /* HRTIM interrupts handling */
+ if (TimerIdx == HRTIM_TIMERINDEX_COMMON)
+ {
+ HRTIM_HRTIM_ISR(hhrtim);
+ }
+ else if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
+ {
+ /* Master related interrupts handling */
+ HRTIM_Master_ISR(hhrtim);
+ }
+ else
+ {
+ /* Timing unit related interrupts handling */
+ HRTIM_Timer_ISR(hhrtim, TimerIdx);
+ }
+
+}
+
+/**
+ * @brief Callback function invoked when a fault 1 interrupt occured
+ * @param hhrtim pointer to HAL HRTIM handle * @retval None
+ * @retval None
+ */
+__weak void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef * hhrtim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhrtim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_Fault1Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when a fault 2 interrupt occured
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @retval None
+ */
+__weak void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef * hhrtim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhrtim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_Fault2Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when a fault 3 interrupt occured
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @retval None
+ */
+__weak void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef * hhrtim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhrtim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_Fault3Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when a fault 4 interrupt occured
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @retval None
+ */
+__weak void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef * hhrtim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhrtim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_Fault4Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when a fault 5 interrupt occured
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @retval None
+ */
+__weak void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef * hhrtim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhrtim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_Fault5Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when a system fault interrupt occured
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @retval None
+ */
+__weak void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef * hhrtim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhrtim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_SystemFaultCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when the DLL calibration is completed
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @retval None
+ */
+__weak void HAL_HRTIM_DLLCalbrationReadyCallback(HRTIM_HandleTypeDef * hhrtim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhrtim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_DLLCalbrationCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when the end of the burst mode period is reached
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @retval None
+ */
+__weak void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef * hhrtim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhrtim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_BurstModeCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when a synchronization input event is received
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @retval None
+ */
+__weak void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef * hhrtim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhrtim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_SynchronizationEventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when timer registers are updated
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_MASTER for master timer
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @retval None
+ */
+__weak void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhrtim);
+ UNUSED(TimerIdx);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_Master_RegistersUpdateCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when timer repetition period has elapsed
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_MASTER for master timer
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @retval None
+ */
+__weak void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhrtim);
+ UNUSED(TimerIdx);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_Master_RepetitionEventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when the timer counter matches the value
+ * programmed in the compare 1 register
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_MASTER for master timer
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @retval None
+ */
+__weak void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhrtim);
+ UNUSED(TimerIdx);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_Master_Compare1EventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when the timer counter matches the value
+ * programmed in the compare 2 register
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @retval None
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_MASTER for master timer
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ */
+__weak void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhrtim);
+ UNUSED(TimerIdx);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_Master_Compare2EventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when the timer counter matches the value
+ * programmed in the compare 3 register
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_MASTER for master timer
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @retval None
+ */
+__weak void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhrtim);
+ UNUSED(TimerIdx);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_Master_Compare3EventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when the timer counter matches the value
+ * programmed in the compare 4 register.
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_MASTER for master timer
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @retval None
+ */
+__weak void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhrtim);
+ UNUSED(TimerIdx);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_Master_Compare4EventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when the timer x capture 1 event occurs
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @retval None
+ */
+__weak void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhrtim);
+ UNUSED(TimerIdx);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_Timer_Capture1EventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when the timer x capture 2 event occurs
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @retval None
+ */
+__weak void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhrtim);
+ UNUSED(TimerIdx);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_Timer_Capture2EventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when the delayed idle or balanced idle mode is
+ * entered.
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @retval None
+ */
+__weak void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhrtim);
+ UNUSED(TimerIdx);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_Timer_DelayedProtectionCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when the timer x counter reset/roll-over
+ * event occurs.
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @retval None
+ */
+__weak void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhrtim);
+ UNUSED(TimerIdx);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_Timer_CounterResetCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when the timer x output 1 is set
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @retval None
+ */
+__weak void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhrtim);
+ UNUSED(TimerIdx);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_Timer_Output1SetCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when the timer x output 1 is reset
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @retval None
+ */
+__weak void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhrtim);
+ UNUSED(TimerIdx);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_Timer_Output1ResetCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when the timer x output 2 is set
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @retval None
+ */
+__weak void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhrtim);
+ UNUSED(TimerIdx);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_Timer_Output2SetCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when the timer x output 2 is reset
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @retval None
+ */
+__weak void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhrtim);
+ UNUSED(TimerIdx);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_Timer_Output2ResetCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when a DMA burst transfer is completed
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_MASTER for master timer
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @retval None
+ */
+__weak void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhrtim);
+ UNUSED(TimerIdx);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_BurstDMATransferCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when a DMA error occurs
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @retval None
+ */
+__weak void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhrtim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup HRTIM_Private_Functions HRTIM Private Functions
+ * @{
+ */
+
+/**
+ * @brief Configures the master timer time base
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param pTimeBaseCfg pointer to the time base configuration structure
+ * @retval None
+ */
+static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim,
+ HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
+{
+ uint32_t hrtim_mcr;
+
+ /* Configure master timer */
+ hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
+
+ /* Set the prescaler ratio */
+ hrtim_mcr &= (uint32_t) ~(HRTIM_MCR_CK_PSC);
+ hrtim_mcr |= (uint32_t)pTimeBaseCfg->PrescalerRatio;
+
+ /* Set the operating mode */
+ hrtim_mcr &= (uint32_t) ~(HRTIM_MCR_CONT | HRTIM_MCR_RETRIG);
+ hrtim_mcr |= (uint32_t)pTimeBaseCfg->Mode;
+
+ /* Update the HRTIM registers */
+ hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
+ hhrtim->Instance->sMasterRegs.MPER = pTimeBaseCfg->Period;
+ hhrtim->Instance->sMasterRegs.MREP = pTimeBaseCfg->RepetitionCounter;
+}
+
+/**
+ * @brief Configures timing unit (Timer A to Timer E) time base
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * @param pTimeBaseCfg pointer to the time base configuration structure
+ * @retval None
+ */
+static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx ,
+ HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
+{
+ uint32_t hrtim_timcr;
+
+ /* Configure master timing unit */
+ hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
+
+ /* Set the prescaler ratio */
+ hrtim_timcr &= (uint32_t) ~(HRTIM_TIMCR_CK_PSC);
+ hrtim_timcr |= (uint32_t)pTimeBaseCfg->PrescalerRatio;
+
+ /* Set the operating mode */
+ hrtim_timcr &= (uint32_t) ~(HRTIM_TIMCR_CONT | HRTIM_TIMCR_RETRIG);
+ hrtim_timcr |= (uint32_t)pTimeBaseCfg->Mode;
+
+ /* Update the HRTIM registers */
+ hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
+ hhrtim->Instance->sTimerxRegs[TimerIdx].PERxR = pTimeBaseCfg->Period;
+ hhrtim->Instance->sTimerxRegs[TimerIdx].REPxR = pTimeBaseCfg->RepetitionCounter;
+}
+
+/**
+ * @brief Configures the master timer in waveform mode
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param pTimerCfg pointer to the timer configuration data structure
+ * @retval None
+ */
+static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
+ HRTIM_TimerCfgTypeDef * pTimerCfg)
+{
+ uint32_t hrtim_mcr;
+ uint32_t hrtim_bmcr;
+
+ /* Configure master timer */
+ hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
+ hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
+
+ /* Enable/Disable the half mode */
+ hrtim_mcr &= ~(HRTIM_MCR_HALF);
+ hrtim_mcr |= pTimerCfg->HalfModeEnable;
+
+ /* Enable/Disable the timer start upon synchronization event reception */
+ hrtim_mcr &= ~(HRTIM_MCR_SYNCSTRTM);
+ hrtim_mcr |= pTimerCfg->StartOnSync;
+
+ /* Enable/Disable the timer reset upon synchronization event reception */
+ hrtim_mcr &= ~(HRTIM_MCR_SYNCRSTM);
+ hrtim_mcr |= pTimerCfg->ResetOnSync;
+
+ /* Enable/Disable the DAC synchronization event generation */
+ hrtim_mcr &= ~(HRTIM_MCR_DACSYNC);
+ hrtim_mcr |= pTimerCfg->DACSynchro;
+
+ /* Enable/Disable preload meachanism for timer registers */
+ hrtim_mcr &= ~(HRTIM_MCR_PREEN);
+ hrtim_mcr |= pTimerCfg->PreloadEnable;
+
+ /* Master timer registers update handling */
+ hrtim_mcr &= ~(HRTIM_MCR_BRSTDMA);
+ hrtim_mcr |= (pTimerCfg->UpdateGating << 2U);
+
+ /* Enable/Disable registers update on repetition */
+ hrtim_mcr &= ~(HRTIM_MCR_MREPU);
+ hrtim_mcr |= pTimerCfg->RepetitionUpdate;
+
+ /* Set the timer burst mode */
+ hrtim_bmcr &= ~(HRTIM_BMCR_MTBM);
+ hrtim_bmcr |= pTimerCfg->BurstMode;
+
+ /* Update the HRTIM registers */
+ hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
+ hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
+}
+
+/**
+ * @brief Configures timing unit (Timer A to Timer E) in waveform mode
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * @param pTimerCfg pointer to the timer configuration data structure
+ * @retval None
+ */
+static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ HRTIM_TimerCfgTypeDef * pTimerCfg)
+{
+ uint32_t hrtim_timcr;
+ uint32_t hrtim_timfltr;
+ uint32_t hrtim_timoutr;
+ uint32_t hrtim_timrstr;
+ uint32_t hrtim_bmcr;
+
+ /* UPDGAT bitfield must be reset before programming a new value */
+ hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~(HRTIM_TIMCR_UPDGAT);
+
+ /* Configure timing unit (Timer A to Timer E) */
+ hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
+ hrtim_timfltr = hhrtim->Instance->sTimerxRegs[TimerIdx].FLTxR;
+ hrtim_timoutr = hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR;
+ hrtim_timrstr = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR;
+ hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
+
+ /* Enable/Disable the half mode */
+ hrtim_timcr &= ~(HRTIM_TIMCR_HALF);
+ hrtim_timcr |= pTimerCfg->HalfModeEnable;
+
+ /* Enable/Disable the timer start upon synchronization event reception */
+ hrtim_timcr &= ~(HRTIM_TIMCR_SYNCSTRT);
+ hrtim_timcr |= pTimerCfg->StartOnSync;
+
+ /* Enable/Disable the timer reset upon synchronization event reception */
+ hrtim_timcr &= ~(HRTIM_TIMCR_SYNCRST);
+ hrtim_timcr |= pTimerCfg->ResetOnSync;
+
+ /* Enable/Disable the DAC synchronization event generation */
+ hrtim_timcr &= ~(HRTIM_TIMCR_DACSYNC);
+ hrtim_timcr |= pTimerCfg->DACSynchro;
+
+ /* Enable/Disable preload meachanism for timer registers */
+ hrtim_timcr &= ~(HRTIM_TIMCR_PREEN);
+ hrtim_timcr |= pTimerCfg->PreloadEnable;
+
+ /* Timing unit registers update handling */
+ hrtim_timcr &= ~(HRTIM_TIMCR_UPDGAT);
+ hrtim_timcr |= pTimerCfg->UpdateGating;
+
+ /* Enable/Disable registers update on repetition */
+ hrtim_timcr &= ~(HRTIM_TIMCR_TREPU);
+ if (pTimerCfg->RepetitionUpdate == HRTIM_UPDATEONREPETITION_ENABLED)
+ {
+ hrtim_timcr |= HRTIM_TIMCR_TREPU;
+ }
+
+ /* Set the push-pull mode */
+ hrtim_timcr &= ~(HRTIM_TIMCR_PSHPLL);
+ hrtim_timcr |= pTimerCfg->PushPull;
+
+ /* Enable/Disable registers update on timer counter reset */
+ hrtim_timcr &= ~(HRTIM_TIMCR_TRSTU);
+ hrtim_timcr |= pTimerCfg->ResetUpdate;
+
+ /* Set the timer update trigger */
+ hrtim_timcr &= ~(HRTIM_TIMCR_TIMUPDATETRIGGER);
+ hrtim_timcr |= pTimerCfg->UpdateTrigger;
+
+ /* Enable/Disable the fault channel at timer level */
+ hrtim_timfltr &= ~(HRTIM_FLTR_FLTxEN);
+ hrtim_timfltr |= (pTimerCfg->FaultEnable & HRTIM_FLTR_FLTxEN);
+
+ /* Lock/Unlock fault sources at timer level */
+ hrtim_timfltr &= ~(HRTIM_FLTR_FLTLCK);
+ hrtim_timfltr |= pTimerCfg->FaultLock;
+
+ /* The deadtime cannot be used simultaneously with the push-pull mode */
+ if (pTimerCfg->PushPull == HRTIM_TIMPUSHPULLMODE_DISABLED)
+ {
+ /* Enable/Disable dead time insertion at timer level */
+ hrtim_timoutr &= ~(HRTIM_OUTR_DTEN);
+ hrtim_timoutr |= pTimerCfg->DeadTimeInsertion;
+ }
+
+ /* Enable/Disable delayed protection at timer level
+ Delayed Idle is available whatever the timer operating mode (regular, push-pull)
+ Balanced Idle is only available in push-pull mode
+ */
+ if ( ((pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6)
+ && (pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7))
+ || (pTimerCfg->PushPull == HRTIM_TIMPUSHPULLMODE_ENABLED))
+ {
+ hrtim_timoutr &= ~(HRTIM_OUTR_DLYPRT| HRTIM_OUTR_DLYPRTEN);
+ hrtim_timoutr |= pTimerCfg->DelayedProtectionMode;
+ }
+
+ /* Set the timer counter reset trigger */
+ hrtim_timrstr = pTimerCfg->ResetTrigger;
+
+ /* Set the timer burst mode */
+ switch (TimerIdx)
+ {
+ case HRTIM_TIMERINDEX_TIMER_A:
+ {
+ hrtim_bmcr &= ~(HRTIM_BMCR_TABM);
+ hrtim_bmcr |= ( pTimerCfg->BurstMode << 1U);
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_B:
+ {
+ hrtim_bmcr &= ~(HRTIM_BMCR_TBBM);
+ hrtim_bmcr |= ( pTimerCfg->BurstMode << 2U);
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_C:
+ {
+ hrtim_bmcr &= ~(HRTIM_BMCR_TCBM);
+ hrtim_bmcr |= ( pTimerCfg->BurstMode << 3U);
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_D:
+ {
+ hrtim_bmcr &= ~(HRTIM_BMCR_TDBM);
+ hrtim_bmcr |= ( pTimerCfg->BurstMode << 4U);
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_E:
+ {
+ hrtim_bmcr &= ~(HRTIM_BMCR_TEBM);
+ hrtim_bmcr |= ( pTimerCfg->BurstMode << 5U);
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* Update the HRTIM registers */
+ hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
+ hhrtim->Instance->sTimerxRegs[TimerIdx].FLTxR = hrtim_timfltr;
+ hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR = hrtim_timoutr;
+ hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = hrtim_timrstr;
+ hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
+}
+
+/**
+ * @brief Configures a compare unit
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * @param CompareUnit Compare unit identifier
+ * @param pCompareCfg pointer to the compare unit configuration data structure
+ * @retval None
+ */
+static void HRTIM_CompareUnitConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CompareUnit,
+ HRTIM_CompareCfgTypeDef * pCompareCfg)
+{
+ if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
+ {
+ /* Configure the compare unit of the master timer */
+ switch (CompareUnit)
+ {
+ case HRTIM_COMPAREUNIT_1:
+ {
+ hhrtim->Instance->sMasterRegs.MCMP1R = pCompareCfg->CompareValue;
+ }
+ break;
+ case HRTIM_COMPAREUNIT_2:
+ {
+ hhrtim->Instance->sMasterRegs.MCMP2R = pCompareCfg->CompareValue;
+ }
+ break;
+ case HRTIM_COMPAREUNIT_3:
+ {
+ hhrtim->Instance->sMasterRegs.MCMP3R = pCompareCfg->CompareValue;
+ }
+ break;
+ case HRTIM_COMPAREUNIT_4:
+ {
+ hhrtim->Instance->sMasterRegs.MCMP4R = pCompareCfg->CompareValue;
+ }
+ break;
+ default:
+ break;
+ }
+ }
+ else
+ {
+ /* Configure the compare unit of the timing unit */
+ switch (CompareUnit)
+ {
+ case HRTIM_COMPAREUNIT_1:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->CompareValue;
+ }
+ break;
+ case HRTIM_COMPAREUNIT_2:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pCompareCfg->CompareValue;
+ }
+ break;
+ case HRTIM_COMPAREUNIT_3:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->CompareValue;
+ }
+ break;
+ case HRTIM_COMPAREUNIT_4:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CMP4xR = pCompareCfg->CompareValue;
+ }
+ break;
+ default:
+ break;
+ }
+ }
+}
+
+/**
+ * @brief Configures a capture unit
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * @param CaptureUnit Capture unit identifier
+ * @param Event Event reference
+ * @retval None
+ */
+static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureUnit,
+ uint32_t Event)
+{
+ uint32_t CaptureTrigger = 0xFFFFFFFFU;
+
+ switch (Event)
+ {
+ case HRTIM_EVENT_1:
+ {
+ CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_1;
+ }
+ break;
+ case HRTIM_EVENT_2:
+ {
+ CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_2;
+ }
+ break;
+ case HRTIM_EVENT_3:
+ {
+ CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_3;
+ }
+ break;
+ case HRTIM_EVENT_4:
+ {
+ CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_4;
+ }
+ break;
+ case HRTIM_EVENT_5:
+ {
+ CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_5;
+ }
+ break;
+ case HRTIM_EVENT_6:
+ {
+ CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_6;
+ }
+ break;
+ case HRTIM_EVENT_7:
+ {
+ CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_7;
+ }
+ break;
+ case HRTIM_EVENT_8:
+ {
+ CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_8;
+ }
+ break;
+ case HRTIM_EVENT_9:
+ {
+ CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_9;
+ }
+ break;
+ case HRTIM_EVENT_10:
+ {
+ CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_10;
+ }
+ break;
+ default:
+ break;
+ }
+
+ switch (CaptureUnit)
+ {
+ case HRTIM_CAPTUREUNIT_1:
+ {
+ hhrtim->TimerParam[TimerIdx].CaptureTrigger1 = CaptureTrigger;
+ }
+ break;
+ case HRTIM_CAPTUREUNIT_2:
+ {
+ hhrtim->TimerParam[TimerIdx].CaptureTrigger2 = CaptureTrigger;
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Configures the output of a timing unit
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * @param Output timing unit output identifier
+ * @param pOutputCfg pointer to the output configuration data structure
+ * @retval None
+ */
+static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t Output,
+ HRTIM_OutputCfgTypeDef * pOutputCfg)
+{
+ uint32_t hrtim_outr;
+ uint32_t hrtim_dtr;
+
+ uint32_t shift = 0xFFFFFFFFU;
+
+ hrtim_outr = hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR;
+ hrtim_dtr = hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR;
+
+ switch (Output)
+ {
+ case HRTIM_OUTPUT_TA1:
+ case HRTIM_OUTPUT_TB1:
+ case HRTIM_OUTPUT_TC1:
+ case HRTIM_OUTPUT_TD1:
+ case HRTIM_OUTPUT_TE1:
+ {
+ /* Set the output set/reset crossbar */
+ hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R = pOutputCfg->SetSource;
+ hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R = pOutputCfg->ResetSource;
+
+ shift = 0U;
+ }
+ break;
+ case HRTIM_OUTPUT_TA2:
+ case HRTIM_OUTPUT_TB2:
+ case HRTIM_OUTPUT_TC2:
+ case HRTIM_OUTPUT_TD2:
+ case HRTIM_OUTPUT_TE2:
+ {
+ /* Set the output set/reset crossbar */
+ hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R = pOutputCfg->SetSource;
+ hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R = pOutputCfg->ResetSource;
+
+ shift = 16U;
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* Clear output config */
+ hrtim_outr &= ~((HRTIM_OUTR_POL1 |
+ HRTIM_OUTR_IDLM1 |
+ HRTIM_OUTR_IDLES1|
+ HRTIM_OUTR_FAULT1|
+ HRTIM_OUTR_CHP1 |
+ HRTIM_OUTR_DIDL1) << shift);
+
+ /* Set the polarity */
+ hrtim_outr |= (pOutputCfg->Polarity << shift);
+
+ /* Set the IDLE mode */
+ hrtim_outr |= (pOutputCfg->IdleMode << shift);
+
+ /* Set the IDLE state */
+ hrtim_outr |= (pOutputCfg->IdleLevel << shift);
+
+ /* Set the FAULT state */
+ hrtim_outr |= (pOutputCfg->FaultLevel << shift);
+
+ /* Set the chopper mode */
+ hrtim_outr |= (pOutputCfg->ChopperModeEnable << shift);
+
+ /* Set the burst mode entry mode : deadtime insertion when entering the idle
+ state during a burst mode operation is allowed only under the following
+ conditions:
+ - the outputs is active during the burst mode (IDLES=1U)
+ - positive deadtimes (SDTR/SDTF set to 0U)
+ */
+ if ((pOutputCfg->IdleLevel == HRTIM_OUTPUTIDLELEVEL_ACTIVE) &&
+ ((hrtim_dtr & HRTIM_DTR_SDTR) == RESET) &&
+ ((hrtim_dtr & HRTIM_DTR_SDTF) == RESET))
+ {
+ hrtim_outr |= (pOutputCfg->BurstModeEntryDelayed << shift);
+ }
+
+ /* Update HRTIM register */
+ hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR = hrtim_outr;
+}
+
+/**
+ * @brief Configures an external event channel
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param Event Event channel identifier
+ * @param pEventCfg pointer to the event channel configuration data structure
+ * @retval None
+ */
+static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t Event,
+ HRTIM_EventCfgTypeDef *pEventCfg)
+{
+ uint32_t hrtim_eecr1;
+ uint32_t hrtim_eecr2;
+ uint32_t hrtim_eecr3;
+
+ /* Configure external event channel */
+ hrtim_eecr1 = hhrtim->Instance->sCommonRegs.EECR1;
+ hrtim_eecr2 = hhrtim->Instance->sCommonRegs.EECR2;
+ hrtim_eecr3 = hhrtim->Instance->sCommonRegs.EECR3;
+
+ switch (Event)
+ {
+ case HRTIM_EVENT_NONE:
+ {
+ hrtim_eecr1 = hhrtim->Instance->sCommonRegs.EECR1 = 0U;
+ hrtim_eecr2 = hhrtim->Instance->sCommonRegs.EECR2 = 0U;
+ hrtim_eecr3 = hhrtim->Instance->sCommonRegs.EECR3 = 0U;
+ }
+ break;
+ case HRTIM_EVENT_1:
+ {
+ hrtim_eecr1 &= ~(HRTIM_EECR1_EE1SRC | HRTIM_EECR1_EE1POL | HRTIM_EECR1_EE1SNS | HRTIM_EECR1_EE1FAST);
+ hrtim_eecr1 |= pEventCfg->Source;
+ hrtim_eecr1 |= (pEventCfg->Polarity & HRTIM_EECR1_EE1POL);
+ hrtim_eecr1 |= pEventCfg->Sensitivity;
+ /* Update the HRTIM registers (all bitfields but EE1FAST bit) */
+ hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
+ /* Update the HRTIM registers (EE1FAST bit) */
+ hrtim_eecr1 |= pEventCfg->FastMode;
+ hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
+ }
+ break;
+ case HRTIM_EVENT_2:
+ {
+ hrtim_eecr1 &= ~(HRTIM_EECR1_EE2SRC | HRTIM_EECR1_EE2POL | HRTIM_EECR1_EE2SNS | HRTIM_EECR1_EE2FAST);
+ hrtim_eecr1 |= (pEventCfg->Source << 6U);
+ hrtim_eecr1 |= ((pEventCfg->Polarity << 6U) & (HRTIM_EECR1_EE2POL));
+ hrtim_eecr1 |= (pEventCfg->Sensitivity << 6U);
+ /* Update the HRTIM registers (all bitfields but EE2FAST bit) */
+ hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
+ /* Update the HRTIM registers (EE2FAST bit) */
+ hrtim_eecr1 |= (pEventCfg->FastMode << 6U);
+ hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
+ }
+ break;
+ case HRTIM_EVENT_3:
+ {
+ hrtim_eecr1 &= ~(HRTIM_EECR1_EE3SRC | HRTIM_EECR1_EE3POL | HRTIM_EECR1_EE3SNS | HRTIM_EECR1_EE3FAST);
+ hrtim_eecr1 |= (pEventCfg->Source << 12U);
+ hrtim_eecr1 |= ((pEventCfg->Polarity << 12U) & (HRTIM_EECR1_EE3POL));
+ hrtim_eecr1 |= (pEventCfg->Sensitivity << 12U);
+ /* Update the HRTIM registers (all bitfields but EE3FAST bit) */
+ hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
+ /* Update the HRTIM registers (EE3FAST bit) */
+ hrtim_eecr1 |= (pEventCfg->FastMode << 12U);
+ hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
+ }
+ break;
+ case HRTIM_EVENT_4:
+ {
+ hrtim_eecr1 &= ~(HRTIM_EECR1_EE4SRC | HRTIM_EECR1_EE4POL | HRTIM_EECR1_EE4SNS | HRTIM_EECR1_EE4FAST);
+ hrtim_eecr1 |= (pEventCfg->Source << 18U);
+ hrtim_eecr1 |= ((pEventCfg->Polarity << 18U) & (HRTIM_EECR1_EE4POL));
+ hrtim_eecr1 |= (pEventCfg->Sensitivity << 18U);
+ /* Update the HRTIM registers (all bitfields but EE4FAST bit) */
+ hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
+ /* Update the HRTIM registers (EE4FAST bit) */
+ hrtim_eecr1 |= (pEventCfg->FastMode << 18U);
+ hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
+ }
+ break;
+ case HRTIM_EVENT_5:
+ {
+ hrtim_eecr1 &= ~(HRTIM_EECR1_EE5SRC | HRTIM_EECR1_EE5POL | HRTIM_EECR1_EE5SNS | HRTIM_EECR1_EE5FAST);
+ hrtim_eecr1 |= (pEventCfg->Source << 24U);
+ hrtim_eecr1 |= ((pEventCfg->Polarity << 24U) & (HRTIM_EECR1_EE5POL));
+ hrtim_eecr1 |= (pEventCfg->Sensitivity << 24U);
+ /* Update the HRTIM registers (all bitfields but EE5FAST bit) */
+ hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
+ /* Update the HRTIM registers (EE5FAST bit) */
+ hrtim_eecr1 |= (pEventCfg->FastMode << 24U);
+ hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
+ }
+ break;
+ case HRTIM_EVENT_6:
+ {
+ hrtim_eecr2 &= ~(HRTIM_EECR2_EE6SRC | HRTIM_EECR2_EE6POL | HRTIM_EECR2_EE6SNS);
+ hrtim_eecr2 |= pEventCfg->Source;
+ hrtim_eecr2 |= (pEventCfg->Polarity & HRTIM_EECR2_EE6POL);
+ hrtim_eecr2 |= pEventCfg->Sensitivity;
+ hrtim_eecr3 &= ~(HRTIM_EECR3_EE6F);
+ hrtim_eecr3 |= pEventCfg->Filter;
+ /* Update the HRTIM registers */
+ hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
+ hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
+ }
+ break;
+ case HRTIM_EVENT_7:
+ {
+ hrtim_eecr2 &= ~(HRTIM_EECR2_EE7SRC | HRTIM_EECR2_EE7POL | HRTIM_EECR2_EE7SNS);
+ hrtim_eecr2 |= (pEventCfg->Source << 6U);
+ hrtim_eecr2 |= ((pEventCfg->Polarity << 6U) & (HRTIM_EECR2_EE7POL));
+ hrtim_eecr2 |= (pEventCfg->Sensitivity << 6U);
+ hrtim_eecr3 &= ~(HRTIM_EECR3_EE7F);
+ hrtim_eecr3 |= (pEventCfg->Filter << 6U);
+ /* Update the HRTIM registers */
+ hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
+ hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
+ }
+ break;
+ case HRTIM_EVENT_8:
+ {
+ hrtim_eecr2 &= ~(HRTIM_EECR2_EE8SRC | HRTIM_EECR2_EE8POL | HRTIM_EECR2_EE8SNS);
+ hrtim_eecr2 |= (pEventCfg->Source << 12U);
+ hrtim_eecr2 |= ((pEventCfg->Polarity << 12U) & (HRTIM_EECR2_EE8POL));
+ hrtim_eecr2 |= (pEventCfg->Sensitivity << 12U);
+ hrtim_eecr3 &= ~(HRTIM_EECR3_EE8F);
+ hrtim_eecr3 |= (pEventCfg->Filter << 12U);
+ /* Update the HRTIM registers */
+ hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
+ hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
+ }
+ break;
+ case HRTIM_EVENT_9:
+ {
+ hrtim_eecr2 &= ~(HRTIM_EECR2_EE9SRC | HRTIM_EECR2_EE9POL | HRTIM_EECR2_EE9SNS);
+ hrtim_eecr2 |= (pEventCfg->Source << 18U);
+ hrtim_eecr2 |= ((pEventCfg->Polarity << 18U) & (HRTIM_EECR2_EE9POL));
+ hrtim_eecr2 |= (pEventCfg->Sensitivity << 18U);
+ hrtim_eecr3 &= ~(HRTIM_EECR3_EE9F);
+ hrtim_eecr3 |= (pEventCfg->Filter << 18U);
+ /* Update the HRTIM registers */
+ hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
+ hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
+ }
+ break;
+ case HRTIM_EVENT_10:
+ {
+ hrtim_eecr2 &= ~(HRTIM_EECR2_EE10SRC | HRTIM_EECR2_EE10POL | HRTIM_EECR2_EE10SNS);
+ hrtim_eecr2 |= (pEventCfg->Source << 24U);
+ hrtim_eecr2 |= ((pEventCfg->Polarity << 24U) & (HRTIM_EECR2_EE10POL));
+ hrtim_eecr2 |= (pEventCfg->Sensitivity << 24U);
+ hrtim_eecr3 &= ~(HRTIM_EECR3_EE10F);
+ hrtim_eecr3 |= (pEventCfg->Filter << 24U);
+ /* Update the HRTIM registers */
+ hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
+ hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Configures the timer counter reset
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * @param Event Event channel identifier
+ * @retval None
+ */
+static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t Event)
+{
+ switch (Event)
+ {
+ case HRTIM_EVENT_1:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_1;
+ }
+ break;
+ case HRTIM_EVENT_2:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_2;
+ }
+ break;
+ case HRTIM_EVENT_3:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_3;
+ }
+ break;
+ case HRTIM_EVENT_4:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_4;
+ }
+ break;
+ case HRTIM_EVENT_5:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_5;
+ }
+ break;
+ case HRTIM_EVENT_6:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_6;
+ }
+ break;
+ case HRTIM_EVENT_7:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_7;
+ }
+ break;
+ case HRTIM_EVENT_8:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_8;
+ }
+ break;
+ case HRTIM_EVENT_9:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_9;
+ }
+ break;
+ case HRTIM_EVENT_10:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_10;
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Returns the interrupt to enable or disable according to the
+ * OC mode.
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * @param OCChannel Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval Interrupt to enable or disable
+ */
+static uint32_t HRTIM_GetITFromOCMode(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OCChannel)
+{
+ uint32_t hrtim_set;
+ uint32_t hrtim_reset;
+ uint32_t interrupt = 0U;
+
+ switch (OCChannel)
+ {
+ case HRTIM_OUTPUT_TA1:
+ case HRTIM_OUTPUT_TB1:
+ case HRTIM_OUTPUT_TC1:
+ case HRTIM_OUTPUT_TD1:
+ case HRTIM_OUTPUT_TE1:
+ {
+ /* Retreives actual OC mode and set interrupt accordingly */
+ hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R;
+ hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R;
+
+ if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
+ ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1))
+ {
+ /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
+ interrupt = HRTIM_TIM_IT_CMP1;
+ }
+ else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
+ (hrtim_reset == 0U))
+ {
+ /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
+ interrupt = HRTIM_TIM_IT_SET1;
+ }
+ else if ((hrtim_set == 0U) &&
+ ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1))
+ {
+ /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
+ interrupt = HRTIM_TIM_IT_RST1;
+ }
+ }
+ break;
+ case HRTIM_OUTPUT_TA2:
+ case HRTIM_OUTPUT_TB2:
+ case HRTIM_OUTPUT_TC2:
+ case HRTIM_OUTPUT_TD2:
+ case HRTIM_OUTPUT_TE2:
+ {
+ /* Retreives actual OC mode and set interrupt accordingly */
+ hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R;
+ hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R;
+
+ if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
+ ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2))
+ {
+ /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
+ interrupt = HRTIM_TIM_IT_CMP2;
+ }
+ else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
+ (hrtim_reset == 0U))
+ {
+ /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
+ interrupt = HRTIM_TIM_IT_SET2;
+ }
+ else if ((hrtim_set == 0U) &&
+ ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2))
+ {
+ /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
+ interrupt = HRTIM_TIM_IT_RST2;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+
+ return interrupt;
+}
+
+/**
+ * @brief Returns the DMA request to enable or disable according to the
+ * OC mode.
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * @param OCChannel Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval DMA request to enable or disable
+ */
+static uint32_t HRTIM_GetDMAFromOCMode(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OCChannel)
+{
+ uint32_t hrtim_set;
+ uint32_t hrtim_reset;
+ uint32_t dma_request = 0U;
+
+ switch (OCChannel)
+ {
+ case HRTIM_OUTPUT_TA1:
+ case HRTIM_OUTPUT_TB1:
+ case HRTIM_OUTPUT_TC1:
+ case HRTIM_OUTPUT_TD1:
+ case HRTIM_OUTPUT_TE1:
+ {
+ /* Retreives actual OC mode and set dma_request accordingly */
+ hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R;
+ hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R;
+
+ if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
+ ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1))
+ {
+ /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
+ dma_request = HRTIM_TIM_DMA_CMP1;
+ }
+ else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
+ (hrtim_reset == 0U))
+ {
+ /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
+ dma_request = HRTIM_TIM_DMA_SET1;
+ }
+ else if ((hrtim_set == 0U) &&
+ ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1))
+ {
+ /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
+ dma_request = HRTIM_TIM_DMA_RST1;
+ }
+ }
+ break;
+ case HRTIM_OUTPUT_TA2:
+ case HRTIM_OUTPUT_TB2:
+ case HRTIM_OUTPUT_TC2:
+ case HRTIM_OUTPUT_TD2:
+ case HRTIM_OUTPUT_TE2:
+ {
+ /* Retreives actual OC mode and set dma_request accordingly */
+ hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R;
+ hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R;
+
+ if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
+ ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2))
+ {
+ /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
+ dma_request = HRTIM_TIM_DMA_CMP2;
+ }
+ else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
+ (hrtim_reset == 0U))
+ {
+ /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
+ dma_request = HRTIM_TIM_DMA_SET2;
+ }
+ else if ((hrtim_set == 0U) &&
+ ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2))
+ {
+ /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
+ dma_request = HRTIM_TIM_DMA_RST2;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+
+ return dma_request;
+}
+
+static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ DMA_HandleTypeDef * hdma = (DMA_HandleTypeDef *)NULL;
+
+ switch (TimerIdx)
+ {
+ case HRTIM_TIMERINDEX_MASTER:
+ {
+ hdma = hhrtim->hdmaMaster;
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_A:
+ {
+ hdma = hhrtim->hdmaTimerA;
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_B:
+ {
+ hdma = hhrtim->hdmaTimerB;
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_C:
+ {
+ hdma = hhrtim->hdmaTimerC;
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_D:
+ {
+ hdma = hhrtim->hdmaTimerD;
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_E:
+ {
+ hdma = hhrtim->hdmaTimerE;
+ }
+ break;
+ default:
+ break;
+ }
+
+ return hdma;
+}
+
+static uint32_t GetTimerIdxFromDMAHandle(HRTIM_HandleTypeDef * hhrtim,
+ DMA_HandleTypeDef * hdma)
+{
+ uint32_t timed_idx = 0xFFFFFFFFU;
+
+ if (hdma == hhrtim->hdmaMaster)
+ {
+ timed_idx = HRTIM_TIMERINDEX_MASTER;
+ }
+ else if (hdma == hhrtim->hdmaTimerA)
+ {
+ timed_idx = HRTIM_TIMERINDEX_TIMER_A;
+ }
+ else if (hdma == hhrtim->hdmaTimerB)
+ {
+ timed_idx = HRTIM_TIMERINDEX_TIMER_B;
+ }
+ else if (hdma == hhrtim->hdmaTimerC)
+ {
+ timed_idx = HRTIM_TIMERINDEX_TIMER_C;
+ }
+ else if (hdma == hhrtim->hdmaTimerD)
+ {
+ timed_idx = HRTIM_TIMERINDEX_TIMER_D;
+ }
+ else if (hdma == hhrtim->hdmaTimerE)
+ {
+ timed_idx = HRTIM_TIMERINDEX_TIMER_E;
+ }
+
+ return timed_idx;
+}
+
+/**
+ * @brief Forces an immediate transfer from the preload to the active
+ * registers.
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * @retval None
+ */
+static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ switch (TimerIdx)
+ {
+ case HRTIM_TIMERINDEX_MASTER:
+ {
+ hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_MSWU;
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_A:
+ {
+ hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TASWU;
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_B:
+ {
+ hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TBSWU;
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_C:
+ {
+ hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TCSWU;
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_D:
+ {
+ hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TDSWU;
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_E:
+ {
+ hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TESWU;
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+
+/**
+ * @brief HRTIM interrupts service routine
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @retval None
+ */
+static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim)
+{
+ /* Fault 1 event */
+ if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT1) != RESET)
+ {
+ if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT1) != RESET)
+ {
+ __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT1);
+
+ /* Invoke Fault 1 event callback */
+ HAL_HRTIM_Fault1Callback(hhrtim);
+ }
+ }
+
+ /* Fault 2 event */
+ if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT2) != RESET)
+ {
+ if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT2) != RESET)
+ {
+ __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT2);
+
+ /* Invoke Fault 2 event callback */
+ HAL_HRTIM_Fault2Callback(hhrtim);
+ }
+ }
+
+ /* Fault 3 event */
+ if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT3) != RESET)
+ {
+ if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT3) != RESET)
+ {
+ __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT3);
+
+ /* Invoke Fault 3 event callback */
+ HAL_HRTIM_Fault3Callback(hhrtim);
+ }
+ }
+
+ /* Fault 4 event */
+ if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT4) != RESET)
+ {
+ if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT4) != RESET)
+ {
+ __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT4);
+
+ /* Invoke Fault 4 event callback */
+ HAL_HRTIM_Fault4Callback(hhrtim);
+ }
+ }
+
+ /* Fault 5 event */
+ if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT5) != RESET)
+ {
+ if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT5) != RESET)
+ {
+ __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT5);
+
+ /* Invoke Fault 5 event callback */
+ HAL_HRTIM_Fault5Callback(hhrtim);
+ }
+ }
+
+ /* System fault event */
+ if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_SYSFLT) != RESET)
+ {
+ if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_SYSFLT) != RESET)
+ {
+ __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_SYSFLT);
+
+ /* Invoke System fault event callback */
+ HAL_HRTIM_SystemFaultCallback(hhrtim);
+ }
+ }
+}
+
+/**
+* @brief Master timer interrupts service routine
+* @param hhrtim pointer to HAL HRTIM handle
+* @retval None
+*/
+static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim)
+{
+ /* DLL calibration ready event */
+ if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_DLLRDY) != RESET)
+ {
+ if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_DLLRDY) != RESET)
+ {
+ __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_DLLRDY);
+
+ /* Set HRTIM State */
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ /* Invoke System fault event callback */
+ HAL_HRTIM_DLLCalbrationReadyCallback(hhrtim);
+ }
+ }
+
+ /* Burst mode period event */
+ if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_BMPER) != RESET)
+ {
+ if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_BMPER) != RESET)
+ {
+ __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_BMPER);
+
+ /* Invoke Burst mode period event callback */
+ HAL_HRTIM_BurstModePeriodCallback(hhrtim);
+ }
+ }
+
+ /* Master timer compare 1 event */
+ if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP1) != RESET)
+ {
+ if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP1) != RESET)
+ {
+ __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP1);
+
+ /* Invoke compare 1 event callback */
+ HAL_HRTIM_Compare1EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
+ }
+ }
+
+ /* Master timer compare 2 event */
+ if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP2) != RESET)
+ {
+ if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP2) != RESET)
+ {
+ __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP2);
+
+ /* Invoke compare 2 event callback */
+ HAL_HRTIM_Compare2EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
+ }
+ }
+
+ /* Master timer compare 3 event */
+ if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP3) != RESET)
+ {
+ if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP3) != RESET)
+ {
+ __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP3);
+
+ /* Invoke compare 3 event callback */
+ HAL_HRTIM_Compare3EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
+ }
+ }
+
+ /* Master timer compare 4 event */
+ if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP4) != RESET)
+ {
+ if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP4) != RESET)
+ {
+ __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP4);
+
+ /* Invoke compare 4 event callback */
+ HAL_HRTIM_Compare4EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
+ }
+ }
+
+ /* Master timer repetition event */
+ if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MREP) != RESET)
+ {
+ if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MREP) != RESET)
+ {
+ __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MREP);
+
+ /* Invoke repetition event callback */
+ HAL_HRTIM_RepetitionEventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
+ }
+ }
+
+ /* Synchronization input event */
+ if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_SYNC) != RESET)
+ {
+ if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_SYNC) != RESET)
+ {
+ __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_SYNC);
+
+ /* Invoke synchronization event callback */
+ HAL_HRTIM_SynchronizationEventCallback(hhrtim);
+ }
+ }
+
+ /* Master timer registers update event */
+ if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MUPD) != RESET)
+ {
+ if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MUPD) != RESET)
+ {
+ __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MUPD);
+
+ /* Invoke registers update event callback */
+ HAL_HRTIM_RegistersUpdateCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
+ }
+ }
+}
+
+/**
+ * @brief Timer interrupts service routine
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @retval None
+*/
+static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ /* Timer compare 1 event */
+ if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP1) != RESET)
+ {
+ if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1) != RESET)
+ {
+ __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
+
+ /* Invoke compare 1 event callback */
+ HAL_HRTIM_Compare1EventCallback(hhrtim, TimerIdx);
+ }
+ }
+
+ /* Timer compare 2 event */
+ if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP2) != RESET)
+ {
+ if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2) != RESET)
+ {
+ __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
+
+ /* Invoke compare 2 event callback */
+ HAL_HRTIM_Compare2EventCallback(hhrtim, TimerIdx);
+ }
+ }
+
+ /* Timer compare 3 event */
+ if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP3) != RESET)
+ {
+ if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP3) != RESET)
+ {
+ __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP3);
+
+ /* Invoke compare 3 event callback */
+ HAL_HRTIM_Compare3EventCallback(hhrtim, TimerIdx);
+ }
+ }
+
+ /* Timer compare 4 event */
+ if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP4) != RESET)
+ {
+ if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP4) != RESET)
+ {
+ __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP4);
+
+ /* Invoke compare 4 event callback */
+ HAL_HRTIM_Compare4EventCallback(hhrtim, TimerIdx);
+ }
+ }
+
+ /* Timer repetition event */
+ if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_REP) != RESET)
+ {
+ if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_REP) != RESET)
+ {
+ __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
+
+ /* Invoke repetition event callback */
+ HAL_HRTIM_RepetitionEventCallback(hhrtim, TimerIdx);
+ }
+ }
+
+ /* Timer registers update event */
+ if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_UPD) != RESET)
+ {
+ if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_UPD) != RESET)
+ {
+ __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_UPD);
+
+ /* Invoke registers update event callback */
+ HAL_HRTIM_RegistersUpdateCallback(hhrtim, TimerIdx);
+ }
+ }
+
+ /* Timer capture 1 event */
+ if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CPT1) != RESET)
+ {
+ if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1) != RESET)
+ {
+ __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
+
+ /* Invoke capture 1 event callback */
+ HAL_HRTIM_Capture1EventCallback(hhrtim, TimerIdx);
+ }
+ }
+
+ /* Timer capture 2 event */
+ if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CPT2) != RESET)
+ {
+ if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2) != RESET)
+ {
+ __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
+
+ /* Invoke capture 2 event callback */
+ HAL_HRTIM_Capture2EventCallback(hhrtim, TimerIdx);
+ }
+ }
+
+ /* Timer output 1 set event */
+ if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_SET1) != RESET)
+ {
+ if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_SET1) != RESET)
+ {
+ __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET1);
+
+ /* Invoke output 1 set event callback */
+ HAL_HRTIM_Output1SetCallback(hhrtim, TimerIdx);
+ }
+ }
+
+ /* Timer output 1 reset event */
+ if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_RST1) != RESET)
+ {
+ if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_RST1) != RESET)
+ {
+ __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST1);
+
+ /* Invoke output 1 reset event callback */
+ HAL_HRTIM_Output1ResetCallback(hhrtim, TimerIdx);
+ }
+ }
+
+ /* Timer output 2 set event */
+ if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_SET2) != RESET)
+ {
+ if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_SET2) != RESET)
+ {
+ __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET2);
+
+ /* Invoke output 2 set event callback */
+ HAL_HRTIM_Output2SetCallback(hhrtim, TimerIdx);
+ }
+ }
+
+ /* Timer output 2 reset event */
+ if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_RST2) != RESET)
+ {
+ if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_RST2) != RESET)
+ {
+ __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST2);
+
+ /* Invoke output 2 reset event callback */
+ HAL_HRTIM_Output2ResetCallback(hhrtim, TimerIdx);
+ }
+ }
+
+ /* Timer reset event */
+ if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_RST) != RESET)
+ {
+ if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_RST) != RESET)
+ {
+ __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST);
+
+ /* Invoke timer reset callback */
+ HAL_HRTIM_CounterResetCallback(hhrtim, TimerIdx);
+ }
+ }
+
+ /* Delayed protection event */
+ if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_DLYPRT) != RESET)
+ {
+ if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_DLYPRT) != RESET)
+ {
+ __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_DLYPRT);
+
+ /* Invoke delayed protection callback */
+ HAL_HRTIM_DelayedProtectionCallback(hhrtim, TimerIdx);
+ }
+ }
+}
+
+/**
+ * @brief DMA callback invoked upon master timer related DMA request completion
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma)
+{
+ HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
+
+ if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP1) != RESET)
+ {
+ HAL_HRTIM_Compare1EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
+ }
+ else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP2) != RESET)
+ {
+ HAL_HRTIM_Compare2EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
+ }
+ else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP3) != RESET)
+ {
+ HAL_HRTIM_Compare3EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
+ }
+ else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP4) != RESET)
+ {
+ HAL_HRTIM_Compare4EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
+ }
+ else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MREP) != RESET)
+ {
+ HAL_HRTIM_RepetitionEventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
+ }
+ else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_SYNC) != RESET)
+ {
+ HAL_HRTIM_SynchronizationEventCallback(hrtim);
+ }
+ else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MUPD) != RESET)
+ {
+ HAL_HRTIM_RegistersUpdateCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
+ }
+}
+
+/**
+ * @brief DMA callback invoked upon timer A..E related DMA request completion
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma)
+{
+ uint8_t timer_idx;
+
+ HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
+
+ timer_idx = GetTimerIdxFromDMAHandle(hrtim, hdma);
+
+ if ( !IS_HRTIM_TIMERINDEX(timer_idx) ) return;
+
+
+ if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP1) != RESET)
+ {
+ HAL_HRTIM_Compare1EventCallback(hrtim, timer_idx);
+ }
+ else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP2) != RESET)
+ {
+ HAL_HRTIM_Compare2EventCallback(hrtim, timer_idx);
+ }
+ else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP3) != RESET)
+ {
+ HAL_HRTIM_Compare3EventCallback(hrtim, timer_idx);
+ }
+ else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP4) != RESET)
+ {
+ HAL_HRTIM_Compare4EventCallback(hrtim, timer_idx);
+ }
+ else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_REP) != RESET)
+ {
+ HAL_HRTIM_RepetitionEventCallback(hrtim, timer_idx);
+ }
+ else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_UPD) != RESET)
+ {
+ HAL_HRTIM_RegistersUpdateCallback(hrtim, timer_idx);
+ }
+ else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CPT1) != RESET)
+ {
+ HAL_HRTIM_Capture1EventCallback(hrtim, timer_idx);
+ }
+ else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CPT2) != RESET)
+ {
+ HAL_HRTIM_Capture2EventCallback(hrtim, timer_idx);
+ }
+ else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_SET1) != RESET)
+ {
+ HAL_HRTIM_Output1SetCallback(hrtim, timer_idx);
+ }
+ else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST1) != RESET)
+ {
+ HAL_HRTIM_Output1ResetCallback(hrtim, timer_idx);
+ }
+ else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_SET2) != RESET)
+ {
+ HAL_HRTIM_Output2SetCallback(hrtim, timer_idx);
+ }
+ else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST2) != RESET)
+ {
+ HAL_HRTIM_Output2ResetCallback(hrtim, timer_idx);
+ }
+ else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST) != RESET)
+ {
+ HAL_HRTIM_CounterResetCallback(hrtim, timer_idx);
+ }
+ else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_DLYPRT) != RESET)
+ {
+ HAL_HRTIM_DelayedProtectionCallback(hrtim, timer_idx);
+ }
+}
+
+/**
+* @brief DMA error callback
+* @param hdma pointer to DMA handle.
+* @retval None
+*/
+static void HRTIM_DMAError(DMA_HandleTypeDef *hdma)
+{
+ HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
+
+ HAL_HRTIM_ErrorCallback(hrtim);
+}
+
+/**
+ * @brief DMA callback invoked upon burst DMA transfer completion
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma)
+{
+ HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
+
+ HAL_HRTIM_BurstDMATransferCallback(hrtim, GetTimerIdxFromDMAHandle(hrtim, hdma));
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HRTIM1 */
+
+#endif /* HAL_HRTIM_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_i2c.c b/Src/stm32f3xx_hal_i2c.c
new file mode 100644
index 0000000..028b3f3
--- /dev/null
+++ b/Src/stm32f3xx_hal_i2c.c
@@ -0,0 +1,4874 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_i2c.c
+ * @author MCD Application Team
+ * @brief I2C HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Inter Integrated Circuit (I2C) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral State and Errors functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The I2C HAL driver can be used as follows:
+
+ (#) Declare a I2C_HandleTypeDef handle structure, for example:
+ I2C_HandleTypeDef hi2c;
+
+ (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
+ (##) Enable the I2Cx interface clock
+ (##) I2C pins configuration
+ (+++) Enable the clock for the I2C GPIOs
+ (+++) Configure I2C pins as alternate function open-drain
+ (##) NVIC configuration if you need to use interrupt process
+ (+++) Configure the I2Cx interrupt priority
+ (+++) Enable the NVIC I2C IRQ Channel
+ (##) DMA Configuration if you need to use DMA process
+ (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
+ (+++) Enable the DMAx interface clock using
+ (+++) Configure the DMA handle parameters
+ (+++) Configure the DMA Tx or Rx channel
+ (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
+ the DMA Tx or Rx channel
+
+ (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
+ Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
+
+ (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
+ (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
+
+ (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
+
+ (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
+ (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
+ (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
+ (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
+
+ *** Polling mode IO MEM operation ***
+ =====================================
+ [..]
+ (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
+ (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
+
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
+ (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
+ (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
+ (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
+ (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
+ (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
+ (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
+ (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_I2C_ErrorCallback()
+ (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+ (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
+ (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
+ This action will inform Master to generate a Stop condition to discard the communication.
+
+
+ *** Interrupt mode IO sequential operation ***
+ ==============================================
+ [..]
+ (@) These interfaces allow to manage a sequential transfer with a repeated start condition
+ when a direction change during transfer
+ [..]
+ (+) A specific option field manage the different steps of a sequential transfer
+ (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below:
+ (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
+ (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
+ and data to transfer without a final stop condition
+ (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address
+ and data to transfer without a final stop condition, an then permit a call the same master sequential interface
+ several times (like HAL_I2C_Master_Sequential_Transmit_IT() then HAL_I2C_Master_Sequential_Transmit_IT())
+ (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
+ and with new data to transfer if the direction change or manage only the new data to transfer
+ if no direction change and without a final stop condition in both cases
+ (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
+ and with new data to transfer if the direction change or manage only the new data to transfer
+ if no direction change and with a final stop condition in both cases
+ (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential
+ interface several times (link with option I2C_FIRST_AND_NEXT_FRAME).
+ Usage can, transfer several bytes one by one using HAL_I2C_Master_Sequential_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
+ or HAL_I2C_Master_Sequential_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME).
+ Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the oposite interface Receive or Transmit
+ without stopping the communication and so generate a restart condition.
+
+ (+) Differents sequential I2C interfaces are listed below:
+ (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT()
+ (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
+ (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT()
+ (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
+ (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+ (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
+ (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()
+ (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can
+ add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
+ (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_ListenCpltCallback()
+ (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT()
+ (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
+ (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT()
+ (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
+ (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_I2C_ErrorCallback()
+ (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+ (++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
+ (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
+ This action will inform Master to generate a Stop condition to discard the communication.
+
+ *** Interrupt mode IO MEM operation ***
+ =======================================
+ [..]
+ (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
+ HAL_I2C_Mem_Write_IT()
+ (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
+ (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
+ HAL_I2C_Mem_Read_IT()
+ (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_I2C_ErrorCallback()
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
+ HAL_I2C_Master_Transmit_DMA()
+ (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
+ (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
+ HAL_I2C_Master_Receive_DMA()
+ (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
+ (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
+ HAL_I2C_Slave_Transmit_DMA()
+ (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
+ (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
+ HAL_I2C_Slave_Receive_DMA()
+ (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_I2C_ErrorCallback()
+ (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+ (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
+ (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
+ This action will inform Master to generate a Stop condition to discard the communication.
+
+ *** DMA mode IO MEM operation ***
+ =================================
+ [..]
+ (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
+ HAL_I2C_Mem_Write_DMA()
+ (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
+ (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
+ HAL_I2C_Mem_Read_DMA()
+ (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_I2C_ErrorCallback()
+
+
+ *** I2C HAL driver macros list ***
+ ==================================
+ [..]
+ Below the list of most used macros in I2C HAL driver.
+
+ (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
+ (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
+ (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
+ (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
+ (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
+ (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
+ (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
+
+ [..]
+ (@) You can refer to the I2C HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup I2C I2C
+ * @brief I2C HAL module driver
+ * @{
+ */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup I2C_Private_Define I2C Private Define
+ * @{
+ */
+#define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */
+#define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */
+#define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */
+#define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */
+#define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */
+#define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */
+#define I2C_TIMEOUT_TC (25U) /*!< 25 ms */
+#define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */
+#define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */
+#define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */
+
+#define MAX_NBYTE_SIZE 255U
+#define SlaveAddr_SHIFT 7U
+#define SlaveAddr_MSK 0x06U
+
+/* Private define for @ref PreviousState usage */
+#define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */
+#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */
+#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MEM_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM)) /*!< Memory Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MEM_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM)) /*!< Memory Busy RX, combinaison of State LSB and Mode enum */
+
+
+/* Private define to centralize the enable/disable of Interrupts */
+#define I2C_XFER_TX_IT (0x00000001U)
+#define I2C_XFER_RX_IT (0x00000002U)
+#define I2C_XFER_LISTEN_IT (0x00000004U)
+
+#define I2C_XFER_ERROR_IT (0x00000011U)
+#define I2C_XFER_CPLT_IT (0x00000012U)
+#define I2C_XFER_RELOAD_IT (0x00000012U)
+
+/* Private define Sequential Transfer Options default/reset value */
+#define I2C_NO_OPTION_FRAME (0xFFFF0000U)
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) ((((__HANDLE__)->State) == HAL_I2C_STATE_BUSY_TX) ? \
+ ((uint32_t)(((DMA_Channel_TypeDef *)(__HANDLE__)->hdmatx->Instance)->CNDTR)) : \
+ ((uint32_t)(((DMA_Channel_TypeDef *)(__HANDLE__)->hdmarx->Instance)->CNDTR)))
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/** @defgroup I2C_Private_Functions I2C Private Functions
+ * @{
+ */
+/* Private functions to handle DMA transfer */
+static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMAError(DMA_HandleTypeDef *hdma);
+static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
+
+/* Private functions to handle IT transfer */
+static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c);
+static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c);
+static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
+
+/* Private functions to handle IT transfer */
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
+
+/* Private functions for I2C transfer IRQ handler */
+static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
+
+/* Private functions to handle flags during polling transfer */
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+
+/* Private functions to centralize the enable/disable of Interrupts */
+static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
+static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
+
+/* Private functions to flush TXDR register */
+static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
+
+/* Private functions to handle start, restart or stop a transfer */
+static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Functions I2C Exported Functions
+ * @{
+ */
+
+/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to initialize and
+ deinitialize the I2Cx peripheral:
+
+ (+) User must Implement HAL_I2C_MspInit() function in which he configures
+ all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+ (+) Call the function HAL_I2C_Init() to configure the selected device with
+ the selected configuration:
+ (++) Clock Timing
+ (++) Own Address 1
+ (++) Addressing mode (Master, Slave)
+ (++) Dual Addressing mode
+ (++) Own Address 2
+ (++) Own Address 2 Mask
+ (++) General call mode
+ (++) Nostretch mode
+
+ (+) Call the function HAL_I2C_DeInit() to restore the default configuration
+ of the selected I2Cx peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the I2C according to the specified parameters
+ * in the I2C_InitTypeDef and initialize the associated handle.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
+{
+ /* Check the I2C handle allocation */
+ if (hi2c == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+ assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
+ assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
+ assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
+ assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
+ assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
+ assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
+ assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
+
+ if (hi2c->State == HAL_I2C_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hi2c->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+ HAL_I2C_MspInit(hi2c);
+ }
+
+ hi2c->State = HAL_I2C_STATE_BUSY;
+
+ /* Disable the selected I2C peripheral */
+ __HAL_I2C_DISABLE(hi2c);
+
+ /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
+ /* Configure I2Cx: Frequency range */
+ hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
+
+ /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
+ /* Disable Own Address1 before set the Own Address1 configuration */
+ hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
+
+ /* Configure I2Cx: Own Address1 and ack own address1 mode */
+ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
+ {
+ hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
+ }
+ else /* I2C_ADDRESSINGMODE_10BIT */
+ {
+ hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
+ }
+
+ /*---------------------------- I2Cx CR2 Configuration ----------------------*/
+ /* Configure I2Cx: Addressing Master mode */
+ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+ {
+ hi2c->Instance->CR2 = (I2C_CR2_ADD10);
+ }
+ /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
+ hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
+
+ /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
+ /* Disable Own Address2 before set the Own Address2 configuration */
+ hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
+
+ /* Configure I2Cx: Dual mode and Own Address2 */
+ hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8));
+
+ /*---------------------------- I2Cx CR1 Configuration ----------------------*/
+ /* Configure I2Cx: Generalcall and NoStretch mode */
+ hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
+
+ /* Enable the selected I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitialize the I2C peripheral.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
+{
+ /* Check the I2C handle allocation */
+ if (hi2c == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+
+ hi2c->State = HAL_I2C_STATE_BUSY;
+
+ /* Disable the I2C Peripheral Clock */
+ __HAL_I2C_DISABLE(hi2c);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_I2C_MspDeInit(hi2c);
+
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ hi2c->State = HAL_I2C_STATE_RESET;
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the I2C MSP.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the I2C MSP.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the I2C data
+ transfers.
+
+ (#) There are two modes of transfer:
+ (++) Blocking mode : The communication is performed in the polling mode.
+ The status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode : The communication is performed using Interrupts
+ or DMA. These functions return the status of the transfer startup.
+ The end of the data processing will be indicated through the
+ dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+
+ (#) Blocking mode functions are :
+ (++) HAL_I2C_Master_Transmit()
+ (++) HAL_I2C_Master_Receive()
+ (++) HAL_I2C_Slave_Transmit()
+ (++) HAL_I2C_Slave_Receive()
+ (++) HAL_I2C_Mem_Write()
+ (++) HAL_I2C_Mem_Read()
+ (++) HAL_I2C_IsDeviceReady()
+
+ (#) No-Blocking mode functions with Interrupt are :
+ (++) HAL_I2C_Master_Transmit_IT()
+ (++) HAL_I2C_Master_Receive_IT()
+ (++) HAL_I2C_Slave_Transmit_IT()
+ (++) HAL_I2C_Slave_Receive_IT()
+ (++) HAL_I2C_Mem_Write_IT()
+ (++) HAL_I2C_Mem_Read_IT()
+
+ (#) No-Blocking mode functions with DMA are :
+ (++) HAL_I2C_Master_Transmit_DMA()
+ (++) HAL_I2C_Master_Receive_DMA()
+ (++) HAL_I2C_Slave_Transmit_DMA()
+ (++) HAL_I2C_Slave_Receive_DMA()
+ (++) HAL_I2C_Mem_Write_DMA()
+ (++) HAL_I2C_Mem_Read_DMA()
+
+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+ (++) HAL_I2C_MemTxCpltCallback()
+ (++) HAL_I2C_MemRxCpltCallback()
+ (++) HAL_I2C_MasterTxCpltCallback()
+ (++) HAL_I2C_MasterRxCpltCallback()
+ (++) HAL_I2C_SlaveTxCpltCallback()
+ (++) HAL_I2C_SlaveRxCpltCallback()
+ (++) HAL_I2C_ErrorCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Transmits in master mode an amount of data in blocking mode.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferISR = NULL;
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
+ }
+
+ while (hi2c->XferCount > 0U)
+ {
+ /* Wait until TXIS flag is set */
+ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ /* Write data to TXDR */
+ hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
+ hi2c->XferCount--;
+ hi2c->XferSize--;
+
+ if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
+ {
+ /* Wait until TCR flag is set */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ }
+ }
+ }
+
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is set */
+ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ I2C_RESET_CR2(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receives in master mode an amount of data in blocking mode.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferISR = NULL;
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+ }
+
+ while (hi2c->XferCount > 0U)
+ {
+ /* Wait until RXNE flag is set */
+ if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Read data from RXDR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+
+ if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
+ {
+ /* Wait until TCR flag is set */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ }
+ }
+ }
+
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is set */
+ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ I2C_RESET_CR2(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmits in slave mode an amount of data in blocking mode.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferISR = NULL;
+
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Wait until ADDR flag is set */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+
+ /* If 10bit addressing mode is selected */
+ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+ {
+ /* Wait until ADDR flag is set */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+ }
+
+ /* Wait until DIR flag is set Transmitter mode */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ while (hi2c->XferCount > 0U)
+ {
+ /* Wait until TXIS flag is set */
+ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Write data to TXDR */
+ hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
+ hi2c->XferCount--;
+ }
+
+ /* Wait until STOP flag is set */
+ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Normal use case for Transmitter mode */
+ /* A NACK is generated to confirm the end of transfer */
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Wait until BUSY flag is reset */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in slave mode an amount of data in blocking mode
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferISR = NULL;
+
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Wait until ADDR flag is set */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+
+ /* Wait until DIR flag is reset Receiver mode */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ while (hi2c->XferCount > 0U)
+ {
+ /* Wait until RXNE flag is set */
+ if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ /* Store Last receive data if any */
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
+ {
+ /* Read data from RXDR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
+ hi2c->XferCount--;
+ }
+
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /* Read data from RXDR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
+ hi2c->XferCount--;
+ }
+
+ /* Wait until STOP flag is set */
+ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Wait until BUSY flag is reset */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+ uint32_t xfermode = 0U;
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferISR = I2C_Master_ISR_IT;
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = I2C_AUTOEND_MODE;
+ }
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+ uint32_t xfermode = 0U;
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferISR = I2C_Master_ISR_IT;
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = I2C_AUTOEND_MODE;
+ }
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferISR = I2C_Slave_ISR_IT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferISR = I2C_Slave_ISR_IT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit in master mode an amount of data in non-blocking mode with DMA
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+ uint32_t xfermode = 0U;
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferISR = I2C_Master_ISR_DMA;
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = I2C_AUTOEND_MODE;
+ }
+
+ if (hi2c->XferSize > 0U)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hi2c->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
+
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR and NACK interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+ }
+ else
+ {
+ /* Update Transfer ISR function pointer */
+ hi2c->XferISR = I2C_Master_ISR_IT;
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and generate START condition */
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in master mode an amount of data in non-blocking mode with DMA
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+ uint32_t xfermode = 0U;
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferISR = I2C_Master_ISR_DMA;
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = I2C_AUTOEND_MODE;
+ }
+
+ if (hi2c->XferSize > 0U)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmarx->XferHalfCpltCallback = NULL;
+ hi2c->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+
+ /* Send Slave Address */
+ /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR and NACK interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+ }
+ else
+ {
+ /* Update Transfer ISR function pointer */
+ hi2c->XferISR = I2C_Master_ISR_IT;
+
+ /* Send Slave Address */
+ /* Set NBYTES to read and generate START condition */
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+ }
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferISR = I2C_Slave_ISR_DMA;
+
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hi2c->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR, STOP, NACK, ADDR interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in slave mode an amount of data in non-blocking mode with DMA
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferISR = I2C_Slave_ISR_DMA;
+
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmarx->XferHalfCpltCallback = NULL;
+ hi2c->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR, STOP, NACK, ADDR interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+/**
+ * @brief Write an amount of data in blocking mode to a specific memory address
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MEM;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferISR = NULL;
+
+ /* Send Slave Address and Memory Address */
+ if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
+ {
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ }
+
+ do
+ {
+ /* Wait until TXIS flag is set */
+ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Write data to TXDR */
+ hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
+ hi2c->XferCount--;
+ hi2c->XferSize--;
+
+ if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
+ {
+ /* Wait until TCR flag is set */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ }
+ }
+
+ }
+ while (hi2c->XferCount > 0U);
+
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ I2C_RESET_CR2(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Read an amount of data in blocking mode from a specific memory address
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MEM;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferISR = NULL;
+
+ /* Send Slave Address and Memory Address */
+ if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
+ {
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+ }
+
+ do
+ {
+ /* Wait until RXNE flag is set */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Read data from RXDR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+
+ if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
+ {
+ /* Wait until TCR flag is set */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ }
+ }
+ }
+ while (hi2c->XferCount > 0U);
+
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ I2C_RESET_CR2(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+/**
+ * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+ uint32_t tickstart = 0U;
+ uint32_t xfermode = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MEM;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferISR = I2C_Master_ISR_IT;
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = I2C_AUTOEND_MODE;
+ }
+
+ /* Send Slave Address and Memory Address */
+ if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+ {
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+ uint32_t tickstart = 0U;
+ uint32_t xfermode = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MEM;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferISR = I2C_Master_ISR_IT;
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = I2C_AUTOEND_MODE;
+ }
+
+ /* Send Slave Address and Memory Address */
+ if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+ {
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+/**
+ * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+ uint32_t tickstart = 0U;
+ uint32_t xfermode = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MEM;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferISR = I2C_Master_ISR_DMA;
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = I2C_AUTOEND_MODE;
+ }
+
+ /* Send Slave Address and Memory Address */
+ if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+ {
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hi2c->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
+
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR and NACK interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be read
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+ uint32_t tickstart = 0U;
+ uint32_t xfermode = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MEM;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferISR = I2C_Master_ISR_DMA;
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = I2C_AUTOEND_MODE;
+ }
+
+ /* Send Slave Address and Memory Address */
+ if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+ {
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmarx->XferHalfCpltCallback = NULL;
+ hi2c->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR and NACK interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Checks if target device is ready for communication.
+ * @note This function is used with Memory devices
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param Trials Number of trials
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ __IO uint32_t I2C_Trials = 0U;
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ do
+ {
+ /* Generate Start */
+ hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress);
+
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is set or a NACK flag is set*/
+ tickstart = HAL_GetTick();
+ while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT))
+ {
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ /* Device is ready */
+ hi2c->State = HAL_I2C_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Check if the NACKF flag has not been set */
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
+ {
+ /* Wait until STOPF flag is reset */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Device is ready */
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Wait until STOPF flag is reset */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Clear STOP Flag, auto generated with autoend*/
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+ }
+
+ /* Check if the maximum allowed number of trials has been reached */
+ if (I2C_Trials++ == Trials)
+ {
+ /* Generate Stop */
+ hi2c->Instance->CR2 |= I2C_CR2_STOP;
+
+ /* Wait until STOPF flag is reset */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+ }
+ }
+ while (I2C_Trials < Trials);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_TIMEOUT;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ uint32_t xfermode = 0U;
+ uint32_t xferrequest = I2C_GENERATE_START_WRITE;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = XferOptions;
+ hi2c->XferISR = I2C_Master_ISR_IT;
+
+ /* If size > MAX_NBYTE_SIZE, use reload mode */
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = hi2c->XferOptions;
+ }
+
+ /* If transfer direction not change, do not generate Restart Condition */
+ /* Mean Previous state is same as current state */
+ if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
+ {
+ xferrequest = I2C_NO_STARTSTOP;
+ }
+
+ /* Send Slave Address and set NBYTES to write */
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ uint32_t xfermode = 0U;
+ uint32_t xferrequest = I2C_GENERATE_START_READ;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = XferOptions;
+ hi2c->XferISR = I2C_Master_ISR_IT;
+
+ /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = hi2c->XferOptions;
+ }
+
+ /* If transfer direction not change, do not generate Restart Condition */
+ /* Mean Previous state is same as current state */
+ if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
+ {
+ xferrequest = I2C_NO_STARTSTOP;
+ }
+
+ /* Send Slave Address and set NBYTES to read */
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+ /* and then toggle the HAL slave RX state to TX state */
+ if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+ {
+ /* Disable associated Interrupts */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+ }
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = XferOptions;
+ hi2c->XferISR = I2C_Slave_ISR_IT;
+
+ if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+ {
+ /* Clear ADDR flag after prepare the transfer parameters */
+ /* This action will generate an acknowledge to the Master */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* REnable ADDR interrupt */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+ /* and then toggle the HAL slave TX state to RX state */
+ if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+ {
+ /* Disable associated Interrupts */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+ }
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = XferOptions;
+ hi2c->XferISR = I2C_Slave_ISR_IT;
+
+ if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
+ {
+ /* Clear ADDR flag after prepare the transfer parameters */
+ /* This action will generate an acknowledge to the Master */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* REnable ADDR interrupt */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Enable the Address listen mode with Interrupt.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
+{
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->XferISR = I2C_Slave_ISR_IT;
+
+ /* Enable the Address Match interrupt */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Disable the Address listen mode with Interrupt.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
+{
+ /* Declaration of tmp to prevent undefined behavior of volatile usage */
+ uint32_t tmp;
+
+ /* Disable Address listen mode only if a transfer is not ongoing */
+ if (hi2c->State == HAL_I2C_STATE_LISTEN)
+ {
+ tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
+ hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->XferISR = NULL;
+
+ /* Disable the Address Match interrupt */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Abort a master I2C IT or DMA process communication with Interrupt.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
+{
+ if (hi2c->Mode == HAL_I2C_MODE_MASTER)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Disable Interrupts */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+ /* Set State at HAL_I2C_STATE_ABORT */
+ hi2c->State = HAL_I2C_STATE_ABORT;
+
+ /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */
+ /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
+ I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Wrong usage of abort function */
+ /* This function should be used only in case of abort monitored by master device */
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+
+/**
+ * @brief This function handles I2C event interrupt request.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
+{
+ /* Get current IT Flags and IT sources value */
+ uint32_t itflags = READ_REG(hi2c->Instance->ISR);
+ uint32_t itsources = READ_REG(hi2c->Instance->CR1);
+
+ /* I2C events treatment -------------------------------------*/
+ if (hi2c->XferISR != NULL)
+ {
+ hi2c->XferISR(hi2c, itflags, itsources);
+ }
+}
+
+/**
+ * @brief This function handles I2C error interrupt request.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
+{
+ uint32_t itflags = READ_REG(hi2c->Instance->ISR);
+ uint32_t itsources = READ_REG(hi2c->Instance->CR1);
+
+ /* I2C Bus error interrupt occurred ------------------------------------*/
+ if (((itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
+
+ /* Clear BERR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
+ }
+
+ /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
+ if (((itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
+
+ /* Clear OVR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
+ }
+
+ /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
+ if (((itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
+
+ /* Clear ARLO flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
+ }
+
+ /* Call the Error Callback in case of Error detected */
+ if ((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE)
+ {
+ I2C_ITError(hi2c, hi2c->ErrorCode);
+ }
+}
+
+/**
+ * @brief Master Tx Transfer completed callback.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Master Rx Transfer completed callback.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
+ */
+}
+
+/** @brief Slave Tx Transfer completed callback.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Slave Rx Transfer completed callback.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Slave Address Match callback.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION
+ * @param AddrMatchCode Address Match Code
+ * @retval None
+ */
+__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+ UNUSED(TransferDirection);
+ UNUSED(AddrMatchCode);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_AddrCallback() could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Listen Complete callback.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_ListenCpltCallback() could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Memory Tx Transfer completed callback.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_MemTxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Memory Rx Transfer completed callback.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_MemRxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C error callback.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C abort callback.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_AbortCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
+ * @brief Peripheral State, Mode and Error functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State, Mode and Error functions #####
+ ===============================================================================
+ [..]
+ This subsection permit to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the I2C handle state.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL state
+ */
+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
+{
+ /* Return I2C handle state */
+ return hi2c->State;
+}
+
+/**
+ * @brief Returns the I2C Master, Slave, Memory or no mode.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
+ * @retval HAL mode
+ */
+HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
+{
+ return hi2c->Mode;
+}
+
+/**
+* @brief Return the I2C error code.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+* @retval I2C Error Code
+*/
+uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
+{
+ return hi2c->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param ITFlags Interrupt flags to handle.
+ * @param ITSources Interrupt sources enabled.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
+{
+ uint16_t devaddress = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Set corresponding Error Code */
+ /* No need to generate STOP, it is automatically done */
+ /* Error callback will be send during stop flag treatment */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+ }
+ else if (((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET))
+ {
+ /* Read data from RXDR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+ }
+ else if (((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET))
+ {
+ /* Write data to TXDR */
+ hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+ }
+ else if (((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
+ {
+ if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
+ {
+ devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+ {
+ I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP);
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ }
+ }
+ }
+ else
+ {
+ /* Call TxCpltCallback() if no stop mode is set */
+ if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+ {
+ /* Call I2C Master Sequential complete process */
+ I2C_ITMasterSequentialCplt(hi2c);
+ }
+ else
+ {
+ /* Wrong size Status regarding TCR flag event */
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+ }
+ }
+ }
+ else if (((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
+ {
+ if (hi2c->XferCount == 0U)
+ {
+ if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+ {
+ /* Generate a stop condition in case of no transfer option */
+ if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
+ {
+ /* Generate Stop */
+ hi2c->Instance->CR2 |= I2C_CR2_STOP;
+ }
+ else
+ {
+ /* Call I2C Master Sequential complete process */
+ I2C_ITMasterSequentialCplt(hi2c);
+ }
+ }
+ }
+ else
+ {
+ /* Wrong size Status regarding TC flag event */
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+ }
+ }
+
+ if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
+ {
+ /* Call I2C Master complete process */
+ I2C_ITMasterCplt(hi2c, ITFlags);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param ITFlags Interrupt flags to handle.
+ * @param ITSources Interrupt sources enabled.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
+{
+ /* Process locked */
+ __HAL_LOCK(hi2c);
+
+ if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
+ {
+ /* Check that I2C transfer finished */
+ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
+ /* Mean XferCount == 0*/
+ /* So clear Flag NACKF only */
+ if (hi2c->XferCount == 0U)
+ {
+ if (((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \
+ (hi2c->State == HAL_I2C_STATE_LISTEN))
+ {
+ /* Call I2C Listen complete process */
+ I2C_ITListenCplt(hi2c, ITFlags);
+ }
+ else if ((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN))
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+
+ /* Last Byte is Transmitted */
+ /* Call I2C Slave Sequential complete process */
+ I2C_ITSlaveSequentialCplt(hi2c);
+ }
+ else
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+ }
+ }
+ else
+ {
+ /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Set ErrorCode corresponding to a Non-Acknowledge */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+ }
+ else if (((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET))
+ {
+ if (hi2c->XferCount > 0U)
+ {
+ /* Read data from RXDR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+ }
+
+ if ((hi2c->XferCount == 0U) && \
+ (hi2c->XferOptions != I2C_NO_OPTION_FRAME))
+ {
+ /* Call I2C Slave Sequential complete process */
+ I2C_ITSlaveSequentialCplt(hi2c);
+ }
+ }
+ else if (((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET))
+ {
+ I2C_ITAddrCplt(hi2c, ITFlags);
+ }
+ else if (((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET))
+ {
+ /* Write data to TXDR only if XferCount not reach "0" */
+ /* A TXIS flag can be set, during STOP treatment */
+ /* Check if all Datas have already been sent */
+ /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
+ if (hi2c->XferCount > 0U)
+ {
+ /* Write data to TXDR */
+ hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
+ hi2c->XferCount--;
+ hi2c->XferSize--;
+ }
+ else
+ {
+ if ((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME))
+ {
+ /* Last Byte is Transmitted */
+ /* Call I2C Slave Sequential complete process */
+ I2C_ITSlaveSequentialCplt(hi2c);
+ }
+ }
+ }
+
+ /* Check if STOPF is set */
+ if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
+ {
+ /* Call I2C Slave complete process */
+ I2C_ITSlaveCplt(hi2c, ITFlags);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param ITFlags Interrupt flags to handle.
+ * @param ITSources Interrupt sources enabled.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
+{
+ uint16_t devaddress = 0U;
+ uint32_t xfermode = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Set corresponding Error Code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+ /* No need to generate STOP, it is automatically done */
+ /* But enable STOP interrupt, to treat it */
+ /* Error callback will be send during stop flag treatment */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+ }
+ else if (((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
+ {
+ /* Disable TC interrupt */
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
+
+ if (hi2c->XferCount != 0U)
+ {
+ /* Recover Slave address */
+ devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
+
+ /* Prepare the new XferSize to transfer */
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = I2C_AUTOEND_MODE;
+ }
+
+ /* Set the new XferSize in Nbytes register */
+ I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
+
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
+
+ /* Enable DMA Request */
+ if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ {
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+ }
+ else
+ {
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+ }
+ }
+ else
+ {
+ /* Wrong size Status regarding TCR flag event */
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+ }
+ }
+ else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
+ {
+ /* Call I2C Master complete process */
+ I2C_ITMasterCplt(hi2c, ITFlags);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param ITFlags Interrupt flags to handle.
+ * @param ITSources Interrupt sources enabled.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
+{
+ /* Process locked */
+ __HAL_LOCK(hi2c);
+
+ if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
+ {
+ /* Check that I2C transfer finished */
+ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
+ /* Mean XferCount == 0 */
+ /* So clear Flag NACKF only */
+ if (I2C_GET_DMA_REMAIN_DATA(hi2c) == 0U)
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+ }
+ else
+ {
+ /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Set ErrorCode corresponding to a Non-Acknowledge */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+ }
+ else if (((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET))
+ {
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+ }
+ else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
+ {
+ /* Call I2C Slave complete process */
+ I2C_ITSlaveCplt(hi2c, ITFlags);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Master sends target device address followed by internal memory address for write request.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param Timeout Timeout duration
+ * @param Tickstart Tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
+{
+ I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
+
+ /* Wait until TXIS flag is set */
+ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+ {
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* If Memory address size is 8Bit */
+ if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
+ {
+ /* Send Memory Address */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+ }
+ /* If Memory address size is 16Bit */
+ else
+ {
+ /* Send MSB of Memory Address */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+
+ /* Wait until TXIS flag is set */
+ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+ {
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Send LSB of Memory Address */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+ }
+
+ /* Wait until TCR flag is set */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Master sends target device address followed by internal memory address for read request.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param Timeout Timeout duration
+ * @param Tickstart Tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
+{
+ I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
+
+ /* Wait until TXIS flag is set */
+ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+ {
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* If Memory address size is 8Bit */
+ if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
+ {
+ /* Send Memory Address */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+ }
+ /* If Memory address size is 16Bit */
+ else
+ {
+ /* Send MSB of Memory Address */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+
+ /* Wait until TXIS flag is set */
+ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+ {
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Send LSB of Memory Address */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+ }
+
+ /* Wait until TC flag is set */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief I2C Address complete process callback.
+ * @param hi2c I2C handle.
+ * @param ITFlags Interrupt flags to handle.
+ * @retval None
+ */
+static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+{
+ uint8_t transferdirection = 0U;
+ uint16_t slaveaddrcode = 0U;
+ uint16_t ownadd1code = 0U;
+ uint16_t ownadd2code = 0U;
+
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(ITFlags);
+
+ /* In case of Listen state, need to inform upper layer of address match code event */
+ if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
+ {
+ transferdirection = I2C_GET_DIR(hi2c);
+ slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c);
+ ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c);
+ ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c);
+
+ /* If 10bits addressing mode is selected */
+ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+ {
+ if ((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK))
+ {
+ slaveaddrcode = ownadd1code;
+ hi2c->AddrEventCount++;
+ if (hi2c->AddrEventCount == 2U)
+ {
+ /* Reset Address Event counter */
+ hi2c->AddrEventCount = 0U;
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call Slave Addr callback */
+ HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
+ }
+ }
+ else
+ {
+ slaveaddrcode = ownadd2code;
+
+ /* Disable ADDR Interrupts */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call Slave Addr callback */
+ HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
+ }
+ }
+ /* else 7 bits addressing mode is selected */
+ else
+ {
+ /* Disable ADDR Interrupts */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call Slave Addr callback */
+ HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
+ }
+ }
+ /* Else clear address flag only */
+ else
+ {
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ }
+}
+
+/**
+ * @brief I2C Master sequential complete process.
+ * @param hi2c I2C handle.
+ * @retval None
+ */
+static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c)
+{
+ /* Reset I2C handle mode */
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* No Generate Stop, to permit restart mode */
+ /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */
+ if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+ hi2c->XferISR = NULL;
+
+ /* Disable Interrupts */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ HAL_I2C_MasterTxCpltCallback(hi2c);
+ }
+ /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
+ else
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+ hi2c->XferISR = NULL;
+
+ /* Disable Interrupts */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ HAL_I2C_MasterRxCpltCallback(hi2c);
+ }
+}
+
+/**
+ * @brief I2C Slave sequential complete process.
+ * @param hi2c I2C handle.
+ * @retval None
+ */
+static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c)
+{
+ /* Reset I2C handle mode */
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+ {
+ /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+
+ /* Disable Interrupts */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call the Tx complete callback to inform upper layer of the end of transmit process */
+ HAL_I2C_SlaveTxCpltCallback(hi2c);
+ }
+
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+ {
+ /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+
+ /* Disable Interrupts */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call the Rx complete callback to inform upper layer of the end of receive process */
+ HAL_I2C_SlaveRxCpltCallback(hi2c);
+ }
+}
+
+/**
+ * @brief I2C Master complete process.
+ * @param hi2c I2C handle.
+ * @param ITFlags Interrupt flags to handle.
+ * @retval None
+ */
+static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+{
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ I2C_RESET_CR2(hi2c);
+
+ /* Reset handle parameters */
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->XferISR = NULL;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+
+ if ((ITFlags & I2C_FLAG_AF) != RESET)
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Set acknowledge error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+
+ /* Disable Interrupts */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ if ((hi2c->ErrorCode != HAL_I2C_ERROR_NONE) || (hi2c->State == HAL_I2C_STATE_ABORT))
+ {
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, hi2c->ErrorCode);
+ }
+ /* hi2c->State == HAL_I2C_STATE_BUSY_TX */
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ if (hi2c->Mode == HAL_I2C_MODE_MEM)
+ {
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ HAL_I2C_MemTxCpltCallback(hi2c);
+ }
+ else
+ {
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ HAL_I2C_MasterTxCpltCallback(hi2c);
+ }
+ }
+ /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ if (hi2c->Mode == HAL_I2C_MODE_MEM)
+ {
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ HAL_I2C_MemRxCpltCallback(hi2c);
+ }
+ else
+ {
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ HAL_I2C_MasterRxCpltCallback(hi2c);
+ }
+ }
+}
+
+/**
+ * @brief I2C Slave complete process.
+ * @param hi2c I2C handle.
+ * @param ITFlags Interrupt flags to handle.
+ * @retval None
+ */
+static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+{
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+
+ /* Disable all interrupts */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
+
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ /* Clear Configuration Register 2 */
+ I2C_RESET_CR2(hi2c);
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+
+ /* If a DMA is ongoing, Update handle size context */
+ if (((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) ||
+ ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN))
+ {
+ hi2c->XferCount = I2C_GET_DMA_REMAIN_DATA(hi2c);
+ }
+
+ /* All data are not transferred, so set error code accordingly */
+ if (hi2c->XferCount != 0U)
+ {
+ /* Set ErrorCode corresponding to a Non-Acknowledge */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+
+ /* Store Last receive data if any */
+ if (((ITFlags & I2C_FLAG_RXNE) != RESET))
+ {
+ /* Read data from RXDR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
+
+ if ((hi2c->XferSize > 0U))
+ {
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+
+ /* Set ErrorCode corresponding to a Non-Acknowledge */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+ }
+
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->XferISR = NULL;
+
+ if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ {
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, hi2c->ErrorCode);
+
+ /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+ if (hi2c->State == HAL_I2C_STATE_LISTEN)
+ {
+ /* Call I2C Listen complete process */
+ I2C_ITListenCplt(hi2c, ITFlags);
+ }
+ }
+ else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+ {
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+ HAL_I2C_ListenCpltCallback(hi2c);
+ }
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call the Slave Rx Complete callback */
+ HAL_I2C_SlaveRxCpltCallback(hi2c);
+ }
+ else
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call the Slave Tx Complete callback */
+ HAL_I2C_SlaveTxCpltCallback(hi2c);
+ }
+}
+
+/**
+ * @brief I2C Listen complete process.
+ * @param hi2c I2C handle.
+ * @param ITFlags Interrupt flags to handle.
+ * @retval None
+ */
+static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+{
+ /* Reset handle parameters */
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->XferISR = NULL;
+
+ /* Store Last receive data if any */
+ if (((ITFlags & I2C_FLAG_RXNE) != RESET))
+ {
+ /* Read data from RXDR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
+
+ if ((hi2c->XferSize > 0U))
+ {
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+
+ /* Set ErrorCode corresponding to a Non-Acknowledge */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+ }
+
+ /* Disable all Interrupts*/
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
+
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+ HAL_I2C_ListenCpltCallback(hi2c);
+}
+
+/**
+ * @brief I2C interrupts error process.
+ * @param hi2c I2C handle.
+ * @param ErrorCode Error code to handle.
+ * @retval None
+ */
+static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
+{
+ /* Reset handle parameters */
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferCount = 0U;
+
+ /* Set new error code */
+ hi2c->ErrorCode |= ErrorCode;
+
+ /* Disable Interrupts */
+ if ((hi2c->State == HAL_I2C_STATE_LISTEN) ||
+ (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
+ (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN))
+ {
+ /* Disable all interrupts, except interrupts related to LISTEN state */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
+
+ /* keep HAL_I2C_STATE_LISTEN if set */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->XferISR = I2C_Slave_ISR_IT;
+ }
+ else
+ {
+ /* Disable all interrupts */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
+
+ /* If state is an abort treatment on goind, don't change state */
+ /* This change will be do later */
+ if (hi2c->State != HAL_I2C_STATE_ABORT)
+ {
+ /* Set HAL_I2C_STATE_READY */
+ hi2c->State = HAL_I2C_STATE_READY;
+ }
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->XferISR = NULL;
+ }
+
+ /* Abort DMA TX transfer if any */
+ if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+ {
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+ /* Set the I2C DMA Abort callback :
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+ }
+ }
+ /* Abort DMA RX transfer if any */
+ else if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+ {
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+ /* Set the I2C DMA Abort callback :
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+ {
+ /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
+ hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+ }
+ }
+ else if (hi2c->State == HAL_I2C_STATE_ABORT)
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ HAL_I2C_AbortCpltCallback(hi2c);
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+}
+
+/**
+ * @brief I2C Tx data register flush process.
+ * @param hi2c I2C handle.
+ * @retval None
+ */
+static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
+{
+ /* If a pending TXIS flag is set */
+ /* Write a dummy data in TXDR to clear it */
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
+ {
+ hi2c->Instance->TXDR = 0x00U;
+ }
+
+ /* Flush TX register if not empty */
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
+ {
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
+ }
+}
+
+/**
+ * @brief DMA I2C master transmit process complete callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+ /* If last transfer, enable STOP interrupt */
+ if (hi2c->XferCount == 0U)
+ {
+ /* Enable STOP interrupt */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+ }
+ /* else prepare a new DMA transfer and enable TCReload interrupt */
+ else
+ {
+ /* Update Buffer pointer */
+ hi2c->pBuffPtr += hi2c->XferSize;
+
+ /* Set the XferSize to transfer */
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ }
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+
+ /* Enable TC interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
+ }
+}
+
+/**
+ * @brief DMA I2C slave transmit process complete callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdma);
+
+ /* No specific action, Master fully manage the generation of STOP condition */
+ /* Mean that this generation can arrive at any time, at the end or during DMA process */
+ /* So STOP condition should be manage through Interrupt treatment */
+}
+
+/**
+ * @brief DMA I2C master receive process complete callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+ /* If last transfer, enable STOP interrupt */
+ if (hi2c->XferCount == 0U)
+ {
+ /* Enable STOP interrupt */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+ }
+ /* else prepare a new DMA transfer and enable TCReload interrupt */
+ else
+ {
+ /* Update Buffer pointer */
+ hi2c->pBuffPtr += hi2c->XferSize;
+
+ /* Set the XferSize to transfer */
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ }
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
+
+ /* Enable TC interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
+ }
+}
+
+/**
+ * @brief DMA I2C slave receive process complete callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdma);
+
+ /* No specific action, Master fully manage the generation of STOP condition */
+ /* Mean that this generation can arrive at any time, at the end or during DMA process */
+ /* So STOP condition should be manage through Interrupt treatment */
+}
+
+/**
+ * @brief DMA I2C communication error callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void I2C_DMAError(DMA_HandleTypeDef *hdma)
+{
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Disable Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
+}
+
+/**
+ * @brief DMA I2C communication abort callback
+ * (To be called at end of DMA Abort procedure).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
+{
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Disable Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ /* Reset AbortCpltCallback */
+ hi2c->hdmatx->XferAbortCallback = NULL;
+ hi2c->hdmarx->XferAbortCallback = NULL;
+
+ /* Check if come from abort from user */
+ if (hi2c->State == HAL_I2C_STATE_ABORT)
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ HAL_I2C_AbortCpltCallback(hi2c);
+ }
+ else
+ {
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+}
+
+/**
+ * @brief This function handles I2C Communication Timeout.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param Flag Specifies the I2C flag to check.
+ * @param Status The new Flag status (SET or RESET).
+ * @param Timeout Timeout duration
+ * @param Tickstart Tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
+{
+ while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param Timeout Timeout duration
+ * @param Tickstart Tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+{
+ while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
+ {
+ /* Check if a NACK is detected */
+ if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles I2C Communication Timeout for specific usage of STOP flag.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param Timeout Timeout duration
+ * @param Tickstart Tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+{
+ while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+ {
+ /* Check if a NACK is detected */
+ if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check for the Timeout */
+ if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param Timeout Timeout duration
+ * @param Tickstart Tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+{
+ while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
+ {
+ /* Check if a NACK is detected */
+ if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check if a STOPF is detected */
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
+ {
+ /* Check if an RXNE is pending */
+ /* Store Last receive data if any */
+ if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U))
+ {
+ /* Return HAL_OK */
+ /* The Reading of data from RXDR will be done in caller function */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ I2C_RESET_CR2(hi2c);
+
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Check for the Timeout */
+ if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles Acknowledge failed detection during an I2C Communication.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param Timeout Timeout duration
+ * @param Tickstart Tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+{
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+ {
+ /* Wait until STOP Flag is reset */
+ /* AutoEnd should be initiate after AF */
+ while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Clear NACKF Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+
+ /* Clear Configuration Register 2 */
+ I2C_RESET_CR2(hi2c);
+
+ hi2c->ErrorCode = HAL_I2C_ERROR_AF;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
+ * @param hi2c I2C handle.
+ * @param DevAddress Specifies the slave address to be programmed.
+ * @param Size Specifies the number of bytes to be programmed.
+ * This parameter must be a value between 0 and 255.
+ * @param Mode New state of the I2C START condition generation.
+ * This parameter can be one of the following values:
+ * @arg @ref I2C_RELOAD_MODE Enable Reload mode .
+ * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode.
+ * @arg @ref I2C_SOFTEND_MODE Enable Software end mode.
+ * @param Request New state of the I2C START condition generation.
+ * This parameter can be one of the following values:
+ * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition.
+ * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
+ * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request.
+ * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
+ * @retval None
+ */
+static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+ assert_param(IS_TRANSFER_MODE(Mode));
+ assert_param(IS_TRANSFER_REQUEST(Request));
+
+ /* update CR2 register */
+ MODIFY_REG(hi2c->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \
+ (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
+}
+
+/**
+ * @brief Manage the enabling of Interrupts.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
+{
+ uint32_t tmpisr = 0U;
+
+ if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \
+ (hi2c->XferISR == I2C_Slave_ISR_DMA))
+ {
+ if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+ {
+ /* Enable ERR, STOP, NACK and ADDR interrupts */
+ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+ }
+
+ if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
+ {
+ /* Enable ERR and NACK interrupts */
+ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
+ }
+
+ if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
+ {
+ /* Enable STOP interrupts */
+ tmpisr |= I2C_IT_STOPI;
+ }
+
+ if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
+ {
+ /* Enable TC interrupts */
+ tmpisr |= I2C_IT_TCI;
+ }
+ }
+ else
+ {
+ if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+ {
+ /* Enable ERR, STOP, NACK, and ADDR interrupts */
+ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+ }
+
+ if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
+ {
+ /* Enable ERR, TC, STOP, NACK and RXI interrupts */
+ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
+ }
+
+ if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
+ {
+ /* Enable ERR, TC, STOP, NACK and TXI interrupts */
+ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
+ }
+
+ if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
+ {
+ /* Enable STOP interrupts */
+ tmpisr |= I2C_IT_STOPI;
+ }
+ }
+
+ /* Enable interrupts only at the end */
+ /* to avoid the risk of I2C interrupt handle execution before */
+ /* all interrupts requested done */
+ __HAL_I2C_ENABLE_IT(hi2c, tmpisr);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Manage the disabling of Interrupts.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
+{
+ uint32_t tmpisr = 0U;
+
+ if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
+ {
+ /* Disable TC and TXI interrupts */
+ tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
+
+ if ((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)
+ {
+ /* Disable NACK and STOP interrupts */
+ tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+ }
+ }
+
+ if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
+ {
+ /* Disable TC and RXI interrupts */
+ tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
+
+ if ((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)
+ {
+ /* Disable NACK and STOP interrupts */
+ tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+ }
+ }
+
+ if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+ {
+ /* Disable ADDR, NACK and STOP interrupts */
+ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+ }
+
+ if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
+ {
+ /* Enable ERR and NACK interrupts */
+ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
+ }
+
+ if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
+ {
+ /* Enable STOP interrupts */
+ tmpisr |= I2C_IT_STOPI;
+ }
+
+ if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
+ {
+ /* Enable TC interrupts */
+ tmpisr |= I2C_IT_TCI;
+ }
+
+ /* Disable interrupts only at the end */
+ /* to avoid a breaking situation like at "t" time */
+ /* all disable interrupts request are not done */
+ __HAL_I2C_DISABLE_IT(hi2c, tmpisr);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_I2C_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_i2c_ex.c b/Src/stm32f3xx_hal_i2c_ex.c
new file mode 100644
index 0000000..cd142d4
--- /dev/null
+++ b/Src/stm32f3xx_hal_i2c_ex.c
@@ -0,0 +1,351 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_i2c_ex.c
+ * @author MCD Application Team
+ * @brief I2C Extended HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of I2C Extended peripheral:
+ * + Extended features functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### I2C peripheral Extended features #####
+ ==============================================================================
+
+ [..] Comparing to other previous devices, the I2C interface for STM32F3xx
+ devices contains the following additional features
+
+ (+) Possibility to disable or enable Analog Noise Filter
+ (+) Use of a configured Digital Noise Filter
+ (+) Disable or enable wakeup from Stop mode(s)
+ (+) Disable or enable Fast Mode Plus
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..] This driver provides functions to configure Noise Filter and Wake Up Feature
+ (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
+ (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
+ (#) Configure the enable or disable of I2C Wake Up Mode using the functions :
+ (++) HAL_I2CEx_EnableWakeUp()
+ (++) HAL_I2CEx_DisableWakeUp()
+ (#) Configure the enable or disable of fast mode plus driving capability using the functions :
+ (++) HAL_I2CEx_EnableFastModePlus()
+ (++) HAL_I2CEx_DisableFastModePlus()
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup I2CEx I2CEx
+ * @brief I2C Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions
+ * @{
+ */
+
+/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions
+ * @brief Extended features functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended features functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure Noise Filters
+ (+) Configure Wake Up Feature
+ (+) Configure Fast Mode Plus
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure I2C Analog noise filter.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2Cx peripheral.
+ * @param AnalogFilter New state of the Analog filter.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+ assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY;
+
+ /* Disable the selected I2C peripheral */
+ __HAL_I2C_DISABLE(hi2c);
+
+ /* Reset I2Cx ANOFF bit */
+ hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
+
+ /* Set analog filter bit*/
+ hi2c->Instance->CR1 |= AnalogFilter;
+
+ __HAL_I2C_ENABLE(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Configure I2C Digital noise filter.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2Cx peripheral.
+ * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
+{
+ uint32_t tmpreg = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+ assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY;
+
+ /* Disable the selected I2C peripheral */
+ __HAL_I2C_DISABLE(hi2c);
+
+ /* Get the old register value */
+ tmpreg = hi2c->Instance->CR1;
+
+ /* Reset I2Cx DNF bits [11:8] */
+ tmpreg &= ~(I2C_CR1_DNF);
+
+ /* Set I2Cx DNF coefficient */
+ tmpreg |= DigitalFilter << 8U;
+
+ /* Store the new register value */
+ hi2c->Instance->CR1 = tmpreg;
+
+ __HAL_I2C_ENABLE(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Enable I2C wakeup from Stop mode(s).
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2Cx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY;
+
+ /* Disable the selected I2C peripheral */
+ __HAL_I2C_DISABLE(hi2c);
+
+ /* Enable wakeup from stop mode */
+ hi2c->Instance->CR1 |= I2C_CR1_WUPEN;
+
+ __HAL_I2C_ENABLE(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Disable I2C wakeup from Stop mode(s).
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2Cx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY;
+
+ /* Disable the selected I2C peripheral */
+ __HAL_I2C_DISABLE(hi2c);
+
+ /* Enable wakeup from stop mode */
+ hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);
+
+ __HAL_I2C_ENABLE(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Enable the I2C fast mode plus driving capability.
+ * @param ConfigFastModePlus Selects the pin.
+ * This parameter can be one of the @ref I2CEx_FastModePlus values
+ * @note For I2C1, fast mode plus driving capability can be enabled on all selected
+ * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
+ * on each one of the following pins PB6, PB7, PB8 and PB9.
+ * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
+ * can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
+ * @note For all I2C2 pins fast mode plus driving capability can be enabled
+ * only by using I2C_FASTMODEPLUS_I2C2 parameter.
+ * @note For all I2C3 pins fast mode plus driving capability can be enabled
+ * only by using I2C_FASTMODEPLUS_I2C3 parameter.
+ * @retval None
+ */
+void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
+{
+ /* Check the parameter */
+ assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
+
+ /* Enable SYSCFG clock */
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+ /* Enable fast mode plus driving capability for selected pin */
+ SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
+}
+
+/**
+ * @brief Disable the I2C fast mode plus driving capability.
+ * @param ConfigFastModePlus Selects the pin.
+ * This parameter can be one of the @ref I2CEx_FastModePlus values
+ * @note For I2C1, fast mode plus driving capability can be disabled on all selected
+ * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
+ * on each one of the following pins PB6, PB7, PB8 and PB9.
+ * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
+ * can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
+ * @note For all I2C2 pins fast mode plus driving capability can be disabled
+ * only by using I2C_FASTMODEPLUS_I2C2 parameter.
+ * @note For all I2C3 pins fast mode plus driving capability can be disabled
+ * only by using I2C_FASTMODEPLUS_I2C3 parameter.
+ * @retval None
+ */
+void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
+{
+ /* Check the parameter */
+ assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
+
+ /* Enable SYSCFG clock */
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+ /* Disable fast mode plus driving capability for selected pin */
+ CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_I2C_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_i2s.c b/Src/stm32f3xx_hal_i2s.c
new file mode 100644
index 0000000..bdfb602
--- /dev/null
+++ b/Src/stm32f3xx_hal_i2s.c
@@ -0,0 +1,1337 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_i2s.c
+ * @author MCD Application Team
+ * @brief I2S HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Integrated Interchip Sound (I2S) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral State and Errors functions
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ The I2S HAL driver can be used as follows:
+
+ (#) Declare a I2S_HandleTypeDef handle structure.
+ (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
+ (##) Enable the SPIx interface clock.
+ (##) I2S pins configuration:
+ (+++) Enable the clock for the I2S GPIOs.
+ (+++) Configure these I2S pins as alternate function pull-up.
+ (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
+ and HAL_I2S_Receive_IT() APIs).
+ (+++) Configure the I2Sx interrupt priority.
+ (+++) Enable the NVIC I2S IRQ handle.
+ (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
+ and HAL_I2S_Receive_DMA() APIs:
+ (+++) Declare a DMA handle structure for the Tx/Rx channel.
+ (+++) Enable the DMAx interface clock.
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+ (+++) Configure the DMA Tx/Rx Channel.
+ (+++) Associate the initilalized DMA handle to the I2S DMA Tx/Rx handle.
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
+ DMA Tx/Rx Channel.
+
+ (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
+ using HAL_I2S_Init() function.
+
+ -@- The specific I2S interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
+ -@- Make sure that either:
+ (+@) I2S clock is configured based on SYSCLK or
+ (+@) External clock source is configured after setting correctly
+ the define constant EXTERNAL_CLOCK_VALUE in the stm32f3xx_hal_conf.h file.
+
+ (#) Three mode of operations are available within this driver :
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
+ (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
+ (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
+ (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_TxCpltCallback
+ (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
+ (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
+ (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_RxCpltCallback
+ (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_I2S_ErrorCallback
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
+ (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
+ (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_TxCpltCallback
+ (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
+ (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
+ (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_RxCpltCallback
+ (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_I2S_ErrorCallback
+ (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
+ (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
+ (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
+
+ *** I2S HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in I2S HAL driver.
+
+ (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
+ (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
+ (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
+ (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
+ (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
+
+ [..]
+ (@) You can refer to the I2S HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+#ifdef HAL_I2S_MODULE_ENABLED
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup I2S I2S
+ * @brief I2S HAL module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup I2S_Private_Functions I2S Private Functions
+ * @{
+ */
+static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
+static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
+static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void I2S_DMAError(DMA_HandleTypeDef *hdma);
+static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
+static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
+static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup I2S_Exported_Functions I2S Exported Functions
+ * @{
+ */
+
+/** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to initialize and
+ de-initialiaze the I2Sx peripheral in simplex mode:
+
+ (+) User must Implement HAL_I2S_MspInit() function in which he configures
+ all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+ (+) Call the function HAL_I2S_Init() to configure the selected device with
+ the selected configuration:
+ (++) Mode
+ (++) Standard
+ (++) Data Format
+ (++) MCLK Output
+ (++) Audio frequency
+ (++) Polarity
+ (++) Full duplex mode
+
+ (+) Call the function HAL_I2S_DeInit() to restore the default configuration
+ of the selected I2Sx periperal.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the I2S according to the specified parameters
+ * in the I2S_InitTypeDef and create the associated handle.
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+
+ /* Note : This function is defined into this file for library reference. */
+ /* Function content is located into file stm32f3xx_hal_i2s_ex.c to */
+ /* handle the possible I2S interfaces defined in STM32F3xx devices */
+
+ /* Return error status as not implemented here */
+ return HAL_ERROR;
+}
+
+/**
+ * @brief DeInitializes the I2S peripheral
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
+{
+ /* Check the I2S handle allocation */
+ if(hi2s == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
+
+ hi2s->State = HAL_I2S_STATE_BUSY;
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+ HAL_I2S_MspDeInit(hi2s);
+
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->State = HAL_I2S_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief I2S MSP Init
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+ __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2S MSP DeInit
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+ __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Exported_Functions_Group2 IO operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the I2S data
+ transfers.
+
+ (#) There are two modes of transfer:
+ (++) Blocking mode : The communication is performed in the polling mode.
+ The status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode : The communication is performed using Interrupts
+ or DMA. These functions return the status of the transfer startup.
+ The end of the data processing will be indicated through the
+ dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+
+ (#) Blocking mode functions are :
+ (++) HAL_I2S_Transmit()
+ (++) HAL_I2S_Receive()
+
+ (#) No-Blocking mode functions with Interrupt are :
+ (++) HAL_I2S_Transmit_IT()
+ (++) HAL_I2S_Receive_IT()
+
+ (#) No-Blocking mode functions with DMA are :
+ (++) HAL_I2S_Transmit_DMA()
+ (++) HAL_I2S_Receive_DMA()
+
+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+ (++) HAL_I2S_TxCpltCallback()
+ (++) HAL_I2S_RxCpltCallback()
+ (++) HAL_I2S_ErrorCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Transmit an amount of data in blocking mode
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param pData a 16-bit pointer to data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @param Timeout Timeout duration
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ if((pData == NULL ) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ if(hi2s->State == HAL_I2S_STATE_READY)
+ {
+ if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
+ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
+ {
+ hi2s->TxXferSize = (Size << 1U);
+ hi2s->TxXferCount = (Size << 1U);
+ }
+ else
+ {
+ hi2s->TxXferSize = Size;
+ hi2s->TxXferCount = Size;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->State = HAL_I2S_STATE_BUSY_TX;
+
+ /* Check if the I2S is already enabled */
+ if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ while(hi2s->TxXferCount > 0U)
+ {
+ hi2s->Instance->DR = (*pData++);
+ hi2s->TxXferCount--;
+ /* Wait until TXE flag is set */
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ {
+ /* Set the error code and execute error callback*/
+ hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;
+ HAL_I2S_ErrorCallback(hi2s);
+ return HAL_TIMEOUT;
+ }
+
+ /* Check if an underrun occurs */
+ if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
+ {
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ /* Set the error code and execute error callback*/
+ hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
+ HAL_I2S_ErrorCallback(hi2s);
+
+ return HAL_ERROR;
+ }
+ }
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param pData a 16-bit pointer to data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @param Timeout Timeout duration
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
+ * in continouse way and as the I2S is not disabled at the end of the I2S transaction.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ if((pData == NULL ) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ if(hi2s->State == HAL_I2S_STATE_READY)
+ {
+ if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
+ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
+ {
+ hi2s->RxXferSize = (Size << 1U);
+ hi2s->RxXferCount = (Size << 1U);
+ }
+ else
+ {
+ hi2s->RxXferSize = Size;
+ hi2s->RxXferCount = Size;
+ }
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->State = HAL_I2S_STATE_BUSY_RX;
+
+ /* Check if the I2S is already enabled */
+ if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Check if Master Receiver mode is selected */
+ if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
+ {
+ /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
+ access to the SPI_SR register. */
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+ }
+
+ /* Receive data */
+ while(hi2s->RxXferCount > 0U)
+ {
+ /* Wait until RXNE flag is set */
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ /* Set the error code and execute error callback*/
+ hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;
+ HAL_I2S_ErrorCallback(hi2s);
+ return HAL_TIMEOUT;
+ }
+
+ /* Check if an overrun occurs */
+ if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
+ {
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ /* Set the error code and execute error callback*/
+ hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
+ HAL_I2S_ErrorCallback(hi2s);
+
+ return HAL_ERROR;
+ }
+
+ (*pData++) = hi2s->Instance->DR;
+ hi2s->RxXferCount--;
+ }
+
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit an amount of data in non-blocking mode with Interrupt
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param pData a 16-bit pointer to data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
+{
+ if(hi2s->State == HAL_I2S_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ hi2s->pTxBuffPtr = pData;
+ if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
+ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
+ {
+ hi2s->TxXferSize = (Size << 1U);
+ hi2s->TxXferCount = (Size << 1U);
+ }
+ else
+ {
+ hi2s->TxXferSize = Size;
+ hi2s->TxXferCount = Size;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->State = HAL_I2S_STATE_BUSY_TX;
+
+ /* Enable TXE and ERR interrupt */
+ __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ /* Check if the I2S is already enabled */
+ if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode with Interrupt
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param pData a 16-bit pointer to the Receive data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation
+ * between Master and Slave otherwise the I2S interrupt should be optimized.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
+{
+ if(hi2s->State == HAL_I2S_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ hi2s->pRxBuffPtr = pData;
+ if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
+ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
+ {
+ hi2s->RxXferSize = (Size << 1U);
+ hi2s->RxXferCount = (Size << 1U);
+ }
+ else
+ {
+ hi2s->RxXferSize = Size;
+ hi2s->RxXferCount = Size;
+ }
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->State = HAL_I2S_STATE_BUSY_RX;
+
+ /* Enable TXE and ERR interrupt */
+ __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+ /* Check if the I2S is already enabled */
+ if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit an amount of data in non-blocking mode with DMA
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param pData a 16-bit pointer to the Transmit data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
+{
+ uint32_t *tmp;
+
+ if((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ if(hi2s->State == HAL_I2S_STATE_READY)
+ {
+ hi2s->pTxBuffPtr = pData;
+ if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
+ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
+ {
+ hi2s->TxXferSize = (Size << 1U);
+ hi2s->TxXferCount = (Size << 1U);
+ }
+ else
+ {
+ hi2s->TxXferSize = Size;
+ hi2s->TxXferCount = Size;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->State = HAL_I2S_STATE_BUSY_TX;
+
+ /* Set the I2S Tx DMA Half transfer complete callback */
+ hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
+
+ /* Set the I2S Tx DMA transfer complete callback */
+ hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
+
+ /* Set the DMA error callback */
+ hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
+
+ /* Enable the Tx DMA Channel */
+ tmp = (uint32_t*)&pData;
+ HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
+
+ /* Check if the I2S is already enabled */
+ if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Enable Tx DMA Request */
+ hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode with DMA
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param pData a 16-bit pointer to the Receive data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
+{
+ uint32_t *tmp;
+
+ if((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ if(hi2s->State == HAL_I2S_STATE_READY)
+ {
+ hi2s->pRxBuffPtr = pData;
+ if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
+ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
+ {
+ hi2s->RxXferSize = (Size << 1U);
+ hi2s->RxXferCount = (Size << 1U);
+ }
+ else
+ {
+ hi2s->RxXferSize = Size;
+ hi2s->RxXferCount = Size;
+ }
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->State = HAL_I2S_STATE_BUSY_RX;
+
+ /* Set the I2S Rx DMA Half transfer complete callback */
+ hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
+
+ /* Set the I2S Rx DMA transfer complete callback */
+ hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
+
+ /* Set the DMA error callback */
+ hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
+
+ /* Check if Master Receiver mode is selected */
+ if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
+ {
+ /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
+ access to the SPI_SR register. */
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+ }
+
+ /* Enable the Rx DMA Channel */
+ tmp = (uint32_t*)&pData;
+ HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
+
+ /* Check if the I2S is already enabled */
+ if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Enable Rx DMA Request */
+ hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Pauses the audio stream playing from the Media.
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
+{
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
+ {
+ /* Disable the I2S DMA Tx request */
+ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
+ }
+ else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
+ {
+ /* Disable the I2S DMA Rx request */
+ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resumes the audio stream playing from the Media.
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
+{
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
+ {
+ /* Enable the I2S DMA Tx request */
+ hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
+ }
+ else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
+ {
+ /* Enable the I2S DMA Rx request */
+ hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
+ }
+
+ /* If the I2S peripheral is still not enabled, enable it */
+ if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0U)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resumes the audio stream playing from the Media.
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
+{
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ /* Disable the I2S Tx/Rx DMA requests */
+ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
+ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
+
+ /* Abort the I2S DMA tx channel */
+ if(hi2s->hdmatx != NULL)
+ {
+ /* Disable the I2S DMA channel */
+ __HAL_DMA_DISABLE(hi2s->hdmatx);
+ HAL_DMA_Abort(hi2s->hdmatx);
+ }
+ /* Abort the I2S DMA rx channel */
+ if(hi2s->hdmarx != NULL)
+ {
+ /* Disable the I2S DMA channel */
+ __HAL_DMA_DISABLE(hi2s->hdmarx);
+ HAL_DMA_Abort(hi2s->hdmarx);
+ }
+
+ /* Disable I2S peripheral */
+ __HAL_I2S_DISABLE(hi2s);
+
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles I2S interrupt request.
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
+{
+ __IO uint32_t i2ssr = hi2s->Instance->SR;
+
+ if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
+ {
+ /* I2S in mode Receiver ----------------------------------------------------*/
+ if(((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
+ {
+ I2S_Receive_IT(hi2s);
+ }
+
+ /* I2S Overrun error interrupt occured -------------------------------------*/
+ if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
+ {
+ /* Disable RXNE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Set the error code and execute error callback*/
+ hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
+ HAL_I2S_ErrorCallback(hi2s);
+ }
+ }
+ else if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
+ {
+ /* I2S in mode Tramitter ---------------------------------------------------*/
+ if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
+ {
+ I2S_Transmit_IT(hi2s);
+ }
+
+ /* I2S Underrun error interrupt occured ------------------------------------*/
+ if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
+ {
+ /* Disable TXE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Set the error code and execute error callback*/
+ hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
+ HAL_I2S_ErrorCallback(hi2s);
+ }
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+
+/** @addtogroup I2S_Exported_Functions I2S Exported Functions
+ * @{
+ */
+
+/** @addtogroup I2S_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+/**
+ * @brief Tx Transfer Half completed callbacks
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+ __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx Transfer completed callbacks
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+ __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer half completed callbacks
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+__weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_RxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callbacks
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+__weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_RxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2S error callbacks
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+ __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the I2S state
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL state
+ */
+HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
+{
+ return hi2s->State;
+}
+
+/**
+ * @brief Return the I2S error code
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval I2S Error Code
+ */
+uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
+{
+ return hi2s->ErrorCode;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2S_Private_Functions I2S Private Functions
+ * @{
+ */
+/**
+ * @brief DMA I2S transmit process complete callback
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
+ {
+ /* Disable Tx DMA Request */
+ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
+
+ hi2s->TxXferCount = 0U;
+ hi2s->State = HAL_I2S_STATE_READY;
+ }
+ HAL_I2S_TxCpltCallback(hi2s);
+}
+
+/**
+ * @brief DMA I2S transmit process half complete callback
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ HAL_I2S_TxHalfCpltCallback(hi2s);
+}
+
+/**
+ * @brief DMA I2S receive process complete callback
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
+ {
+ /* Disable Rx DMA Request */
+ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
+ hi2s->RxXferCount = 0U;
+ hi2s->State = HAL_I2S_STATE_READY;
+ }
+ HAL_I2S_RxCpltCallback(hi2s);
+}
+
+/**
+ * @brief DMA I2S receive process half complete callback
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ HAL_I2S_RxHalfCpltCallback(hi2s);
+}
+
+/**
+ * @brief DMA I2S communication error callback
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void I2S_DMAError(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Disable Rx and Tx DMA Request */
+ hi2s->Instance->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
+ hi2s->TxXferCount = 0U;
+ hi2s->RxXferCount = 0U;
+
+ hi2s->State= HAL_I2S_STATE_READY;
+
+ /* Set the error code and execute error callback*/
+ hi2s->ErrorCode |= HAL_I2S_ERROR_DMA;
+ HAL_I2S_ErrorCallback(hi2s);
+}
+
+/**
+ * @brief Transmit an amount of data in non-blocking mode with Interrupt
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
+{
+ /* Transmit data */
+ hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
+ hi2s->TxXferCount--;
+
+ if(hi2s->TxXferCount == 0U)
+ {
+ /* Disable TXE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ hi2s->State = HAL_I2S_STATE_READY;
+ HAL_I2S_TxCpltCallback(hi2s);
+ }
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode with Interrupt
+ * @param hi2s: I2S handle
+ * @retval None
+ */
+static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
+{
+ /* Receive data */
+ (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
+ hi2s->RxXferCount--;
+
+ if(hi2s->RxXferCount == 0U)
+ {
+ /* Disable RXNE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+ hi2s->State = HAL_I2S_STATE_READY;
+ HAL_I2S_RxCpltCallback(hi2s);
+ }
+}
+
+/**
+ * @brief This function handles I2S Communication Timeout.
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param Flag Flag checked
+ * @param State Value of the flag expected
+ * @param Timeout Duration of the timeout
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Wait until flag is set */
+ if(State == RESET)
+ {
+ while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ /* Set the I2S State ready */
+ hi2s->State= HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else
+ {
+ while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ /* Set the I2S State ready */
+ hi2s->State= HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
+ /* STM32F373xC || STM32F378xx */
+
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_i2s_ex.c b/Src/stm32f3xx_hal_i2s_ex.c
new file mode 100644
index 0000000..d6b53f7
--- /dev/null
+++ b/Src/stm32f3xx_hal_i2s_ex.c
@@ -0,0 +1,1600 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_i2s_ex.c
+ * @author MCD Application Team
+ * @brief I2S Extended HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of I2S Extended peripheral:
+ * + Extended features Functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### I2S Extended features #####
+ ==============================================================================
+ [..]
+ (#) In I2S full duplex mode, each SPI peripheral is able to manage sending and receiving
+ data simultaneously using two data lines. Each SPI peripheral has an extended block
+ called I2Sxext ie. I2S2ext for SPI2 and I2S3ext for SPI3).
+ (#) The Extended block is not a full SPI IP, it is used only as I2S slave to
+ implement full duplex mode. The Extended block uses the same clock sources
+ as its master.
+
+ (#) Both I2Sx and I2Sx_ext can be configured as transmitters or receivers.
+
+ -@- Only I2Sx can deliver SCK and WS to I2Sx_ext in full duplex mode, where
+ I2Sx can be I2S2 or I2S3.
+
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ Three mode of operations are available within this driver :
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Send and receive in the same time an amount of data in blocking mode using HAL_I2S_TransmitReceive()
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Send and receive in the same time an amount of data in non blocking mode using HAL_I2S_TransmitReceive_IT()
+ (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
+ (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_TxCpltCallback
+ (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
+ (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_RxCpltCallback
+ (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_I2S_ErrorCallback
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Send and receive an amount of data in non blocking mode (DMA) using HAL_I2S_TransmitReceive_DMA()
+ (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
+ (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_TxCpltCallback
+ (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
+ (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_RxCpltCallback
+ (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_I2S_ErrorCallback
+ (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
+ (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
+ (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+/*
+ Additional Figure: The Extended block uses the same clock sources as its master.
+
+ +-----------------------+
+ I2Sx_SCK | |
+ ----------+-->| I2Sx |------------------->I2Sx_SD(in/out)
+ +--|-->| |
+ | | +-----------------------+
+ | |
+ I2S_WS | |
+ ------>| |
+ | | +-----------------------+
+ | +-->| |
+ | | I2Sx_ext |------------------->I2Sx_extSD(in/out)
+ +----->| |
+ +-----------------------+
+*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+#ifdef HAL_I2S_MODULE_ENABLED
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup I2SEx I2SEx
+ * @brief I2S Extended HAL module driver
+ * @{
+ */
+
+#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
+
+/* Private typedef -----------------------------------------------------------*/
+/** @defgroup I2SEx_Private_Typedef I2S Extended Private Typedef
+ * @{
+ */
+typedef enum
+{
+ I2S_USE_I2S = 0x00U, /*!< I2Sx should be used */
+ I2S_USE_I2SEXT = 0x01 /*!< I2Sx_ext should be used */
+}I2S_UseTypeDef;
+/**
+ * @}
+ */
+
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup I2SEx_Private_Functions I2S Extended Private Functions
+ * @{
+ */
+static void I2S_TxRxDMACplt(DMA_HandleTypeDef *hdma);
+static void I2S_TxRxDMAHalfCplt(DMA_HandleTypeDef *hdma);
+static void I2S_TxRxDMAError(DMA_HandleTypeDef *hdma);
+static void I2S_FullDuplexTx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed);
+static void I2S_FullDuplexRx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed);
+static HAL_StatusTypeDef I2S_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag,
+ uint32_t State, uint32_t Timeout, I2S_UseTypeDef i2sUsed);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @addtogroup I2S I2S
+ * @{
+ */
+
+/** @addtogroup I2S_Exported_Functions I2S Exported Functions
+ * @{
+ */
+
+/** @addtogroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to initialize and
+ de-initialiaze the I2Sx peripheral in simplex mode:
+
+ (+) User must Implement HAL_I2S_MspInit() function in which he configures
+ all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+ (+) Call the function HAL_I2S_Init() to configure the selected device with
+ the selected configuration:
+ (++) Mode
+ (++) Standard
+ (++) Data Format
+ (++) MCLK Output
+ (++) Audio frequency
+ (++) Polarity
+
+ (+) Call the function HAL_I2S_DeInit() to restore the default configuration
+ of the selected I2Sx periperal.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the I2S according to the specified parameters
+ * in the I2S_InitTypeDef and create the associated handle.
+ * @param hi2s: I2S handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
+{
+ uint16_t tmpreg = 0U, i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
+ uint32_t tmp = 0U, i2sclk = 0U;
+#if defined(SPI_I2S_FULLDUPLEX_SUPPORT)
+ RCC_PeriphCLKInitTypeDef rccperiphclkinit;
+#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
+
+ /* Check the I2S handle allocation */
+ if(hi2s == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
+ assert_param(IS_I2S_MODE(hi2s->Init.Mode));
+ assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
+ assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
+ assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
+ assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
+ assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
+ assert_param(IS_I2S_CLOCKSOURCE(hi2s->Init.ClockSource));
+ assert_param(IS_I2S_FULLDUPLEX_MODE(hi2s->Init.FullDuplexMode));
+
+ hi2s->State = HAL_I2S_STATE_BUSY;
+
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+ HAL_I2S_MspInit(hi2s);
+
+ /*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
+ /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
+ hi2s->Instance->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
+ SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
+ SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD);
+ hi2s->Instance->I2SPR = 0x0002U;
+
+ /* Get the I2SCFGR register value */
+ tmpreg = hi2s->Instance->I2SCFGR;
+
+ /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
+ if(hi2s->Init.AudioFreq == I2S_AUDIOFREQ_DEFAULT)
+ {
+ i2sodd = (uint16_t)0U;
+ i2sdiv = (uint16_t)2U;
+ }
+ /* If the requested audio frequency is not the default, compute the prescaler */
+ else
+ {
+ /* Check the frame length (For the Prescaler computing) *******************/
+ if(hi2s->Init.DataFormat == I2S_DATAFORMAT_16B)
+ {
+ /* Packet length is 16 bits */
+ packetlength = 1U;
+ }
+ else
+ {
+ /* Packet length is 32 bits */
+ packetlength = 2U;
+ }
+
+ /* Get I2S source Clock frequency ****************************************/
+#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
+ rccperiphclkinit.PeriphClockSelection = RCC_PERIPHCLK_I2S;
+
+ /* If an external I2S clock has to be used, the specific define should be set
+ in the project configuration or in the stm32f3xx_conf.h file */
+ if(hi2s->Init.ClockSource == I2S_CLOCK_EXTERNAL)
+ {
+ /* Set external clock as I2S clock source */
+ rccperiphclkinit.I2sClockSelection = RCC_I2SCLKSOURCE_EXT;
+ HAL_RCCEx_PeriphCLKConfig(&rccperiphclkinit);
+
+ /* Set the I2S clock to the external clock value */
+ i2sclk = EXTERNAL_CLOCK_VALUE;
+ }
+ else
+ {
+ /* Set SYSCLK as I2S clock source */
+ rccperiphclkinit.I2sClockSelection = RCC_I2SCLKSOURCE_SYSCLK;
+ HAL_RCCEx_PeriphCLKConfig(&rccperiphclkinit);
+
+ /* Get the I2S source clock value */
+ i2sclk = HAL_RCC_GetSysClockFreq();
+ }
+#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
+
+#if defined (STM32F373xC) || defined (STM32F378xx)
+ if(hi2s->Instance == SPI1)
+ {
+ i2sclk = HAL_RCC_GetPCLK2Freq();
+ }
+ else if((hi2s->Instance == SPI2) || (hi2s->Instance == SPI3))
+ {
+ i2sclk = HAL_RCC_GetPCLK1Freq();
+ }
+#endif /* STM32F373xC || STM32F378xx */
+
+ /* Compute the Real divider depending on the MCLK output state, with a floating point */
+ if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
+ {
+ /* MCLK output is enabled */
+ tmp = (uint16_t)(((((i2sclk / 256U) * 10U) / hi2s->Init.AudioFreq)) + 5U);
+ }
+ else
+ {
+ /* MCLK output is disabled */
+ tmp = (uint16_t)(((((i2sclk / (32U * packetlength)) *10U ) / hi2s->Init.AudioFreq)) + 5U);
+ }
+
+ /* Remove the flatting point */
+ tmp = tmp / 10U;
+
+ /* Check the parity of the divider */
+ i2sodd = (uint16_t)(tmp & (uint16_t)0x0001U);
+
+ /* Compute the i2sdiv prescaler */
+ i2sdiv = (uint16_t)((tmp - i2sodd) / 2U);
+
+ /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
+ i2sodd = (uint16_t) (i2sodd << 8U);
+ }
+
+ /* Test if the divider is 1 or 0 or greater than 0xFFU */
+ if((i2sdiv < 2U) || (i2sdiv > 0xFFU))
+ {
+ /* Set the default values */
+ i2sdiv = 2U;
+ i2sodd = 0U;
+ }
+
+ /* Write to SPIx I2SPR register the computed value */
+ hi2s->Instance->I2SPR = (uint16_t)((uint16_t)i2sdiv | (uint16_t)(i2sodd | (uint16_t)hi2s->Init.MCLKOutput));
+
+ /* Configure the I2S with the I2S_InitStruct values */
+ tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(hi2s->Init.Mode | \
+ (uint16_t)(hi2s->Init.Standard | (uint16_t)(hi2s->Init.DataFormat | \
+ (uint16_t)hi2s->Init.CPOL))));
+
+ /* Write to SPIx I2SCFGR */
+ hi2s->Instance->I2SCFGR = tmpreg;
+
+#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
+ if (hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
+ {
+ /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
+ I2SxEXT(hi2s->Instance)->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
+ SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
+ SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD);
+ I2SxEXT(hi2s->Instance)->I2SPR = 0x0002U;
+
+ /* Get the I2SCFGR register value */
+ tmpreg = I2SxEXT(hi2s->Instance)->I2SCFGR;
+
+ /* Get the mode to be configured for the extended I2S */
+ if((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX))
+ {
+ tmp = I2S_MODE_SLAVE_RX;
+ }
+ else
+ {
+ if((hi2s->Init.Mode == I2S_MODE_MASTER_RX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_RX))
+ {
+ tmp = I2S_MODE_SLAVE_TX;
+ }
+ }
+
+ /* Configure the I2S Slave with the I2S Master parameter values */
+ tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(tmp | \
+ (uint16_t)(hi2s->Init.Standard | (uint16_t)(hi2s->Init.DataFormat | \
+ (uint16_t)hi2s->Init.CPOL))));
+
+ /* Write to SPIx I2SCFGR */
+ I2SxEXT(hi2s->Instance)->I2SCFGR = tmpreg;
+ }
+#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
+
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->State= HAL_I2S_STATE_READY;
+
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
+/** @addtogroup I2S_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+
+/**
+ * @brief This function handles I2S/I2Sext interrupt requests in full-duplex mode.
+ * @param hi2s: I2S handle
+ * @retval HAL status
+ */
+void HAL_I2S_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s)
+{
+ __IO uint32_t i2ssr = hi2s->Instance->SR ;
+ __IO uint32_t i2sextsr = I2SxEXT(hi2s->Instance)->SR;
+
+ /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
+ if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
+ {
+ /* I2S in mode Transmitter -------------------------------------------------*/
+ if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
+ {
+ /* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX,
+ the I2S TXE interrupt will be generated to manage the full-duplex transmit phase. */
+ I2S_FullDuplexTx_IT(hi2s, I2S_USE_I2S);
+ }
+
+ /* I2Sext in mode Receiver -----------------------------------------------*/
+ if(((i2sextsr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2SEXT_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
+ {
+ /* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX,
+ the I2Sext RXNE interrupt will be generated to manage the full-duplex receive phase. */
+ I2S_FullDuplexRx_IT(hi2s, I2S_USE_I2SEXT);
+ }
+
+ /* I2Sext Overrun error interrupt occured --------------------------------*/
+ if(((i2sextsr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2SEXT_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
+ {
+ /* Disable RXNE and ERR interrupt */
+ __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+ /* Disable TXE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Set the error code and execute error callback*/
+ hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
+ HAL_I2S_ErrorCallback(hi2s);
+ }
+
+ /* I2S Underrun error interrupt occured ----------------------------------*/
+ if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
+ {
+ /* Disable TXE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ /* Disable RXNE and ERR interrupt */
+ __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Set the error code and execute error callback*/
+ hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
+ HAL_I2S_ErrorCallback(hi2s);
+ }
+ }
+ /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
+ else
+ {
+ /* I2Sext in mode Transmitter ----------------------------------------------*/
+ if(((i2sextsr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2SEXT_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
+ {
+ /* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX,
+ the I2Sext TXE interrupt will be generated to manage the full-duplex transmit phase. */
+ I2S_FullDuplexTx_IT(hi2s, I2S_USE_I2SEXT);
+ }
+
+ /* I2S in mode Receiver --------------------------------------------------*/
+ if(((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
+ {
+ /* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX,
+ the I2S RXNE interrupt will be generated to manage the full-duplex receive phase. */
+ I2S_FullDuplexRx_IT(hi2s, I2S_USE_I2S);
+ }
+
+ /* I2S Overrun error interrupt occured -------------------------------------*/
+ if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
+ {
+ /* Disable RXNE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+ /* Disable TXE and ERR interrupt */
+ __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Set the error code and execute error callback*/
+ hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
+ HAL_I2S_ErrorCallback(hi2s);
+ }
+
+ /* I2Sext Underrun error interrupt occured -------------------------------*/
+ if(((i2sextsr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2SEXT_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
+ {
+ /* Disable TXE and ERR interrupt */
+ __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ /* Disable RXNE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Set the error code and execute error callback*/
+ hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
+ HAL_I2S_ErrorCallback(hi2s);
+ }
+ }
+}
+
+/**
+ * @brief Tx and Rx Transfer completed callbacks
+ * @param hi2s: I2S handle
+ * @retval None
+ */
+__weak void HAL_I2S_TxRxCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_TxRxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx and Rx Transfer half completed callbacks
+ * @param hi2s: I2S handle
+ * @retval None
+ */
+__weak void HAL_I2S_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_TxRxHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
+
+/** @addtogroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief Peripheral State functions
+ *
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..]
+ This subsection permit to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Pauses the audio stream playing from the Media.
+ * @param hi2s : I2S handle
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
+{
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
+ {
+ /* Pause the audio file playing by disabling the I2S DMA request */
+ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
+ }
+ else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
+ {
+ /* Pause the audio file playing by disabling the I2S DMA request */
+ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
+ }
+#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
+ else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
+ {
+ /* Pause the audio file playing by disabling the I2S DMA request */
+ hi2s->Instance->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
+ I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
+ }
+#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resumes the audio stream playing from the Media.
+ * @param hi2s : I2S handle
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
+{
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
+ {
+ /* Enable the I2S DMA request */
+ hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
+ }
+ else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
+ {
+ /* Enable the I2S DMA request */
+ hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
+ }
+#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
+ else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
+ {
+ /* Pause the audio file playing by disabling the I2S DMA request */
+ hi2s->Instance->CR2 |= (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN);
+ I2SxEXT(hi2s->Instance)->CR2 |= (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN);
+
+ /* If the I2Sext peripheral is still not enabled, enable it */
+ if ((I2SxEXT(hi2s->Instance)->I2SCFGR & SPI_I2SCFGR_I2SE) == 0U)
+ {
+ /* Enable I2Sext peripheral */
+ __HAL_I2SEXT_ENABLE(hi2s);
+ }
+ }
+#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
+
+ /* If the I2S peripheral is still not enabled, enable it */
+ if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0U)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resumes the audio stream playing from the Media.
+ * @param hi2s: I2S handle
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
+{
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
+ {
+ /* Disable the I2S DMA requests */
+ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
+
+ /* Disable the I2S DMA Channel */
+ HAL_DMA_Abort(hi2s->hdmatx);
+ }
+ else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
+ {
+ /* Disable the I2S DMA requests */
+ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
+
+ /* Disable the I2S DMA Channel */
+ HAL_DMA_Abort(hi2s->hdmarx);
+ }
+#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
+ else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
+ {
+ /* Disable the I2S DMA requests */
+ hi2s->Instance->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
+ I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
+
+ /* Disable the I2S DMA Channels */
+ HAL_DMA_Abort(hi2s->hdmatx);
+ HAL_DMA_Abort(hi2s->hdmarx);
+
+ /* Disable I2Sext peripheral */
+ __HAL_I2SEXT_DISABLE(hi2s);
+ }
+#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
+
+ /* Disable I2S peripheral */
+ __HAL_I2S_DISABLE(hi2s);
+
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
+/** @addtogroup I2SEx
+ * @brief I2S Extended HAL module driver
+ * @{
+ */
+
+/** @defgroup I2SEx_Exported_Functions I2S Extended Exported Functions
+ * @{
+ */
+
+/** @defgroup I2SEx_Exported_Functions_Group1 I2S Extended Features Functions
+ * @brief Extended features functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended features Functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the I2S data
+ transfers.
+
+ (#) There is two mode of transfer:
+ (++) Blocking mode: The communication is performed in the polling mode.
+ The status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode: The communication is performed using Interrupts
+ or DMA. These functions return the status of the transfer startup.
+ The end of the data processing will be indicated through the
+ dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+
+ (#) Blocking mode functions are :
+ (++) HAL_I2S_TransmitReceive()
+
+ (#) No-Blocking mode functions with Interrupt are:
+ (++) HAL_I2S_TransmitReceive_IT()
+ (++) HAL_I2SFullDuplex_IRQHandler()
+
+ (#) No-Blocking mode functions with DMA are:
+ (++) HAL_I2S_TransmitReceive_DMA()
+
+ (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
+ (++) HAL_I2S_TxRxCpltCallback()
+ (++) HAL_I2S_TxRxHalfCpltCallback()
+ (++) HAL_I2S_TxRxErrorCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Full-Duplex Transmit/Receive data in blocking mode.
+ * @param hi2s: I2S handle
+ * @param pTxData a 16-bit pointer to the Transmit data buffer.
+ * @param pRxData a 16-bit pointer to the Receive data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @param Timeout Timeout duration
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size, uint32_t Timeout)
+{
+ if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the I2S State */
+ if(hi2s->State == HAL_I2S_STATE_READY)
+ {
+ /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
+ is selected during the I2S configuration phase, the Size parameter means the number
+ of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
+ frame is selected the Size parameter means the number of 16-bit data length. */
+ if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
+ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
+ {
+ hi2s->TxXferSize = (Size << 1U);
+ hi2s->TxXferCount = (Size << 1U);
+ hi2s->RxXferSize = (Size << 1U);
+ hi2s->RxXferCount = (Size << 1U);
+ }
+ else
+ {
+ hi2s->TxXferSize = Size;
+ hi2s->TxXferCount = Size;
+ hi2s->RxXferSize = Size;
+ hi2s->RxXferCount = Size;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+
+ /* Set the I2S State busy TX/RX */
+ hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
+
+ /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
+ if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
+ {
+ /* Prepare the First Data before enabling the I2S */
+ if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX)
+ {
+ hi2s->Instance->DR = (*pTxData++);
+ hi2s->TxXferCount--;
+ }
+
+ /* Check if the I2S is already enabled: The I2S is kept enabled at the end of transaction
+ to avoid the clock de-synchronization between Master and Slave. */
+ if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
+ __HAL_I2SEXT_ENABLE(hi2s);
+
+ /* Enable I2Sx peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ while(hi2s->RxXferCount > 0U)
+ {
+ /* Wait until TXE flag is set */
+ if (I2S_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout, I2S_USE_I2S) != HAL_OK)
+ {
+ /* Set the error code and execute error callback*/
+ hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;
+ HAL_I2S_ErrorCallback(hi2s);
+ return HAL_TIMEOUT;
+ }
+
+ if (hi2s->TxXferCount > 0U)
+ {
+ /* Check if an underrun occurs */
+ if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
+ {
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ /* Set the error code and execute error callback*/
+ hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
+ HAL_I2S_ErrorCallback(hi2s);
+
+ return HAL_ERROR;
+ }
+
+ hi2s->Instance->DR = (*pTxData++);
+ hi2s->TxXferCount--;
+ }
+
+ /* Wait until RXNE flag is set */
+ if (I2S_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout, I2S_USE_I2SEXT) != HAL_OK)
+ {
+ /* Set the error code and execute error callback*/
+ hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;
+ HAL_I2S_ErrorCallback(hi2s);
+ return HAL_TIMEOUT;
+ }
+
+ /* Check if an overrun occurs */
+ if(__HAL_I2SEXT_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
+ {
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ /* Set the error code and execute error callback*/
+ hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
+ HAL_I2S_ErrorCallback(hi2s);
+
+ return HAL_ERROR;
+ }
+
+ (*pRxData++) = I2SxEXT(hi2s->Instance)->DR;
+ hi2s->RxXferCount--;
+ }
+ }
+ /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
+ else
+ {
+ /* Prepare the First Data before enabling the I2S */
+ I2SxEXT(hi2s->Instance)->DR = (*pTxData++);
+ hi2s->TxXferCount--;
+
+ /* Check if the I2S is already enabled */
+ if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2S peripheral before the I2Sext*/
+ __HAL_I2S_ENABLE(hi2s);
+
+ /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
+ __HAL_I2SEXT_ENABLE(hi2s);
+ }
+
+ /* Check if Master Receiver mode is selected */
+ if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
+ {
+ /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
+ access to the SPI_SR register. */
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+ }
+
+ while(hi2s->RxXferCount > 0U)
+ {
+ /* Wait until TXE flag is set */
+ if (I2S_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout, I2S_USE_I2SEXT) != HAL_OK)
+ {
+ /* Set the error code and execute error callback*/
+ hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;
+ HAL_I2S_ErrorCallback(hi2s);
+ return HAL_TIMEOUT;
+ }
+
+ if (hi2s->TxXferCount > 0U)
+ {
+ /* Check if an underrun occurs */
+ if(__HAL_I2SEXT_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
+ {
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ /* Set the error code and execute error callback*/
+ hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
+ HAL_I2S_ErrorCallback(hi2s);
+
+ return HAL_ERROR;
+ }
+
+ I2SxEXT(hi2s->Instance)->DR = (*pTxData++);
+ hi2s->TxXferCount--;
+ }
+
+ /* Wait until RXNE flag is set */
+ if (I2S_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout, I2S_USE_I2S) != HAL_OK)
+ {
+ /* Set the error code and execute error callback*/
+ hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;
+ HAL_I2S_ErrorCallback(hi2s);
+ return HAL_TIMEOUT;
+ }
+
+ /* Check if an overrun occurs */
+ if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
+ {
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ /* Set the error code and execute error callback*/
+ hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
+ HAL_I2S_ErrorCallback(hi2s);
+
+ return HAL_ERROR;
+ }
+
+ (*pRxData++) = hi2s->Instance->DR;
+ hi2s->RxXferCount--;
+ }
+ }
+
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt
+ * @param hi2s: I2S handle
+ * @param pTxData a 16-bit pointer to the Transmit data buffer.
+ * @param pRxData a 16-bit pointer to the Receive data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size)
+{
+ if(hi2s->State == HAL_I2S_STATE_READY)
+ {
+ if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ hi2s->pTxBuffPtr = pTxData;
+ hi2s->pRxBuffPtr = pRxData;
+
+ /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
+ is selected during the I2S configuration phase, the Size parameter means the number
+ of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
+ frame is selected the Size parameter means the number of 16-bit data length. */
+ if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
+ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
+ {
+ hi2s->TxXferSize = (Size << 1U);
+ hi2s->TxXferCount = (Size << 1U);
+ hi2s->RxXferSize = (Size << 1U);
+ hi2s->RxXferCount = (Size << 1U);
+ }
+ else
+ {
+ hi2s->TxXferSize = Size;
+ hi2s->TxXferCount = Size;
+ hi2s->RxXferSize = Size;
+ hi2s->RxXferCount = Size;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
+
+ /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
+ if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
+ {
+ /* Enable I2Sext RXNE and ERR interrupts */
+ __HAL_I2SEXT_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+ /* Enable I2Sx TXE and ERR interrupts */
+ __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ /* Check if the I2S is already enabled */
+ if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX)
+ {
+ /* Prepare the First Data before enabling the I2S */
+ if(hi2s->TxXferCount != 0U)
+ {
+ /* Transmit First data */
+ hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
+ hi2s->TxXferCount--;
+
+ if(hi2s->TxXferCount == 0U)
+ {
+ /* Disable TXE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ if(hi2s->RxXferCount == 0U)
+ {
+ /* Disable I2Sext RXNE and ERR interrupt */
+ __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE| I2S_IT_ERR));
+
+ hi2s->State = HAL_I2S_STATE_READY;
+ HAL_I2S_TxRxCpltCallback(hi2s);
+ }
+ }
+ }
+ }
+ /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
+ __HAL_I2SEXT_ENABLE(hi2s);
+
+ /* Enable I2Sx peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+ }
+ /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
+ else
+ {
+ /* Enable I2Sext TXE and ERR interrupts */
+ __HAL_I2SEXT_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ /* Enable I2Sext RXNE and ERR interrupts */
+ __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+ /* Check if the I2S is already enabled */
+ if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Prepare the First Data before enabling the I2S */
+ if(hi2s->TxXferCount != 0U)
+ {
+ /* Transmit First data */
+ I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++);
+ hi2s->TxXferCount--;
+
+ if(hi2s->TxXferCount == 0U)
+ {
+ /* Disable I2Sext TXE and ERR interrupt */
+ __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ if(hi2s->RxXferCount == 0U)
+ {
+ /* Disable RXNE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE| I2S_IT_ERR));
+
+ hi2s->State = HAL_I2S_STATE_READY;
+ HAL_I2S_TxRxCpltCallback(hi2s);
+ }
+ }
+ }
+ /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
+ __HAL_I2SEXT_ENABLE(hi2s);
+
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+ }
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Full-Duplex Transmit/Receive data in non-blocking mode using DMA
+ * @param hi2s: I2S handle
+ * @param pTxData a 16-bit pointer to the Transmit data buffer.
+ * @param pRxData a 16-bit pointer to the Receive data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size)
+{
+ uint32_t *tmp;
+
+ if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ if(hi2s->State == HAL_I2S_STATE_READY)
+ {
+ hi2s->pTxBuffPtr = pTxData;
+ hi2s->pRxBuffPtr = pRxData;
+
+ /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
+ is selected during the I2S configuration phase, the Size parameter means the number
+ of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
+ frame is selected the Size parameter means the number of 16-bit data length. */
+ if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
+ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
+ {
+ hi2s->TxXferSize = (Size << 1U);
+ hi2s->TxXferCount = (Size << 1U);
+ hi2s->RxXferSize = (Size << 1U);
+ hi2s->RxXferCount = (Size << 1U);
+ }
+ else
+ {
+ hi2s->TxXferSize = Size;
+ hi2s->TxXferCount = Size;
+ hi2s->RxXferSize = Size;
+ hi2s->RxXferCount = Size;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
+
+ /* Set the I2S Rx DMA transfer complete callback */
+ hi2s->hdmarx->XferCpltCallback = I2S_TxRxDMACplt;
+
+ /* Set the I2S Rx DMA Half transfer complete callback */
+ hi2s->hdmarx->XferHalfCpltCallback = I2S_TxRxDMAHalfCplt;
+
+ /* Set the I2S Rx DMA error callback */
+ hi2s->hdmarx->XferErrorCallback = I2S_TxRxDMAError;
+
+ /* Set the I2S Tx DMA transfer callbacks as NULL because the
+ communication closing is performed in DMA reception callbacks */
+ hi2s->hdmatx->XferCpltCallback = NULL;
+ hi2s->hdmatx->XferHalfCpltCallback = NULL;
+
+ /* Set the I2S Tx DMA error callback */
+ hi2s->hdmatx->XferErrorCallback = I2S_TxRxDMAError;
+
+ /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
+ if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
+ {
+ /* Enable the Rx DMA Channel */
+ tmp = (uint32_t*)&pRxData;
+ HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
+
+ /* Enable Rx DMA Request */
+ I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_RXDMAEN;
+
+ /* Enable the Tx DMA Channel */
+ tmp = (uint32_t*)&pTxData;
+ HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
+
+ /* Enable Tx DMA Request */
+ hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
+
+ /* Check if the I2S is already enabled */
+ if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
+ __HAL_I2SEXT_ENABLE(hi2s);
+
+ /* Enable I2S peripheral after the I2Sext*/
+ __HAL_I2S_ENABLE(hi2s);
+ }
+ }
+ else
+ {
+ /* Check if Master Receiver mode is selected */
+ if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
+ {
+ /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
+ access to the SPI_SR register. */
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+ }
+
+ /* Enable the Tx DMA Channel */
+ tmp = (uint32_t*)&pTxData;
+ HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, hi2s->TxXferSize);
+
+ /* Enable Tx DMA Request */
+ I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_TXDMAEN;
+
+ /* Enable the Rx DMA Channel */
+ tmp = (uint32_t*)&pRxData;
+ HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
+
+ /* Enable Rx DMA Request */
+ hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
+
+ /* Check if the I2S is already enabled */
+ if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2Sext(transmitter) before enabling I2Sx peripheral */
+ __HAL_I2SEXT_ENABLE(hi2s);
+
+ /* Enable I2S peripheral after the I2Sext*/
+ __HAL_I2S_ENABLE(hi2s);
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2SEx_Private_Functions I2S Extended Private Functions
+ * @{
+ */
+
+/**
+ * @brief DMA I2S transmit receive process complete callback
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void I2S_TxRxDMACplt(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* DMA Normal Mode */
+ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
+ {
+ /* Disable Rx/Tx DMA Request */
+ if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
+ {
+ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
+ I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
+ }
+ else
+ {
+ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
+ I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
+ }
+
+ hi2s->RxXferCount = 0U;
+ hi2s->TxXferCount = 0U;
+
+ hi2s->State = HAL_I2S_STATE_READY;
+ }
+
+ HAL_I2S_TxRxCpltCallback(hi2s);
+}
+
+static void I2S_TxRxDMAHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ HAL_I2S_TxRxHalfCpltCallback(hi2s);
+}
+
+/**
+ * @brief DMA I2S communication error callback
+ * @param hdma : DMA handle
+ * @retval None
+ */
+static void I2S_TxRxDMAError(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Disable Rx and Tx DMA Request */
+ hi2s->Instance->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
+ I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
+
+ hi2s->TxXferCount = 0U;
+ hi2s->RxXferCount = 0U;
+
+ hi2s->State= HAL_I2S_STATE_READY;
+
+ /* Set the error code and execute error callback*/
+ hi2s->ErrorCode |= HAL_I2S_ERROR_DMA;
+ HAL_I2S_ErrorCallback(hi2s);
+}
+
+/**
+ * @brief Full-Duplex IT handler transmit function
+ * @param hi2s: I2S handle
+ * @param i2sUsed: indicate if I2Sx or I2Sx_ext is concerned
+ * @retval None
+ */
+static void I2S_FullDuplexTx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed)
+{
+ if(i2sUsed == I2S_USE_I2S)
+ {
+ /* Transmit data */
+ hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
+ hi2s->TxXferCount--;
+
+ if(hi2s->TxXferCount == 0U)
+ {
+ /* Disable TXE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ if(hi2s->RxXferCount == 0U)
+ {
+ hi2s->State = HAL_I2S_STATE_READY;
+ HAL_I2S_TxRxCpltCallback(hi2s);
+ }
+ }
+ }
+ else
+ {
+ /* Transmit data */
+ I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++);
+ hi2s->TxXferCount--;
+
+ if(hi2s->TxXferCount == 0U)
+ {
+ /* Disable I2Sext TXE and ERR interrupt */
+ __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ if(hi2s->RxXferCount == 0U)
+ {
+ hi2s->State = HAL_I2S_STATE_READY;
+ HAL_I2S_TxRxCpltCallback(hi2s);
+ }
+ }
+ }
+}
+
+/**
+ * @brief Full-Duplex IT handler receive function
+ * @param hi2s: I2S handle
+ * @param i2sUsed: indicate if I2Sx or I2Sx_ext is concerned
+ * @retval None
+ */
+static void I2S_FullDuplexRx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed)
+{
+ if(i2sUsed == I2S_USE_I2S)
+ {
+ /* Receive data */
+ (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
+ hi2s->RxXferCount--;
+
+ if(hi2s->RxXferCount == 0U)
+ {
+ /* Disable RXNE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+ if(hi2s->TxXferCount == 0U)
+ {
+ hi2s->State = HAL_I2S_STATE_READY;
+ HAL_I2S_TxRxCpltCallback(hi2s);
+ }
+ }
+ }
+ else
+ {
+ /* Receive data */
+ (*hi2s->pRxBuffPtr++) = I2SxEXT(hi2s->Instance)->DR;
+ hi2s->RxXferCount--;
+
+ if(hi2s->RxXferCount == 0U)
+ {
+ /* Disable I2Sext RXNE and ERR interrupt */
+ __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+ if(hi2s->TxXferCount == 0U)
+ {
+ hi2s->State = HAL_I2S_STATE_READY;
+ HAL_I2S_TxRxCpltCallback(hi2s);
+ }
+ }
+ }
+}
+
+/**
+ * @brief This function handles I2S Communication Timeout.
+ * @param hi2s: I2S handle
+ * @param Flag Flag checked
+ * @param State Value of the flag expected
+ * @param Timeout Duration of the timeout
+ * @param i2sUsed: I2S instance reference
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2S_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag,
+ uint32_t State, uint32_t Timeout, I2S_UseTypeDef i2sUsed)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ if(i2sUsed == I2S_USE_I2S)
+ {
+ if(State == RESET)
+ {
+ /* Wait until flag is reset */
+ while((__HAL_I2S_GET_FLAG(hi2s, Flag)) != RESET)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ /* Set the I2S State ready */
+ hi2s->State= HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else /* State == SET */
+ {
+ /* Wait until flag is set */
+ while((__HAL_I2S_GET_FLAG(hi2s, Flag)) != SET)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ /* Set the I2S State ready */
+ hi2s->State= HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ }
+ else /* i2sUsed == I2S_USE_I2SEXT */
+ {
+ if(State == RESET)
+ {
+ /* Wait until flag is reset */
+ while((__HAL_I2SEXT_GET_FLAG(hi2s, Flag)) != RESET)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ /* Set the I2S State ready */
+ hi2s->State= HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else /* State == SET */
+ {
+ /* Wait until flag is set */
+ while((__HAL_I2SEXT_GET_FLAG(hi2s, Flag)) != SET)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ /* Set the I2S State ready */
+ hi2s->State= HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ }
+
+ return HAL_OK;
+}
+#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
+ /* STM32F373xC || STM32F378xx */
+
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_irda.c b/Src/stm32f3xx_hal_irda.c
new file mode 100644
index 0000000..7c84358
--- /dev/null
+++ b/Src/stm32f3xx_hal_irda.c
@@ -0,0 +1,2294 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_irda.c
+ * @author MCD Application Team
+ * @brief IRDA HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the IrDA (Infrared Data Association) Peripheral
+ * (IRDA)
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral State and Errors functions
+ * + Peripheral Control functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The IRDA HAL driver can be used as follows:
+
+ (#) Declare a IRDA_HandleTypeDef handle structure (eg. IRDA_HandleTypeDef hirda).
+ (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API
+ in setting the associated USART or UART in IRDA mode:
+ (++) Enable the USARTx/UARTx interface clock.
+ (++) USARTx/UARTx pins configuration:
+ (+++) Enable the clock for the USARTx/UARTx GPIOs.
+ (+++) Configure these USARTx/UARTx pins (TX as alternate function pull-up, RX as alternate function Input).
+ (++) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
+ and HAL_IRDA_Receive_IT() APIs):
+ (+++) Configure the USARTx/UARTx interrupt priority.
+ (+++) Enable the NVIC USARTx/UARTx IRQ handle.
+ (+++) The specific IRDA interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
+
+ (++) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
+ and HAL_IRDA_Receive_DMA() APIs):
+ (+++) Declare a DMA handle structure for the Tx/Rx channel.
+ (+++) Enable the DMAx interface clock.
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+ (+++) Configure the DMA Tx/Rx channel.
+ (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
+
+ (#) Program the Baud Rate, Word Length and Parity and Mode(Receiver/Transmitter),
+ the normal or low power mode and the clock prescaler in the hirda handle Init structure.
+
+ (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
+ (++) This API configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)
+ by calling the customized HAL_IRDA_MspInit() API.
+
+ -@@- The specific IRDA interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
+
+ (#) Three operation modes are available within this driver :
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()
+ (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Send an amount of data in non-blocking mode using HAL_IRDA_Transmit_IT()
+ (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
+ (+) Receive an amount of data in non-blocking mode using HAL_IRDA_Receive_IT()
+ (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
+ (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_ErrorCallback()
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Send an amount of data in non-blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
+ (+) At transmission half of transfer HAL_IRDA_TxHalfCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_TxHalfCpltCallback()
+ (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
+ (+) Receive an amount of data in non-blocking mode (DMA) using HAL_IRDA_Receive_DMA()
+ (+) At reception half of transfer HAL_IRDA_RxHalfCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_RxHalfCpltCallback()
+ (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
+ (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_ErrorCallback()
+
+ *** IRDA HAL driver macros list ***
+ ====================================
+ [..]
+ Below the list of most used macros in IRDA HAL driver.
+
+ (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
+ (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
+ (+) __HAL_IRDA_GET_FLAG : Check whether the specified IRDA flag is set or not
+ (+) __HAL_IRDA_CLEAR_FLAG : Clear the specified IRDA pending flag
+ (+) __HAL_IRDA_ENABLE_IT: Enable the specified IRDA interrupt
+ (+) __HAL_IRDA_DISABLE_IT: Disable the specified IRDA interrupt
+ (+) __HAL_IRDA_GET_IT_SOURCE: Check whether or not the specified IRDA interrupt is enabled
+
+ [..]
+ (@) You can refer to the IRDA HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup IRDA IRDA
+ * @brief IRDA HAL module driver
+ * @{
+ */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup IRDA_Private_Constants IRDA Private Constants
+ * @{
+ */
+#define IRDA_TEACK_REACK_TIMEOUT 1000 /*!< IRDA TX or RX enable acknowledge time-out value */
+#define IRDA_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE \
+ | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)) /*!< UART or USART CR1 fields of parameters set by IRDA_SetConfig API */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup IRDA_Private_Functions
+ * @{
+ */
+static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda);
+static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda);
+static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
+static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda);
+static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda);
+static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma);
+static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma);
+static void IRDA_DMAError(DMA_HandleTypeDef *hdma);
+static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
+static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);
+static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup IRDA_Exported_Functions IRDA Exported Functions
+ * @{
+ */
+
+/** @defgroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and Configuration functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the USARTx
+ in asynchronous IRDA mode.
+ (+) For the asynchronous mode only these parameters can be configured:
+ (++) Baud Rate
+ (++) Word Length
+ (++) Parity
+ (++) Power mode
+ (++) Prescaler setting
+ (++) Receiver/transmitter modes
+
+ [..]
+ The HAL_IRDA_Init() API follows the USART asynchronous configuration procedures
+ (details for the procedures are available in reference manual).
+
+@endverbatim
+ * @{
+ */
+
+/*
+ Additional remark: If the parity is enabled, then the MSB bit of the data written
+ in the data register is transmitted but is changed by the parity bit.
+ According to device capability (support or not of 7-bit word length),
+ frame length is either defined by the M bit (8-bits or 9-bits)
+ or by the M1 and M0 bits (7-bit, 8-bit or 9-bit).
+ Possible IRDA frame formats are as listed in the following table:
+
+ Table 1. IRDA frame format.
+ +-----------------------------------------------------------------------+
+ | M bit | PCE bit | IRDA frame |
+ |-------------------|-----------|---------------------------------------|
+ | 0 | 0 | | SB | 8-bit data | STB | |
+ |-------------------|-----------|---------------------------------------|
+ | 0 | 1 | | SB | 7-bit data | PB | STB | |
+ |-------------------|-----------|---------------------------------------|
+ | 1 | 0 | | SB | 9-bit data | STB | |
+ |-------------------|-----------|---------------------------------------|
+ | 1 | 1 | | SB | 8-bit data | PB | STB | |
+ +-----------------------------------------------------------------------+
+ | M1 bit | M0 bit | PCE bit | IRDA frame |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 0 | 0 | | SB | 8 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 1 | 0 | | SB | 9 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 1 | 0 | 0 | | SB | 7 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
+ +-----------------------------------------------------------------------+
+
+*/
+
+/**
+ * @brief Initialize the IRDA mode according to the specified
+ * parameters in the IRDA_InitTypeDef and initialize the associated handle.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
+{
+ /* Check the IRDA handle allocation */
+ if(hirda == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the USART/UART associated to the IRDA handle */
+ assert_param(IS_IRDA_INSTANCE(hirda->Instance));
+
+ if(hirda->gState == HAL_IRDA_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hirda->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_IRDA_MspInit(hirda);
+ }
+
+ hirda->gState = HAL_IRDA_STATE_BUSY;
+
+ /* Disable the Peripheral to update the configuration registers */
+ __HAL_IRDA_DISABLE(hirda);
+
+ /* Set the IRDA Communication parameters */
+ if (IRDA_SetConfig(hirda) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ /* In IRDA mode, the following bits must be kept cleared:
+ - LINEN, STOP and CLKEN bits in the USART_CR2 register,
+ - SCEN and HDSEL bits in the USART_CR3 register.*/
+ CLEAR_BIT(hirda->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
+ CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
+
+ /* set the UART/USART in IRDA mode */
+ hirda->Instance->CR3 |= USART_CR3_IREN;
+
+ /* Enable the Peripheral */
+ __HAL_IRDA_ENABLE(hirda);
+
+ /* TEACK and/or REACK to check before moving hirda->gState and hirda->RxState to Ready */
+ return (IRDA_CheckIdleState(hirda));
+}
+
+/**
+ * @brief DeInitialize the IRDA peripheral.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
+{
+ /* Check the IRDA handle allocation */
+ if(hirda == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the USART/UART associated to the IRDA handle */
+ assert_param(IS_IRDA_INSTANCE(hirda->Instance));
+
+ hirda->gState = HAL_IRDA_STATE_BUSY;
+
+ /* DeInit the low level hardware */
+ HAL_IRDA_MspDeInit(hirda);
+ /* Disable the Peripheral */
+ __HAL_IRDA_DISABLE(hirda);
+
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ hirda->gState = HAL_IRDA_STATE_RESET;
+ hirda->RxState = HAL_IRDA_STATE_RESET;
+
+ /* Process Unlock */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the IRDA MSP.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+__weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_IRDA_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the IRDA MSP.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+__weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_IRDA_MspDeInit can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Exported_Functions_Group2 IO operation functions
+ * @brief IRDA Transmit and Receive functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the IRDA data transfers.
+
+ [..]
+ IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
+ on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
+ is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
+ While receiving data, transmission should be avoided as the data to be transmitted
+ could be corrupted.
+
+ (#) There are two mode of transfer:
+ (++) Blocking mode: the communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) Non-Blocking mode: the communication is performed using Interrupts
+ or DMA, these API's return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
+ will be executed respectively at the end of the Transmit or Receive process
+ The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected
+
+ (#) Blocking mode APIs are :
+ (++) HAL_IRDA_Transmit()
+ (++) HAL_IRDA_Receive()
+
+ (#) Non Blocking mode APIs with Interrupt are :
+ (++) HAL_IRDA_Transmit_IT()
+ (++) HAL_IRDA_Receive_IT()
+ (++) HAL_IRDA_IRQHandler()
+
+ (#) Non Blocking mode functions with DMA are :
+ (++) HAL_IRDA_Transmit_DMA()
+ (++) HAL_IRDA_Receive_DMA()
+ (++) HAL_IRDA_DMAPause()
+ (++) HAL_IRDA_DMAResume()
+ (++) HAL_IRDA_DMAStop()
+
+ (#) A set of Transfer Complete Callbacks are provided in Non Blocking mode:
+ (++) HAL_IRDA_TxHalfCpltCallback()
+ (++) HAL_IRDA_TxCpltCallback()
+ (++) HAL_IRDA_RxHalfCpltCallback()
+ (++) HAL_IRDA_RxCpltCallback()
+ (++) HAL_IRDA_ErrorCallback()
+
+ (#) Non-Blocking mode transfers could be aborted using Abort API's :
+ (++) HAL_IRDA_Abort()
+ (++) HAL_IRDA_AbortTransmit()
+ (++) HAL_IRDA_AbortReceive()
+ (++) HAL_IRDA_Abort_IT()
+ (++) HAL_IRDA_AbortTransmit_IT()
+ (++) HAL_IRDA_AbortReceive_IT()
+
+ (#) For Abort services based on interrupts (HAL_IRDA_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
+ (++) HAL_IRDA_AbortCpltCallback()
+ (++) HAL_IRDA_AbortTransmitCpltCallback()
+ (++) HAL_IRDA_AbortReceiveCpltCallback()
+
+ (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
+ Errors are handled as follows :
+ (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+ to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
+ Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
+ and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side.
+ If user wants to abort it, Abort services should be called by user.
+ (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+ This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
+ Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Send an amount of data in blocking mode.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData Pointer to data buffer.
+ * @param Size Amount of data to be sent.
+ * @param Timeout Specify timeout value.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint16_t* tmp;
+ uint32_t tickstart = 0U;
+
+ /* Check that a Tx process is not already ongoing */
+ if(hirda->gState == HAL_IRDA_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ hirda->gState = HAL_IRDA_STATE_BUSY_TX;
+
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
+
+ hirda->TxXferSize = Size;
+ hirda->TxXferCount = Size;
+ while(hirda->TxXferCount > 0U)
+ {
+ hirda->TxXferCount--;
+
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+ {
+ tmp = (uint16_t*) pData;
+ hirda->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
+ pData += 2U;
+ }
+ else
+ {
+ hirda->Instance->TDR = (*pData++ & (uint8_t)0xFFU);
+ }
+ }
+
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* At end of Tx process, restore hirda->gState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData Pointer to data buffer.
+ * @param Size Amount of data to be received.
+ * @param Timeout Specify timeout value.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint16_t* tmp;
+ uint16_t uhMask;
+ uint32_t tickstart = 0U;
+
+ /* Check that a Rx process is not already ongoing */
+ if(hirda->RxState == HAL_IRDA_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
+
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
+
+ hirda->RxXferSize = Size;
+ hirda->RxXferCount = Size;
+
+ /* Computation of the mask to apply to RDR register
+ of the UART associated to the IRDA */
+ IRDA_MASK_COMPUTATION(hirda);
+ uhMask = hirda->Mask;
+
+ /* Check data remaining to be received */
+ while(hirda->RxXferCount > 0U)
+ {
+ hirda->RxXferCount--;
+
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+ {
+ tmp = (uint16_t*) pData ;
+ *tmp = (uint16_t)(hirda->Instance->RDR & uhMask);
+ pData +=2U;
+ }
+ else
+ {
+ *pData++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask);
+ }
+ }
+
+ /* At end of Rx process, restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in interrupt mode.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData Pointer to data buffer.
+ * @param Size Amount of data to be sent.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+{
+ /* Check that a Tx process is not already ongoing */
+ if(hirda->gState == HAL_IRDA_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ hirda->pTxBuffPtr = pData;
+ hirda->TxXferSize = Size;
+ hirda->TxXferCount = Size;
+
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ hirda->gState = HAL_IRDA_STATE_BUSY_TX;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ /* Enable the IRDA Transmit Data Register Empty Interrupt */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_TXEIE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in interrupt mode.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData Pointer to data buffer.
+ * @param Size Amount of data to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+{
+ /* Check that a Rx process is not already ongoing */
+ if(hirda->RxState == HAL_IRDA_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ hirda->pRxBuffPtr = pData;
+ hirda->RxXferSize = Size;
+ hirda->RxXferCount = Size;
+
+ /* Computation of the mask to apply to the RDR register
+ of the UART associated to the IRDA */
+ IRDA_MASK_COMPUTATION(hirda);
+
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ /* Enable the IRDA Parity Error and Data Register not empty Interrupts */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE);
+
+ /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in DMA mode.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData pointer to data buffer.
+ * @param Size amount of data to be sent.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+{
+ /* Check if USART/UART instance associated to the IRDA handle supports continuous communication using DMA */
+ assert_param(IS_UART_DMA_INSTANCE(hirda->Instance));
+
+ /* Check that a Tx process is not already ongoing */
+ if(hirda->gState == HAL_IRDA_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ hirda->pTxBuffPtr = pData;
+ hirda->TxXferSize = Size;
+ hirda->TxXferCount = Size;
+
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ hirda->gState = HAL_IRDA_STATE_BUSY_TX;
+
+ /* Set the IRDA DMA transfer complete callback */
+ hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt;
+
+ /* Set the IRDA DMA half transfer complete callback */
+ hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt;
+
+ /* Set the DMA error callback */
+ hirda->hdmatx->XferErrorCallback = IRDA_DMAError;
+
+ /* Set the DMA abort callback */
+ hirda->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the IRDA transmit DMA channel */
+ HAL_DMA_Start_IT(hirda->hdmatx, (uint32_t)hirda->pTxBuffPtr, (uint32_t)&hirda->Instance->TDR, Size);
+
+ /* Clear the TC flag in the ICR register */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_TCF);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the USART CR3 register */
+ SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in DMA mode.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData Pointer to data buffer.
+ * @param Size Amount of data to be received.
+ * @note When the IRDA parity is enabled (PCE = 1), the received data contains
+ * the parity bit (MSB position).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+{
+ /* Check if USART/UART instance associated to the IRDA handle supports continuous communication using DMA */
+ assert_param(IS_UART_DMA_INSTANCE(hirda->Instance));
+
+ /* Check that a Rx process is not already ongoing */
+ if(hirda->RxState == HAL_IRDA_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ hirda->pRxBuffPtr = pData;
+ hirda->RxXferSize = Size;
+
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
+
+ /* Set the IRDA DMA transfer complete callback */
+ hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt;
+
+ /* Set the IRDA DMA half transfer complete callback */
+ hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt;
+
+ /* Set the DMA error callback */
+ hirda->hdmarx->XferErrorCallback = IRDA_DMAError;
+
+ /* Set the DMA abort callback */
+ hirda->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, (uint32_t)hirda->pRxBuffPtr, Size);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ /* Enable the UART Parity Error Interrupt */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+
+ /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the USART CR3 register */
+ SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+
+/**
+ * @brief Pause the DMA Transfer.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)
+{
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) &&
+ (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)))
+ {
+ /* Disable the IRDA DMA Tx request */
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+ }
+ if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) &&
+ (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))
+ {
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the IRDA DMA Rx request */
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resume the DMA Transfer.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
+{
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
+ {
+ /* Enable the IRDA DMA Tx request */
+ SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+ }
+ if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
+ {
+ /* Clear the Overrun flag before resuming the Rx transfer*/
+ __HAL_IRDA_CLEAR_OREFLAG(hirda);
+
+ /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+ SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the IRDA DMA Rx request */
+ SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the DMA Transfer.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
+{
+ /* The Lock is not implemented on this API to allow the user application
+ to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback() /
+ HAL_IRDA_TxHalfCpltCallback() / HAL_IRDA_RxHalfCpltCallback():
+ indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
+ interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
+ the stream and the corresponding call back is executed. */
+
+ /* Stop IRDA DMA Tx request if ongoing */
+ if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) &&
+ (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the IRDA DMA Tx channel */
+ if(hirda->hdmatx != NULL)
+ {
+ HAL_DMA_Abort(hirda->hdmatx);
+ }
+
+ IRDA_EndTxTransfer(hirda);
+ }
+
+ /* Stop IRDA DMA Rx request if ongoing */
+ if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) &&
+ (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the IRDA DMA Rx channel */
+ if(hirda->hdmarx != NULL)
+ {
+ HAL_DMA_Abort(hirda->hdmarx);
+ }
+
+ IRDA_EndRxTransfer(hirda);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing transfers (blocking mode).
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable IRDA Interrupts (Tx and Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the IRDA DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if(hirda->hdmatx != NULL)
+ {
+ /* Set the IRDA DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hirda->hdmatx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(hirda->hdmatx);
+ }
+ }
+
+ /* Disable the IRDA DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if(hirda->hdmarx != NULL)
+ {
+ /* Set the IRDA DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hirda->hdmarx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(hirda->hdmarx);
+ }
+ }
+
+ /* Reset Tx and Rx transfer counters */
+ hirda->TxXferCount = 0U;
+ hirda->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+ /* Restore hirda->gState and hirda->RxState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* Reset Handle ErrorCode to No Error */
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Transmit transfer (blocking mode).
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable IRDA Interrupts (Tx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable TXEIE and TCIE interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+ /* Disable the IRDA DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if(hirda->hdmatx != NULL)
+ {
+ /* Set the IRDA DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hirda->hdmatx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(hirda->hdmatx);
+ }
+ }
+
+ /* Reset Tx transfer counter */
+ hirda->TxXferCount = 0U;
+
+ /* Restore hirda->gState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Receive transfer (blocking mode).
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable IRDA Interrupts (Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the IRDA DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if(hirda->hdmarx != NULL)
+ {
+ /* Set the IRDA DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hirda->hdmarx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(hirda->hdmarx);
+ }
+ }
+
+ /* Reset Rx transfer counter */
+ hirda->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+ /* Restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing transfers (Interrupt mode).
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable IRDA Interrupts (Tx and Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda)
+{
+ uint32_t abortcplt = 1U;
+
+ /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised
+ before any call to DMA Abort functions */
+ /* DMA Tx Handle is valid */
+ if(hirda->hdmatx != NULL)
+ {
+ /* Set DMA Abort Complete callback if IRDA DMA Tx request if enabled.
+ Otherwise, set it to NULL */
+ if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ {
+ hirda->hdmatx->XferAbortCallback = IRDA_DMATxAbortCallback;
+ }
+ else
+ {
+ hirda->hdmatx->XferAbortCallback = NULL;
+ }
+ }
+ /* DMA Rx Handle is valid */
+ if(hirda->hdmarx != NULL)
+ {
+ /* Set DMA Abort Complete callback if IRDA DMA Rx request if enabled.
+ Otherwise, set it to NULL */
+ if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ {
+ hirda->hdmarx->XferAbortCallback = IRDA_DMARxAbortCallback;
+ }
+ else
+ {
+ hirda->hdmarx->XferAbortCallback = NULL;
+ }
+ }
+
+ /* Disable the IRDA DMA Tx request if enabled */
+ if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ {
+ /* Disable DMA Tx at UART level */
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
+ if(hirda->hdmatx != NULL)
+ {
+ /* IRDA Tx DMA Abort callback has already been initialised :
+ will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA TX */
+ if(HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
+ {
+ hirda->hdmatx->XferAbortCallback = NULL;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+
+ /* Disable the IRDA DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
+ if(hirda->hdmarx != NULL)
+ {
+ /* IRDA Rx DMA Abort callback has already been initialised :
+ will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA RX */
+ if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
+ {
+ hirda->hdmarx->XferAbortCallback = NULL;
+ abortcplt = 1U;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+
+ /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+ if (abortcplt == 1U)
+ {
+ /* Reset Tx and Rx transfer counters */
+ hirda->TxXferCount = 0U;
+ hirda->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+ /* Restore hirda->gState and hirda->RxState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_IRDA_AbortCpltCallback(hirda);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Transmit transfer (Interrupt mode).
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable IRDA Interrupts (Tx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable TXEIE and TCIE interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+ /* Disable the IRDA DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
+ if(hirda->hdmatx != NULL)
+ {
+ /* Set the IRDA DMA Abort callback :
+ will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
+ hirda->hdmatx->XferAbortCallback = IRDA_DMATxOnlyAbortCallback;
+
+ /* Abort DMA TX */
+ if(HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
+ {
+ /* Call Directly hirda->hdmatx->XferAbortCallback function in case of error */
+ hirda->hdmatx->XferAbortCallback(hirda->hdmatx);
+ }
+ }
+ else
+ {
+ /* Reset Tx transfer counter */
+ hirda->TxXferCount = 0U;
+
+ /* Restore hirda->gState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_IRDA_AbortTransmitCpltCallback(hirda);
+ }
+ }
+ else
+ {
+ /* Reset Tx transfer counter */
+ hirda->TxXferCount = 0U;
+
+ /* Restore hirda->gState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_IRDA_AbortTransmitCpltCallback(hirda);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Receive transfer (Interrupt mode).
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable IRDA Interrupts (Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the IRDA DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
+ if(hirda->hdmarx != NULL)
+ {
+ /* Set the IRDA DMA Abort callback :
+ will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
+ hirda->hdmarx->XferAbortCallback = IRDA_DMARxOnlyAbortCallback;
+
+ /* Abort DMA RX */
+ if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
+ {
+ /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
+ hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
+ }
+ }
+ else
+ {
+ /* Reset Rx transfer counter */
+ hirda->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+ /* Restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_IRDA_AbortReceiveCpltCallback(hirda);
+ }
+ }
+ else
+ {
+ /* Reset Rx transfer counter */
+ hirda->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+ /* Restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_IRDA_AbortReceiveCpltCallback(hirda);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle IRDA interrupt request.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
+{
+ uint32_t isrflags = READ_REG(hirda->Instance->ISR);
+ uint32_t cr1its = READ_REG(hirda->Instance->CR1);
+ uint32_t cr3its;
+ uint32_t errorflags;
+
+ /* If no error occurs */
+ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
+ if (errorflags == RESET)
+ {
+ /* IRDA in mode Receiver ---------------------------------------------------*/
+ if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ {
+ IRDA_Receive_IT(hirda);
+ return;
+ }
+ }
+
+ /* If some errors occur */
+ cr3its = READ_REG(hirda->Instance->CR3);
+ if( (errorflags != RESET)
+ && ( ((cr3its & USART_CR3_EIE) != RESET)
+ || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) )
+ {
+ /* IRDA parity error interrupt occurred -------------------------------------*/
+ if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
+ {
+ __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF);
+
+ hirda->ErrorCode |= HAL_IRDA_ERROR_PE;
+ }
+
+ /* IRDA frame error interrupt occurred --------------------------------------*/
+ if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ {
+ __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF);
+
+ hirda->ErrorCode |= HAL_IRDA_ERROR_FE;
+ }
+
+ /* IRDA noise error interrupt occurred --------------------------------------*/
+ if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ {
+ __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF);
+
+ hirda->ErrorCode |= HAL_IRDA_ERROR_NE;
+ }
+
+ /* IRDA Over-Run interrupt occurred -----------------------------------------*/
+ if(((isrflags & USART_ISR_ORE) != RESET) &&
+ (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
+ {
+ __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF);
+
+ hirda->ErrorCode |= HAL_IRDA_ERROR_ORE;
+ }
+
+ /* Call IRDA Error Call back function if need be --------------------------*/
+ if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
+ {
+ /* IRDA in mode Receiver ---------------------------------------------------*/
+ if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ {
+ IRDA_Receive_IT(hirda);
+ }
+
+ /* If Overrun error occurs, or if any error occurs in DMA mode reception,
+ consider error as blocking */
+ if (((hirda->ErrorCode & HAL_IRDA_ERROR_ORE) != RESET) ||
+ (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))
+ {
+ /* Blocking error : transfer is aborted
+ Set the IRDA state ready to be able to start again the process,
+ Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+ IRDA_EndRxTransfer(hirda);
+
+ /* Disable the IRDA DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the IRDA DMA Rx channel */
+ if(hirda->hdmarx != NULL)
+ {
+ /* Set the IRDA DMA Abort callback :
+ will lead to call HAL_IRDA_ErrorCallback() at end of DMA abort procedure */
+ hirda->hdmarx->XferAbortCallback = IRDA_DMAAbortOnError;
+
+ /* Abort DMA RX */
+ if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
+ {
+ /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
+ hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+ HAL_IRDA_ErrorCallback(hirda);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+ HAL_IRDA_ErrorCallback(hirda);
+ }
+ }
+ else
+ {
+ /* Non Blocking error : transfer could go on.
+ Error is notified to user through user error callback */
+ HAL_IRDA_ErrorCallback(hirda);
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ }
+ }
+ return;
+
+ } /* End if some error occurs */
+
+ /* IRDA in mode Transmitter ------------------------------------------------*/
+ if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
+ {
+ IRDA_Transmit_IT(hirda);
+ return;
+ }
+
+ /* IRDA in mode Transmitter (transmission end) -----------------------------*/
+ if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
+ {
+ IRDA_EndTransmit_IT(hirda);
+ return;
+ }
+
+}
+
+/**
+ * @brief Tx Transfer completed callback.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+__weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_TxCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Tx Half Transfer completed callback.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval None
+ */
+__weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callback.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+__weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_RxCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Rx Half Transfer complete callback.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+__weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief IRDA error callback.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+__weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_ErrorCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief IRDA Abort Complete callback.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+__weak void HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_AbortCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief IRDA Abort Complete callback.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+__weak void HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_AbortTransmitCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief IRDA Abort Receive Complete callback.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+__weak void HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_AbortReceiveCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Exported_Functions_Group3 Peripheral State and Error functions
+ * @brief IRDA State and Errors functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State and Error functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to return the State of IrDA
+ communication process and also return Peripheral Errors occurred during communication process
+ (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state
+ of the IRDA peripheral handle.
+ (+) HAL_IRDA_GetError() checks in run-time errors that could occur during
+ communication.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the IRDA handle state.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL state
+ */
+HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
+{
+ /* Return IRDA handle state */
+ uint32_t temp1= 0x00U, temp2 = 0x00U;
+ temp1 = hirda->gState;
+ temp2 = hirda->RxState;
+
+ return (HAL_IRDA_StateTypeDef)(temp1 | temp2);
+}
+
+/**
+ * @brief Return the IRDA handle error code.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval IRDA Error Code
+ */
+uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)
+{
+ return hirda->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Private_Functions IRDA Private Functions
+ * @{
+ */
+
+/**
+ * @brief Configure the IRDA peripheral.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
+{
+ uint32_t tmpreg = 0x00000000U;
+ IRDA_ClockSourceTypeDef clocksource = IRDA_CLOCKSOURCE_UNDEFINED;
+ HAL_StatusTypeDef ret = HAL_OK;
+
+ /* Check the communication parameters */
+ assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
+ assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength));
+ assert_param(IS_IRDA_PARITY(hirda->Init.Parity));
+ assert_param(IS_IRDA_TX_RX_MODE(hirda->Init.Mode));
+ assert_param(IS_IRDA_PRESCALER(hirda->Init.Prescaler));
+ assert_param(IS_IRDA_POWERMODE(hirda->Init.PowerMode));
+
+ /*-------------------------- USART CR1 Configuration -----------------------*/
+ /* Configure the IRDA Word Length, Parity and transfer Mode:
+ Set the M bits according to hirda->Init.WordLength value
+ Set PCE and PS bits according to hirda->Init.Parity value
+ Set TE and RE bits according to hirda->Init.Mode value */
+ tmpreg = (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode ;
+
+ MODIFY_REG(hirda->Instance->CR1, IRDA_CR1_FIELDS, tmpreg);
+
+ /*-------------------------- USART CR3 Configuration -----------------------*/
+ MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.PowerMode);
+
+ /*-------------------------- USART GTPR Configuration ----------------------*/
+ MODIFY_REG(hirda->Instance->GTPR, USART_GTPR_PSC, hirda->Init.Prescaler);
+
+ /*-------------------------- USART BRR Configuration -----------------------*/
+ IRDA_GETCLOCKSOURCE(hirda, clocksource);
+ switch (clocksource)
+ {
+ case IRDA_CLOCKSOURCE_PCLK1:
+ hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hirda->Init.BaudRate/2U)) / hirda->Init.BaudRate);
+ break;
+ case IRDA_CLOCKSOURCE_PCLK2:
+ hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hirda->Init.BaudRate/2U)) / hirda->Init.BaudRate);
+ break;
+ case IRDA_CLOCKSOURCE_HSI:
+ hirda->Instance->BRR = (uint16_t)((HSI_VALUE + (hirda->Init.BaudRate/2U)) / hirda->Init.BaudRate);
+ break;
+ case IRDA_CLOCKSOURCE_SYSCLK:
+ hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hirda->Init.BaudRate/2U)) / hirda->Init.BaudRate);
+ break;
+ case IRDA_CLOCKSOURCE_LSE:
+ hirda->Instance->BRR = (uint16_t)((LSE_VALUE + (hirda->Init.BaudRate/2U)) / hirda->Init.BaudRate);
+ break;
+ case IRDA_CLOCKSOURCE_UNDEFINED:
+ default:
+ ret = HAL_ERROR;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Check the IRDA Idle State.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda)
+{
+ uint32_t tickstart = 0U;
+
+ /* Initialize the IRDA ErrorCode */
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
+
+ /* TEACK bits in ISR is checked only when available.
+ Bit is defined and available only for UART instances supporting WakeUp from Stop Mode feature.
+ */
+ if (IS_UART_WAKEUP_FROMSTOP_INSTANCE(hirda->Instance))
+ {
+ /* Check if the Transmitter is enabled */
+ if((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+ {
+ /* Wait until TEACK flag is set */
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ /* Timeout occurred */
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Check if the Receiver is enabled */
+ if((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+ {
+ /* Wait until REACK flag is set */
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ /* Timeout Occured */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Initialize the IRDA state*/
+ hirda->gState = HAL_IRDA_STATE_READY;
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle IRDA Communication Timeout.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param Flag Specifies the IRDA flag to check.
+ * @param Status the new flag status (SET or RESET). The function is locked in a while loop as long as the flag remains set to Status.
+ * @param Tickstart Tick start value
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
+{
+ /* Wait until flag is set */
+ while((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ hirda->gState = HAL_IRDA_STATE_READY;
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+
+/**
+ * @brief End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable TXEIE and TCIE interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+ /* At end of Tx process, restore hirda->gState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+}
+
+
+/**
+ * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* At end of Rx process, restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+}
+
+
+/**
+ * @brief DMA IRDA transmit process complete callback.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
+
+ /* DMA Normal mode */
+ if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
+ {
+ hirda->TxXferCount = 0U;
+
+ /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+ in the IRDA CR3 register */
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+ /* Enable the IRDA Transmit Complete Interrupt */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
+ }
+ /* DMA Circular mode */
+ else
+ {
+ HAL_IRDA_TxCpltCallback(hirda);
+ }
+
+}
+
+/**
+ * @brief DMA IRDA transmit process half complete callback.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
+
+ HAL_IRDA_TxHalfCpltCallback(hirda);
+}
+
+/**
+ * @brief DMA IRDA receive process complete callback.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
+
+ /* DMA Normal mode */
+ if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
+ {
+ hirda->RxXferCount = 0U;
+
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+ in the IRDA CR3 register */
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ /* At end of Rx process, restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+ }
+
+ HAL_IRDA_RxCpltCallback(hirda);
+}
+
+/**
+ * @brief DMA IRDA receive process half complete callback.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
+
+ HAL_IRDA_RxHalfCpltCallback(hirda);
+}
+
+/**
+ * @brief DMA IRDA communication error callback.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
+
+ /* Stop IRDA DMA Tx request if ongoing */
+ if ( (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
+ &&(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) )
+ {
+ hirda->TxXferCount = 0U;
+ IRDA_EndTxTransfer(hirda);
+ }
+
+ /* Stop IRDA DMA Rx request if ongoing */
+ if ( (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
+ &&(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) )
+ {
+ hirda->RxXferCount = 0U;
+ IRDA_EndRxTransfer(hirda);
+ }
+
+ hirda->ErrorCode |= HAL_IRDA_ERROR_DMA;
+ HAL_IRDA_ErrorCallback(hirda);
+}
+
+/**
+ * @brief DMA IRDA communication abort callback, when initiated by HAL services on Error
+ * (To be called at end of DMA Abort procedure following error occurrence).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
+ hirda->RxXferCount = 0U;
+ hirda->TxXferCount = 0U;
+
+ HAL_IRDA_ErrorCallback(hirda);
+}
+
+/**
+ * @brief DMA IRDA Tx communication abort callback, when initiated by user
+ * (To be called at end of DMA Tx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Rx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef* )(hdma->Parent);
+
+ hirda->hdmatx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if(hirda->hdmarx != NULL)
+ {
+ if(hirda->hdmarx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ hirda->TxXferCount = 0U;
+ hirda->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+ /* Restore hirda->gState and hirda->RxState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_IRDA_AbortCpltCallback(hirda);
+}
+
+
+/**
+ * @brief DMA IRDA Rx communication abort callback, when initiated by user
+ * (To be called at end of DMA Rx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Tx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef* )(hdma->Parent);
+
+ hirda->hdmarx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if(hirda->hdmatx != NULL)
+ {
+ if(hirda->hdmatx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ hirda->TxXferCount = 0U;
+ hirda->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+ /* Restore hirda->gState and hirda->RxState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_IRDA_AbortCpltCallback(hirda);
+}
+
+
+/**
+ * @brief DMA IRDA Tx communication abort callback, when initiated by user by a call to
+ * HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer)
+ * (This callback is executed at end of DMA Tx Abort procedure following user abort request,
+ * and leads to user Tx Abort Complete callback execution).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
+
+ hirda->TxXferCount = 0U;
+
+ /* Restore hirda->gState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_IRDA_AbortTransmitCpltCallback(hirda);
+}
+
+/**
+ * @brief DMA IRDA Rx communication abort callback, when initiated by user by a call to
+ * HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer)
+ * (This callback is executed at end of DMA Rx Abort procedure following user abort request,
+ * and leads to user Rx Abort Complete callback execution).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ hirda->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+ /* Restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_IRDA_AbortReceiveCpltCallback(hirda);
+}
+
+/**
+ * @brief Send an amount of data in interrupt mode.
+ * @note Function is called under interruption only, once
+ * interruptions have been enabled by HAL_IRDA_Transmit_IT().
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
+{
+ uint16_t* tmp;
+
+ /* Check that a Tx process is ongoing */
+ if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
+ {
+ if(hirda->TxXferCount == 0U)
+ {
+ /* Disable the IRDA Transmit Data Register Empty Interrupt */
+ CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE);
+
+ /* Enable the IRDA Transmit Complete Interrupt */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+ {
+ tmp = (uint16_t*) hirda->pTxBuffPtr;
+ hirda->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
+ hirda->pTxBuffPtr += 2U;
+ }
+ else
+ {
+ hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0xFFU);
+ }
+ hirda->TxXferCount--;
+
+ return HAL_OK;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Wrap up transmission in non-blocking mode.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable the IRDA Transmit Complete Interrupt */
+ CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
+
+ /* Tx process is ended, restore hirda->gState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+
+ HAL_IRDA_TxCpltCallback(hirda);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Receive an amount of data in interrupt mode.
+ * @note Function is called under interruption only, once
+ * interruptions have been enabled by HAL_IRDA_Receive_IT()
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
+{
+ uint16_t* tmp;
+ uint16_t uhMask = hirda->Mask;
+ uint16_t uhdata;
+
+ /* Check that a Rx process is ongoing */
+ if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
+ {
+ uhdata = (uint16_t) READ_REG(hirda->Instance->RDR);
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+ {
+ tmp = (uint16_t*) hirda->pRxBuffPtr ;
+ *tmp = (uint16_t)(uhdata & uhMask);
+ hirda->pRxBuffPtr +=2U;
+ }
+ else
+ {
+ *hirda->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask);
+ }
+
+ if(--hirda->RxXferCount == 0U)
+ {
+ /* Disable the IRDA Parity Error Interrupt and RXNE interrupt */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+
+ /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* Rx process is completed, restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ HAL_IRDA_RxCpltCallback(hirda);
+
+ return HAL_OK;
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Clear RXNE interrupt flag */
+ __HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST);
+
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_IRDA_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_iwdg.c b/Src/stm32f3xx_hal_iwdg.c
new file mode 100644
index 0000000..479f4d9
--- /dev/null
+++ b/Src/stm32f3xx_hal_iwdg.c
@@ -0,0 +1,280 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_iwdg.c
+ * @author MCD Application Team
+ * @brief IWDG HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Independent Watchdog (IWDG) peripheral:
+ * + Initialization and Start functions
+ * + IO operation functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### IWDG Generic features #####
+ ==============================================================================
+ [..]
+ (+) The IWDG can be started by either software or hardware (configurable
+ through option byte).
+
+ (+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even
+ if the main clock fails.
+
+ (+) Once the IWDG is started, the LSI is forced ON and both can not be
+ disabled. The counter starts counting down from the reset value (0xFFFU).
+ When it reaches the end of count value (0x000U) a reset signal is
+ generated (IWDG reset).
+
+ (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
+ the IWDG_RLR value is reloaded in the counter and the watchdog reset is
+ prevented.
+
+ (+) The IWDG is implemented in the VDD voltage domain that is still functional
+ in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
+ IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
+ reset occurs.
+
+ (+) Debug mode : When the microcontroller enters debug mode (core halted),
+ the IWDG counter either continues to work normally or stops, depending
+ on DBG_IWDG_STOP configuration bit in DBG module, accessible through
+ __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros
+
+ [..] Min-max timeout value @41KHz (LSI): ~0.1ms / ~25.5s
+ The IWDG timeout may vary due to LSI frequency dispersion. STM32F3xx
+ devices provide the capability to measure the LSI frequency (LSI clock
+ connected internally to TIM16 CH1 input capture). The measured value
+ can be used to have an IWDG timeout with an acceptable accuracy.
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Use IWDG using HAL_IWDG_Init() function to :
+ (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
+ clock is forced ON and IWDG counter starts downcounting.
+ (++) Enable write access to configuration register: IWDG_PR, IWDG_RLR &
+ IWDG_WINR.
+ (++) Configure the IWDG prescaler and counter reload value. This reload
+ value will be loaded in the IWDG counter each time the watchdog is
+ reloaded, then the IWDG will start counting down from this value.
+ (++) wait for status flags to be reset"
+ (++) Depending on window parameter:
+ (+++) If Window Init parameter is same as Window register value,
+ nothing more is done but reload counter value in order to exit
+ function withy exact time base.
+ (+++) Else modify Window register. This will automatically reload
+ watchdog counter.
+
+ (#) Then the application program must refresh the IWDG counter at regular
+ intervals during normal operation to prevent an MCU reset, using
+ HAL_IWDG_Refresh() function.
+
+ *** IWDG HAL driver macros list ***
+ ====================================
+ [..]
+ Below the list of most used macros in IWDG HAL driver:
+ (+) __HAL_IWDG_START: Enable the IWDG peripheral
+ (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
+ the reload register
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+/** @addtogroup IWDG
+ * @brief IWDG HAL module driver.
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup IWDG_Private_Defines IWDG Private Defines
+ * @{
+ */
+/* Status register need 5 RC LSI divided by prescaler clock to be updated. With
+ higher prescaler (256U), and according to HSI variation, we need to wait at
+ least 6 cycles so 48 ms. */
+#define HAL_IWDG_DEFAULT_TIMEOUT 48u
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup IWDG_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup IWDG_Exported_Functions_Group1
+ * @brief Initialization and Start functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Start functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize the IWDG according to the specified parameters in the
+ IWDG_InitTypeDef of associated handle.
+ (+) Manage Window option.
+ (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
+ is reloaded in order to exit function with correct time base.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the IWDG according to the specified parameters in the
+ * IWDG_InitTypeDef and start watchdog. Before exiting function,
+ * watchdog is refreshed in order to have correct time base.
+ * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified IWDG module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
+{
+ uint32_t tickstart;
+
+ /* Check the IWDG handle allocation */
+ if(hiwdg == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
+ assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
+ assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
+ assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window));
+
+ /* Enable IWDG. LSI is turned on automaticaly */
+ __HAL_IWDG_START(hiwdg);
+
+ /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing
+ 0x5555 in KR */
+ IWDG_ENABLE_WRITE_ACCESS(hiwdg);
+
+ /* Write to IWDG registers the Prescaler & Reload values to work with */
+ hiwdg->Instance->PR = hiwdg->Init.Prescaler;
+ hiwdg->Instance->RLR = hiwdg->Init.Reload;
+
+ /* Check pending flag, if previous update not done, return timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait for register to be updated */
+ while(hiwdg->Instance->SR != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* If window parameter is different than current value, modify window
+ register */
+ if(hiwdg->Instance->WINR != hiwdg->Init.Window)
+ {
+ /* Write to IWDG WINR the IWDG_Window value to compare with. In any case,
+ even if window feature is disabled, Watchdog will be reloaded by writing
+ windows register */
+ hiwdg->Instance->WINR = hiwdg->Init.Window;
+ }
+ else
+ {
+ /* Reload IWDG counter with value defined in the reload register */
+ __HAL_IWDG_RELOAD_COUNTER(hiwdg);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup IWDG_Exported_Functions_Group2
+ * @brief IO operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Refresh the IWDG.
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Refresh the IWDG.
+ * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified IWDG module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
+{
+ /* Reload IWDG counter with value defined in the reload register */
+ __HAL_IWDG_RELOAD_COUNTER(hiwdg);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_IWDG_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_msp_template.c b/Src/stm32f3xx_hal_msp_template.c
new file mode 100644
index 0000000..2772b83
--- /dev/null
+++ b/Src/stm32f3xx_hal_msp_template.c
@@ -0,0 +1,117 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_msp_template.c
+ * @author MCD Application Team
+ * @brief HAL MSP module.
+ * This file template is located in the HAL folder and should be copied
+ * to the user folder.
+ *
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup HAL_MSP HAL MSP module
+ * @brief HAL MSP module.
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup HAL_MSP_Exported_Functions HAL MSP Exported Functions
+ * @{
+ */
+
+/**
+ * @brief Initializes the Global MSP.
+ * @retval None
+ */
+void HAL_MspInit(void)
+{
+
+}
+
+/**
+ * @brief DeInitializes the Global MSP.
+ * @retval None
+ */
+void HAL_MspDeInit(void)
+{
+
+}
+
+/**
+ * @brief Initializes the PPP MSP.
+ * @retval None
+ */
+void HAL_PPP_MspInit(void)
+{
+
+}
+
+/**
+ * @brief DeInitializes the PPP MSP.
+ * @retval None
+ */
+void HAL_PPP_MspDeInit(void)
+{
+
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_nand.c b/Src/stm32f3xx_hal_nand.c
new file mode 100644
index 0000000..23fb514
--- /dev/null
+++ b/Src/stm32f3xx_hal_nand.c
@@ -0,0 +1,1807 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_nand.c
+ * @author MCD Application Team
+ * @brief NAND HAL module driver.
+ * This file provides a generic firmware to drive NAND memories mounted
+ * as external device.
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ This driver is a generic layered driver which contains a set of APIs used to
+ control NAND flash memories. It uses the FMC layer functions to interface
+ with NAND devices. This driver is used as follows:
+
+ (+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
+ with control and timing parameters for both common and attribute spaces.
+
+ (+) Read NAND flash memory maker and device IDs using the function
+ HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
+ structure declared by the function caller.
+
+ (+) Access NAND flash memory by read/write operations using the functions
+ HAL_NAND_Read_Page_8b()/HAL_NAND_Read_SpareArea_8b(),
+ HAL_NAND_Write_Page_8b()/HAL_NAND_Write_SpareArea_8b(),
+ HAL_NAND_Read_Page_16b()/HAL_NAND_Read_SpareArea_16b(),
+ HAL_NAND_Write_Page_16b()/HAL_NAND_Write_SpareArea_16b()
+ to read/write page(s)/spare area(s). These functions use specific device
+ information (Block, page size..) predefined by the user in the HAL_NAND_Info_TypeDef
+ structure. The read/write address information is contained by the Nand_Address_Typedef
+ structure passed as parameter.
+
+ (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().
+
+ (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
+ The erase block address information is contained in the Nand_Address_Typedef
+ structure passed as parameter.
+
+ (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().
+
+ (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
+ HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
+ feature or the function HAL_NAND_GetECC() to get the ECC correction code.
+
+ (+) You can monitor the NAND device HAL state by calling the function
+ HAL_NAND_GetState()
+
+ [..]
+ (@) This driver is a set of generic APIs which handle standard NAND flash operations.
+ If a NAND flash device contains different operations and/or implementations,
+ it should be implemented separately.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+
+/** @defgroup NAND NAND
+ * @brief NAND HAL module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup NAND_Private_Constants NAND Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup NAND_Private_Macros NAND Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup NAND_Exported_Functions NAND Exported Functions
+ * @{
+ */
+
+/** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### NAND Initialization and de-initialization functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to initialize/de-initialize
+ the NAND memory
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Perform NAND memory Initialization sequence
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param ComSpace_Timing pointer to Common space timing structure
+ * @param AttSpace_Timing pointer to Attribute space timing structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
+{
+ /* Check the NAND handle state */
+ if(hnand == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ if(hnand->State == HAL_NAND_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hnand->Lock = HAL_UNLOCKED;
+ /* Initialize the low level hardware (MSP) */
+ HAL_NAND_MspInit(hnand);
+ }
+
+ /* Initialize NAND control Interface */
+ FMC_NAND_Init(hnand->Instance, &(hnand->Init));
+
+ /* Initialize NAND common space timing Interface */
+ FMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
+
+ /* Initialize NAND attribute space timing Interface */
+ FMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
+
+ /* Enable the NAND device */
+ __FMC_NAND_ENABLE(hnand->Instance, hnand->Init.NandBank);
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Perform NAND memory De-Initialization sequence
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
+{
+ /* Initialize the low level hardware (MSP) */
+ HAL_NAND_MspDeInit(hnand);
+
+ /* Configure the NAND registers with their reset values */
+ FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
+
+ /* Reset the NAND controller state */
+ hnand->State = HAL_NAND_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief NAND MSP Init
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @retval None
+ */
+__weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hnand);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_NAND_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief NAND MSP DeInit
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @retval None
+ */
+__weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hnand);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_NAND_MspDeInit could be implemented in the user file
+ */
+}
+
+
+/**
+ * @brief This function handles NAND device interrupt request.
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @retval HAL status
+*/
+void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
+{
+ /* Check NAND interrupt Rising edge flag */
+ if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE))
+ {
+ /* NAND interrupt callback*/
+ HAL_NAND_ITCallback(hnand);
+
+ /* Clear NAND interrupt Rising edge pending bit */
+ __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE);
+ }
+
+ /* Check NAND interrupt Level flag */
+ if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL))
+ {
+ /* NAND interrupt callback*/
+ HAL_NAND_ITCallback(hnand);
+
+ /* Clear NAND interrupt Level pending bit */
+ __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL);
+ }
+
+ /* Check NAND interrupt Falling edge flag */
+ if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE))
+ {
+ /* NAND interrupt callback*/
+ HAL_NAND_ITCallback(hnand);
+
+ /* Clear NAND interrupt Falling edge pending bit */
+ __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE);
+ }
+
+ /* Check NAND interrupt FIFO empty flag */
+ if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT))
+ {
+ /* NAND interrupt callback*/
+ HAL_NAND_ITCallback(hnand);
+
+ /* Clear NAND interrupt FIFO empty pending bit */
+ __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT);
+ }
+}
+
+/**
+ * @brief NAND interrupt feature callback
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @retval None
+ */
+__weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hnand);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_NAND_ITCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup NAND_Exported_Functions_Group2 Input and Output functions
+ * @brief Input Output and memory control functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### NAND Input and Output functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to use and control the NAND
+ memory
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Read the NAND memory electronic signature
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pNAND_ID NAND ID structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
+{
+ __IO uint32_t data = 0U;
+ __IO uint32_t data1 = 0U;
+ uint32_t deviceaddress = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Identify the device address */
+ if(hnand->Init.NandBank == FMC_NAND_BANK2)
+ {
+ deviceaddress = NAND_DEVICE1;
+ }
+ else
+ {
+ deviceaddress = NAND_DEVICE2;
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Send Read ID command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_READID;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+
+ /* Read the electronic signature from NAND flash */
+ if (hnand->Init.MemoryDataWidth == FMC_NAND_PCC_MEM_BUS_WIDTH_8)
+ {
+ data = *(__IO uint32_t *)deviceaddress;
+
+ /* Return the data read */
+ pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
+ pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data);
+ pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data);
+ pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data);
+ }
+ else
+ {
+ data = *(__IO uint32_t *)deviceaddress;
+ data1 = *((__IO uint32_t *)deviceaddress + 4U);
+
+ /* Return the data read */
+ pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
+ pNAND_ID->Device_Id = ADDR_3RD_CYCLE(data);
+ pNAND_ID->Third_Id = ADDR_1ST_CYCLE(data1);
+ pNAND_ID->Fourth_Id = ADDR_3RD_CYCLE(data1);
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief NAND memory reset
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
+{
+ uint32_t deviceaddress = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Identify the device address */
+ if(hnand->Init.NandBank == FMC_NAND_BANK2)
+ {
+ deviceaddress = NAND_DEVICE1;
+ }
+ else
+ {
+ deviceaddress = NAND_DEVICE2;
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Send NAND reset command */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF;
+
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_OK;
+
+}
+
+/**
+ * @brief Configure the device: Enter the physical parameters of the device
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pDeviceConfig pointer to NAND_DeviceConfigTypeDef structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig)
+{
+ hnand->Config.PageSize = pDeviceConfig->PageSize;
+ hnand->Config.SpareAreaSize = pDeviceConfig->SpareAreaSize;
+ hnand->Config.BlockSize = pDeviceConfig->BlockSize;
+ hnand->Config.BlockNbr = pDeviceConfig->BlockNbr;
+ hnand->Config.PlaneSize = pDeviceConfig->PlaneSize;
+ hnand->Config.PlaneNbr = pDeviceConfig->PlaneNbr;
+ hnand->Config.ExtraCommandEnable = pDeviceConfig->ExtraCommandEnable;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Read Page(s) from NAND memory block (8-bits addressing)
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress pointer to NAND address structure
+ * @param pBuffer pointer to destination read buffer
+ * @param NumPageToRead number of pages to read from block
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
+{
+ __IO uint32_t index = 0U;
+ uint32_t tickstart = 0U;
+ uint32_t deviceaddress = 0U, size = 0U, numPagesRead = 0U, nandaddress = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Identify the device address */
+ if(hnand->Init.NandBank == FMC_NAND_BANK2)
+ {
+ deviceaddress = NAND_DEVICE1;
+ }
+ else
+ {
+ deviceaddress = NAND_DEVICE2;
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* NAND raw address calculation */
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
+
+ /* Page(s) read loop */
+ while((NumPageToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ {
+ /* update the buffer size */
+ size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesRead);
+
+ /* Send read page command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+
+ /* Cards with page size <= 512 bytes */
+ if((hnand->Config.PageSize) <= 512U)
+ {
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+ else /* (hnand->Config.PageSize) > 512 */
+ {
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
+
+ /* Check if an extra command is needed for reading pages */
+ if(hnand->Config.ExtraCommandEnable == ENABLE)
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Read status until NAND is ready */
+ while(HAL_NAND_Read_Status(hnand) != NAND_READY)
+ {
+ if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Go back to read mode */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
+ __DSB();
+ }
+
+ /* Get Data into Buffer */
+ for(; index < size; index++)
+ {
+ *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
+ }
+
+ /* Increment read pages number */
+ numPagesRead++;
+
+ /* Decrement pages to read */
+ NumPageToRead--;
+
+ /* Increment the NAND address */
+ nandaddress = (uint32_t)(nandaddress + 1U);
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Read Page(s) from NAND memory block (16-bits addressing)
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress pointer to NAND address structure
+ * @param pBuffer pointer to destination read buffer. pBuffer should be 16bits aligned
+ * @param NumPageToRead number of pages to read from block
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead)
+{
+ __IO uint32_t index = 0U;
+ uint32_t tickstart = 0U;
+ uint32_t deviceaddress = 0U, size = 0U, numPagesRead = 0U, nandaddress = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Identify the device address */
+ if(hnand->Init.NandBank == FMC_NAND_BANK2)
+ {
+ deviceaddress = NAND_DEVICE1;
+ }
+ else
+ {
+ deviceaddress = NAND_DEVICE2;
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* NAND raw address calculation */
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
+
+ /* Page(s) read loop */
+ while((NumPageToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ {
+ /* update the buffer size */
+ size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesRead);
+
+ /* Send read page command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ __DSB();
+
+ /* Cards with page size <= 512 bytes */
+ if((hnand->Config.PageSize) <= 512U)
+ {
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+ else /* (hnand->Config.PageSize) > 512 */
+ {
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
+
+ if(hnand->Config.ExtraCommandEnable == ENABLE)
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Read status until NAND is ready */
+ while(HAL_NAND_Read_Status(hnand) != NAND_READY)
+ {
+ if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Go back to read mode */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
+ }
+
+ /* Get Data into Buffer */
+ for(; index < size; index++)
+ {
+ *(uint16_t *)pBuffer++ = *(uint16_t *)deviceaddress;
+ }
+
+ /* Increment read pages number */
+ numPagesRead++;
+
+ /* Decrement pages to read */
+ NumPageToRead--;
+
+ /* Increment the NAND address */
+ nandaddress = (uint32_t)(nandaddress + 1U);
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Write Page(s) to NAND memory block (8-bits addressing)
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress pointer to NAND address structure
+ * @param pBuffer pointer to source buffer to write
+ * @param NumPageToWrite : number of pages to write to block
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
+{
+ __IO uint32_t index = 0U;
+ uint32_t tickstart = 0U;
+ uint32_t deviceaddress = 0U, size = 0U, numPagesWritten = 0U, nandaddress = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Identify the device address */
+ if(hnand->Init.NandBank == FMC_NAND_BANK2)
+ {
+ deviceaddress = NAND_DEVICE1;
+ }
+ else
+ {
+ deviceaddress = NAND_DEVICE2;
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* NAND raw address calculation */
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
+
+ /* Page(s) write loop */
+ while((NumPageToWrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ {
+ /* update the buffer size */
+ size = hnand->Config.PageSize + ((hnand->Config.PageSize) * numPagesWritten);
+
+ /* Send write page command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
+
+ /* Cards with page size <= 512 bytes */
+ if((hnand->Config.PageSize) <= 512U)
+ {
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+ else /* (hnand->Config.PageSize) > 512 */
+ {
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ __DSB();
+ }
+ }
+
+
+ /* Write data to memory */
+ for(; index < size; index++)
+ {
+ *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
+ }
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
+
+ /* Read status until NAND is ready */
+ while(HAL_NAND_Read_Status(hnand) != NAND_READY)
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Increment written pages number */
+ numPagesWritten++;
+
+ /* Decrement pages to write */
+ NumPageToWrite--;
+
+ /* Increment the NAND address */
+ nandaddress = (uint32_t)(nandaddress + 1U);
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Write Page(s) to NAND memory block (16-bits addressing)
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress pointer to NAND address structure
+ * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned
+ * @param NumPageToWrite : number of pages to write to block
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite)
+{
+ __IO uint32_t index = 0U;
+ uint32_t tickstart = 0U;
+ uint32_t deviceaddress = 0U, size = 0U, numPagesWritten = 0U, nandaddress = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Identify the device address */
+ if(hnand->Init.NandBank == FMC_NAND_BANK2)
+ {
+ deviceaddress = NAND_DEVICE1;
+ }
+ else
+ {
+ deviceaddress = NAND_DEVICE2;
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* NAND raw address calculation */
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
+
+ /* Page(s) write loop */
+ while((NumPageToWrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ {
+ /* update the buffer size */
+ size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesWritten);
+
+ /* Send write page command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
+ __DSB();
+
+ /* Cards with page size <= 512 bytes */
+ if((hnand->Config.PageSize) <= 512U)
+ {
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+ else /* (hnand->Config.PageSize) > 512 */
+ {
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+
+ /* Write data to memory */
+ for(; index < size; index++)
+ {
+ *(__IO uint16_t *)deviceaddress = *(uint16_t *)pBuffer++;
+ }
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
+
+ /* Read status until NAND is ready */
+ while(HAL_NAND_Read_Status(hnand) != NAND_READY)
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Increment written pages number */
+ numPagesWritten++;
+
+ /* Decrement pages to write */
+ NumPageToWrite--;
+
+ /* Increment the NAND address */
+ nandaddress = (uint32_t)(nandaddress + 1U);
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Read Spare area(s) from NAND memory
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress pointer to NAND address structure
+ * @param pBuffer pointer to source buffer to write
+ * @param NumSpareAreaToRead Number of spare area to read
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
+{
+ __IO uint32_t index = 0U;
+ uint32_t tickstart = 0U;
+ uint32_t deviceaddress = 0U, size = 0U, numSpareAreaRead = 0U, nandaddress = 0U, columnaddress = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Identify the device address */
+ if(hnand->Init.NandBank == FMC_NAND_BANK2)
+ {
+ deviceaddress = NAND_DEVICE1;
+ }
+ else
+ {
+ deviceaddress = NAND_DEVICE2;
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* NAND raw address calculation */
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
+
+ /* Column in page address */
+ columnaddress = COLUMN_ADDRESS(hnand);
+
+ /* Spare area(s) read loop */
+ while((NumSpareAreaToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ {
+ /* update the buffer size */
+ size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaRead);
+
+ /* Cards with page size <= 512 bytes */
+ if((hnand->Config.PageSize) <= 512U)
+ {
+ /* Send read spare area command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
+
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+ else /* (hnand->Config.PageSize) > 512 */
+ {
+ /* Send read spare area command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
+
+ if(hnand->Config.ExtraCommandEnable == ENABLE)
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Read status until NAND is ready */
+ while(HAL_NAND_Read_Status(hnand) != NAND_READY)
+ {
+ if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Go back to read mode */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
+ }
+
+ /* Get Data into Buffer */
+ for(; index < size; index++)
+ {
+ *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
+ }
+
+ /* Increment read spare areas number */
+ numSpareAreaRead++;
+
+ /* Decrement spare areas to read */
+ NumSpareAreaToRead--;
+
+ /* Increment the NAND address */
+ nandaddress = (uint32_t)(nandaddress + 1U);
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Read Spare area(s) from NAND memory (16-bits addressing)
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress pointer to NAND address structure
+ * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned.
+ * @param NumSpareAreaToRead Number of spare area to read
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
+{
+ __IO uint32_t index = 0U;
+ uint32_t tickstart = 0U;
+ uint32_t deviceaddress = 0U, size = 0U, numSpareAreaRead = 0U, nandaddress = 0U, columnaddress = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Identify the device address */
+ if(hnand->Init.NandBank == FMC_NAND_BANK2)
+ {
+ deviceaddress = NAND_DEVICE1;
+ }
+ else
+ {
+ deviceaddress = NAND_DEVICE2;
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* NAND raw address calculation */
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
+
+ /* Column in page address */
+ columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U);
+
+ /* Spare area(s) read loop */
+ while((NumSpareAreaToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ {
+ /* update the buffer size */
+ size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaRead);
+
+ /* Cards with page size <= 512 bytes */
+ if((hnand->Config.PageSize) <= 512U)
+ {
+ /* Send read spare area command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
+
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+ else /* (hnand->Config.PageSize) > 512 */
+ {
+ /* Send read spare area command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
+
+ if(hnand->Config.ExtraCommandEnable == ENABLE)
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Read status until NAND is ready */
+ while(HAL_NAND_Read_Status(hnand) != NAND_READY)
+ {
+ if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Go back to read mode */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
+ }
+
+ /* Get Data into Buffer */
+ for(; index < size; index++)
+ {
+ *(uint16_t *)pBuffer++ = *(uint16_t *)deviceaddress;
+ }
+
+ /* Increment read spare areas number */
+ numSpareAreaRead++;
+
+ /* Decrement spare areas to read */
+ NumSpareAreaToRead--;
+
+ /* Increment the NAND address */
+ nandaddress = (uint32_t)(nandaddress + 1U);
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Write Spare area(s) to NAND memory
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress pointer to NAND address structure
+ * @param pBuffer pointer to source buffer to write
+ * @param NumSpareAreaTowrite : number of spare areas to write to block
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
+{
+ __IO uint32_t index = 0U;
+ uint32_t tickstart = 0U;
+ uint32_t deviceaddress = 0U, size = 0U, numSpareAreaWritten = 0U, nandaddress = 0U, columnaddress = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Identify the device address */
+ if(hnand->Init.NandBank == FMC_NAND_BANK2)
+ {
+ deviceaddress = NAND_DEVICE1;
+ }
+ else
+ {
+ deviceaddress = NAND_DEVICE2;
+ }
+
+ /* Update the FMC_NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Page address calculation */
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
+
+ /* Column in page address */
+ columnaddress = COLUMN_ADDRESS(hnand);
+
+ /* Spare area(s) write loop */
+ while((NumSpareAreaTowrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ {
+ /* update the buffer size */
+ size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaWritten);
+
+ /* Cards with page size <= 512 bytes */
+ if((hnand->Config.PageSize) <= 512U)
+ {
+ /* Send write Spare area command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
+
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+ else /* (hnand->Config.PageSize) > 512 */
+ {
+ /* Send write Spare area command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
+
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+
+ /* Write data to memory */
+ for(; index < size; index++)
+ {
+ *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
+ }
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Read status until NAND is ready */
+ while(HAL_NAND_Read_Status(hnand) != NAND_READY)
+ {
+ if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Increment written spare areas number */
+ numSpareAreaWritten++;
+
+ /* Decrement spare areas to write */
+ NumSpareAreaTowrite--;
+
+ /* Increment the NAND address */
+ nandaddress = (uint32_t)(nandaddress + 1U);
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Write Spare area(s) to NAND memory (16-bits addressing)
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress pointer to NAND address structure
+ * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned.
+ * @param NumSpareAreaTowrite : number of spare areas to write to block
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
+{
+ __IO uint32_t index = 0U;
+ uint32_t tickstart = 0U;
+ uint32_t deviceaddress = 0U, size = 0U, numSpareAreaWritten = 0U, nandaddress = 0U, columnaddress = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Identify the device address */
+ if(hnand->Init.NandBank == FMC_NAND_BANK2)
+ {
+ deviceaddress = NAND_DEVICE1;
+ }
+ else
+ {
+ deviceaddress = NAND_DEVICE2;
+ }
+
+ /* Update the FMC_NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* NAND raw address calculation */
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
+
+ /* Column in page address */
+ columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U);
+
+ /* Spare area(s) write loop */
+ while((NumSpareAreaTowrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ {
+ /* update the buffer size */
+ size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaWritten);
+
+ /* Cards with page size <= 512 bytes */
+ if((hnand->Config.PageSize) <= 512U)
+ {
+ /* Send write Spare area command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
+
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+ else /* (hnand->Config.PageSize) > 512 */
+ {
+ /* Send write Spare area command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
+
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+
+ /* Write data to memory */
+ for(; index < size; index++)
+ {
+ *(__IO uint16_t *)deviceaddress = *(uint16_t *)pBuffer++;
+ }
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
+
+ /* Read status until NAND is ready */
+ while(HAL_NAND_Read_Status(hnand) != NAND_READY)
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Increment written spare areas number */
+ numSpareAreaWritten++;
+
+ /* Decrement spare areas to write */
+ NumSpareAreaTowrite--;
+
+ /* Increment the NAND address */
+ nandaddress = (uint32_t)(nandaddress + 1U);
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief NAND memory Block erase
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress pointer to NAND address structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
+{
+ uint32_t deviceaddress = 0U;
+ uint32_t tickstart = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Identify the device address */
+ if(hnand->Init.NandBank == FMC_NAND_BANK2)
+ {
+ deviceaddress = NAND_DEVICE1;
+ }
+ else
+ {
+ deviceaddress = NAND_DEVICE2;
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Send Erase block command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0;
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1;
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Read status until NAND is ready */
+ while(HAL_NAND_Read_Status(hnand) != NAND_READY)
+ {
+ if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief NAND memory read status
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @retval NAND status
+ */
+uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
+{
+ uint32_t data = 0U;
+ uint32_t deviceaddress = 0U;
+
+ /* Identify the device address */
+ if(hnand->Init.NandBank == FMC_NAND_BANK2)
+ {
+ deviceaddress = NAND_DEVICE1;
+ }
+ else
+ {
+ deviceaddress = NAND_DEVICE2;
+ }
+
+ /* Send Read status operation command */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS;
+
+ /* Read status register data */
+ data = *(__IO uint8_t *)deviceaddress;
+
+ /* Return the status */
+ if((data & NAND_ERROR) == NAND_ERROR)
+ {
+ return NAND_ERROR;
+ }
+ else if((data & NAND_READY) == NAND_READY)
+ {
+ return NAND_READY;
+ }
+
+ return NAND_BUSY;
+}
+
+/**
+ * @brief Increment the NAND memory address
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress pointer to NAND address structure
+ * @retval The new status of the increment address operation. It can be:
+ * - NAND_VALID_ADDRESS: When the new address is valid address
+ * - NAND_INVALID_ADDRESS: When the new address is invalid address
+ */
+uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
+{
+ uint32_t status = NAND_VALID_ADDRESS;
+
+ /* Increment page address */
+ pAddress->Page++;
+
+ /* Check NAND address is valid */
+ if(pAddress->Page == hnand->Config.BlockSize)
+ {
+ pAddress->Page = 0U;
+ pAddress->Block++;
+
+ if(pAddress->Block == hnand->Config.PlaneSize)
+ {
+ pAddress->Block = 0U;
+ pAddress->Plane++;
+
+ if(pAddress->Plane == (hnand->Config.PlaneNbr))
+ {
+ status = NAND_INVALID_ADDRESS;
+ }
+ }
+ }
+
+ return (status);
+}
+/**
+ * @}
+ */
+
+/** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions
+ * @brief management functions
+ *
+@verbatim
+ ==============================================================================
+ ##### NAND Control functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control dynamically
+ the NAND interface.
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Enables dynamically NAND ECC feature.
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
+{
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Update the NAND state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Enable ECC feature */
+ FMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
+
+ /* Update the NAND state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables dynamically FMC_NAND ECC feature.
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
+{
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Update the NAND state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Disable ECC feature */
+ FMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
+
+ /* Update the NAND state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables dynamically NAND ECC feature.
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param ECCval pointer to ECC value
+ * @param Timeout maximum timeout to wait
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Update the NAND state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Get NAND ECC value */
+ status = FMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
+
+ /* Update the NAND state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ return status;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### NAND State functions #####
+ ==============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the NAND controller
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief return the NAND state
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @retval HAL state
+ */
+HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
+{
+ return hnand->State;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_nor.c b/Src/stm32f3xx_hal_nor.c
new file mode 100644
index 0000000..25bf412
--- /dev/null
+++ b/Src/stm32f3xx_hal_nor.c
@@ -0,0 +1,1057 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_nor.c
+ * @author MCD Application Team
+ * @brief NOR HAL module driver.
+ * This file provides a generic firmware to drive NOR memories mounted
+ * as external device.
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ This driver is a generic layered driver which contains a set of APIs used to
+ control NOR flash memories. It uses the FMC layer functions to interface
+ with NOR devices. This driver is used as follows:
+
+ (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
+ with control and timing parameters for both normal and extended mode.
+
+ (+) Read NOR flash memory manufacturer code and device IDs using the function
+ HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
+ structure declared by the function caller.
+
+ (+) Access NOR flash memory by read/write data unit operations using the functions
+ HAL_NOR_Read(), HAL_NOR_Program().
+
+ (+) Perform NOR flash erase block/chip operations using the functions
+ HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
+
+ (+) Read the NOR flash CFI (common flash interface) IDs using the function
+ HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
+ structure declared by the function caller.
+
+ (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
+ HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
+
+ (+) You can monitor the NOR device HAL state by calling the function
+ HAL_NOR_GetState()
+ [..]
+ (@) This driver is a set of generic APIs which handle standard NOR flash operations.
+ If a NOR flash device contains different operations and/or implementations,
+ it should be implemented separately.
+
+ *** NOR HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in NOR HAL driver.
+
+ (+) NOR_WRITE: NOR memory write data to specified address
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+/** @defgroup NOR NOR
+ * @brief NOR HAL module driver
+ * @{
+ */
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup NOR_Private_Constants NOR Private Constants
+ * @{
+ */
+
+/* Constants to define address to set to write a command */
+#define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
+#define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
+#define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
+#define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555
+#define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555
+#define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA
+#define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555
+
+/* Constants to define data to program a command */
+#define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0
+#define NOR_CMD_DATA_FIRST (uint16_t)0x00AA
+#define NOR_CMD_DATA_SECOND (uint16_t)0x0055
+#define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090
+#define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0
+#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080
+#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA
+#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055
+#define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010
+#define NOR_CMD_DATA_CFI (uint16_t)0x0098
+
+#define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25
+#define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
+#define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
+
+/* Mask on NOR STATUS REGISTER */
+#define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
+#define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup NOR_Private_Macros NOR Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+
+/** @defgroup NOR_Private_Variables NOR Private Variables
+ * @{
+ */
+
+static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B;
+
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup NOR_Exported_Functions NOR Exported Functions
+ * @{
+ */
+
+/** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### NOR Initialization and de_initialization functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to initialize/de-initialize
+ the NOR memory
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Perform the NOR memory Initialization sequence
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param Timing pointer to NOR control timing structure
+ * @param ExtTiming pointer to NOR extended mode timing structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
+{
+ /* Check the NOR handle parameter */
+ if(hnor == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ if(hnor->State == HAL_NOR_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hnor->Lock = HAL_UNLOCKED;
+
+ /* Initialize the low level hardware (MSP) */
+ HAL_NOR_MspInit(hnor);
+ }
+
+ /* Initialize NOR control Interface */
+ FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
+
+ /* Initialize NOR timing Interface */
+ FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
+
+ /* Initialize NOR extended mode timing Interface */
+ FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
+
+ /* Enable the NORSRAM device */
+ __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
+
+ /* Initialize NOR Memory Data Width*/
+ if (hnor->Init.MemoryDataWidth == FMC_NORSRAM_MEM_BUS_WIDTH_8)
+ {
+ uwNORMemoryDataWidth = NOR_MEMORY_8B;
+ }
+ else
+ {
+ uwNORMemoryDataWidth = NOR_MEMORY_16B;
+ }
+
+ /* Check the NOR controller state */
+ hnor->State = HAL_NOR_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Perform NOR memory De-Initialization sequence
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
+{
+ /* De-Initialize the low level hardware (MSP) */
+ HAL_NOR_MspDeInit(hnor);
+
+ /* Configure the NOR registers with their reset values */
+ FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hnor);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief NOR MSP Init
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @retval None
+ */
+__weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hnor);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_NOR_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief NOR MSP DeInit
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @retval None
+ */
+__weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hnor);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_NOR_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief NOR MSP Wait fro Ready/Busy signal
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param Timeout Maximum timeout value
+ * @retval None
+ */
+__weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hnor);
+ UNUSED(Timeout);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_NOR_MspWait could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
+ * @brief Input Output and memory control functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### NOR Input and Output functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to use and control the NOR memory
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Read NOR flash IDs
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param pNOR_ID pointer to NOR ID structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
+{
+ uint32_t deviceaddress = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Check the NOR controller state */
+ if(hnor->State == HAL_NOR_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_BUSY;
+
+ /* Send read ID command */
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
+
+ /* Read the NOR IDs */
+ pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
+ pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR);
+ pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR);
+ pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR);
+
+ /* Check the NOR controller state */
+ hnor->State = HAL_NOR_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Returns the NOR memory to Read mode.
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
+{
+ uint32_t deviceaddress = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Check the NOR controller state */
+ if(hnor->State == HAL_NOR_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
+
+ NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
+
+ /* Check the NOR controller state */
+ hnor->State = HAL_NOR_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Read data from NOR memory
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param pAddress pointer to Device address
+ * @param pData pointer to read data
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
+{
+ uint32_t deviceaddress = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Check the NOR controller state */
+ if(hnor->State == HAL_NOR_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_BUSY;
+
+ /* Send read data command */
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE((uint32_t)pAddress, NOR_CMD_DATA_READ_RESET);
+
+ /* Read the data */
+ *pData = *(__IO uint32_t *)(uint32_t)pAddress;
+
+ /* Check the NOR controller state */
+ hnor->State = HAL_NOR_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Program data to NOR memory
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param pAddress Device address
+ * @param pData pointer to the data to write
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
+{
+ uint32_t deviceaddress = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Check the NOR controller state */
+ if(hnor->State == HAL_NOR_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_BUSY;
+
+ /* Send program data command */
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
+
+ /* Write the data */
+ NOR_WRITE(pAddress, *pData);
+
+ /* Check the NOR controller state */
+ hnor->State = HAL_NOR_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Reads a block of data from the FMC NOR memory.
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param uwAddress NOR memory internal address to read from.
+ * @param pData pointer to the buffer that receives the data read from the
+ * NOR memory.
+ * @param uwBufferSize number of Half word to read.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
+{
+ uint32_t deviceaddress = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Check the NOR controller state */
+ if(hnor->State == HAL_NOR_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_BUSY;
+
+ /* Send read data command */
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(uwAddress, NOR_CMD_DATA_READ_RESET);
+
+ /* Read buffer */
+ while( uwBufferSize > 0U)
+ {
+ *pData++ = *(__IO uint16_t *)uwAddress;
+ uwAddress += 2U;
+ uwBufferSize--;
+ }
+
+ /* Check the NOR controller state */
+ hnor->State = HAL_NOR_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Writes a half-word buffer to the FMC NOR memory. This function
+ * must be used only with S29GL128P NOR memory.
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param uwAddress NOR memory internal address from which the data
+ * @note Some NOR memory need Address aligned to xx bytes (can be aligned to
+ * 64 bytes boundary for example).
+ * @param pData pointer to source data buffer.
+ * @param uwBufferSize number of Half words to write.
+ * @note The maximum buffer size allowed is NOR memory dependent
+ * (can be 64 Bytes max for example).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
+{
+ uint16_t * p_currentaddress = (uint16_t *)NULL;
+ uint16_t * p_endaddress = (uint16_t *)NULL;
+ uint32_t lastloadedaddress = 0U, deviceaddress = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Check the NOR controller state */
+ if(hnor->State == HAL_NOR_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_BUSY;
+
+ /* Initialize variables */
+ p_currentaddress = (uint16_t*)((uint32_t)(uwAddress));
+ p_endaddress = p_currentaddress + (uwBufferSize-1U);
+ lastloadedaddress = (uint32_t)(uwAddress);
+
+ /* Issue unlock command sequence */
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+
+ /* Write Buffer Load Command */
+ NOR_WRITE((uint32_t)(p_currentaddress), NOR_CMD_DATA_BUFFER_AND_PROG);
+ NOR_WRITE((uint32_t)(p_currentaddress), (uwBufferSize-1U));
+
+ /* Load Data into NOR Buffer */
+ while(p_currentaddress <= p_endaddress)
+ {
+ /* Store last loaded address & data value (for polling) */
+ lastloadedaddress = (uint32_t)p_currentaddress;
+
+ NOR_WRITE(p_currentaddress, *pData++);
+
+ p_currentaddress++;
+ }
+
+ NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
+
+ /* Check the NOR controller state */
+ hnor->State = HAL_NOR_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+
+ return HAL_OK;
+
+}
+
+/**
+ * @brief Erase the specified block of the NOR memory
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param BlockAddress Block to erase address
+ * @param Address Device address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
+{
+ uint32_t deviceaddress = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Check the NOR controller state */
+ if(hnor->State == HAL_NOR_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_BUSY;
+
+ /* Send block erase command sequence */
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
+ NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
+
+ /* Check the NOR memory status and update the controller state */
+ hnor->State = HAL_NOR_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+
+ return HAL_OK;
+
+}
+
+/**
+ * @brief Erase the entire NOR chip.
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param Address Device address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
+{
+ uint32_t deviceaddress = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Check the NOR controller state */
+ if(hnor->State == HAL_NOR_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_BUSY;
+
+ /* Send NOR chip erase command sequence */
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
+
+ /* Check the NOR memory status and update the controller state */
+ hnor->State = HAL_NOR_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Read NOR flash CFI IDs
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param pNOR_CFI pointer to NOR CFI IDs structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
+{
+ uint32_t deviceaddress = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Check the NOR controller state */
+ if(hnor->State == HAL_NOR_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_BUSY;
+
+ /* Send read CFI query command */
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
+
+ /* read the NOR CFI information */
+ pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
+ pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
+ pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS);
+ pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS);
+
+ /* Check the NOR controller state */
+ hnor->State = HAL_NOR_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup NOR_Exported_Functions_Group3 Peripheral Control functions
+ * @brief management functions
+ *
+@verbatim
+ ==============================================================================
+ ##### NOR Control functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control dynamically
+ the NOR interface.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables dynamically NOR write operation.
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
+{
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Enable write operation */
+ FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables dynamically NOR write operation.
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
+{
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Update the SRAM controller state */
+ hnor->State = HAL_NOR_STATE_BUSY;
+
+ /* Disable write operation */
+ FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_PROTECTED;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup NOR_Exported_Functions_Group4 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### NOR State functions #####
+ ==============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the NOR controller
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief return the NOR controller state
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @retval NOR controller state
+ */
+HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
+{
+ return hnor->State;
+}
+
+/**
+ * @brief Returns the NOR operation status.
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param Address Device address
+ * @param Timeout NOR progamming Timeout
+ * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
+ * or HAL_NOR_STATUS_TIMEOUT
+ */
+HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
+{
+ HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
+ uint16_t tmp_sr1 = 0U, tmp_sr2 = 0U;
+ uint32_t tickstart = 0U;
+
+ /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
+ HAL_NOR_MspWait(hnor, Timeout);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+ while((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ status = HAL_NOR_STATUS_TIMEOUT;
+ }
+ }
+
+ /* Read NOR status register (DQ6 and DQ5) */
+ tmp_sr1 = *(__IO uint16_t *)Address;
+ tmp_sr2 = *(__IO uint16_t *)Address;
+
+ /* If DQ6 did not toggle between the two reads then return NOR_Success */
+ if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6))
+ {
+ return HAL_NOR_STATUS_SUCCESS;
+ }
+
+ if((tmp_sr1 & NOR_MASK_STATUS_DQ5) != NOR_MASK_STATUS_DQ5)
+ {
+ status = HAL_NOR_STATUS_ONGOING;
+ }
+
+ tmp_sr1 = *(__IO uint16_t *)Address;
+ tmp_sr2 = *(__IO uint16_t *)Address;
+
+ /* If DQ6 did not toggle between the two reads then return NOR_Success */
+ if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6))
+ {
+ return HAL_NOR_STATUS_SUCCESS;
+ }
+ else if((tmp_sr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
+ {
+ return HAL_NOR_STATUS_ERROR;
+ }
+ }
+
+ /* Return the operation status */
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_opamp.c b/Src/stm32f3xx_hal_opamp.c
new file mode 100644
index 0000000..3a69f7f
--- /dev/null
+++ b/Src/stm32f3xx_hal_opamp.c
@@ -0,0 +1,922 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_opamp.c
+ * @author MCD Application Team
+ * @brief OPAMP HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the operational amplifiers (OPAMP1,...OPAMP4)
+ * peripheral:
+ * + OPAMP Configuration
+ * + OPAMP calibration
+ * Thanks to
+ * + Initialization/de-initialization functions
+ * + I/O operation functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ @verbatim
+================================================================================
+ ##### OPAMP Peripheral Features #####
+================================================================================
+
+ [..] The device integrates up to 4 operational amplifiers OPAMP1, OPAMP2,
+ OPAMP3 and OPAMP4:
+
+ (#) The OPAMP(s) provides several exclusive running modes.
+ (++) Standalone mode
+ (++) Programmable Gain Amplifier (PGA) mode (Resistor feedback output)
+ (++) Follower mode
+
+ (#) The OPAMP(s) provide(s) calibration capabilities.
+ (++) Calibration aims at correcting some offset for running mode.
+ (++) The OPAMP uses either factory calibration settings OR user defined
+ calibration (trimming) settings (i.e. trimming mode).
+ (++) The user defined settings can be figured out using self calibration
+ handled by HAL_OPAMP_SelfCalibrate, HAL_OPAMPEx_SelfCalibrateAll
+ (++) HAL_OPAMP_SelfCalibrate:
+ (++) Runs automatically the calibration in 2 steps.
+ (90U% of VDDA for NMOS transistors, 10U% of VDDA for PMOS transistors).
+ (As OPAMP is Rail-to-rail input/output, these 2 steps calibration is
+ appropriate and enough in most cases).
+ (++) Enables the user trimming mode
+ (++) Updates the init structure with trimming values with fresh calibration
+ results.
+ The user may store the calibration results for larger
+ (ex monitoring the trimming as a function of temperature
+ for instance)
+ (++) for STM32F3 devices having 2 or 4 OPAMPs
+ HAL_OPAMPEx_SelfCalibrateAll
+ runs calibration of 2 or 4 OPAMPs in parallel.
+
+ (#) For any running mode, an additional Timer-controlled Mux (multiplexer)
+ mode can be set on top.
+ (++) Timer-controlled Mux mode allows Automatic switching between inverting
+ and non-inverting input.
+ (++) Hence on top of defaults (primary) inverting and non-inverting inputs,
+ the user shall select secondary inverting and non inverting inputs.
+ (++) TIM1 CC6 provides the alternate switching tempo between defaults
+ (primary) and secondary inputs.
+
+ (#) Running mode: Standalone mode
+ (++) Gain is set externally (gain depends on external loads).
+ (++) Follower mode also possible externally by connecting the inverting input to
+ the output.
+
+ (#) Running mode: Follower mode
+ (++) No Inverting Input is connected.
+
+ (#) Running mode: Programmable Gain Amplifier (PGA) mode
+ (Resistor feedback output)
+ (++) The OPAMP(s) output(s) can be internally connected to resistor feedback
+ output.
+ (++) OPAMP gain is either 2U, 4U, 8 or 16.
+
+
+ ##### How to use this driver #####
+================================================================================
+ [..]
+ *** Calibration ***
+ ============================================
+ [..]
+ To run the opamp calibration self calibration:
+
+ (#) Start calibration using HAL_OPAMP_SelfCalibrate.
+ Store the calibration results.
+
+ *** Running mode ***
+ ============================================
+ [..]
+ To use the opamp, perform the following steps:
+
+ (#) Fill in the HAL_OPAMP_MspInit() to
+ (++) Configure the opamp input AND output in analog mode using
+ HAL_GPIO_Init() to map the opamp output to the GPIO pin.
+
+ (#) Configure the opamp using HAL_OPAMP_Init() function:
+ (++) Select the mode
+ (++) Select the inverting input
+ (++) Select the non-inverting input
+ (++) Select if the Timer controlled Mux mode is enabled/disabled
+ (++) If the Timer controlled Mux mode is enabled, select the secondary inverting input
+ (++) If the Timer controlled Mux mode is enabled, Select the secondary non-inverting input
+ (++) If PGA mode is enabled, Select if inverting input is connected.
+ (++) Select either factory or user defined trimming mode.
+ (++) If the user defined trimming mode is enabled, select PMOS & NMOS trimming values
+ (typ. settings returned by HAL_OPAMP_SelfCalibrate function).
+
+ (#) Enable the opamp using HAL_OPAMP_Start() function.
+
+ (#) Disable the opamp using HAL_OPAMP_Stop() function.
+
+ (#) Lock the opamp in running mode using HAL_OPAMP_Lock() function. From then The configuration
+ can be modified
+ (++) After HW reset
+ (++) OR thanks to HAL_OPAMP_MspDeInit called (user defined) from HAL_OPAMP_DeInit.
+
+ *** Running mode: change of configuration while OPAMP ON ***
+ ============================================
+ [..]
+ To Re-configure OPAMP when OPAMP is ON (change on the fly)
+ (#) If needed, Fill in the HAL_OPAMP_MspInit()
+ (++) This is the case for instance if you wish to use new OPAMP I/O
+
+ (#) Configure the opamp using HAL_OPAMP_Init() function:
+ (++) As in configure case, selects first the parameters you wish to modify.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*
+ Additional Tables:
+ The OPAMPs non inverting input (both default and secondary) can be
+ selected among the list shown by table below.
+
+ The OPAMPs non inverting input (both default and secondary) can be
+ selected among the list shown by table below.
+
+ Table 1. OPAMPs inverting/non-inverting inputs for the STM32F3 devices:
+ +--------------------------------------------------------------+
+ | | | OPAMP1 | OPAMP2 | OPAMP3 | OPAMP4 |
+ |-----------------|--------|--------|--------|--------|--------|
+ | | No conn| X | X | X | X |
+ | Inverting Input | VM0 | PC5 | PC5 | PB10 | PB10 |
+ | (1) | VM1 | PA3 | PA5 | PB2 | PD8 |
+ |-----------------|--------|--------|--------|--------|--------|
+ | | VP0 | PA1 | PA7 | PB0 | PB13 |
+ | Non Inverting | VP1 | PA7 | PD14 | PB13 | PD11 |
+ | Input | VP2 | PA3 | PB0 | PA1 | PA4 |
+ | | VP3 | PA5 | PB14 | PA5 | PB11 |
+ +--------------------------------------------------------------+
+ (1): NA in follower mode.
+
+ Table 2. OPAMPs outputs for the STM32F3 devices:
+ +--------------------------------------------------------------+
+ | | | OPAMP1 | OPAMP2 | OPAMP3 | OPAMP4 |
+ |-----------------|--------|--------|--------|--------|--------|
+ | Output | | PA2 | PA6 | PB1 | PB12 |
+ |-----------------|--------|--------|--------|--------|--------|
+
+*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_OPAMP_MODULE_ENABLED
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+
+/** @defgroup OPAMP OPAMP
+ * @brief OPAMP HAL module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup OPAMP_Private_Define OPAMP Private Define
+ * @{
+ */
+/* CSR register reset value */
+#define OPAMP_CSR_RESET_VALUE (0x00000000U)
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup OPAMP_Exported_Functions OPAMP Exported Functions
+ * @{
+ */
+
+/** @defgroup OPAMP_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the OPAMP according to the specified
+ * parameters in the OPAMP_InitTypeDef and create the associated handle.
+ * @note If the selected opamp is locked, initialization can't be performed.
+ * To unlock the configuration, perform a system reset.
+ * @param hopamp OPAMP handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp)
+
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the OPAMP handle allocation and lock status */
+ /* Init not allowed if calibration is ongoing */
+ if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED) \
+ || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+
+ /* Check the parameter */
+ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
+
+ /* Set OPAMP parameters */
+ assert_param(IS_OPAMP_FUNCTIONAL_NORMALMODE(hopamp->Init.Mode));
+ assert_param(IS_OPAMP_NONINVERTING_INPUT(hopamp->Init.NonInvertingInput));
+ if ((hopamp->Init.Mode) == OPAMP_STANDALONE_MODE)
+ {
+ assert_param(IS_OPAMP_INVERTING_INPUT(hopamp->Init.InvertingInput));
+ }
+
+ assert_param(IS_OPAMP_TIMERCONTROLLED_MUXMODE(hopamp->Init.TimerControlledMuxmode));
+
+ if ((hopamp->Init.TimerControlledMuxmode) == OPAMP_TIMERCONTROLLEDMUXMODE_ENABLE)
+ {
+ assert_param(IS_OPAMP_SEC_NONINVERTINGINPUT(hopamp->Init.NonInvertingInputSecondary));
+ if ((hopamp->Init.Mode) == OPAMP_STANDALONE_MODE)
+ {
+ assert_param(IS_OPAMP_SEC_INVERTINGINPUT(hopamp->Init.InvertingInputSecondary));
+ }
+ }
+
+ if ((hopamp->Init.Mode) == OPAMP_PGA_MODE)
+ {
+ assert_param(IS_OPAMP_PGACONNECT(hopamp->Init.PgaConnect));
+ assert_param(IS_OPAMP_PGA_GAIN(hopamp->Init.PgaGain));
+ }
+
+ assert_param(IS_OPAMP_TRIMMING(hopamp->Init.UserTrimming));
+ if ((hopamp->Init.UserTrimming) == OPAMP_TRIMMING_USER)
+ {
+ assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueP));
+ assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueN));
+ }
+
+ /* Init SYSCFG and the low level hardware to access opamp */
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+ if(hopamp->State == HAL_OPAMP_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hopamp->Lock = HAL_UNLOCKED;
+ }
+
+ /* Call MSP init function */
+ HAL_OPAMP_MspInit(hopamp);
+
+ /* Set OPAMP parameters */
+ /* Set bits according to hopamp->hopamp->Init.Mode value */
+ /* Set bits according to hopamp->hopamp->Init.InvertingInput value */
+ /* Set bits according to hopamp->hopamp->Init.NonInvertingInput value */
+ /* Set bits according to hopamp->hopamp->Init.TimerControlledMuxmode value */
+ /* Set bits according to hopamp->hopamp->Init.InvertingInputSecondary value */
+ /* Set bits according to hopamp->hopamp->Init.NonInvertingInputSecondary value */
+ /* Set bits according to hopamp->hopamp->Init.PgaConnect value */
+ /* Set bits according to hopamp->hopamp->Init.PgaGain value */
+ /* Set bits according to hopamp->hopamp->Init.UserTrimming value */
+ /* Set bits according to hopamp->hopamp->Init.TrimmingValueP value */
+ /* Set bits according to hopamp->hopamp->Init.TrimmingValueN value */
+
+
+ /* check if OPAMP_PGA_MODE & in Follower mode */
+ /* - InvertingInput */
+ /* - InvertingInputSecondary */
+ /* are Not Applicable */
+
+ if ((hopamp->Init.Mode == OPAMP_PGA_MODE) || (hopamp->Init.Mode == OPAMP_FOLLOWER_MODE))
+ {
+ MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_UPDATE_PARAMETERS_INIT_MASK, \
+ hopamp->Init.Mode | \
+ hopamp->Init.NonInvertingInput | \
+ hopamp->Init.TimerControlledMuxmode | \
+ hopamp->Init.NonInvertingInputSecondary | \
+ hopamp->Init.PgaConnect | \
+ hopamp->Init.PgaGain | \
+ hopamp->Init.UserTrimming | \
+ (hopamp->Init.TrimmingValueP << OPAMP_INPUT_NONINVERTING) | \
+ (hopamp->Init.TrimmingValueN << OPAMP_INPUT_INVERTING));
+
+ }
+ else /* OPAMP_STANDALONE_MODE */
+ {
+ MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_UPDATE_PARAMETERS_INIT_MASK, \
+ hopamp->Init.Mode | \
+ hopamp->Init.InvertingInput | \
+ hopamp->Init.NonInvertingInput | \
+ hopamp->Init.TimerControlledMuxmode | \
+ hopamp->Init.InvertingInputSecondary | \
+ hopamp->Init.NonInvertingInputSecondary | \
+ hopamp->Init.PgaConnect | \
+ hopamp->Init.PgaGain | \
+ hopamp->Init.UserTrimming | \
+ (hopamp->Init.TrimmingValueP << OPAMP_INPUT_NONINVERTING) | \
+ (hopamp->Init.TrimmingValueN << OPAMP_INPUT_INVERTING));
+ }
+
+ /* Update the OPAMP state*/
+ if (hopamp->State == HAL_OPAMP_STATE_RESET)
+ {
+ /* From RESET state to READY State */
+ hopamp->State = HAL_OPAMP_STATE_READY;
+ }
+ /* else: remain in READY or BUSY state (no update) */
+
+ return status;
+ }
+}
+
+
+/**
+ * @brief DeInitializes the OPAMP peripheral
+ * @note Deinitialization can't be performed if the OPAMP configuration is locked.
+ * To unlock the configuration, perform a system reset.
+ * @param hopamp OPAMP handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_OPAMP_DeInit(OPAMP_HandleTypeDef *hopamp)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the OPAMP handle allocation */
+ /* DeInit not allowed if calibration is ongoing */
+ if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY))
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Check the parameter */
+ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
+
+ /* Set OPAMP_CSR register to reset value */
+ WRITE_REG(hopamp->Instance->CSR, OPAMP_CSR_RESET_VALUE);
+
+ /* DeInit the low level hardware: GPIO, CLOCK and NVIC */
+ /* When OPAMP is locked, unlocking can be achieved thanks to */
+ /* __HAL_RCC_SYSCFG_CLK_DISABLE() call within HAL_OPAMP_MspDeInit */
+ /* Note that __HAL_RCC_SYSCFG_CLK_DISABLE() also disables comparator */
+ HAL_OPAMP_MspDeInit(hopamp);
+
+ if (OPAMP_CSR_RESET_VALUE == hopamp->Instance->CSR)
+ {
+ /* Update the OPAMP state */
+ hopamp->State = HAL_OPAMP_STATE_RESET;
+ }
+ else /* RESET STATE */
+ {
+ /* DeInit not complete */
+ /* It can be the case if OPAMP was formerly locked */
+ status = HAL_ERROR;
+
+ /* The OPAMP state is NOT updated */
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hopamp);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Initializes the OPAMP MSP.
+ * @param hopamp OPAMP handle
+ * @retval None
+ */
+__weak void HAL_OPAMP_MspInit(OPAMP_HandleTypeDef *hopamp)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hopamp);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_OPAMP_MspInit could be implemented in the user file
+ */
+
+ /* Example */
+}
+
+/**
+ * @brief DeInitializes OPAMP MSP.
+ * @param hopamp OPAMP handle
+ * @retval None
+ */
+__weak void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef *hopamp)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hopamp);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_OPAMP_MspDeInit could be implemented in the user file
+ */
+
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup OPAMP_Exported_Functions_Group2 Input and Output operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the OPAMP data
+ transfers.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Start the opamp
+ * @param hopamp OPAMP handle
+ * @retval HAL status
+ */
+
+HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef *hopamp)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the OPAMP handle allocation */
+ /* Check if OPAMP locked */
+ if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED))
+
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Check the parameter */
+ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
+
+ if(hopamp->State == HAL_OPAMP_STATE_READY)
+ {
+ /* Enable the selected opamp */
+ SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
+
+ /* Update the OPAMP state*/
+ /* From HAL_OPAMP_STATE_READY to HAL_OPAMP_STATE_BUSY */
+ hopamp->State = HAL_OPAMP_STATE_BUSY;
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+
+
+ }
+ return status;
+}
+
+/**
+ * @brief Stop the opamp
+ * @param hopamp OPAMP handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the OPAMP handle allocation */
+ /* Check if OPAMP locked */
+ /* Check if OPAMP calibration ongoing */
+ if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED) \
+ || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY))
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Check the parameter */
+ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
+
+ if(hopamp->State == HAL_OPAMP_STATE_BUSY)
+ {
+ /* Disable the selected opamp */
+ CLEAR_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
+
+ /* Update the OPAMP state*/
+ /* From HAL_OPAMP_STATE_BUSY to HAL_OPAMP_STATE_READY*/
+ hopamp->State = HAL_OPAMP_STATE_READY;
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ }
+ return status;
+}
+
+/**
+ * @brief Run the self calibration of one OPAMP
+ * @param hopamp handle
+ * @retval Updated offset trimming values (PMOS & NMOS), user trimming is enabled
+ * @retval HAL status
+ * @note Calibration runs about 25 ms.
+ */
+
+HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp)
+{
+
+ HAL_StatusTypeDef status = HAL_OK;
+
+ uint32_t trimmingvaluen = 0U;
+ uint32_t trimmingvaluep = 0U;
+ uint32_t delta;
+
+ /* Check the OPAMP handle allocation */
+ /* Check if OPAMP locked */
+ if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED))
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+
+ /* Check if OPAMP in calibration mode and calibration not yet enable */
+ if(hopamp->State == HAL_OPAMP_STATE_READY)
+ {
+ /* Check the parameter */
+ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
+
+ /* Set Calibration mode */
+ /* Non-inverting input connected to calibration reference voltage. */
+ SET_BIT(hopamp->Instance->CSR, OPAMP_CSR_FORCEVP);
+
+ /* user trimming values are used for offset calibration */
+ SET_BIT(hopamp->Instance->CSR, OPAMP_CSR_USERTRIM);
+
+ /* Enable calibration */
+ SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_CALON);
+
+ /* 1st calibration - N */
+ /* Select 90U% VREF */
+ MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
+
+ /* Enable the selected opamp */
+ SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
+
+ /* Init trimming counter */
+ /* Medium value */
+ trimmingvaluen = 16U;
+ delta = 8U;
+
+ while (delta != 0U)
+ {
+ /* Set candidate trimming */
+ MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen<<OPAMP_INPUT_INVERTING);
+
+ /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
+ /* Offset trim time: during calibration, minimum time needed between */
+ /* two steps to have 1 mV accuracy */
+ HAL_Delay(2U);
+
+ if ((hopamp->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
+ {
+ /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
+ trimmingvaluen += delta;
+ }
+ else
+ {
+ /* OPAMP_CSR_OUTCAL is LOW try lower trimming */
+ trimmingvaluen -= delta;
+ }
+
+ delta >>= 1U;
+ }
+
+ /* Still need to check if righ calibration is current value or un step below */
+ /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0 */
+ MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen<<OPAMP_INPUT_INVERTING);
+
+ /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
+ /* Offset trim time: during calibration, minimum time needed between */
+ /* two steps to have 1 mV accuracy */
+ HAL_Delay(2U);
+
+ if ((hopamp->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
+ {
+ /* OPAMP_CSR_OUTCAL is actually one value more */
+ trimmingvaluen++;
+ /* Set right trimming */
+ MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen<<OPAMP_INPUT_INVERTING);
+ }
+
+ /* 2nd calibration - P */
+ /* Select 10U% VREF */
+ MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
+
+ /* Init trimming counter */
+ /* Medium value */
+ trimmingvaluep = 16U;
+ delta = 8U;
+
+ while (delta != 0U)
+ {
+ /* Set candidate trimming */
+ MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep<<OPAMP_INPUT_NONINVERTING);
+
+ /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
+ /* Offset trim time: during calibration, minimum time needed between */
+ /* two steps to have 1 mV accuracy */
+ HAL_Delay(2U);
+
+ if ((hopamp->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
+ {
+ /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
+ trimmingvaluep += delta;
+ }
+ else
+ {
+ trimmingvaluep -= delta;
+ }
+
+ delta >>= 1U;
+ }
+
+ /* Still need to check if righ calibration is current value or un step below */
+ /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0U */
+ /* Set candidate trimming */
+ MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep<<OPAMP_INPUT_NONINVERTING);
+
+ /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
+ /* Offset trim time: during calibration, minimum time needed between */
+ /* two steps to have 1 mV accuracy */
+ HAL_Delay(2U);
+
+ if ((hopamp->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
+ {
+ /* OPAMP_CSR_OUTCAL is actually one value more */
+ trimmingvaluep++;
+ /* Set right trimming */
+ MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep<<OPAMP_INPUT_NONINVERTING);
+ }
+
+ /* Disable calibration */
+ CLEAR_BIT (hopamp->Instance->CSR, OPAMP_CSR_CALON);
+
+ /* Disable the OPAMP */
+ CLEAR_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
+
+ /* Set operating mode */
+ /* Non-inverting input connected to calibration reference voltage. */
+ CLEAR_BIT(hopamp->Instance->CSR, OPAMP_CSR_FORCEVP);
+
+ /* Self calibration is successful */
+ /* Store calibration(user timming) results in init structure. */
+
+ /* Write calibration result N */
+ hopamp->Init.TrimmingValueN = trimmingvaluen;
+
+ /* Write calibration result P */
+ hopamp->Init.TrimmingValueP = trimmingvaluep;
+
+ /* Select user timming mode */
+ /* And updated with calibrated settings */
+ hopamp->Init.UserTrimming = OPAMP_TRIMMING_USER;
+ MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep<<OPAMP_INPUT_NONINVERTING);
+ MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen<<OPAMP_INPUT_INVERTING);
+ }
+
+ else
+ {
+ /* OPAMP can not be calibrated from this mode */
+ status = HAL_ERROR;
+ }
+ }
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_Exported_Functions_Group3 Peripheral Control functions
+ * @brief management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the OPAMP data
+ transfers.
+
+
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Lock the selected opamp configuration.
+ * @param hopamp OPAMP handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the OPAMP handle allocation */
+ /* Check if OPAMP locked */
+ /* OPAMP can be locked when enabled and running in normal mode */
+ /* It is meaningless otherwise */
+ if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_RESET) \
+ || (hopamp->State == HAL_OPAMP_STATE_READY) \
+ || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)\
+ || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED))
+
+ {
+ status = HAL_ERROR;
+ }
+
+ else
+ {
+ /* Check the parameter */
+ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
+
+ /* Lock OPAMP */
+ SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_LOCK);
+
+ /* OPAMP state changed to locked */
+ hopamp->State = HAL_OPAMP_STATE_BUSYLOCKED;
+ }
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_Exported_Functions_Group4 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..]
+ This subsection permit to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the OPAMP state
+ * @param hopamp OPAMP handle
+ * @retval HAL state
+ */
+HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp)
+{
+ /* Check the OPAMP handle allocation */
+ if(hopamp == NULL)
+ {
+ return HAL_OPAMP_STATE_RESET;
+ }
+
+ /* Check the parameter */
+ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
+
+ return hopamp->State;
+}
+
+/**
+ * @brief Return the OPAMP factory trimming value
+ * @param hopamp OPAMP handle
+ * @param trimmingoffset Trimming offset (P or N)
+ * @retval Trimming value (P or N): range: 0->31
+ * or OPAMP_FACTORYTRIMMING_DUMMY if trimming value is not available
+ */
+
+OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset)
+{
+ uint32_t oldusertrimming = 0U;
+ OPAMP_TrimmingValueTypeDef oldtrimmingvaluep = 0U, oldtrimmingvaluen = 0U, trimmingvalue = 0U;
+
+ /* Check the OPAMP handle allocation */
+ /* Value can be retrieved in HAL_OPAMP_STATE_READY state */
+ if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_RESET) \
+ || (hopamp->State == HAL_OPAMP_STATE_BUSY) \
+ || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)\
+ || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED))
+ {
+ return OPAMP_FACTORYTRIMMING_DUMMY;
+ }
+ else
+ {
+ /* Check the parameter */
+ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
+ assert_param(IS_OPAMP_FACTORYTRIMMING(trimmingoffset));
+
+ /* Check the trimming mode */
+ if ((READ_BIT(hopamp->Instance->CSR,OPAMP_CSR_USERTRIM)) != RESET)
+ {
+ /* User trimming is used */
+ oldusertrimming = OPAMP_TRIMMING_USER;
+ /* Store the TrimmingValueP & TrimmingValueN */
+ oldtrimmingvaluep = (hopamp->Instance->CSR & OPAMP_CSR_TRIMOFFSETP) >> OPAMP_INPUT_NONINVERTING;
+ oldtrimmingvaluen = (hopamp->Instance->CSR & OPAMP_CSR_TRIMOFFSETN) >> OPAMP_INPUT_INVERTING;
+ }
+
+ /* Set factory timming mode */
+ CLEAR_BIT (hopamp->Instance->CSR, OPAMP_CSR_USERTRIM);
+
+ /* Get factory trimming */
+ if (trimmingoffset == OPAMP_FACTORYTRIMMING_P)
+ {
+ /* Return TrimOffsetP */
+ trimmingvalue = ((hopamp->Instance->CSR & OPAMP_CSR_TRIMOFFSETP) >> OPAMP_INPUT_NONINVERTING);
+ }
+ else
+ {
+ /* Return TrimOffsetN */
+ trimmingvalue = ((hopamp->Instance->CSR & OPAMP_CSR_TRIMOFFSETN) >> OPAMP_INPUT_INVERTING);
+ }
+
+ /* Restore user trimming configuration if it was formerly set */
+ /* Check if user trimming was used */
+ if (oldusertrimming == OPAMP_TRIMMING_USER)
+ {
+ /* Restore user trimming */
+ SET_BIT(hopamp->Instance->CSR,OPAMP_CSR_USERTRIM);
+ MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, oldtrimmingvaluep<<OPAMP_INPUT_NONINVERTING);
+ MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, oldtrimmingvaluen<<OPAMP_INPUT_INVERTING);
+ }
+ }
+ return trimmingvalue;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#endif /* HAL_OPAMP_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_opamp_ex.c b/Src/stm32f3xx_hal_opamp_ex.c
new file mode 100644
index 0000000..df614c6
--- /dev/null
+++ b/Src/stm32f3xx_hal_opamp_ex.c
@@ -0,0 +1,743 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_opamp_ex.c
+ * @author MCD Application Team
+ * @brief Extended OPAMP HAL module driver.
+ *
+ * This file provides firmware functions to manage the following
+ * functionalities of the Power Controller (OPAMP) peripheral:
+ * + Extended Initialization and de-initialization functions
+ * + Extended Peripheral Control functions
+ *
+ @verbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_OPAMP_MODULE_ENABLED
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+
+/** @defgroup OPAMPEx OPAMPEx
+ * @brief OPAMP Extended HAL module driver.
+ * @{
+ */
+
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup OPAMPEx_Exported_Functions OPAMP Extended Exported Functions
+ * @{
+ */
+
+
+/** @defgroup OPAMPEx_Exported_Functions_Group1 Extended Input and Output operation functions
+ * @brief Extended Self calibration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended IO operation functions #####
+ ===============================================================================
+ [..]
+
+@endverbatim
+ * @{
+ */
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC)
+/* 2 OPAMPS available */
+/* 2 OPAMPS can be calibrated in parallel */
+
+/**
+ * @brief Run the self calibration of 2 OPAMPs in parallel.
+ * @param hopamp1 handle
+ * @param hopamp2 handle
+ * @retval HAL status
+ * @note Updated offset trimming values (PMOS & NMOS), user trimming is enabled
+ * @note Calibration runs about 25 ms.
+ */
+
+HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ uint32_t trimmingvaluen1 = 0U;
+ uint32_t trimmingvaluep1 = 0U;
+ uint32_t trimmingvaluen2 = 0U;
+ uint32_t trimmingvaluep2 = 0U;
+
+ uint32_t delta;
+
+ if((hopamp1 == NULL) || (hopamp1->State == HAL_OPAMP_STATE_BUSYLOCKED) || \
+ (hopamp2 == NULL) || (hopamp2->State == HAL_OPAMP_STATE_BUSYLOCKED))
+ {
+ status = HAL_ERROR;
+ }
+
+ if(status == HAL_OK)
+ {
+ /* Check if OPAMP in calibration mode and calibration not yet enable */
+ if((hopamp1->State == HAL_OPAMP_STATE_READY) && (hopamp2->State == HAL_OPAMP_STATE_READY))
+ {
+ /* Check the parameter */
+ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp1->Instance));
+ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp2->Instance));
+
+ /* Set Calibration mode */
+ /* Non-inverting input connected to calibration reference voltage. */
+ SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_FORCEVP);
+ SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_FORCEVP);
+
+ /* user trimming values are used for offset calibration */
+ SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_USERTRIM);
+ SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_USERTRIM);
+
+ /* Enable calibration */
+ SET_BIT (hopamp1->Instance->CSR, OPAMP_CSR_CALON);
+ SET_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALON);
+
+ /* 1st calibration - N */
+ /* Select 90U% VREF */
+ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
+ MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
+
+ /* Enable the opamps */
+ SET_BIT (hopamp1->Instance->CSR, OPAMP_CSR_OPAMPxEN);
+ SET_BIT (hopamp2->Instance->CSR, OPAMP_CSR_OPAMPxEN);
+
+ /* Init trimming counter */
+ /* Medium value */
+ trimmingvaluen1 = 16U;
+ trimmingvaluen2 = 16U;
+ delta = 8U;
+
+ while (delta != 0U)
+ {
+ /* Set candidate trimming */
+ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1<<OPAMP_INPUT_INVERTING);
+ MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen2<<OPAMP_INPUT_INVERTING);
+
+ /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
+ /* Offset trim time: during calibration, minimum time needed between */
+ /* two steps to have 1 mV accuracy */
+ HAL_Delay(2U);
+
+ if (hopamp1->Instance->CSR & OPAMP_CSR_OUTCAL)
+ {
+ /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
+ trimmingvaluen1 += delta;
+ }
+ else
+ {
+ /* OPAMP_CSR_OUTCAL is LOW try lower trimming */
+ trimmingvaluen1 -= delta;
+ }
+
+ if (hopamp2->Instance->CSR & OPAMP_CSR_OUTCAL)
+ {
+ /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
+ trimmingvaluen2 += delta;
+ }
+ else
+ {
+ /* OPAMP_CSR_OUTCAL is LOW try lower trimming */
+ trimmingvaluen2 -= delta;
+ }
+
+ delta >>= 1U;
+ }
+
+ // Still need to check if righ calibration is current value or un step below
+ // Indeed the first value that causes the OUTCAL bit to change from 1 to 0
+ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1<<OPAMP_INPUT_INVERTING);
+ MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen2<<OPAMP_INPUT_INVERTING);
+
+ /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
+ /* Offset trim time: during calibration, minimum time needed between */
+ /* two steps to have 1 mV accuracy */
+ HAL_Delay(2U);
+
+ if (hopamp1->Instance->CSR & OPAMP_CSR_OUTCAL)
+ {
+ /* OPAMP_CSR_OUTCAL is actually one value more */
+ trimmingvaluen1++;
+ /* Set right trimming */
+ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1<<OPAMP_INPUT_INVERTING);
+ }
+
+ if (hopamp2->Instance->CSR & OPAMP_CSR_OUTCAL)
+ {
+ /* OPAMP_CSR_OUTCAL is actually one value more */
+ trimmingvaluen2++;
+ /* Set right trimming */
+ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen2<<OPAMP_INPUT_INVERTING);
+ }
+
+ /* 2nd calibration - P */
+ /* Select 10U% VREF */
+ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
+ MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
+
+ /* Init trimming counter */
+ /* Medium value */
+ trimmingvaluep1 = 16U;
+ trimmingvaluep2 = 16U;
+ delta = 8U;
+
+ while (delta != 0U)
+ {
+ /* Set candidate trimming */
+ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1<<OPAMP_INPUT_NONINVERTING);
+ MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep2<<OPAMP_INPUT_NONINVERTING);
+
+ /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
+ /* Offset trim time: during calibration, minimum time needed between */
+ /* two steps to have 1 mV accuracy */
+ HAL_Delay(2U);
+
+ if (hopamp1->Instance->CSR & OPAMP_CSR_OUTCAL)
+ {
+ /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
+ trimmingvaluep1 += delta;
+ }
+ else
+ {
+ trimmingvaluep1 -= delta;
+ }
+
+ if (hopamp2->Instance->CSR & OPAMP_CSR_OUTCAL)
+ {
+ /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
+ trimmingvaluep2 += delta;
+ }
+ else
+ {
+ trimmingvaluep2 -= delta;
+ }
+
+ delta >>= 1U;
+ }
+
+ // Still need to check if righ calibration is current value or un step below
+ // Indeed the first value that causes the OUTCAL bit to change from 1 to 0
+ /* Set candidate trimming */
+ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1<<OPAMP_INPUT_NONINVERTING);
+ MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep2<<OPAMP_INPUT_NONINVERTING);
+
+ /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
+ /* Offset trim time: during calibration, minimum time needed between */
+ /* two steps to have 1 mV accuracy */
+ HAL_Delay(2U);
+
+ if (hopamp1->Instance->CSR & OPAMP_CSR_OUTCAL)
+ {
+ /* OPAMP_CSR_OUTCAL is actually one value more */
+ trimmingvaluep1++;
+ /* Set right trimming */
+ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1<<OPAMP_INPUT_NONINVERTING);
+ }
+
+ if (hopamp2->Instance->CSR & OPAMP_CSR_OUTCAL)
+ {
+ /* OPAMP_CSR_OUTCAL is actually one value more */
+ trimmingvaluep2++;
+ /* Set right trimming */
+ MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep2<<OPAMP_INPUT_NONINVERTING);
+ }
+
+ /* Disable calibration */
+ CLEAR_BIT (hopamp1->Instance->CSR, OPAMP_CSR_CALON);
+ CLEAR_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALON);
+
+ /* Disable the OPAMPs */
+ CLEAR_BIT (hopamp1->Instance->CSR, OPAMP_CSR_OPAMPxEN);
+ CLEAR_BIT (hopamp2->Instance->CSR, OPAMP_CSR_OPAMPxEN);
+
+ /* Set operating mode back */
+ CLEAR_BIT(hopamp1->Instance->CSR, OPAMP_CSR_FORCEVP);
+ CLEAR_BIT(hopamp2->Instance->CSR, OPAMP_CSR_FORCEVP);
+
+ /* Self calibration is successful */
+ /* Store calibration(user timming) results in init structure. */
+ /* Select user timming mode */
+
+ /* Write calibration result N */
+ hopamp1->Init.TrimmingValueN = trimmingvaluen1;
+ hopamp2->Init.TrimmingValueN = trimmingvaluen2;
+
+ /* Write calibration result P */
+ hopamp1->Init.TrimmingValueP = trimmingvaluep1;
+ hopamp2->Init.TrimmingValueP = trimmingvaluep2;
+
+ /* Calibration */
+ hopamp1->Init.UserTrimming = OPAMP_TRIMMING_USER;
+ hopamp2->Init.UserTrimming = OPAMP_TRIMMING_USER;
+
+ /* Select user timming mode */
+ /* And updated with calibrated settings */
+ hopamp1->Init.UserTrimming = OPAMP_TRIMMING_USER;
+ hopamp2->Init.UserTrimming = OPAMP_TRIMMING_USER;
+
+ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1<<OPAMP_INPUT_INVERTING);
+ MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen2<<OPAMP_INPUT_INVERTING);
+
+ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1<<OPAMP_INPUT_NONINVERTING);
+ MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep2<<OPAMP_INPUT_NONINVERTING);
+
+ }
+
+ else
+ {
+ /* At least one OPAMP can not be calibrated */
+ status = HAL_ERROR;
+ }
+ }
+
+ return status;
+}
+#endif /* STM32F302xE || */
+ /* STM32F302xC */
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+/* 4 OPAMPS available */
+/* 4 OPAMPS can be calibrated in parallel */
+
+/**
+ * @brief Run the self calibration of 4 OPAMPs in parallel.
+ * @param hopamp1 handle
+ * @param hopamp2 handle
+ * @param hopamp3 handle
+ * @param hopamp4 handle
+ * @retval HAL status
+ * @note Updated offset trimming values (PMOS & NMOS), user trimming is enabled
+ * @note Calibration runs about 25 ms.
+ */
+
+HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2, OPAMP_HandleTypeDef *hopamp3, OPAMP_HandleTypeDef *hopamp4)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ uint32_t trimmingvaluen1 = 0U;
+ uint32_t trimmingvaluep1 = 0U;
+ uint32_t trimmingvaluen2 = 0U;
+ uint32_t trimmingvaluep2 = 0U;
+ uint32_t trimmingvaluen3 = 0U;
+ uint32_t trimmingvaluep3 = 0U;
+ uint32_t trimmingvaluen4 = 0U;
+ uint32_t trimmingvaluep4 = 0U;
+
+ uint32_t delta;
+
+ if((hopamp1 == NULL) || (hopamp1->State == HAL_OPAMP_STATE_BUSYLOCKED) || \
+ (hopamp2 == NULL) || (hopamp2->State == HAL_OPAMP_STATE_BUSYLOCKED) || \
+ (hopamp3 == NULL) || (hopamp3->State == HAL_OPAMP_STATE_BUSYLOCKED) || \
+ (hopamp4 == NULL) || (hopamp4->State == HAL_OPAMP_STATE_BUSYLOCKED))
+ {
+ status = HAL_ERROR;
+ }
+
+ if(status == HAL_OK)
+ {
+ /* Check if OPAMP in calibration mode and calibration not yet enable */
+ if((hopamp1->State == HAL_OPAMP_STATE_READY) && (hopamp2->State == HAL_OPAMP_STATE_READY) && \
+ (hopamp3->State == HAL_OPAMP_STATE_READY) && (hopamp4->State == HAL_OPAMP_STATE_READY))
+ {
+ /* Check the parameter */
+ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp1->Instance));
+ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp2->Instance));
+ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp3->Instance));
+ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp4->Instance));
+
+ /* Set Calibration mode */
+ /* Non-inverting input connected to calibration reference voltage. */
+ SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_FORCEVP);
+ SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_FORCEVP);
+ SET_BIT(hopamp3->Instance->CSR, OPAMP_CSR_FORCEVP);
+ SET_BIT(hopamp4->Instance->CSR, OPAMP_CSR_FORCEVP);
+
+ /* user trimming values are used for offset calibration */
+ SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_USERTRIM);
+ SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_USERTRIM);
+ SET_BIT(hopamp3->Instance->CSR, OPAMP_CSR_USERTRIM);
+ SET_BIT(hopamp4->Instance->CSR, OPAMP_CSR_USERTRIM);
+
+ /* Enable calibration */
+ SET_BIT (hopamp1->Instance->CSR, OPAMP_CSR_CALON);
+ SET_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALON);
+ SET_BIT (hopamp3->Instance->CSR, OPAMP_CSR_CALON);
+ SET_BIT (hopamp4->Instance->CSR, OPAMP_CSR_CALON);
+
+ /* 1st calibration - N */
+ /* Select 90U% VREF */
+ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
+ MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
+ MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
+ MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
+
+ /* Enable the opamps */
+ SET_BIT (hopamp1->Instance->CSR, OPAMP_CSR_OPAMPxEN);
+ SET_BIT (hopamp2->Instance->CSR, OPAMP_CSR_OPAMPxEN);
+ SET_BIT (hopamp3->Instance->CSR, OPAMP_CSR_OPAMPxEN);
+ SET_BIT (hopamp4->Instance->CSR, OPAMP_CSR_OPAMPxEN);
+
+ /* Init trimming counter */
+ /* Medium value */
+ trimmingvaluen1 = 16U;
+ trimmingvaluen2 = 16U;
+ trimmingvaluen3 = 16U;
+ trimmingvaluen4 = 16U;
+ delta = 8U;
+
+ while (delta != 0U)
+ {
+ /* Set candidate trimming */
+ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1<<OPAMP_INPUT_INVERTING);
+ MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen2<<OPAMP_INPUT_INVERTING);
+ MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen3<<OPAMP_INPUT_INVERTING);
+ MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen4<<OPAMP_INPUT_INVERTING);
+
+ /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
+ /* Offset trim time: during calibration, minimum time needed between */
+ /* two steps to have 1 mV accuracy */
+ HAL_Delay(2U);
+
+ if ((hopamp1->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
+ {
+ /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
+ trimmingvaluen1 += delta;
+ }
+ else
+ {
+ /* OPAMP_CSR_OUTCAL is LOW try lower trimming */
+ trimmingvaluen1 -= delta;
+ }
+
+ if ((hopamp2->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
+ {
+ /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
+ trimmingvaluen2 += delta;
+ }
+ else
+ {
+ /* OPAMP_CSR_OUTCAL is LOW try lower trimming */
+ trimmingvaluen2 -= delta;
+ }
+
+ if ((hopamp3->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
+ {
+ /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
+ trimmingvaluen3 += delta;
+ }
+ else
+ {
+ /* OPAMP_CSR_OUTCAL is LOW try lower trimming */
+ trimmingvaluen3 -= delta;
+ }
+
+ if ((hopamp4->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
+ {
+ /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
+ trimmingvaluen4 += delta;
+ }
+ else
+ {
+ /* OPAMP_CSR_OUTCAL is LOW try lower trimming */
+ trimmingvaluen4 -= delta;
+ }
+
+ delta >>= 1U;
+ }
+
+ /* Still need to check if righ calibration is current value or un step below */
+ /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0U */
+ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1<<OPAMP_INPUT_INVERTING);
+ MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen2<<OPAMP_INPUT_INVERTING);
+ MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen3<<OPAMP_INPUT_INVERTING);
+ MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen4<<OPAMP_INPUT_INVERTING);
+
+ /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
+ /* Offset trim time: during calibration, minimum time needed between */
+ /* two steps to have 1 mV accuracy */
+ HAL_Delay(2U);
+
+ if ((hopamp1->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
+ {
+ /* OPAMP_CSR_OUTCAL is actually one value more */
+ trimmingvaluen1++;
+ /* Set right trimming */
+ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1<<OPAMP_INPUT_INVERTING);
+ }
+
+ if ((hopamp2->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
+ {
+ /* OPAMP_CSR_OUTCAL is actually one value more */
+ trimmingvaluen2++;
+ /* Set right trimming */
+ MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen2<<OPAMP_INPUT_INVERTING);
+ }
+
+ if ((hopamp3->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
+ {
+ /* OPAMP_CSR_OUTCAL is actually one value more */
+ trimmingvaluen3++;
+ /* Set right trimming */
+ MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen3<<OPAMP_INPUT_INVERTING);
+ }
+
+ if ((hopamp4->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
+ {
+ /* OPAMP_CSR_OUTCAL is actually one value more */
+ trimmingvaluen4++;
+ /* Set right trimming */
+ MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen4<<OPAMP_INPUT_INVERTING);
+ }
+
+ /* 2nd calibration - P */
+ /* Select 10U% VREF */
+ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
+ MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
+ MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
+ MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
+
+ /* Init trimming counter */
+ /* Medium value */
+ trimmingvaluep1 = 16U;
+ trimmingvaluep2 = 16U;
+ trimmingvaluep3 = 16U;
+ trimmingvaluep4 = 16U;
+
+ delta = 8U;
+
+ while (delta != 0U)
+ {
+ /* Set candidate trimming */
+ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1<<OPAMP_INPUT_NONINVERTING);
+ MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep2<<OPAMP_INPUT_NONINVERTING);
+ MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep3<<OPAMP_INPUT_NONINVERTING);
+ MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep4<<OPAMP_INPUT_NONINVERTING);
+
+ /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
+ /* Offset trim time: during calibration, minimum time needed between */
+ /* two steps to have 1 mV accuracy */
+ HAL_Delay(2U);
+
+ if ((hopamp1->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
+ {
+ /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
+ trimmingvaluep1 += delta;
+ }
+ else
+ {
+ trimmingvaluep1 -= delta;
+ }
+
+ if ((hopamp2->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
+ {
+ /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
+ trimmingvaluep2 += delta;
+ }
+ else
+ {
+ trimmingvaluep2 -= delta;
+ }
+
+ if ((hopamp3->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
+ {
+ /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
+ trimmingvaluep3 += delta;
+ }
+ else
+ {
+ trimmingvaluep3 -= delta;
+ }
+
+ if ((hopamp4->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
+ {
+ /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
+ trimmingvaluep4 += delta;
+ }
+ else
+ {
+ trimmingvaluep4 -= delta;
+ }
+
+ delta >>= 1U;
+ }
+
+ /* Still need to check if righ calibration is current value or un step below */
+ /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0U */
+ /* Set candidate trimming */
+ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1<<OPAMP_INPUT_NONINVERTING);
+ MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep2<<OPAMP_INPUT_NONINVERTING);
+ MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep3<<OPAMP_INPUT_NONINVERTING);
+ MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep4<<OPAMP_INPUT_NONINVERTING);
+
+ /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
+ /* Offset trim time: during calibration, minimum time needed between */
+ /* two steps to have 1 mV accuracy */
+ HAL_Delay(2U);
+
+ if ((hopamp1->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
+ {
+ /* Trimming value is actually one value more */
+ trimmingvaluep1++;
+ /* Set right trimming */
+ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1<<OPAMP_INPUT_NONINVERTING);
+ }
+
+ if ((hopamp2->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
+ {
+ /* Trimming value is actually one value more */
+ trimmingvaluep2++;
+ /* Set right trimming */
+ MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep2<<OPAMP_INPUT_NONINVERTING);
+ }
+
+ if ((hopamp3->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
+ {
+ /* Trimming value is actually one value more */
+ trimmingvaluep3++;
+ /* Set right trimming */
+ MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep3<<OPAMP_INPUT_NONINVERTING);
+ }
+
+ if ((hopamp4->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
+ {
+ /* Trimming value is actually one value more */
+ trimmingvaluep4++;
+ /* Set right trimming */
+ MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep4<<OPAMP_INPUT_NONINVERTING);
+ }
+
+ /* Disable calibration */
+ CLEAR_BIT (hopamp1->Instance->CSR, OPAMP_CSR_CALON);
+ CLEAR_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALON);
+ CLEAR_BIT (hopamp3->Instance->CSR, OPAMP_CSR_CALON);
+ CLEAR_BIT (hopamp4->Instance->CSR, OPAMP_CSR_CALON);
+
+ /* Disable the OPAMPs */
+ CLEAR_BIT (hopamp1->Instance->CSR, OPAMP_CSR_OPAMPxEN);
+ CLEAR_BIT (hopamp2->Instance->CSR, OPAMP_CSR_OPAMPxEN);
+ CLEAR_BIT (hopamp3->Instance->CSR, OPAMP_CSR_OPAMPxEN);
+ CLEAR_BIT (hopamp4->Instance->CSR, OPAMP_CSR_OPAMPxEN);
+
+ /* Set normal operating mode back */
+ CLEAR_BIT(hopamp1->Instance->CSR, OPAMP_CSR_FORCEVP);
+ CLEAR_BIT(hopamp2->Instance->CSR, OPAMP_CSR_FORCEVP);
+ CLEAR_BIT(hopamp3->Instance->CSR, OPAMP_CSR_FORCEVP);
+ CLEAR_BIT(hopamp4->Instance->CSR, OPAMP_CSR_FORCEVP);
+
+ /* Self calibration is successful */
+ /* Store calibration(user timming) results in init structure. */
+ /* Select user timming mode */
+
+ /* Write calibration result N */
+ hopamp1->Init.TrimmingValueN = trimmingvaluen1;
+ hopamp2->Init.TrimmingValueN = trimmingvaluen2;
+ hopamp3->Init.TrimmingValueN = trimmingvaluen3;
+ hopamp4->Init.TrimmingValueN = trimmingvaluen4;
+
+ /* Write calibration result P */
+ hopamp1->Init.TrimmingValueP = trimmingvaluep1;
+ hopamp2->Init.TrimmingValueP = trimmingvaluep2;
+ hopamp3->Init.TrimmingValueP = trimmingvaluep3;
+ hopamp4->Init.TrimmingValueP = trimmingvaluep4;
+
+ /* Select user timming mode */
+ /* And updated with calibrated settings */
+ hopamp1->Init.UserTrimming = OPAMP_TRIMMING_USER;
+ hopamp2->Init.UserTrimming = OPAMP_TRIMMING_USER;
+ hopamp3->Init.UserTrimming = OPAMP_TRIMMING_USER;
+ hopamp4->Init.UserTrimming = OPAMP_TRIMMING_USER;
+
+ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1<<OPAMP_INPUT_INVERTING);
+ MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen2<<OPAMP_INPUT_INVERTING);
+ MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen3<<OPAMP_INPUT_INVERTING);
+ MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen4<<OPAMP_INPUT_INVERTING);
+
+ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1<<OPAMP_INPUT_NONINVERTING);
+ MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep2<<OPAMP_INPUT_NONINVERTING);
+ MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep3<<OPAMP_INPUT_NONINVERTING);
+ MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep4<<OPAMP_INPUT_NONINVERTING);
+
+ }
+
+ else
+ {
+ /* At least one OPAMP can not be calibrated */
+ status = HAL_ERROR;
+ }
+ }
+
+ return status;
+}
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#endif /* HAL_OPAMP_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_pccard.c b/Src/stm32f3xx_hal_pccard.c
new file mode 100644
index 0000000..e1cae18
--- /dev/null
+++ b/Src/stm32f3xx_hal_pccard.c
@@ -0,0 +1,749 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_pccard.c
+ * @author MCD Application Team
+ * @brief PCCARD HAL module driver.
+ * This file provides a generic firmware to drive PCCARD memories mounted
+ * as external device.
+ *
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ This driver is a generic layered driver which contains a set of APIs used to
+ control PCCARD/compact flash memories. It uses the FMC layer functions
+ to interface with PCCARD devices. This driver is used for:
+
+ (+) PCCARD/compact flash memory configuration sequence using the function
+ HAL_PCCARD_Init() with control and timing parameters for both common and
+ attribute spaces.
+
+ (+) Read PCCARD/compact flash memory maker and device IDs using the function
+ HAL_PCCARD_Read_ID(). The read information is stored in the CompactFlash_ID
+ structure declared by the function caller.
+
+ (+) Access PCCARD/compact flash memory by read/write operations using the functions
+ HAL_PCCARD_Read_Sector()/HAL_PCCARD_Write_Sector(), to read/write sector.
+
+ (+) Perform PCCARD/compact flash Reset chip operation using the function HAL_PCCARD_Reset().
+
+ (+) Perform PCCARD/compact flash erase sector operation using the function
+ HAL_PCCARD_Erase_Sector().
+
+ (+) Read the PCCARD/compact flash status operation using the function HAL_PCCARD_ReadStatus().
+
+ (+) You can monitor the PCCARD/compact flash device HAL state by calling the function
+ HAL_PCCARD_GetState()
+
+ [..]
+ (@) This driver is a set of generic APIs which handle standard PCCARD/compact flash
+ operations. If a PCCARD/compact flash device contains different operations
+ and/or implementations, it should be implemented separately.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_PCCARD_MODULE_ENABLED
+
+/** @defgroup PCCARD PCCARD
+ * @brief PCCARD HAL module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup PCCARD_Private_Constants PCCARD Private Constants
+ * @{
+ */
+
+#define PCCARD_TIMEOUT_READ_ID 0x0000FFFF
+#define PCCARD_TIMEOUT_SECTOR 0x0000FFFF
+#define PCCARD_TIMEOUT_STATUS 0x01000000
+
+#define PCCARD_STATUS_OK (uint8_t)0x58
+#define PCCARD_STATUS_WRITE_OK (uint8_t)0x50
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup PCCARD_Exported_Functions PCCARD Exported Functions
+ * @{
+ */
+
+/** @defgroup PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### PCCARD Initialization and de-initialization functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to initialize/de-initialize
+ the PCCARD memory
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Perform the PCCARD memory Initialization sequence
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @param ComSpaceTiming Common space timing structure
+ * @param AttSpaceTiming Attribute space timing structure
+ * @param IOSpaceTiming IO space timing structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming)
+{
+ /* Check the PCCARD controller state */
+ if(hpccard == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ if(hpccard->State == HAL_PCCARD_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hpccard->Lock = HAL_UNLOCKED;
+
+ /* Initialize the low level hardware (MSP) */
+ HAL_PCCARD_MspInit(hpccard);
+ }
+
+ /* Initialize the PCCARD state */
+ hpccard->State = HAL_PCCARD_STATE_BUSY;
+
+ /* Initialize PCCARD control Interface */
+ FMC_PCCARD_Init(hpccard->Instance, &(hpccard->Init));
+
+ /* Init PCCARD common space timing Interface */
+ FMC_PCCARD_CommonSpace_Timing_Init(hpccard->Instance, ComSpaceTiming);
+
+ /* Init PCCARD attribute space timing Interface */
+ FMC_PCCARD_AttributeSpace_Timing_Init(hpccard->Instance, AttSpaceTiming);
+
+ /* Init PCCARD IO space timing Interface */
+ FMC_PCCARD_IOSpace_Timing_Init(hpccard->Instance, IOSpaceTiming);
+
+ /* Enable the PCCARD device */
+ __FMC_PCCARD_ENABLE(hpccard->Instance);
+
+ /* Update the PCCARD state */
+ hpccard->State = HAL_PCCARD_STATE_READY;
+
+ return HAL_OK;
+
+}
+
+/**
+ * @brief Perform the PCCARD memory De-initialization sequence
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard)
+{
+ /* De-Initialize the low level hardware (MSP) */
+ HAL_PCCARD_MspDeInit(hpccard);
+
+ /* Configure the PCCARD registers with their reset values */
+ FMC_PCCARD_DeInit(hpccard->Instance);
+
+ /* Update the PCCARD controller state */
+ hpccard->State = HAL_PCCARD_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpccard);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief PCCARD MSP Init
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @retval None
+ */
+__weak void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpccard);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PCCARD_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief PCCARD MSP DeInit
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @retval None
+ */
+__weak void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpccard);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PCCARD_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup PCCARD_Exported_Functions_Group2 Input Output and memory functions
+ * @brief Input Output and memory control functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### PCCARD Input Output and memory functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to use and control the PCCARD memory
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Read Compact Flash's ID.
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @param CompactFlash_ID Compact flash ID structure.
+ * @param pStatus pointer to compact flash status
+ * @retval HAL status
+ *
+ */
+HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus)
+{
+ uint32_t timeout = PCCARD_TIMEOUT_READ_ID, index = 0U;
+ uint8_t status = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hpccard);
+
+ /* Check the PCCARD controller state */
+ if(hpccard->State == HAL_PCCARD_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Update the PCCARD controller state */
+ hpccard->State = HAL_PCCARD_STATE_BUSY;
+
+ /* Initialize the CF status */
+ *pStatus = PCCARD_READY;
+
+ /* Send the Identify Command */
+ *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = 0xECEC;
+
+ /* Read CF IDs and timeout treatment */
+ do
+ {
+ /* Read the CF status */
+ status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
+
+ timeout--;
+ }while((status != PCCARD_STATUS_OK) && timeout);
+
+ if(timeout == 0U)
+ {
+ *pStatus = PCCARD_TIMEOUT_ERROR;
+ }
+ else
+ {
+ /* Read CF ID bytes */
+ for(index = 0U; index < 16U; index++)
+ {
+ CompactFlash_ID[index] = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_DATA);
+ }
+ }
+
+ /* Update the PCCARD controller state */
+ hpccard->State = HAL_PCCARD_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hpccard);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Read sector from PCCARD memory
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @param pBuffer pointer to destination read buffer
+ * @param SectorAddress Sector address to read
+ * @param pStatus pointer to CF status
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
+{
+ uint32_t timeout = PCCARD_TIMEOUT_SECTOR, index = 0U;
+ uint8_t status = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hpccard);
+
+ /* Check the PCCARD controller state */
+ if(hpccard->State == HAL_PCCARD_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Update the PCCARD controller state */
+ hpccard->State = HAL_PCCARD_STATE_BUSY;
+
+ /* Initialize CF status */
+ *pStatus = PCCARD_READY;
+
+ /* Set the parameters to write a sector */
+ *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x00;
+ *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = ((uint16_t)0x0100 ) | ((uint16_t)SectorAddress);
+ *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = (uint16_t)0xE4A0;
+
+ do
+ {
+ /* wait till the Status = 0x80U */
+ status = *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
+ timeout--;
+ }while((status == 0x80U) && timeout);
+
+ if(timeout == 0U)
+ {
+ *pStatus = PCCARD_TIMEOUT_ERROR;
+ }
+
+ timeout = 0xFFFFU;
+
+ do
+ {
+ /* wait till the Status = PCCARD_STATUS_OK */
+ status = *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
+ timeout--;
+ }while((status != PCCARD_STATUS_OK) && timeout);
+
+ if(timeout == 0U)
+ {
+ *pStatus = PCCARD_TIMEOUT_ERROR;
+ }
+
+ /* Read bytes */
+ for(; index < PCCARD_SECTOR_SIZE; index++)
+ {
+ *(uint16_t *)pBuffer++ = *(uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR);
+ }
+
+ /* Update the PCCARD controller state */
+ hpccard->State = HAL_PCCARD_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hpccard);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Write sector to PCCARD memory
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @param pBuffer pointer to source write buffer
+ * @param SectorAddress Sector address to write
+ * @param pStatus pointer to CF status
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
+{
+ uint32_t timeout = PCCARD_TIMEOUT_SECTOR, index = 0U;
+ uint8_t status = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hpccard);
+
+ /* Check the PCCARD controller state */
+ if(hpccard->State == HAL_PCCARD_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Update the PCCARD controller state */
+ hpccard->State = HAL_PCCARD_STATE_BUSY;
+
+ /* Initialize CF status */
+ *pStatus = PCCARD_READY;
+
+ /* Set the parameters to write a sector */
+ *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x00;
+ *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = ((uint16_t)0x0100 ) | ((uint16_t)SectorAddress);
+ *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = (uint16_t)0x30A0;
+
+ do
+ {
+ /* Wait till the Status = PCCARD_STATUS_OK */
+ status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
+ timeout--;
+ }while((status != PCCARD_STATUS_OK) && timeout);
+
+ if(timeout == 0U)
+ {
+ *pStatus = PCCARD_TIMEOUT_ERROR;
+ }
+
+ /* Write bytes */
+ for(; index < PCCARD_SECTOR_SIZE; index++)
+ {
+ *(uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR) = *(uint16_t *)pBuffer++;
+ }
+
+ do
+ {
+ /* Wait till the Status = PCCARD_STATUS_WRITE_OK */
+ status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
+ timeout--;
+ }while((status != PCCARD_STATUS_WRITE_OK) && timeout);
+
+ if(timeout == 0U)
+ {
+ *pStatus = PCCARD_TIMEOUT_ERROR;
+ }
+
+ /* Update the PCCARD controller state */
+ hpccard->State = HAL_PCCARD_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hpccard);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Erase sector from PCCARD memory
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @param SectorAddress Sector address to erase
+ * @param pStatus pointer to CF status
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus)
+{
+ uint32_t timeout = 0x400U;
+ uint8_t status = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hpccard);
+
+ /* Check the PCCARD controller state */
+ if(hpccard->State == HAL_PCCARD_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Update the PCCARD controller state */
+ hpccard->State = HAL_PCCARD_STATE_BUSY;
+
+ /* Initialize CF status */
+ *pStatus = PCCARD_READY;
+
+ /* Set the parameters to write a sector */
+ *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_LOW) = 0x00;
+ *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = 0x00;
+ *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_NUMBER) = SectorAddress;
+ *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = 0x01;
+ *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CARD_HEAD) = 0xA0;
+ *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = ATA_ERASE_SECTOR_CMD;
+
+ /* wait till the CF is ready */
+ status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
+
+ while((status != PCCARD_STATUS_WRITE_OK) && timeout)
+ {
+ status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
+ timeout--;
+ }
+
+ if(timeout == 0U)
+ {
+ *pStatus = PCCARD_TIMEOUT_ERROR;
+ }
+
+ /* Check the PCCARD controller state */
+ hpccard->State = HAL_PCCARD_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hpccard);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Reset the PCCARD memory
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard)
+{
+ /* Process Locked */
+ __HAL_LOCK(hpccard);
+
+ /* Check the PCCARD controller state */
+ if(hpccard->State == HAL_PCCARD_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Provide an SW reset and Read and verify the:
+ - CF Configuration Option Register at address 0x98000200U --> 0x80
+ - Card Configuration and Status Register at address 0x98000202U --> 0x00
+ - Pin Replacement Register at address 0x98000204U --> 0x0C
+ - Socket and Copy Register at address 0x98000206U --> 0x00
+ */
+
+ /* Check the PCCARD controller state */
+ hpccard->State = HAL_PCCARD_STATE_BUSY;
+
+ *(__IO uint8_t *)(PCCARD_ATTRIBUTE_SPACE_ADDRESS | ATA_CARD_CONFIGURATION) = 0x01;
+
+ /* Check the PCCARD controller state */
+ hpccard->State = HAL_PCCARD_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hpccard);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles PCCARD device interrupt request.
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @retval HAL status
+*/
+void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard)
+{
+ /* Check PCCARD interrupt Rising edge flag */
+ if(__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_RISING_EDGE))
+ {
+ /* PCCARD interrupt callback*/
+ HAL_PCCARD_ITCallback(hpccard);
+
+ /* Clear PCCARD interrupt Rising edge pending bit */
+ __FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_RISING_EDGE);
+ }
+
+ /* Check PCCARD interrupt Level flag */
+ if(__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_LEVEL))
+ {
+ /* PCCARD interrupt callback*/
+ HAL_PCCARD_ITCallback(hpccard);
+
+ /* Clear PCCARD interrupt Level pending bit */
+ __FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_LEVEL);
+ }
+
+ /* Check PCCARD interrupt Falling edge flag */
+ if(__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_FALLING_EDGE))
+ {
+ /* PCCARD interrupt callback*/
+ HAL_PCCARD_ITCallback(hpccard);
+
+ /* Clear PCCARD interrupt Falling edge pending bit */
+ __FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_FALLING_EDGE);
+ }
+
+ /* Check PCCARD interrupt FIFO empty flag */
+ if(__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_FEMPT))
+ {
+ /* PCCARD interrupt callback*/
+ HAL_PCCARD_ITCallback(hpccard);
+
+ /* Clear PCCARD interrupt FIFO empty pending bit */
+ __FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_FEMPT);
+ }
+
+}
+
+/**
+ * @brief PCCARD interrupt feature callback
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @retval None
+ */
+__weak void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpccard);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PCCARD_ITCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup PCCARD_Exported_Functions_Group3 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### PCCARD Peripheral State functions #####
+ ==============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the PCCARD controller
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief return the PCCARD controller state
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @retval HAL state
+ */
+HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard)
+{
+ return hpccard->State;
+}
+
+/**
+ * @brief Get the compact flash memory status
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @retval New status of the CF operation. This parameter can be:
+ * - CompactFlash_TIMEOUT_ERROR: when the previous operation generate
+ * a Timeout error
+ * - CompactFlash_READY: when memory is ready for the next operation
+ *
+ */
+HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard)
+{
+ uint32_t timeout = PCCARD_TIMEOUT_STATUS, status_cf = 0U;
+
+ /* Check the PCCARD controller state */
+ if(hpccard->State == HAL_PCCARD_STATE_BUSY)
+ {
+ return HAL_PCCARD_STATUS_ONGOING;
+ }
+
+ status_cf = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
+
+ while((status_cf == PCCARD_BUSY) && timeout)
+ {
+ status_cf = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
+ timeout--;
+ }
+
+ if(timeout == 0U)
+ {
+ status_cf = PCCARD_TIMEOUT_ERROR;
+ }
+
+ /* Return the operation status */
+ return (HAL_PCCARD_StatusTypeDef) status_cf;
+}
+
+/**
+ * @brief Reads the Compact Flash memory status using the Read status command
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @retval The status of the Compact Flash memory. This parameter can be:
+ * - CompactFlash_BUSY: when memory is busy
+ * - CompactFlash_READY: when memory is ready for the next operation
+ * - CompactFlash_ERROR: when the previous operation gererates error
+ */
+HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard)
+{
+ uint8_t data = 0U, status_cf = PCCARD_BUSY;
+
+ /* Check the PCCARD controller state */
+ if(hpccard->State == HAL_PCCARD_STATE_BUSY)
+ {
+ return HAL_PCCARD_STATUS_ONGOING;
+ }
+
+ /* Read status operation */
+ data = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
+
+ if((data & PCCARD_TIMEOUT_ERROR) == PCCARD_TIMEOUT_ERROR)
+ {
+ status_cf = PCCARD_TIMEOUT_ERROR;
+ }
+ else if((data & PCCARD_READY) == PCCARD_READY)
+ {
+ status_cf = PCCARD_READY;
+ }
+
+ return (HAL_PCCARD_StatusTypeDef) status_cf;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_pcd.c b/Src/stm32f3xx_hal_pcd.c
new file mode 100644
index 0000000..ccad29a
--- /dev/null
+++ b/Src/stm32f3xx_hal_pcd.c
@@ -0,0 +1,1336 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_pcd.c
+ * @author MCD Application Team
+ * @brief PCD HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the USB Peripheral Controller:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The PCD HAL driver can be used as follows:
+
+ (#) Declare a PCD_HandleTypeDef handle structure, for example:
+ PCD_HandleTypeDef hpcd;
+
+ (#) Fill parameters of Init structure in HCD handle
+
+ (#) Call HAL_PCD_Init() API to initialize the HCD peripheral (Core, Device core, ...)
+
+ (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
+ (##) Enable the PCD/USB Low Level interface clock using
+ (+++) __HAL_RCC_USB_CLK_ENABLE();
+
+ (##) Initialize the related GPIO clocks
+ (##) Configure PCD pin-out
+ (##) Configure PCD NVIC interrupt
+
+ (#)Associate the Upper USB device stack to the HAL PCD Driver:
+ (##) hpcd.pData = pdev;
+
+ (#)Enable HCD transmission and reception:
+ (##) HAL_PCD_Start();
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+#ifdef HAL_PCD_MODULE_ENABLED
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || \
+ defined(STM32F302x8) || \
+ defined(STM32F373xC)
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup PCD PCD
+ * @brief PCD HAL module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup PCD_Private_Define PCD Private Define
+ * @{
+ */
+#define BTABLE_ADDRESS (0x000U)
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup PCD_Private_Functions PCD Private Functions
+ * @{
+ */
+static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup PCD_Exported_Functions PCD Exported Functions
+ * @{
+ */
+
+/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the PCD according to the specified
+ * parameters in the PCD_InitTypeDef and create the associated handle.
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
+{
+ uint32_t i = 0U;
+
+ uint32_t wInterrupt_Mask = 0U;
+
+ /* Check the PCD handle allocation */
+ if(hpcd == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
+
+ if(hpcd->State == HAL_PCD_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hpcd->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+ HAL_PCD_MspInit(hpcd);
+ }
+
+ hpcd->State = HAL_PCD_STATE_BUSY;
+
+ /* Init endpoints structures */
+ for (i = 0U; i < hpcd->Init.dev_endpoints ; i++)
+ {
+ /* Init ep structure */
+ hpcd->IN_ep[i].is_in = 1U;
+ hpcd->IN_ep[i].num = i;
+ /* Control until ep is actvated */
+ hpcd->IN_ep[i].type = PCD_EP_TYPE_CTRL;
+ hpcd->IN_ep[i].maxpacket = 0U;
+ hpcd->IN_ep[i].xfer_buff = 0U;
+ hpcd->IN_ep[i].xfer_len = 0U;
+ }
+
+ for (i = 0U; i < hpcd->Init.dev_endpoints ; i++)
+ {
+ hpcd->OUT_ep[i].is_in = 0U;
+ hpcd->OUT_ep[i].num = i;
+ /* Control until ep is activated */
+ hpcd->OUT_ep[i].type = PCD_EP_TYPE_CTRL;
+ hpcd->OUT_ep[i].maxpacket = 0U;
+ hpcd->OUT_ep[i].xfer_buff = 0U;
+ hpcd->OUT_ep[i].xfer_len = 0U;
+ }
+
+ /* Init Device */
+ /*CNTR_FRES = 1U*/
+ hpcd->Instance->CNTR = USB_CNTR_FRES;
+
+ /*CNTR_FRES = 0U*/
+ hpcd->Instance->CNTR = 0U;
+
+ /*Clear pending interrupts*/
+ hpcd->Instance->ISTR = 0U;
+
+ /*Set Btable Adress*/
+ hpcd->Instance->BTABLE = BTABLE_ADDRESS;
+
+ /*set wInterrupt_Mask global variable*/
+ wInterrupt_Mask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \
+ | USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_RESETM;
+
+ /*Set interrupt mask*/
+ hpcd->Instance->CNTR = wInterrupt_Mask;
+
+ hpcd->USB_Address = 0U;
+ hpcd->State= HAL_PCD_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the PCD peripheral
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
+{
+ /* Check the PCD handle allocation */
+ if(hpcd == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ hpcd->State = HAL_PCD_STATE_BUSY;
+
+ /* Stop Device */
+ HAL_PCD_Stop(hpcd);
+
+ /* DeInit the low level hardware */
+ HAL_PCD_MspDeInit(hpcd);
+
+ hpcd->State = HAL_PCD_STATE_RESET;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the PCD MSP.
+ * @param hpcd PCD handle
+ * @retval None
+ */
+__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes PCD MSP.
+ * @param hpcd PCD handle
+ * @retval None
+ */
+__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup PCD_Exported_Functions_Group2 IO operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the PCD data
+ transfers.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Start the USB device.
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
+{
+ /* DP Pull-Down is external */
+ HAL_PCDEx_SetConnectionState (hpcd, 1U);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the USB device.
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
+{
+ __HAL_LOCK(hpcd);
+
+ /* disable all interrupts and force USB reset */
+ hpcd->Instance->CNTR = USB_CNTR_FRES;
+
+ /* clear interrupt status register */
+ hpcd->Instance->ISTR = 0U;
+
+ /* switch-off device */
+ hpcd->Instance->CNTR = (USB_CNTR_FRES | USB_CNTR_PDWN);
+
+ __HAL_UNLOCK(hpcd);
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup PCD_Private_Functions PCD Private Functions
+ * @{
+ */
+/**
+ * @brief This function handles PCD Endpoint interrupt request.
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
+{
+ PCD_EPTypeDef *ep;
+ uint16_t count=0U;
+ uint8_t EPindex;
+ __IO uint16_t wIstr;
+ __IO uint16_t wEPVal = 0U;
+
+ /* stay in loop while pending interrupts */
+ while (((wIstr = hpcd->Instance->ISTR) & USB_ISTR_CTR) != 0U)
+ {
+ /* extract highest priority endpoint number */
+ EPindex = (uint8_t)(wIstr & USB_ISTR_EP_ID);
+
+ if (EPindex == 0U)
+ {
+ /* Decode and service control endpoint interrupt */
+
+ /* DIR bit = origin of the interrupt */
+ if ((wIstr & USB_ISTR_DIR) == 0U)
+ {
+ /* DIR = 0U */
+
+ /* DIR = 0 => IN int */
+ /* DIR = 0 implies that (EP_CTR_TX = 1U) always */
+ PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0);
+ ep = &hpcd->IN_ep[0];
+
+ ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
+ ep->xfer_buff += ep->xfer_count;
+
+ /* TX COMPLETE */
+ HAL_PCD_DataInStageCallback(hpcd, 0U);
+
+
+ if((hpcd->USB_Address > 0U)&& ( ep->xfer_len == 0U))
+ {
+ hpcd->Instance->DADDR = (hpcd->USB_Address | USB_DADDR_EF);
+ hpcd->USB_Address = 0U;
+ }
+
+ }
+ else
+ {
+ /* DIR = 1U */
+
+ /* DIR = 1U & CTR_RX => SETUP or OUT int */
+ /* DIR = 1U & (CTR_TX | CTR_RX) => 2 int pending */
+ ep = &hpcd->OUT_ep[0];
+ wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
+
+ if ((wEPVal & USB_EP_SETUP) != 0U)
+ {
+ /* Get SETUP Packet*/
+ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
+ PCD_ReadPMA(hpcd->Instance, (uint8_t*)(void*)hpcd->Setup ,ep->pmaadress , ep->xfer_count);
+ /* SETUP bit kept frozen while CTR_RX = 1U*/
+ PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
+
+ /* Process SETUP Packet*/
+ HAL_PCD_SetupStageCallback(hpcd);
+ }
+
+ else if ((wEPVal & USB_EP_CTR_RX) != 0U)
+ {
+ PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
+ /* Get Control Data OUT Packet*/
+ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
+
+ if (ep->xfer_count != 0U)
+ {
+ PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count);
+ ep->xfer_buff+=ep->xfer_count;
+ }
+
+ /* Process Control Data OUT Packet*/
+ HAL_PCD_DataOutStageCallback(hpcd, 0U);
+
+ PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket)
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID)
+ }
+ }
+ }
+ else
+ {
+
+ /* Decode and service non control endpoints interrupt */
+
+ /* process related endpoint register */
+ wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, EPindex);
+ if ((wEPVal & USB_EP_CTR_RX) != 0U)
+ {
+ /* clear int flag */
+ PCD_CLEAR_RX_EP_CTR(hpcd->Instance, EPindex);
+ ep = &hpcd->OUT_ep[EPindex];
+
+ /* OUT double Buffering*/
+ if (ep->doublebuffer == 0U)
+ {
+ count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
+ if (count != 0U)
+ {
+ PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count);
+ }
+ }
+ else
+ {
+ if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_RX) == USB_EP_DTOG_RX)
+ {
+ /*read from endpoint BUF0Addr buffer*/
+ count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
+ if (count != 0U)
+ {
+ PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
+ }
+ }
+ else
+ {
+ /*read from endpoint BUF1Addr buffer*/
+ count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
+ if (count != 0U)
+ {
+ PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
+ }
+ }
+ PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_OUT)
+ }
+ /*multi-packet on the NON control OUT endpoint*/
+ ep->xfer_count+=count;
+ ep->xfer_buff+=count;
+
+ if ((ep->xfer_len == 0U) || (count < ep->maxpacket))
+ {
+ /* RX COMPLETE */
+ HAL_PCD_DataOutStageCallback(hpcd, ep->num);
+ }
+ else
+ {
+ HAL_PCD_EP_Receive(hpcd, ep->num, ep->xfer_buff, ep->xfer_len);
+ }
+
+ } /* if((wEPVal & EP_CTR_RX) */
+
+ if ((wEPVal & USB_EP_CTR_TX) != 0U)
+ {
+ ep = &hpcd->IN_ep[EPindex];
+
+ /* clear int flag */
+ PCD_CLEAR_TX_EP_CTR(hpcd->Instance, EPindex);
+
+ /* IN double Buffering*/
+ if (ep->doublebuffer == 0U)
+ {
+ ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
+ if (ep->xfer_count != 0U)
+ {
+ PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count);
+ }
+ }
+ else
+ {
+ if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_TX) == USB_EP_DTOG_TX)
+ {
+ /*read from endpoint BUF0Addr buffer*/
+ ep->xfer_count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
+ if (ep->xfer_count != 0U)
+ {
+ PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, ep->xfer_count);
+ }
+ }
+ else
+ {
+ /*read from endpoint BUF1Addr buffer*/
+ ep->xfer_count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
+ if (ep->xfer_count != 0U)
+ {
+ PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, ep->xfer_count);
+ }
+ }
+ PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_IN)
+ }
+ /*multi-packet on the NON control IN endpoint*/
+ ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
+ ep->xfer_buff+=ep->xfer_count;
+
+ /* Zero Length Packet? */
+ if (ep->xfer_len == 0U)
+ {
+ /* TX COMPLETE */
+ HAL_PCD_DataInStageCallback(hpcd, ep->num);
+ }
+ else
+ {
+ HAL_PCD_EP_Transmit(hpcd, ep->num, ep->xfer_buff, ep->xfer_len);
+ }
+ }
+ }
+ }
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+/** @addtogroup PCD_Exported_Functions
+ * @{
+ */
+
+/** @defgroup PCD_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+
+/**
+ * @brief This function handles PCD interrupt request.
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
+{
+
+ if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_CTR))
+ {
+ /* servicing of the endpoint correct transfer interrupt */
+ /* clear of the CTR flag into the sub */
+ PCD_EP_ISR_Handler(hpcd);
+ }
+
+ if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_RESET))
+ {
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET);
+ HAL_PCD_ResetCallback(hpcd);
+ HAL_PCD_SetAddress(hpcd, 0U);
+ }
+
+ if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_PMAOVR))
+ {
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR);
+ }
+ if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ERR))
+ {
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR);
+ }
+
+ if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP))
+ {
+ hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_LPMODE);
+ hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP);
+
+ HAL_PCD_ResumeCallback(hpcd);
+
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP);
+ }
+
+ if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SUSP))
+ {
+ /* Force low-power mode in the macrocell */
+ hpcd->Instance->CNTR |= USB_CNTR_FSUSP;
+
+ /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP);
+
+ hpcd->Instance->CNTR |= USB_CNTR_LPMODE;
+ if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP) == 0U)
+ {
+ HAL_PCD_SuspendCallback(hpcd);
+ }
+ }
+
+ if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SOF))
+ {
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF);
+ HAL_PCD_SOFCallback(hpcd);
+ }
+
+ if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ESOF))
+ {
+ /* clear ESOF flag in ISTR */
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF);
+ }
+}
+
+/**
+ * @brief Data out stage callbacks
+ * @param hpcd PCD handle
+ * @param epnum endpoint number
+ * @retval None
+ */
+ __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+ UNUSED(epnum);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_DataOutStageCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Data IN stage callbacks
+ * @param hpcd PCD handle
+ * @param epnum endpoint number
+ * @retval None
+ */
+ __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+ UNUSED(epnum);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_DataInStageCallback could be implemented in the user file
+ */
+}
+/**
+ * @brief Setup stage callback
+ * @param hpcd PCD handle
+ * @retval None
+ */
+ __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_SetupStageCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief USB Start Of Frame callbacks
+ * @param hpcd PCD handle
+ * @retval None
+ */
+ __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_SOFCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief USB Reset callbacks
+ * @param hpcd PCD handle
+ * @retval None
+ */
+ __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_ResetCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Suspend event callbacks
+ * @param hpcd PCD handle
+ * @retval None
+ */
+ __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_SuspendCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Resume event callbacks
+ * @param hpcd PCD handle
+ * @retval None
+ */
+ __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_ResumeCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Incomplete ISO OUT callbacks
+ * @param hpcd PCD handle
+ * @param epnum endpoint number
+ * @retval None
+ */
+ __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+ UNUSED(epnum);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Incomplete ISO IN callbacks
+ * @param hpcd PCD handle
+ * @param epnum endpoint number
+ * @retval None
+ */
+ __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+ UNUSED(epnum);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Connection event callbacks
+ * @param hpcd PCD handle
+ * @retval None
+ */
+ __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_ConnectCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Disconnection event callbacks
+ * @param hpcd PCD handle
+ * @retval None
+ */
+ __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_DisconnectCallback could be implemented in the user file
+ */
+}
+/**
+ * @}
+ */
+
+/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions
+ * @brief management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the PCD data
+ transfers.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Connect the USB device
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
+{
+ __HAL_LOCK(hpcd);
+
+ /* Enabling DP Pull-Down bit to Connect internal pull-up on USB DP line */
+ HAL_PCDEx_SetConnectionState(hpcd, 1U);
+
+ __HAL_UNLOCK(hpcd);
+ return HAL_OK;
+}
+
+/**
+ * @brief Disconnect the USB device
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
+{
+ __HAL_LOCK(hpcd);
+
+ /* Disable DP Pull-Down bit*/
+ HAL_PCDEx_SetConnectionState(hpcd, 0U);
+
+ __HAL_UNLOCK(hpcd);
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the USB Device address
+ * @param hpcd PCD handle
+ * @param address new device address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
+{
+ __HAL_LOCK(hpcd);
+
+ if(address == 0U)
+ {
+ /* set device address and enable function */
+ hpcd->Instance->DADDR = USB_DADDR_EF;
+ }
+ else /* USB Address will be applied later */
+ {
+ hpcd->USB_Address = address;
+ }
+
+ __HAL_UNLOCK(hpcd);
+ return HAL_OK;
+}
+/**
+ * @brief Open and configure an endpoint
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
+ * @param ep_mps endpoint max packet size
+ * @param ep_type endpoint type
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
+{
+ HAL_StatusTypeDef ret = HAL_OK;
+ PCD_EPTypeDef *ep;
+
+ if ((ep_addr & 0x80U) == 0x80U)
+ {
+ ep = &hpcd->IN_ep[ep_addr & 0x7FU];
+ }
+ else
+ {
+ ep = &hpcd->OUT_ep[ep_addr & 0x7FU];
+ }
+ ep->num = ep_addr & 0x7FU;
+
+ ep->is_in = (0x80U & ep_addr) != 0U;
+ ep->maxpacket = ep_mps;
+ ep->type = ep_type;
+
+ __HAL_LOCK(hpcd);
+
+ /* initialize Endpoint */
+ switch (ep->type)
+ {
+ case PCD_EP_TYPE_CTRL:
+ PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_CONTROL);
+ break;
+ case PCD_EP_TYPE_BULK:
+ PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_BULK);
+ break;
+ case PCD_EP_TYPE_INTR:
+ PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_INTERRUPT);
+ break;
+ case PCD_EP_TYPE_ISOC:
+ PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_ISOCHRONOUS);
+ break;
+ default:
+ break;
+ }
+
+ PCD_SET_EP_ADDRESS(hpcd->Instance, ep->num, ep->num);
+
+ if (ep->doublebuffer == 0U)
+ {
+ if (ep->is_in)
+ {
+ /*Set the endpoint Transmit buffer address */
+ PCD_SET_EP_TX_ADDRESS(hpcd->Instance, ep->num, ep->pmaadress);
+ PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
+ /* Configure NAK status for the Endpoint*/
+ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK)
+ }
+ else
+ {
+ /*Set the endpoint Receive buffer address */
+ PCD_SET_EP_RX_ADDRESS(hpcd->Instance, ep->num, ep->pmaadress);
+ /*Set the endpoint Receive buffer counter*/
+ PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, ep->maxpacket)
+ PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
+ /* Configure VALID status for the Endpoint*/
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID)
+ }
+ }
+ /*Double Buffer*/
+ else
+ {
+ /*Set the endpoint as double buffered*/
+ PCD_SET_EP_DBUF(hpcd->Instance, ep->num);
+ /*Set buffer address for double buffered mode*/
+ PCD_SET_EP_DBUF_ADDR(hpcd->Instance, ep->num,ep->pmaaddr0, ep->pmaaddr1)
+
+ if (ep->is_in==0U)
+ {
+ /* Clear the data toggle bits for the endpoint IN/OUT*/
+ PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
+ PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
+
+ /* Reset value of the data toggle bits for the endpoint out*/
+ PCD_TX_DTOG(hpcd->Instance, ep->num);
+
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID)
+ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS)
+ }
+ else
+ {
+ /* Clear the data toggle bits for the endpoint IN/OUT*/
+ PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
+ PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
+ PCD_RX_DTOG(hpcd->Instance, ep->num);
+ /* Configure DISABLE status for the Endpoint*/
+ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS)
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS)
+ }
+ }
+
+ __HAL_UNLOCK(hpcd);
+ return ret;
+}
+
+
+/**
+ * @brief Deactivate an endpoint
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+ PCD_EPTypeDef *ep;
+
+ if ((ep_addr & 0x80U) == 0x80U)
+ {
+ ep = &hpcd->IN_ep[ep_addr & 0x7F];
+ }
+ else
+ {
+ ep = &hpcd->OUT_ep[ep_addr & 0x7F];
+ }
+ ep->num = ep_addr & 0x7FU;
+
+ ep->is_in = (0x80U & ep_addr) != 0U;
+
+ __HAL_LOCK(hpcd);
+
+ if (ep->doublebuffer == 0U)
+ {
+ if (ep->is_in)
+ {
+ PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
+ /* Configure DISABLE status for the Endpoint*/
+ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS)
+ }
+ else
+ {
+ PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
+ /* Configure DISABLE status for the Endpoint*/
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS)
+ }
+ }
+ /*Double Buffer*/
+ else
+ {
+ if (ep->is_in==0U)
+ {
+ /* Clear the data toggle bits for the endpoint IN/OUT*/
+ PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
+ PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
+
+ /* Reset value of the data toggle bits for the endpoint out*/
+ PCD_TX_DTOG(hpcd->Instance, ep->num);
+
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS)
+ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS)
+ }
+ else
+ {
+ /* Clear the data toggle bits for the endpoint IN/OUT*/
+ PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
+ PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
+ PCD_RX_DTOG(hpcd->Instance, ep->num);
+ /* Configure DISABLE status for the Endpoint*/
+ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS)
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS)
+ }
+ }
+
+ __HAL_UNLOCK(hpcd);
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Receive an amount of data
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
+ * @param pBuf pointer to the reception buffer
+ * @param len amount of data to be received
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
+{
+
+ PCD_EPTypeDef *ep;
+
+ ep = &hpcd->OUT_ep[ep_addr & 0x7F];
+
+ /*setup and start the Xfer */
+ ep->xfer_buff = pBuf;
+ ep->xfer_len = len;
+ ep->xfer_count = 0U;
+ ep->is_in = 0U;
+ ep->num = ep_addr & 0x7FU;
+
+ /* Multi packet transfer*/
+ if (ep->xfer_len > ep->maxpacket)
+ {
+ len=ep->maxpacket;
+ ep->xfer_len-=len;
+ }
+ else
+ {
+ len=ep->xfer_len;
+ ep->xfer_len =0U;
+ }
+
+ /* configure and validate Rx endpoint */
+ if (ep->doublebuffer == 0U)
+ {
+ /*Set RX buffer count*/
+ PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, len)
+ }
+ else
+ {
+ /*Set the Double buffer counter*/
+ PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len)
+ }
+
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID)
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get Received Data Size
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
+ * @retval Data Size
+ */
+uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+ return hpcd->OUT_ep[ep_addr & 0x7F].xfer_count;
+}
+/**
+ * @brief Send an amount of data
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
+ * @param pBuf pointer to the transmission buffer
+ * @param len amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
+{
+ PCD_EPTypeDef *ep;
+ uint16_t pmabuffer = 0U;
+
+ ep = &hpcd->IN_ep[ep_addr & 0x7F];
+
+ /*setup and start the Xfer */
+ ep->xfer_buff = pBuf;
+ ep->xfer_len = len;
+ ep->xfer_count = 0U;
+ ep->is_in = 1U;
+ ep->num = ep_addr & 0x7FU;
+
+ /*Multi packet transfer*/
+ if (ep->xfer_len > ep->maxpacket)
+ {
+ len=ep->maxpacket;
+ ep->xfer_len-=len;
+ }
+ else
+ {
+ len=ep->xfer_len;
+ ep->xfer_len =0U;
+ }
+
+ /* configure and validate Tx endpoint */
+ if (ep->doublebuffer == 0U)
+ {
+ PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, len);
+ PCD_SET_EP_TX_CNT(hpcd->Instance, ep->num, len);
+ }
+ else
+ {
+ /*Write the data to the USB endpoint*/
+ if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_TX) == USB_EP_DTOG_TX)
+ {
+ pmabuffer = ep->pmaaddr1;
+ }
+ else
+ {
+ pmabuffer = ep->pmaaddr0;
+ }
+ PCD_WritePMA(hpcd->Instance, ep->xfer_buff, pmabuffer, len);
+ PCD_FreeUserBuffer(hpcd->Instance, ep->num, ep->is_in)
+ }
+
+ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID)
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set a STALL condition over an endpoint
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+ PCD_EPTypeDef *ep;
+
+ __HAL_LOCK(hpcd);
+
+ if ((0x80U & ep_addr) == 0x80U)
+ {
+ ep = &hpcd->IN_ep[ep_addr & 0x7F];
+ }
+ else
+ {
+ ep = &hpcd->OUT_ep[ep_addr];
+ }
+
+ ep->is_stall = 1U;
+ ep->num = ep_addr & 0x7FU;
+ ep->is_in = ((ep_addr & 0x80U) == 0x80U);
+
+ if (ep->num == 0U)
+ {
+ /* This macro sets STALL status for RX & TX*/
+ PCD_SET_EP_TXRX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_STALL, USB_EP_TX_STALL)
+ }
+ else
+ {
+ if (ep->is_in)
+ {
+ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num , USB_EP_TX_STALL)
+ }
+ else
+ {
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num , USB_EP_RX_STALL)
+ }
+ }
+ __HAL_UNLOCK(hpcd);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Clear a STALL condition over in an endpoint
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+ PCD_EPTypeDef *ep;
+
+ if ((0x80U & ep_addr) == 0x80U)
+ {
+ ep = &hpcd->IN_ep[ep_addr & 0x7F];
+ }
+ else
+ {
+ ep = &hpcd->OUT_ep[ep_addr];
+ }
+
+ ep->is_stall = 0U;
+ ep->num = ep_addr & 0x7FU;
+ ep->is_in = ((ep_addr & 0x80U) == 0x80U);
+
+ __HAL_LOCK(hpcd);
+
+ if (ep->is_in)
+ {
+ PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
+ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID)
+ }
+ else
+ {
+ PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID)
+ }
+ __HAL_UNLOCK(hpcd);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Flush an endpoint
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+ return HAL_OK;
+}
+
+/**
+ * @brief HAL_PCD_ActivateRemoteWakeup : active remote wakeup signalling
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
+{
+ hpcd->Instance->CNTR |= USB_CNTR_RESUME;
+ return HAL_OK;
+}
+
+/**
+ * @brief HAL_PCD_DeActivateRemoteWakeup : de-active remote wakeup signalling
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
+{
+ hpcd->Instance->CNTR &=~((uint32_t)USB_CNTR_RESUME);
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the PCD state
+ * @param hpcd PCD handle
+ * @retval HAL state
+ */
+PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
+{
+ return hpcd->State;
+}
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F302xE || STM32F303xE || */
+ /* STM32F302xC || STM32F303xC || */
+ /* STM32F302x8 || */
+ /* STM32F373xC */
+
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_pcd_ex.c b/Src/stm32f3xx_hal_pcd_ex.c
new file mode 100644
index 0000000..e2befbf
--- /dev/null
+++ b/Src/stm32f3xx_hal_pcd_ex.c
@@ -0,0 +1,327 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_pcd_ex.c
+ * @author MCD Application Team
+ * @brief Extended PCD HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the USB Peripheral Controller:
+ * + Configuration of the PMA for EP
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+#ifdef HAL_PCD_MODULE_ENABLED
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || \
+ defined(STM32F302x8) || \
+ defined(STM32F373xC)
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup PCDEx PCDEx
+ * @brief PCD Extended HAL module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
+ * @{
+ */
+
+/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
+ * @brief PCDEx control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Update PMA configuration
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure PMA for EP
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
+ * @param ep_kind endpoint Kind
+ * @arg USB_SNG_BUF: Single Buffer used
+ * @arg USB_DBL_BUF: Double Buffer used
+ * @param pmaadress EP address in The PMA: In case of single buffer endpoint
+ * this parameter is 16-bit value providing the address
+ * in PMA allocated to endpoint.
+ * In case of double buffer endpoint this parameter
+ * is a 32-bit value providing the endpoint buffer 0 address
+ * in the LSB part of 32-bit value and endpoint buffer 1 address
+ * in the MSB part of 32-bit value.
+ * @retval : status
+ */
+
+HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
+ uint16_t ep_addr,
+ uint16_t ep_kind,
+ uint32_t pmaadress)
+
+{
+ PCD_EPTypeDef *ep;
+
+ /* initialize ep structure*/
+ if ((0x80U & ep_addr) == 0x80U)
+ {
+ ep = &hpcd->IN_ep[ep_addr & 0x7FU];
+ }
+ else
+ {
+ ep = &hpcd->OUT_ep[ep_addr];
+ }
+
+ /* Here we check if the endpoint is single or double Buffer*/
+ if (ep_kind == PCD_SNG_BUF)
+ {
+ /*Single Buffer*/
+ ep->doublebuffer = 0U;
+ /*Configure the PMA*/
+ ep->pmaadress = (uint16_t)pmaadress;
+ }
+ else /*USB_DBL_BUF*/
+ {
+ /*Double Buffer Endpoint*/
+ ep->doublebuffer = 1;
+ /*Configure the PMA*/
+ ep->pmaaddr0 = pmaadress & 0xFFFFU;
+ ep->pmaaddr1 = (pmaadress & 0xFFFF0000U) >> 16U;
+ }
+
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup PCDEx_Private_Functions PCD Extended Private Functions
+ * @{
+ */
+#if defined(STM32F303xC) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || \
+ defined(STM32F301x8) || \
+ defined(STM32F373xC) || defined(STM32F378xx) || \
+ defined(STM32F302xC)
+
+/**
+ * @brief Copy a buffer from user memory area to packet memory area (PMA)
+ * @param USBx: USB peripheral instance register address.
+ * @param pbUsrBuf: pointer to user memory area.
+ * @param wPMABufAddr: address into PMA.
+ * @param wNBytes: no. of bytes to be copied.
+ * @retval None
+ */
+void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
+{
+ uint32_t n = ((uint32_t)((uint32_t)wNBytes + 1U)) >> 1U;
+
+ uint32_t i, temp1, temp2;
+ uint16_t *pdwVal;
+ pdwVal = (uint16_t *)((uint32_t)(wPMABufAddr * 2 + (uint32_t)USBx + 0x400U));
+
+ for (i = n; i != 0; i--)
+ {
+ temp1 = (uint16_t) * pbUsrBuf;
+ pbUsrBuf++;
+ temp2 = temp1 | ((uint16_t)((uint16_t) * pbUsrBuf << 8U)) ;
+ *pdwVal++ = temp2;
+ pdwVal++;
+ pbUsrBuf++;
+ }
+}
+
+/**
+ * @brief Copy a buffer from user memory area to packet memory area (PMA)
+ * @param USBx: USB peripheral instance register address.
+ * @param pbUsrBuf: pointer to user memory area.
+ * @param wPMABufAddr: address into PMA.
+ * @param wNBytes: no. of bytes to be copied.
+ * @retval None
+ */
+void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
+{
+ uint32_t n = (uint32_t)wNBytes >> 1U;
+ uint32_t i;
+ uint16_t *pdwVal;
+ uint32_t temp;
+ pdwVal = (uint16_t *)((uint32_t)(wPMABufAddr * 2 + (uint32_t)USBx + 0x400U));
+
+ for (i = n; i != 0U; i--)
+ {
+ temp = *pdwVal++;
+ *pbUsrBuf++ = ((temp >> 0) & 0xFF);
+ *pbUsrBuf++ = ((temp >> 8) & 0xFF);
+ pdwVal++;
+ }
+
+ if (wNBytes % 2)
+ {
+ temp = *pdwVal++;
+ *pbUsrBuf++ = ((temp >> 0) & 0xFF);
+ }
+}
+#endif /* STM32F303xC || */
+ /* STM32F303x8 || STM32F334x8 || */
+ /* STM32F301x8 || */
+ /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || \
+ defined(STM32F302x8)
+/**
+ * @brief Copy a buffer from user memory area to packet memory area (PMA)
+ * @param USBx: USB peripheral instance register address.
+ * @param pbUsrBuf: pointer to user memory area.
+ * @param wPMABufAddr: address into PMA.
+ * @param wNBytes: no. of bytes to be copied.
+ * @retval None
+ */
+void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
+{
+ uint32_t n = ((uint32_t)((uint32_t)wNBytes + 1U)) >> 1U;
+ uint32_t i;
+ uint16_t temp1, temp2;
+ uint16_t *pdwVal;
+ pdwVal = (uint16_t *)((uint32_t)(wPMABufAddr + (uint32_t)USBx + 0x400U));
+ for (i = n; i != 0U; i--)
+ {
+ temp1 = (uint16_t) * pbUsrBuf;
+ pbUsrBuf++;
+ temp2 = temp1 | ((uint16_t)((uint16_t) * pbUsrBuf << 8U)) ;
+ *pdwVal++ = temp2;
+ pbUsrBuf++;
+ }
+}
+
+/**
+ * @brief Copy a buffer from user memory area to packet memory area (PMA)
+ * @param USBx: USB peripheral instance register address.
+ * @param pbUsrBuf: pointer to user memory area.
+ * @param wPMABufAddr: address into PMA.
+ * @param wNBytes: no. of bytes to be copied.
+ * @retval None
+ */
+void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
+{
+ uint32_t n = (uint32_t)wNBytes >> 1U;
+ uint32_t i;
+ uint16_t *pdwVal;
+ uint32_t temp;
+ pdwVal = (uint16_t *)((uint32_t)(wPMABufAddr + (uint32_t)USBx + 0x400U));
+
+ for (i = n; i != 0U; i--)
+ {
+ temp = *pdwVal++;
+ *pbUsrBuf++ = ((temp >> 0) & 0xFF);
+ *pbUsrBuf++ = ((temp >> 8) & 0xFF);
+ }
+
+ if (wNBytes % 2)
+ {
+ temp = *pdwVal++;
+ *pbUsrBuf++ = ((temp >> 0) & 0xFF);
+ }
+}
+#endif /* STM32F302xE || STM32F303xE || */
+ /* STM32F302xC || */
+ /* STM32F302x8 */
+
+/**
+ * @}
+ */
+
+/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
+ * @{
+ */
+
+/** @addtogroup PCDEx_Exported_Functions_Group2 Extended Initialization and de-initialization functions
+ * @{
+ */
+/**
+ * @brief Software Device Connection
+ * @param hpcd PCD handle
+ * @param state Device state
+ * @retval None
+ */
+ __weak void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+ UNUSED(state);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PCDEx_SetConnectionState could be implenetd in the user file
+ */
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F302xE || STM32F303xE || */
+ /* STM32F302xC || STM32F303xC || */
+ /* STM32F302x8 || */
+ /* STM32F373xC */
+
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_pwr.c b/Src/stm32f3xx_hal_pwr.c
new file mode 100644
index 0000000..55c49a7
--- /dev/null
+++ b/Src/stm32f3xx_hal_pwr.c
@@ -0,0 +1,477 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_pwr.c
+ * @author MCD Application Team
+ * @brief PWR HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Power Controller (PWR) peripheral:
+ * + Initialization/de-initialization functions
+ * + Peripheral Control functions
+ *
+ @verbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup PWR PWR
+ * @brief PWR HAL module driver
+ * @{
+ */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Functions PWR Exported Functions
+ * @{
+ */
+
+/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and de-initialization functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..]
+ After reset, the backup domain (RTC registers, RTC backup data
+ registers and backup SRAM) is protected against possible unwanted
+ write accesses.
+ To enable access to the RTC Domain and RTC registers, proceed as follows:
+ (+) Enable the Power Controller (PWR) APB1 interface clock using the
+ __HAL_RCC_PWR_CLK_ENABLE() macro.
+ (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the PWR peripheral registers to their default reset values.
+ * @retval None
+ */
+void HAL_PWR_DeInit(void)
+{
+ __HAL_RCC_PWR_FORCE_RESET();
+ __HAL_RCC_PWR_RELEASE_RESET();
+}
+
+/**
+ * @brief Enables access to the backup domain (RTC registers, RTC
+ * backup data registers and backup SRAM).
+ * @note If the HSE divided by 32 is used as the RTC clock, the
+ * Backup Domain Access should be kept enabled.
+ * @retval None
+ */
+void HAL_PWR_EnableBkUpAccess(void)
+{
+ SET_BIT(PWR->CR, PWR_CR_DBP);
+}
+
+/**
+ * @brief Disables access to the backup domain (RTC registers, RTC
+ * backup data registers and backup SRAM).
+ * @note If the HSE divided by 32 is used as the RTC clock, the
+ * Backup Domain Access should be kept enabled.
+ * @retval None
+ */
+void HAL_PWR_DisableBkUpAccess(void)
+{
+ CLEAR_BIT(PWR->CR, PWR_CR_DBP);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
+ * @brief Low Power modes configuration functions
+ *
+@verbatim
+
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+
+ *** WakeUp pin configuration ***
+ ================================
+ [..]
+ (+) WakeUp pin is used to wakeup the system from Standby mode. This pin is
+ forced in input pull down configuration and is active on rising edges.
+ (+) There are up to three WakeUp pins:
+ (++)WakeUp Pin 1 on PA.00.
+ (++)WakeUp Pin 2 on PC.13 (STM32F303xC, STM32F303xE only).
+ (++)WakeUp Pin 3 on PE.06.
+
+ *** Main and Backup Regulators configuration ***
+ ================================================
+ [..]
+ (+) When the backup domain is supplied by VDD (analog switch connected to VDD)
+ the backup SRAM is powered from VDD which replaces the VBAT power supply to
+ save battery life.
+
+ (+) The backup SRAM is not mass erased by a tamper event. It is read
+ protected to prevent confidential data, such as cryptographic private
+ key, from being accessed. The backup SRAM can be erased only through
+ the Flash interface when a protection level change from level 1 to
+ level 0 is requested.
+ -@- Refer to the description of Read protection (RDP) in the Flash
+ programming manual.
+
+ Refer to the datasheets for more details.
+
+ *** Low Power modes configuration ***
+ =====================================
+ [..]
+ The devices feature 3 low-power modes:
+ (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running.
+ (+) Stop mode: all clocks are stopped, regulator running, regulator
+ in low power mode
+ (+) Standby mode: 1.2V domain powered off (mode not available on STM32F3x8 devices).
+
+ *** Sleep mode ***
+ ==================
+ [..]
+ (+) Entry:
+ The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx)
+ functions with
+ (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
+ (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
+
+ (+) Exit:
+ (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
+ controller (NVIC) can wake up the device from Sleep mode.
+
+ *** Stop mode ***
+ =================
+ [..]
+ In Stop mode, all clocks in the 1.8V domain are stopped, the PLL, the HSI,
+ and the HSE RC oscillators are disabled. Internal SRAM and register contents
+ are preserved.
+ The voltage regulator can be configured either in normal or low-power mode to minimize the consumption.
+
+ (+) Entry:
+ The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_STOPENTRY_WFI )
+ function with:
+ (++) Main regulator ON or
+ (++) Low Power regulator ON.
+ (++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction or
+ (++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction
+ (+) Exit:
+ (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
+ (++) Some specific communication peripherals (CEC, USART, I2C) interrupts,
+ when programmed in wakeup mode (the peripheral must be
+ programmed in wakeup mode and the corresponding interrupt vector
+ must be enabled in the NVIC).
+
+ *** Standby mode ***
+ ====================
+ [..]
+ The Standby mode allows to achieve the lowest power consumption. It is based
+ on the Cortex-M4 deep sleep mode, with the voltage regulator disabled.
+ The 1.8V domain is consequently powered off. The PLL, the HSI oscillator and
+ the HSE oscillator are also switched off. SRAM and register contents are lost
+ except for the RTC registers, RTC backup registers, backup SRAM and Standby
+ circuitry.
+ The voltage regulator is OFF.
+
+ (+) Entry:
+ (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
+ (+) Exit:
+ (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
+ tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
+
+ *** Auto-wakeup (AWU) from low-power mode ***
+ =============================================
+ [..]
+ The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
+ Wakeup event, a tamper event, a time-stamp event, or a comparator event,
+ without depending on an external interrupt (Auto-wakeup mode).
+
+ (+) RTC auto-wakeup (AWU) from the Stop and Standby modes
+
+ (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
+ configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
+
+ (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
+ is necessary to configure the RTC to detect the tamper or time stamp event using the
+ HAL_RTC_SetTimeStamp_IT() or HAL_RTC_SetTamper_IT() functions.
+
+ (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
+ configure the RTC to generate the RTC WakeUp event using the HAL_RTC_SetWakeUpTimer_IT() function.
+
+ (+) Comparator auto-wakeup (AWU) from the Stop mode
+
+ (++) To wake up from the Stop mode with a comparator wakeup event, it is necessary to:
+ (+++) Configure the EXTI Line associated with the comparator (example EXTI Line 22 for comparator 2U)
+ to be sensitive to to the selected edges (falling, rising or falling
+ and rising) (Interrupt or Event modes) using the EXTI_Init() function.
+ (+++) Configure the comparator to generate the event.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables the WakeUp PINx functionality.
+ * @param WakeUpPinx Specifies the Power Wake-Up pin to enable.
+ * This parameter can be value of :
+ * @ref PWR_WakeUp_Pins
+ * @retval None
+ */
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
+ /* Enable the EWUPx pin */
+ SET_BIT(PWR->CSR, WakeUpPinx);
+}
+
+/**
+ * @brief Disables the WakeUp PINx functionality.
+ * @param WakeUpPinx Specifies the Power Wake-Up pin to disable.
+ * This parameter can be values of :
+ * @ref PWR_WakeUp_Pins
+ * @retval None
+ */
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
+ /* Disable the EWUPx pin */
+ CLEAR_BIT(PWR->CSR, WakeUpPinx);
+}
+
+/**
+ * @brief Enters Sleep mode.
+ * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
+ * @param Regulator Specifies the regulator state in SLEEP mode.
+ * This parameter can be one of the following values:
+ * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
+ * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
+ * @note This parameter has no effect in F3 family and is just maintained to
+ * offer full portability of other STM32 families softwares.
+ * @param SLEEPEntry Specifies if SLEEP mode is entered with WFI or WFE instruction.
+ * When WFI entry is used, tick interrupt have to be disabled if not desired as
+ * the interrupt wake up source.
+ * This parameter can be one of the following values:
+ * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
+ * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
+ * @retval None
+ */
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
+
+ /* Clear SLEEPDEEP bit of Cortex System Control Register */
+ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
+
+ /* Select SLEEP mode entry -------------------------------------------------*/
+ if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
+ {
+ /* Request Wait For Interrupt */
+ __WFI();
+ }
+ else
+ {
+ /* Request Wait For Event */
+ __SEV();
+ __WFE();
+ __WFE();
+ }
+}
+
+/**
+ * @brief Enters STOP mode.
+ * @note In Stop mode, all I/O pins keep the same state as in Run mode.
+ * @note When exiting Stop mode by issuing an interrupt or a wakeup event,
+ * the HSI RC oscillator is selected as system clock.
+ * @note When the voltage regulator operates in low power mode, an additional
+ * startup delay is incurred when waking up from Stop mode.
+ * By keeping the internal regulator ON during Stop mode, the consumption
+ * is higher although the startup time is reduced.
+ * @param Regulator Specifies the regulator state in STOP mode.
+ * This parameter can be one of the following values:
+ * @arg PWR_MAINREGULATOR_ON: STOP mode with regulator ON
+ * @arg PWR_LOWPOWERREGULATOR_ON: STOP mode with low power regulator ON
+ * @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction.
+ * This parameter can be one of the following values:
+ * @arg PWR_STOPENTRY_WFI:Enter STOP mode with WFI instruction
+ * @arg PWR_STOPENTRY_WFE: Enter STOP mode with WFE instruction
+ * @retval None
+ */
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
+{
+ uint32_t tmpreg = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_PWR_REGULATOR(Regulator));
+ assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
+
+ /* Select the regulator state in STOP mode ---------------------------------*/
+ tmpreg = PWR->CR;
+
+ /* Clear PDDS and LPDS bits */
+ tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS);
+
+ /* Set LPDS bit according to Regulator value */
+ tmpreg |= Regulator;
+
+ /* Store the new value */
+ PWR->CR = tmpreg;
+
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+ /* Select STOP mode entry --------------------------------------------------*/
+ if(STOPEntry == PWR_STOPENTRY_WFI)
+ {
+ /* Request Wait For Interrupt */
+ __WFI();
+ }
+ else
+ {
+ /* Request Wait For Event */
+ __SEV();
+ __WFE();
+ __WFE();
+ }
+
+ /* Reset SLEEPDEEP bit of Cortex System Control Register */
+ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
+}
+
+/**
+ * @brief Enters STANDBY mode.
+ * @note In Standby mode, all I/O pins are high impedance except for:
+ * - Reset pad (still available),
+ * - RTC alternate function pins if configured for tamper, time-stamp, RTC
+ * Alarm out, or RTC clock calibration out,
+ * - WKUP pins if enabled.
+ * @retval None
+ */
+void HAL_PWR_EnterSTANDBYMode(void)
+{
+ /* Select STANDBY mode */
+ PWR->CR |= PWR_CR_PDDS;
+
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+ /* This option is used to ensure that store operations are completed */
+#if defined ( __CC_ARM)
+ __force_stores();
+#endif
+ /* Request Wait For Interrupt */
+ __WFI();
+}
+
+/**
+ * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
+ * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
+ * re-enters SLEEP mode when an interruption handling is over.
+ * Setting this bit is useful when the processor is expected to run only on
+ * interruptions handling.
+ * @retval None
+ */
+void HAL_PWR_EnableSleepOnExit(void)
+{
+ /* Set SLEEPONEXIT bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+
+/**
+ * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
+ * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
+ * re-enters SLEEP mode when an interruption handling is over.
+ * @retval None
+ */
+void HAL_PWR_DisableSleepOnExit(void)
+{
+ /* Clear SLEEPONEXIT bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+
+
+/**
+ * @brief Enables CORTEX M4 SEVONPEND bit.
+ * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
+ * WFE to wake up when an interrupt moves from inactive to pended.
+ * @retval None
+ */
+void HAL_PWR_EnableSEVOnPend(void)
+{
+ /* Set SEVONPEND bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+
+/**
+ * @brief Disables CORTEX M4 SEVONPEND bit.
+ * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
+ * WFE to wake up when an interrupt moves from inactive to pended.
+ * @retval None
+ */
+void HAL_PWR_DisableSEVOnPend(void)
+{
+ /* Clear SEVONPEND bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_PWR_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_pwr_ex.c b/Src/stm32f3xx_hal_pwr_ex.c
new file mode 100644
index 0000000..ef5db43
--- /dev/null
+++ b/Src/stm32f3xx_hal_pwr_ex.c
@@ -0,0 +1,288 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_pwr_ex.c
+ * @author MCD Application Team
+ * @brief Extended PWR HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Power Controller (PWR) peripheral:
+ * + Extended Initialization and de-initialization functions
+ * + Extended Peripheral Control functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup PWREx PWREx
+ * @brief PWREx HAL module driver
+ * @{
+ */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup PWREx_Private_Constants PWR Extended Private Constants
+ * @{
+ */
+#define PVD_MODE_IT (0x00010000U)
+#define PVD_MODE_EVT (0x00020000U)
+#define PVD_RISING_EDGE (0x00000001U)
+#define PVD_FALLING_EDGE (0x00000002U)
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions
+ * @{
+ */
+
+/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended Control Functions
+ * @brief Extended Peripheral Control functions
+ *
+@verbatim
+
+ ===============================================================================
+ ##### Peripheral Extended control functions #####
+ ===============================================================================
+ *** PVD configuration (present on all other devices than STM32F3x8 devices) ***
+ =========================
+ [..]
+ (+) The PVD is used to monitor the VDD power supply by comparing it to a
+ threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
+ (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
+ than the PVD threshold. This event is internally connected to the EXTI
+ line16 and can generate an interrupt if enabled. This is done through
+ __HAL_PWR_PVD_EXTI_ENABLE_IT() macro
+ (+) The PVD is stopped in Standby mode.
+ -@- PVD is not available on STM32F3x8 Product Line
+
+
+ *** Voltage regulator ***
+ =========================
+ [..]
+ (+) The voltage regulator is always enabled after Reset. It works in three different
+ modes.
+ In Run mode, the regulator supplies full power to the 1.8V domain (core, memories
+ and digital peripherals).
+ In Stop mode, the regulator supplies low power to the 1.8V domain, preserving
+ contents of registers and SRAM.
+ In Stop mode, the regulator is powered off. The contents of the registers and SRAM
+ are lost except for the Standby circuitry and the Backup Domain.
+ Note: in the STM32F3x8xx devices, the voltage regulator is bypassed and the
+ microcontroller must be powered from a nominal VDD = 1.8V +/-8U% voltage.
+
+
+ (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
+ than the PVD threshold. This event is internally connected to the EXTI
+ line16 and can generate an interrupt if enabled. This is done through
+ __HAL_PWR_PVD_EXTI_ENABLE_IT() macro
+ (+) The PVD is stopped in Standby mode.
+
+
+ *** SDADC power configuration ***
+ ================================
+ [..]
+ (+) On STM32F373xC/STM32F378xx devices, there are up to
+ 3 SDADC instances that can be enabled/disabled.
+
+@endverbatim
+ * @{
+ */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || \
+ defined(STM32F373xC)
+
+/**
+ * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
+ * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration
+ * information for the PVD.
+ * @note Refer to the electrical characteristics of your device datasheet for
+ * more details about the voltage threshold corresponding to each
+ * detection level.
+ * @retval None
+ */
+void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
+ assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
+
+ /* Set PLS[7:5] bits according to PVDLevel value */
+ MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
+
+ /* Clear any previous config. Keep it clear if no event or IT mode is selected */
+ __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
+ __HAL_PWR_PVD_EXTI_DISABLE_IT();
+ __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
+
+ /* Configure interrupt mode */
+ if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
+ {
+ __HAL_PWR_PVD_EXTI_ENABLE_IT();
+ }
+
+ /* Configure event mode */
+ if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
+ {
+ __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
+ }
+
+ /* Configure the edge */
+ if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
+ {
+ __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
+ }
+
+ if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
+ {
+ __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
+ }
+}
+
+/**
+ * @brief Enables the Power Voltage Detector(PVD).
+ * @retval None
+ */
+void HAL_PWR_EnablePVD(void)
+{
+ SET_BIT(PWR->CR, PWR_CR_PVDE);
+}
+
+/**
+ * @brief Disables the Power Voltage Detector(PVD).
+ * @retval None
+ */
+void HAL_PWR_DisablePVD(void)
+{
+ CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
+}
+
+/**
+ * @brief This function handles the PWR PVD interrupt request.
+ * @note This API should be called under the PVD_IRQHandler().
+ * @retval None
+ */
+void HAL_PWR_PVD_IRQHandler(void)
+{
+ /* Check PWR exti flag */
+ if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
+ {
+ /* PWR PVD interrupt user callback */
+ HAL_PWR_PVDCallback();
+
+ /* Clear PWR Exti pending bit */
+ __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
+ }
+}
+
+/**
+ * @brief PWR PVD interrupt callback
+ * @retval None
+ */
+__weak void HAL_PWR_PVDCallback(void)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PWR_PVDCallback could be implemented in the user file
+ */
+}
+
+#endif /* STM32F302xE || STM32F303xE || */
+ /* STM32F302xC || STM32F303xC || */
+ /* STM32F303x8 || STM32F334x8 || */
+ /* STM32F301x8 || STM32F302x8 || */
+ /* STM32F373xC */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+
+/**
+ * @brief Enables the SDADC peripheral functionaliy
+ * @param Analogx specifies the SDADC peripheral instance.
+ * This parameter can be: PWR_SDADC_ANALOG1, PWR_SDADC_ANALOG2 or PWR_SDADC_ANALOG3.
+ * @retval None
+ */
+void HAL_PWREx_EnableSDADC(uint32_t Analogx)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_SDADC_ANALOG(Analogx));
+
+ /* Enable PWR clock interface for SDADC use */
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ PWR->CR |= Analogx;
+}
+
+/**
+ * @brief Disables the SDADC peripheral functionaliy
+ * @param Analogx specifies the SDADC peripheral instance.
+ * This parameter can be: PWR_SDADC_ANALOG1, PWR_SDADC_ANALOG2 or PWR_SDADC_ANALOG3.
+ * @retval None
+ */
+void HAL_PWREx_DisableSDADC(uint32_t Analogx)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_SDADC_ANALOG(Analogx));
+
+ PWR->CR &= ~Analogx;
+}
+
+#endif /* STM32F373xC || STM32F378xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_PWR_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_rcc.c b/Src/stm32f3xx_hal_rcc.c
new file mode 100644
index 0000000..382b234
--- /dev/null
+++ b/Src/stm32f3xx_hal_rcc.c
@@ -0,0 +1,1215 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_rcc.c
+ * @author MCD Application Team
+ * @brief RCC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Reset and Clock Control (RCC) peripheral:
+ * + Initialization and de-initialization functions
+ * + Peripheral Control functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### RCC specific features #####
+ ==============================================================================
+ [..]
+ After reset the device is running from Internal High Speed oscillator
+ (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled,
+ and all peripherals are off except internal SRAM, Flash and JTAG.
+ (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses;
+ all peripherals mapped on these buses are running at HSI speed.
+ (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
+ (+) All GPIOs are in input floating state, except the JTAG pins which
+ are assigned to be used for debug purpose.
+ [..] Once the device started from reset, the user application has to:
+ (+) Configure the clock source to be used to drive the System clock
+ (if the application needs higher frequency/performance)
+ (+) Configure the System clock frequency and Flash settings
+ (+) Configure the AHB and APB buses prescalers
+ (+) Enable the clock for the peripheral(s) to be used
+ (+) Configure the clock source(s) for peripherals whose clocks are not
+ derived from the System clock (RTC, ADC, I2C, I2S, TIM, USB FS)
+
+ ##### RCC Limitations #####
+ ==============================================================================
+ [..]
+ A delay between an RCC peripheral clock enable and the effective peripheral
+ enabling should be taken into account in order to manage the peripheral read/write
+ from/to registers.
+ (+) This delay depends on the peripheral mapping.
+ (++) AHB & APB peripherals, 1 dummy read is necessary
+
+ [..]
+ Workarounds:
+ (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
+ inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup RCC RCC
+* @brief RCC HAL module driver
+ * @{
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup RCC_Private_Constants RCC Private Constants
+ * @{
+ */
+/* Bits position in in the CFGR register */
+#define RCC_CFGR_HPRE_BITNUMBER POSITION_VAL(RCC_CFGR_HPRE)
+#define RCC_CFGR_PPRE1_BITNUMBER POSITION_VAL(RCC_CFGR_PPRE1)
+#define RCC_CFGR_PPRE2_BITNUMBER POSITION_VAL(RCC_CFGR_PPRE2)
+/**
+ * @}
+ */
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup RCC_Private_Macros RCC Private Macros
+ * @{
+ */
+
+#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
+#define MCO1_GPIO_PORT GPIOA
+#define MCO1_PIN GPIO_PIN_8
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup RCC_Private_Variables RCC Private Variables
+ * @{
+ */
+const uint8_t aPLLMULFactorTable[16] = { 2U, 3U, 4U, 5U, 6U, 7U, 8U, 9U,
+ 10U, 11U, 12U, 13U, 14U, 15U, 16U, 16U};
+const uint8_t aPredivFactorTable[16] = { 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U,
+ 9U,10U, 11U, 12U, 13U, 14U, 15U, 16U};
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Functions RCC Exported Functions
+ * @{
+ */
+
+/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+ @verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..]
+ This section provides functions allowing to configure the internal/external oscillators
+ (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1
+ and APB2).
+
+ [..] Internal/external clock and PLL configuration
+ (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through
+ the PLL as System clock source.
+ The HSI clock can be used also to clock the USART and I2C peripherals.
+
+ (#) LSI (low-speed internal), ~40 KHz low consumption RC used as IWDG and/or RTC
+ clock source.
+
+ (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or
+ through the PLL as System clock source. Can be used also as RTC clock source.
+
+ (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
+
+ (#) PLL (clocked by HSI or HSE), featuring different output clocks:
+ (++) The first output is used to generate the high speed system clock (up to 72 MHz)
+ (++) The second output is used to generate the clock for the USB FS (48 MHz)
+ (++) The third output may be used to generate the clock for the ADC peripherals (up to 72 MHz)
+ (++) The fourth output may be used to generate the clock for the TIM peripherals (144 MHz)
+
+ (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
+ and if a HSE clock failure occurs(HSE used directly or through PLL as System
+ clock source), the System clocks automatically switched to HSI and an interrupt
+ is generated if enabled. The interrupt is linked to the Cortex-M4 NMI
+ (Non-Maskable Interrupt) exception vector.
+
+ (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSE, LSI, LSE or PLL
+ clock (divided by 2) output on pin (such as PA8 pin).
+
+ [..] System, AHB and APB buses clocks configuration
+ (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
+ HSE and PLL.
+ The AHB clock (HCLK) is derived from System clock through configurable
+ prescaler and used to clock the CPU, memory and peripherals mapped
+ on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
+ from AHB clock through configurable prescalers and used to clock
+ the peripherals mapped on these buses. You can use
+ "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
+
+ (#) All the peripheral clocks are derived from the System clock (SYSCLK) except:
+ (++) The FLASH program/erase clock which is always HSI 8MHz clock.
+ (++) The USB 48 MHz clock which is derived from the PLL VCO clock.
+ (++) The USART clock which can be derived as well from HSI 8MHz, LSI or LSE.
+ (++) The I2C clock which can be derived as well from HSI 8MHz clock.
+ (++) The ADC clock which is derived from PLL output.
+ (++) The RTC clock which is derived from the LSE, LSI or 1 MHz HSE_RTC
+ (HSE divided by a programmable prescaler). The System clock (SYSCLK)
+ frequency must be higher or equal to the RTC clock frequency.
+ (++) IWDG clock which is always the LSI clock.
+
+ (#) For the STM32F3xx devices, the maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 72 MHz,
+ Depending on the SYSCLK frequency, the flash latency should be adapted accordingly.
+
+ (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and
+ prefetch is disabled.
+ @endverbatim
+ * @{
+ */
+
+/*
+ Additional consideration on the SYSCLK based on Latency settings:
+ +-----------------------------------------------+
+ | Latency | SYSCLK clock frequency (MHz) |
+ |---------------|-------------------------------|
+ |0WS(1CPU cycle)| 0 < SYSCLK <= 24 |
+ |---------------|-------------------------------|
+ |1WS(2CPU cycle)| 24 < SYSCLK <= 48 |
+ |---------------|-------------------------------|
+ |2WS(3CPU cycle)| 48 < SYSCLK <= 72 |
+ +-----------------------------------------------+
+ */
+
+/**
+ * @brief Resets the RCC clock configuration to the default reset state.
+ * @note The default reset state of the clock configuration is given below:
+ * - HSI ON and used as system clock source
+ * - HSE and PLL OFF
+ * - AHB, APB1 and APB2 prescaler set to 1.
+ * - CSS and MCO1 OFF
+ * - All interrupts disabled
+ * @note This function does not modify the configuration of the
+ * - Peripheral clocks
+ * - LSI, LSE and RTC clocks
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCC_DeInit(void)
+{
+ uint32_t tickstart = 0;
+
+ /* Set HSION bit */
+ SET_BIT(RCC->CR, RCC_CR_HSION);
+
+ /* Insure HSIRDY bit is set before writing default HSITRIM value */
+ /* Get start tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSI is ready */
+ while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set HSITRIM default value */
+ MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, RCC_CR_HSITRIM_4);
+
+ /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0] and MCOSEL[2:0] bits */
+ CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2 | RCC_CFGR_MCO);
+
+ /* Insure HSI selected as system clock source */
+ /* Get start tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till system clock source is ready */
+ while(READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
+ {
+ if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Update the SystemCoreClock global variable for HSI as system clock source */
+ SystemCoreClock = HSI_VALUE;
+
+ /* Configure the source of time base considering new system clock settings */
+ if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Reset HSEON, CSSON, PLLON bits */
+ CLEAR_BIT(RCC->CR, RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON);
+
+ /* Reset HSEBYP bit */
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
+
+ /* Insure PLLRDY is reset */
+ /* Get start tick */
+ tickstart = HAL_GetTick();
+ while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
+ {
+ if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Reset CFGR register */
+ CLEAR_REG(RCC->CFGR);
+
+ /* Reset CFGR2 register */
+ CLEAR_REG(RCC->CFGR2);
+
+ /* Reset CFGR3 register */
+ CLEAR_REG(RCC->CFGR3);
+
+ /* Clear all interrupt flags */
+ SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_CSSC);
+
+ /* Disable all interrupts */
+ CLEAR_REG(RCC->CIR);
+
+ /* Reset all CSR flags */
+ __HAL_RCC_CLEAR_RESET_FLAGS();
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the RCC Oscillators according to the specified parameters in the
+ * RCC_OscInitTypeDef.
+ * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
+ * contains the configuration information for the RCC Oscillators.
+ * @note The PLL is not disabled when used as system clock.
+ * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
+ * supported by this macro. User should request a transition to LSE Off
+ * first and then LSE On or LSE Bypass.
+ * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
+ * supported by this macro. User should request a transition to HSE Off
+ * first and then HSE On or HSE Bypass.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
+{
+ uint32_t tickstart;
+
+ /* Check Null pointer */
+ if(RCC_OscInitStruct == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
+
+ /*------------------------------- HSE Configuration ------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
+
+ /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
+ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
+ || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
+ {
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
+ {
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Set the new HSE configuration ---------------------------------------*/
+ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
+
+#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
+ /* Configure the HSE predivision factor --------------------------------*/
+ __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
+#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
+
+ /* Check the HSE State */
+ if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
+ {
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSE is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ }
+ /*----------------------------- HSI Configuration --------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
+ assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
+
+ /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
+ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
+ || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)))
+ {
+ /* When HSI is used as system clock it will not disabled */
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
+ {
+ return HAL_ERROR;
+ }
+ /* Otherwise, just the calibration is allowed */
+ else
+ {
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ }
+ }
+ else
+ {
+ /* Check the HSI State */
+ if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
+ {
+ /* Enable the Internal High Speed oscillator (HSI). */
+ __HAL_RCC_HSI_ENABLE();
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSI is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ }
+ else
+ {
+ /* Disable the Internal High Speed oscillator (HSI). */
+ __HAL_RCC_HSI_DISABLE();
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSI is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ }
+ /*------------------------------ LSI Configuration -------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
+
+ /* Check the LSI State */
+ if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
+ {
+ /* Enable the Internal Low Speed oscillator (LSI). */
+ __HAL_RCC_LSI_ENABLE();
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSI is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Disable the Internal Low Speed oscillator (LSI). */
+ __HAL_RCC_LSI_DISABLE();
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSI is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ /*------------------------------ LSE Configuration -------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
+ {
+ FlagStatus pwrclkchanged = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
+
+ /* Update LSE configuration in Backup Domain control register */
+ /* Requires to enable write access to Backup Domain of necessary */
+ if(__HAL_RCC_PWR_IS_CLK_DISABLED())
+ {
+ __HAL_RCC_PWR_CLK_ENABLE();
+ pwrclkchanged = SET;
+ }
+
+ if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
+ {
+ /* Enable write access to Backup domain */
+ SET_BIT(PWR->CR, PWR_CR_DBP);
+
+ /* Wait for Backup domain Write protection disable */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
+ {
+ if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Set the new LSE configuration -----------------------------------------*/
+ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
+ /* Check the LSE State */
+ if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
+ {
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Require to disable power clock if necessary */
+ if(pwrclkchanged == SET)
+ {
+ __HAL_RCC_PWR_CLK_DISABLE();
+ }
+ }
+
+ /*-------------------------------- PLL Configuration -----------------------*/
+ /* Check the parameters */
+ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
+ if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
+ {
+ /* Check if the PLL is used as system clock or not */
+ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
+ {
+ if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
+ assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
+#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
+ assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV));
+#endif
+
+ /* Disable the main PLL. */
+ __HAL_RCC_PLL_DISABLE();
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
+ /* Configure the main PLL clock source, predivider and multiplication factor. */
+ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
+ RCC_OscInitStruct->PLL.PREDIV,
+ RCC_OscInitStruct->PLL.PLLMUL);
+#else
+ /* Configure the main PLL clock source and multiplication factor. */
+ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
+ RCC_OscInitStruct->PLL.PLLMUL);
+#endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */
+ /* Enable the main PLL. */
+ __HAL_RCC_PLL_ENABLE();
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Disable the main PLL. */
+ __HAL_RCC_PLL_DISABLE();
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CPU, AHB and APB buses clocks according to the specified
+ * parameters in the RCC_ClkInitStruct.
+ * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
+ * contains the configuration information for the RCC peripheral.
+ * @param FLatency FLASH Latency
+ * The value of this parameter depend on device used within the same series
+ * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
+ * and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function
+ *
+ * @note The HSI is used (enabled by hardware) as system clock source after
+ * start-up from Reset, wake-up from STOP and STANDBY mode, or in case
+ * of failure of the HSE used directly or indirectly as system clock
+ * (if the Clock Security System CSS is enabled).
+ *
+ * @note A switch from one clock source to another occurs only if the target
+ * clock source is ready (clock stable after start-up delay or PLL locked).
+ * If a clock source which is not yet ready is selected, the switch will
+ * occur when the clock source will be ready.
+ * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
+ * currently used as system clock source.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
+{
+ uint32_t tickstart = 0U;
+
+ /* Check Null pointer */
+ if(RCC_ClkInitStruct == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
+ assert_param(IS_FLASH_LATENCY(FLatency));
+
+ /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
+ must be correctly programmed according to the frequency of the CPU clock
+ (HCLK) of the device. */
+
+ /* Increasing the number of wait states because of higher CPU frequency */
+ if(FLatency > __HAL_FLASH_GET_LATENCY())
+ {
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ __HAL_FLASH_SET_LATENCY(FLatency);
+
+ /* Check that the new number of wait states is taken into account to access the Flash
+ memory by reading the FLASH_ACR register */
+ if(__HAL_FLASH_GET_LATENCY() != FLatency)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /*-------------------------- HCLK Configuration --------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+ {
+ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+ }
+
+ /*------------------------- SYSCLK Configuration ---------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
+ {
+ assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
+
+ /* HSE is selected as System Clock Source */
+ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+ {
+ /* Check the HSE ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+ }
+ /* PLL is selected as System Clock Source */
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+ {
+ /* Check the PLL ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+ }
+ /* HSI is selected as System Clock Source */
+ else
+ {
+ /* Check the HSI ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
+ {
+ if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /* Decreasing the number of wait states because of lower CPU frequency */
+ if(FLatency < __HAL_FLASH_GET_LATENCY())
+ {
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ __HAL_FLASH_SET_LATENCY(FLatency);
+
+ /* Check that the new number of wait states is taken into account to access the Flash
+ memory by reading the FLASH_ACR register */
+ if(__HAL_FLASH_GET_LATENCY() != FLatency)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /*-------------------------- PCLK1 Configuration ---------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+ {
+ assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
+ }
+
+ /*-------------------------- PCLK2 Configuration ---------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+ {
+ assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
+ }
+
+ /* Update the SystemCoreClock global variable */
+ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER];
+
+ /* Configure the source of time base considering new system clocks settings*/
+ HAL_InitTick (TICK_INT_PRIORITY);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
+ * @brief RCC clocks control functions
+ *
+ @verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the RCC Clocks
+ frequencies.
+
+ @endverbatim
+ * @{
+ */
+
+#if defined(RCC_CFGR_MCOPRE)
+/**
+ * @brief Selects the clock source to output on MCO pin.
+ * @note MCO pin should be configured in alternate function mode.
+ * @param RCC_MCOx specifies the output direction for the clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8).
+ * @param RCC_MCOSource specifies the clock source to output.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected
+ * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock
+ * @param RCC_MCODiv specifies the MCO DIV.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_MCODIV_1 no division applied to MCO clock
+ * @arg @ref RCC_MCODIV_2 division by 2 applied to MCO clock
+ * @arg @ref RCC_MCODIV_4 division by 4 applied to MCO clock
+ * @arg @ref RCC_MCODIV_8 division by 8 applied to MCO clock
+ * @arg @ref RCC_MCODIV_16 division by 16 applied to MCO clock
+ * @arg @ref RCC_MCODIV_32 division by 32 applied to MCO clock
+ * @arg @ref RCC_MCODIV_64 division by 64 applied to MCO clock
+ * @arg @ref RCC_MCODIV_128 division by 128 applied to MCO clock
+ * @retval None
+ */
+#else
+/**
+ * @brief Selects the clock source to output on MCO pin.
+ * @note MCO pin should be configured in alternate function mode.
+ * @param RCC_MCOx specifies the output direction for the clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8).
+ * @param RCC_MCOSource specifies the clock source to output.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock
+ * @param RCC_MCODiv specifies the MCO DIV.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_MCODIV_1 no division applied to MCO clock
+ * @retval None
+ */
+#endif
+void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
+{
+ GPIO_InitTypeDef gpio;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_MCO(RCC_MCOx));
+ assert_param(IS_RCC_MCODIV(RCC_MCODiv));
+ assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
+
+ /* Configure the MCO1 pin in alternate function mode */
+ gpio.Mode = GPIO_MODE_AF_PP;
+ gpio.Speed = GPIO_SPEED_FREQ_HIGH;
+ gpio.Pull = GPIO_NOPULL;
+ gpio.Pin = MCO1_PIN;
+ gpio.Alternate = GPIO_AF0_MCO;
+
+ /* MCO1 Clock Enable */
+ MCO1_CLK_ENABLE();
+
+ HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio);
+
+ /* Configure the MCO clock source */
+ __HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv);
+}
+
+/**
+ * @brief Enables the Clock Security System.
+ * @note If a failure is detected on the HSE oscillator clock, this oscillator
+ * is automatically disabled and an interrupt is generated to inform the
+ * software about the failure (Clock Security System Interrupt, CSSI),
+ * allowing the MCU to perform rescue operations. The CSSI is linked to
+ * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
+ * @retval None
+ */
+void HAL_RCC_EnableCSS(void)
+{
+ *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE;
+}
+
+/**
+ * @brief Disables the Clock Security System.
+ * @retval None
+ */
+void HAL_RCC_DisableCSS(void)
+{
+ *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE;
+}
+
+/**
+ * @brief Returns the SYSCLK frequency
+ * @note The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
+ * @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE
+ * divided by PREDIV factor(**)
+ * @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE
+ * divided by PREDIV factor(**) or HSI_VALUE(*) multiplied by the PLL factor.
+ * @note (*) HSI_VALUE is a constant defined in stm32f3xx_hal_conf.h file (default value
+ * 8 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ * @note (**) HSE_VALUE is a constant defined in stm32f3xx_hal_conf.h file (default value
+ * 8 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * @note The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @note This function can be used by the user application to compute the
+ * baud-rate for the communication peripherals or configure other parameters.
+ *
+ * @note Each time SYSCLK changes, this function must be called to update the
+ * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
+ *
+ * @retval SYSCLK frequency
+ */
+uint32_t HAL_RCC_GetSysClockFreq(void)
+{
+ uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
+ uint32_t sysclockfreq = 0U;
+
+ tmpreg = RCC->CFGR;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ switch (tmpreg & RCC_CFGR_SWS)
+ {
+ case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
+ {
+ sysclockfreq = HSE_VALUE;
+ break;
+ }
+ case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
+ {
+ pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> POSITION_VAL(RCC_CFGR_PLLMUL)];
+ prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> POSITION_VAL(RCC_CFGR2_PREDIV)];
+#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
+ if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI)
+ {
+ /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
+ pllclk = (HSE_VALUE / prediv) * pllmul;
+ }
+ else
+ {
+ /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
+ pllclk = (HSI_VALUE >> 1U) * pllmul;
+ }
+#else
+ if ((tmpreg & RCC_CFGR_PLLSRC_HSE_PREDIV) == RCC_CFGR_PLLSRC_HSE_PREDIV)
+ {
+ /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
+ pllclk = (HSE_VALUE / prediv) * pllmul;
+ }
+ else
+ {
+ /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */
+ pllclk = (HSI_VALUE / prediv) * pllmul;
+ }
+#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
+ sysclockfreq = pllclk;
+ break;
+ }
+ case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
+ default: /* HSI used as system clock */
+ {
+ sysclockfreq = HSI_VALUE;
+ break;
+ }
+ }
+ return sysclockfreq;
+}
+
+/**
+ * @brief Returns the HCLK frequency
+ * @note Each time HCLK changes, this function must be called to update the
+ * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
+ *
+ * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
+ * and updated within this function
+ * @retval HCLK frequency
+ */
+uint32_t HAL_RCC_GetHCLKFreq(void)
+{
+ return SystemCoreClock;
+}
+
+/**
+ * @brief Returns the PCLK1 frequency
+ * @note Each time PCLK1 changes, this function must be called to update the
+ * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
+ * @retval PCLK1 frequency
+ */
+uint32_t HAL_RCC_GetPCLK1Freq(void)
+{
+ /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
+ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_BITNUMBER]);
+}
+
+/**
+ * @brief Returns the PCLK2 frequency
+ * @note Each time PCLK2 changes, this function must be called to update the
+ * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
+ * @retval PCLK2 frequency
+ */
+uint32_t HAL_RCC_GetPCLK2Freq(void)
+{
+ /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
+ return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_BITNUMBER]);
+}
+
+/**
+ * @brief Configures the RCC_OscInitStruct according to the internal
+ * RCC configuration registers.
+ * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
+ * will be configured.
+ * @retval None
+ */
+void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
+{
+ /* Check the parameters */
+ assert_param(RCC_OscInitStruct != NULL);
+
+ /* Set all possible values for the Oscillator type parameter ---------------*/
+ RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI \
+ | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
+
+
+ /* Get the HSE configuration -----------------------------------------------*/
+ if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
+ {
+ RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
+ }
+ else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
+ {
+ RCC_OscInitStruct->HSEState = RCC_HSE_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
+ }
+#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
+ RCC_OscInitStruct->HSEPredivValue = __HAL_RCC_HSE_GET_PREDIV();
+#endif
+
+ /* Get the HSI configuration -----------------------------------------------*/
+ if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
+ {
+ RCC_OscInitStruct->HSIState = RCC_HSI_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
+ }
+
+ RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
+
+ /* Get the LSE configuration -----------------------------------------------*/
+ if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
+ {
+ RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
+ }
+ else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
+ {
+ RCC_OscInitStruct->LSEState = RCC_LSE_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
+ }
+
+ /* Get the LSI configuration -----------------------------------------------*/
+ if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
+ {
+ RCC_OscInitStruct->LSIState = RCC_LSI_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
+ }
+
+
+ /* Get the PLL configuration -----------------------------------------------*/
+ if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
+ {
+ RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
+ }
+ RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC);
+ RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMUL);
+#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
+ RCC_OscInitStruct->PLL.PREDIV = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV);
+#endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */
+}
+
+/**
+ * @brief Get the RCC_ClkInitStruct according to the internal
+ * RCC configuration registers.
+ * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
+ * contains the current clock configuration.
+ * @param pFLatency Pointer on the Flash Latency.
+ * @retval None
+ */
+void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
+{
+ /* Check the parameters */
+ assert_param(RCC_ClkInitStruct != NULL);
+ assert_param(pFLatency != NULL);
+
+ /* Set all possible values for the Clock type parameter --------------------*/
+ RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+
+ /* Get the SYSCLK configuration --------------------------------------------*/
+ RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
+
+ /* Get the HCLK configuration ----------------------------------------------*/
+ RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
+
+ /* Get the APB1 configuration ----------------------------------------------*/
+ RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
+
+ /* Get the APB2 configuration ----------------------------------------------*/
+ RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U);
+
+ /* Get the Flash Wait State (Latency) configuration ------------------------*/
+ *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
+}
+
+/**
+ * @brief This function handles the RCC CSS interrupt request.
+ * @note This API should be called under the NMI_Handler().
+ * @retval None
+ */
+void HAL_RCC_NMI_IRQHandler(void)
+{
+ /* Check RCC CSSF flag */
+ if(__HAL_RCC_GET_IT(RCC_IT_CSS))
+ {
+ /* RCC Clock Security System interrupt user callback */
+ HAL_RCC_CSSCallback();
+
+ /* Clear RCC CSS pending bit */
+ __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
+ }
+}
+
+/**
+ * @brief RCC Clock Security System interrupt callback
+ * @retval none
+ */
+__weak void HAL_RCC_CSSCallback(void)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_RCC_CSSCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_RCC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_rcc_ex.c b/Src/stm32f3xx_hal_rcc_ex.c
new file mode 100644
index 0000000..7ba8cff
--- /dev/null
+++ b/Src/stm32f3xx_hal_rcc_ex.c
@@ -0,0 +1,1596 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_rcc_ex.c
+ * @author MCD Application Team
+ * @brief Extended RCC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities RCC extension peripheral:
+ * + Extended Peripheral Control functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+
+/** @defgroup RCCEx RCCEx
+ * @brief RCC Extension HAL module driver.
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+#if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34) || defined(RCC_CFGR_USBPRE) \
+ || defined(RCC_CFGR3_TIM1SW) || defined(RCC_CFGR3_TIM2SW) || defined(RCC_CFGR3_TIM8SW) || defined(RCC_CFGR3_TIM15SW) \
+ || defined(RCC_CFGR3_TIM16SW) || defined(RCC_CFGR3_TIM17SW) || defined(RCC_CFGR3_TIM20SW) || defined(RCC_CFGR3_TIM34SW) \
+ || defined(RCC_CFGR3_HRTIM1SW)
+/** @defgroup RCCEx_Private_Functions RCCEx Private Functions
+ * @{
+ */
+static uint32_t RCC_GetPLLCLKFreq(void);
+
+/**
+ * @}
+ */
+#endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRExx || RCC_CFGR3_TIMxSW || RCC_CFGR3_HRTIM1SW || RCC_CFGR_USBPRE */
+
+/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
+ * @{
+ */
+
+/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
+ * @brief Extended Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the RCC Clocks
+ frequencies.
+ [..]
+ (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
+ select the RTC clock source; in this case the Backup domain will be reset in
+ order to modify the RTC Clock source, as consequence RTC registers (including
+ the backup registers) are set to their reset values.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the RCC extended peripherals clocks according to the specified
+ * parameters in the RCC_PeriphCLKInitTypeDef.
+ * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * contains the configuration information for the Extended Peripherals clocks
+ * (ADC, CEC, I2C, I2S, SDADC, HRTIM, TIM, USART, RTC and USB).
+ *
+ * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
+ * the RTC clock source; in this case the Backup domain will be reset in
+ * order to modify the RTC Clock source, as consequence RTC registers (including
+ * the backup registers) and RCC_BDCR register are set to their reset values.
+ *
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
+{
+ uint32_t tickstart = 0U;
+ uint32_t temp_reg = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
+
+ /*---------------------------- RTC configuration -------------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
+ {
+ /* check for RTC Parameters used to output RTCCLK */
+ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
+
+ FlagStatus pwrclkchanged = RESET;
+
+ /* As soon as function is called to change RTC clock source, activation of the
+ power domain is done. */
+ /* Requires to enable write access to Backup Domain of necessary */
+ if(__HAL_RCC_PWR_IS_CLK_DISABLED())
+ {
+ __HAL_RCC_PWR_CLK_ENABLE();
+ pwrclkchanged = SET;
+ }
+
+ if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
+ {
+ /* Enable write access to Backup domain */
+ SET_BIT(PWR->CR, PWR_CR_DBP);
+
+ /* Wait for Backup domain Write protection disable */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
+ {
+ if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
+ temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
+ if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
+ {
+ /* Store the content of BDCR register before the reset of Backup Domain */
+ temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
+ /* RTC Clock selection can be changed only if the Backup Domain is reset */
+ __HAL_RCC_BACKUPRESET_FORCE();
+ __HAL_RCC_BACKUPRESET_RELEASE();
+ /* Restore the Content of BDCR register */
+ RCC->BDCR = temp_reg;
+
+ /* Wait for LSERDY if LSE was enabled */
+ if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
+ {
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+
+ /* Require to disable power clock if necessary */
+ if(pwrclkchanged == SET)
+ {
+ __HAL_RCC_PWR_CLK_DISABLE();
+ }
+ }
+
+ /*------------------------------- USART1 Configuration ------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
+
+ /* Configure the USART1 clock source */
+ __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
+ }
+
+#if defined(RCC_CFGR3_USART2SW)
+ /*----------------------------- USART2 Configuration --------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
+
+ /* Configure the USART2 clock source */
+ __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
+ }
+#endif /* RCC_CFGR3_USART2SW */
+
+#if defined(RCC_CFGR3_USART3SW)
+ /*------------------------------ USART3 Configuration ------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
+
+ /* Configure the USART3 clock source */
+ __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
+ }
+#endif /* RCC_CFGR3_USART3SW */
+
+ /*------------------------------ I2C1 Configuration ------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
+
+ /* Configure the I2C1 clock source */
+ __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
+ }
+
+#if defined(STM32F302xE) || defined(STM32F303xE)\
+ || defined(STM32F302xC) || defined(STM32F303xC)\
+ || defined(STM32F302x8) \
+ || defined(STM32F373xC)
+ /*------------------------------ USB Configuration ------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->USBClockSelection));
+
+ /* Configure the USB clock source */
+ __HAL_RCC_USB_CONFIG(PeriphClkInit->USBClockSelection);
+ }
+
+#endif /* STM32F302xE || STM32F303xE || */
+ /* STM32F302xC || STM32F303xC || */
+ /* STM32F302x8 || */
+ /* STM32F373xC */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
+ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\
+ || defined(STM32F373xC) || defined(STM32F378xx)
+
+ /*------------------------------ I2C2 Configuration ------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
+
+ /* Configure the I2C2 clock source */
+ __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
+ }
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
+ /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+
+ /*------------------------------ I2C3 Configuration ------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
+
+ /* Configure the I2C3 clock source */
+ __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
+ }
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+
+ /*------------------------------ UART4 Configuration ------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
+
+ /* Configure the UART4 clock source */
+ __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
+ }
+
+ /*------------------------------ UART5 Configuration ------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
+
+ /* Configure the UART5 clock source */
+ __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
+ }
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
+ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+ /*------------------------------ I2S Configuration ------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
+
+ /* Configure the I2S clock source */
+ __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
+ }
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+
+ /*------------------------------ ADC1 clock Configuration ------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC1) == RCC_PERIPHCLK_ADC1)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_ADC1PLLCLK_DIV(PeriphClkInit->Adc1ClockSelection));
+
+ /* Configure the ADC1 clock source */
+ __HAL_RCC_ADC1_CONFIG(PeriphClkInit->Adc1ClockSelection);
+ }
+
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
+ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+
+ /*------------------------------ ADC1 & ADC2 clock Configuration -------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_ADC12PLLCLK_DIV(PeriphClkInit->Adc12ClockSelection));
+
+ /* Configure the ADC12 clock source */
+ __HAL_RCC_ADC12_CONFIG(PeriphClkInit->Adc12ClockSelection);
+ }
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F303xC) || defined(STM32F358xx)
+
+ /*------------------------------ ADC3 & ADC4 clock Configuration -------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC34) == RCC_PERIPHCLK_ADC34)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_ADC34PLLCLK_DIV(PeriphClkInit->Adc34ClockSelection));
+
+ /* Configure the ADC34 clock source */
+ __HAL_RCC_ADC34_CONFIG(PeriphClkInit->Adc34ClockSelection);
+ }
+
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+
+ /*------------------------------ ADC1 clock Configuration ------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC1) == RCC_PERIPHCLK_ADC1)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_ADC1PCLK2_DIV(PeriphClkInit->Adc1ClockSelection));
+
+ /* Configure the ADC1 clock source */
+ __HAL_RCC_ADC1_CONFIG(PeriphClkInit->Adc1ClockSelection);
+ }
+
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
+ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
+ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+
+ /*------------------------------ TIM1 clock Configuration ----------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_TIM1CLKSOURCE(PeriphClkInit->Tim1ClockSelection));
+
+ /* Configure the TIM1 clock source */
+ __HAL_RCC_TIM1_CONFIG(PeriphClkInit->Tim1ClockSelection);
+ }
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F303xC) || defined(STM32F358xx)
+
+ /*------------------------------ TIM8 clock Configuration ----------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM8) == RCC_PERIPHCLK_TIM8)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_TIM8CLKSOURCE(PeriphClkInit->Tim8ClockSelection));
+
+ /* Configure the TIM8 clock source */
+ __HAL_RCC_TIM8_CONFIG(PeriphClkInit->Tim8ClockSelection);
+ }
+
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+
+ /*------------------------------ TIM15 clock Configuration ----------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_TIM15CLKSOURCE(PeriphClkInit->Tim15ClockSelection));
+
+ /* Configure the TIM15 clock source */
+ __HAL_RCC_TIM15_CONFIG(PeriphClkInit->Tim15ClockSelection);
+ }
+
+ /*------------------------------ TIM16 clock Configuration ----------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM16) == RCC_PERIPHCLK_TIM16)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_TIM16CLKSOURCE(PeriphClkInit->Tim16ClockSelection));
+
+ /* Configure the TIM16 clock source */
+ __HAL_RCC_TIM16_CONFIG(PeriphClkInit->Tim16ClockSelection);
+ }
+
+ /*------------------------------ TIM17 clock Configuration ----------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM17) == RCC_PERIPHCLK_TIM17)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_TIM17CLKSOURCE(PeriphClkInit->Tim17ClockSelection));
+
+ /* Configure the TIM17 clock source */
+ __HAL_RCC_TIM17_CONFIG(PeriphClkInit->Tim17ClockSelection);
+ }
+
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F334x8)
+
+ /*------------------------------ HRTIM1 clock Configuration ----------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_HRTIM1CLKSOURCE(PeriphClkInit->Hrtim1ClockSelection));
+
+ /* Configure the HRTIM1 clock source */
+ __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection);
+ }
+
+#endif /* STM32F334x8 */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+
+ /*------------------------------ SDADC clock Configuration -------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDADC) == RCC_PERIPHCLK_SDADC)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_SDADCSYSCLK_DIV(PeriphClkInit->SdadcClockSelection));
+
+ /* Configure the SDADC clock prescaler */
+ __HAL_RCC_SDADC_CONFIG(PeriphClkInit->SdadcClockSelection);
+ }
+
+ /*------------------------------ CEC clock Configuration -------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
+
+ /* Configure the CEC clock source */
+ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
+ }
+
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+
+ /*------------------------------ TIM2 clock Configuration -------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM2) == RCC_PERIPHCLK_TIM2)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_TIM2CLKSOURCE(PeriphClkInit->Tim2ClockSelection));
+
+ /* Configure the CEC clock source */
+ __HAL_RCC_TIM2_CONFIG(PeriphClkInit->Tim2ClockSelection);
+ }
+
+ /*------------------------------ TIM3 clock Configuration -------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM34) == RCC_PERIPHCLK_TIM34)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_TIM3CLKSOURCE(PeriphClkInit->Tim34ClockSelection));
+
+ /* Configure the CEC clock source */
+ __HAL_RCC_TIM34_CONFIG(PeriphClkInit->Tim34ClockSelection);
+ }
+
+ /*------------------------------ TIM15 clock Configuration ------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_TIM15CLKSOURCE(PeriphClkInit->Tim15ClockSelection));
+
+ /* Configure the CEC clock source */
+ __HAL_RCC_TIM15_CONFIG(PeriphClkInit->Tim15ClockSelection);
+ }
+
+ /*------------------------------ TIM16 clock Configuration ------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM16) == RCC_PERIPHCLK_TIM16)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_TIM16CLKSOURCE(PeriphClkInit->Tim16ClockSelection));
+
+ /* Configure the CEC clock source */
+ __HAL_RCC_TIM16_CONFIG(PeriphClkInit->Tim16ClockSelection);
+ }
+
+ /*------------------------------ TIM17 clock Configuration ------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM17) == RCC_PERIPHCLK_TIM17)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_TIM17CLKSOURCE(PeriphClkInit->Tim17ClockSelection));
+
+ /* Configure the CEC clock source */
+ __HAL_RCC_TIM17_CONFIG(PeriphClkInit->Tim17ClockSelection);
+ }
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)
+ /*------------------------------ TIM20 clock Configuration ------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM20) == RCC_PERIPHCLK_TIM20)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_TIM20CLKSOURCE(PeriphClkInit->Tim20ClockSelection));
+
+ /* Configure the CEC clock source */
+ __HAL_RCC_TIM20_CONFIG(PeriphClkInit->Tim20ClockSelection);
+ }
+#endif /* STM32F303xE || STM32F398xx */
+
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get the RCC_ClkInitStruct according to the internal
+ * RCC configuration registers.
+ * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * returns the configuration information for the Extended Peripherals clocks
+ * (ADC, CEC, I2C, I2S, SDADC, HRTIM, TIM, USART, RTC and USB clocks).
+ * @retval None
+ */
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
+{
+ /* Set all possible values for the extended clock type parameter------------*/
+ /* Common part first */
+#if defined(RCC_CFGR3_USART2SW) && defined(RCC_CFGR3_USART3SW)
+ PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC;
+#else
+ PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC;
+#endif /* RCC_CFGR3_USART2SW && RCC_CFGR3_USART3SW */
+
+ /* Get the RTC configuration --------------------------------------------*/
+ PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE();
+ /* Get the USART1 clock configuration --------------------------------------------*/
+ PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
+#if defined(RCC_CFGR3_USART2SW)
+ /* Get the USART2 clock configuration -----------------------------------------*/
+ PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
+#endif /* RCC_CFGR3_USART2SW */
+#if defined(RCC_CFGR3_USART3SW)
+ /* Get the USART3 clock configuration -----------------------------------------*/
+ PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();
+#endif /* RCC_CFGR3_USART3SW */
+ /* Get the I2C1 clock configuration -----------------------------------------*/
+ PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
+
+#if defined(STM32F302xE) || defined(STM32F303xE)\
+ || defined(STM32F302xC) || defined(STM32F303xC)\
+ || defined(STM32F302x8) \
+ || defined(STM32F373xC)
+
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB;
+ /* Get the USB clock configuration -----------------------------------------*/
+ PeriphClkInit->USBClockSelection = __HAL_RCC_GET_USB_SOURCE();
+
+#endif /* STM32F302xE || STM32F303xE || */
+ /* STM32F302xC || STM32F303xC || */
+ /* STM32F302x8 || */
+ /* STM32F373xC */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
+ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\
+ || defined(STM32F373xC) || defined(STM32F378xx)
+
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C2;
+ /* Get the I2C2 clock configuration -----------------------------------------*/
+ PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE();
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
+ /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C3;
+ /* Get the I2C3 clock configuration -----------------------------------------*/
+ PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F302xC) || defined(STM32F303xC) ||defined(STM32F358xx)
+
+ PeriphClkInit->PeriphClockSelection |= (RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5);
+ /* Get the UART4 clock configuration -----------------------------------------*/
+ PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE();
+ /* Get the UART5 clock configuration -----------------------------------------*/
+ PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE();
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
+ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S;
+ /* Get the I2S clock configuration -----------------------------------------*/
+ PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2S_SOURCE();
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\
+ || defined(STM32F373xC) || defined(STM32F378xx)
+
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC1;
+ /* Get the ADC1 clock configuration -----------------------------------------*/
+ PeriphClkInit->Adc1ClockSelection = __HAL_RCC_GET_ADC1_SOURCE();
+
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
+ /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
+ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC12;
+ /* Get the ADC1 & ADC2 clock configuration -----------------------------------------*/
+ PeriphClkInit->Adc12ClockSelection = __HAL_RCC_GET_ADC12_SOURCE();
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F303xC) || defined(STM32F358xx)
+
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC34;
+ /* Get the ADC3 & ADC4 clock configuration -----------------------------------------*/
+ PeriphClkInit->Adc34ClockSelection = __HAL_RCC_GET_ADC34_SOURCE();
+
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
+ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
+ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM1;
+ /* Get the TIM1 clock configuration -----------------------------------------*/
+ PeriphClkInit->Tim1ClockSelection = __HAL_RCC_GET_TIM1_SOURCE();
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F303xC) || defined(STM32F358xx)
+
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM8;
+ /* Get the TIM8 clock configuration -----------------------------------------*/
+ PeriphClkInit->Tim8ClockSelection = __HAL_RCC_GET_TIM8_SOURCE();
+
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+
+ PeriphClkInit->PeriphClockSelection |= (RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | RCC_PERIPHCLK_TIM17);
+ /* Get the TIM15 clock configuration -----------------------------------------*/
+ PeriphClkInit->Tim15ClockSelection = __HAL_RCC_GET_TIM15_SOURCE();
+ /* Get the TIM16 clock configuration -----------------------------------------*/
+ PeriphClkInit->Tim16ClockSelection = __HAL_RCC_GET_TIM16_SOURCE();
+ /* Get the TIM17 clock configuration -----------------------------------------*/
+ PeriphClkInit->Tim17ClockSelection = __HAL_RCC_GET_TIM17_SOURCE();
+
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F334x8)
+
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_HRTIM1;
+ /* Get the HRTIM1 clock configuration -----------------------------------------*/
+ PeriphClkInit->Hrtim1ClockSelection = __HAL_RCC_GET_HRTIM1_SOURCE();
+
+#endif /* STM32F334x8 */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SDADC;
+ /* Get the SDADC clock configuration -----------------------------------------*/
+ PeriphClkInit->SdadcClockSelection = __HAL_RCC_GET_SDADC_SOURCE();
+
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_CEC;
+ /* Get the CEC clock configuration -----------------------------------------*/
+ PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
+
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM2;
+ /* Get the TIM2 clock configuration -----------------------------------------*/
+ PeriphClkInit->Tim2ClockSelection = __HAL_RCC_GET_TIM2_SOURCE();
+
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM34;
+ /* Get the TIM3 clock configuration -----------------------------------------*/
+ PeriphClkInit->Tim34ClockSelection = __HAL_RCC_GET_TIM34_SOURCE();
+
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM15;
+ /* Get the TIM15 clock configuration -----------------------------------------*/
+ PeriphClkInit->Tim15ClockSelection = __HAL_RCC_GET_TIM15_SOURCE();
+
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM16;
+ /* Get the TIM16 clock configuration -----------------------------------------*/
+ PeriphClkInit->Tim16ClockSelection = __HAL_RCC_GET_TIM16_SOURCE();
+
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM17;
+ /* Get the TIM17 clock configuration -----------------------------------------*/
+ PeriphClkInit->Tim17ClockSelection = __HAL_RCC_GET_TIM17_SOURCE();
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+
+#if defined (STM32F303xE) || defined(STM32F398xx)
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM20;
+ /* Get the TIM20 clock configuration -----------------------------------------*/
+ PeriphClkInit->Tim20ClockSelection = __HAL_RCC_GET_TIM20_SOURCE();
+#endif /* STM32F303xE || STM32F398xx */
+}
+
+/**
+ * @brief Returns the peripheral clock frequency
+ * @note Returns 0 if peripheral clock is unknown or 0xDEADDEAD if not applicable.
+ * @param PeriphClk Peripheral clock identifier
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
+ * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
+ @if STM32F301x8
+ * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
+ * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock
+ @endif
+ @if STM32F302x8
+ * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
+ * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
+ * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock
+ @endif
+ @if STM32F302xC
+ * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
+ * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
+ * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
+ @endif
+ @if STM32F302xE
+ * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
+ * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
+ * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM2 TIM2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM34 TIM34 peripheral clock
+ @endif
+ @if STM32F303x8
+ * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
+ @endif
+ @if STM32F303xC
+ * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
+ * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
+ * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_ADC34 ADC34 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM8 TIM8 peripheral clock
+ @endif
+ @if STM32F303xE
+ * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
+ * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
+ * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_ADC34 ADC34 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM2 TIM2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM8 TIM8 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM20 TIM20 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM34 TIM34 peripheral clock
+ @endif
+ @if STM32F318xx
+ * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
+ * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock
+ @endif
+ @if STM32F328xx
+ * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
+ @endif
+ @if STM32F334x8
+ * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_HRTIM1 HRTIM1 peripheral clock
+ @endif
+ @if STM32F358xx
+ * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
+ * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_ADC34 ADC34 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM8 TIM8 peripheral clock
+ @endif
+ @if STM32F373xC
+ * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
+ * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_SDADC SDADC peripheral clock
+ * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock
+ @endif
+ @if STM32F378xx
+ * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_SDADC SDADC peripheral clock
+ * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock
+ @endif
+ @if STM32F398xx
+ * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
+ * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_ADC34 ADC34 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM2 TIM2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM8 TIM8 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM20 TIM20 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM34 TIM34 peripheral clock
+ @endif
+ * @retval Frequency in Hz (0: means that no available frequency for the peripheral)
+ */
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
+{
+ /* frequency == 0 : means that no available frequency for the peripheral */
+ uint32_t frequency = 0U;
+
+ uint32_t srcclk = 0U;
+#if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
+ uint16_t adc_pll_prediv_table[16] = { 1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U, 256U, 256U, 256U, 256U};
+#endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */
+#if defined(RCC_CFGR_SDPRE)
+ uint8_t sdadc_prescaler_table[16] = { 2U, 4U, 6U, 8U, 10U, 12U, 14U, 16U, 20U, 24U, 28U, 32U, 36U, 40U, 44U, 48U};
+#endif /* RCC_CFGR_SDPRE */
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
+
+ switch (PeriphClk)
+ {
+ case RCC_PERIPHCLK_RTC:
+ {
+ /* Get the current RTC source */
+ srcclk = __HAL_RCC_GET_RTC_SOURCE();
+
+ /* Check if LSE is ready and if RTC clock selection is LSE */
+ if ((srcclk == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
+ {
+ frequency = LSE_VALUE;
+ }
+ /* Check if LSI is ready and if RTC clock selection is LSI */
+ else if ((srcclk == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
+ {
+ frequency = LSI_VALUE;
+ }
+ /* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/
+ else if ((srcclk == RCC_RTCCLKSOURCE_HSE_DIV32) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)))
+ {
+ frequency = HSE_VALUE / 32U;
+ }
+ break;
+ }
+ case RCC_PERIPHCLK_USART1:
+ {
+ /* Get the current USART1 source */
+ srcclk = __HAL_RCC_GET_USART1_SOURCE();
+
+ /* Check if USART1 clock selection is PCLK1 */
+#if defined(RCC_USART1CLKSOURCE_PCLK2)
+ if (srcclk == RCC_USART1CLKSOURCE_PCLK2)
+ {
+ frequency = HAL_RCC_GetPCLK2Freq();
+ }
+#else
+ if (srcclk == RCC_USART1CLKSOURCE_PCLK1)
+ {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ }
+#endif /* RCC_USART1CLKSOURCE_PCLK2 */
+ /* Check if HSI is ready and if USART1 clock selection is HSI */
+ else if ((srcclk == RCC_USART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
+ {
+ frequency = HSI_VALUE;
+ }
+ /* Check if USART1 clock selection is SYSCLK */
+ else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ /* Check if LSE is ready and if USART1 clock selection is LSE */
+ else if ((srcclk == RCC_USART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
+ {
+ frequency = LSE_VALUE;
+ }
+ break;
+ }
+#if defined(RCC_CFGR3_USART2SW)
+ case RCC_PERIPHCLK_USART2:
+ {
+ /* Get the current USART2 source */
+ srcclk = __HAL_RCC_GET_USART2_SOURCE();
+
+ /* Check if USART2 clock selection is PCLK1 */
+ if (srcclk == RCC_USART2CLKSOURCE_PCLK1)
+ {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ }
+ /* Check if HSI is ready and if USART2 clock selection is HSI */
+ else if ((srcclk == RCC_USART2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
+ {
+ frequency = HSI_VALUE;
+ }
+ /* Check if USART2 clock selection is SYSCLK */
+ else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ /* Check if LSE is ready and if USART2 clock selection is LSE */
+ else if ((srcclk == RCC_USART2CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
+ {
+ frequency = LSE_VALUE;
+ }
+ break;
+ }
+#endif /* RCC_CFGR3_USART2SW */
+#if defined(RCC_CFGR3_USART3SW)
+ case RCC_PERIPHCLK_USART3:
+ {
+ /* Get the current USART3 source */
+ srcclk = __HAL_RCC_GET_USART3_SOURCE();
+
+ /* Check if USART3 clock selection is PCLK1 */
+ if (srcclk == RCC_USART3CLKSOURCE_PCLK1)
+ {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ }
+ /* Check if HSI is ready and if USART3 clock selection is HSI */
+ else if ((srcclk == RCC_USART3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
+ {
+ frequency = HSI_VALUE;
+ }
+ /* Check if USART3 clock selection is SYSCLK */
+ else if (srcclk == RCC_USART3CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ /* Check if LSE is ready and if USART3 clock selection is LSE */
+ else if ((srcclk == RCC_USART3CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
+ {
+ frequency = LSE_VALUE;
+ }
+ break;
+ }
+#endif /* RCC_CFGR3_USART3SW */
+#if defined(RCC_CFGR3_UART4SW)
+ case RCC_PERIPHCLK_UART4:
+ {
+ /* Get the current UART4 source */
+ srcclk = __HAL_RCC_GET_UART4_SOURCE();
+
+ /* Check if UART4 clock selection is PCLK1 */
+ if (srcclk == RCC_UART4CLKSOURCE_PCLK1)
+ {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ }
+ /* Check if HSI is ready and if UART4 clock selection is HSI */
+ else if ((srcclk == RCC_UART4CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
+ {
+ frequency = HSI_VALUE;
+ }
+ /* Check if UART4 clock selection is SYSCLK */
+ else if (srcclk == RCC_UART4CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ /* Check if LSE is ready and if UART4 clock selection is LSE */
+ else if ((srcclk == RCC_UART4CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
+ {
+ frequency = LSE_VALUE;
+ }
+ break;
+ }
+#endif /* RCC_CFGR3_UART4SW */
+#if defined(RCC_CFGR3_UART5SW)
+ case RCC_PERIPHCLK_UART5:
+ {
+ /* Get the current UART5 source */
+ srcclk = __HAL_RCC_GET_UART5_SOURCE();
+
+ /* Check if UART5 clock selection is PCLK1 */
+ if (srcclk == RCC_UART5CLKSOURCE_PCLK1)
+ {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ }
+ /* Check if HSI is ready and if UART5 clock selection is HSI */
+ else if ((srcclk == RCC_UART5CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
+ {
+ frequency = HSI_VALUE;
+ }
+ /* Check if UART5 clock selection is SYSCLK */
+ else if (srcclk == RCC_UART5CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ /* Check if LSE is ready and if UART5 clock selection is LSE */
+ else if ((srcclk == RCC_UART5CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
+ {
+ frequency = LSE_VALUE;
+ }
+ break;
+ }
+#endif /* RCC_CFGR3_UART5SW */
+ case RCC_PERIPHCLK_I2C1:
+ {
+ /* Get the current I2C1 source */
+ srcclk = __HAL_RCC_GET_I2C1_SOURCE();
+
+ /* Check if HSI is ready and if I2C1 clock selection is HSI */
+ if ((srcclk == RCC_I2C1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
+ {
+ frequency = HSI_VALUE;
+ }
+ /* Check if I2C1 clock selection is SYSCLK */
+ else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ break;
+ }
+#if defined(RCC_CFGR3_I2C2SW)
+ case RCC_PERIPHCLK_I2C2:
+ {
+ /* Get the current I2C2 source */
+ srcclk = __HAL_RCC_GET_I2C2_SOURCE();
+
+ /* Check if HSI is ready and if I2C2 clock selection is HSI */
+ if ((srcclk == RCC_I2C2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
+ {
+ frequency = HSI_VALUE;
+ }
+ /* Check if I2C2 clock selection is SYSCLK */
+ else if (srcclk == RCC_I2C2CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ break;
+ }
+#endif /* RCC_CFGR3_I2C2SW */
+#if defined(RCC_CFGR3_I2C3SW)
+ case RCC_PERIPHCLK_I2C3:
+ {
+ /* Get the current I2C3 source */
+ srcclk = __HAL_RCC_GET_I2C3_SOURCE();
+
+ /* Check if HSI is ready and if I2C3 clock selection is HSI */
+ if ((srcclk == RCC_I2C3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
+ {
+ frequency = HSI_VALUE;
+ }
+ /* Check if I2C3 clock selection is SYSCLK */
+ else if (srcclk == RCC_I2C3CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ break;
+ }
+#endif /* RCC_CFGR3_I2C3SW */
+#if defined(RCC_CFGR_I2SSRC)
+ case RCC_PERIPHCLK_I2S:
+ {
+ /* Get the current I2S source */
+ srcclk = __HAL_RCC_GET_I2S_SOURCE();
+
+ /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin */
+ if (srcclk == RCC_I2SCLKSOURCE_EXT)
+ {
+ /* External clock used. Frequency cannot be returned.*/
+ frequency = 0xDEADDEADU;
+ }
+ /* Check if I2S clock selection is SYSCLK */
+ else if (srcclk == RCC_I2SCLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ break;
+ }
+#endif /* RCC_CFGR_I2SSRC */
+#if defined(RCC_CFGR_USBPRE)
+ case RCC_PERIPHCLK_USB:
+ {
+ /* Check if PLL is ready */
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
+ {
+ /* Get the current USB source */
+ srcclk = __HAL_RCC_GET_USB_SOURCE();
+
+ /* Check if USB clock selection is not divided */
+ if (srcclk == RCC_USBCLKSOURCE_PLL)
+ {
+ frequency = RCC_GetPLLCLKFreq();
+ }
+ /* Check if USB clock selection is divided by 1.5 */
+ else /* RCC_USBCLKSOURCE_PLL_DIV1_5 */
+ {
+ frequency = (RCC_GetPLLCLKFreq() * 3U) / 2U;
+ }
+ }
+ break;
+ }
+#endif /* RCC_CFGR_USBPRE */
+#if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR_ADCPRE)
+ case RCC_PERIPHCLK_ADC1:
+ {
+ /* Get the current ADC1 source */
+ srcclk = __HAL_RCC_GET_ADC1_SOURCE();
+#if defined(RCC_CFGR2_ADC1PRES)
+ /* Check if ADC1 clock selection is AHB */
+ if (srcclk == RCC_ADC1PLLCLK_OFF)
+ {
+ frequency = SystemCoreClock;
+ }
+ /* PLL clock has been selected */
+ else
+ {
+ /* Check if PLL is ready */
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
+ {
+ /* Frequency is the PLL frequency divided by ADC prescaler (1U/2U/4U/6U/8U/10U/12U/16U/32U/64U/128U/256U) */
+ frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> POSITION_VAL(RCC_CFGR2_ADC1PRES)) & 0xFU];
+ }
+ }
+#else /* RCC_CFGR_ADCPRE */
+ /* ADC1 is set to PLCK2 frequency divided by 2U/4U/6U/8U */
+ frequency = HAL_RCC_GetPCLK2Freq() / (((srcclk >> POSITION_VAL(RCC_CFGR_ADCPRE)) + 1U) * 2U);
+#endif /* RCC_CFGR2_ADC1PRES */
+ break;
+ }
+#endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR_ADCPRE */
+#if defined(RCC_CFGR2_ADCPRE12)
+ case RCC_PERIPHCLK_ADC12:
+ {
+ /* Get the current ADC12 source */
+ srcclk = __HAL_RCC_GET_ADC12_SOURCE();
+ /* Check if ADC12 clock selection is AHB */
+ if (srcclk == RCC_ADC12PLLCLK_OFF)
+ {
+ frequency = SystemCoreClock;
+ }
+ /* PLL clock has been selected */
+ else
+ {
+ /* Check if PLL is ready */
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
+ {
+ /* Frequency is the PLL frequency divided by ADC prescaler (1U/2U/4U/6/8U/10U/12U/16U/32U/64U/128U/256U) */
+ frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> POSITION_VAL(RCC_CFGR2_ADCPRE12)) & 0xF];
+ }
+ }
+ break;
+ }
+#endif /* RCC_CFGR2_ADCPRE12 */
+#if defined(RCC_CFGR2_ADCPRE34)
+ case RCC_PERIPHCLK_ADC34:
+ {
+ /* Get the current ADC34 source */
+ srcclk = __HAL_RCC_GET_ADC34_SOURCE();
+ /* Check if ADC34 clock selection is AHB */
+ if (srcclk == RCC_ADC34PLLCLK_OFF)
+ {
+ frequency = SystemCoreClock;
+ }
+ /* PLL clock has been selected */
+ else
+ {
+ /* Check if PLL is ready */
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
+ {
+ /* Frequency is the PLL frequency divided by ADC prescaler (1U/2U/4U/6U/8U/10U/12U/16U/32U/64U/128U/256U) */
+ frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> POSITION_VAL(RCC_CFGR2_ADCPRE34)) & 0xF];
+ }
+ }
+ break;
+ }
+#endif /* RCC_CFGR2_ADCPRE34 */
+#if defined(RCC_CFGR3_TIM1SW)
+ case RCC_PERIPHCLK_TIM1:
+ {
+ /* Get the current TIM1 source */
+ srcclk = __HAL_RCC_GET_TIM1_SOURCE();
+
+ /* Check if PLL is ready and if TIM1 clock selection is PLL */
+ if ((srcclk == RCC_TIM1CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
+ {
+ frequency = RCC_GetPLLCLKFreq();
+ }
+ /* Check if TIM1 clock selection is SYSCLK */
+ else if (srcclk == RCC_TIM1CLK_HCLK)
+ {
+ frequency = SystemCoreClock;
+ }
+ break;
+ }
+#endif /* RCC_CFGR3_TIM1SW */
+#if defined(RCC_CFGR3_TIM2SW)
+ case RCC_PERIPHCLK_TIM2:
+ {
+ /* Get the current TIM2 source */
+ srcclk = __HAL_RCC_GET_TIM2_SOURCE();
+
+ /* Check if PLL is ready and if TIM2 clock selection is PLL */
+ if ((srcclk == RCC_TIM2CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
+ {
+ frequency = RCC_GetPLLCLKFreq();
+ }
+ /* Check if TIM2 clock selection is SYSCLK */
+ else if (srcclk == RCC_TIM2CLK_HCLK)
+ {
+ frequency = SystemCoreClock;
+ }
+ break;
+ }
+#endif /* RCC_CFGR3_TIM2SW */
+#if defined(RCC_CFGR3_TIM8SW)
+ case RCC_PERIPHCLK_TIM8:
+ {
+ /* Get the current TIM8 source */
+ srcclk = __HAL_RCC_GET_TIM8_SOURCE();
+
+ /* Check if PLL is ready and if TIM8 clock selection is PLL */
+ if ((srcclk == RCC_TIM8CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
+ {
+ frequency = RCC_GetPLLCLKFreq();
+ }
+ /* Check if TIM8 clock selection is SYSCLK */
+ else if (srcclk == RCC_TIM8CLK_HCLK)
+ {
+ frequency = SystemCoreClock;
+ }
+ break;
+ }
+#endif /* RCC_CFGR3_TIM8SW */
+#if defined(RCC_CFGR3_TIM15SW)
+ case RCC_PERIPHCLK_TIM15:
+ {
+ /* Get the current TIM15 source */
+ srcclk = __HAL_RCC_GET_TIM15_SOURCE();
+
+ /* Check if PLL is ready and if TIM15 clock selection is PLL */
+ if ((srcclk == RCC_TIM15CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
+ {
+ frequency = RCC_GetPLLCLKFreq();
+ }
+ /* Check if TIM15 clock selection is SYSCLK */
+ else if (srcclk == RCC_TIM15CLK_HCLK)
+ {
+ frequency = SystemCoreClock;
+ }
+ break;
+ }
+#endif /* RCC_CFGR3_TIM15SW */
+#if defined(RCC_CFGR3_TIM16SW)
+ case RCC_PERIPHCLK_TIM16:
+ {
+ /* Get the current TIM16 source */
+ srcclk = __HAL_RCC_GET_TIM16_SOURCE();
+
+ /* Check if PLL is ready and if TIM16 clock selection is PLL */
+ if ((srcclk == RCC_TIM16CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
+ {
+ frequency = RCC_GetPLLCLKFreq();
+ }
+ /* Check if TIM16 clock selection is SYSCLK */
+ else if (srcclk == RCC_TIM16CLK_HCLK)
+ {
+ frequency = SystemCoreClock;
+ }
+ break;
+ }
+#endif /* RCC_CFGR3_TIM16SW */
+#if defined(RCC_CFGR3_TIM17SW)
+ case RCC_PERIPHCLK_TIM17:
+ {
+ /* Get the current TIM17 source */
+ srcclk = __HAL_RCC_GET_TIM17_SOURCE();
+
+ /* Check if PLL is ready and if TIM17 clock selection is PLL */
+ if ((srcclk == RCC_TIM17CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
+ {
+ frequency = RCC_GetPLLCLKFreq();
+ }
+ /* Check if TIM17 clock selection is SYSCLK */
+ else if (srcclk == RCC_TIM17CLK_HCLK)
+ {
+ frequency = SystemCoreClock;
+ }
+ break;
+ }
+#endif /* RCC_CFGR3_TIM17SW */
+#if defined(RCC_CFGR3_TIM20SW)
+ case RCC_PERIPHCLK_TIM20:
+ {
+ /* Get the current TIM20 source */
+ srcclk = __HAL_RCC_GET_TIM20_SOURCE();
+
+ /* Check if PLL is ready and if TIM20 clock selection is PLL */
+ if ((srcclk == RCC_TIM20CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
+ {
+ frequency = RCC_GetPLLCLKFreq();
+ }
+ /* Check if TIM20 clock selection is SYSCLK */
+ else if (srcclk == RCC_TIM20CLK_HCLK)
+ {
+ frequency = SystemCoreClock;
+ }
+ break;
+ }
+#endif /* RCC_CFGR3_TIM20SW */
+#if defined(RCC_CFGR3_TIM34SW)
+ case RCC_PERIPHCLK_TIM34:
+ {
+ /* Get the current TIM34 source */
+ srcclk = __HAL_RCC_GET_TIM34_SOURCE();
+
+ /* Check if PLL is ready and if TIM34 clock selection is PLL */
+ if ((srcclk == RCC_TIM34CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
+ {
+ frequency = RCC_GetPLLCLKFreq();
+ }
+ /* Check if TIM34 clock selection is SYSCLK */
+ else if (srcclk == RCC_TIM34CLK_HCLK)
+ {
+ frequency = SystemCoreClock;
+ }
+ break;
+ }
+#endif /* RCC_CFGR3_TIM34SW */
+#if defined(RCC_CFGR3_HRTIM1SW)
+ case RCC_PERIPHCLK_HRTIM1:
+ {
+ /* Get the current HRTIM1 source */
+ srcclk = __HAL_RCC_GET_HRTIM1_SOURCE();
+
+ /* Check if PLL is ready and if HRTIM1 clock selection is PLL */
+ if ((srcclk == RCC_HRTIM1CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
+ {
+ frequency = RCC_GetPLLCLKFreq();
+ }
+ /* Check if HRTIM1 clock selection is SYSCLK */
+ else if (srcclk == RCC_HRTIM1CLK_HCLK)
+ {
+ frequency = SystemCoreClock;
+ }
+ break;
+ }
+#endif /* RCC_CFGR3_HRTIM1SW */
+#if defined(RCC_CFGR_SDPRE)
+ case RCC_PERIPHCLK_SDADC:
+ {
+ /* Get the current SDADC source */
+ srcclk = __HAL_RCC_GET_SDADC_SOURCE();
+ /* Frequency is the system frequency divided by SDADC prescaler (2U/4U/6U/8U/10U/12U/14U/16U/20U/24U/28U/32U/36U/40U/44U/48U) */
+ frequency = SystemCoreClock / sdadc_prescaler_table[(srcclk >> POSITION_VAL(RCC_CFGR_SDPRE)) & 0xF];
+ break;
+ }
+#endif /* RCC_CFGR_SDPRE */
+#if defined(RCC_CFGR3_CECSW)
+ case RCC_PERIPHCLK_CEC:
+ {
+ /* Get the current CEC source */
+ srcclk = __HAL_RCC_GET_CEC_SOURCE();
+
+ /* Check if HSI is ready and if CEC clock selection is HSI */
+ if ((srcclk == RCC_CECCLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
+ {
+ frequency = HSI_VALUE;
+ }
+ /* Check if LSE is ready and if CEC clock selection is LSE */
+ else if ((srcclk == RCC_CECCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
+ {
+ frequency = LSE_VALUE;
+ }
+ break;
+ }
+#endif /* RCC_CFGR3_CECSW */
+ default:
+ {
+ break;
+ }
+ }
+ return(frequency);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34) || defined(RCC_CFGR_USBPRE) \
+ || defined(RCC_CFGR3_TIM1SW) || defined(RCC_CFGR3_TIM2SW) || defined(RCC_CFGR3_TIM8SW) || defined(RCC_CFGR3_TIM15SW) \
+ || defined(RCC_CFGR3_TIM16SW) || defined(RCC_CFGR3_TIM17SW) || defined(RCC_CFGR3_TIM20SW) || defined(RCC_CFGR3_TIM34SW) \
+ || defined(RCC_CFGR3_HRTIM1SW)
+
+/** @addtogroup RCCEx_Private_Functions
+ * @{
+ */
+static uint32_t RCC_GetPLLCLKFreq(void)
+{
+ uint32_t pllmul = 0U, pllsource = 0U, prediv = 0U, pllclk = 0U;
+
+ pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
+ pllmul = ( pllmul >> 18U) + 2U;
+ pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
+ if (pllsource != RCC_PLLSOURCE_HSI)
+ {
+ prediv = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1U;
+ /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
+ pllclk = (HSE_VALUE/prediv) * pllmul;
+ }
+ else
+ {
+ /* HSI used as PLL clock source : PLLCLK = HSI/2U * PLLMUL */
+ pllclk = (HSI_VALUE >> 1U) * pllmul;
+ }
+#else
+ prediv = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1U;
+ if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
+ {
+ /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
+ pllclk = (HSE_VALUE/prediv) * pllmul;
+ }
+ else
+ {
+ /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */
+ pllclk = (HSI_VALUE/prediv) * pllmul;
+ }
+#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
+
+ return pllclk;
+}
+/**
+ * @}
+ */
+
+#endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRExx || RCC_CFGR3_TIMxSW || RCC_CFGR3_HRTIM1SW || RCC_CFGR_USBPRE */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_rtc.c b/Src/stm32f3xx_hal_rtc.c
new file mode 100644
index 0000000..1e9f875
--- /dev/null
+++ b/Src/stm32f3xx_hal_rtc.c
@@ -0,0 +1,1588 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_rtc.c
+ * @author MCD Application Team
+ * @brief RTC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Real-Time Clock (RTC) peripheral:
+ * + Initialization
+ * + Calendar (Time and Date) configuration
+ * + Alarms (Alarm A and Alarm B) configuration
+ * + WakeUp Timer configuration
+ * + TimeStamp configuration
+ * + Tampers configuration
+ * + Backup Data Registers configuration
+ * + RTC Tamper and TimeStamp Pins Selection
+ * + Interrupts and flags management
+ *
+ @verbatim
+
+ ===============================================================================
+ ##### RTC Operating Condition #####
+ ===============================================================================
+ [..] The real-time clock (RTC) and the RTC backup registers can be powered
+ from the VBAT voltage when the main VDD supply is powered off.
+ To retain the content of the RTC backup registers and supply the RTC
+ when VDD is turned off, VBAT pin can be connected to an optional
+ standby voltage supplied by a battery or by another source.
+
+ [..] To allow the RTC to operate even when the main digital supply (VDD)
+ is turned off, the VBAT pin powers the following blocks:
+ (#) The RTC
+ (#) The LSE oscillator
+ (#) PC13 to PC15 I/Os (when available)
+
+ [..] When the backup domain is supplied by VDD (analog switch connected
+ to VDD), the following functions are available:
+ (#) PC14 and PC15 can be used as either GPIO or LSE pins
+ (#) PC13 can be used as a GPIO or as the RTC_OUT pin
+
+ [..] When the backup domain is supplied by VBAT (analog switch connected
+ to VBAT because VDD is not present), the following functions are available:
+ (#) PC14 and PC15 can be used as LSE pins only
+ (#) PC13 can be used as the RTC_OUT pin
+
+ ##### Backup Domain Reset #####
+ ===============================================================================
+ [..] The backup domain reset sets all RTC registers and the RCC_BDCR
+ register to their reset values.
+ A backup domain reset is generated when one of the following events
+ occurs:
+ (#) Software reset, triggered by setting the BDRST bit in the
+ RCC Backup domain control register (RCC_BDCR).
+ (#) VDD or VBAT power on, if both supplies have previously been
+ powered off.
+
+ ##### Backup Domain Access #####
+ ===================================================================
+ [..] After reset, the backup domain (RTC registers, RTC backup data
+ registers and backup SRAM) is protected against possible unwanted write
+ accesses.
+
+ [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
+ (#) Enable the Power Controller (PWR) APB1 interface clock using the
+ __HAL_RCC_PWR_CLK_ENABLE() function.
+ (#) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
+ (#) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function.
+ (#) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function.
+
+
+ ##### How to use RTC Driver #####
+ ===================================================================
+ [..]
+ (+) Enable the RTC domain access (see description in the section above).
+ (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
+ format using the HAL_RTC_Init() function.
+
+ *** Time and Date configuration ***
+ ===================================
+ [..]
+ (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime()
+ and HAL_RTC_SetDate() functions.
+ (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions.
+
+ *** Alarm configuration ***
+ ===========================
+ [..]
+ (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function.
+ You can also configure the RTC Alarm with interrupt mode using the
+ HAL_RTC_SetAlarm_IT() function.
+ (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.
+
+ *** RTC Wakeup configuration ***
+ ================================
+ [..]
+ (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTC_SetWakeUpTimer()
+ function. You can also configure the RTC Wakeup timer with interrupt mode
+ using the HAL_RTC_SetWakeUpTimer_IT() function.
+ (+) To read the RTC WakeUp Counter register, use the HAL_RTC_GetWakeUpTimer()
+ function.
+
+ *** TimeStamp configuration ***
+ ===============================
+ [..]
+ (+) Configure the RTC_AF trigger and enables the RTC TimeStamp using the
+ HAL_RTC_SetTimeStamp() function. You can also configure the RTC TimeStamp with
+ interrupt mode using the HAL_RTC_SetTimeStamp_IT() function.
+ (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTC_GetTimeStamp()
+ function.
+
+ *** Tamper configuration ***
+ ============================
+ [..]
+ (+) Enable the RTC Tamper and Configure the Tamper filter count, trigger Edge
+ or Level according to the Tamper filter (if equal to 0 Edge else Level)
+ value, sampling frequency, precharge or discharge and Pull-UP using the
+ HAL_RTC_SetTamper() function. You can configure RTC Tamper with interrupt
+ mode using HAL_RTC_SetTamper_IT() function.
+
+ *** Backup Data Registers configuration ***
+ ===========================================
+ [..]
+ (+) To write to the RTC Backup Data registers, use the HAL_RTC_BKUPWrite()
+ function.
+ (+) To read the RTC Backup Data registers, use the HAL_RTC_BKUPRead()
+ function.
+
+
+ ##### RTC and low power modes #####
+ ===================================================================
+ [..] The MCU can be woken up from a low power mode by an RTC alternate
+ function.
+ [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
+ RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
+ These RTC alternate functions can wake up the system from the Stop and
+ Standby low power modes.
+ [..] The system can also wake up from low power modes without depending
+ on an external interrupt (Auto-wakeup mode), by using the RTC alarm
+ or the RTC wakeup events.
+ [..] The RTC provides a programmable time base for waking up from the
+ Stop or Standby mode at regular intervals.
+ Wakeup from STOP and Standby modes is possible only when the RTC clock source
+ is LSE or LSI.
+
+ @endverbatim
+
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup RTC
+ * @brief RTC HAL module driver
+ * @{
+ */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+
+/** @addtogroup RTC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup RTC_Exported_Functions_Group1
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to initialize and configure the
+ RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable
+ RTC registers Write protection, enter and exit the RTC initialization mode,
+ RTC registers synchronization check and reference clock detection enable.
+ (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
+ It is split into 2 programmable prescalers to minimize power consumption.
+ (++) A 7-bit asynchronous prescaler and a 15-bit synchronous prescaler.
+ (++) When both prescalers are used, it is recommended to configure the
+ asynchronous prescaler to a high value to minimize power consumption.
+ (#) All RTC registers are Write protected. Writing to the RTC registers
+ is enabled by writing a key into the Write Protection register, RTC_WPR.
+ (#) To configure the RTC Calendar, user application should enter
+ initialization mode. In this mode, the calendar counter is stopped
+ and its value can be updated. When the initialization sequence is
+ complete, the calendar restarts counting after 4 RTCCLK cycles.
+ (#) To read the calendar through the shadow registers after Calendar
+ initialization, calendar update or after wakeup from low power modes
+ the software must first clear the RSF flag. The software must then
+ wait until it is set again before reading the calendar, which means
+ that the calendar registers have been correctly copied into the
+ RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function
+ implements the above software sequence (RSF clear and RSF check).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the RTC according to the specified parameters
+ * in the RTC_InitTypeDef structure and initialize the associated handle.
+ * @param hrtc RTC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
+{
+ /* Check the RTC peripheral state */
+ if(hrtc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
+ assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat));
+ assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv));
+ assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv));
+ assert_param(IS_RTC_OUTPUT(hrtc->Init.OutPut));
+ assert_param(IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity));
+ assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType));
+
+ if(hrtc->State == HAL_RTC_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hrtc->Lock = HAL_UNLOCKED;
+
+ /* Initialize RTC MSP */
+ HAL_RTC_MspInit(hrtc);
+ }
+
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Set Initialization mode */
+ if(RTC_EnterInitMode(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Clear RTC_CR FMT, OSEL and POL Bits */
+ hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL));
+ /* Set RTC_CR register */
+ hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
+
+ /* Configure the RTC PRER */
+ hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv);
+ hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16U);
+
+ /* Exit Initialization mode */
+ hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
+
+ /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+ if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
+ {
+ if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+ }
+
+ hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_ALARMOUTTYPE;
+ hrtc->Instance->TAFCR |= (uint32_t)(hrtc->Init.OutPutType);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ return HAL_OK;
+ }
+}
+
+/**
+ * @brief DeInitialize the RTC peripheral.
+ * @param hrtc RTC handle
+ * @note This function doesn't reset the RTC Backup Data registers.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
+{
+ uint32_t tickstart = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
+
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Set Initialization mode */
+ if(RTC_EnterInitMode(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Reset TR, DR and CR registers */
+ hrtc->Instance->TR = 0x00000000U;
+ hrtc->Instance->DR = (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0);
+ /* Reset All CR bits except CR[2:0] */
+ hrtc->Instance->CR &= RTC_CR_WUCKSEL;
+
+ tickstart = HAL_GetTick();
+
+ /* Wait till WUTWF flag is set and if Time out is reached exit */
+ while(((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == (uint32_t)RESET)
+ {
+ if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Reset all RTC CR register bits */
+ hrtc->Instance->CR &= 0x00000000U;
+ hrtc->Instance->WUTR = RTC_WUTR_WUT;
+ hrtc->Instance->PRER = ((uint32_t)(RTC_PRER_PREDIV_A | 0x000000FFU));
+ hrtc->Instance->ALRMAR = 0x00000000U;
+ hrtc->Instance->ALRMBR = 0x00000000U;
+ hrtc->Instance->SHIFTR = 0x00000000U;
+ hrtc->Instance->CALR = 0x00000000U;
+ hrtc->Instance->ALRMASSR = 0x00000000U;
+ hrtc->Instance->ALRMBSSR = 0x00000000U;
+
+ /* Reset ISR register and exit initialization mode */
+ hrtc->Instance->ISR = 0x00000000U;
+
+ /* Reset Tamper and alternate functions configuration register */
+ hrtc->Instance->TAFCR = 0x00000000U;
+
+ /* If RTC_CR_BYPSHAD bit = 0U, wait for synchro else this check is not needed */
+ if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
+ {
+ if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* De-Initialize RTC MSP */
+ HAL_RTC_MspDeInit(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the RTC MSP.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+__weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RTC_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the RTC MSP.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RTC_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Exported_Functions_Group2
+ * @brief RTC Time and Date functions
+ *
+@verbatim
+ ===============================================================================
+ ##### RTC Time and Date functions #####
+ ===============================================================================
+
+ [..] This section provides functions allowing to configure Time and Date features
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Set RTC current time.
+ * @param hrtc RTC handle
+ * @param sTime Pointer to Time structure
+ * @param Format Specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
+{
+ uint32_t tmpreg = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+ assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving));
+ assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ if(Format == RTC_FORMAT_BIN)
+ {
+ if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+ {
+ assert_param(IS_RTC_HOUR12(sTime->Hours));
+ assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
+ }
+ else
+ {
+ sTime->TimeFormat = 0x00U;
+ assert_param(IS_RTC_HOUR24(sTime->Hours));
+ }
+ assert_param(IS_RTC_MINUTES(sTime->Minutes));
+ assert_param(IS_RTC_SECONDS(sTime->Seconds));
+
+ tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16U) | \
+ ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8U) | \
+ ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \
+ (((uint32_t)sTime->TimeFormat) << 16U));
+ }
+ else
+ {
+ if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+ {
+ tmpreg = RTC_Bcd2ToByte(sTime->Hours);
+ assert_param(IS_RTC_HOUR12(tmpreg));
+ assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
+ }
+ else
+ {
+ sTime->TimeFormat = 0x00U;
+ assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours)));
+ }
+ assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes)));
+ assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds)));
+ tmpreg = (((uint32_t)(sTime->Hours) << 16U) | \
+ ((uint32_t)(sTime->Minutes) << 8U) | \
+ ((uint32_t)sTime->Seconds) | \
+ ((uint32_t)(sTime->TimeFormat) << 16U));
+ }
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Set Initialization mode */
+ if(RTC_EnterInitMode(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Set the RTC_TR register */
+ hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
+
+ /* Clear the bits to be configured */
+ hrtc->Instance->CR &= ((uint32_t)~RTC_CR_BCK);
+
+ /* Configure the RTC_CR register */
+ hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation);
+
+ /* Exit Initialization mode */
+ hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT);
+
+ /* If CR_BYPSHAD bit = 0U, wait for synchro else this check is not needed */
+ if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
+ {
+ if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+ }
+}
+
+/**
+ * @brief Get RTC current time.
+ * @param hrtc RTC handle
+ * @param sTime Pointer to Time structure
+ * @param Format Specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @note You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds
+ * value in second fraction ratio with time unit following generic formula:
+ * Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
+ * This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS
+ * @note Call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
+ * in the higher-order calendar shadow registers.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
+{
+ uint32_t tmpreg = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+
+ /* Get subseconds structure field from the corresponding register*/
+ sTime->SubSeconds = (uint32_t)(hrtc->Instance->SSR);
+
+ /* Get SecondFraction structure field from the corresponding register field*/
+ sTime->SecondFraction = (uint32_t)(hrtc->Instance->PRER & RTC_PRER_PREDIV_S);
+
+ /* Get the TR register */
+ tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK);
+
+ /* Fill the structure fields with the read parameters */
+ sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16U);
+ sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8U);
+ sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));
+ sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16U);
+
+ /* Check the input parameters format */
+ if(Format == RTC_FORMAT_BIN)
+ {
+ /* Convert the time structure parameters to Binary format */
+ sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours);
+ sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes);
+ sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set RTC current date.
+ * @param hrtc RTC handle
+ * @param sDate Pointer to date structure
+ * @param Format specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
+{
+ uint32_t datetmpreg = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U))
+ {
+ sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU);
+ }
+
+ assert_param(IS_RTC_WEEKDAY(sDate->WeekDay));
+
+ if(Format == RTC_FORMAT_BIN)
+ {
+ assert_param(IS_RTC_YEAR(sDate->Year));
+ assert_param(IS_RTC_MONTH(sDate->Month));
+ assert_param(IS_RTC_DATE(sDate->Date));
+
+ datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16U) | \
+ ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8U) | \
+ ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \
+ ((uint32_t)sDate->WeekDay << 13U));
+ }
+ else
+ {
+ assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year)));
+ assert_param(IS_RTC_MONTH(RTC_Bcd2ToByte(sDate->Month)));
+ assert_param(IS_RTC_DATE(RTC_Bcd2ToByte(sDate->Date)));
+
+ datetmpreg = ((((uint32_t)sDate->Year) << 16U) | \
+ (((uint32_t)sDate->Month) << 8U) | \
+ ((uint32_t)sDate->Date) | \
+ (((uint32_t)sDate->WeekDay) << 13U));
+ }
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Set Initialization mode */
+ if(RTC_EnterInitMode(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Set RTC state*/
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Set the RTC_DR register */
+ hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK);
+
+ /* Exit Initialization mode */
+ hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT);
+
+ /* If CR_BYPSHAD bit = 0U, wait for synchro else this check is not needed */
+ if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
+ {
+ if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY ;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+ }
+}
+
+/**
+ * @brief Get RTC current date.
+ * @param hrtc RTC handle
+ * @param sDate Pointer to Date structure
+ * @param Format Specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN : Binary data format
+ * @arg RTC_FORMAT_BCD : BCD data format
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
+{
+ uint32_t datetmpreg = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+
+ /* Get the DR register */
+ datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK);
+
+ /* Fill the structure fields with the read parameters */
+ sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16U);
+ sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8U);
+ sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU));
+ sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13U);
+
+ /* Check the input parameters format */
+ if(Format == RTC_FORMAT_BIN)
+ {
+ /* Convert the date structure parameters to Binary format */
+ sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year);
+ sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month);
+ sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date);
+ }
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Exported_Functions_Group3
+ * @brief RTC Alarm functions
+ *
+@verbatim
+ ===============================================================================
+ ##### RTC Alarm functions #####
+ ===============================================================================
+
+ [..] This section provides functions allowing to configure Alarm feature
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Set the specified RTC Alarm.
+ * @param hrtc RTC handle
+ * @param sAlarm Pointer to Alarm structure
+ * @param Format Specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
+{
+ uint32_t tickstart = 0U;
+ uint32_t tmpreg = 0U, subsecondtmpreg = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+ assert_param(IS_RTC_ALARM(sAlarm->Alarm));
+ assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
+ assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
+ assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ if(Format == RTC_FORMAT_BIN)
+ {
+ if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+ {
+ assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
+ assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
+ }
+ else
+ {
+ sAlarm->AlarmTime.TimeFormat = 0x00U;
+ assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
+ }
+ assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
+ assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
+
+ if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+ {
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
+ }
+ else
+ {
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
+ }
+
+ tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \
+ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
+ ((uint32_t)sAlarm->AlarmMask));
+ }
+ else
+ {
+ if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+ {
+ tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
+ assert_param(IS_RTC_HOUR12(tmpreg));
+ assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
+ }
+ else
+ {
+ sAlarm->AlarmTime.TimeFormat = 0x00U;
+ assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
+ }
+
+ assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
+ assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
+
+ if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+ {
+ tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));
+ }
+ else
+ {
+ tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));
+ }
+
+ tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \
+ ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \
+ ((uint32_t) sAlarm->AlarmTime.Seconds) | \
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
+ ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \
+ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
+ ((uint32_t)sAlarm->AlarmMask));
+ }
+
+ /* Configure the Alarm A or Alarm B Sub Second registers */
+ subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Configure the Alarm register */
+ if(sAlarm->Alarm == RTC_ALARM_A)
+ {
+ /* Disable the Alarm A interrupt */
+ __HAL_RTC_ALARMA_DISABLE(hrtc);
+
+ /* In case of interrupt mode is used, the interrupt source must disabled */
+ __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
+
+ tickstart = HAL_GetTick();
+ /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
+ while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
+ {
+ if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
+ /* Configure the Alarm A Sub Second register */
+ hrtc->Instance->ALRMASSR = subsecondtmpreg;
+ /* Configure the Alarm state: Enable Alarm */
+ __HAL_RTC_ALARMA_ENABLE(hrtc);
+ }
+ else
+ {
+ /* Disable the Alarm B interrupt */
+ __HAL_RTC_ALARMB_DISABLE(hrtc);
+
+ /* In case of interrupt mode is used, the interrupt source must disabled */
+ __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB);
+
+ tickstart = HAL_GetTick();
+ /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
+ while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
+ {
+ if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
+ /* Configure the Alarm B Sub Second register */
+ hrtc->Instance->ALRMBSSR = subsecondtmpreg;
+ /* Configure the Alarm state: Enable Alarm */
+ __HAL_RTC_ALARMB_ENABLE(hrtc);
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the specified RTC Alarm with Interrupt.
+ * @param hrtc RTC handle
+ * @param sAlarm Pointer to Alarm structure
+ * @param Format Specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @note The Alarm register can only be written when the corresponding Alarm
+ * is disabled (Use the HAL_RTC_DeactivateAlarm()).
+ * @note The HAL_RTC_SetTime() must be called before enabling the Alarm feature.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
+{
+ uint32_t tickstart = 0U;
+ uint32_t tmpreg = 0U, subsecondtmpreg = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+ assert_param(IS_RTC_ALARM(sAlarm->Alarm));
+ assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
+ assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
+ assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ if(Format == RTC_FORMAT_BIN)
+ {
+ if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+ {
+ assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
+ assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
+ }
+ else
+ {
+ sAlarm->AlarmTime.TimeFormat = 0x00U;
+ assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
+ }
+ assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
+ assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
+
+ if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+ {
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
+ }
+ else
+ {
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
+ }
+ tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \
+ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
+ ((uint32_t)sAlarm->AlarmMask));
+ }
+ else
+ {
+ if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+ {
+ tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
+ assert_param(IS_RTC_HOUR12(tmpreg));
+ assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
+ }
+ else
+ {
+ sAlarm->AlarmTime.TimeFormat = 0x00U;
+ assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
+ }
+
+ assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
+ assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
+
+ if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+ {
+ tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));
+ }
+ else
+ {
+ tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));
+ }
+ tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \
+ ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \
+ ((uint32_t) sAlarm->AlarmTime.Seconds) | \
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
+ ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \
+ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
+ ((uint32_t)sAlarm->AlarmMask));
+ }
+ /* Configure the Alarm A or Alarm B Sub Second registers */
+ subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Configure the Alarm register */
+ if(sAlarm->Alarm == RTC_ALARM_A)
+ {
+ /* Disable the Alarm A interrupt */
+ __HAL_RTC_ALARMA_DISABLE(hrtc);
+
+ /* Clear flag alarm A */
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
+
+ tickstart = HAL_GetTick();
+ /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
+ while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
+ {
+ if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
+ /* Configure the Alarm A Sub Second register */
+ hrtc->Instance->ALRMASSR = subsecondtmpreg;
+ /* Configure the Alarm state: Enable Alarm */
+ __HAL_RTC_ALARMA_ENABLE(hrtc);
+ /* Configure the Alarm interrupt */
+ __HAL_RTC_ALARM_ENABLE_IT(hrtc,RTC_IT_ALRA);
+ }
+ else
+ {
+ /* Disable the Alarm B interrupt */
+ __HAL_RTC_ALARMB_DISABLE(hrtc);
+
+ /* Clear flag alarm B */
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
+
+ tickstart = HAL_GetTick();
+ /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
+ while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
+ {
+ if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
+ /* Configure the Alarm B Sub Second register */
+ hrtc->Instance->ALRMBSSR = subsecondtmpreg;
+ /* Configure the Alarm state: Enable Alarm */
+ __HAL_RTC_ALARMB_ENABLE(hrtc);
+ /* Configure the Alarm interrupt */
+ __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRB);
+ }
+
+ /* RTC Alarm Interrupt Configuration: EXTI configuration */
+ __HAL_RTC_ALARM_EXTI_ENABLE_IT();
+
+ __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Deactivate the specified RTC Alarm.
+ * @param hrtc RTC handle
+ * @param Alarm Specifies the Alarm.
+ * This parameter can be one of the following values:
+ * @arg RTC_ALARM_A : AlarmA
+ * @arg RTC_ALARM_B : AlarmB
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm)
+{
+ uint32_t tickstart = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_ALARM(Alarm));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ if(Alarm == RTC_ALARM_A)
+ {
+ /* AlarmA */
+ __HAL_RTC_ALARMA_DISABLE(hrtc);
+
+ /* In case of interrupt mode is used, the interrupt source must disabled */
+ __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
+
+ tickstart = HAL_GetTick();
+
+ /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
+ while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
+ {
+ if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* AlarmB */
+ __HAL_RTC_ALARMB_DISABLE(hrtc);
+
+ /* In case of interrupt mode is used, the interrupt source must disabled */
+ __HAL_RTC_ALARM_DISABLE_IT(hrtc,RTC_IT_ALRB);
+
+ tickstart = HAL_GetTick();
+
+ /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
+ while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
+ {
+ if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get the RTC Alarm value and masks.
+ * @param hrtc RTC handle
+ * @param sAlarm Pointer to Date structure
+ * @param Alarm Specifies the Alarm.
+ * This parameter can be one of the following values:
+ * @arg RTC_ALARM_A: AlarmA
+ * @arg RTC_ALARM_B: AlarmB
+ * @param Format Specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
+{
+ uint32_t tmpreg = 0U, subsecondtmpreg = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+ assert_param(IS_RTC_ALARM(Alarm));
+
+ if(Alarm == RTC_ALARM_A)
+ {
+ /* AlarmA */
+ sAlarm->Alarm = RTC_ALARM_A;
+
+ tmpreg = (uint32_t)(hrtc->Instance->ALRMAR);
+ subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR ) & RTC_ALRMASSR_SS);
+ }
+ else
+ {
+ sAlarm->Alarm = RTC_ALARM_B;
+
+ tmpreg = (uint32_t)(hrtc->Instance->ALRMBR);
+ subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMBSSR) & RTC_ALRMBSSR_SS);
+ }
+
+ /* Fill the structure with the read parameters */
+ sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16U);
+ sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8U);
+ sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU));
+ sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16U);
+ sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg;
+ sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24U);
+ sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
+ sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL);
+
+ if(Format == RTC_FORMAT_BIN)
+ {
+ sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
+ sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes);
+ sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds);
+ sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle Alarm interrupt request.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
+{
+ /* Get the AlarmA interrupt source enable status */
+ if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != RESET)
+ {
+ /* Get the pending status of the AlarmA Interrupt */
+ if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != RESET)
+ {
+ /* AlarmA callback */
+ HAL_RTC_AlarmAEventCallback(hrtc);
+
+ /* Clear the AlarmA interrupt pending bit */
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRAF);
+ }
+ }
+
+ /* Get the AlarmB interrupt source enable status */
+ if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRB) != RESET)
+ {
+ /* Get the pending status of the AlarmB Interrupt */
+ if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) != RESET)
+ {
+ /* AlarmB callback */
+ HAL_RTCEx_AlarmBEventCallback(hrtc);
+
+ /* Clear the AlarmB interrupt pending bit */
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRBF);
+ }
+ }
+
+ /* Clear the EXTI's line Flag for RTC Alarm */
+ __HAL_RTC_ALARM_EXTI_CLEAR_FLAG();
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+}
+
+/**
+ * @brief Alarm A callback.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RTC_AlarmAEventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Handle AlarmA Polling request.
+ * @param hrtc RTC handle
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{
+
+ uint32_t tickstart = HAL_GetTick();
+
+ while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Clear the Alarm interrupt pending bit */
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @@addtogroup RTC_Exported_Functions_Group4 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Wait for RTC Time and Date Synchronization
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are
+ * synchronized with RTC APB clock.
+ * @note The RTC Resynchronization mode is write protected, use the
+ * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
+ * @note To read the calendar through the shadow registers after Calendar
+ * initialization, calendar update or after wakeup from low power modes
+ * the software must first clear the RSF flag.
+ * The software must then wait until it is set again before reading
+ * the calendar, which means that the calendar registers have been
+ * correctly copied into the RTC_TR and RTC_DR shadow registers.
+ * @param hrtc RTC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc)
+{
+ uint32_t tickstart = 0U;
+
+ /* Clear RSF flag */
+ hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK;
+
+ tickstart = HAL_GetTick();
+
+ /* Wait the registers to be synchronised */
+ while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET)
+ {
+ if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @@addtogroup RTC_Exported_Functions_Group5 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Get RTC state
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Return the RTC handle state.
+ * @param hrtc RTC handle
+ * @retval HAL state
+ */
+HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc)
+{
+ /* Return RTC handle state */
+ return hrtc->State;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @@addtogroup RTC_Private_Functions RTC Private Functions
+ * @{
+ */
+
+/**
+ * @brief Enter the RTC Initialization mode.
+ * @note The RTC Initialization mode is write protected, use the
+ * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
+ * @param hrtc RTC handle
+ * @retval An ErrorStatus enumeration value:
+ * - HAL_OK : RTC is in Init mode
+ * - HAL_TIMEOUT : RTC is not in Init mode and in Timeout
+ */
+HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc)
+{
+ uint32_t tickstart = 0U;
+
+ /* Check if the Initialization mode is set */
+ if((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
+ {
+ /* Set the Initialization mode */
+ hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK;
+
+ tickstart = HAL_GetTick();
+ /* Wait till RTC is in INIT state and if Time out is reached exit */
+ while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
+ {
+ if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Convert a 2 digit decimal to BCD format.
+ * @param Value Byte to be converted
+ * @retval Converted byte
+ */
+uint8_t RTC_ByteToBcd2(uint8_t Value)
+{
+ uint32_t bcdhigh = 0U;
+
+ while(Value >= 10U)
+ {
+ bcdhigh++;
+ Value -= 10U;
+ }
+
+ return ((uint8_t)(bcdhigh << 4U) | Value);
+}
+
+/**
+ * @brief Convert from 2 digit BCD to Binary.
+ * @param Value BCD value to be converted
+ * @retval Converted word
+ */
+uint8_t RTC_Bcd2ToByte(uint8_t Value)
+{
+ uint32_t tmp = 0U;
+ tmp = ((uint8_t)(Value & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U;
+ return (tmp + (Value & (uint8_t)0x0FU));
+}
+/**
+ * @}
+ */
+
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_rtc_ex.c b/Src/stm32f3xx_hal_rtc_ex.c
new file mode 100644
index 0000000..9d7277c
--- /dev/null
+++ b/Src/stm32f3xx_hal_rtc_ex.c
@@ -0,0 +1,1648 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_rtc_ex.c
+ * @author MCD Application Team
+ * @brief Extended RTC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Real Time Clock (RTC) Extended peripheral:
+ * + RTC Time Stamp functions
+ * + RTC Tamper functions
+ * + RTC Wake-up functions
+ * + Extended Control functions
+ * + Extended RTC features functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (+) Enable the RTC domain access.
+ (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
+ format using the HAL_RTC_Init() function.
+
+ *** RTC Wakeup configuration ***
+ ================================
+ [..]
+ (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer()
+ function. You can also configure the RTC Wakeup timer with interrupt mode
+ using the HAL_RTCEx_SetWakeUpTimer_IT() function.
+ (+) To read the RTC WakeUp Counter register, use the HAL_RTCEx_GetWakeUpTimer()
+ function.
+
+ *** TimeStamp configuration ***
+ ===============================
+ [..]
+ (+) Configure the RTC_AF trigger and enable the RTC TimeStamp using the
+ HAL_RTCEx_SetTimeStamp() function. You can also configure the RTC TimeStamp with
+ interrupt mode using the HAL_RTCEx_SetTimeStamp_IT() function.
+ (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
+ function.
+ (+) The TIMESTAMP alternate function is mapped to RTC_AF1 (PC13U).
+
+ *** Tamper configuration ***
+ ============================
+ [..]
+ (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge
+ or Level according to the Tamper filter (if equal to 0 Edge else Level)
+ value, sampling frequency, precharge or discharge and Pull-UP using the
+ HAL_RTCEx_SetTamper() function. You can configure RTC Tamper with interrupt
+ mode using HAL_RTCEx_SetTamper_IT() function.
+ (+) The TAMPER1 alternate function is mapped to RTC_AF1 (PC13U).
+
+ *** Backup Data Registers configuration ***
+ ===========================================
+ [..]
+ (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite()
+ function.
+ (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead()
+ function.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+
+
+/** @addtogroup RTCEx
+ * @brief RTC Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+
+/** @addtogroup RTCEx_Exported_Functions
+ * @{
+ */
+
+
+/** @addtogroup RTCEx_Exported_Functions_Group1
+ * @brief RTC TimeStamp and Tamper functions
+ *
+@verbatim
+ ===============================================================================
+ ##### RTC TimeStamp and Tamper functions #####
+ ===============================================================================
+
+ [..] This section provides functions allowing to configure TimeStamp feature
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Set TimeStamp.
+ * @note This API must be called before enabling the TimeStamp feature.
+ * @param hrtc RTC handle
+ * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is
+ * activated.
+ * This parameter can be one of the following values:
+ * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
+ * rising edge of the related pin.
+ * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
+ * falling edge of the related pin.
+ * @param RTC_TimeStampPin specifies the RTC TimeStamp Pin.
+ * This parameter can be one of the following values:
+ * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
+{
+ uint32_t tmpreg = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
+ assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Get the RTC_CR register and clear the bits to be configured */
+ tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
+
+ tmpreg|= TimeStampEdge;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Configure the Time Stamp TSEDGE and Enable bits */
+ hrtc->Instance->CR = (uint32_t)tmpreg;
+
+ __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set TimeStamp with Interrupt.
+ * @param hrtc RTC handle
+ * @note This API must be called before enabling the TimeStamp feature.
+ * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is
+ * activated.
+ * This parameter can be one of the following values:
+ * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
+ * rising edge of the related pin.
+ * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
+ * falling edge of the related pin.
+ * @param RTC_TimeStampPin Specifies the RTC TimeStamp Pin.
+ * This parameter can be one of the following values:
+ * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
+{
+ uint32_t tmpreg = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
+ assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Get the RTC_CR register and clear the bits to be configured */
+ tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
+
+ tmpreg |= TimeStampEdge;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Configure the Time Stamp TSEDGE and Enable bits */
+ hrtc->Instance->CR = (uint32_t)tmpreg;
+
+ __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
+
+ /* Enable IT timestamp */
+ __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc,RTC_IT_TS);
+
+ /* RTC timestamp Interrupt Configuration: EXTI configuration */
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
+
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Deactivate TimeStamp.
+ * @param hrtc RTC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)
+{
+ uint32_t tmpreg = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* In case of interrupt mode is used, the interrupt source must disabled */
+ __HAL_RTC_TIMESTAMP_DISABLE_IT(hrtc, RTC_IT_TS);
+
+ /* Get the RTC_CR register and clear the bits to be configured */
+ tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
+
+ /* Configure the Time Stamp TSEDGE and Enable bits */
+ hrtc->Instance->CR = (uint32_t)tmpreg;
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get the RTC TimeStamp value.
+ * @param hrtc RTC handle
+ * @param sTimeStamp Pointer to Time structure
+ * @param sTimeStampDate Pointer to Date structure
+ * @param Format specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format)
+{
+ uint32_t tmptime = 0U, tmpdate = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+
+ /* Get the TimeStamp time and date registers values */
+ tmptime = (uint32_t)(hrtc->Instance->TSTR & RTC_TR_RESERVED_MASK);
+ tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK);
+
+ /* Fill the Time structure fields with the read parameters */
+ sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16U);
+ sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8U);
+ sTimeStamp->Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));
+ sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16U);
+ sTimeStamp->SubSeconds = (uint32_t) hrtc->Instance->TSSSR;
+
+ /* Fill the Date structure fields with the read parameters */
+ sTimeStampDate->Year = 0U;
+ sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8U);
+ sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));
+ sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13U);
+
+ /* Check the input parameters format */
+ if(Format == RTC_FORMAT_BIN)
+ {
+ /* Convert the TimeStamp structure parameters to Binary format */
+ sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours);
+ sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes);
+ sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds);
+
+ /* Convert the DateTimeStamp structure parameters to Binary format */
+ sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month);
+ sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date);
+ sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay);
+ }
+
+ /* Clear the TIMESTAMP Flag */
+ __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set Tamper
+ * @note By calling this API we disable the tamper interrupt for all tampers.
+ * @param hrtc RTC handle
+ * @param sTamper Pointer to Tamper Structure.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
+{
+ uint32_t tmpreg = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_TAMPER(sTamper->Tamper));
+ assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
+ assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
+ assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
+ assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
+ assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
+ assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
+ {
+ sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1U);
+ }
+
+ tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->Filter |\
+ (uint32_t)sTamper->SamplingFrequency | (uint32_t)sTamper->PrechargeDuration |\
+ (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);
+
+ hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1U) | (uint32_t)RTC_TAFCR_TAMPTS |\
+ (uint32_t)RTC_TAFCR_TAMPFREQ | (uint32_t)RTC_TAFCR_TAMPFLT | (uint32_t)RTC_TAFCR_TAMPPRCH |\
+ (uint32_t)RTC_TAFCR_TAMPPUDIS | (uint32_t)RTC_TAFCR_TAMPIE);
+
+ hrtc->Instance->TAFCR |= tmpreg;
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set Tamper with interrupt.
+ * @note By calling this API we force the tamper interrupt for all tampers.
+ * @param hrtc RTC handle
+ * @param sTamper Pointer to RTC Tamper.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
+{
+ uint32_t tmpreg = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_TAMPER(sTamper->Tamper));
+ assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
+ assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
+ assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
+ assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
+ assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
+ assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Configure the tamper trigger */
+ if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
+ {
+ sTamper->Trigger = (uint32_t) (sTamper->Tamper<<1U);
+ }
+
+ tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->Filter |\
+ (uint32_t)sTamper->SamplingFrequency | (uint32_t)sTamper->PrechargeDuration |\
+ (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);
+
+ hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1U) | (uint32_t)RTC_TAFCR_TAMPTS |\
+ (uint32_t)RTC_TAFCR_TAMPFREQ | (uint32_t)RTC_TAFCR_TAMPFLT | (uint32_t)RTC_TAFCR_TAMPPRCH |\
+ (uint32_t)RTC_TAFCR_TAMPPUDIS);
+
+ hrtc->Instance->TAFCR |= tmpreg;
+
+ /* Configure the Tamper Interrupt in the RTC_TAFCR */
+ hrtc->Instance->TAFCR |= (uint32_t)RTC_TAFCR_TAMPIE;
+
+ /* RTC Tamper Interrupt Configuration: EXTI configuration */
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
+
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Deactivate Tamper.
+ * @param hrtc RTC handle
+ * @param Tamper Selected tamper pin.
+ * This parameter can be any combination of RTC_TAMPER_1, RTC_TAMPER_2 and RTC_TAMPER_3 (*)
+ * @note (*) RTC_TAMPER_3 not present on all the devices
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper)
+{
+ assert_param(IS_RTC_TAMPER(Tamper));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the selected Tamper pin */
+ hrtc->Instance->TAFCR &= (uint32_t)~Tamper;
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle TimeStamp interrupt request.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
+{
+ /* Get the TimeStamp interrupt source enable status */
+ if(__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(hrtc, RTC_IT_TS) != RESET)
+ {
+ /* Get the pending status of the TIMESTAMP Interrupt */
+ if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) != RESET)
+ {
+ /* TIMESTAMP callback */
+ HAL_RTCEx_TimeStampEventCallback(hrtc);
+
+ /* Clear the TIMESTAMP interrupt pending bit */
+ __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc,RTC_FLAG_TSF);
+ }
+ }
+
+ /* Get the Tamper interrupts source enable status */
+ if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP))
+ {
+ /* Get the pending status of the Tamper1 Interrupt */
+ if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != RESET)
+ {
+ /* Tamper1 callback */
+ HAL_RTCEx_Tamper1EventCallback(hrtc);
+
+ /* Clear the Tamper1 interrupt pending bit */
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);
+ }
+ }
+
+ /* Get the Tamper interrupts source enable status */
+ if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP))
+ {
+ /* Get the pending status of the Tamper2 Interrupt */
+ if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != RESET)
+ {
+ /* Tamper2 callback */
+ HAL_RTCEx_Tamper2EventCallback(hrtc);
+
+ /* Clear the Tamper2 interrupt pending bit */
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);
+ }
+ }
+
+#if defined(RTC_TAMPER3_SUPPORT)
+ /* Get the Tamper interrupts source enable status */
+ if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP))
+ {
+ /* Get the pending status of the Tamper3 Interrupt */
+ if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) != RESET)
+ {
+ /* Tamper3 callback */
+ HAL_RTCEx_Tamper3EventCallback(hrtc);
+
+ /* Clear the Tamper3 interrupt pending bit */
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F);
+ }
+ }
+#endif /* RTC_TAMPER3_SUPPORT */
+
+ /* Clear the EXTI's Flag for RTC TimeStamp and Tamper */
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG();
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+}
+
+/**
+ * @brief TimeStamp callback.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+__weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RTCEx_TimeStampEventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tamper 1 callback.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tamper 2 callback.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+__weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file
+ */
+}
+
+#if defined(RTC_TAMPER3_SUPPORT)
+/**
+ * @brief Tamper 3 callback.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+__weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file
+ */
+}
+#endif /* RTC_TAMPER3_SUPPORT */
+
+/**
+ * @brief Handle TimeStamp polling request.
+ * @param hrtc RTC handle
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ while(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == RESET)
+ {
+ if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != RESET)
+ {
+ /* Clear the TIMESTAMP OverRun Flag */
+ __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF);
+
+ /* Change TIMESTAMP state */
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle Tamper 1 Polling.
+ * @param hrtc RTC handle
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Get the status of the Interrupt */
+ while(__HAL_RTC_TAMPER_GET_FLAG(hrtc,RTC_FLAG_TAMP1F)== RESET)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Clear the Tamper Flag */
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle Tamper 2 Polling.
+ * @param hrtc RTC handle
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Get the status of the Interrupt */
+ while(__HAL_RTC_TAMPER_GET_FLAG(hrtc,RTC_FLAG_TAMP2F) == RESET)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Clear the Tamper Flag */
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP2F);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ return HAL_OK;
+}
+
+#if defined(RTC_TAMPER3_SUPPORT)
+/**
+ * @brief Handle Tamper 3 Polling.
+ * @param hrtc RTC handle
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Get the status of the Interrupt */
+ while(__HAL_RTC_TAMPER_GET_FLAG(hrtc,RTC_FLAG_TAMP3F) == RESET)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Clear the Tamper Flag */
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP3F);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ return HAL_OK;
+}
+#endif /* RTC_TAMPER3_SUPPORT */
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTCEx_Exported_Functions_Group2
+ * @brief RTC Wake-up functions
+ *
+@verbatim
+ ===============================================================================
+ ##### RTC Wake-up functions #####
+ ===============================================================================
+
+ [..] This section provides functions allowing to configure Wake-up feature
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Set wake up timer.
+ * @param hrtc RTC handle
+ * @param WakeUpCounter Wake up counter
+ * @param WakeUpClock Wake up clock
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
+{
+ uint32_t tickstart = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
+ assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
+ if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET){
+ tickstart = HAL_GetTick();
+
+ /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
+ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET)
+ {
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
+
+ tickstart = HAL_GetTick();
+
+ /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
+ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
+ {
+ if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear the Wakeup Timer clock source bits in CR register */
+ hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
+
+ /* Configure the clock source */
+ hrtc->Instance->CR |= (uint32_t)WakeUpClock;
+
+ /* Configure the Wakeup Timer counter */
+ hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
+
+ /* Enable the Wakeup Timer */
+ __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set wake up timer with interrupt.
+ * @param hrtc RTC handle
+ * @param WakeUpCounter Wake up counter
+ * @param WakeUpClock Wake up clock
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
+{
+ uint32_t tickstart = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
+ assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
+ if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET){
+ tickstart = HAL_GetTick();
+
+ /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
+ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET)
+ {
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Disable the Wake-Up timer */
+ __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
+
+ /* Clear flag Wake-Up */
+ __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
+
+ tickstart = HAL_GetTick();
+
+ /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
+ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
+ {
+ if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Configure the Wakeup Timer counter */
+ hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
+
+ /* Clear the Wakeup Timer clock source bits in CR register */
+ hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
+
+ /* Configure the clock source */
+ hrtc->Instance->CR |= (uint32_t)WakeUpClock;
+
+ /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */
+ __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
+
+ __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
+
+ /* Configure the Interrupt in the RTC_CR register */
+ __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT);
+
+ /* Enable the Wakeup Timer */
+ __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Deactivate wake up timer counter.
+ * @param hrtc RTC handle
+ * @retval HAL status
+ */
+uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
+{
+ uint32_t tickstart = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Disable the Wakeup Timer */
+ __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
+
+ /* In case of interrupt mode is used, the interrupt source must disabled */
+ __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc,RTC_IT_WUT);
+
+ tickstart = HAL_GetTick();
+ /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
+ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
+ {
+ if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get wake up timer counter.
+ * @param hrtc RTC handle
+ * @retval Counter value
+ */
+uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc)
+{
+ /* Get the counter value */
+ return ((uint32_t)(hrtc->Instance->WUTR & RTC_WUTR_WUT));
+}
+
+/**
+ * @brief Handle Wake Up Timer interrupt request.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
+{
+ /* Get the pending status of the WAKEUPTIMER Interrupt */
+ if(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != RESET)
+ {
+ /* WAKEUPTIMER callback */
+ HAL_RTCEx_WakeUpTimerEventCallback(hrtc);
+
+ /* Clear the WAKEUPTIMER interrupt pending bit */
+ __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
+ }
+
+ /* Clear the EXTI's line Flag for RTC WakeUpTimer */
+ __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG();
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+}
+
+/**
+ * @brief Wake Up Timer callback.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+__weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RTCEx_WakeUpTimerEventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Handle Wake Up Timer Polling.
+ * @param hrtc RTC handle
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == RESET)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Clear the WAKEUPTIMER Flag */
+ __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup RTCEx_Exported_Functions_Group3
+ * @brief Extended Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Write a data in a specified RTC Backup data register
+ (+) Read a data in a specified RTC Backup data register
+ (+) Set the Coarse calibration parameters.
+ (+) Deactivate the Coarse calibration parameters
+ (+) Set the Smooth calibration parameters.
+ (+) Configure the Synchronization Shift Control Settings.
+ (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+ (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+ (+) Enable the RTC reference clock detection.
+ (+) Disable the RTC reference clock detection.
+ (+) Enable the Bypass Shadow feature.
+ (+) Disable the Bypass Shadow feature.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Write a data in a specified RTC Backup data register.
+ * @param hrtc RTC handle
+ * @param BackupRegister RTC Backup data Register number.
+ * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
+ * specify the register.
+ * @param Data Data to be written in the specified RTC Backup data register.
+ * @retval None
+ */
+void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
+{
+ uint32_t tmp = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_BKP(BackupRegister));
+
+ tmp = (uint32_t)&(hrtc->Instance->BKP0R);
+ tmp += (BackupRegister * 4U);
+
+ /* Write the specified register */
+ *(__IO uint32_t *)tmp = (uint32_t)Data;
+}
+
+/**
+ * @brief Reads data from the specified RTC Backup data Register.
+ * @param hrtc RTC handle
+ * @param BackupRegister RTC Backup data Register number.
+ * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
+ * specify the register.
+ * @retval Read value
+ */
+uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
+{
+ uint32_t tmp = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_BKP(BackupRegister));
+
+ tmp = (uint32_t)&(hrtc->Instance->BKP0R);
+ tmp += (BackupRegister * 4U);
+
+ /* Read the specified register */
+ return (*(__IO uint32_t *)tmp);
+}
+
+/**
+ * @brief Set the Smooth calibration parameters.
+ * @param hrtc RTC handle
+ * @param SmoothCalibPeriod Select the Smooth Calibration Period.
+ * This parameter can be can be one of the following values :
+ * @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.
+ * @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s.
+ * @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s.
+ * @param SmoothCalibPlusPulses Select to Set or reset the CALP bit.
+ * This parameter can be one of the following values:
+ * @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses.
+ * @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.
+ * @param SmoothCalibMinusPulsesValue Select the value of CALM[8:0] bits.
+ * This parameter can be one any value from 0 to 0x000001FF.
+ * @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses
+ * must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field
+ * SmoothCalibMinusPulsesValue mut be equal to 0.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue)
+{
+ uint32_t tickstart = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod));
+ assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses));
+ assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmoothCalibMinusPulsesValue));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* check if a calibration is pending*/
+ if((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)
+ {
+ tickstart = HAL_GetTick();
+
+ /* check if a calibration is pending*/
+ while((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)
+ {
+ if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Configure the Smooth calibration settings */
+ hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | (uint32_t)SmoothCalibMinusPulsesValue);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the Synchronization Shift Control Settings.
+ * @note When REFCKON is set, firmware must not write to Shift control register.
+ * @param hrtc RTC handle
+ * @param ShiftAdd1S: Select to add or not 1 second to the time calendar.
+ * This parameter can be one of the following values :
+ * @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar.
+ * @arg RTC_SHIFTADD1S_RESET: No effect.
+ * @param ShiftSubFS Select the number of Second Fractions to substitute.
+ * This parameter can be one any value from 0 to 0x7FFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
+{
+ uint32_t tickstart = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S));
+ assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ tickstart = HAL_GetTick();
+
+ /* Wait until the shift is completed*/
+ while((hrtc->Instance->ISR & RTC_ISR_SHPF) != RESET)
+ {
+ if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Check if the reference clock detection is disabled */
+ if((hrtc->Instance->CR & RTC_CR_REFCKON) == RESET)
+ {
+ /* Configure the Shift settings */
+ hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S);
+
+ /* If RTC_CR_BYPSHAD bit = 0U, wait for synchro else this check is not needed */
+ if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
+ {
+ if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+ else
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+ * @param hrtc RTC handle
+ * @param CalibOutput Select the Calibration output Selection .
+ * This parameter can be one of the following values:
+ * @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz.
+ * @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32_t CalibOutput)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Clear flags before config */
+ hrtc->Instance->CR &= (uint32_t)~RTC_CR_COSEL;
+
+ /* Configure the RTC_CR register */
+ hrtc->Instance->CR |= (uint32_t)CalibOutput;
+
+ __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(hrtc);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+ * @param hrtc RTC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc)
+{
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(hrtc);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable the RTC reference clock detection.
+ * @param hrtc RTC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc)
+{
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Set Initialization mode */
+ if(RTC_EnterInitMode(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Set RTC state*/
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ __HAL_RTC_CLOCKREF_DETECTION_ENABLE(hrtc);
+
+ /* Exit Initialization mode */
+ hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the RTC reference clock detection.
+ * @param hrtc RTC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc)
+{
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Set Initialization mode */
+ if(RTC_EnterInitMode(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Set RTC state*/
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ __HAL_RTC_CLOCKREF_DETECTION_DISABLE(hrtc);
+
+ /* Exit Initialization mode */
+ hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable the Bypass Shadow feature.
+ * @param hrtc RTC handle
+ * @note When the Bypass Shadow is enabled the calendar value are taken
+ * directly from the Calendar counter.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc)
+{
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Set the BYPSHAD bit */
+ hrtc->Instance->CR |= (uint8_t)RTC_CR_BYPSHAD;
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the Bypass Shadow feature.
+ * @param hrtc RTC handle
+ * @note When the Bypass Shadow is enabled the calendar value are taken
+ * directly from the Calendar counter.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc)
+{
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Reset the BYPSHAD bit */
+ hrtc->Instance->CR &= ((uint8_t)~RTC_CR_BYPSHAD);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTCEx_Exported_Functions_Group4 Extended features functions
+ * @brief Extended features functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended features functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) RTC Alram B callback
+ (+) RTC Poll for Alarm B request
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Alarm B callback.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+__weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RTCEx_AlarmBEventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief This function handles AlarmB Polling request.
+ * @param hrtc RTC handle
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == RESET)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Clear the Alarm Flag */
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_RTC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_sdadc.c b/Src/stm32f3xx_hal_sdadc.c
new file mode 100644
index 0000000..c480ab3
--- /dev/null
+++ b/Src/stm32f3xx_hal_sdadc.c
@@ -0,0 +1,2694 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_sdadc.c
+ * @author MCD Application Team
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Sigma-Delta Analog to Digital Converter
+ * (SDADC) peripherals:
+ * + Initialization and Configuration
+ * + Regular Channels Configuration
+ * + Injected channels Configuration
+ * + Power saving
+ * + Regular/Injected Channels DMA Configuration
+ * + Interrupts and flags management
+ @verbatim
+ ==============================================================================
+ ##### SDADC specific features #####
+ ==============================================================================
+ [..]
+ (#) 16-bit sigma delta architecture.
+ (#) Self calibration.
+ (#) Interrupt generation at the end of calibration, regular/injected conversion
+ and in case of overrun events.
+ (#) Single and continuous conversion modes.
+ (#) External trigger option with configurable polarity for injected conversion.
+ (#) Multi mode (synchronized another SDADC with SDADC1).
+ (#) DMA request generation during regular or injected channel conversion.
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ *** Initialization ***
+ ======================
+ [..]
+ (#) As prerequisite, fill in the HAL_SDADC_MspInit() :
+ (++) Enable SDADCx clock interface with __SDADCx_CLK_ENABLE().
+ (++) Configure SDADCx clock divider with HAL_RCCEx_PeriphCLKConfig.
+ (++) Enable power on SDADC with HAL_PWREx_EnableSDADC().
+ (++) Enable the clocks for the SDADC GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
+ (++) Configure these SDADC pins in analog mode using HAL_GPIO_Init().
+ (++) If interrupt mode is used, enable and configure SDADC global
+ interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
+ (++) If DMA mode is used, configure DMA with HAL_DMA_Init and link it
+ with SDADC handle using __HAL_LINKDMA.
+ (#) Configure the SDADC low power mode, fast conversion mode, slow clock
+ mode and SDADC1 reference voltage using the HAL_ADC_Init() function.
+ Note: Common reference voltage. is common to all SDADC instances.
+ (#) Prepare channel configurations (input mode, common mode, gain and
+ offset) using HAL_SDADC_PrepareChannelConfig and associate channel
+ with one configuration using HAL_SDADC_AssociateChannelConfig.
+
+ *** Calibration ***
+ ============================================
+ [..]
+ (#) Start calibration using HAL_SDADC_StartCalibration or
+ HAL_SDADC_CalibrationStart_IT.
+ (#) In polling mode, use HAL_SDADC_PollForCalibEvent to detect the end of
+ calibration.
+ (#) In interrupt mode, HAL_SDADC_CalibrationCpltCallback will be called at
+ the end of calibration.
+
+ *** Regular channel conversion ***
+ ============================================
+ [..]
+ (#) Select trigger for regular conversion using
+ HAL_SDADC_SelectRegularTrigger.
+ (#) Select regular channel and enable/disable continuous mode using
+ HAL_SDADC_ConfigChannel.
+ (#) Start regular conversion using HAL_SDADC_Start, HAL_SDADC_Start_IT
+ or HAL_SDADC_Start_DMA.
+ (#) In polling mode, use HAL_SDADC_PollForConversion to detect the end of
+ regular conversion.
+ (#) In interrupt mode, HAL_SDADC_ConvCpltCallback will be called at the
+ end of regular conversion.
+ (#) Get value of regular conversion using HAL_SDADC_GetValue.
+ (#) In DMA mode, HAL_SDADC_ConvHalfCpltCallback and
+ HAL_SDADC_ConvCpltCallback will be called respectively at the half
+ transfer and at the transfer complete.
+ (#) Stop regular conversion using HAL_SDADC_Stop, HAL_SDADC_Stop_IT
+ or HAL_SDADC_Stop_DMA.
+
+ *** Injected channels conversion ***
+ ============================================
+ [..]
+ (#) Enable/disable delay on injected conversion using
+ HAL_SDADC_SelectInjectedDelay.
+ (#) If external trigger is used for injected conversion, configure this
+ trigger using HAL_SDADC_SelectInjectedExtTrigger.
+ (#) Select trigger for injected conversion using
+ HAL_SDADC_SelectInjectedTrigger.
+ (#) Select injected channels and enable/disable continuous mode using
+ HAL_SDADC_InjectedConfigChannel.
+ (#) Start injected conversion using HAL_SDADC_InjectedStart,
+ HAL_SDADC_InjectedStart_IT or HAL_SDADC_InjectedStart_DMA.
+ (#) In polling mode, use HAL_SDADC_PollForInjectedConversion to detect the
+ end of injected conversion.
+ (#) In interrupt mode, HAL_SDADC_InjectedConvCpltCallback will be called
+ at the end of injected conversion.
+ (#) Get value of injected conversion and corresponding channel using
+ HAL_SDADC_InjectedGetValue.
+ (#) In DMA mode, HAL_SDADC_InjectedConvHalfCpltCallback and
+ HAL_SDADC_InjectedConvCpltCallback will be called respectively at the
+ half transfer and at the transfer complete.
+ (#) Stop injected conversion using HAL_SDADC_InjectedStop,
+ HAL_SDADC_InjectedStop_IT or HAL_SDADC_InjectedStop_DMA.
+
+ *** Multi mode regular channels conversions ***
+ ======================================================
+ [..]
+ (#) Select type of multimode (SDADC1/SDADC2 or SDADC1/SDADC3) using
+ HAL_SDADC_MultiModeConfigChannel.
+ (#) Select software trigger for SDADC1 and synchronized trigger for
+ SDADC2 (or SDADC3) using HAL_SDADC_SelectRegularTrigger.
+ (#) Select regular channel for SDADC1 and SDADC2 (or SDADC3) using
+ HAL_SDADC_ConfigChannel.
+ (#) Start regular conversion for SDADC2 (or SDADC3) with HAL_SDADC_Start.
+ (#) Start regular conversion for SDADC1 using HAL_SDADC_Start,
+ HAL_SDADC_Start_IT or HAL_SDADC_MultiModeStart_DMA.
+ (#) In polling mode, use HAL_SDADC_PollForConversion to detect the end of
+ regular conversion for SDADC1.
+ (#) In interrupt mode, HAL_SDADC_ConvCpltCallback will be called at the
+ end of regular conversion for SDADC1.
+ (#) Get value of regular conversions using HAL_SDADC_MultiModeGetValue.
+ (#) In DMA mode, HAL_SDADC_ConvHalfCpltCallback and
+ HAL_SDADC_ConvCpltCallback will be called respectively at the half
+ transfer and at the transfer complete for SDADC1.
+ (#) Stop regular conversion using HAL_SDADC_Stop, HAL_SDADC_Stop_IT
+ or HAL_SDADC_MultiModeStop_DMA for SDADC1.
+ (#) Stop regular conversion using HAL_SDADC_Stop for SDADC2 (or SDADC3).
+
+ *** Multi mode injected channels conversions ***
+ ======================================================
+ [..]
+ (#) Select type of multimode (SDADC1/SDADC2 or SDADC1/SDADC3) using
+ HAL_SDADC_InjectedMultiModeConfigChannel.
+ (#) Select software or external trigger for SDADC1 and synchronized
+ trigger for SDADC2 (or SDADC3) using HAL_SDADC_SelectInjectedTrigger.
+ (#) Select injected channels for SDADC1 and SDADC2 (or SDADC3) using
+ HAL_SDADC_InjectedConfigChannel.
+ (#) Start injected conversion for SDADC2 (or SDADC3) with
+ HAL_SDADC_InjectedStart.
+ (#) Start injected conversion for SDADC1 using HAL_SDADC_InjectedStart,
+ HAL_SDADC_InjectedStart_IT or HAL_SDADC_InjectedMultiModeStart_DMA.
+ (#) In polling mode, use HAL_SDADC_InjectedPollForConversion to detect
+ the end of injected conversion for SDADC1.
+ (#) In interrupt mode, HAL_SDADC_InjectedConvCpltCallback will be called
+ at the end of injected conversion for SDADC1.
+ (#) Get value of injected conversions using
+ HAL_SDADC_InjectedMultiModeGetValue.
+ (#) In DMA mode, HAL_SDADC_InjectedConvHalfCpltCallback and
+ HAL_SDADC_InjectedConvCpltCallback will be called respectively at the
+ half transfer and at the transfer complete for SDADC1.
+ (#) Stop injected conversion using HAL_SDADC_InjectedStop,
+ HAL_SDADC_InjectedStop_IT or HAL_SDADC_InjecteddMultiModeStop_DMA
+ for SDADC1.
+ (#) Stop injected conversion using HAL_SDADC_InjectedStop for SDADC2
+ (or SDADC3).
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_SDADC_MODULE_ENABLED
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/** @defgroup SDADC SDADC
+ * @brief SDADC HAL driver modules
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup SDADC_Private_Define SDADC Private Define
+ * @{
+ */
+#define SDADC_TIMEOUT 200UL
+#define SDADC_CONFREG_OFFSET 0x00000020UL
+#define SDADC_JDATAR_CH_OFFSET 24UL
+#define SDADC_MSB_MASK 0xFFFF0000UL
+#define SDADC_LSB_MASK 0x0000FFFFUL
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup SDADC_Private_Functions SDADC Private Functions
+ * @{
+ */
+
+static HAL_StatusTypeDef SDADC_EnterInitMode(SDADC_HandleTypeDef* hsdadc);
+static void SDADC_ExitInitMode(SDADC_HandleTypeDef* hsdadc);
+static uint32_t SDADC_GetInjChannelsNbr(uint32_t Channels);
+static HAL_StatusTypeDef SDADC_RegConvStart(SDADC_HandleTypeDef* hsdadc);
+static HAL_StatusTypeDef SDADC_RegConvStop(SDADC_HandleTypeDef* hsdadc);
+static HAL_StatusTypeDef SDADC_InjConvStart(SDADC_HandleTypeDef* hsdadc);
+static HAL_StatusTypeDef SDADC_InjConvStop(SDADC_HandleTypeDef* hsdadc);
+static void SDADC_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma);
+static void SDADC_DMARegularConvCplt(DMA_HandleTypeDef *hdma);
+static void SDADC_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma);
+static void SDADC_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma);
+static void SDADC_DMAError(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup SDADC_Exported_Functions SDADC Exported Functions
+ * @{
+ */
+
+/** @defgroup SDADC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and de-initialization functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize the SDADC.
+ (+) De-initialize the SDADC.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the SDADC according to the specified
+ * parameters in the SDADC_InitTypeDef structure.
+ * @note If multiple SDADC are used, please configure first SDADC1 to set
+ * the common reference voltage.
+ * @param hsdadc SDADC handle.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_SDADC_Init(SDADC_HandleTypeDef* hsdadc)
+{
+ /* Check SDADC handle */
+ if(hsdadc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+ assert_param(IS_SDADC_LOWPOWER_MODE(hsdadc->Init.IdleLowPowerMode));
+ assert_param(IS_SDADC_FAST_CONV_MODE(hsdadc->Init.FastConversionMode));
+ assert_param(IS_SDADC_SLOW_CLOCK_MODE(hsdadc->Init.SlowClockMode));
+ assert_param(IS_SDADC_VREF(hsdadc->Init.ReferenceVoltage));
+
+ /* Initialize SDADC variables with default values */
+ hsdadc->RegularContMode = SDADC_CONTINUOUS_CONV_OFF;
+ hsdadc->InjectedContMode = SDADC_CONTINUOUS_CONV_OFF;
+ hsdadc->InjectedChannelsNbr = 1U;
+ hsdadc->InjConvRemaining = 1U;
+ hsdadc->RegularTrigger = SDADC_SOFTWARE_TRIGGER;
+ hsdadc->InjectedTrigger = SDADC_SOFTWARE_TRIGGER;
+ hsdadc->ExtTriggerEdge = SDADC_EXT_TRIG_RISING_EDGE;
+ hsdadc->RegularMultimode = SDADC_MULTIMODE_SDADC1_SDADC2;
+ hsdadc->InjectedMultimode = SDADC_MULTIMODE_SDADC1_SDADC2;
+ hsdadc->ErrorCode = SDADC_ERROR_NONE;
+
+ /* Call MSP init function */
+ HAL_SDADC_MspInit(hsdadc);
+
+ /* Set idle low power and slow clock modes */
+ hsdadc->Instance->CR1 &= ~(SDADC_CR1_SBI|SDADC_CR1_PDI|SDADC_CR1_SLOWCK);
+ hsdadc->Instance->CR1 |= (hsdadc->Init.IdleLowPowerMode | \
+ hsdadc->Init.SlowClockMode);
+
+ /* Set fast conversion mode */
+ hsdadc->Instance->CR2 &= ~(SDADC_CR2_FAST);
+ hsdadc->Instance->CR2 |= hsdadc->Init.FastConversionMode;
+
+ /* Set reference voltage common to all SDADC instances */
+ /* Update this parameter only if needed to avoid unnecessary settling time */
+ if((SDADC1->CR1 & SDADC_CR1_REFV) != hsdadc->Init.ReferenceVoltage)
+ {
+ /* Voltage reference bits are common to all SADC instances but are */
+ /* present in SDADC1 register. */
+ SDADC1->CR1 &= ~(SDADC_CR1_REFV);
+ SDADC1->CR1 |= hsdadc->Init.ReferenceVoltage;
+
+ /* Wait at least 2ms before setting ADON */
+ HAL_Delay(2U);
+ }
+
+ /* Enable SDADC */
+ hsdadc->Instance->CR2 |= SDADC_CR2_ADON;
+
+ /* Wait end of stabilization */
+ while((hsdadc->Instance->ISR & SDADC_ISR_STABIP) != 0UL)
+ {
+ }
+
+ /* Set SDADC to ready state */
+ hsdadc->State = HAL_SDADC_STATE_READY;
+
+ /* Return HAL status */
+ return HAL_OK;
+}
+
+/**
+ * @brief De-initializes the SDADC.
+ * @param hsdadc SDADC handle.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_SDADC_DeInit(SDADC_HandleTypeDef* hsdadc)
+{
+ /* Check SDADC handle */
+ if(hsdadc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+
+ /* Disable the SDADC */
+ hsdadc->Instance->CR2 &= ~(SDADC_CR2_ADON);
+
+ /* Reset all registers */
+ hsdadc->Instance->CR1 = 0x00000000UL;
+ hsdadc->Instance->CR2 = 0x00000000UL;
+ hsdadc->Instance->JCHGR = 0x00000001UL;
+ hsdadc->Instance->CONF0R = 0x00000000UL;
+ hsdadc->Instance->CONF1R = 0x00000000UL;
+ hsdadc->Instance->CONF2R = 0x00000000UL;
+ hsdadc->Instance->CONFCHR1 = 0x00000000UL;
+ hsdadc->Instance->CONFCHR2 = 0x00000000UL;
+
+ /* Call MSP deinit function */
+ HAL_SDADC_MspDeInit(hsdadc);
+
+ /* Set SDADC in reset state */
+ hsdadc->State = HAL_SDADC_STATE_RESET;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the SDADC MSP.
+ * @param hsdadc SDADC handle
+ * @retval None
+ */
+__weak void HAL_SDADC_MspInit(SDADC_HandleTypeDef* hsdadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsdadc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SDADC_MspInit could be implemented in the user file.
+ */
+}
+
+/**
+ * @brief De-initializes the SDADC MSP.
+ * @param hsdadc SDADC handle
+ * @retval None
+ */
+__weak void HAL_SDADC_MspDeInit(SDADC_HandleTypeDef* hsdadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsdadc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SDADC_MspDeInit could be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SDADC_Exported_Functions_Group2 peripheral control functions
+ * @brief Peripheral control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Program one of the three different configurations for channels.
+ (+) Associate channel to one of configurations.
+ (+) Select regular and injected channels.
+ (+) Enable/disable continuous mode for regular and injected conversions.
+ (+) Select regular and injected triggers.
+ (+) Select and configure injected external trigger.
+ (+) Enable/disable delay addition for injected conversions.
+ (+) Configure multimode.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function allows the user to set parameters for a configuration.
+ * Parameters are input mode, common mode, gain and offset.
+ * @note This function should be called only when SDADC instance is in idle state
+ * (neither calibration nor regular or injected conversion ongoing)
+ * @param hsdadc SDADC handle.
+ * @param ConfIndex Index of configuration to modify.
+ * This parameter can be a value of @ref SDADC_ConfIndex.
+ * @param ConfParamStruct Parameters to apply for this configuration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_PrepareChannelConfig(SDADC_HandleTypeDef *hsdadc,
+ uint32_t ConfIndex,
+ SDADC_ConfParamTypeDef* ConfParamStruct)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmp;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+ assert_param(IS_SDADC_CONF_INDEX(ConfIndex));
+ assert_param(ConfParamStruct != ((void*) 0));
+ assert_param(IS_SDADC_INPUT_MODE(ConfParamStruct->InputMode));
+ assert_param(IS_SDADC_GAIN(ConfParamStruct->Gain));
+ assert_param(IS_SDADC_COMMON_MODE(ConfParamStruct->CommonMode));
+ assert_param(IS_SDADC_OFFSET_VALUE(ConfParamStruct->Offset));
+
+ /* Check SDADC state is ready */
+ if(hsdadc->State != HAL_SDADC_STATE_READY)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Enter init mode */
+ if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
+ {
+ /* Set SDADC in error state */
+ hsdadc->State = HAL_SDADC_STATE_ERROR;
+ status = HAL_TIMEOUT;
+ }
+ else
+ {
+ /* Program configuration register with parameters */
+ tmp = (uint32_t)((uint32_t)(hsdadc->Instance) + \
+ SDADC_CONFREG_OFFSET + \
+ (uint32_t)(ConfIndex << 2UL));
+ *(__IO uint32_t *) (tmp) = (uint32_t) (ConfParamStruct->InputMode | \
+ ConfParamStruct->Gain | \
+ ConfParamStruct->CommonMode | \
+ ConfParamStruct->Offset);
+ /* Exit init mode */
+ SDADC_ExitInitMode(hsdadc);
+ }
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows the user to associate a channel with one of the
+ * available configurations.
+ * @note This function should be called only when SDADC instance is in idle state
+ * (neither calibration nor regular or injected conversion ongoing)
+ * @param hsdadc SDADC handle.
+ * @param Channel Channel to associate with configuration.
+ * This parameter can be a value of @ref SDADC_Channel_Selection.
+ * @param ConfIndex Index of configuration to associate with channel.
+ * This parameter can be a value of @ref SDADC_ConfIndex.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_AssociateChannelConfig(SDADC_HandleTypeDef *hsdadc,
+ uint32_t Channel,
+ uint32_t ConfIndex)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t channelnum;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+ assert_param(IS_SDADC_REGULAR_CHANNEL(Channel));
+ assert_param(IS_SDADC_CONF_INDEX(ConfIndex));
+
+ /* Check SDADC state is ready */
+ if(hsdadc->State != HAL_SDADC_STATE_READY)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Enter init mode */
+ if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
+ {
+ /* Set SDADC in error state */
+ hsdadc->State = HAL_SDADC_STATE_ERROR;
+ status = HAL_TIMEOUT;
+ }
+ else
+ {
+ /* Program channel configuration register according parameters */
+ if(Channel != SDADC_CHANNEL_8)
+ {
+ /* Get channel number */
+ channelnum = (uint32_t)(Channel>>16UL);
+
+ /* Set the channel configuration */
+ hsdadc->Instance->CONFCHR1 &= (uint32_t) ~((uint32_t)SDADC_CONFCHR1_CONFCH0 << ((channelnum << 2UL) & 0x1FUL));
+ hsdadc->Instance->CONFCHR1 |= (uint32_t) (ConfIndex << ((channelnum << 2UL) & 0x1FUL));
+ }
+ else
+ {
+ hsdadc->Instance->CONFCHR2 = (uint32_t) (ConfIndex);
+ }
+ /* Exit init mode */
+ SDADC_ExitInitMode(hsdadc);
+ }
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to select channel for regular conversion and
+ * to enable/disable continuous mode for regular conversion.
+ * @param hsdadc SDADC handle.
+ * @param Channel Channel for regular conversion.
+ * This parameter can be a value of @ref SDADC_Channel_Selection.
+ * @param ContinuousMode Enable/disable continuous mode for regular conversion.
+ * This parameter can be a value of @ref SDADC_ContinuousMode.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_ConfigChannel(SDADC_HandleTypeDef *hsdadc,
+ uint32_t Channel,
+ uint32_t ContinuousMode)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+ assert_param(IS_SDADC_REGULAR_CHANNEL(Channel));
+ assert_param(IS_SDADC_CONTINUOUS_MODE(ContinuousMode));
+
+ /* Check SDADC state */
+ if((hsdadc->State != HAL_SDADC_STATE_RESET) && (hsdadc->State != HAL_SDADC_STATE_ERROR))
+ {
+ /* Set RCH[3:0] and RCONT bits in SDADC_CR2 */
+ hsdadc->Instance->CR2 &= (uint32_t) ~(SDADC_CR2_RCH | SDADC_CR2_RCONT);
+ if(ContinuousMode == SDADC_CONTINUOUS_CONV_ON)
+ {
+ hsdadc->Instance->CR2 |= (uint32_t) ((Channel & SDADC_MSB_MASK) | SDADC_CR2_RCONT);
+ }
+ else
+ {
+ hsdadc->Instance->CR2 |= (uint32_t) ((Channel & SDADC_MSB_MASK));
+ }
+ /* Store continuous mode information */
+ hsdadc->RegularContMode = ContinuousMode;
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to select channels for injected conversion and
+ * to enable/disable continuous mode for injected conversion.
+ * @param hsdadc SDADC handle.
+ * @param Channel Channels for injected conversion.
+ * This parameter can be a values combination of @ref SDADC_Channel_Selection.
+ * @param ContinuousMode Enable/disable continuous mode for injected conversion.
+ * This parameter can be a value of @ref SDADC_ContinuousMode.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_InjectedConfigChannel(SDADC_HandleTypeDef *hsdadc,
+ uint32_t Channel,
+ uint32_t ContinuousMode)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+ assert_param(IS_SDADC_INJECTED_CHANNEL(Channel));
+ assert_param(IS_SDADC_CONTINUOUS_MODE(ContinuousMode));
+
+ /* Check SDADC state */
+ if((hsdadc->State != HAL_SDADC_STATE_RESET) && (hsdadc->State != HAL_SDADC_STATE_ERROR))
+ {
+ /* Set JCHG[8:0] bits in SDADC_JCHG */
+ hsdadc->Instance->JCHGR = (uint32_t) (Channel & SDADC_LSB_MASK);
+ /* Set or clear JCONT bit in SDADC_CR2 */
+ if(ContinuousMode == SDADC_CONTINUOUS_CONV_ON)
+ {
+ hsdadc->Instance->CR2 |= SDADC_CR2_JCONT;
+ }
+ else
+ {
+ hsdadc->Instance->CR2 &= ~(SDADC_CR2_JCONT);
+ }
+ /* Store continuous mode information */
+ hsdadc->InjectedContMode = ContinuousMode;
+ /* Store number of injected channels */
+ hsdadc->InjectedChannelsNbr = SDADC_GetInjChannelsNbr(Channel);
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to select trigger for regular conversions.
+ * @note This function should not be called if regular conversion is ongoing.
+ * @param hsdadc SDADC handle.
+ * @param Trigger Trigger for regular conversions.
+ * This parameter can be one of the following value :
+ * @arg SDADC_SOFTWARE_TRIGGER : Software trigger.
+ * @arg SDADC_SYNCHRONOUS_TRIGGER : Synchronous with SDADC1 (only for SDADC2 and SDADC3).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_SelectRegularTrigger(SDADC_HandleTypeDef *hsdadc, uint32_t Trigger)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+ assert_param(IS_SDADC_REGULAR_TRIGGER(Trigger));
+
+ /* Check parameters compatibility */
+ if((hsdadc->Instance == SDADC1) && (Trigger == SDADC_SYNCHRONOUS_TRIGGER))
+ {
+ status = HAL_ERROR;
+ }
+ /* Check SDADC state */
+ else if((hsdadc->State == HAL_SDADC_STATE_READY) || \
+ (hsdadc->State == HAL_SDADC_STATE_CALIB) || \
+ (hsdadc->State == HAL_SDADC_STATE_INJ))
+ {
+ /* Store regular trigger information */
+ hsdadc->RegularTrigger = Trigger;
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to select trigger for injected conversions.
+ * @note This function should not be called if injected conversion is ongoing.
+ * @param hsdadc SDADC handle.
+ * @param Trigger Trigger for injected conversions.
+ * This parameter can be one of the following value :
+ * @arg SDADC_SOFTWARE_TRIGGER : Software trigger.
+ * @arg SDADC_SYNCHRONOUS_TRIGGER : Synchronous with SDADC1 (only for SDADC2 and SDADC3).
+ * @arg SDADC_EXTERNAL_TRIGGER : External trigger.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_SelectInjectedTrigger(SDADC_HandleTypeDef *hsdadc, uint32_t Trigger)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+ assert_param(IS_SDADC_INJECTED_TRIGGER(Trigger));
+
+ /* Check parameters compatibility */
+ if((hsdadc->Instance == SDADC1) && (Trigger == SDADC_SYNCHRONOUS_TRIGGER))
+ {
+ status = HAL_ERROR;
+ }
+ /* Check SDADC state */
+ else if((hsdadc->State == HAL_SDADC_STATE_READY) || \
+ (hsdadc->State == HAL_SDADC_STATE_CALIB) || \
+ (hsdadc->State == HAL_SDADC_STATE_REG))
+ {
+ /* Store regular trigger information */
+ hsdadc->InjectedTrigger = Trigger;
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to select and configure injected external trigger.
+ * @note This function should be called only when SDADC instance is in idle state
+ * (neither calibration nor regular or injected conversion ongoing)
+ * @param hsdadc SDADC handle.
+ * @param InjectedExtTrigger External trigger for injected conversions.
+ * This parameter can be a value of @ref SDADC_InjectedExtTrigger.
+ * @param ExtTriggerEdge Edge of external injected trigger.
+ * This parameter can be a value of @ref SDADC_ExtTriggerEdge.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_SelectInjectedExtTrigger(SDADC_HandleTypeDef *hsdadc,
+ uint32_t InjectedExtTrigger,
+ uint32_t ExtTriggerEdge)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+ assert_param(IS_SDADC_EXT_INJEC_TRIG(InjectedExtTrigger));
+ assert_param(IS_SDADC_EXT_TRIG_EDGE(ExtTriggerEdge));
+
+ /* Check SDADC state */
+ if(hsdadc->State == HAL_SDADC_STATE_READY)
+ {
+ /* Enter init mode */
+ if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
+ {
+ /* Set SDADC in error state */
+ hsdadc->State = HAL_SDADC_STATE_ERROR;
+ status = HAL_TIMEOUT;
+ }
+ else
+ {
+ /* Set JEXTSEL[2:0] bits in SDADC_CR2 register */
+ hsdadc->Instance->CR2 &= ~(SDADC_CR2_JEXTSEL);
+ hsdadc->Instance->CR2 |= InjectedExtTrigger;
+
+ /* Store external trigger edge information */
+ hsdadc->ExtTriggerEdge = ExtTriggerEdge;
+
+ /* Exit init mode */
+ SDADC_ExitInitMode(hsdadc);
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to enable/disable delay addition for injected conversions.
+ * @note This function should be called only when SDADC instance is in idle state
+ * (neither calibration nor regular or injected conversion ongoing)
+ * @param hsdadc SDADC handle.
+ * @param InjectedDelay Enable/disable delay for injected conversions.
+ * This parameter can be a value of @ref SDADC_InjectedDelay.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_SelectInjectedDelay(SDADC_HandleTypeDef *hsdadc,
+ uint32_t InjectedDelay)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+ assert_param(IS_SDADC_INJECTED_DELAY(InjectedDelay));
+
+ /* Check SDADC state */
+ if(hsdadc->State == HAL_SDADC_STATE_READY)
+ {
+ /* Enter init mode */
+ if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
+ {
+ /* Set SDADC in error state */
+ hsdadc->State = HAL_SDADC_STATE_ERROR;
+ status = HAL_TIMEOUT;
+ }
+ else
+ {
+ /* Set JDS bit in SDADC_CR2 register */
+ hsdadc->Instance->CR2 &= ~(SDADC_CR2_JDS);
+ hsdadc->Instance->CR2 |= InjectedDelay;
+
+ /* Exit init mode */
+ SDADC_ExitInitMode(hsdadc);
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to configure multimode for regular conversions.
+ * @note This function should not be called if regular conversion is ongoing
+ * and should be could only for SDADC1.
+ * @param hsdadc SDADC handle.
+ * @param MultimodeType Type of multimode for regular conversions.
+ * This parameter can be a value of @ref SDADC_MultimodeType.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_MultiModeConfigChannel(SDADC_HandleTypeDef* hsdadc,
+ uint32_t MultimodeType)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+ assert_param(IS_SDADC_MULTIMODE_TYPE(MultimodeType));
+
+ /* Check instance is SDADC1 */
+ if(hsdadc->Instance != SDADC1)
+ {
+ status = HAL_ERROR;
+ }
+ /* Check SDADC state */
+ else if((hsdadc->State == HAL_SDADC_STATE_READY) || \
+ (hsdadc->State == HAL_SDADC_STATE_CALIB) || \
+ (hsdadc->State == HAL_SDADC_STATE_INJ))
+ {
+ /* Store regular trigger information */
+ hsdadc->RegularMultimode = MultimodeType;
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to configure multimode for injected conversions.
+ * @note This function should not be called if injected conversion is ongoing
+ * and should be could only for SDADC1.
+ * @param hsdadc SDADC handle.
+ * @param MultimodeType Type of multimode for injected conversions.
+ * This parameter can be a value of @ref SDADC_MultimodeType.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeConfigChannel(SDADC_HandleTypeDef* hsdadc,
+ uint32_t MultimodeType)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+ assert_param(IS_SDADC_MULTIMODE_TYPE(MultimodeType));
+
+ /* Check instance is SDADC1 */
+ if(hsdadc->Instance != SDADC1)
+ {
+ status = HAL_ERROR;
+ }
+ /* Check SDADC state */
+ else if((hsdadc->State == HAL_SDADC_STATE_READY) || \
+ (hsdadc->State == HAL_SDADC_STATE_CALIB) || \
+ (hsdadc->State == HAL_SDADC_STATE_REG))
+ {
+ /* Store regular trigger information */
+ hsdadc->InjectedMultimode = MultimodeType;
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SDADC_Exported_Functions_Group3 Input and Output operation functions
+ * @brief IO operation Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Start calibration.
+ (+) Poll for the end of calibration.
+ (+) Start calibration and enable interrupt.
+ (+) Start conversion of regular/injected channel.
+ (+) Poll for the end of regular/injected conversion.
+ (+) Stop conversion of regular/injected channel.
+ (+) Start conversion of regular/injected channel and enable interrupt.
+ (+) Stop conversion of regular/injected channel and disable interrupt.
+ (+) Start conversion of regular/injected channel and enable DMA transfer.
+ (+) Stop conversion of regular/injected channel and disable DMA transfer.
+ (+) Start multimode and enable DMA transfer for regular/injected conversion.
+ (+) Stop multimode and disable DMA transfer for regular/injected conversion..
+ (+) Get result of regular channel conversion.
+ (+) Get result of injected channel conversion.
+ (+) Get result of multimode conversion.
+ (+) Handle SDADC interrupt request.
+ (+) Callbacks for calibration and regular/injected conversions.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function allows to start calibration in polling mode.
+ * @note This function should be called only when SDADC instance is in idle state
+ * (neither calibration nor regular or injected conversion ongoing).
+ * @param hsdadc SDADC handle.
+ * @param CalibrationSequence Calibration sequence.
+ * This parameter can be a value of @ref SDADC_CalibrationSequence.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_CalibrationStart(SDADC_HandleTypeDef *hsdadc,
+ uint32_t CalibrationSequence)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+ assert_param(IS_SDADC_CALIB_SEQUENCE(CalibrationSequence));
+
+ /* Check SDADC state */
+ if(hsdadc->State == HAL_SDADC_STATE_READY)
+ {
+ /* Enter init mode */
+ if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
+ {
+ /* Set SDADC in error state */
+ hsdadc->State = HAL_SDADC_STATE_ERROR;
+ status = HAL_TIMEOUT;
+ }
+ else
+ {
+ /* Set CALIBCNT[1:0] bits in SDADC_CR2 register */
+ hsdadc->Instance->CR2 &= ~(SDADC_CR2_CALIBCNT);
+ hsdadc->Instance->CR2 |= CalibrationSequence;
+
+ /* Exit init mode */
+ SDADC_ExitInitMode(hsdadc);
+
+ /* Set STARTCALIB in SDADC_CR2 */
+ hsdadc->Instance->CR2 |= SDADC_CR2_STARTCALIB;
+
+ /* Set SDADC in calibration state */
+ hsdadc->State = HAL_SDADC_STATE_CALIB;
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to poll for the end of calibration.
+ * @note This function should be called only if calibration is ongoing.
+ * @param hsdadc SDADC handle.
+ * @param Timeout Timeout value in milliseconds.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_PollForCalibEvent(SDADC_HandleTypeDef* hsdadc, uint32_t Timeout)
+{
+ uint32_t tickstart;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+
+ /* Check SDADC state */
+ if(hsdadc->State != HAL_SDADC_STATE_CALIB)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait EOCALF bit in SDADC_ISR register */
+ while((hsdadc->Instance->ISR & SDADC_ISR_EOCALF) != SDADC_ISR_EOCALF)
+ {
+ /* Check the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if(((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0UL))
+ {
+ /* Return timeout status */
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /* Set CLREOCALF bit in SDADC_CLRISR register */
+ hsdadc->Instance->CLRISR |= SDADC_ISR_CLREOCALF;
+
+ /* Set SDADC in ready state */
+ hsdadc->State = HAL_SDADC_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+ }
+}
+
+/**
+ * @brief This function allows to start calibration in interrupt mode.
+ * @note This function should be called only when SDADC instance is in idle state
+ * (neither calibration nor regular or injected conversion ongoing).
+ * @param hsdadc SDADC handle.
+ * @param CalibrationSequence Calibration sequence.
+ * This parameter can be a value of @ref SDADC_CalibrationSequence.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_CalibrationStart_IT(SDADC_HandleTypeDef *hsdadc,
+ uint32_t CalibrationSequence)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+ assert_param(IS_SDADC_CALIB_SEQUENCE(CalibrationSequence));
+
+ /* Check SDADC state */
+ if(hsdadc->State == HAL_SDADC_STATE_READY)
+ {
+ /* Enter init mode */
+ if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
+ {
+ /* Set SDADC in error state */
+ hsdadc->State = HAL_SDADC_STATE_ERROR;
+ status = HAL_TIMEOUT;
+ }
+ else
+ {
+ /* Set CALIBCNT[1:0] bits in SDADC_CR2 register */
+ hsdadc->Instance->CR2 &= ~(SDADC_CR2_CALIBCNT);
+ hsdadc->Instance->CR2 |= CalibrationSequence;
+
+ /* Exit init mode */
+ SDADC_ExitInitMode(hsdadc);
+
+ /* Set EOCALIE bit in SDADC_CR1 register */
+ hsdadc->Instance->CR1 |= SDADC_CR1_EOCALIE;
+
+ /* Set STARTCALIB in SDADC_CR2 */
+ hsdadc->Instance->CR2 |= SDADC_CR2_STARTCALIB;
+
+ /* Set SDADC in calibration state */
+ hsdadc->State = HAL_SDADC_STATE_CALIB;
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to start regular conversion in polling mode.
+ * @note This function should be called only when SDADC instance is in idle state
+ * or if injected conversion is ongoing.
+ * @param hsdadc SDADC handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_Start(SDADC_HandleTypeDef *hsdadc)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+
+ /* Check SDADC state */
+ if((hsdadc->State == HAL_SDADC_STATE_READY) || \
+ (hsdadc->State == HAL_SDADC_STATE_INJ))
+ {
+ /* Start regular conversion */
+ status = SDADC_RegConvStart(hsdadc);
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to poll for the end of regular conversion.
+ * @note This function should be called only if regular conversion is ongoing.
+ * @param hsdadc SDADC handle.
+ * @param Timeout Timeout value in milliseconds.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_PollForConversion(SDADC_HandleTypeDef* hsdadc, uint32_t Timeout)
+{
+ uint32_t tickstart;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+
+ /* Check SDADC state */
+ if((hsdadc->State != HAL_SDADC_STATE_REG) && \
+ (hsdadc->State != HAL_SDADC_STATE_REG_INJ))
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait REOCF bit in SDADC_ISR register */
+ while((hsdadc->Instance->ISR & SDADC_ISR_REOCF) != SDADC_ISR_REOCF)
+ {
+ /* Check the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if(((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0UL))
+ {
+ /* Return timeout status */
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /* Check if overrun occurs */
+ if((hsdadc->Instance->ISR & SDADC_ISR_ROVRF) == SDADC_ISR_ROVRF)
+ {
+ /* Update error code and call error callback */
+ hsdadc->ErrorCode = SDADC_ERROR_REGULAR_OVERRUN;
+ HAL_SDADC_ErrorCallback(hsdadc);
+
+ /* Set CLRROVRF bit in SDADC_CLRISR register */
+ hsdadc->Instance->CLRISR |= SDADC_ISR_CLRROVRF;
+ }
+ /* Update SDADC state only if not continuous conversion and SW trigger */
+ if((hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_OFF) && \
+ (hsdadc->RegularTrigger == SDADC_SOFTWARE_TRIGGER))
+ {
+ hsdadc->State = (hsdadc->State == HAL_SDADC_STATE_REG) ? \
+ HAL_SDADC_STATE_READY : HAL_SDADC_STATE_INJ;
+ }
+ /* Return function status */
+ return HAL_OK;
+ }
+}
+
+/**
+ * @brief This function allows to stop regular conversion in polling mode.
+ * @note This function should be called only if regular conversion is ongoing.
+ * @param hsdadc SDADC handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_Stop(SDADC_HandleTypeDef *hsdadc)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+
+ /* Check SDADC state */
+ if((hsdadc->State != HAL_SDADC_STATE_REG) && \
+ (hsdadc->State != HAL_SDADC_STATE_REG_INJ))
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Stop regular conversion */
+ status = SDADC_RegConvStop(hsdadc);
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to start regular conversion in interrupt mode.
+ * @note This function should be called only when SDADC instance is in idle state
+ * or if injected conversion is ongoing.
+ * @param hsdadc SDADC handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_Start_IT(SDADC_HandleTypeDef *hsdadc)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+
+ /* Check SDADC state */
+ if((hsdadc->State == HAL_SDADC_STATE_READY) || \
+ (hsdadc->State == HAL_SDADC_STATE_INJ))
+ {
+ /* Set REOCIE and ROVRIE bits in SDADC_CR1 register */
+ hsdadc->Instance->CR1 |= (uint32_t) (SDADC_CR1_REOCIE | SDADC_CR1_ROVRIE);
+
+ /* Start regular conversion */
+ status = SDADC_RegConvStart(hsdadc);
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to stop regular conversion in interrupt mode.
+ * @note This function should be called only if regular conversion is ongoing.
+ * @param hsdadc SDADC handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_Stop_IT(SDADC_HandleTypeDef *hsdadc)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+
+ /* Check SDADC state */
+ if((hsdadc->State != HAL_SDADC_STATE_REG) && \
+ (hsdadc->State != HAL_SDADC_STATE_REG_INJ))
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Clear REOCIE and ROVRIE bits in SDADC_CR1 register */
+ hsdadc->Instance->CR1 &= (uint32_t) ~(SDADC_CR1_REOCIE | SDADC_CR1_ROVRIE);
+
+ /* Stop regular conversion */
+ status = SDADC_RegConvStop(hsdadc);
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to start regular conversion in DMA mode.
+ * @note This function should be called only when SDADC instance is in idle state
+ * or if injected conversion is ongoing.
+ * @param hsdadc SDADC handle.
+ * @param pData The destination buffer address.
+ * @param Length The length of data to be transferred from SDADC peripheral to memory.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_Start_DMA(SDADC_HandleTypeDef *hsdadc, uint32_t *pData,
+ uint32_t Length)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+ assert_param(pData != ((void*) 0));
+ assert_param(Length != 0UL);
+
+ /* Check that DMA is not enabled for injected conversion */
+ if((hsdadc->Instance->CR1 & SDADC_CR1_JDMAEN) == SDADC_CR1_JDMAEN)
+ {
+ status = HAL_ERROR;
+ }
+ /* Check parameters compatibility */
+ else if((hsdadc->RegularTrigger == SDADC_SOFTWARE_TRIGGER) && \
+ (hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_OFF) && \
+ (hsdadc->hdma->Init.Mode == DMA_NORMAL) && \
+ (Length != 1U))
+ {
+ status = HAL_ERROR;
+ }
+ else if((hsdadc->RegularTrigger == SDADC_SOFTWARE_TRIGGER) && \
+ (hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_OFF) && \
+ (hsdadc->hdma->Init.Mode == DMA_CIRCULAR))
+ {
+ status = HAL_ERROR;
+ }
+ /* Check SDADC state */
+ else if((hsdadc->State == HAL_SDADC_STATE_READY) || \
+ (hsdadc->State == HAL_SDADC_STATE_INJ))
+ {
+ /* Set callbacks on DMA handler */
+ hsdadc->hdma->XferCpltCallback = SDADC_DMARegularConvCplt;
+ hsdadc->hdma->XferErrorCallback = SDADC_DMAError;
+ if(hsdadc->hdma->Init.Mode == DMA_CIRCULAR)
+ {
+ hsdadc->hdma->XferHalfCpltCallback = SDADC_DMARegularHalfConvCplt;
+ }
+
+ /* Set RDMAEN bit in SDADC_CR1 register */
+ hsdadc->Instance->CR1 |= SDADC_CR1_RDMAEN;
+
+ /* Start DMA in interrupt mode */
+ if(HAL_DMA_Start_IT(hsdadc->hdma, (uint32_t)&hsdadc->Instance->RDATAR, \
+ (uint32_t) pData, Length) != HAL_OK)
+ {
+ /* Set SDADC in error state */
+ hsdadc->State = HAL_SDADC_STATE_ERROR;
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Start regular conversion */
+ status = SDADC_RegConvStart(hsdadc);
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to stop regular conversion in DMA mode.
+ * @note This function should be called only if regular conversion is ongoing.
+ * @param hsdadc SDADC handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_Stop_DMA(SDADC_HandleTypeDef *hsdadc)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+
+ /* Check SDADC state */
+ if((hsdadc->State != HAL_SDADC_STATE_REG) && \
+ (hsdadc->State != HAL_SDADC_STATE_REG_INJ))
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Clear RDMAEN bit in SDADC_CR1 register */
+ hsdadc->Instance->CR1 &= ~(SDADC_CR1_RDMAEN);
+
+ /* Stop current DMA transfer */
+ if(HAL_DMA_Abort(hsdadc->hdma) != HAL_OK)
+ {
+ /* Set SDADC in error state */
+ hsdadc->State = HAL_SDADC_STATE_ERROR;
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Stop regular conversion */
+ status = SDADC_RegConvStop(hsdadc);
+ }
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to get regular conversion value.
+ * @param hsdadc SDADC handle.
+ * @retval Regular conversion value
+ */
+uint32_t HAL_SDADC_GetValue(SDADC_HandleTypeDef *hsdadc)
+{
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+
+ /* Return regular conversion value */
+ return hsdadc->Instance->RDATAR;
+}
+
+/**
+ * @brief This function allows to start injected conversion in polling mode.
+ * @note This function should be called only when SDADC instance is in idle state
+ * or if regular conversion is ongoing.
+ * @param hsdadc SDADC handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_InjectedStart(SDADC_HandleTypeDef *hsdadc)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+
+ /* Check SDADC state */
+ if((hsdadc->State == HAL_SDADC_STATE_READY) || \
+ (hsdadc->State == HAL_SDADC_STATE_REG))
+ {
+ /* Start injected conversion */
+ status = SDADC_InjConvStart(hsdadc);
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to poll for the end of injected conversion.
+ * @note This function should be called only if injected conversion is ongoing.
+ * @param hsdadc SDADC handle.
+ * @param Timeout Timeout value in milliseconds.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_PollForInjectedConversion(SDADC_HandleTypeDef* hsdadc,
+ uint32_t Timeout)
+{
+ uint32_t tickstart;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+
+ /* Check SDADC state */
+ if((hsdadc->State != HAL_SDADC_STATE_INJ) && \
+ (hsdadc->State != HAL_SDADC_STATE_REG_INJ))
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait JEOCF bit in SDADC_ISR register */
+ while((hsdadc->Instance->ISR & SDADC_ISR_JEOCF) != SDADC_ISR_JEOCF)
+ {
+ /* Check the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if(((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0UL))
+ {
+ /* Return timeout status */
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /* Check if overrun occurs */
+ if((hsdadc->Instance->ISR & SDADC_ISR_JOVRF) == SDADC_ISR_JOVRF)
+ {
+ /* Update error code and call error callback */
+ hsdadc->ErrorCode = SDADC_ERROR_INJECTED_OVERRUN;
+ HAL_SDADC_ErrorCallback(hsdadc);
+
+ /* Set CLRJOVRF bit in SDADC_CLRISR register */
+ hsdadc->Instance->CLRISR |= SDADC_ISR_CLRJOVRF;
+ }
+ /* Update remaining injected conversions */
+ hsdadc->InjConvRemaining--;
+ if(hsdadc->InjConvRemaining == 0UL)
+ {
+ /* end of injected sequence, reset the value */
+ hsdadc->InjConvRemaining = hsdadc->InjectedChannelsNbr;
+ }
+
+ /* Update SDADC state only if not continuous conversion, SW trigger */
+ /* and end of injected sequence */
+ if((hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_OFF) && \
+ (hsdadc->InjectedTrigger == SDADC_SOFTWARE_TRIGGER) && \
+ (hsdadc->InjConvRemaining == hsdadc->InjectedChannelsNbr))
+ {
+ hsdadc->State = (hsdadc->State == HAL_SDADC_STATE_INJ) ? \
+ HAL_SDADC_STATE_READY : HAL_SDADC_STATE_REG;
+ }
+ /* Return function status */
+ return HAL_OK;
+ }
+}
+
+/**
+ * @brief This function allows to stop injected conversion in polling mode.
+ * @note This function should be called only if injected conversion is ongoing.
+ * @param hsdadc SDADC handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_InjectedStop(SDADC_HandleTypeDef *hsdadc)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+
+ /* Check SDADC state */
+ if((hsdadc->State != HAL_SDADC_STATE_INJ) && \
+ (hsdadc->State != HAL_SDADC_STATE_REG_INJ))
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Stop injected conversion */
+ status = SDADC_InjConvStop(hsdadc);
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to start injected conversion in interrupt mode.
+ * @note This function should be called only when SDADC instance is in idle state
+ * or if regular conversion is ongoing.
+ * @param hsdadc SDADC handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_InjectedStart_IT(SDADC_HandleTypeDef *hsdadc)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+
+ /* Check SDADC state */
+ if((hsdadc->State == HAL_SDADC_STATE_READY) || \
+ (hsdadc->State == HAL_SDADC_STATE_REG))
+ {
+ /* Set JEOCIE and JOVRIE bits in SDADC_CR1 register */
+ hsdadc->Instance->CR1 |= (uint32_t) (SDADC_CR1_JEOCIE | SDADC_CR1_JOVRIE);
+
+ /* Start injected conversion */
+ status = SDADC_InjConvStart(hsdadc);
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to stop injected conversion in interrupt mode.
+ * @note This function should be called only if injected conversion is ongoing.
+ * @param hsdadc SDADC handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_InjectedStop_IT(SDADC_HandleTypeDef *hsdadc)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+
+ /* Check SDADC state */
+ if((hsdadc->State != HAL_SDADC_STATE_INJ) && \
+ (hsdadc->State != HAL_SDADC_STATE_REG_INJ))
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Clear JEOCIE and JOVRIE bits in SDADC_CR1 register */
+ hsdadc->Instance->CR1 &= (uint32_t) ~(SDADC_CR1_JEOCIE | SDADC_CR1_JOVRIE);
+
+ /* Stop injected conversion */
+ status = SDADC_InjConvStop(hsdadc);
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to start injected conversion in DMA mode.
+ * @note This function should be called only when SDADC instance is in idle state
+ * or if regular conversion is ongoing.
+ * @param hsdadc SDADC handle.
+ * @param pData The destination buffer address.
+ * @param Length The length of data to be transferred from SDADC peripheral to memory.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_InjectedStart_DMA(SDADC_HandleTypeDef *hsdadc, uint32_t *pData,
+ uint32_t Length)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+ assert_param(pData != ((void*) 0));
+ assert_param(Length != 0UL);
+
+ /* Check that DMA is not enabled for regular conversion */
+ if((hsdadc->Instance->CR1 & SDADC_CR1_RDMAEN) == SDADC_CR1_RDMAEN)
+ {
+ status = HAL_ERROR;
+ }
+ /* Check parameters compatibility */
+ else if((hsdadc->InjectedTrigger == SDADC_SOFTWARE_TRIGGER) && \
+ (hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_OFF) && \
+ (hsdadc->hdma->Init.Mode == DMA_NORMAL) && \
+ (Length > hsdadc->InjectedChannelsNbr))
+ {
+ status = HAL_ERROR;
+ }
+ else if((hsdadc->InjectedTrigger == SDADC_SOFTWARE_TRIGGER) && \
+ (hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_OFF) && \
+ (hsdadc->hdma->Init.Mode == DMA_CIRCULAR))
+ {
+ status = HAL_ERROR;
+ }
+ /* Check SDADC state */
+ else if((hsdadc->State == HAL_SDADC_STATE_READY) || \
+ (hsdadc->State == HAL_SDADC_STATE_REG))
+ {
+ /* Set callbacks on DMA handler */
+ hsdadc->hdma->XferCpltCallback = SDADC_DMAInjectedConvCplt;
+ hsdadc->hdma->XferErrorCallback = SDADC_DMAError;
+ if(hsdadc->hdma->Init.Mode == DMA_CIRCULAR)
+ {
+ hsdadc->hdma->XferHalfCpltCallback = SDADC_DMAInjectedHalfConvCplt;
+ }
+
+ /* Set JDMAEN bit in SDADC_CR1 register */
+ hsdadc->Instance->CR1 |= SDADC_CR1_JDMAEN;
+
+ /* Start DMA in interrupt mode */
+ if(HAL_DMA_Start_IT(hsdadc->hdma, (uint32_t)&hsdadc->Instance->JDATAR, \
+ (uint32_t) pData, Length) != HAL_OK)
+ {
+ /* Set SDADC in error state */
+ hsdadc->State = HAL_SDADC_STATE_ERROR;
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Start injected conversion */
+ status = SDADC_InjConvStart(hsdadc);
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to stop injected conversion in DMA mode.
+ * @note This function should be called only if injected conversion is ongoing.
+ * @param hsdadc SDADC handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_InjectedStop_DMA(SDADC_HandleTypeDef *hsdadc)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+
+ /* Check SDADC state */
+ if((hsdadc->State != HAL_SDADC_STATE_INJ) && \
+ (hsdadc->State != HAL_SDADC_STATE_REG_INJ))
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Clear JDMAEN bit in SDADC_CR1 register */
+ hsdadc->Instance->CR1 &= ~(SDADC_CR1_JDMAEN);
+
+ /* Stop current DMA transfer */
+ if(HAL_DMA_Abort(hsdadc->hdma) != HAL_OK)
+ {
+ /* Set SDADC in error state */
+ hsdadc->State = HAL_SDADC_STATE_ERROR;
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Stop injected conversion */
+ status = SDADC_InjConvStop(hsdadc);
+ }
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to get injected conversion value.
+ * @param hsdadc SDADC handle.
+ * @param Channel Corresponding channel of injected conversion.
+ * @retval Injected conversion value
+ */
+uint32_t HAL_SDADC_InjectedGetValue(SDADC_HandleTypeDef *hsdadc, uint32_t* Channel)
+{
+ uint32_t value;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+ assert_param(Channel != ((void*) 0));
+
+ /* Read SDADC_JDATAR register and extract channel and conversion value */
+ value = hsdadc->Instance->JDATAR;
+ *Channel = ((value & SDADC_JDATAR_JDATACH) >> SDADC_JDATAR_CH_OFFSET);
+ value &= SDADC_JDATAR_JDATA;
+
+ /* Return injected conversion value */
+ return value;
+}
+
+/**
+ * @brief This function allows to start multimode regular conversions in DMA mode.
+ * @note This function should be called only when SDADC instance is in idle state
+ * or if injected conversion is ongoing.
+ * @param hsdadc SDADC handle.
+ * @param pData The destination buffer address.
+ * @param Length The length of data to be transferred from SDADC peripheral to memory.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_MultiModeStart_DMA(SDADC_HandleTypeDef* hsdadc, uint32_t* pData,
+ uint32_t Length)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+ assert_param(pData != ((void*) 0));
+ assert_param(Length != 0UL);
+
+ /* Check instance is SDADC1 */
+ if(hsdadc->Instance != SDADC1)
+ {
+ status = HAL_ERROR;
+ }
+ /* Check that DMA is not enabled for injected conversion */
+ else if((hsdadc->Instance->CR1 & SDADC_CR1_JDMAEN) == SDADC_CR1_JDMAEN)
+ {
+ status = HAL_ERROR;
+ }
+ /* Check parameters compatibility */
+ else if((hsdadc->RegularTrigger == SDADC_SOFTWARE_TRIGGER) && \
+ (hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_OFF) && \
+ (hsdadc->hdma->Init.Mode == DMA_NORMAL) && \
+ (Length != 1U))
+ {
+ status = HAL_ERROR;
+ }
+ else if((hsdadc->RegularTrigger == SDADC_SOFTWARE_TRIGGER) && \
+ (hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_OFF) && \
+ (hsdadc->hdma->Init.Mode == DMA_CIRCULAR))
+ {
+ status = HAL_ERROR;
+ }
+ /* Check SDADC state */
+ else if((hsdadc->State == HAL_SDADC_STATE_READY) || \
+ (hsdadc->State == HAL_SDADC_STATE_INJ))
+ {
+ /* Set callbacks on DMA handler */
+ hsdadc->hdma->XferCpltCallback = SDADC_DMARegularConvCplt;
+ hsdadc->hdma->XferErrorCallback = SDADC_DMAError;
+ if(hsdadc->hdma->Init.Mode == DMA_CIRCULAR)
+ {
+ hsdadc->hdma->XferHalfCpltCallback = SDADC_DMARegularHalfConvCplt;
+ }
+ /* Set RDMAEN bit in SDADC_CR1 register */
+ hsdadc->Instance->CR1 |= SDADC_CR1_RDMAEN;
+
+ /* Start DMA in interrupt mode */
+ if(hsdadc->RegularMultimode == SDADC_MULTIMODE_SDADC1_SDADC2)
+ {
+ status = HAL_DMA_Start_IT(hsdadc->hdma, (uint32_t)&hsdadc->Instance->RDATA12R, \
+ (uint32_t) pData, Length);
+ }
+ else
+ {
+ status = HAL_DMA_Start_IT(hsdadc->hdma, (uint32_t)&hsdadc->Instance->RDATA13R, \
+ (uint32_t) pData, Length);
+ }
+ if(status != HAL_OK)
+ {
+ /* Set SDADC in error state */
+ hsdadc->State = HAL_SDADC_STATE_ERROR;
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Start regular conversion */
+ status = SDADC_RegConvStart(hsdadc);
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to stop multimode regular conversions in DMA mode.
+ * @note This function should be called only if regular conversion is ongoing.
+ * @param hsdadc SDADC handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_MultiModeStop_DMA(SDADC_HandleTypeDef* hsdadc)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+
+ /* Check instance is SDADC1 */
+ if(hsdadc->Instance != SDADC1)
+ {
+ status = HAL_ERROR;
+ }
+ /* Check SDADC state */
+ else if((hsdadc->State != HAL_SDADC_STATE_REG) && \
+ (hsdadc->State != HAL_SDADC_STATE_REG_INJ))
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Clear RDMAEN bit in SDADC_CR1 register */
+ hsdadc->Instance->CR1 &= ~(SDADC_CR1_RDMAEN);
+
+ /* Stop current DMA transfer */
+ if(HAL_DMA_Abort(hsdadc->hdma) != HAL_OK)
+ {
+ /* Set SDADC in error state */
+ hsdadc->State = HAL_SDADC_STATE_ERROR;
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Stop regular conversion */
+ status = SDADC_RegConvStop(hsdadc);
+ }
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to get multimode regular conversion value.
+ * @param hsdadc SDADC handle.
+ * @retval Multimode regular conversion value
+ */
+uint32_t HAL_SDADC_MultiModeGetValue(SDADC_HandleTypeDef* hsdadc)
+{
+ uint32_t value;
+
+ /* Check parameters and check instance is SDADC1 */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+ assert_param(hsdadc->Instance == SDADC1);
+
+ /* read multimode regular value */
+ value = (hsdadc->RegularMultimode == SDADC_MULTIMODE_SDADC1_SDADC2) ? \
+ hsdadc->Instance->RDATA12R : hsdadc->Instance->RDATA13R;
+
+ /* Return multimode regular conversions value */
+ return value;
+}
+
+/**
+ * @brief This function allows to start multimode injected conversions in DMA mode.
+ * @note This function should be called only when SDADC instance is in idle state
+ * or if regular conversion is ongoing.
+ * @param hsdadc SDADC handle.
+ * @param pData The destination buffer address.
+ * @param Length The length of data to be transferred from SDADC peripheral to memory.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeStart_DMA(SDADC_HandleTypeDef* hsdadc,
+ uint32_t* pData, uint32_t Length)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+ assert_param(pData != ((void*) 0));
+ assert_param(Length != 0UL);
+
+ /* Check instance is SDADC1 */
+ if(hsdadc->Instance != SDADC1)
+ {
+ status = HAL_ERROR;
+ }
+ /* Check that DMA is not enabled for regular conversion */
+ else if((hsdadc->Instance->CR1 & SDADC_CR1_RDMAEN) == SDADC_CR1_RDMAEN)
+ {
+ status = HAL_ERROR;
+ }
+ /* Check parameters compatibility */
+ else if((hsdadc->InjectedTrigger == SDADC_SOFTWARE_TRIGGER) && \
+ (hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_OFF) && \
+ (hsdadc->hdma->Init.Mode == DMA_NORMAL) && \
+ (Length > (hsdadc->InjectedChannelsNbr << 1U)))
+ {
+ status = HAL_ERROR;
+ }
+ else if((hsdadc->InjectedTrigger == SDADC_SOFTWARE_TRIGGER) && \
+ (hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_OFF) && \
+ (hsdadc->hdma->Init.Mode == DMA_CIRCULAR))
+ {
+ status = HAL_ERROR;
+ }
+ /* Check SDADC state */
+ else if((hsdadc->State == HAL_SDADC_STATE_READY) || \
+ (hsdadc->State == HAL_SDADC_STATE_REG))
+ {
+ /* Set callbacks on DMA handler */
+ hsdadc->hdma->XferCpltCallback = SDADC_DMAInjectedConvCplt;
+ hsdadc->hdma->XferErrorCallback = SDADC_DMAError;
+ if(hsdadc->hdma->Init.Mode == DMA_CIRCULAR)
+ {
+ hsdadc->hdma->XferHalfCpltCallback = SDADC_DMAInjectedHalfConvCplt;
+ }
+ /* Set JDMAEN bit in SDADC_CR1 register */
+ hsdadc->Instance->CR1 |= SDADC_CR1_JDMAEN;
+
+ /* Start DMA in interrupt mode */
+ if(hsdadc->InjectedMultimode == SDADC_MULTIMODE_SDADC1_SDADC2)
+ {
+ status = HAL_DMA_Start_IT(hsdadc->hdma, (uint32_t)&hsdadc->Instance->JDATA12R, \
+ (uint32_t) pData, Length);
+ }
+ else
+ {
+ status = HAL_DMA_Start_IT(hsdadc->hdma, (uint32_t)&hsdadc->Instance->JDATA13R, \
+ (uint32_t) pData, Length);
+ }
+ if(status != HAL_OK)
+ {
+ /* Set SDADC in error state */
+ hsdadc->State = HAL_SDADC_STATE_ERROR;
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Start injected conversion */
+ status = SDADC_InjConvStart(hsdadc);
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to stop multimode injected conversions in DMA mode.
+ * @note This function should be called only if injected conversion is ongoing.
+ * @param hsdadc SDADC handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeStop_DMA(SDADC_HandleTypeDef* hsdadc)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+
+ /* Check instance is SDADC1 */
+ if(hsdadc->Instance != SDADC1)
+ {
+ status = HAL_ERROR;
+ }
+ /* Check SDADC state */
+ else if((hsdadc->State != HAL_SDADC_STATE_INJ) && \
+ (hsdadc->State != HAL_SDADC_STATE_REG_INJ))
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Clear JDMAEN bit in SDADC_CR1 register */
+ hsdadc->Instance->CR1 &= ~(SDADC_CR1_JDMAEN);
+
+ /* Stop current DMA transfer */
+ if(HAL_DMA_Abort(hsdadc->hdma) != HAL_OK)
+ {
+ /* Set SDADC in error state */
+ hsdadc->State = HAL_SDADC_STATE_ERROR;
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Stop injected conversion */
+ status = SDADC_InjConvStop(hsdadc);
+ }
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to get multimode injected conversion value.
+ * @param hsdadc SDADC handle.
+ * @retval Multimode injected conversion value
+ */
+uint32_t HAL_SDADC_InjectedMultiModeGetValue(SDADC_HandleTypeDef* hsdadc)
+{
+ uint32_t value;
+
+ /* Check parameters and check instance is SDADC1 */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+ assert_param(hsdadc->Instance == SDADC1);
+
+ /* read multimode injected value */
+ value = (hsdadc->InjectedMultimode == SDADC_MULTIMODE_SDADC1_SDADC2) ? \
+ hsdadc->Instance->JDATA12R : hsdadc->Instance->JDATA13R;
+
+ /* Return multimode injected conversions value */
+ return value;
+}
+
+/**
+ * @brief This function handles the SDADC interrupts.
+ * @param hsdadc SDADC handle.
+ * @retval None
+ */
+void HAL_SDADC_IRQHandler(SDADC_HandleTypeDef* hsdadc)
+{
+ uint32_t tmp_isr = hsdadc->Instance->ISR;
+
+ /* Check if end of regular conversion */
+ if(((hsdadc->Instance->CR1 & SDADC_CR1_REOCIE) == SDADC_CR1_REOCIE) &&
+ ((tmp_isr & SDADC_ISR_REOCF) == SDADC_ISR_REOCF))
+ {
+ /* Call regular conversion complete callback */
+ HAL_SDADC_ConvCpltCallback(hsdadc);
+
+ /* End of conversion if mode is not continuous and software trigger */
+ if((hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_OFF) && \
+ (hsdadc->RegularTrigger == SDADC_SOFTWARE_TRIGGER))
+ {
+ /* Clear REOCIE and ROVRIE bits in SDADC_CR1 register */
+ hsdadc->Instance->CR1 &= ~(SDADC_CR1_REOCIE | SDADC_CR1_ROVRIE);
+
+ /* Update SDADC state */
+ hsdadc->State = (hsdadc->State == HAL_SDADC_STATE_REG) ? \
+ HAL_SDADC_STATE_READY : HAL_SDADC_STATE_INJ;
+ }
+ }
+ /* Check if end of injected conversion */
+ else if(((hsdadc->Instance->CR1 & SDADC_CR1_JEOCIE) == SDADC_CR1_JEOCIE) &&
+ ((tmp_isr & SDADC_ISR_JEOCF) == SDADC_ISR_JEOCF))
+ {
+ /* Call injected conversion complete callback */
+ HAL_SDADC_InjectedConvCpltCallback(hsdadc);
+
+ /* Update remaining injected conversions */
+ hsdadc->InjConvRemaining--;
+ if(hsdadc->InjConvRemaining ==0UL)
+ {
+ /* end of injected sequence, reset the value */
+ hsdadc->InjConvRemaining = hsdadc->InjectedChannelsNbr;
+ }
+ /* End of conversion if mode is not continuous, software trigger */
+ /* and end of injected sequence */
+ if((hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_OFF) && \
+ (hsdadc->InjectedTrigger == SDADC_SOFTWARE_TRIGGER) && \
+ (hsdadc->InjConvRemaining == hsdadc->InjectedChannelsNbr))
+ {
+ /* Clear JEOCIE and JOVRIE bits in SDADC_CR1 register */
+ hsdadc->Instance->CR1 &= ~(SDADC_CR1_JEOCIE | SDADC_CR1_JOVRIE);
+
+ /* Update SDADC state */
+ hsdadc->State = (hsdadc->State == HAL_SDADC_STATE_INJ) ? \
+ HAL_SDADC_STATE_READY : HAL_SDADC_STATE_REG;
+ }
+ }
+ /* Check if end of calibration */
+ else if(((hsdadc->Instance->CR1 & SDADC_CR1_EOCALIE) == SDADC_CR1_EOCALIE) &&
+ ((tmp_isr & SDADC_ISR_EOCALF) == SDADC_ISR_EOCALF))
+ {
+ /* Clear EOCALIE bit in SDADC_CR1 register */
+ hsdadc->Instance->CR1 &= ~(SDADC_CR1_EOCALIE);
+
+ /* Set CLREOCALF bit in SDADC_CLRISR register */
+ hsdadc->Instance->CLRISR |= SDADC_ISR_CLREOCALF;
+
+ /* Call calibration callback */
+ HAL_SDADC_CalibrationCpltCallback(hsdadc);
+
+ /* Update SDADC state */
+ hsdadc->State = HAL_SDADC_STATE_READY;
+ }
+ /* Check if overrun occurs during regular conversion */
+ else if(((hsdadc->Instance->CR1 & SDADC_CR1_ROVRIE) == SDADC_CR1_ROVRIE) &&
+ ((tmp_isr & SDADC_ISR_ROVRF) == SDADC_ISR_ROVRF))
+ {
+ /* Set CLRROVRF bit in SDADC_CLRISR register */
+ hsdadc->Instance->CLRISR |= SDADC_ISR_CLRROVRF;
+
+ /* Update error code */
+ hsdadc->ErrorCode = SDADC_ERROR_REGULAR_OVERRUN;
+
+ /* Call error callback */
+ HAL_SDADC_ErrorCallback(hsdadc);
+ }
+ /* Check if overrun occurs during injected conversion */
+ else if(((hsdadc->Instance->CR1 & SDADC_CR1_JOVRIE) == SDADC_CR1_JOVRIE) &&
+ ((tmp_isr & SDADC_ISR_JOVRF) == SDADC_ISR_JOVRF))
+ {
+ /* Set CLRJOVRF bit in SDADC_CLRISR register */
+ hsdadc->Instance->CLRISR |= SDADC_ISR_CLRJOVRF;
+
+ /* Update error code */
+ hsdadc->ErrorCode = SDADC_ERROR_INJECTED_OVERRUN;
+
+ /* Call error callback */
+ HAL_SDADC_ErrorCallback(hsdadc);
+ }
+ else
+ {
+ /* No additional IRQ source */
+ }
+
+ return;
+}
+
+/**
+ * @brief Calibration complete callback.
+ * @param hsdadc SDADC handle.
+ * @retval None
+ */
+__weak void HAL_SDADC_CalibrationCpltCallback(SDADC_HandleTypeDef* hsdadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsdadc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SDADC_CalibrationCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Half regular conversion complete callback.
+ * @param hsdadc SDADC handle.
+ * @retval None
+ */
+__weak void HAL_SDADC_ConvHalfCpltCallback(SDADC_HandleTypeDef* hsdadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsdadc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SDADC_ConvHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Regular conversion complete callback.
+ * @note In interrupt mode, user has to read conversion value in this function
+ using HAL_SDADC_GetValue or HAL_SDADC_MultiModeGetValue.
+ * @param hsdadc SDADC handle.
+ * @retval None
+ */
+__weak void HAL_SDADC_ConvCpltCallback(SDADC_HandleTypeDef* hsdadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsdadc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SDADC_ConvCpltCallback could be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Half injected conversion complete callback.
+ * @param hsdadc SDADC handle.
+ * @retval None
+ */
+__weak void HAL_SDADC_InjectedConvHalfCpltCallback(SDADC_HandleTypeDef* hsdadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsdadc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SDADC_InjectedConvHalfCpltCallback could be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Injected conversion complete callback.
+ * @note In interrupt mode, user has to read conversion value in this function
+ using HAL_SDADC_InjectedGetValue or HAL_SDADC_InjectedMultiModeGetValue.
+ * @param hsdadc SDADC handle.
+ * @retval None
+ */
+__weak void HAL_SDADC_InjectedConvCpltCallback(SDADC_HandleTypeDef* hsdadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsdadc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SDADC_InjectedConvCpltCallback could be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Error callback.
+ * @param hsdadc SDADC handle.
+ * @retval None
+ */
+__weak void HAL_SDADC_ErrorCallback(SDADC_HandleTypeDef* hsdadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsdadc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SDADC_ErrorCallback could be implemented in the user file.
+ */
+}
+
+/**
+ * @brief DMA half transfer complete callback for regular conversion.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SDADC_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma)
+{
+ /* Get SDADC handle */
+ SDADC_HandleTypeDef* hsdadc = (SDADC_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* Call regular half conversion complete callback */
+ HAL_SDADC_ConvHalfCpltCallback(hsdadc);
+}
+
+/**
+ * @brief DMA transfer complete callback for regular conversion.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SDADC_DMARegularConvCplt(DMA_HandleTypeDef *hdma)
+{
+ /* Get SDADC handle */
+ SDADC_HandleTypeDef* hsdadc = (SDADC_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* Call regular conversion complete callback */
+ HAL_SDADC_ConvCpltCallback(hsdadc);
+}
+
+/**
+ * @brief DMA half transfer complete callback for injected conversion.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SDADC_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma)
+{
+ /* Get SDADC handle */
+ SDADC_HandleTypeDef* hsdadc = (SDADC_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* Call injected half conversion complete callback */
+ HAL_SDADC_InjectedConvHalfCpltCallback(hsdadc);
+}
+
+/**
+ * @brief DMA transfer complete callback for injected conversion.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SDADC_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma)
+{
+ /* Get SDADC handle */
+ SDADC_HandleTypeDef* hsdadc = (SDADC_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* Call injected conversion complete callback */
+ HAL_SDADC_InjectedConvCpltCallback(hsdadc);
+}
+
+/**
+ * @brief DMA error callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SDADC_DMAError(DMA_HandleTypeDef *hdma)
+{
+ /* Get SDADC handle */
+ SDADC_HandleTypeDef* hsdadc = (SDADC_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* Update error code */
+ hsdadc->ErrorCode = SDADC_ERROR_DMA;
+
+ /* Call error callback */
+ HAL_SDADC_ErrorCallback(hsdadc);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SDADC_Exported_Functions_Group4 Peripheral State functions
+ * @brief SDADC Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### ADC Peripheral State functions #####
+ ===============================================================================
+ [..] This subsection provides functions allowing to
+ (+) Get the SDADC state
+ (+) Get the SDADC Error
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function allows to get the current SDADC state.
+ * @param hsdadc SDADC handle.
+ * @retval SDADC state.
+ */
+HAL_SDADC_StateTypeDef HAL_SDADC_GetState(SDADC_HandleTypeDef* hsdadc)
+{
+ return hsdadc->State;
+}
+
+/**
+ * @brief This function allows to get the current SDADC error code.
+ * @param hsdadc SDADC handle.
+ * @retval SDADC error code.
+ */
+uint32_t HAL_SDADC_GetError(SDADC_HandleTypeDef* hsdadc)
+{
+ return hsdadc->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup SDADC_Private_Functions SDADC Private Functions
+ * @{
+ */
+
+/**
+ * @brief This function allows to enter in init mode for SDADC instance.
+ * @param hsdadc SDADC handle.
+ * @retval HAL status.
+ */
+static HAL_StatusTypeDef SDADC_EnterInitMode(SDADC_HandleTypeDef* hsdadc)
+{
+ uint32_t tickstart;
+
+ /* Set INIT bit on SDADC_CR1 register */
+ hsdadc->Instance->CR1 |= SDADC_CR1_INIT;
+
+ /* Wait INITRDY bit on SDADC_ISR */
+ tickstart = HAL_GetTick();
+ while((hsdadc->Instance->ISR & SDADC_ISR_INITRDY) == (uint32_t)RESET)
+ {
+ if((HAL_GetTick()-tickstart) > SDADC_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Return HAL status */
+ return HAL_OK;
+}
+
+/**
+ * @brief This function allows to exit from init mode for SDADC instance.
+ * @param hsdadc SDADC handle.
+ * @retval None.
+ */
+static void SDADC_ExitInitMode(SDADC_HandleTypeDef* hsdadc)
+{
+ /* Reset INIT bit in SDADC_CR1 register */
+ hsdadc->Instance->CR1 &= ~(SDADC_CR1_INIT);
+}
+
+/**
+ * @brief This function allows to get the number of injected channels.
+ * @param Channels bitfield of injected channels.
+ * @retval Number of injected channels.
+ */
+static uint32_t SDADC_GetInjChannelsNbr(uint32_t Channels)
+{
+ uint32_t nbChannels = 0UL;
+ uint32_t tmp,i;
+
+ /* Get the number of channels from bitfield */
+ tmp = (uint32_t) (Channels & SDADC_LSB_MASK);
+ for(i = 0UL ; i < 9UL ; i++)
+ {
+ if((tmp & 0x00000001UL) != 0UL)
+ {
+ nbChannels++;
+ }
+ tmp = (uint32_t) (tmp >> 1UL);
+ }
+ return nbChannels;
+}
+
+/**
+ * @brief This function allows to really start regular conversion.
+ * @param hsdadc SDADC handle.
+ * @retval HAL status.
+ */
+static HAL_StatusTypeDef SDADC_RegConvStart(SDADC_HandleTypeDef* hsdadc)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check regular trigger */
+ if(hsdadc->RegularTrigger == SDADC_SOFTWARE_TRIGGER)
+ {
+ /* Set RSWSTART bit in SDADC_CR2 register */
+ hsdadc->Instance->CR2 |= SDADC_CR2_RSWSTART;
+ }
+ else /* synchronuous trigger */
+ {
+ /* Enter init mode */
+ if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
+ {
+ /* Set SDADC in error state */
+ hsdadc->State = HAL_SDADC_STATE_ERROR;
+ status = HAL_TIMEOUT;
+ }
+ else
+ {
+ /* Set RSYNC bit in SDADC_CR1 register */
+ hsdadc->Instance->CR1 |= SDADC_CR1_RSYNC;
+
+ /* Exit init mode */
+ SDADC_ExitInitMode(hsdadc);
+ }
+ }
+ /* Update SDADC state only if status is OK */
+ if(status == HAL_OK)
+ {
+ hsdadc->State = (hsdadc->State == HAL_SDADC_STATE_READY) ? \
+ HAL_SDADC_STATE_REG : HAL_SDADC_STATE_REG_INJ;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to really stop regular conversion.
+ * @param hsdadc SDADC handle.
+ * @retval HAL status.
+ */
+static HAL_StatusTypeDef SDADC_RegConvStop(SDADC_HandleTypeDef* hsdadc)
+{
+ uint32_t tickstart;
+ __IO uint32_t dummy_read_for_register_reset;
+
+ /* Check continuous mode */
+ if(hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_ON)
+ {
+ /* Clear REOCF by reading SDADC_RDATAR register */
+ dummy_read_for_register_reset = hsdadc->Instance->RDATAR;
+ UNUSED(dummy_read_for_register_reset);
+
+ /* Clear RCONT bit in SDADC_CR2 register */
+ hsdadc->Instance->CR2 &= ~(SDADC_CR2_RCONT);
+ }
+ /* Wait for the end of regular conversion */
+ tickstart = HAL_GetTick();
+ while((hsdadc->Instance->ISR & SDADC_ISR_RCIP) != 0UL)
+ {
+ if((HAL_GetTick()-tickstart) > SDADC_TIMEOUT)
+ {
+ /* Set SDADC in error state and return timeout status */
+ hsdadc->State = HAL_SDADC_STATE_ERROR;
+ return HAL_TIMEOUT;
+ }
+ }
+ /* Check if trigger is synchronuous */
+ if(hsdadc->RegularTrigger == SDADC_SYNCHRONOUS_TRIGGER)
+ {
+ /* Enter init mode */
+ if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
+ {
+ /* Set SDADC in error state and return timeout status */
+ hsdadc->State = HAL_SDADC_STATE_ERROR;
+ return HAL_TIMEOUT;
+ }
+ else
+ {
+ /* Clear RSYNC bit in SDADC_CR1 register */
+ hsdadc->Instance->CR1 &= ~(SDADC_CR1_RSYNC);
+
+ /* Exit init mode */
+ SDADC_ExitInitMode(hsdadc);
+ }
+ }
+ /* Check if continuous mode */
+ if(hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_ON)
+ {
+ /* Restore RCONT bit in SDADC_CR2 register */
+ hsdadc->Instance->CR2 |= SDADC_CR2_RCONT;
+ }
+ /* Clear REOCF by reading SDADC_RDATAR register */
+ dummy_read_for_register_reset = hsdadc->Instance->RDATAR;
+ UNUSED(dummy_read_for_register_reset);
+
+ /* Set CLRROVRF bit in SDADC_CLRISR register */
+ hsdadc->Instance->CLRISR |= SDADC_ISR_CLRROVRF;
+
+ /* Update SDADC state */
+ hsdadc->State = (hsdadc->State == HAL_SDADC_STATE_REG) ? \
+ HAL_SDADC_STATE_READY : HAL_SDADC_STATE_INJ;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief This function allows to really start injected conversion.
+ * @param hsdadc SDADC handle.
+ * @retval HAL status.
+ */
+static HAL_StatusTypeDef SDADC_InjConvStart(SDADC_HandleTypeDef* hsdadc)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Initialize number of injected conversions remaining */
+ hsdadc->InjConvRemaining = hsdadc->InjectedChannelsNbr;
+
+ /* Check injected trigger */
+ if(hsdadc->InjectedTrigger == SDADC_SOFTWARE_TRIGGER)
+ {
+ /* Set JSWSTART bit in SDADC_CR2 register */
+ hsdadc->Instance->CR2 |= SDADC_CR2_JSWSTART;
+ }
+ else /* external or synchronuous trigger */
+ {
+ /* Enter init mode */
+ if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
+ {
+ /* Set SDADC in error state */
+ hsdadc->State = HAL_SDADC_STATE_ERROR;
+ status = HAL_TIMEOUT;
+ }
+ else
+ {
+ if(hsdadc->InjectedTrigger == SDADC_SYNCHRONOUS_TRIGGER)
+ {
+ /* Set JSYNC bit in SDADC_CR1 register */
+ hsdadc->Instance->CR1 |= SDADC_CR1_JSYNC;
+ }
+ else /* external trigger */
+ {
+ /* Set JEXTEN[1:0] bits in SDADC_CR2 register */
+ hsdadc->Instance->CR2 |= hsdadc->ExtTriggerEdge;
+ }
+ /* Exit init mode */
+ SDADC_ExitInitMode(hsdadc);
+ }
+ }
+ /* Update SDADC state only if status is OK */
+ if(status == HAL_OK)
+ {
+ hsdadc->State = (hsdadc->State == HAL_SDADC_STATE_READY) ? \
+ HAL_SDADC_STATE_INJ : HAL_SDADC_STATE_REG_INJ;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to really stop injected conversion.
+ * @param hsdadc SDADC handle.
+ * @retval HAL status.
+ */
+static HAL_StatusTypeDef SDADC_InjConvStop(SDADC_HandleTypeDef* hsdadc)
+{
+ uint32_t tickstart;
+ __IO uint32_t dummy_read_for_register_reset;
+
+ /* Check continuous mode */
+ if(hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_ON)
+ {
+ /* Clear JEOCF by reading SDADC_JDATAR register */
+ dummy_read_for_register_reset = hsdadc->Instance->JDATAR;
+ UNUSED(dummy_read_for_register_reset);
+
+ /* Clear JCONT bit in SDADC_CR2 register */
+ hsdadc->Instance->CR2 &= ~(SDADC_CR2_JCONT);
+ }
+ /* Wait for the end of injected conversion */
+ tickstart = HAL_GetTick();
+ while((hsdadc->Instance->ISR & SDADC_ISR_JCIP) != 0UL)
+ {
+ if((HAL_GetTick()-tickstart) > SDADC_TIMEOUT)
+ {
+ /* Set SDADC in error state and return timeout status */
+ hsdadc->State = HAL_SDADC_STATE_ERROR;
+ return HAL_TIMEOUT;
+ }
+ }
+ /* Check if trigger is not software */
+ if(hsdadc->InjectedTrigger != SDADC_SOFTWARE_TRIGGER)
+ {
+ /* Enter init mode */
+ if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
+ {
+ /* Set SDADC in error state and return timeout status */
+ hsdadc->State = HAL_SDADC_STATE_ERROR;
+ return HAL_TIMEOUT;
+ }
+ else
+ {
+ /* Check if trigger is synchronuous */
+ if(hsdadc->InjectedTrigger == SDADC_SYNCHRONOUS_TRIGGER)
+ {
+ /* Clear JSYNC bit in SDADC_CR1 register */
+ hsdadc->Instance->CR1 &= ~(SDADC_CR1_JSYNC);
+ }
+ else /* external trigger */
+ {
+ /* Clear JEXTEN[1:0] bits in SDADC_CR2 register */
+ hsdadc->Instance->CR2 &= ~(SDADC_CR2_JEXTEN);
+ }
+ /* Exit init mode */
+ SDADC_ExitInitMode(hsdadc);
+ }
+ }
+ /* Check if continuous mode */
+ if(hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_ON)
+ {
+ /* Restore JCONT bit in SDADC_CR2 register */
+ hsdadc->Instance->CR2 |= SDADC_CR2_JCONT;
+ }
+ /* Clear JEOCF by reading SDADC_JDATAR register */
+ dummy_read_for_register_reset = hsdadc->Instance->JDATAR;
+ UNUSED(dummy_read_for_register_reset);
+
+ /* Set CLRJOVRF bit in SDADC_CLRISR register */
+ hsdadc->Instance->CLRISR |= SDADC_ISR_CLRJOVRF;
+
+ /* Update SDADC state */
+ hsdadc->State = (hsdadc->State == HAL_SDADC_STATE_INJ) ? \
+ HAL_SDADC_STATE_READY : HAL_SDADC_STATE_REG;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(STM32F373xC) || defined(STM32F378xx) */
+#endif /* HAL_SDADC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_smartcard.c b/Src/stm32f3xx_hal_smartcard.c
new file mode 100644
index 0000000..c5ccfeb
--- /dev/null
+++ b/Src/stm32f3xx_hal_smartcard.c
@@ -0,0 +1,2294 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_smartcard.c
+ * @author MCD Application Team
+ * @brief SMARTCARD HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the SMARTCARD peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State and Error functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The SMARTCARD HAL driver can be used as follows:
+
+ (#) Declare a SMARTCARD_HandleTypeDef handle structure (eg. SMARTCARD_HandleTypeDef hsmartcard).
+ (#) Associate a USART to the SMARTCARD handle hsmartcard.
+ (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:
+ (++) Enable the USARTx interface clock.
+ (++) USART pins configuration:
+ (+++) Enable the clock for the USART GPIOs.
+ (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input).
+ (++) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()
+ and HAL_SMARTCARD_Receive_IT() APIs):
+ (+++) Configure the USARTx interrupt priority.
+ (+++) Enable the NVIC USART IRQ handle.
+ (++) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()
+ and HAL_SMARTCARD_Receive_DMA() APIs):
+ (+++) Declare a DMA handle structure for the Tx/Rx channel.
+ (+++) Enable the DMAx interface clock.
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+ (+++) Configure the DMA Tx/Rx channel.
+ (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
+
+ (#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly,
+ the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission
+ error enabling or disabling in the hsmartcard handle Init structure.
+
+ (#) If required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut, auto-retry counter,...)
+ in the hsmartcard handle AdvancedInit structure.
+
+ (#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API:
+ (++) This API configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)
+ by calling the customized HAL_SMARTCARD_MspInit() API.
+ [..]
+ (@) The specific SMARTCARD interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.
+
+ [..]
+ [..] Three operation modes are available within this driver :
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit()
+ (+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive()
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Send an amount of data in non-blocking mode using HAL_SMARTCARD_Transmit_IT()
+ (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
+ (+) Receive an amount of data in non-blocking mode using HAL_SMARTCARD_Receive_IT()
+ (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
+ (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Send an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA()
+ (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
+ (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA()
+ (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
+ (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()
+
+ *** SMARTCARD HAL driver macros list ***
+ ========================================
+ [..]
+ Below the list of most used macros in SMARTCARD HAL driver.
+
+ (+) __HAL_SMARTCARD_GET_FLAG : Check whether or not the specified SMARTCARD flag is set
+ (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag
+ (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt
+ (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt
+ (+) __HAL_SMARTCARD_GET_IT_SOURCE: Check whether or not the specified SMARTCARD interrupt is enabled
+
+ [..]
+ (@) You can refer to the SMARTCARD HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SMARTCARD SMARTCARD
+ * @brief SMARTCARD HAL module driver
+ * @{
+ */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
+ * @{
+ */
+#define SMARTCARD_TEACK_REACK_TIMEOUT 1000 /*!< SMARTCARD TX or RX enable acknowledge time-out value */
+
+#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
+ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */
+#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */
+#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN|USART_CR2_CLK_FIELDS|USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */
+#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT|USART_CR3_NACK|USART_CR3_SCARCNT)) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup SMARTCARD_Private_Functions
+ * @{
+ */
+static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard);
+static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard);
+static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
+static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions
+ * @{
+ */
+
+/** @defgroup SMARTCARD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and Configuration functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the USARTx
+ associated to the SmartCard.
+ [..]
+ The Smartcard interface is designed to support asynchronous protocol Smartcards as
+ defined in the ISO 7816-3 standard.
+ [..]
+ The USART can provide a clock to the smartcard through the SCLK output.
+ In smartcard mode, SCLK is not associated to the communication but is simply derived
+ from the internal peripheral input clock through a 5-bit prescaler.
+ [..]
+ (+) These parameters can be configured:
+ (++) Baud Rate
+ (++) Parity: should be enabled
+ (++) Receiver/transmitter modes
+ (++) Synchronous mode (and if enabled, phase, polarity and last bit parameters)
+ (++) Prescaler value
+ (++) Guard bit time
+ (++) NACK enabling or disabling on transmission error
+
+ (+) The following advanced features can be configured as well:
+ (++) TX and/or RX pin level inversion
+ (++) data logical level inversion
+ (++) RX and TX pins swap
+ (++) RX overrun detection disabling
+ (++) DMA disabling on RX error
+ (++) MSB first on communication line
+ (++) Time out enabling (and if activated, timeout value)
+ (++) Block length
+ (++) Auto-retry counter
+ [..]
+ The HAL_SMARTCARD_Init() API follows the USART synchronous configuration procedures
+ (details for the procedures are available in reference manual).
+
+@endverbatim
+ * @{
+ */
+
+/*
+ Additional Table:
+ Frame Length is fixed to 8 bits plus parity:
+ SMARTCARD frame format is given in the following table:
+ +---------------------------------------------------------------+
+ | M1M0 bits | PCE bit | SMARTCARD frame |
+ |-----------------------|---------------------------------------|
+ | 01 | 1 | | SB | 8 bit data | PB | STB | |
+ +---------------------------------------------------------------+
+
+*/
+
+/**
+ * @brief Initialize the SMARTCARD mode according to the specified
+ * parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Check the SMARTCARD handle allocation */
+ if(hsmartcard == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the USART associated to the SMARTCARD handle */
+ assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
+
+ if(hsmartcard->gState == HAL_SMARTCARD_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hsmartcard->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_SMARTCARD_MspInit(hsmartcard);
+ }
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+ /* Disable the Peripheral to set smartcard mode */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ /* In SmartCard mode, the following bits must be kept cleared:
+ - LINEN in the USART_CR2 register,
+ - HDSEL and IREN bits in the USART_CR3 register.*/
+ CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_LINEN);
+ CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN));
+
+ /* set the USART in SMARTCARD mode */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_SCEN);
+
+ /* Set the SMARTCARD Communication parameters */
+ if (SMARTCARD_SetConfig(hsmartcard) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ if (hsmartcard->AdvancedInit.AdvFeatureInit != SMARTCARD_ADVFEATURE_NO_INIT)
+ {
+ SMARTCARD_AdvFeatureConfig(hsmartcard);
+ }
+
+ /* Enable the Peripheral */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ /* TEACK and/or REACK to check before moving hsmartcard->gState and hsmartcard->RxState to Ready */
+ return (SMARTCARD_CheckIdleState(hsmartcard));
+}
+
+/**
+ * @brief DeInitialize the SMARTCARD peripheral.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Check the SMARTCARD handle allocation */
+ if(hsmartcard == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the USART/UART associated to the SMARTCARD handle */
+ assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ WRITE_REG(hsmartcard->Instance->CR1, 0x0U);
+ WRITE_REG(hsmartcard->Instance->CR2, 0x0U);
+ WRITE_REG(hsmartcard->Instance->CR3, 0x0U);
+ WRITE_REG(hsmartcard->Instance->RTOR, 0x0U);
+ WRITE_REG(hsmartcard->Instance->GTPR, 0x0U);
+
+ /* DeInit the low level hardware */
+ HAL_SMARTCARD_MspDeInit(hsmartcard);
+
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsmartcard->gState = HAL_SMARTCARD_STATE_RESET;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_RESET;
+
+ /* Process Unlock */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the SMARTCARD MSP.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+__weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmartcard);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the SMARTCARD MSP.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+__weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmartcard);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_MspDeInit can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions
+ * @brief SMARTCARD Transmit and Receive functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.
+
+ [..]
+ Smartcard is a single wire half duplex communication protocol.
+ The Smartcard interface is designed to support asynchronous protocol Smartcards as
+ defined in the ISO 7816-3 standard. The USART should be configured as:
+ (+) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
+ (+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
+
+ [..]
+ (#) There are two modes of transfer:
+ (++) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) Non-Blocking mode: The communication is performed using Interrupts
+ or DMA, the relevant API's return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ (++) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
+ will be executed respectively at the end of the Transmit or Receive process
+ The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication
+ error is detected.
+
+ (#) Blocking mode APIs are :
+ (++) HAL_SMARTCARD_Transmit()
+ (++) HAL_SMARTCARD_Receive()
+
+ (#) Non Blocking mode APIs with Interrupt are :
+ (++) HAL_SMARTCARD_Transmit_IT()
+ (++) HAL_SMARTCARD_Receive_IT()
+ (++) HAL_SMARTCARD_IRQHandler()
+
+ (#) Non Blocking mode functions with DMA are :
+ (++) HAL_SMARTCARD_Transmit_DMA()
+ (++) HAL_SMARTCARD_Receive_DMA()
+
+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+ (++) HAL_SMARTCARD_TxCpltCallback()
+ (++) HAL_SMARTCARD_RxCpltCallback()
+ (++) HAL_SMARTCARD_ErrorCallback()
+
+ (#) Non-Blocking mode transfers could be aborted using Abort API's :
+ (++) HAL_SMARTCARD_Abort()
+ (++) HAL_SMARTCARD_AbortTransmit()
+ (++) HAL_SMARTCARD_AbortReceive()
+ (++) HAL_SMARTCARD_Abort_IT()
+ (++) HAL_SMARTCARD_AbortTransmit_IT()
+ (++) HAL_SMARTCARD_AbortReceive_IT()
+
+ (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
+ (++) HAL_SMARTCARD_AbortCpltCallback()
+ (++) HAL_SMARTCARD_AbortTransmitCpltCallback()
+ (++) HAL_SMARTCARD_AbortReceiveCpltCallback()
+
+ (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
+ Errors are handled as follows :
+ (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+ to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
+ Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
+ and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
+ If user wants to abort it, Abort services should be called by user.
+ (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+ This concerns Frame Error in Interrupt mode tranmission, Overrun Error in Interrupt mode reception and all errors in DMA mode.
+ Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Send an amount of data in blocking mode.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param pData pointer to data buffer.
+ * @param Size amount of data to be sent.
+ * @param Timeout Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ /* Check that a Tx process is not already ongoing */
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
+
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
+
+ /* Disable the Peripheral first to update mode for TX master */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ /* Disable Rx, enable Tx */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+ SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST);
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
+
+ /* Enable the Peripheral */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsmartcard->TxXferSize = Size;
+ hsmartcard->TxXferCount = Size;
+
+ while(hsmartcard->TxXferCount > 0U)
+ {
+ hsmartcard->TxXferCount--;
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ hsmartcard->Instance->TDR = (*pData++ & (uint8_t)0xFFU);
+ }
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ /* Re-enable Rx at end of transmission if initial mode is Rx/Tx */
+ if(hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
+ {
+ /* Disable the Peripheral first to update modes */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+ /* Enable the Peripheral */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+ }
+
+ /* At end of Tx process, restore hsmartcard->gState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param pData pointer to data buffer.
+ * @param Size amount of data to be received.
+ * @param Timeout Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ /* Check that a Rx process is not already ongoing */
+ if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
+
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
+
+ hsmartcard->RxXferSize = Size;
+ hsmartcard->RxXferCount = Size;
+
+ /* Check the remain data to be received */
+ while(hsmartcard->RxXferCount > 0U)
+ {
+ hsmartcard->RxXferCount--;
+
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ *pData++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0x00FF);
+ }
+
+ /* At end of Rx process, restore hsmartcard->RxState to Ready */
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in interrupt mode.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param pData pointer to data buffer.
+ * @param Size amount of data to be sent.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
+{
+ /* Check that a Tx process is not already ongoing */
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
+
+ hsmartcard->pTxBuffPtr = pData;
+ hsmartcard->TxXferSize = Size;
+ hsmartcard->TxXferCount = Size;
+
+ /* Disable the Peripheral first to update mode for TX master */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ /* Disable Rx, enable Tx */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+ SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST);
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
+
+ /* Enable the Peripheral */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ /* Enable the SMARTCARD Error Interrupt: (Frame error) */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the SMARTCARD Transmit Data Register Empty Interrupt */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in interrupt mode.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param pData pointer to data buffer.
+ * @param Size amount of data to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
+{
+ /* Check that a Rx process is not already ongoing */
+ if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
+
+ hsmartcard->pRxBuffPtr = pData;
+ hsmartcard->RxXferSize = Size;
+ hsmartcard->RxXferCount = Size;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ /* Enable the SMARTCARD Parity Error and Data Register not empty Interrupts */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE);
+
+ /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in DMA mode.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param pData pointer to data buffer.
+ * @param Size amount of data to be sent.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
+{
+ /* Check that a Tx process is not already ongoing */
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
+
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsmartcard->pTxBuffPtr = pData;
+ hsmartcard->TxXferSize = Size;
+ hsmartcard->TxXferCount = Size;
+
+ /* Disable the Peripheral first to update mode for TX master */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ /* Disable Rx, enable Tx */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+ SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST);
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
+
+ /* Enable the Peripheral */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ /* Set the SMARTCARD DMA transfer complete callback */
+ hsmartcard->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;
+
+ /* Set the SMARTCARD error callback */
+ hsmartcard->hdmatx->XferErrorCallback = SMARTCARD_DMAError;
+
+ /* Set the DMA abort callback */
+ hsmartcard->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the SMARTCARD transmit DMA channel */
+ HAL_DMA_Start_IT(hsmartcard->hdmatx, (uint32_t)hsmartcard->pTxBuffPtr, (uint32_t)&hsmartcard->Instance->TDR, Size);
+
+ /* Clear the TC flag in the ICR register */
+ CLEAR_BIT(hsmartcard->Instance->ICR, USART_ICR_TCCF);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ /* Enable the UART Error Interrupt: (Frame error) */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the SMARTCARD associated USART CR3 register */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in DMA mode.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param pData pointer to data buffer.
+ * @param Size amount of data to be received.
+ * @note The SMARTCARD-associated USART parity is enabled (PCE = 1),
+ * the received data contain the parity bit (MSB position).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
+{
+ /* Check that a Rx process is not already ongoing */
+ if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
+
+ hsmartcard->pRxBuffPtr = pData;
+ hsmartcard->RxXferSize = Size;
+
+ /* Set the SMARTCARD DMA transfer complete callback */
+ hsmartcard->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt;
+
+ /* Set the SMARTCARD DMA error callback */
+ hsmartcard->hdmarx->XferErrorCallback = SMARTCARD_DMAError;
+
+ /* Set the DMA abort callback */
+ hsmartcard->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, (uint32_t)hsmartcard->pRxBuffPtr, Size);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ /* Enable the UART Parity Error Interrupt */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
+
+ /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the SMARTCARD associated USART CR3 register */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Abort ongoing transfers (blocking mode).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable SMARTCARD Interrupts (Tx and Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the SMARTCARD DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if(hsmartcard->hdmatx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hsmartcard->hdmatx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(hsmartcard->hdmatx);
+ }
+ }
+
+ /* Disable the SMARTCARD DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if(hsmartcard->hdmarx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hsmartcard->hdmarx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(hsmartcard->hdmarx);
+ }
+ }
+
+ /* Reset Tx and Rx transfer counters */
+ hsmartcard->TxXferCount = 0U;
+ hsmartcard->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+ /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* Reset Handle ErrorCode to No Error */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Transmit transfer (blocking mode).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable SMARTCARD Interrupts (Tx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable TXEIE and TCIE interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+ /* Check if a receive process is ongoing or not. If not disable ERR IT */
+ if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+ {
+ /* Disable the SMARTCARD Error Interrupt: (Frame error) */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+ }
+
+ /* Disable the SMARTCARD DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if(hsmartcard->hdmatx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hsmartcard->hdmatx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(hsmartcard->hdmatx);
+ }
+ }
+
+ /* Reset Tx transfer counter */
+ hsmartcard->TxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
+
+ /* Restore hsmartcard->gState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Receive transfer (blocking mode).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable SMARTCARD Interrupts (Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable RTOIE, EOBIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
+
+ /* Check if a Transmit process is ongoing or not. If not disable ERR IT */
+ if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ /* Disable the SMARTCARD Error Interrupt: (Frame error) */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+ }
+
+ /* Disable the SMARTCARD DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if(hsmartcard->hdmarx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hsmartcard->hdmarx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(hsmartcard->hdmarx);
+ }
+ }
+
+ /* Reset Rx transfer counter */
+ hsmartcard->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+ /* Restore hsmartcard->RxState to Ready */
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing transfers (Interrupt mode).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable SMARTCARD Interrupts (Tx and Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ uint32_t abortcplt = 1U;
+
+ /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, DMA Abort complete callbacks should be initialised
+ before any call to DMA Abort functions */
+ /* DMA Tx Handle is valid */
+ if(hsmartcard->hdmatx != NULL)
+ {
+ /* Set DMA Abort Complete callback if SMARTCARD DMA Tx request if enabled.
+ Otherwise, set it to NULL */
+ if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+ {
+ hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxAbortCallback;
+ }
+ else
+ {
+ hsmartcard->hdmatx->XferAbortCallback = NULL;
+ }
+ }
+ /* DMA Rx Handle is valid */
+ if(hsmartcard->hdmarx != NULL)
+ {
+ /* Set DMA Abort Complete callback if SMARTCARD DMA Rx request if enabled.
+ Otherwise, set it to NULL */
+ if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+ {
+ hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxAbortCallback;
+ }
+ else
+ {
+ hsmartcard->hdmarx->XferAbortCallback = NULL;
+ }
+ }
+
+ /* Disable the SMARTCARD DMA Tx request if enabled */
+ if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+ {
+ /* Disable DMA Tx at UART level */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
+ if(hsmartcard->hdmatx != NULL)
+ {
+ /* SMARTCARD Tx DMA Abort callback has already been initialised :
+ will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA TX */
+ if(HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
+ {
+ hsmartcard->hdmatx->XferAbortCallback = NULL;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+
+ /* Disable the SMARTCARD DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
+ if(hsmartcard->hdmarx != NULL)
+ {
+ /* SMARTCARD Rx DMA Abort callback has already been initialised :
+ will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA RX */
+ if(HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
+ {
+ hsmartcard->hdmarx->XferAbortCallback = NULL;
+ abortcplt = 1U;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+
+ /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+ if (abortcplt == 1U)
+ {
+ /* Reset Tx and Rx transfer counters */
+ hsmartcard->TxXferCount = 0U;
+ hsmartcard->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+ /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Transmit transfer (Interrupt mode).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable SMARTCARD Interrupts (Tx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable TXEIE and TCIE interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+ /* Check if a receive process is ongoing or not. If not disable ERR IT */
+ if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+ {
+ /* Disable the SMARTCARD Error Interrupt: (Frame error) */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+ }
+
+ /* Disable the SMARTCARD DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
+ if(hsmartcard->hdmatx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback :
+ will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+ hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxOnlyAbortCallback;
+
+ /* Abort DMA TX */
+ if(HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
+ {
+ /* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */
+ hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx);
+ }
+ }
+ else
+ {
+ /* Reset Tx transfer counter */
+ hsmartcard->TxXferCount = 0U;
+
+ /* Restore hsmartcard->gState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
+ }
+ }
+ else
+ {
+ /* Reset Tx transfer counter */
+ hsmartcard->TxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
+
+ /* Restore hsmartcard->gState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Receive transfer (Interrupt mode).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable SMARTCARD Interrupts (Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable RTOIE, EOBIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
+
+ /* Check if a Transmit process is ongoing or not. If not disable ERR IT */
+ if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ /* Disable the SMARTCARD Error Interrupt: (Frame error) */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+ }
+
+ /* Disable the SMARTCARD DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
+ if(hsmartcard->hdmarx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback :
+ will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+ hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxOnlyAbortCallback;
+
+ /* Abort DMA RX */
+ if(HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
+ {
+ /* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */
+ hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx);
+ }
+ }
+ else
+ {
+ /* Reset Rx transfer counter */
+ hsmartcard->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+ /* Restore hsmartcard->RxState to Ready */
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
+ }
+ }
+ else
+ {
+ /* Reset Rx transfer counter */
+ hsmartcard->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+ /* Restore hsmartcard->RxState to Ready */
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle SMARTCARD interrupt requests.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ uint32_t isrflags = READ_REG(hsmartcard->Instance->ISR);
+ uint32_t cr1its = READ_REG(hsmartcard->Instance->CR1);
+ uint32_t cr3its;
+ uint32_t errorflags;
+
+ /* If no error occurs */
+ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
+ if (errorflags == RESET)
+ {
+ /* SMARTCARD in mode Receiver ---------------------------------------------------*/
+ if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ {
+ SMARTCARD_Receive_IT(hsmartcard);
+ /* Clear RXNE interrupt flag done by reading RDR in SMARTCARD_Receive_IT() */
+ return;
+ }
+ }
+
+ /* If some errors occur */
+ cr3its = READ_REG(hsmartcard->Instance->CR3);
+ if( (errorflags != RESET)
+ && ( ((cr3its & USART_CR3_EIE) != RESET)
+ || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != RESET)) )
+ {
+ /* SMARTCARD parity error interrupt occurred -------------------------------------*/
+ if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
+ {
+ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_PEF);
+
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_PE;
+ }
+
+ /* SMARTCARD frame error interrupt occurred --------------------------------------*/
+ if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ {
+ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_FEF);
+
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_FE;
+ }
+
+ /* SMARTCARD noise error interrupt occurred --------------------------------------*/
+ if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ {
+ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_NEF);
+
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_NE;
+ }
+
+ /* SMARTCARD Over-Run interrupt occurred -----------------------------------------*/
+ if(((isrflags & USART_ISR_ORE) != RESET) &&
+ (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
+ {
+ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_OREF);
+
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;
+ }
+
+ /* SMARTCARD receiver timeout interrupt occurred -----------------------------------------*/
+ if(((isrflags & USART_ISR_RTOF) != RESET) && ((cr1its & USART_CR1_RTOIE) != RESET))
+ {
+ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_RTOF);
+
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_RTO;
+ }
+
+ /* Call SMARTCARD Error Call back function if need be --------------------------*/
+ if(hsmartcard->ErrorCode != HAL_SMARTCARD_ERROR_NONE)
+ {
+ /* SMARTCARD in mode Receiver ---------------------------------------------------*/
+ if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ {
+ SMARTCARD_Receive_IT(hsmartcard);
+ }
+
+ /* If Error is to be considered as blocking :
+ - Receiver Timeout error in Reception
+ - Overrun error in Reception
+ - any error occurs in DMA mode reception
+ */
+ if ( ((hsmartcard->ErrorCode & (HAL_SMARTCARD_ERROR_RTO | HAL_SMARTCARD_ERROR_ORE)) != RESET)
+ || (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)))
+ {
+ /* Blocking error : transfer is aborted
+ Set the SMARTCARD state ready to be able to start again the process,
+ Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+ SMARTCARD_EndRxTransfer(hsmartcard);
+
+ /* Disable the SMARTCARD DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the SMARTCARD DMA Rx channel */
+ if(hsmartcard->hdmarx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback :
+ will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
+ hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
+
+ /* Abort DMA RX */
+ if(HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
+ {
+ /* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */
+ hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+ HAL_SMARTCARD_ErrorCallback(hsmartcard);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+ HAL_SMARTCARD_ErrorCallback(hsmartcard);
+ }
+ }
+ /* other error type to be considered as blocking :
+ - Frame error in Transmission
+ */
+ else if ((hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) && ((hsmartcard->ErrorCode & HAL_SMARTCARD_ERROR_FE) != RESET))
+ {
+ /* Blocking error : transfer is aborted
+ Set the SMARTCARD state ready to be able to start again the process,
+ Disable Tx Interrupts, and disable Tx DMA request, if ongoing */
+ SMARTCARD_EndTxTransfer(hsmartcard);
+
+ /* Disable the SMARTCARD DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the SMARTCARD DMA Tx channel */
+ if(hsmartcard->hdmatx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback :
+ will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
+ hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
+
+ /* Abort DMA TX */
+ if(HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
+ {
+ /* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */
+ hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+ HAL_SMARTCARD_ErrorCallback(hsmartcard);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+ HAL_SMARTCARD_ErrorCallback(hsmartcard);
+ }
+ }
+ else
+ {
+ /* Non Blocking error : transfer could go on.
+ Error is notified to user through user error callback */
+ HAL_SMARTCARD_ErrorCallback(hsmartcard);
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ }
+ }
+ return;
+
+ } /* End if some error occurs */
+
+ /* SMARTCARD in mode Receiver, end of block interruption ------------------------*/
+ if(((isrflags & USART_ISR_EOBF) != RESET) && ((cr1its & USART_CR1_EOBIE) != RESET))
+ {
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+ __HAL_UNLOCK(hsmartcard);
+ HAL_SMARTCARD_RxCpltCallback(hsmartcard);
+ /* Clear EOBF interrupt after HAL_SMARTCARD_RxCpltCallback() call for the End of Block information
+ * to be available during HAL_SMARTCARD_RxCpltCallback() processing */
+ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_EOBF);
+ return;
+ }
+
+ /* SMARTCARD in mode Transmitter ------------------------------------------------*/
+ if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
+ {
+ SMARTCARD_Transmit_IT(hsmartcard);
+ return;
+ }
+
+ /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/
+ if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_TC) != RESET) &&(__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_TC) != RESET))
+ {
+ SMARTCARD_EndTransmit_IT(hsmartcard);
+ return;
+ }
+}
+
+/**
+ * @brief Tx Transfer completed callback.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+__weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmartcard);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_TxCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callback.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+__weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmartcard);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_RxCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief SMARTCARD error callback.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+__weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmartcard);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_ErrorCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief SMARTCARD Abort Complete callback.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+__weak void HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmartcard);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_AbortCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief SMARTCARD Abort Complete callback.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+__weak void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmartcard);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_AbortTransmitCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief SMARTCARD Abort Receive Complete callback.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+__weak void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmartcard);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_AbortReceiveCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief SMARTCARD State and Errors functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State and Errors functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to return the State of SmartCard
+ handle and also return Peripheral Errors occurred during communication process
+ (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state
+ of the SMARTCARD peripheral.
+ (+) HAL_SMARTCARD_GetError() checks in run-time errors that could occur during
+ communication.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the SMARTCARD handle state.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval SMARTCARD handle state
+ */
+HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Return SMARTCARD handle state */
+ uint32_t temp1= 0x00U, temp2 = 0x00U;
+ temp1 = hsmartcard->gState;
+ temp2 = hsmartcard->RxState;
+
+ return (HAL_SMARTCARD_StateTypeDef)(temp1 | temp2);
+}
+
+/**
+ * @brief Return the SMARTCARD handle error code.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval SMARTCARD handle Error Code
+*/
+uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ return hsmartcard->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions
+ * @{
+ */
+
+/**
+ * @brief Configure the SMARTCARD associated USART peripheral.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ uint32_t tmpreg = 0x00000000U;
+ SMARTCARD_ClockSourceTypeDef clocksource = SMARTCARD_CLOCKSOURCE_UNDEFINED;
+ HAL_StatusTypeDef ret = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
+ assert_param(IS_SMARTCARD_BAUDRATE(hsmartcard->Init.BaudRate));
+ assert_param(IS_SMARTCARD_WORD_LENGTH(hsmartcard->Init.WordLength));
+ assert_param(IS_SMARTCARD_STOPBITS(hsmartcard->Init.StopBits));
+ assert_param(IS_SMARTCARD_PARITY(hsmartcard->Init.Parity));
+ assert_param(IS_SMARTCARD_MODE(hsmartcard->Init.Mode));
+ assert_param(IS_SMARTCARD_POLARITY(hsmartcard->Init.CLKPolarity));
+ assert_param(IS_SMARTCARD_PHASE(hsmartcard->Init.CLKPhase));
+ assert_param(IS_SMARTCARD_LASTBIT(hsmartcard->Init.CLKLastBit));
+ assert_param(IS_SMARTCARD_ONE_BIT_SAMPLE(hsmartcard->Init.OneBitSampling));
+ assert_param(IS_SMARTCARD_NACK(hsmartcard->Init.NACKEnable));
+ assert_param(IS_SMARTCARD_TIMEOUT(hsmartcard->Init.TimeOutEnable));
+ assert_param(IS_SMARTCARD_AUTORETRY_COUNT(hsmartcard->Init.AutoRetryCount));
+
+ /*-------------------------- USART CR1 Configuration -----------------------*/
+ /* In SmartCard mode, M and PCE are forced to 1 (8 bits + parity).
+ * Oversampling is forced to 16 (OVER8 = 0).
+ * Configure the Parity and Mode:
+ * set PS bit according to hsmartcard->Init.Parity value
+ * set TE and RE bits according to hsmartcard->Init.Mode value */
+ tmpreg = (uint32_t) hsmartcard->Init.Parity | hsmartcard->Init.Mode;
+ tmpreg |= (uint32_t) hsmartcard->Init.WordLength;
+ MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg);
+
+ /*-------------------------- USART CR2 Configuration -----------------------*/
+ tmpreg = hsmartcard->Init.StopBits;
+ /* Synchronous mode is activated by default */
+ tmpreg |= (uint32_t) USART_CR2_CLKEN | hsmartcard->Init.CLKPolarity;
+ tmpreg |= (uint32_t) hsmartcard->Init.CLKPhase | hsmartcard->Init.CLKLastBit;
+ tmpreg |= (uint32_t) hsmartcard->Init.TimeOutEnable;
+ MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_FIELDS, tmpreg);
+
+ /*-------------------------- USART CR3 Configuration -----------------------*/
+ /* Configure
+ * - one-bit sampling method versus three samples' majority rule
+ * according to hsmartcard->Init.OneBitSampling
+ * - NACK transmission in case of parity error according
+ * to hsmartcard->Init.NACKEnable
+ * - autoretry counter according to hsmartcard->Init.AutoRetryCount */
+ tmpreg = (uint32_t) hsmartcard->Init.OneBitSampling | hsmartcard->Init.NACKEnable;
+ tmpreg |= ((uint32_t)hsmartcard->Init.AutoRetryCount << SMARTCARD_CR3_SCARCNT_LSB_POS);
+ MODIFY_REG(hsmartcard->Instance-> CR3,USART_CR3_FIELDS, tmpreg);
+
+ /*-------------------------- USART GTPR Configuration ----------------------*/
+ tmpreg = (hsmartcard->Init.Prescaler | ((uint32_t)hsmartcard->Init.GuardTime << SMARTCARD_GTPR_GT_LSB_POS));
+ MODIFY_REG(hsmartcard->Instance->GTPR, (USART_GTPR_GT|USART_GTPR_PSC), tmpreg);
+
+ /*-------------------------- USART RTOR Configuration ----------------------*/
+ tmpreg = ((uint32_t)hsmartcard->Init.BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS);
+ if (hsmartcard->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLE)
+ {
+ assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
+ tmpreg |= (uint32_t) hsmartcard->Init.TimeOutValue;
+ }
+ MODIFY_REG(hsmartcard->Instance->RTOR, (USART_RTOR_RTO|USART_RTOR_BLEN), tmpreg);
+
+ /*-------------------------- USART BRR Configuration -----------------------*/
+ SMARTCARD_GETCLOCKSOURCE(hsmartcard, clocksource);
+ switch (clocksource)
+ {
+ case SMARTCARD_CLOCKSOURCE_PCLK1:
+ hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hsmartcard->Init.BaudRate/2U)) / hsmartcard->Init.BaudRate);
+ break;
+ case SMARTCARD_CLOCKSOURCE_PCLK2:
+ hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hsmartcard->Init.BaudRate/2U)) / hsmartcard->Init.BaudRate);
+ break;
+ case SMARTCARD_CLOCKSOURCE_HSI:
+ hsmartcard->Instance->BRR = (uint16_t)((HSI_VALUE + (hsmartcard->Init.BaudRate/2U)) / hsmartcard->Init.BaudRate);
+ break;
+ case SMARTCARD_CLOCKSOURCE_SYSCLK:
+ hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hsmartcard->Init.BaudRate/2U)) / hsmartcard->Init.BaudRate);
+ break;
+ case SMARTCARD_CLOCKSOURCE_LSE:
+ hsmartcard->Instance->BRR = (uint16_t)((LSE_VALUE + (hsmartcard->Init.BaudRate/2U)) / hsmartcard->Init.BaudRate);
+ break;
+ case SMARTCARD_CLOCKSOURCE_UNDEFINED:
+ default:
+ ret = HAL_ERROR;
+ break;
+ }
+
+ return ret;
+}
+
+
+/**
+ * @brief Configure the SMARTCARD associated USART peripheral advanced features.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Check whether the set of advanced features to configure is properly set */
+ assert_param(IS_SMARTCARD_ADVFEATURE_INIT(hsmartcard->AdvancedInit.AdvFeatureInit));
+
+ /* if required, configure TX pin active level inversion */
+ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXINVERT_INIT))
+ {
+ assert_param(IS_SMARTCARD_ADVFEATURE_TXINV(hsmartcard->AdvancedInit.TxPinLevelInvert));
+ MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_TXINV, hsmartcard->AdvancedInit.TxPinLevelInvert);
+ }
+
+ /* if required, configure RX pin active level inversion */
+ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXINVERT_INIT))
+ {
+ assert_param(IS_SMARTCARD_ADVFEATURE_RXINV(hsmartcard->AdvancedInit.RxPinLevelInvert));
+ MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_RXINV, hsmartcard->AdvancedInit.RxPinLevelInvert);
+ }
+
+ /* if required, configure data inversion */
+ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DATAINVERT_INIT))
+ {
+ assert_param(IS_SMARTCARD_ADVFEATURE_DATAINV(hsmartcard->AdvancedInit.DataInvert));
+ MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_DATAINV, hsmartcard->AdvancedInit.DataInvert);
+ }
+
+ /* if required, configure RX/TX pins swap */
+ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_SWAP_INIT))
+ {
+ assert_param(IS_SMARTCARD_ADVFEATURE_SWAP(hsmartcard->AdvancedInit.Swap));
+ MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_SWAP, hsmartcard->AdvancedInit.Swap);
+ }
+
+ /* if required, configure RX overrun detection disabling */
+ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT))
+ {
+ assert_param(IS_SMARTCARD_OVERRUN(hsmartcard->AdvancedInit.OverrunDisable));
+ MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_OVRDIS, hsmartcard->AdvancedInit.OverrunDisable);
+ }
+
+ /* if required, configure DMA disabling on reception error */
+ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT))
+ {
+ assert_param(IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(hsmartcard->AdvancedInit.DMADisableonRxError));
+ MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_DDRE, hsmartcard->AdvancedInit.DMADisableonRxError);
+ }
+
+ /* if required, configure MSB first on communication line */
+ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
+ {
+ assert_param(IS_SMARTCARD_ADVFEATURE_MSBFIRST(hsmartcard->AdvancedInit.MSBFirst));
+ MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_MSBFIRST, hsmartcard->AdvancedInit.MSBFirst);
+ }
+
+}
+
+/**
+ * @brief Check the SMARTCARD Idle State.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ uint32_t tickstart = 0U;
+
+ /* Initialize the SMARTCARD ErrorCode */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
+
+ /* Check if the Transmitter is enabled */
+ if((hsmartcard->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+ {
+ /* Wait until TEACK flag is set */
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, tickstart, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ /* Timeout occurred */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Check if the Receiver is enabled */
+ if((hsmartcard->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+ {
+ /* Wait until REACK flag is set */
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_REACK, RESET, tickstart, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ /* Timeout occurred */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Initialize the SMARTCARD states */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle SMARTCARD Communication Timeout.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param Flag Specifies the SMARTCARD flag to check.
+ * @param Status The new Flag status (SET or RESET).
+ * @param Tickstart Tick start value
+ * @param Timeout Timeout duration.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
+{
+ /* Wait until flag is set */
+ while((__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) ? SET : RESET) == Status)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+
+/**
+ * @brief End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable TXEIE, TCIE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ /* At end of Tx process, restore hsmartcard->gState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+}
+
+
+/**
+ * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ /* At end of Rx process, restore hsmartcard->RxState to Ready */
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+}
+
+
+/**
+ * @brief DMA SMARTCARD transmit process complete callback.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
+ hsmartcard->TxXferCount = 0U;
+
+ /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+ in the SMARTCARD associated USART CR3 register */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+ /* Enable the SMARTCARD Transmit Complete Interrupt */
+ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_TC);
+}
+
+/**
+ * @brief DMA SMARTCARD receive process complete callback.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
+ hsmartcard->RxXferCount = 0U;
+
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+ in the SMARTCARD associated USART CR3 register */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+ /* At end of Rx process, restore hsmartcard->RxState to Ready */
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ HAL_SMARTCARD_RxCpltCallback(hsmartcard);
+}
+
+/**
+ * @brief DMA SMARTCARD communication error callback.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
+
+ /* Stop SMARTCARD DMA Tx request if ongoing */
+ if ( (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
+ &&(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) )
+ {
+ hsmartcard->TxXferCount = 0U;
+ SMARTCARD_EndTxTransfer(hsmartcard);
+ }
+
+ /* Stop SMARTCARD DMA Rx request if ongoing */
+ if ( (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
+ &&(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) )
+ {
+ hsmartcard->RxXferCount = 0U;
+ SMARTCARD_EndRxTransfer(hsmartcard);
+ }
+
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_DMA;
+ HAL_SMARTCARD_ErrorCallback(hsmartcard);
+}
+
+/**
+ * @brief DMA SMARTCARD communication abort callback, when initiated by HAL services on Error
+ * (To be called at end of DMA Abort procedure following error occurrence).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
+ hsmartcard->RxXferCount = 0U;
+ hsmartcard->TxXferCount = 0U;
+
+ HAL_SMARTCARD_ErrorCallback(hsmartcard);
+}
+
+/**
+ * @brief DMA SMARTCARD Tx communication abort callback, when initiated by user
+ * (To be called at end of DMA Tx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Rx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef* )(hdma->Parent);
+
+ hsmartcard->hdmatx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if(hsmartcard->hdmarx != NULL)
+ {
+ if(hsmartcard->hdmarx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ hsmartcard->TxXferCount = 0U;
+ hsmartcard->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+ /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
+}
+
+
+/**
+ * @brief DMA SMARTCARD Rx communication abort callback, when initiated by user
+ * (To be called at end of DMA Rx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Tx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef* )(hdma->Parent);
+
+ hsmartcard->hdmarx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if(hsmartcard->hdmatx != NULL)
+ {
+ if(hsmartcard->hdmatx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ hsmartcard->TxXferCount = 0U;
+ hsmartcard->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+ /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
+}
+
+
+/**
+ * @brief DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to
+ * HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer)
+ * (This callback is executed at end of DMA Tx Abort procedure following user abort request,
+ * and leads to user Tx Abort Complete callback execution).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
+
+ hsmartcard->TxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
+
+ /* Restore hsmartcard->gState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
+}
+
+/**
+ * @brief DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to
+ * HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer)
+ * (This callback is executed at end of DMA Rx Abort procedure following user abort request,
+ * and leads to user Rx Abort Complete callback execution).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef* hsmartcard = ( SMARTCARD_HandleTypeDef* )(hdma->Parent);
+
+ hsmartcard->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+ /* Restore hsmartcard->RxState to Ready */
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
+}
+
+/**
+ * @brief Send an amount of data in non-blocking mode.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * Function called under interruption only, once
+ * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT()
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Check that a Tx process is ongoing */
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
+ {
+ if(hsmartcard->TxXferCount == 0U)
+ {
+ /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE);
+
+ /* Enable the SMARTCARD Transmit Complete Interrupt */
+ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_TC);
+
+ return HAL_OK;
+ }
+ else
+ {
+ hsmartcard->Instance->TDR = (*hsmartcard->pTxBuffPtr++ & (uint8_t)0xFFU);
+ hsmartcard->TxXferCount--;
+
+ return HAL_OK;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Wrap up transmission in non-blocking mode.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable the SMARTCARD Transmit Complete Interrupt */
+ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TC);
+
+ /* Check if a receive process is ongoing or not. If not disable ERR IT */
+ if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+ {
+ /* Disable the SMARTCARD Error Interrupt: (Frame error) */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+ }
+
+ /* Re-enable Rx at end of transmission if initial mode is Rx/Tx */
+ if(hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
+ {
+ /* Disable the Peripheral first to update modes */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+ /* Enable the Peripheral */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+ }
+
+ /* Tx process is ended, restore hsmartcard->gState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ HAL_SMARTCARD_TxCpltCallback(hsmartcard);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * Function called under interruption only, once
+ * interruptions have been enabled by HAL_SMARTCARD_Receive_IT().
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Check that a Rx process is ongoing */
+ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
+ {
+ *hsmartcard->pRxBuffPtr++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF);
+
+ if(--hsmartcard->RxXferCount == 0U)
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE);
+
+ /* Check if a transmit process is ongoing or not. If not disable ERR IT */
+ if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+ }
+
+ /* Disable the SMARTCARD Parity Error Interrupt */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
+
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ HAL_SMARTCARD_RxCpltCallback(hsmartcard);
+
+ return HAL_OK;
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Clear RXNE interrupt flag */
+ __HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST);
+
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_smartcard_ex.c b/Src/stm32f3xx_hal_smartcard_ex.c
new file mode 100644
index 0000000..6663419
--- /dev/null
+++ b/Src/stm32f3xx_hal_smartcard_ex.c
@@ -0,0 +1,206 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_smartcard_ex.c
+ * @author MCD Application Team
+ * @brief SMARTCARD HAL module driver.
+ * This file provides extended firmware functions to manage the following
+ * functionalities of the SmartCard.
+ * + Initialization and de-initialization functions
+ * + Peripheral Control functions
+ *
+ *
+ @verbatim
+ =============================================================================
+ ##### SMARTCARD peripheral extended features #####
+ =============================================================================
+ [..]
+ The Extended SMARTCARD HAL driver can be used as follows:
+
+ (#) After having configured the SMARTCARD basic features with HAL_SMARTCARD_Init(),
+ then program SMARTCARD advanced features if required (TX/RX pins swap, TimeOut,
+ auto-retry counter,...) in the hsmartcard AdvancedInit structure.
+
+
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SMARTCARDEx SMARTCARDEx
+ * @brief SMARTCARD Extension HAL module driver
+ * @{
+ */
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SMARTCARDEx_Exported_Functions SMARTCARD Extended Exported Functions
+ * @{
+ */
+
+/** @defgroup SMARTCARDEx_Exported_Functions_Group1 Extended Peripheral Control functions
+ * @brief Extended control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the SMARTCARD.
+ (+) HAL_SMARTCARDEx_BlockLength_Config() API allows to configure the Block Length on the fly
+ (+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly
+ (+) HAL_SMARTCARDEx_EnableReceiverTimeOut() API enables the receiver timeout feature
+ (+) HAL_SMARTCARDEx_DisableReceiverTimeOut() API disables the receiver timeout feature
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Update on the fly the SMARTCARD block length in RTOR register.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param BlockLength SMARTCARD block length (8-bit long at most)
+ * @retval None
+ */
+void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength)
+{
+ MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_BLEN, ((uint32_t)BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS));
+}
+
+/**
+ * @brief Update on the fly the receiver timeout value in RTOR register.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param TimeOutValue receiver timeout value in number of baud blocks. The timeout
+ * value must be less or equal to 0x0FFFFFFFF.
+ * @retval None
+ */
+void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue)
+{
+ assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
+ MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_RTO, TimeOutValue);
+}
+
+/**
+ * @brief Enable the SMARTCARD receiver timeout feature.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+
+ if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+ /* Set the USART RTOEN bit */
+ SET_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Disable the SMARTCARD receiver timeout feature.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+
+ if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+ /* Clear the USART RTOEN bit */
+ CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_smbus.c b/Src/stm32f3xx_hal_smbus.c
new file mode 100644
index 0000000..1803183
--- /dev/null
+++ b/Src/stm32f3xx_hal_smbus.c
@@ -0,0 +1,2161 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_smbus.c
+ * @author MCD Application Team
+ * @brief SMBUS HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the System Management Bus (SMBus) peripheral,
+ * based on I2C principles of operation :
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral State and Errors functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The SMBUS HAL driver can be used as follows:
+
+ (#) Declare a SMBUS_HandleTypeDef handle structure, for example:
+ SMBUS_HandleTypeDef hsmbus;
+
+ (#)Initialize the SMBUS low level resources by implementing the HAL_SMBUS_MspInit() API:
+ (##) Enable the SMBUSx interface clock
+ (##) SMBUS pins configuration
+ (+++) Enable the clock for the SMBUS GPIOs
+ (+++) Configure SMBUS pins as alternate function open-drain
+ (##) NVIC configuration if you need to use interrupt process
+ (+++) Configure the SMBUSx interrupt priority
+ (+++) Enable the NVIC SMBUS IRQ Channel
+
+ (#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Addressing mode,
+ Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode,
+ Peripheral mode and Packet Error Check mode in the hsmbus Init structure.
+
+ (#) Initialize the SMBUS registers by calling the HAL_SMBUS_Init() API:
+ (++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ by calling the customized HAL_SMBUS_MspInit(&hsmbus) API.
+
+ (#) To check if target device is ready for communication, use the function HAL_SMBUS_IsDeviceReady()
+
+ (#) For SMBUS IO operations, only one mode of operations is available within this driver
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Master_Transmit_IT()
+ (++) At transmission end of transfer HAL_SMBUS_MasterTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SMBUS_MasterTxCpltCallback()
+ (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Master_Receive_IT()
+ (++) At reception end of transfer HAL_SMBUS_MasterRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SMBUS_MasterRxCpltCallback()
+ (+) Abort a master/host SMBUS process communication with Interrupt using HAL_SMBUS_Master_Abort_IT()
+ (++) The associated previous transfer callback is called at the end of abort process
+ (++) mean HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit
+ (++) mean HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive
+ (+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode
+ using HAL_SMBUS_EnableListen_IT() HAL_SMBUS_DisableListen_IT()
+ (++) When address slave/device SMBUS match, HAL_SMBUS_AddrCallback() is executed and user can
+ add his own code to check the Address Match Code and the transmission direction request by master/host (Write/Read).
+ (++) At Listen mode end HAL_SMBUS_ListenCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SMBUS_ListenCpltCallback()
+ (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Slave_Transmit_IT()
+ (++) At transmission end of transfer HAL_SMBUS_SlaveTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SMBUS_SlaveTxCpltCallback()
+ (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Slave_Receive_IT()
+ (++) At reception end of transfer HAL_SMBUS_SlaveRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SMBUS_SlaveRxCpltCallback()
+ (+) Enable/Disable the SMBUS alert mode using HAL_SMBUS_EnableAlert_IT() HAL_SMBUS_DisableAlert_IT()
+ (++) When SMBUS Alert is generated HAL_SMBUS_ErrorCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SMBUS_ErrorCallback()
+ to check the Alert Error Code using function HAL_SMBUS_GetError()
+ (+) Get HAL state machine or error values using HAL_SMBUS_GetState() or HAL_SMBUS_GetError()
+ (+) In case of transfer Error, HAL_SMBUS_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_SMBUS_ErrorCallback()
+ to check the Error Code using function HAL_SMBUS_GetError()
+
+ *** SMBUS HAL driver macros list ***
+ ==================================
+ [..]
+ Below the list of most used macros in SMBUS HAL driver.
+
+ (+) __HAL_SMBUS_ENABLE: Enable the SMBUS peripheral
+ (+) __HAL_SMBUS_DISABLE: Disable the SMBUS peripheral
+ (+) __HAL_SMBUS_GET_FLAG: Check whether the specified SMBUS flag is set or not
+ (+) __HAL_SMBUS_CLEAR_FLAG: Clear the specified SMBUS pending flag
+ (+) __HAL_SMBUS_ENABLE_IT: Enable the specified SMBUS interrupt
+ (+) __HAL_SMBUS_DISABLE_IT: Disable the specified SMBUS interrupt
+
+ [..]
+ (@) You can refer to the SMBUS HAL driver header file for more useful macros
+
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SMBUS SMBUS
+ * @brief SMBUS HAL module driver
+ * @{
+ */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SMBUS_Private_Define SMBUS Private Constants
+ * @{
+ */
+#define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< SMBUS TIMING clear register Mask */
+#define HAL_TIMEOUT_ADDR (10000U) /*!< 10 s */
+#define HAL_TIMEOUT_BUSY (25U) /*!< 25 ms */
+#define HAL_TIMEOUT_DIR (25U) /*!< 25 ms */
+#define HAL_TIMEOUT_RXNE (25U) /*!< 25 ms */
+#define HAL_TIMEOUT_STOPF (25U) /*!< 25 ms */
+#define HAL_TIMEOUT_TC (25U) /*!< 25 ms */
+#define HAL_TIMEOUT_TCR (25U) /*!< 25 ms */
+#define HAL_TIMEOUT_TXIS (25U) /*!< 25 ms */
+#define MAX_NBYTE_SIZE 255U
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
+ * @{
+ */
+static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+
+static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest);
+static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest);
+static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus);
+static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus);
+
+static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus);
+
+static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus);
+
+static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup SMBUS_Exported_Functions SMBUS Exported Functions
+ * @{
+ */
+
+/** @defgroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to initialize and
+ deinitialize the SMBUSx peripheral:
+
+ (+) User must Implement HAL_SMBUS_MspInit() function in which he configures
+ all related peripherals resources (CLOCK, GPIO, IT and NVIC ).
+
+ (+) Call the function HAL_SMBUS_Init() to configure the selected device with
+ the selected configuration:
+ (++) Clock Timing
+ (++) Bus Timeout
+ (++) Analog Filer mode
+ (++) Own Address 1
+ (++) Addressing mode (Master, Slave)
+ (++) Dual Addressing mode
+ (++) Own Address 2
+ (++) Own Address 2 Mask
+ (++) General call mode
+ (++) Nostretch mode
+ (++) Packet Error Check mode
+ (++) Peripheral mode
+
+
+ (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration
+ of the selected SMBUSx peripheral.
+
+ (+) Enable/Disable Analog/Digital filters with HAL_SMBUS_ConfigAnalogFilter() and
+ HAL_SMBUS_ConfigDigitalFilter().
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the SMBUS according to the specified parameters
+ * in the SMBUS_InitTypeDef and initialize the associated handle.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Check the SMBUS handle allocation */
+ if (hsmbus == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
+ assert_param(IS_SMBUS_ANALOG_FILTER(hsmbus->Init.AnalogFilter));
+ assert_param(IS_SMBUS_OWN_ADDRESS1(hsmbus->Init.OwnAddress1));
+ assert_param(IS_SMBUS_ADDRESSING_MODE(hsmbus->Init.AddressingMode));
+ assert_param(IS_SMBUS_DUAL_ADDRESS(hsmbus->Init.DualAddressMode));
+ assert_param(IS_SMBUS_OWN_ADDRESS2(hsmbus->Init.OwnAddress2));
+ assert_param(IS_SMBUS_OWN_ADDRESS2_MASK(hsmbus->Init.OwnAddress2Masks));
+ assert_param(IS_SMBUS_GENERAL_CALL(hsmbus->Init.GeneralCallMode));
+ assert_param(IS_SMBUS_NO_STRETCH(hsmbus->Init.NoStretchMode));
+ assert_param(IS_SMBUS_PEC(hsmbus->Init.PacketErrorCheckMode));
+ assert_param(IS_SMBUS_PERIPHERAL_MODE(hsmbus->Init.PeripheralMode));
+
+ if (hsmbus->State == HAL_SMBUS_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hsmbus->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ HAL_SMBUS_MspInit(hsmbus);
+ }
+
+ hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+ /* Disable the selected SMBUS peripheral */
+ __HAL_SMBUS_DISABLE(hsmbus);
+
+ /*---------------------------- SMBUSx TIMINGR Configuration ------------------------*/
+ /* Configure SMBUSx: Frequency range */
+ hsmbus->Instance->TIMINGR = hsmbus->Init.Timing & TIMING_CLEAR_MASK;
+
+ /*---------------------------- SMBUSx TIMEOUTR Configuration ------------------------*/
+ /* Configure SMBUSx: Bus Timeout */
+ hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TIMOUTEN;
+ hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TEXTEN;
+ hsmbus->Instance->TIMEOUTR = hsmbus->Init.SMBusTimeout;
+
+ /*---------------------------- SMBUSx OAR1 Configuration -----------------------*/
+ /* Configure SMBUSx: Own Address1 and ack own address1 mode */
+ hsmbus->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
+
+ if (hsmbus->Init.OwnAddress1 != 0U)
+ {
+ if (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT)
+ {
+ hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | hsmbus->Init.OwnAddress1);
+ }
+ else /* SMBUS_ADDRESSINGMODE_10BIT */
+ {
+ hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hsmbus->Init.OwnAddress1);
+ }
+ }
+
+ /*---------------------------- SMBUSx CR2 Configuration ------------------------*/
+ /* Configure SMBUSx: Addressing Master mode */
+ if (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_10BIT)
+ {
+ hsmbus->Instance->CR2 = (I2C_CR2_ADD10);
+ }
+ /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process) */
+ /* AUTOEND and NACK bit will be manage during Transfer process */
+ hsmbus->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
+
+ /*---------------------------- SMBUSx OAR2 Configuration -----------------------*/
+ /* Configure SMBUSx: Dual mode and Own Address2 */
+ hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | (hsmbus->Init.OwnAddress2Masks << 8U));
+
+ /*---------------------------- SMBUSx CR1 Configuration ------------------------*/
+ /* Configure SMBUSx: Generalcall and NoStretch mode */
+ hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | hsmbus->Init.AnalogFilter);
+
+ /* Enable Slave Byte Control only in case of Packet Error Check is enabled and SMBUS Peripheral is set in Slave mode */
+ if ((hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE)
+ && ((hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)))
+ {
+ hsmbus->Instance->CR1 |= I2C_CR1_SBC;
+ }
+
+ /* Enable the selected SMBUS peripheral */
+ __HAL_SMBUS_ENABLE(hsmbus);
+
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+ hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitialize the SMBUS peripheral.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Check the SMBUS handle allocation */
+ if (hsmbus == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
+
+ hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+ /* Disable the SMBUS Peripheral Clock */
+ __HAL_SMBUS_DISABLE(hsmbus);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_SMBUS_MspDeInit(hsmbus);
+
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+ hsmbus->PreviousState = HAL_SMBUS_STATE_RESET;
+ hsmbus->State = HAL_SMBUS_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the SMBUS MSP.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+__weak void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmbus);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the SMBUS MSP.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+__weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmbus);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Configure Analog noise filter.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param AnalogFilter This parameter can be one of the following values:
+ * @arg @ref SMBUS_ANALOGFILTER_ENABLE
+ * @arg @ref SMBUS_ANALOGFILTER_DISABLE
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter)
+{
+ /* Check the parameters */
+ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
+ assert_param(IS_SMBUS_ANALOG_FILTER(AnalogFilter));
+
+ if (hsmbus->State == HAL_SMBUS_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+ /* Disable the selected SMBUS peripheral */
+ __HAL_SMBUS_DISABLE(hsmbus);
+
+ /* Reset ANOFF bit */
+ hsmbus->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
+
+ /* Set analog filter bit*/
+ hsmbus->Instance->CR1 |= AnalogFilter;
+
+ __HAL_SMBUS_ENABLE(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Configure Digital noise filter.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter)
+{
+ uint32_t tmpreg = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
+ assert_param(IS_SMBUS_DIGITAL_FILTER(DigitalFilter));
+
+ if (hsmbus->State == HAL_SMBUS_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+ /* Disable the selected SMBUS peripheral */
+ __HAL_SMBUS_DISABLE(hsmbus);
+
+ /* Get the old register value */
+ tmpreg = hsmbus->Instance->CR1;
+
+ /* Reset I2C DNF bits [11:8] */
+ tmpreg &= ~(I2C_CR1_DNF);
+
+ /* Set I2Cx DNF coefficient */
+ tmpreg |= DigitalFilter << I2C_CR1_DNF_Pos;
+
+ /* Store the new register value */
+ hsmbus->Instance->CR1 = tmpreg;
+
+ __HAL_SMBUS_ENABLE(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the SMBUS data
+ transfers.
+
+ (#) Blocking mode function to check if device is ready for usage is :
+ (++) HAL_SMBUS_IsDeviceReady()
+
+ (#) There is only one mode of transfer:
+ (++) Non-Blocking mode : The communication is performed using Interrupts.
+ These functions return the status of the transfer startup.
+ The end of the data processing will be indicated through the
+ dedicated SMBUS IRQ when using Interrupt mode.
+
+ (#) Non-Blocking mode functions with Interrupt are :
+ (++) HAL_SMBUS_Master_Transmit_IT()
+ (++) HAL_SMBUS_Master_Receive_IT()
+ (++) HAL_SMBUS_Slave_Transmit_IT()
+ (++) HAL_SMBUS_Slave_Receive_IT()
+ (++) HAL_SMBUS_EnableListen_IT() or alias HAL_SMBUS_EnableListen_IT()
+ (++) HAL_SMBUS_DisableListen_IT()
+ (++) HAL_SMBUS_EnableAlert_IT()
+ (++) HAL_SMBUS_DisableAlert_IT()
+
+ (#) A set of Transfer Complete Callbacks are provided in non-Blocking mode:
+ (++) HAL_SMBUS_MasterTxCpltCallback()
+ (++) HAL_SMBUS_MasterRxCpltCallback()
+ (++) HAL_SMBUS_SlaveTxCpltCallback()
+ (++) HAL_SMBUS_SlaveRxCpltCallback()
+ (++) HAL_SMBUS_AddrCallback()
+ (++) HAL_SMBUS_ListenCpltCallback()
+ (++) HAL_SMBUS_ErrorCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ /* Check the parameters */
+ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if (hsmbus->State == HAL_SMBUS_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+ /* Prepare transfer parameters */
+ hsmbus->pBuffPtr = pData;
+ hsmbus->XferCount = Size;
+ hsmbus->XferOptions = XferOptions;
+
+ /* In case of Quick command, remove autoend mode */
+ /* Manage the stop generation by software */
+ if (hsmbus->pBuffPtr == NULL)
+ {
+ hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
+ }
+
+ if (Size > MAX_NBYTE_SIZE)
+ {
+ hsmbus->XferSize = MAX_NBYTE_SIZE;
+ }
+ else
+ {
+ hsmbus->XferSize = Size;
+ }
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
+ if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount))
+ {
+ SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE);
+ }
+ else
+ {
+ /* If transfer direction not change, do not generate Restart Condition */
+ /* Mean Previous state is same as current state */
+ if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0))
+ {
+ SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ }
+ /* Else transfer direction change, so generate Restart with new transfer direction */
+ else
+ {
+ /* Convert OTHER_xxx XferOptions if any */
+ SMBUS_ConvertOtherXferOptions(hsmbus);
+
+ /* Handle Transfer */
+ SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE);
+ }
+
+ /* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */
+ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
+ if (SMBUS_GET_PEC_MODE(hsmbus) != RESET)
+ {
+ hsmbus->XferSize--;
+ hsmbus->XferCount--;
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Note : The SMBUS interrupts must be enabled after unlocking current process
+ to avoid the risk of SMBUS interrupt handle execution before current
+ process unlock */
+ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ /* Check the parameters */
+ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if (hsmbus->State == HAL_SMBUS_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hsmbus->pBuffPtr = pData;
+ hsmbus->XferCount = Size;
+ hsmbus->XferOptions = XferOptions;
+
+ /* In case of Quick command, remove autoend mode */
+ /* Manage the stop generation by software */
+ if (hsmbus->pBuffPtr == NULL)
+ {
+ hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
+ }
+
+ if (Size > MAX_NBYTE_SIZE)
+ {
+ hsmbus->XferSize = MAX_NBYTE_SIZE;
+ }
+ else
+ {
+ hsmbus->XferSize = Size;
+ }
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
+ if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount))
+ {
+ SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ);
+ }
+ else
+ {
+ /* If transfer direction not change, do not generate Restart Condition */
+ /* Mean Previous state is same as current state */
+ if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0))
+ {
+ SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ }
+ /* Else transfer direction change, so generate Restart with new transfer direction */
+ else
+ {
+ /* Convert OTHER_xxx XferOptions if any */
+ SMBUS_ConvertOtherXferOptions(hsmbus);
+
+ /* Handle Transfer */
+ SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ);
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Note : The SMBUS interrupts must be enabled after unlocking current process
+ to avoid the risk of SMBUS interrupt handle execution before current
+ process unlock */
+ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Abort a master/host SMBUS process communication with Interrupt.
+ * @note This abort can be called only if state is ready
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
+{
+ if (hsmbus->State == HAL_SMBUS_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ /* Keep the same state as previous */
+ /* to perform as well the call of the corresponding end of transfer callback */
+ if (hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+ {
+ hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
+ }
+ else if (hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+ {
+ hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
+ }
+ else
+ {
+ /* Wrong usage of abort function */
+ /* This function should be used only in case of abort monitored by master device */
+ return HAL_ERROR;
+ }
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+
+ /* Set NBYTES to 1 to generate a dummy read on SMBUS peripheral */
+ /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
+ SMBUS_TransferConfig(hsmbus, DevAddress, 1U, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Note : The SMBUS interrupts must be enabled after unlocking current process
+ to avoid the risk of SMBUS interrupt handle execution before current
+ process unlock */
+ if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+ {
+ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
+ }
+ else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+ {
+ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ /* Check the parameters */
+ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_TX);
+
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ hsmbus->State = (HAL_SMBUS_STATE_SLAVE_BUSY_TX | HAL_SMBUS_STATE_LISTEN);
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+
+ /* Set SBC bit to manage Acknowledge at each bit */
+ hsmbus->Instance->CR1 |= I2C_CR1_SBC;
+
+ /* Enable Address Acknowledge */
+ hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Prepare transfer parameters */
+ hsmbus->pBuffPtr = pData;
+ hsmbus->XferCount = Size;
+ hsmbus->XferOptions = XferOptions;
+
+ /* Convert OTHER_xxx XferOptions if any */
+ SMBUS_ConvertOtherXferOptions(hsmbus);
+
+ if (Size > MAX_NBYTE_SIZE)
+ {
+ hsmbus->XferSize = MAX_NBYTE_SIZE;
+ }
+ else
+ {
+ hsmbus->XferSize = Size;
+ }
+
+ /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
+ if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount))
+ {
+ SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
+ }
+ else
+ {
+ /* Set NBYTE to transmit */
+ SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+
+ /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
+ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
+ if (SMBUS_GET_PEC_MODE(hsmbus) != RESET)
+ {
+ hsmbus->XferSize--;
+ hsmbus->XferCount--;
+ }
+ }
+
+ /* Clear ADDR flag after prepare the transfer parameters */
+ /* This action will generate an acknowledge to the HOST */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Note : The SMBUS interrupts must be enabled after unlocking current process
+ to avoid the risk of SMBUS interrupt handle execution before current
+ process unlock */
+ /* REnable ADDR interrupt */
+ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX | SMBUS_IT_ADDR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ /* Check the parameters */
+ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_RX);
+
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ hsmbus->State = (HAL_SMBUS_STATE_SLAVE_BUSY_RX | HAL_SMBUS_STATE_LISTEN);
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+
+ /* Set SBC bit to manage Acknowledge at each bit */
+ hsmbus->Instance->CR1 |= I2C_CR1_SBC;
+
+ /* Enable Address Acknowledge */
+ hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Prepare transfer parameters */
+ hsmbus->pBuffPtr = pData;
+ hsmbus->XferSize = Size;
+ hsmbus->XferCount = Size;
+ hsmbus->XferOptions = XferOptions;
+
+ /* Convert OTHER_xxx XferOptions if any */
+ SMBUS_ConvertOtherXferOptions(hsmbus);
+
+ /* Set NBYTE to receive */
+ /* If XferSize equal "1", or XferSize equal "2" with PEC requested (mean 1 data byte + 1 PEC byte */
+ /* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */
+ /* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */
+ /* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */
+ if ((hsmbus->XferSize == 1U) || ((hsmbus->XferSize == 2U) && (SMBUS_GET_PEC_MODE(hsmbus) != RESET)))
+ {
+ SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ }
+ else
+ {
+ SMBUS_TransferConfig(hsmbus, 0U, 1U, hsmbus->XferOptions | SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP);
+ }
+
+ /* Clear ADDR flag after prepare the transfer parameters */
+ /* This action will generate an acknowledge to the HOST */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Note : The SMBUS interrupts must be enabled after unlocking current process
+ to avoid the risk of SMBUS interrupt handle execution before current
+ process unlock */
+ /* REnable ADDR interrupt */
+ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_ADDR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Enable the Address listen mode with Interrupt.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus)
+{
+ hsmbus->State = HAL_SMBUS_STATE_LISTEN;
+
+ /* Enable the Address Match interrupt */
+ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ADDR);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the Address listen mode with Interrupt.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Disable Address listen mode only if a transfer is not ongoing */
+ if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
+ {
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Disable the Address Match interrupt */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Enable the SMBUS alert mode with Interrupt.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUSx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Enable SMBus alert */
+ hsmbus->Instance->CR1 |= I2C_CR1_ALERTEN;
+
+ /* Clear ALERT flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
+
+ /* Enable Alert Interrupt */
+ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ALERT);
+
+ return HAL_OK;
+}
+/**
+ * @brief Disable the SMBUS alert mode with Interrupt.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUSx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Enable SMBus alert */
+ hsmbus->Instance->CR1 &= ~I2C_CR1_ALERTEN;
+
+ /* Disable Alert Interrupt */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ALERT);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Check if target device is ready for communication.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param Trials Number of trials
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ __IO uint32_t SMBUS_Trials = 0U;
+
+ if (hsmbus->State == HAL_SMBUS_STATE_READY)
+ {
+ if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BUSY) != RESET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_BUSY;
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+
+ do
+ {
+ /* Generate Start */
+ hsmbus->Instance->CR2 = SMBUS_GENERATE_START(hsmbus->Init.AddressingMode, DevAddress);
+
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is set or a NACK flag is set*/
+ tickstart = HAL_GetTick();
+ while ((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) == RESET) && (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) && (hsmbus->State != HAL_SMBUS_STATE_TIMEOUT))
+ {
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ /* Device is ready */
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Check if the NACKF flag has not been set */
+ if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET)
+ {
+ /* Wait until STOPF flag is reset */
+ if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear STOP Flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+
+ /* Device is ready */
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Wait until STOPF flag is reset */
+ if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear NACK Flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
+
+ /* Clear STOP Flag, auto generated with autoend*/
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+ }
+
+ /* Check if the maximum allowed number of trials has been reached */
+ if (SMBUS_Trials++ == Trials)
+ {
+ /* Generate Stop */
+ hsmbus->Instance->CR2 |= I2C_CR2_STOP;
+
+ /* Wait until STOPF flag is reset */
+ if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear STOP Flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+ }
+ }
+ while (SMBUS_Trials < Trials);
+
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_TIMEOUT;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+
+/**
+ * @brief Handle SMBUS event interrupt request.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
+{
+ uint32_t tmpisrvalue = 0U;
+
+ /* Use a local variable to store the current ISR flags */
+ /* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */
+ tmpisrvalue = SMBUS_GET_ISR_REG(hsmbus);
+
+ /* SMBUS in mode Transmitter ---------------------------------------------------*/
+ if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET))
+ {
+ /* Slave mode selected */
+ if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
+ {
+ SMBUS_Slave_ISR(hsmbus);
+ }
+ /* Master mode selected */
+ else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+ {
+ SMBUS_Master_ISR(hsmbus);
+ }
+ }
+
+ /* SMBUS in mode Receiver ----------------------------------------------------*/
+ if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET))
+ {
+ /* Slave mode selected */
+ if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
+ {
+ SMBUS_Slave_ISR(hsmbus);
+ }
+ /* Master mode selected */
+ else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+ {
+ SMBUS_Master_ISR(hsmbus);
+ }
+ }
+
+ /* SMBUS in mode Listener Only --------------------------------------------------*/
+ if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))
+ && ((__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ADDRI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_STOPI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_NACKI) != RESET)))
+ {
+ if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
+ {
+ SMBUS_Slave_ISR(hsmbus);
+ }
+ }
+}
+
+/**
+ * @brief Handle SMBUS error interrupt request.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
+{
+ SMBUS_ITErrorHandler(hsmbus);
+}
+
+/**
+ * @brief Master Tx Transfer completed callback.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+__weak void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmbus);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_MasterTxCpltCallback() could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Master Rx Transfer completed callback.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+__weak void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmbus);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_MasterRxCpltCallback() could be implemented in the user file
+ */
+}
+
+/** @brief Slave Tx Transfer completed callback.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+__weak void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmbus);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_SlaveTxCpltCallback() could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Slave Rx Transfer completed callback.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+__weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmbus);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_SlaveRxCpltCallback() could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Slave Address Match callback.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param TransferDirection Master request Transfer Direction (Write/Read)
+ * @param AddrMatchCode Address Match Code
+ * @retval None
+ */
+__weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmbus);
+ UNUSED(TransferDirection);
+ UNUSED(AddrMatchCode);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_AddrCallback() could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Listen Complete callback.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+__weak void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmbus);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_ListenCpltCallback() could be implemented in the user file
+ */
+}
+
+/**
+ * @brief SMBUS error callback.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+__weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmbus);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_ErrorCallback() could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief Peripheral State and Errors functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the SMBUS handle state.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval HAL state
+ */
+uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Return SMBUS handle state */
+ return hsmbus->State;
+}
+
+/**
+* @brief Return the SMBUS error code.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+* @retval SMBUS Error Code
+*/
+uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus)
+{
+ return hsmbus->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
+ * @brief Data transfers Private functions
+ * @{
+ */
+
+/**
+ * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus)
+{
+ uint16_t DevAddress;
+
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET)
+ {
+ /* Clear NACK Flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
+
+ /* Set corresponding Error Code */
+ /* No need to generate STOP, it is automatically done */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Call the Error callback to inform upper layer */
+ HAL_SMBUS_ErrorCallback(hsmbus);
+ }
+ else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET)
+ {
+ /* Check and treat errors if errors occurs during STOP process */
+ SMBUS_ITErrorHandler(hsmbus);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+ {
+ /* Disable Interrupt */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
+
+ /* Clear STOP Flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ SMBUS_RESET_CR2(hsmbus);
+
+ /* Flush remaining data in Fifo register in case of error occurs before TXEmpty */
+ /* Disable the selected SMBUS peripheral */
+ __HAL_SMBUS_DISABLE(hsmbus);
+
+ hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* REenable the selected SMBUS peripheral */
+ __HAL_SMBUS_ENABLE(hsmbus);
+
+ HAL_SMBUS_MasterTxCpltCallback(hsmbus);
+ }
+ else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+ {
+ /* Store Last receive data if any */
+ if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
+ {
+ /* Read data from RXDR */
+ (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
+
+ if ((hsmbus->XferSize > 0U))
+ {
+ hsmbus->XferSize--;
+ hsmbus->XferCount--;
+ }
+ }
+
+ /* Disable Interrupt */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
+
+ /* Clear STOP Flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ SMBUS_RESET_CR2(hsmbus);
+
+ hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ HAL_SMBUS_MasterRxCpltCallback(hsmbus);
+ }
+ }
+ else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
+ {
+ /* Read data from RXDR */
+ (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
+ hsmbus->XferSize--;
+ hsmbus->XferCount--;
+ }
+ else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
+ {
+ /* Write data to TXDR */
+ hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++);
+ hsmbus->XferSize--;
+ hsmbus->XferCount--;
+ }
+ else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET)
+ {
+ if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount != 0U))
+ {
+ DevAddress = (hsmbus->Instance->CR2 & I2C_CR2_SADD);
+
+ if (hsmbus->XferCount > MAX_NBYTE_SIZE)
+ {
+ SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
+ hsmbus->XferSize = MAX_NBYTE_SIZE;
+ }
+ else
+ {
+ hsmbus->XferSize = hsmbus->XferCount;
+ SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
+ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
+ if (SMBUS_GET_PEC_MODE(hsmbus) != RESET)
+ {
+ hsmbus->XferSize--;
+ hsmbus->XferCount--;
+ }
+ }
+ }
+ else if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount == 0U))
+ {
+ /* Call TxCpltCallback() if no stop mode is set */
+ if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
+ {
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+ {
+ /* Disable Interrupt */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
+ hsmbus->PreviousState = hsmbus->State;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ HAL_SMBUS_MasterTxCpltCallback(hsmbus);
+ }
+ else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+ {
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
+ hsmbus->PreviousState = hsmbus->State;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ HAL_SMBUS_MasterRxCpltCallback(hsmbus);
+ }
+ }
+ }
+ }
+ else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TC) != RESET)
+ {
+ if (hsmbus->XferCount == 0U)
+ {
+ /* Specific use case for Quick command */
+ if (hsmbus->pBuffPtr == NULL)
+ {
+ /* Generate a Stop command */
+ hsmbus->Instance->CR2 |= I2C_CR2_STOP;
+ }
+ /* Call TxCpltCallback() if no stop mode is set */
+ else if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
+ {
+ /* No Generate Stop, to permit restart mode */
+ /* The stop will be done at the end of transfer, when SMBUS_AUTOEND_MODE enable */
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+ {
+ /* Disable Interrupt */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
+ hsmbus->PreviousState = hsmbus->State;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ HAL_SMBUS_MasterTxCpltCallback(hsmbus);
+ }
+ else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+ {
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
+ hsmbus->PreviousState = hsmbus->State;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ HAL_SMBUS_MasterRxCpltCallback(hsmbus);
+ }
+ }
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_OK;
+}
+/**
+ * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus)
+{
+ uint8_t TransferDirection = 0U;
+ uint16_t SlaveAddrCode = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET)
+ {
+ /* Check that SMBUS transfer finished */
+ /* if yes, normal usecase, a NACK is sent by the HOST when Transfer is finished */
+ /* Mean XferCount == 0*/
+ /* So clear Flag NACKF only */
+ if (hsmbus->XferCount == 0U)
+ {
+ /* Clear NACK Flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+ }
+ else
+ {
+ /* if no, error usecase, a Non-Acknowledge of last Data is generated by the HOST*/
+ /* Clear NACK Flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
+
+ /* Set HAL State to "Idle" State, mean to LISTEN state */
+ /* So reset Slave Busy state */
+ hsmbus->PreviousState = hsmbus->State;
+ hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX);
+ hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
+
+ /* Disable RX/TX Interrupts, keep only ADDR Interrupt */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX);
+
+ /* Set ErrorCode corresponding to a Non-Acknowledge */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Call the Error callback to inform upper layer */
+ HAL_SMBUS_ErrorCallback(hsmbus);
+ }
+ }
+ else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ADDR) != RESET)
+ {
+ TransferDirection = SMBUS_GET_DIR(hsmbus);
+ SlaveAddrCode = SMBUS_GET_ADDR_MATCH(hsmbus);
+
+ /* Disable ADDR interrupt to prevent multiple ADDRInterrupt*/
+ /* Other ADDRInterrupt will be treat in next Listen usecase */
+ __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_ADDRI);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Call Slave Addr callback */
+ HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode);
+ }
+ else if ((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) || (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET))
+ {
+ if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
+ {
+ /* Read data from RXDR */
+ (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
+ hsmbus->XferSize--;
+ hsmbus->XferCount--;
+
+ if (hsmbus->XferCount == 1U)
+ {
+ /* Receive last Byte, can be PEC byte in case of PEC BYTE enabled */
+ /* or only the last Byte of Transfer */
+ /* So reset the RELOAD bit mode */
+ hsmbus->XferOptions &= ~SMBUS_RELOAD_MODE;
+ SMBUS_TransferConfig(hsmbus, 0U, 1U, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ }
+ else if (hsmbus->XferCount == 0U)
+ {
+ /* Last Byte is received, disable Interrupt */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
+
+ /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_RX, keep only HAL_SMBUS_STATE_LISTEN */
+ hsmbus->PreviousState = hsmbus->State;
+ hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Call the Rx complete callback to inform upper layer of the end of receive process */
+ HAL_SMBUS_SlaveRxCpltCallback(hsmbus);
+ }
+ else
+ {
+ /* Set Reload for next Bytes */
+ SMBUS_TransferConfig(hsmbus, 0U, 1U, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
+
+ /* Ack last Byte Read */
+ hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
+ }
+ }
+ else if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
+ {
+ if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount != 0U))
+ {
+ if (hsmbus->XferCount > MAX_NBYTE_SIZE)
+ {
+ SMBUS_TransferConfig(hsmbus, 0U, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
+ hsmbus->XferSize = MAX_NBYTE_SIZE;
+ }
+ else
+ {
+ hsmbus->XferSize = hsmbus->XferCount;
+ SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
+ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
+ if (SMBUS_GET_PEC_MODE(hsmbus) != RESET)
+ {
+ hsmbus->XferSize--;
+ hsmbus->XferCount--;
+ }
+ }
+ }
+ }
+ }
+ else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
+ {
+ /* Write data to TXDR only if XferCount not reach "0" */
+ /* A TXIS flag can be set, during STOP treatment */
+ /* Check if all Data have already been sent */
+ /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
+ if (hsmbus->XferCount > 0U)
+ {
+ /* Write data to TXDR */
+ hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++);
+ hsmbus->XferCount--;
+ hsmbus->XferSize--;
+ }
+
+ if (hsmbus->XferCount == 0U)
+ {
+ /* Last Byte is Transmitted */
+ /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_TX, keep only HAL_SMBUS_STATE_LISTEN */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
+ hsmbus->PreviousState = hsmbus->State;
+ hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Call the Tx complete callback to inform upper layer of the end of transmit process */
+ HAL_SMBUS_SlaveTxCpltCallback(hsmbus);
+ }
+ }
+
+ /* Check if STOPF is set */
+ if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET)
+ {
+ if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
+ {
+ /* Store Last receive data if any */
+ if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
+ {
+ /* Read data from RXDR */
+ (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
+
+ if ((hsmbus->XferSize > 0U))
+ {
+ hsmbus->XferSize--;
+ hsmbus->XferCount--;
+ }
+ }
+
+ /* Disable RX and TX Interrupts */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX);
+
+ /* Disable ADDR Interrupt */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
+
+ /* Disable Address Acknowledge */
+ hsmbus->Instance->CR2 |= I2C_CR2_NACK;
+
+ /* Clear Configuration Register 2 */
+ SMBUS_RESET_CR2(hsmbus);
+
+ /* Clear STOP Flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+
+ /* Clear ADDR flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
+
+ hsmbus->XferOptions = 0U;
+ hsmbus->PreviousState = hsmbus->State;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+ HAL_SMBUS_ListenCpltCallback(hsmbus);
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_OK;
+}
+/**
+ * @brief Manage the enabling of Interrupts.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
+{
+ uint32_t tmpisr = 0U;
+
+ if ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT)
+ {
+ /* Enable ERR interrupt */
+ tmpisr |= SMBUS_IT_ERRI;
+ }
+
+ if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
+ {
+ /* Enable ADDR, STOP interrupt */
+ tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_ERRI;
+ }
+
+ if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
+ {
+ /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+ tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI;
+ }
+
+ if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
+ {
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI;
+ }
+
+ /* Enable interrupts only at the end */
+ /* to avoid the risk of SMBUS interrupt handle execution before */
+ /* all interrupts requested done */
+ __HAL_SMBUS_ENABLE_IT(hsmbus, tmpisr);
+
+ return HAL_OK;
+}
+/**
+ * @brief Manage the disabling of Interrupts.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
+{
+ uint32_t tmpisr = 0U;
+
+ if (((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) && (hsmbus->State == HAL_SMBUS_STATE_READY))
+ {
+ /* Disable ERR interrupt */
+ tmpisr |= SMBUS_IT_ERRI;
+ }
+
+ if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
+ {
+ /* Disable TC, STOP, NACK, TXI interrupt */
+ tmpisr |= SMBUS_IT_TCI | SMBUS_IT_TXI;
+
+ if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
+ && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
+ {
+ /* Disable ERR interrupt */
+ tmpisr |= SMBUS_IT_ERRI;
+ }
+
+ if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
+ {
+ /* Disable STOPI, NACKI */
+ tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
+ }
+ }
+
+ if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
+ {
+ /* Disable TC, STOP, NACK, RXI interrupt */
+ tmpisr |= SMBUS_IT_TCI | SMBUS_IT_RXI;
+
+ if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
+ && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
+ {
+ /* Disable ERR interrupt */
+ tmpisr |= SMBUS_IT_ERRI;
+ }
+
+ if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
+ {
+ /* Disable STOPI, NACKI */
+ tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
+ }
+ }
+
+ if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
+ {
+ /* Enable ADDR, STOP interrupt */
+ tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI;
+
+ if (SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
+ {
+ /* Disable ERR interrupt */
+ tmpisr |= SMBUS_IT_ERRI;
+ }
+ }
+
+ /* Disable interrupts only at the end */
+ /* to avoid a breaking situation like at "t" time */
+ /* all disable interrupts request are not done */
+ __HAL_SMBUS_DISABLE_IT(hsmbus, tmpisr);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief SMBUS interrupts error handler.
+ * @param hsmbus SMBUS handle.
+ * @retval None
+ */
+static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus)
+{
+ uint32_t itflags = READ_REG(hsmbus->Instance->ISR);
+ uint32_t itsources = READ_REG(hsmbus->Instance->CR1);
+
+ /* SMBUS Bus error interrupt occurred ------------------------------------*/
+ if (((itflags & SMBUS_FLAG_BERR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
+ {
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR;
+
+ /* Clear BERR flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_BERR);
+ }
+
+ /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/
+ if (((itflags & SMBUS_FLAG_OVR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
+ {
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR;
+
+ /* Clear OVR flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_OVR);
+ }
+
+ /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/
+ if (((itflags & SMBUS_FLAG_ARLO) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
+ {
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO;
+
+ /* Clear ARLO flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ARLO);
+ }
+
+ /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/
+ if (((itflags & SMBUS_FLAG_TIMEOUT) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
+ {
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT;
+
+ /* Clear TIMEOUT flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT);
+ }
+
+ /* SMBUS Alert error interrupt occurred -----------------------------------------------*/
+ if (((itflags & SMBUS_FLAG_ALERT) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
+ {
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT;
+
+ /* Clear ALERT flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
+ }
+
+ /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/
+ if (((itflags & SMBUS_FLAG_PECERR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
+ {
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR;
+
+ /* Clear PEC error flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR);
+ }
+
+ /* Call the Error Callback in case of Error detected */
+ if ((hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE) && (hsmbus->ErrorCode != HAL_SMBUS_ERROR_ACKF))
+ {
+ /* Do not Reset the HAL state in case of ALERT error */
+ if ((hsmbus->ErrorCode & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT)
+ {
+ if (((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
+ || ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX))
+ {
+ /* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */
+ /* keep HAL_SMBUS_STATE_LISTEN if set */
+ hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
+ hsmbus->State = HAL_SMBUS_STATE_LISTEN;
+ }
+ }
+
+ /* Call the Error callback to inform upper layer */
+ HAL_SMBUS_ErrorCallback(hsmbus);
+ }
+}
+
+/**
+ * @brief Handle SMBUS Communication Timeout.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param Flag Specifies the SMBUS flag to check.
+ * @param Status The new Flag status (SET or RESET).
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Wait until flag is set */
+ if (Status == RESET)
+ {
+ while (__HAL_SMBUS_GET_FLAG(hsmbus, Flag) == RESET)
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ hsmbus->PreviousState = hsmbus->State;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else
+ {
+ while (__HAL_SMBUS_GET_FLAG(hsmbus, Flag) != RESET)
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ hsmbus->PreviousState = hsmbus->State;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).
+ * @param hsmbus SMBUS handle.
+ * @param DevAddress specifies the slave address to be programmed.
+ * @param Size specifies the number of bytes to be programmed.
+ * This parameter must be a value between 0 and 255.
+ * @param Mode New state of the SMBUS START condition generation.
+ * This parameter can be one or a combination of the following values:
+ * @arg @ref SMBUS_RELOAD_MODE Enable Reload mode.
+ * @arg @ref SMBUS_AUTOEND_MODE Enable Automatic end mode.
+ * @arg @ref SMBUS_SOFTEND_MODE Enable Software end mode and Reload mode.
+ * @arg @ref SMBUS_SENDPEC_MODE Enable Packet Error Calculation mode.
+ * @param Request New state of the SMBUS START condition generation.
+ * This parameter can be one of the following values:
+ * @arg @ref SMBUS_NO_STARTSTOP Don't Generate stop and start condition.
+ * @arg @ref SMBUS_GENERATE_STOP Generate stop condition (Size should be set to 0).
+ * @arg @ref SMBUS_GENERATE_START_READ Generate Restart for read request.
+ * @arg @ref SMBUS_GENERATE_START_WRITE Generate Restart for write request.
+ * @retval None
+ */
+static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
+{
+ /* Check the parameters */
+ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
+ assert_param(IS_SMBUS_TRANSFER_MODE(Mode));
+ assert_param(IS_SMBUS_TRANSFER_REQUEST(Request));
+
+ /* update CR2 register */
+ MODIFY_REG(hsmbus->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)), \
+ (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
+}
+
+/**
+ * @brief Convert SMBUSx OTHER_xxx XferOptions to functionnal XferOptions.
+ * @param hsmbus SMBUS handle.
+ * @retval None
+ */
+static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* if user set XferOptions to SMBUS_OTHER_FRAME_NO_PEC */
+ /* it request implicitly to generate a restart condition */
+ /* set XferOptions to SMBUS_FIRST_FRAME */
+ if (hsmbus->XferOptions == SMBUS_OTHER_FRAME_NO_PEC)
+ {
+ hsmbus->XferOptions = SMBUS_FIRST_FRAME;
+ }
+ /* else if user set XferOptions to SMBUS_OTHER_FRAME_WITH_PEC */
+ /* it request implicitly to generate a restart condition */
+ /* set XferOptions to SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE */
+ else if (hsmbus->XferOptions == SMBUS_OTHER_FRAME_WITH_PEC)
+ {
+ hsmbus->XferOptions = SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE;
+ }
+ /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_NO_PEC */
+ /* it request implicitly to generate a restart condition */
+ /* then generate a stop condition at the end of transfer */
+ /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_NO_PEC */
+ else if (hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC)
+ {
+ hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_NO_PEC;
+ }
+ /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC */
+ /* it request implicitly to generate a restart condition */
+ /* then generate a stop condition at the end of transfer */
+ /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC */
+ else if (hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)
+ {
+ hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC;
+ }
+}
+/**
+ * @}
+ */
+
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_spi.c b/Src/stm32f3xx_hal_spi.c
new file mode 100644
index 0000000..b568ac8
--- /dev/null
+++ b/Src/stm32f3xx_hal_spi.c
@@ -0,0 +1,3863 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_spi.c
+ * @author MCD Application Team
+ * @brief SPI HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Serial Peripheral Interface (SPI) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The SPI HAL driver can be used as follows:
+
+ (#) Declare a SPI_HandleTypeDef handle structure, for example:
+ SPI_HandleTypeDef hspi;
+
+ (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
+ (##) Enable the SPIx interface clock
+ (##) SPI pins configuration
+ (+++) Enable the clock for the SPI GPIOs
+ (+++) Configure these SPI pins as alternate function push-pull
+ (##) NVIC configuration if you need to use interrupt process
+ (+++) Configure the SPIx interrupt priority
+ (+++) Enable the NVIC SPI IRQ handle
+ (##) DMA Configuration if you need to use DMA process
+ (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
+ (+++) Enable the DMAx clock
+ (+++) Configure the DMA handle parameters
+ (+++) Configure the DMA Tx or Rx Stream/Channel
+ (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
+
+ (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
+ management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
+
+ (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
+ (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ by calling the customized HAL_SPI_MspInit() API.
+ [..]
+ Circular mode restriction:
+ (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
+ (##) Master 2Lines RxOnly
+ (##) Master 1Line Rx
+ (#) The CRC feature is not managed when the DMA circular mode is enabled
+ (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
+ the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
+ [..]
+ Master Receive mode restriction:
+ (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=0) or
+ bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
+ does not initiate a new transfer the following procedure has to be respected:
+ (##) HAL_SPI_DeInit()
+ (##) HAL_SPI_Init()
+ [..]
+ The HAL drivers do not allow reaching all supported SPI frequencies in the different SPI
+ modes. Refer to the source code (stm32xxxx_hal_spi.c header) to get a summary of the
+ maximum SPI frequency that can be reached with a data size of 8 or 16 bits, depending on
+ the APBx peripheral clock frequency (fPCLK) used by the SPI instance.
+
+
+ @endverbatim
+
+ Additional table :
+
+ DataSize = SPI_DATASIZE_8BIT:
+ +----------------------------------------------------------------------------------------------+
+ | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
+ | Process | Tranfert mode |---------------------|----------------------|----------------------|
+ | | | Master | Slave | Master | Slave | Master | Slave |
+ |==============================================================================================|
+ | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
+ | X |----------------|----------|----------|-----------|----------|-----------|----------|
+ | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA |
+ | R |----------------|----------|----------|-----------|----------|-----------|----------|
+ | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
+ |=========|================|==========|==========|===========|==========|===========|==========|
+ | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 |
+ | |----------------|----------|----------|-----------|----------|-----------|----------|
+ | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 |
+ | X |----------------|----------|----------|-----------|----------|-----------|----------|
+ | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 |
+ |=========|================|==========|==========|===========|==========|===========|==========|
+ | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 |
+ | |----------------|----------|----------|-----------|----------|-----------|----------|
+ | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 |
+ | X |----------------|----------|----------|-----------|----------|-----------|----------|
+ | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 |
+ +----------------------------------------------------------------------------------------------+
+
+ DataSize = SPI_DATASIZE_16BIT:
+ +----------------------------------------------------------------------------------------------+
+ | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
+ | Process | Tranfert mode |---------------------|----------------------|----------------------|
+ | | | Master | Slave | Master | Slave | Master | Slave |
+ |==============================================================================================|
+ | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
+ | X |----------------|----------|----------|-----------|----------|-----------|----------|
+ | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA |
+ | R |----------------|----------|----------|-----------|----------|-----------|----------|
+ | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
+ |=========|================|==========|==========|===========|==========|===========|==========|
+ | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 |
+ | |----------------|----------|----------|-----------|----------|-----------|----------|
+ | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 |
+ | X |----------------|----------|----------|-----------|----------|-----------|----------|
+ | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 |
+ |=========|================|==========|==========|===========|==========|===========|==========|
+ | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 |
+ | |----------------|----------|----------|-----------|----------|-----------|----------|
+ | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 |
+ | X |----------------|----------|----------|-----------|----------|-----------|----------|
+ | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 |
+ +----------------------------------------------------------------------------------------------+
+ @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits),
+ SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
+ @note
+ (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
+ (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
+ (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
+
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SPI SPI
+ * @brief SPI HAL module driver
+ * @{
+ */
+#ifdef HAL_SPI_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup SPI_Private_Constants SPI Private Constants
+ * @{
+ */
+#define SPI_DEFAULT_TIMEOUT 100U
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup SPI_Private_Functions SPI Private Functions
+ * @{
+ */
+static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAError(DMA_HandleTypeDef *hdma);
+static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State,
+ uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
+ uint32_t Timeout, uint32_t Tickstart);
+static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
+#if (USE_SPI_CRC != 0U)
+static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
+static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
+#endif /* USE_SPI_CRC */
+static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
+static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
+static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
+static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
+static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
+static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SPI_Exported_Functions SPI Exported Functions
+ * @{
+ */
+
+/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to initialize and
+ de-initialize the SPIx peripheral:
+
+ (+) User must implement HAL_SPI_MspInit() function in which he configures
+ all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+ (+) Call the function HAL_SPI_Init() to configure the selected device with
+ the selected configuration:
+ (++) Mode
+ (++) Direction
+ (++) Data Size
+ (++) Clock Polarity and Phase
+ (++) NSS Management
+ (++) BaudRate Prescaler
+ (++) FirstBit
+ (++) TIMode
+ (++) CRC Calculation
+ (++) CRC Polynomial if CRC enabled
+ (++) CRC Length, used only with Data8 and Data16
+ (++) FIFO reception threshold
+
+ (+) Call the function HAL_SPI_DeInit() to restore the default configuration
+ of the selected SPIx peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the SPI according to the specified parameters
+ * in the SPI_InitTypeDef and initialize the associated handle.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
+{
+ uint32_t frxth;
+
+ /* Check the SPI handle allocation */
+ if (hspi == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
+ assert_param(IS_SPI_MODE(hspi->Init.Mode));
+ assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
+ assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
+ assert_param(IS_SPI_NSS(hspi->Init.NSS));
+ assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
+ assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
+ assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
+ assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
+ if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
+ {
+ assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
+ assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
+ }
+#if (USE_SPI_CRC != 0U)
+ assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
+ assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
+ }
+#else
+ hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
+#endif /* USE_SPI_CRC */
+
+ if (hspi->State == HAL_SPI_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hspi->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+ HAL_SPI_MspInit(hspi);
+ }
+
+ hspi->State = HAL_SPI_STATE_BUSY;
+
+ /* Disable the selected SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* Align by default the rs fifo threshold on the data size */
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ frxth = SPI_RXFIFO_THRESHOLD_HF;
+ }
+ else
+ {
+ frxth = SPI_RXFIFO_THRESHOLD_QF;
+ }
+
+ /* CRC calculation is valid only for 16Bit and 8 Bit */
+ if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
+ {
+ /* CRC must be disabled */
+ hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
+ }
+
+ /* Align the CRC Length on the data size */
+ if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
+ {
+ /* CRC Length aligned on the data size : value set by default */
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
+ }
+ else
+ {
+ hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
+ }
+ }
+
+ /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
+ /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
+ Communication speed, First bit and CRC calculation state */
+ WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction |
+ hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
+ hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation));
+#if (USE_SPI_CRC != 0U)
+ /* Configure : CRC Length */
+ if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
+ {
+ hspi->Instance->CR1 |= SPI_CR1_CRCL;
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo Threshold */
+ WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode |
+ hspi->Init.NSSPMode | hspi->Init.DataSize) | frxth);
+
+#if (USE_SPI_CRC != 0U)
+ /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
+ /* Configure : CRC Polynomial */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
+ }
+#endif /* USE_SPI_CRC */
+
+#if defined(SPI_I2SCFGR_I2SMOD)
+ /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
+ CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
+#endif /* SPI_I2SCFGR_I2SMOD */
+
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->State = HAL_SPI_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief De-Initialize the SPI peripheral.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
+{
+ /* Check the SPI handle allocation */
+ if (hspi == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check SPI Instance parameter */
+ assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
+
+ hspi->State = HAL_SPI_STATE_BUSY;
+
+ /* Disable the SPI Peripheral Clock */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+ HAL_SPI_MspDeInit(hspi);
+
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->State = HAL_SPI_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hspi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the SPI MSP.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_MspInit should be implemented in the user file
+ */
+}
+
+/**
+ * @brief De-Initialize the SPI MSP.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_MspDeInit should be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the SPI
+ data transfers.
+
+ [..] The SPI supports master and slave mode :
+
+ (#) There are two modes of transfer:
+ (++) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode: The communication is performed using Interrupts
+ or DMA, These APIs return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
+ will be executed respectively at the end of the transmit or Receive process
+ The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
+
+ (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
+ exist for 1Line (simplex) and 2Lines (full duplex) modes.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Transmit an amount of data in blocking mode.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData pointer to data buffer
+ * @param Size amount of data to be sent
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+
+ /* Check Direction parameter */
+ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ if (hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ if ((pData == NULL) || (Size == 0U))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ /* Set the transaction information */
+ hspi->State = HAL_SPI_STATE_BUSY_TX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = (uint8_t *)pData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+
+ /*Init field not used in handle to zero */
+ hspi->pRxBuffPtr = (uint8_t *)NULL;
+ hspi->RxXferSize = 0U;
+ hspi->RxXferCount = 0U;
+ hspi->TxISR = NULL;
+ hspi->RxISR = NULL;
+
+ /* Configure communication direction : 1Line */
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ SPI_1LINE_TX(hspi);
+ }
+
+#if (USE_SPI_CRC != 0U)
+ /* Reset CRC Calculation */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Check if the SPI is already enabled */
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+ /* Transmit data in 16 Bit mode */
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
+ {
+ hspi->Instance->DR = *((uint16_t *)pData);
+ pData += sizeof(uint16_t);
+ hspi->TxXferCount--;
+ }
+ /* Transmit data in 16 Bit mode */
+ while (hspi->TxXferCount > 0U)
+ {
+ /* Wait until TXE flag is set to send data */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
+ {
+ hspi->Instance->DR = *((uint16_t *)pData);
+ pData += sizeof(uint16_t);
+ hspi->TxXferCount--;
+ }
+ else
+ {
+ /* Timeout management */
+ if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
+ {
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+ }
+ }
+ }
+ /* Transmit data in 8 Bit mode */
+ else
+ {
+ if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
+ {
+ if (hspi->TxXferCount > 1U)
+ {
+ /* write on the data register in packing mode */
+ hspi->Instance->DR = *((uint16_t *)pData);
+ pData += sizeof(uint16_t);
+ hspi->TxXferCount -= 2U;
+ }
+ else
+ {
+ *((__IO uint8_t *)&hspi->Instance->DR) = (*pData++);
+ hspi->TxXferCount--;
+ }
+ }
+ while (hspi->TxXferCount > 0U)
+ {
+ /* Wait until TXE flag is set to send data */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
+ {
+ if (hspi->TxXferCount > 1U)
+ {
+ /* write on the data register in packing mode */
+ hspi->Instance->DR = *((uint16_t *)pData);
+ pData += sizeof(uint16_t);
+ hspi->TxXferCount -= 2U;
+ }
+ else
+ {
+ *((__IO uint8_t *)&hspi->Instance->DR) = (*pData++);
+ hspi->TxXferCount--;
+ }
+ }
+ else
+ {
+ /* Timeout management */
+ if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
+ {
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+ }
+ }
+ }
+#if (USE_SPI_CRC != 0U)
+ /* Enable CRC Transmission */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Check the end of the transaction */
+ if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
+ }
+
+ /* Clear overrun flag in 2 Lines communication mode because received is not read */
+ if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
+ {
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ }
+
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ errorcode = HAL_ERROR;
+ }
+
+error:
+ hspi->State = HAL_SPI_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData pointer to data buffer
+ * @param Size amount of data to be received
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+#if (USE_SPI_CRC != 0U)
+ __IO uint16_t tmpreg = 0U;
+#endif /* USE_SPI_CRC */
+ uint32_t tickstart = 0U;
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+
+ if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
+ return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ if (hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ if ((pData == NULL) || (Size == 0U))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ /* Set the transaction information */
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pRxBuffPtr = (uint8_t *)pData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
+
+ /*Init field not used in handle to zero */
+ hspi->pTxBuffPtr = (uint8_t *)NULL;
+ hspi->TxXferSize = 0U;
+ hspi->TxXferCount = 0U;
+ hspi->RxISR = NULL;
+ hspi->TxISR = NULL;
+
+#if (USE_SPI_CRC != 0U)
+ /* Reset CRC Calculation */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ /* this is done to handle the CRCNEXT before the latest data */
+ hspi->RxXferCount--;
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Set the Rx FiFo threshold */
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ /* set fiforxthresold according the reception data length: 16bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
+ else
+ {
+ /* set fiforxthresold according the reception data length: 8bit */
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
+
+ /* Configure communication direction: 1Line */
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ SPI_1LINE_RX(hspi);
+ }
+
+ /* Check if the SPI is already enabled */
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+ /* Receive data in 8 Bit mode */
+ if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
+ {
+ /* Transfer loop */
+ while (hspi->RxXferCount > 0U)
+ {
+ /* Check the RXNE flag */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
+ {
+ /* read the received data */
+ (* (uint8_t *)pData) = *(__IO uint8_t *)&hspi->Instance->DR;
+ pData += sizeof(uint8_t);
+ hspi->RxXferCount--;
+ }
+ else
+ {
+ /* Timeout management */
+ if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
+ {
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+ }
+ }
+ }
+ else
+ {
+ /* Transfer loop */
+ while (hspi->RxXferCount > 0U)
+ {
+ /* Check the RXNE flag */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
+ {
+ *((uint16_t *)pData) = hspi->Instance->DR;
+ pData += sizeof(uint16_t);
+ hspi->RxXferCount--;
+ }
+ else
+ {
+ /* Timeout management */
+ if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
+ {
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+ }
+ }
+ }
+
+#if (USE_SPI_CRC != 0U)
+ /* Handle the CRC Transmission */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ /* freeze the CRC before the latest data */
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+
+ /* Read the latest data */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
+ {
+ /* the latest data has not been received */
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+
+ /* Receive last data in 16 Bit mode */
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ *((uint16_t *)pData) = hspi->Instance->DR;
+ }
+ /* Receive last data in 8 Bit mode */
+ else
+ {
+ (*(uint8_t *)pData) = *(__IO uint8_t *)&hspi->Instance->DR;
+ }
+
+ /* Wait the CRC data */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+
+ /* Read CRC to Flush DR and RXNE flag */
+ if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
+ {
+ tmpreg = hspi->Instance->DR;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+ }
+ else
+ {
+ tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+
+ if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
+ {
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout, tickstart) != HAL_OK)
+ {
+ /* Error on the CRC reception */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+ tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+ }
+ }
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Check the end of the transaction */
+ if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
+ }
+
+#if (USE_SPI_CRC != 0U)
+ /* Check if CRC error occurred */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ }
+#endif /* USE_SPI_CRC */
+
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ errorcode = HAL_ERROR;
+ }
+
+error :
+ hspi->State = HAL_SPI_STATE_READY;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Transmit and Receive an amount of data in blocking mode.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pTxData pointer to transmission data buffer
+ * @param pRxData pointer to reception data buffer
+ * @param Size amount of data to be sent and received
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
+ uint32_t Timeout)
+{
+ uint32_t tmp = 0U, tmp1 = 0U;
+#if (USE_SPI_CRC != 0U)
+ __IO uint16_t tmpreg = 0U;
+#endif /* USE_SPI_CRC */
+ uint32_t tickstart = 0U;
+ /* Variable used to alternate Rx and Tx during transfer */
+ uint32_t txallowed = 1U;
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+
+ /* Check Direction parameter */
+ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ tmp = hspi->State;
+ tmp1 = hspi->Init.Mode;
+
+ if (!((tmp == HAL_SPI_STATE_READY) || \
+ ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
+ if (hspi->State != HAL_SPI_STATE_BUSY_RX)
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+ }
+
+ /* Set the transaction information */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pRxBuffPtr = (uint8_t *)pRxData;
+ hspi->RxXferCount = Size;
+ hspi->RxXferSize = Size;
+ hspi->pTxBuffPtr = (uint8_t *)pTxData;
+ hspi->TxXferCount = Size;
+ hspi->TxXferSize = Size;
+
+ /*Init field not used in handle to zero */
+ hspi->RxISR = NULL;
+ hspi->TxISR = NULL;
+
+#if (USE_SPI_CRC != 0U)
+ /* Reset CRC Calculation */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Set the Rx Fifo threshold */
+ if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1U))
+ {
+ /* set fiforxthreshold according the reception data length: 16bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
+ else
+ {
+ /* set fiforxthreshold according the reception data length: 8bit */
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
+
+ /* Check if the SPI is already enabled */
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+ /* Transmit and Receive data in 16 Bit mode */
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
+ {
+ hspi->Instance->DR = *((uint16_t *)pTxData);
+ pTxData += sizeof(uint16_t);
+ hspi->TxXferCount--;
+ }
+ while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
+ {
+ /* Check TXE flag */
+ if (txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
+ {
+ hspi->Instance->DR = *((uint16_t *)pTxData);
+ pTxData += sizeof(uint16_t);
+ hspi->TxXferCount--;
+ /* Next Data is a reception (Rx). Tx not allowed */
+ txallowed = 0U;
+
+#if (USE_SPI_CRC != 0U)
+ /* Enable CRC Transmission */
+ if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+ {
+ /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
+ if (((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0U) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP))
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
+ }
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+#endif /* USE_SPI_CRC */
+ }
+
+ /* Check RXNE flag */
+ if ((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
+ {
+ *((uint16_t *)pRxData) = hspi->Instance->DR;
+ pRxData += sizeof(uint16_t);
+ hspi->RxXferCount--;
+ /* Next Data is a Transmission (Tx). Tx is allowed */
+ txallowed = 1U;
+ }
+ if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout))
+ {
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+ }
+ }
+ /* Transmit and Receive data in 8 Bit mode */
+ else
+ {
+ if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
+ {
+ if (hspi->TxXferCount > 1U)
+ {
+ hspi->Instance->DR = *((uint16_t *)pTxData);
+ pTxData += sizeof(uint16_t);
+ hspi->TxXferCount -= 2U;
+ }
+ else
+ {
+ *(__IO uint8_t *)&hspi->Instance->DR = (*pTxData++);
+ hspi->TxXferCount--;
+ }
+ }
+ while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
+ {
+ /* check TXE flag */
+ if (txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
+ {
+ if (hspi->TxXferCount > 1U)
+ {
+ hspi->Instance->DR = *((uint16_t *)pTxData);
+ pTxData += sizeof(uint16_t);
+ hspi->TxXferCount -= 2U;
+ }
+ else
+ {
+ *(__IO uint8_t *)&hspi->Instance->DR = (*pTxData++);
+ hspi->TxXferCount--;
+ }
+ /* Next Data is a reception (Rx). Tx not allowed */
+ txallowed = 0U;
+
+#if (USE_SPI_CRC != 0U)
+ /* Enable CRC Transmission */
+ if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+ {
+ /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
+ if (((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0U) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP))
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
+ }
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+#endif /* USE_SPI_CRC */
+ }
+
+ /* Wait until RXNE flag is reset */
+ if ((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
+ {
+ if (hspi->RxXferCount > 1U)
+ {
+ *((uint16_t *)pRxData) = hspi->Instance->DR;
+ pRxData += sizeof(uint16_t);
+ hspi->RxXferCount -= 2U;
+ if (hspi->RxXferCount <= 1U)
+ {
+ /* set fiforxthresold before to switch on 8 bit data size */
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
+ }
+ else
+ {
+ (*(uint8_t *)pRxData++) = *(__IO uint8_t *)&hspi->Instance->DR;
+ hspi->RxXferCount--;
+ }
+ /* Next Data is a Transmission (Tx). Tx is allowed */
+ txallowed = 1U;
+ }
+ if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout))
+ {
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+ }
+ }
+
+#if (USE_SPI_CRC != 0U)
+ /* Read CRC from DR to close CRC calculation process */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ /* Wait until TXE flag */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
+ {
+ /* Error on the CRC reception */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+ /* Read CRC */
+ if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
+ {
+ tmpreg = hspi->Instance->DR;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+ }
+ else
+ {
+ tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+
+ if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
+ {
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
+ {
+ /* Error on the CRC reception */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+ tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+ }
+ }
+ }
+
+ /* Check if CRC error occurred */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ /* Clear CRC Flag */
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+
+ errorcode = HAL_ERROR;
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Check the end of the transaction */
+ if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
+ }
+
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ errorcode = HAL_ERROR;
+ }
+
+error :
+ hspi->State = HAL_SPI_STATE_READY;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Transmit an amount of data in non-blocking mode with Interrupt.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData pointer to data buffer
+ * @param Size amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+
+ /* Check Direction parameter */
+ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ if ((pData == NULL) || (Size == 0U))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ if (hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ /* Set the transaction information */
+ hspi->State = HAL_SPI_STATE_BUSY_TX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = (uint8_t *)pData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+
+ /* Init field not used in handle to zero */
+ hspi->pRxBuffPtr = (uint8_t *)NULL;
+ hspi->RxXferSize = 0U;
+ hspi->RxXferCount = 0U;
+ hspi->RxISR = NULL;
+
+ /* Set the function for IT treatment */
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ hspi->TxISR = SPI_TxISR_16BIT;
+ }
+ else
+ {
+ hspi->TxISR = SPI_TxISR_8BIT;
+ }
+
+ /* Configure communication direction : 1Line */
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ SPI_1LINE_TX(hspi);
+ }
+
+#if (USE_SPI_CRC != 0U)
+ /* Reset CRC Calculation */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Enable TXE and ERR interrupt */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
+
+
+ /* Check if the SPI is already enabled */
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+error :
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode with Interrupt.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData pointer to data buffer
+ * @param Size amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+
+ if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
+ return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ if (hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ if ((pData == NULL) || (Size == 0U))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ /* Set the transaction information */
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pRxBuffPtr = (uint8_t *)pData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
+
+ /* Init field not used in handle to zero */
+ hspi->pTxBuffPtr = (uint8_t *)NULL;
+ hspi->TxXferSize = 0U;
+ hspi->TxXferCount = 0U;
+ hspi->TxISR = NULL;
+
+ /* Check the data size to adapt Rx threshold and the set the function for IT treatment */
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ /* Set fiforxthresold according the reception data length: 16 bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ hspi->RxISR = SPI_RxISR_16BIT;
+ }
+ else
+ {
+ /* Set fiforxthresold according the reception data length: 8 bit */
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ hspi->RxISR = SPI_RxISR_8BIT;
+ }
+
+ /* Configure communication direction : 1Line */
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ SPI_1LINE_RX(hspi);
+ }
+
+#if (USE_SPI_CRC != 0U)
+ /* Reset CRC Calculation */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ hspi->CRCSize = 1U;
+ if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
+ {
+ hspi->CRCSize = 2U;
+ }
+ SPI_RESET_CRC(hspi);
+ }
+ else
+ {
+ hspi->CRCSize = 0U;
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Enable TXE and ERR interrupt */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+ /* Note : The SPI must be enabled after unlocking current process
+ to avoid the risk of SPI interrupt handle execution before current
+ process unlock */
+
+ /* Check if the SPI is already enabled */
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+error :
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pTxData pointer to transmission data buffer
+ * @param pRxData pointer to reception data buffer
+ * @param Size amount of data to be sent and received
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
+{
+ uint32_t tmp = 0U, tmp1 = 0U;
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+
+ /* Check Direction parameter */
+ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
+
+ /* Process locked */
+ __HAL_LOCK(hspi);
+
+ tmp = hspi->State;
+ tmp1 = hspi->Init.Mode;
+
+ if (!((tmp == HAL_SPI_STATE_READY) || \
+ ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
+ if (hspi->State != HAL_SPI_STATE_BUSY_RX)
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+ }
+
+ /* Set the transaction information */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = (uint8_t *)pTxData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+ hspi->pRxBuffPtr = (uint8_t *)pRxData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
+
+ /* Set the function for IT treatment */
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ hspi->RxISR = SPI_2linesRxISR_16BIT;
+ hspi->TxISR = SPI_2linesTxISR_16BIT;
+ }
+ else
+ {
+ hspi->RxISR = SPI_2linesRxISR_8BIT;
+ hspi->TxISR = SPI_2linesTxISR_8BIT;
+ }
+
+#if (USE_SPI_CRC != 0U)
+ /* Reset CRC Calculation */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ hspi->CRCSize = 1U;
+ if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
+ {
+ hspi->CRCSize = 2U;
+ }
+ SPI_RESET_CRC(hspi);
+ }
+ else
+ {
+ hspi->CRCSize = 0U;
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Check if packing mode is enabled and if there is more than 2 data to receive */
+ if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2U))
+ {
+ /* Set fiforxthresold according the reception data length: 16 bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
+ else
+ {
+ /* Set fiforxthresold according the reception data length: 8 bit */
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
+
+ /* Enable TXE, RXNE and ERR interrupt */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
+
+ /* Check if the SPI is already enabled */
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+error :
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Transmit an amount of data in non-blocking mode with DMA.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData pointer to data buffer
+ * @param Size amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ /* check tx dma handle */
+ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
+
+ /* Check Direction parameter */
+ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ if (hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ if ((pData == NULL) || (Size == 0U))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ /* Set the transaction information */
+ hspi->State = HAL_SPI_STATE_BUSY_TX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = (uint8_t *)pData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+
+ /* Init field not used in handle to zero */
+ hspi->pRxBuffPtr = (uint8_t *)NULL;
+ hspi->TxISR = NULL;
+ hspi->RxISR = NULL;
+ hspi->RxXferSize = 0U;
+ hspi->RxXferCount = 0U;
+
+ /* Configure communication direction : 1Line */
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ SPI_1LINE_TX(hspi);
+ }
+
+#if (USE_SPI_CRC != 0U)
+ /* Reset CRC Calculation */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Set the SPI TxDMA Half transfer complete callback */
+ hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
+
+ /* Set the SPI TxDMA transfer complete callback */
+ hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
+
+ /* Set the DMA error callback */
+ hspi->hdmatx->XferErrorCallback = SPI_DMAError;
+
+ /* Set the DMA AbortCpltCallback */
+ hspi->hdmatx->XferAbortCallback = NULL;
+
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
+ /* Packing mode is enabled only if the DMA setting is HALWORD */
+ if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
+ {
+ /* Check the even/odd of the data size + crc if enabled */
+ if ((hspi->TxXferCount & 0x1U) == 0U)
+ {
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
+ hspi->TxXferCount = (hspi->TxXferCount >> 1U);
+ }
+ else
+ {
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
+ hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
+ }
+ }
+
+ /* Enable the Tx DMA Stream/Channel */
+ HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
+
+ /* Check if the SPI is already enabled */
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+ /* Enable the SPI Error Interrupt Bit */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
+
+ /* Enable Tx DMA Request */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+
+error :
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode with DMA.
+ * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData pointer to data buffer
+ * @note When the CRC feature is enabled the pData Length must be Size + 1.
+ * @param Size amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ /* check rx dma handle */
+ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
+
+ if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+
+ /* check tx dma handle */
+ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
+
+ /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
+ return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ if (hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ if ((pData == NULL) || (Size == 0U))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ /* Set the transaction information */
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pRxBuffPtr = (uint8_t *)pData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
+
+ /*Init field not used in handle to zero */
+ hspi->RxISR = NULL;
+ hspi->TxISR = NULL;
+ hspi->TxXferSize = 0U;
+ hspi->TxXferCount = 0U;
+
+ /* Configure communication direction : 1Line */
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ SPI_1LINE_RX(hspi);
+ }
+
+#if (USE_SPI_CRC != 0U)
+ /* Reset CRC Calculation */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+#endif /* USE_SPI_CRC */
+
+#if defined (STM32F302xC) || defined (STM32F303xC) || defined (STM32F373xC) || defined (STM32F358xx) || defined (STM32F378xx)
+ /* Packing mode management is enabled by the DMA settings */
+ if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
+ {
+ /* Restriction the DMA data received is not allowed in this mode */
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+#endif
+
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ /* Set fiforxthresold according the reception data length: 16bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
+ else
+ {
+ /* Set fiforxthresold according the reception data length: 8bit */
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+
+ if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
+ {
+ /* set fiforxthresold according the reception data length: 16bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+
+ if ((hspi->RxXferCount & 0x1U) == 0x0U)
+ {
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
+ hspi->RxXferCount = hspi->RxXferCount >> 1U;
+ }
+ else
+ {
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
+ hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
+ }
+ }
+ }
+
+ /* Set the SPI RxDMA Half transfer complete callback */
+ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
+
+ /* Set the SPI Rx DMA transfer complete callback */
+ hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
+
+ /* Set the DMA error callback */
+ hspi->hdmarx->XferErrorCallback = SPI_DMAError;
+
+ /* Set the DMA AbortCpltCallback */
+ hspi->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the Rx DMA Stream/Channel */
+ HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
+
+ /* Check if the SPI is already enabled */
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+ /* Enable the SPI Error Interrupt Bit */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
+
+ /* Enable Rx DMA Request */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
+
+error:
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pTxData pointer to transmission data buffer
+ * @param pRxData pointer to reception data buffer
+ * @note When the CRC feature is enabled the pRxData Length must be Size + 1
+ * @param Size amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size)
+{
+ uint32_t tmp = 0U, tmp1 = 0U;
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ /* check rx & tx dma handles */
+ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
+ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
+
+ /* Check Direction parameter */
+ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
+
+ /* Process locked */
+ __HAL_LOCK(hspi);
+
+ tmp = hspi->State;
+ tmp1 = hspi->Init.Mode;
+ if (!((tmp == HAL_SPI_STATE_READY) ||
+ ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
+ if (hspi->State != HAL_SPI_STATE_BUSY_RX)
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+ }
+
+ /* Set the transaction information */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = (uint8_t *)pTxData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+ hspi->pRxBuffPtr = (uint8_t *)pRxData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
+
+ /* Init field not used in handle to zero */
+ hspi->RxISR = NULL;
+ hspi->TxISR = NULL;
+
+#if (USE_SPI_CRC != 0U)
+ /* Reset CRC Calculation */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+#endif /* USE_SPI_CRC */
+
+
+#if defined (STM32F302xC) || defined (STM32F303xC) || defined (STM32F373xC) || defined (STM32F358xx) || defined (STM32F378xx)
+ /* packing mode management is enabled by the DMA settings */
+ if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
+ {
+ /* Restriction the DMA data received is not allowed in this mode */
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+#endif
+
+ /* Reset the threshold bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);
+
+ /* The packing mode management is enabled by the DMA settings according the spi data size */
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ /* Set fiforxthreshold according the reception data length: 16bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
+ else
+ {
+ /* Set fiforxthresold according the reception data length: 8bit */
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+
+ if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
+ {
+ if ((hspi->TxXferSize & 0x1U) == 0x0U)
+ {
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
+ hspi->TxXferCount = hspi->TxXferCount >> 1U;
+ }
+ else
+ {
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
+ hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
+ }
+ }
+
+ if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
+ {
+ /* Set fiforxthresold according the reception data length: 16bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+
+ if ((hspi->RxXferCount & 0x1U) == 0x0U)
+ {
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
+ hspi->RxXferCount = hspi->RxXferCount >> 1U;
+ }
+ else
+ {
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
+ hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
+ }
+ }
+ }
+
+ /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
+ if (hspi->State == HAL_SPI_STATE_BUSY_RX)
+ {
+ /* Set the SPI Rx DMA Half transfer complete callback */
+ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
+ hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
+ }
+ else
+ {
+ /* Set the SPI Tx/Rx DMA Half transfer complete callback */
+ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
+ hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
+ }
+
+ /* Set the DMA error callback */
+ hspi->hdmarx->XferErrorCallback = SPI_DMAError;
+
+ /* Set the DMA AbortCpltCallback */
+ hspi->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the Rx DMA Stream/Channel */
+ HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
+
+ /* Enable Rx DMA Request */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
+
+ /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
+ is performed in DMA reception complete callback */
+ hspi->hdmatx->XferHalfCpltCallback = NULL;
+ hspi->hdmatx->XferCpltCallback = NULL;
+ hspi->hdmatx->XferErrorCallback = NULL;
+ hspi->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the Tx DMA Stream/Channel */
+ HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
+
+ /* Check if the SPI is already enabled */
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+ /* Enable the SPI Error Interrupt Bit */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
+
+ /* Enable Tx DMA Request */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+
+error :
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Abort ongoing transfer (blocking mode).
+ * @param hspi SPI handle.
+ * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
+ * started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable SPI Interrupts (depending of transfer direction)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
+{
+ HAL_StatusTypeDef errorcode;
+ __IO uint32_t count, resetcount;
+
+ /* Initialized local variable */
+ errorcode = HAL_OK;
+ resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
+ count = resetcount;
+
+ /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
+ {
+ hspi->TxISR = SPI_AbortTx_ISR;
+ /* Wait HAL_SPI_STATE_ABORT state */
+ do
+ {
+ if (count-- == 0U)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ break;
+ }
+ }
+ while (hspi->State != HAL_SPI_STATE_ABORT);
+ /* Reset Timeout Counter */
+ count = resetcount;
+ }
+
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
+ {
+ hspi->RxISR = SPI_AbortRx_ISR;
+ /* Wait HAL_SPI_STATE_ABORT state */
+ do
+ {
+ if (count-- == 0U)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ break;
+ }
+ }
+ while (hspi->State != HAL_SPI_STATE_ABORT);
+ /* Reset Timeout Counter */
+ count = resetcount;
+ }
+
+ /* Clear ERRIE interrupts in case of DMA Mode */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
+
+ /* Disable the SPI DMA Tx or SPI DMA Rx request if enabled */
+ if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
+ {
+ /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
+ if (hspi->hdmatx != NULL)
+ {
+ /* Set the SPI DMA Abort callback :
+ will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
+ hspi->hdmatx->XferAbortCallback = NULL;
+
+ /* Abort DMA Tx Handle linked to SPI Peripheral */
+ if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Disable Tx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
+
+ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Disable SPI Peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* Empty the FRLVL fifo */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+ }
+ /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
+ if (hspi->hdmarx != NULL)
+ {
+ /* Set the SPI DMA Abort callback :
+ will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
+ hspi->hdmarx->XferAbortCallback = NULL;
+
+ /* Abort DMA Rx Handle linked to SPI Peripheral */
+ if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Disable peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* Control the BSY flag */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Empty the FRLVL fifo */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Disable Rx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
+ }
+ }
+ /* Reset Tx and Rx transfer counters */
+ hspi->RxXferCount = 0U;
+ hspi->TxXferCount = 0U;
+
+ /* Check error during Abort procedure */
+ if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
+ {
+ /* return HAL_Error in case of error during Abort procedure */
+ errorcode = HAL_ERROR;
+ }
+ else
+ {
+ /* Reset errorCode */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ }
+
+ /* Clear the Error flags in the SR register */
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ __HAL_SPI_CLEAR_FREFLAG(hspi);
+
+ /* Restore hspi->state to ready */
+ hspi->State = HAL_SPI_STATE_READY;
+
+ return errorcode;
+}
+
+/**
+ * @brief Abort ongoing transfer (Interrupt mode).
+ * @param hspi SPI handle.
+ * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
+ * started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable SPI Interrupts (depending of transfer direction)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
+{
+ HAL_StatusTypeDef errorcode;
+ uint32_t abortcplt ;
+ __IO uint32_t count, resetcount;
+
+ /* Initialized local variable */
+ errorcode = HAL_OK;
+ abortcplt = 1U;
+ resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
+ count = resetcount;
+
+ /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
+ {
+ hspi->TxISR = SPI_AbortTx_ISR;
+ /* Wait HAL_SPI_STATE_ABORT state */
+ do
+ {
+ if (count-- == 0U)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ break;
+ }
+ }
+ while (hspi->State != HAL_SPI_STATE_ABORT);
+ /* Reset Timeout Counter */
+ count = resetcount;
+ }
+
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
+ {
+ hspi->RxISR = SPI_AbortRx_ISR;
+ /* Wait HAL_SPI_STATE_ABORT state */
+ do
+ {
+ if (count-- == 0U)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ break;
+ }
+ }
+ while (hspi->State != HAL_SPI_STATE_ABORT);
+ /* Reset Timeout Counter */
+ count = resetcount;
+ }
+
+ /* Clear ERRIE interrupts in case of DMA Mode */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
+
+ /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
+ before any call to DMA Abort functions */
+ /* DMA Tx Handle is valid */
+ if (hspi->hdmatx != NULL)
+ {
+ /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
+ Otherwise, set it to NULL */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
+ {
+ hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
+ }
+ else
+ {
+ hspi->hdmatx->XferAbortCallback = NULL;
+ }
+ }
+ /* DMA Rx Handle is valid */
+ if (hspi->hdmarx != NULL)
+ {
+ /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
+ Otherwise, set it to NULL */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
+ {
+ hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
+ }
+ else
+ {
+ hspi->hdmarx->XferAbortCallback = NULL;
+ }
+ }
+
+ /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
+ if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) && (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
+ {
+ /* Abort the SPI DMA Tx Stream/Channel */
+ if (hspi->hdmatx != NULL)
+ {
+ /* Abort DMA Tx Handle linked to SPI Peripheral */
+ if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
+ {
+ hspi->hdmatx->XferAbortCallback = NULL;
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ /* Abort the SPI DMA Rx Stream/Channel */
+ if (hspi->hdmarx != NULL)
+ {
+ /* Abort DMA Rx Handle linked to SPI Peripheral */
+ if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
+ {
+ hspi->hdmarx->XferAbortCallback = NULL;
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ abortcplt = 1U;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+
+ /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
+ {
+ /* Abort the SPI DMA Tx Stream/Channel */
+ if (hspi->hdmatx != NULL)
+ {
+ /* Abort DMA Tx Handle linked to SPI Peripheral */
+ if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
+ {
+ hspi->hdmatx->XferAbortCallback = NULL;
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+ /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
+ {
+ /* Abort the SPI DMA Rx Stream/Channel */
+ if (hspi->hdmarx != NULL)
+ {
+ /* Abort DMA Rx Handle linked to SPI Peripheral */
+ if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
+ {
+ hspi->hdmarx->XferAbortCallback = NULL;
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+
+ if (abortcplt == 1U)
+ {
+ /* Reset Tx and Rx transfer counters */
+ hspi->RxXferCount = 0U;
+ hspi->TxXferCount = 0U;
+
+ /* Check error during Abort procedure */
+ if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
+ {
+ /* return HAL_Error in case of error during Abort procedure */
+ errorcode = HAL_ERROR;
+ }
+ else
+ {
+ /* Reset errorCode */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ }
+
+ /* Clear the Error flags in the SR register */
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ __HAL_SPI_CLEAR_FREFLAG(hspi);
+
+ /* Restore hspi->State to Ready */
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_SPI_AbortCpltCallback(hspi);
+ }
+
+ return errorcode;
+}
+
+/**
+ * @brief Pause the DMA Transfer.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
+{
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ /* Disable the SPI DMA Tx & Rx requests */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resume the DMA Transfer.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
+{
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ /* Enable the SPI DMA Tx & Rx requests */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the DMA Transfer.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
+{
+ /* The Lock is not implemented on this API to allow the user application
+ to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
+ when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
+ and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
+ */
+
+ /* Abort the SPI DMA tx Stream/Channel */
+ if (hspi->hdmatx != NULL)
+ {
+ HAL_DMA_Abort(hspi->hdmatx);
+ }
+ /* Abort the SPI DMA rx Stream/Channel */
+ if (hspi->hdmarx != NULL)
+ {
+ HAL_DMA_Abort(hspi->hdmarx);
+ }
+
+ /* Disable the SPI DMA Tx & Rx requests */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+ hspi->State = HAL_SPI_STATE_READY;
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle SPI interrupt request.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval None
+ */
+void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
+{
+ uint32_t itsource = hspi->Instance->CR2;
+ uint32_t itflag = hspi->Instance->SR;
+
+ /* SPI in mode Receiver ----------------------------------------------------*/
+ if (((itflag & SPI_FLAG_OVR) == RESET) &&
+ ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET))
+ {
+ hspi->RxISR(hspi);
+ return;
+ }
+
+ /* SPI in mode Transmitter -------------------------------------------------*/
+ if (((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET))
+ {
+ hspi->TxISR(hspi);
+ return;
+ }
+
+ /* SPI in Error Treatment --------------------------------------------------*/
+ if (((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET) && ((itsource & SPI_IT_ERR) != RESET))
+ {
+ /* SPI Overrun error interrupt occurred ----------------------------------*/
+ if ((itflag & SPI_FLAG_OVR) != RESET)
+ {
+ if (hspi->State != HAL_SPI_STATE_BUSY_TX)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ }
+ else
+ {
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ return;
+ }
+ }
+
+ /* SPI Mode Fault error interrupt occurred -------------------------------*/
+ if ((itflag & SPI_FLAG_MODF) != RESET)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
+ __HAL_SPI_CLEAR_MODFFLAG(hspi);
+ }
+
+ /* SPI Frame error interrupt occurred ------------------------------------*/
+ if ((itflag & SPI_FLAG_FRE) != RESET)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
+ __HAL_SPI_CLEAR_FREFLAG(hspi);
+ }
+
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ /* Disable all interrupts */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
+
+ hspi->State = HAL_SPI_STATE_READY;
+ /* Disable the SPI DMA requests if enabled */
+ if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
+ {
+ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
+
+ /* Abort the SPI DMA Rx channel */
+ if (hspi->hdmarx != NULL)
+ {
+ /* Set the SPI DMA Abort callback :
+ will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
+ hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
+ HAL_DMA_Abort_IT(hspi->hdmarx);
+ }
+ /* Abort the SPI DMA Tx channel */
+ if (hspi->hdmatx != NULL)
+ {
+ /* Set the SPI DMA Abort callback :
+ will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
+ hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
+ HAL_DMA_Abort_IT(hspi->hdmatx);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+ HAL_SPI_ErrorCallback(hspi);
+ }
+ }
+ return;
+ }
+}
+
+/**
+ * @brief Tx Transfer completed callback.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_TxCpltCallback should be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callback.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_RxCpltCallback should be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx and Rx Transfer completed callback.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_TxRxCpltCallback should be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx Half Transfer completed callback.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Half Transfer completed callback.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx and Rx Half Transfer callback.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
+ */
+}
+
+/**
+ * @brief SPI error callback.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_ErrorCallback should be implemented in the user file
+ */
+ /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
+ and user can use HAL_SPI_GetError() API to check the latest error occurred
+ */
+}
+
+/**
+ * @brief SPI Abort Complete callback.
+ * @param hspi SPI handle.
+ * @retval None
+ */
+__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_AbortCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief SPI control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the SPI.
+ (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
+ (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the SPI handle state.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval SPI state
+ */
+HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
+{
+ /* Return SPI handle state */
+ return hspi->State;
+}
+
+/**
+ * @brief Return the SPI error code.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval SPI error code in bitmap format
+ */
+uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
+{
+ /* Return SPI ErrorCode */
+ return hspi->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Private_Functions
+ * @brief Private functions
+ * @{
+ */
+
+/**
+ * @brief DMA SPI transmit process complete callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ uint32_t tickstart = 0U;
+
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
+
+ /* DMA Normal Mode */
+ if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
+ {
+ /* Disable ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
+
+ /* Disable Tx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+
+ /* Check the end of the transaction */
+ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ }
+
+ /* Clear overrun flag in 2 Lines communication mode because received data is not read */
+ if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
+ {
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ }
+
+ hspi->TxXferCount = 0U;
+ hspi->State = HAL_SPI_STATE_READY;
+
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ HAL_SPI_ErrorCallback(hspi);
+ return;
+ }
+ }
+ HAL_SPI_TxCpltCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI receive process complete callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ uint32_t tickstart = 0U;
+#if (USE_SPI_CRC != 0U)
+ __IO uint16_t tmpreg = 0U;
+#endif /* USE_SPI_CRC */
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ /* DMA Normal Mode */
+ if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
+ {
+ /* Disable ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
+
+#if (USE_SPI_CRC != 0U)
+ /* CRC handling */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ /* Wait until RXNE flag */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+ {
+ /* Error on the CRC reception */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ }
+ /* Read CRC */
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ tmpreg = hspi->Instance->DR;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+ }
+ else
+ {
+ tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+
+ if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
+ {
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+ {
+ /* Error on the CRC reception */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ }
+ tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+ }
+ }
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
+ /* Check the end of the transaction */
+ if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
+ }
+
+ hspi->RxXferCount = 0U;
+ hspi->State = HAL_SPI_STATE_READY;
+
+#if (USE_SPI_CRC != 0U)
+ /* Check if CRC error occurred */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ }
+#endif /* USE_SPI_CRC */
+
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ HAL_SPI_ErrorCallback(hspi);
+ return;
+ }
+ }
+ HAL_SPI_RxCpltCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI transmit receive process complete callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ uint32_t tickstart = 0U;
+#if (USE_SPI_CRC != 0U)
+ __IO int16_t tmpreg = 0U;
+#endif /* USE_SPI_CRC */
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ /* DMA Normal Mode */
+ if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
+ {
+ /* Disable ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
+
+#if (USE_SPI_CRC != 0U)
+ /* CRC handling */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
+ {
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT,
+ tickstart) != HAL_OK)
+ {
+ /* Error on the CRC reception */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ }
+ /* Read CRC to Flush DR and RXNE flag */
+ tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+ }
+ else
+ {
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+ {
+ /* Error on the CRC reception */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ }
+ /* Read CRC to Flush DR and RXNE flag */
+ tmpreg = hspi->Instance->DR;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+ }
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Check the end of the transaction */
+ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ }
+
+ /* Disable Rx/Tx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
+ hspi->TxXferCount = 0U;
+ hspi->RxXferCount = 0U;
+ hspi->State = HAL_SPI_STATE_READY;
+
+#if (USE_SPI_CRC != 0U)
+ /* Check if CRC error occurred */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ }
+#endif /* USE_SPI_CRC */
+
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ HAL_SPI_ErrorCallback(hspi);
+ return;
+ }
+ }
+ HAL_SPI_TxRxCpltCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI half transmit process complete callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ HAL_SPI_TxHalfCpltCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI half receive process complete callback
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ HAL_SPI_RxHalfCpltCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI half transmit receive process complete callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ HAL_SPI_TxRxHalfCpltCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI communication error callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMAError(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Stop the disable DMA transfer on SPI side */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+ hspi->State = HAL_SPI_STATE_READY;
+ HAL_SPI_ErrorCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI communication abort callback, when initiated by HAL services on Error
+ * (To be called at end of DMA Abort procedure following error occurrence).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ hspi->RxXferCount = 0U;
+ hspi->TxXferCount = 0U;
+
+ HAL_SPI_ErrorCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI Tx communication abort callback, when initiated by user
+ * (To be called at end of DMA Tx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Rx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ hspi->hdmatx->XferAbortCallback = NULL;
+
+ /* Disable Tx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+
+ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Disable SPI Peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* Empty the FRLVL fifo */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Check if an Abort process is still ongoing */
+ if (hspi->hdmarx != NULL)
+ {
+ if (hspi->hdmarx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
+ hspi->RxXferCount = 0U;
+ hspi->TxXferCount = 0U;
+
+ /* Check no error during Abort procedure */
+ if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
+ {
+ /* Reset errorCode */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ }
+
+ /* Clear the Error flags in the SR register */
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ __HAL_SPI_CLEAR_FREFLAG(hspi);
+
+ /* Restore hspi->State to Ready */
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_SPI_AbortCpltCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI Rx communication abort callback, when initiated by user
+ * (To be called at end of DMA Rx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Tx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Disable SPI Peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ hspi->hdmarx->XferAbortCallback = NULL;
+
+ /* Disable Rx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
+
+ /* Control the BSY flag */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Empty the FRLVL fifo */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Check if an Abort process is still ongoing */
+ if (hspi->hdmatx != NULL)
+ {
+ if (hspi->hdmatx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
+ hspi->RxXferCount = 0U;
+ hspi->TxXferCount = 0U;
+
+ /* Check no error during Abort procedure */
+ if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
+ {
+ /* Reset errorCode */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ }
+
+ /* Clear the Error flags in the SR register */
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ __HAL_SPI_CLEAR_FREFLAG(hspi);
+
+ /* Restore hspi->State to Ready */
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_SPI_AbortCpltCallback(hspi);
+}
+
+/**
+ * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
+{
+ /* Receive data in packing mode */
+ if (hspi->RxXferCount > 1U)
+ {
+ *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ hspi->RxXferCount -= 2U;
+ if (hspi->RxXferCount == 1U)
+ {
+ /* set fiforxthresold according the reception data length: 8bit */
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
+ }
+ /* Receive data in 8 Bit mode */
+ else
+ {
+ *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR);
+ hspi->RxXferCount--;
+ }
+
+ /* check end of the reception */
+ if (hspi->RxXferCount == 0U)
+ {
+#if (USE_SPI_CRC != 0U)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ hspi->RxISR = SPI_2linesRxISR_8BITCRC;
+ return;
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Disable RXNE and ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+ if (hspi->TxXferCount == 0U)
+ {
+ SPI_CloseRxTx_ISR(hspi);
+ }
+ }
+}
+
+#if (USE_SPI_CRC != 0U)
+/**
+ * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
+{
+ __IO uint8_t tmpreg = 0U;
+
+ /* Read data register to flush CRC */
+ tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
+
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+
+ hspi->CRCSize--;
+
+ /* check end of the reception */
+ if (hspi->CRCSize == 0U)
+ {
+ /* Disable RXNE and ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+ if (hspi->TxXferCount == 0U)
+ {
+ SPI_CloseRxTx_ISR(hspi);
+ }
+ }
+}
+#endif /* USE_SPI_CRC */
+
+/**
+ * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
+{
+ /* Transmit data in packing Bit mode */
+ if (hspi->TxXferCount >= 2U)
+ {
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount -= 2U;
+ }
+ /* Transmit data in 8 Bit mode */
+ else
+ {
+ *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
+ hspi->TxXferCount--;
+ }
+
+ /* check the end of the transmission */
+ if (hspi->TxXferCount == 0U)
+ {
+#if (USE_SPI_CRC != 0U)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ /* Set CRC Next Bit to send CRC */
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ /* Disable TXE interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
+ return;
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Disable TXE interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
+
+ if (hspi->RxXferCount == 0U)
+ {
+ SPI_CloseRxTx_ISR(hspi);
+ }
+ }
+}
+
+/**
+ * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
+{
+ /* Receive data in 16 Bit mode */
+ *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ hspi->RxXferCount--;
+
+ if (hspi->RxXferCount == 0U)
+ {
+#if (USE_SPI_CRC != 0U)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ hspi->RxISR = SPI_2linesRxISR_16BITCRC;
+ return;
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Disable RXNE interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
+
+ if (hspi->TxXferCount == 0U)
+ {
+ SPI_CloseRxTx_ISR(hspi);
+ }
+ }
+}
+
+#if (USE_SPI_CRC != 0U)
+/**
+ * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
+{
+ /* Receive data in 16 Bit mode */
+ __IO uint16_t tmpreg = 0U;
+
+ /* Read data register to flush CRC */
+ tmpreg = hspi->Instance->DR;
+
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+
+ /* Disable RXNE interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
+
+ SPI_CloseRxTx_ISR(hspi);
+}
+#endif /* USE_SPI_CRC */
+
+/**
+ * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
+{
+ /* Transmit data in 16 Bit mode */
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount--;
+
+ /* Enable CRC Transmission */
+ if (hspi->TxXferCount == 0U)
+ {
+#if (USE_SPI_CRC != 0U)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ /* Set CRC Next Bit to send CRC */
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ /* Disable TXE interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
+ return;
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Disable TXE interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
+
+ if (hspi->RxXferCount == 0U)
+ {
+ SPI_CloseRxTx_ISR(hspi);
+ }
+ }
+}
+
+#if (USE_SPI_CRC != 0U)
+/**
+ * @brief Manage the CRC 8-bit receive in Interrupt context.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
+{
+ __IO uint8_t tmpreg = 0U;
+
+ /* Read data register to flush CRC */
+ tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
+
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+
+ hspi->CRCSize--;
+
+ if (hspi->CRCSize == 0U)
+ {
+ SPI_CloseRx_ISR(hspi);
+ }
+}
+#endif /* USE_SPI_CRC */
+
+/**
+ * @brief Manage the receive 8-bit in Interrupt context.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
+{
+ *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR);
+ hspi->RxXferCount--;
+
+#if (USE_SPI_CRC != 0U)
+ /* Enable CRC Transmission */
+ if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+#endif /* USE_SPI_CRC */
+
+ if (hspi->RxXferCount == 0U)
+ {
+#if (USE_SPI_CRC != 0U)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ hspi->RxISR = SPI_RxISR_8BITCRC;
+ return;
+ }
+#endif /* USE_SPI_CRC */
+ SPI_CloseRx_ISR(hspi);
+ }
+}
+
+#if (USE_SPI_CRC != 0U)
+/**
+ * @brief Manage the CRC 16-bit receive in Interrupt context.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
+{
+ __IO uint16_t tmpreg = 0U;
+
+ /* Read data register to flush CRC */
+ tmpreg = hspi->Instance->DR;
+
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+
+ /* Disable RXNE and ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+ SPI_CloseRx_ISR(hspi);
+}
+#endif /* USE_SPI_CRC */
+
+/**
+ * @brief Manage the 16-bit receive in Interrupt context.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
+{
+ *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ hspi->RxXferCount--;
+
+#if (USE_SPI_CRC != 0U)
+ /* Enable CRC Transmission */
+ if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+#endif /* USE_SPI_CRC */
+
+ if (hspi->RxXferCount == 0U)
+ {
+#if (USE_SPI_CRC != 0U)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ hspi->RxISR = SPI_RxISR_16BITCRC;
+ return;
+ }
+#endif /* USE_SPI_CRC */
+ SPI_CloseRx_ISR(hspi);
+ }
+}
+
+/**
+ * @brief Handle the data 8-bit transmit in Interrupt mode.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
+{
+ *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
+ hspi->TxXferCount--;
+
+ if (hspi->TxXferCount == 0U)
+ {
+#if (USE_SPI_CRC != 0U)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ /* Enable CRC Transmission */
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+#endif /* USE_SPI_CRC */
+ SPI_CloseTx_ISR(hspi);
+ }
+}
+
+/**
+ * @brief Handle the data 16-bit transmit in Interrupt mode.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
+{
+ /* Transmit data in 16 Bit mode */
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount--;
+
+ if (hspi->TxXferCount == 0U)
+ {
+#if (USE_SPI_CRC != 0U)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ /* Enable CRC Transmission */
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+#endif /* USE_SPI_CRC */
+ SPI_CloseTx_ISR(hspi);
+ }
+}
+
+/**
+ * @brief Handle SPI Communication Timeout.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param Flag SPI flag to check
+ * @param State flag state to check
+ * @param Timeout Timeout duration
+ * @param Tickstart tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State,
+ uint32_t Timeout, uint32_t Tickstart)
+{
+ while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
+ {
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) >= Timeout))
+ {
+ /* Disable the SPI and reset the CRC: the CRC value should be cleared
+ on both master and slave sides in order to resynchronize the master
+ and slave for their respective CRC calculation */
+
+ /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
+
+ if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+ {
+ /* Disable SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+ }
+
+ /* Reset CRC Calculation */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle SPI FIFO Communication Timeout.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param Fifo Fifo to check
+ * @param State Fifo state to check
+ * @param Timeout Timeout duration
+ * @param Tickstart tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
+ uint32_t Timeout, uint32_t Tickstart)
+{
+ __IO uint8_t tmpreg;
+
+ while ((hspi->Instance->SR & Fifo) != State)
+ {
+ if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
+ {
+ tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+ }
+
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) >= Timeout))
+ {
+ /* Disable the SPI and reset the CRC: the CRC value should be cleared
+ on both master and slave sides in order to resynchronize the master
+ and slave for their respective CRC calculation */
+
+ /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
+
+ if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+ {
+ /* Disable SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+ }
+
+ /* Reset CRC Calculation */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle the check of the RX transaction complete.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param Timeout Timeout duration
+ * @param Tickstart tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
+{
+ if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+ {
+ /* Disable SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+ }
+
+ /* Control the BSY flag */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ return HAL_TIMEOUT;
+ }
+
+ if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+ {
+ /* Empty the FRLVL fifo */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ return HAL_TIMEOUT;
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle the check of the RXTX or TX transaction complete.
+ * @param hspi SPI handle
+ * @param Timeout Timeout duration
+ * @param Tickstart tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
+{
+ /* Control if the TX fifo is empty */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ return HAL_TIMEOUT;
+ }
+
+ /* Control the BSY flag */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ return HAL_TIMEOUT;
+ }
+
+ /* Control if the RX fifo is empty */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ return HAL_TIMEOUT;
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle the end of the RXTX transaction.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
+{
+ uint32_t tickstart = 0U;
+
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
+
+ /* Disable ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
+
+ /* Check the end of the transaction */
+ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ }
+
+#if (USE_SPI_CRC != 0U)
+ /* Check if CRC error occurred */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ {
+ hspi->State = HAL_SPI_STATE_READY;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ HAL_SPI_ErrorCallback(hspi);
+ }
+ else
+ {
+#endif /* USE_SPI_CRC */
+ if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
+ {
+ if (hspi->State == HAL_SPI_STATE_BUSY_RX)
+ {
+ hspi->State = HAL_SPI_STATE_READY;
+ HAL_SPI_RxCpltCallback(hspi);
+ }
+ else
+ {
+ hspi->State = HAL_SPI_STATE_READY;
+ HAL_SPI_TxRxCpltCallback(hspi);
+ }
+ }
+ else
+ {
+ hspi->State = HAL_SPI_STATE_READY;
+ HAL_SPI_ErrorCallback(hspi);
+ }
+#if (USE_SPI_CRC != 0U)
+ }
+#endif /* USE_SPI_CRC */
+}
+
+/**
+ * @brief Handle the end of the RX transaction.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
+{
+ /* Disable RXNE and ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+ /* Check the end of the transaction */
+ if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ }
+ hspi->State = HAL_SPI_STATE_READY;
+
+#if (USE_SPI_CRC != 0U)
+ /* Check if CRC error occurred */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ HAL_SPI_ErrorCallback(hspi);
+ }
+ else
+ {
+#endif /* USE_SPI_CRC */
+ if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
+ {
+ HAL_SPI_RxCpltCallback(hspi);
+ }
+ else
+ {
+ HAL_SPI_ErrorCallback(hspi);
+ }
+#if (USE_SPI_CRC != 0U)
+ }
+#endif /* USE_SPI_CRC */
+}
+
+/**
+ * @brief Handle the end of the TX transaction.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
+{
+ uint32_t tickstart = 0U;
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ /* Disable TXE and ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
+
+ /* Check the end of the transaction */
+ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ }
+
+ /* Clear overrun flag in 2 Lines communication mode because received is not read */
+ if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
+ {
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ }
+
+ hspi->State = HAL_SPI_STATE_READY;
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ HAL_SPI_ErrorCallback(hspi);
+ }
+ else
+ {
+ HAL_SPI_TxCpltCallback(hspi);
+ }
+}
+
+/**
+ * @brief Handle abort a Rx transaction.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
+{
+ __IO uint32_t count;
+
+ /* Disable SPI Peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
+
+ /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
+ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
+
+ /* Check RXNEIE is disabled */
+ do
+ {
+ if (count-- == 0U)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ break;
+ }
+ }
+ while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
+
+ /* Control the BSY flag */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Empty the FRLVL fifo */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ hspi->State = HAL_SPI_STATE_ABORT;
+}
+
+/**
+ * @brief Handle abort a Tx or Rx/Tx transaction.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
+{
+ __IO uint32_t count;
+
+ count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
+
+ /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
+ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
+
+ /* Check TXEIE is disabled */
+ do
+ {
+ if (count-- == 0U)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ break;
+ }
+ }
+ while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE));
+
+ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Disable SPI Peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* Empty the FRLVL fifo */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ hspi->State = HAL_SPI_STATE_ABORT;
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_spi_ex.c b/Src/stm32f3xx_hal_spi_ex.c
new file mode 100644
index 0000000..367b208
--- /dev/null
+++ b/Src/stm32f3xx_hal_spi_ex.c
@@ -0,0 +1,131 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_spi_ex.c
+ * @author MCD Application Team
+ * @brief Extended SPI HAL module driver.
+ * This file provides firmware functions to manage the following
+ * SPI peripheral extended functionalities :
+ * + IO operation functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SPIEx SPIEx
+ * @brief SPI Extended HAL module driver
+ * @{
+ */
+#ifdef HAL_SPI_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup SPIEx_Private_Constants SPIEx Private Constants
+ * @{
+ */
+#define SPI_FIFO_SIZE 4
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup SPIEx_Exported_Functions SPIEx Exported Functions
+ * @{
+ */
+
+/** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of extended functions to manage the SPI
+ data transfers.
+
+ (#) Rx data flush function:
+ (++) HAL_SPIEx_FlushRxFifo()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Flush the RX fifo.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi)
+{
+ __IO uint32_t tmpreg;
+ uint8_t count = 0U;
+ while ((hspi->Instance->SR & SPI_FLAG_FRLVL) != SPI_FRLVL_EMPTY)
+ {
+ count++;
+ tmpreg = hspi->Instance->DR;
+ UNUSED(tmpreg); /* To avoid GCC warning */
+ if (count == SPI_FIFO_SIZE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_sram.c b/Src/stm32f3xx_hal_sram.c
new file mode 100644
index 0000000..d9c141b
--- /dev/null
+++ b/Src/stm32f3xx_hal_sram.c
@@ -0,0 +1,693 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_sram.c
+ * @author MCD Application Team
+ * @brief SRAM HAL module driver.
+ * This file provides a generic firmware to drive SRAM memories
+ * mounted as external device.
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ This driver is a generic layered driver which contains a set of APIs used to
+ control SRAM memories. It uses the FMC layer functions to interface
+ with SRAM devices.
+ The following sequence should be followed to configure the FMC to interface
+ with SRAM/PSRAM memories:
+
+ (#) Declare a SRAM_HandleTypeDef handle structure, for example:
+ SRAM_HandleTypeDef hsram; and:
+
+ (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
+ values of the structure member.
+
+ (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
+ base register instance for NOR or SRAM device
+
+ (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
+ base register instance for NOR or SRAM extended mode
+
+ (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
+ mode timings; for example:
+ FMC_NORSRAM_TimingTypeDef Timing and FMC_NORSRAM_TimingTypeDef ExTiming;
+ and fill its fields with the allowed values of the structure member.
+
+ (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
+ performs the following sequence:
+
+ (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
+ (##) Control register configuration using the FMC NORSRAM interface function
+ FMC_NORSRAM_Init()
+ (##) Timing register configuration using the FMC NORSRAM interface function
+ FMC_NORSRAM_Timing_Init()
+ (##) Extended mode Timing register configuration using the FMC NORSRAM interface function
+ FMC_NORSRAM_Extended_Timing_Init()
+ (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()
+
+ (#) At this stage you can perform read/write accesses from/to the memory connected
+ to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
+ following APIs:
+ (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
+ (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
+
+ (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
+ HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
+
+ (#) You can continuously monitor the SRAM device HAL state by calling the function
+ HAL_SRAM_GetState()
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+
+/** @defgroup SRAM SRAM
+ * @brief SRAM HAL module driver
+ * @{
+ */
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup SRAM_Exported_Functions SRAM Exported Functions
+ * @{
+ */
+
+/** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions.
+ *
+ @verbatim
+ ==============================================================================
+ ##### SRAM Initialization and de_initialization functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to initialize/de-initialize
+ the SRAM memory
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Performs the SRAM device initialization sequence
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @param Timing Pointer to SRAM control timing structure
+ * @param ExtTiming Pointer to SRAM extended mode timing structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
+{
+ /* Check the SRAM handle parameter */
+ if(hsram == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ if(hsram->State == HAL_SRAM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hsram->Lock = HAL_UNLOCKED;
+
+ /* Initialize the low level hardware (MSP) */
+ HAL_SRAM_MspInit(hsram);
+ }
+
+ /* Initialize SRAM control Interface */
+ FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
+
+ /* Initialize SRAM timing Interface */
+ FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
+
+ /* Initialize SRAM extended mode timing Interface */
+ FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode);
+
+ /* Enable the NORSRAM device */
+ __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Performs the SRAM device De-initialization sequence.
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
+{
+ /* De-Initialize the low level hardware (MSP) */
+ HAL_SRAM_MspDeInit(hsram);
+
+ /* Configure the SRAM registers with their reset values */
+ FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
+
+ hsram->State = HAL_SRAM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsram);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief SRAM MSP Init.
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @retval None
+ */
+__weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsram);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SRAM_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief SRAM MSP DeInit.
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @retval None
+ */
+__weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsram);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SRAM_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DMA transfer complete callback.
+ * @param hdma pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @retval None
+ */
+__weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdma);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DMA transfer complete error callback.
+ * @param hdma pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @retval None
+ */
+__weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdma);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
+ * @brief Input Output and memory control functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### SRAM Input and Output functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to use and control the SRAM memory
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Reads 8-bit buffer from SRAM memory.
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @param pAddress Pointer to read start address
+ * @param pDstBuffer Pointer to destination buffer
+ * @param BufferSize Size of the buffer to read from memory
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
+{
+ __IO uint8_t * psramaddress = (uint8_t *)pAddress;
+
+ /* Process Locked */
+ __HAL_LOCK(hsram);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_BUSY;
+
+ /* Read data from memory */
+ for(; BufferSize != 0U; BufferSize--)
+ {
+ *pDstBuffer = *(__IO uint8_t *)psramaddress;
+ pDstBuffer++;
+ psramaddress++;
+ }
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hsram);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Writes 8-bit buffer to SRAM memory.
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @param pAddress Pointer to write start address
+ * @param pSrcBuffer Pointer to source buffer to write
+ * @param BufferSize Size of the buffer to write to memory
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
+{
+ __IO uint8_t * psramaddress = (uint8_t *)pAddress;
+
+ /* Check the SRAM controller state */
+ if(hsram->State == HAL_SRAM_STATE_PROTECTED)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsram);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_BUSY;
+
+ /* Write data to memory */
+ for(; BufferSize != 0U; BufferSize--)
+ {
+ *(__IO uint8_t *)psramaddress = *pSrcBuffer;
+ pSrcBuffer++;
+ psramaddress++;
+ }
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hsram);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Reads 16-bit buffer from SRAM memory.
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @param pAddress Pointer to read start address
+ * @param pDstBuffer Pointer to destination buffer
+ * @param BufferSize Size of the buffer to read from memory
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
+{
+ __IO uint16_t * psramaddress = (uint16_t *)pAddress;
+
+ /* Process Locked */
+ __HAL_LOCK(hsram);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_BUSY;
+
+ /* Read data from memory */
+ for(; BufferSize != 0U; BufferSize--)
+ {
+ *pDstBuffer = *(__IO uint16_t *)psramaddress;
+ pDstBuffer++;
+ psramaddress++;
+ }
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hsram);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Writes 16-bit buffer to SRAM memory.
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @param pAddress Pointer to write start address
+ * @param pSrcBuffer Pointer to source buffer to write
+ * @param BufferSize Size of the buffer to write to memory
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
+{
+ __IO uint16_t * psramaddress = (uint16_t *)pAddress;
+
+ /* Check the SRAM controller state */
+ if(hsram->State == HAL_SRAM_STATE_PROTECTED)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsram);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_BUSY;
+
+ /* Write data to memory */
+ for(; BufferSize != 0U; BufferSize--)
+ {
+ *(__IO uint16_t *)psramaddress = *pSrcBuffer;
+ pSrcBuffer++;
+ psramaddress++;
+ }
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hsram);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Reads 32-bit buffer from SRAM memory.
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @param pAddress Pointer to read start address
+ * @param pDstBuffer Pointer to destination buffer
+ * @param BufferSize Size of the buffer to read from memory
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
+{
+ /* Process Locked */
+ __HAL_LOCK(hsram);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_BUSY;
+
+ /* Read data from memory */
+ for(; BufferSize != 0U; BufferSize--)
+ {
+ *pDstBuffer = *(__IO uint32_t *)pAddress;
+ pDstBuffer++;
+ pAddress++;
+ }
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hsram);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Writes 32-bit buffer to SRAM memory.
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @param pAddress Pointer to write start address
+ * @param pSrcBuffer Pointer to source buffer to write
+ * @param BufferSize Size of the buffer to write to memory
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
+{
+ /* Check the SRAM controller state */
+ if(hsram->State == HAL_SRAM_STATE_PROTECTED)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsram);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_BUSY;
+
+ /* Write data to memory */
+ for(; BufferSize != 0U; BufferSize--)
+ {
+ *(__IO uint32_t *)pAddress = *pSrcBuffer;
+ pSrcBuffer++;
+ pAddress++;
+ }
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hsram);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Reads a Words data from the SRAM memory using DMA transfer.
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @param pAddress Pointer to read start address
+ * @param pDstBuffer Pointer to destination buffer
+ * @param BufferSize Size of the buffer to read from memory
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
+{
+ /* Process Locked */
+ __HAL_LOCK(hsram);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_BUSY;
+
+ /* Configure DMA user callbacks */
+ hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
+ hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
+
+ /* Enable the DMA Channel */
+ HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hsram);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Writes a Words data buffer to SRAM memory using DMA transfer.
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @param pAddress Pointer to write start address
+ * @param pSrcBuffer Pointer to source buffer to write
+ * @param BufferSize Size of the buffer to write to memory
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
+{
+ /* Check the SRAM controller state */
+ if(hsram->State == HAL_SRAM_STATE_PROTECTED)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsram);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_BUSY;
+
+ /* Configure DMA user callbacks */
+ hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
+ hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
+
+ /* Enable the DMA Channel */
+ HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hsram);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SRAM_Exported_Functions_Group3 Control functions
+ * @brief Control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### SRAM Control functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control dynamically
+ the SRAM interface.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables dynamically SRAM write operation.
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
+{
+ /* Process Locked */
+ __HAL_LOCK(hsram);
+
+ /* Enable write operation */
+ FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hsram);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables dynamically SRAM write operation.
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
+{
+ /* Process Locked */
+ __HAL_LOCK(hsram);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_BUSY;
+
+ /* Disable write operation */
+ FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_PROTECTED;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hsram);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### SRAM State functions #####
+ ==============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the SRAM controller
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns the SRAM controller state
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @retval HAL state
+ */
+HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
+{
+ return hsram->State;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_tim.c b/Src/stm32f3xx_hal_tim.c
new file mode 100644
index 0000000..c85cb3b
--- /dev/null
+++ b/Src/stm32f3xx_hal_tim.c
@@ -0,0 +1,5516 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_tim.c
+ * @author MCD Application Team
+ * @brief TIM HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Timer (TIM) peripheral:
+ * + Time Base Initialization
+ * + Time Base Start
+ * + Time Base Start Interruption
+ * + Time Base Start DMA
+ * + Time Output Compare/PWM Initialization
+ * + Time Output Compare/PWM Channel Configuration
+ * + Time Output Compare/PWM Start
+ * + Time Output Compare/PWM Start Interruption
+ * + Time Output Compare/PWM Start DMA
+ * + Time Input Capture Initialization
+ * + Time Input Capture Channel Configuration
+ * + Time Input Capture Start
+ * + Time Input Capture Start Interruption
+ * + Time Input Capture Start DMA
+ * + Time One Pulse Initialization
+ * + Time One Pulse Channel Configuration
+ * + Time One Pulse Start
+ * + Time Encoder Interface Initialization
+ * + Time Encoder Interface Start
+ * + Time Encoder Interface Start Interruption
+ * + Time Encoder Interface Start DMA
+ * + Commutation Event configuration with Interruption and DMA
+ * + Time OCRef clear configuration
+ * + Time External Clock configuration
+ @verbatim
+ ==============================================================================
+ ##### TIMER Generic features #####
+ ==============================================================================
+ [..] The Timer features include:
+ (#) 16-bit up, down, up/down auto-reload counter.
+ (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
+ counter clock frequency either by any factor between 1 and 65536.
+ (#) Up to 4 independent channels for:
+ (++) Input Capture
+ (++) Output Compare
+ (++) PWM generation (Edge and Center-aligned Mode)
+ (++) One-pulse mode output
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Initialize the TIM low level resources by implementing the following functions
+ depending from feature used :
+ (++) Time Base : HAL_TIM_Base_MspInit()
+ (++) Input Capture : HAL_TIM_IC_MspInit()
+ (++) Output Compare : HAL_TIM_OC_MspInit()
+ (++) PWM generation : HAL_TIM_PWM_MspInit()
+ (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
+ (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
+
+ (#) Initialize the TIM low level resources :
+ (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE ();
+ (##) TIM pins configuration
+ (+++) Enable the clock for the TIM GPIOs using the following function:
+ __HAL_RCC_GPIOx_CLK_ENABLE();
+ (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
+
+ (#) The external Clock can be configured, if needed (the default clock is the
+ internal clock from the APBx), using the following function:
+ HAL_TIM_ConfigClockSource, the clock configuration should be done before
+ any start function.
+
+ (#) Configure the TIM in the desired functioning mode using one of the
+ Initialization function of this driver:
+ (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
+ (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
+ Output Compare signal.
+ (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
+ PWM signal.
+ (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
+ external signal.
+ (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
+ in One Pulse Mode.
+ (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
+
+ (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
+ (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
+ (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
+ (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
+ (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
+ (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
+ (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
+
+ (#) The DMA Burst is managed with the two following functions:
+ HAL_TIM_DMABurst_WriteStart()
+ HAL_TIM_DMABurst_ReadStart()
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup TIM TIM
+ * @brief TIM HAL module driver
+ * @{
+ */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/** @defgroup TIM_Private_Functions TIM Private Functions
+ * @{
+ */
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter);
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter);
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter);
+static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource);
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
+static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+ TIM_SlaveConfigTypeDef * sSlaveConfig);
+
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup TIM_Exported_Functions TIM Exported Functions
+ * @{
+ */
+
+/** @defgroup TIM_Exported_Functions_Group1 Time Base functions
+ * @brief Time Base functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Time Base functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM base.
+ (+) De-initialize the TIM base.
+ (+) Start the Time Base.
+ (+) Stop the Time Base.
+ (+) Start the Time Base and enable interrupt.
+ (+) Stop the Time Base and disable interrupt.
+ (+) Start the Time Base and enable DMA transfer.
+ (+) Stop the Time Base and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM Time base Unit according to the specified
+ * parameters in the TIM_HandleTypeDef and create the associated handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
+ * @param htim TIM Base handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
+{
+ /* Check the TIM handle allocation */
+ if(htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+ if(htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ HAL_TIM_Base_MspInit(htim);
+ }
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Set the Time Base configuration */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Initialize the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM Base peripheral
+ * @param htim TIM Base handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_TIM_Base_MspDeInit(htim);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Base MSP.
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_Base_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM Base MSP.
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_Base_MspDeInit could be implemented in the user file
+ */
+}
+
+
+/**
+ * @brief Starts the TIM Base generation.
+ * @param htim TIM handle
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Change the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Base generation.
+ * @param htim TIM handle
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Base generation in interrupt mode.
+ * @param htim TIM handle
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ /* Enable the TIM Update interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Base generation in interrupt mode.
+ * @param htim TIM handle
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ /* Disable the TIM Update interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Base generation in DMA mode.
+ * @param htim TIM handle
+ * @param pData The source Buffer address.
+ * @param Length The length of data to be transferred from memory to peripheral.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if((pData == 0U ) && (Length > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
+
+ /* Enable the TIM Update DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Base generation in DMA mode.
+ * @param htim TIM handle
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+
+ /* Disable the TIM Update DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
+ * @brief Time Output Compare functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Time Output Compare functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM Output Compare.
+ (+) De-initialize the TIM Output Compare.
+ (+) Start the Time Output Compare.
+ (+) Stop the Time Output Compare.
+ (+) Start the Time Output Compare and enable interrupt.
+ (+) Stop the Time Output Compare and disable interrupt.
+ (+) Start the Time Output Compare and enable DMA transfer.
+ (+) Stop the Time Output Compare and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM Output Compare according to the specified
+ * parameters in the TIM_HandleTypeDef and create the associated handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
+ * @param htim TIM Output Compare handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
+{
+ /* Check the TIM handle allocation */
+ if(htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+ if(htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_OC_MspInit(htim);
+ }
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Init the base time for the Output Compare */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Initialize the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM peripheral
+ * @param htim TIM Output Compare handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_OC_MspDeInit(htim);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Output Compare MSP.
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_OC_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM Output Compare MSP.
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_OC_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the TIM Output Compare signal generation.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Enable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation.
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Disable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Output Compare signal generation in interrupt mode.
+ * @param htim TIM OC handle
+ * @param Channel TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Enable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Enable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation in interrupt mode.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Output Compare signal generation in DMA mode.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param pData The source Buffer address.
+ * @param Length The length of data to be transferred from memory to TIM peripheral
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if(((uint32_t)pData == 0U ) && (Length > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
+
+ /* Enable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
+
+ /* Enable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
+
+ /* Enable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
+
+ /* Enable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation in DMA mode.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
+ * @brief Time PWM functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Time PWM functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM OPWM.
+ (+) De-initialize the TIM PWM.
+ (+) Start the Time PWM.
+ (+) Stop the Time PWM.
+ (+) Start the Time PWM and enable interrupt.
+ (+) Stop the Time PWM and disable interrupt.
+ (+) Start the Time PWM and enable DMA transfer.
+ (+) Stop the Time PWM and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM PWM Time Base according to the specified
+ * parameters in the TIM_HandleTypeDef and create the associated handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
+ * @param htim TIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
+{
+ /* Check the TIM handle allocation */
+ if(htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+ if(htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_PWM_MspInit(htim);
+ }
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Init the base time for the PWM */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Initialize the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM peripheral
+ * @param htim TIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_PWM_MspDeInit(htim);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM PWM MSP.
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_PWM_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM PWM MSP.
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_PWM_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the PWM signal generation.
+ * @param htim TIM handle
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the PWM signal generation.
+ * @param htim TIM handle
+ * @param Channel TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Disable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the PWM signal generation in interrupt mode.
+ * @param htim TIM handle
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Enable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Enable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the PWM signal generation in interrupt mode.
+ * @param htim TIM handle
+ * @param Channel TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM PWM signal generation in DMA mode.
+ * @param htim TIM handle
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param pData The source Buffer address.
+ * @param Length The length of data to be transferred from memory to TIM peripheral
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if(((uint32_t)pData == 0U ) && (Length > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
+
+ /* Enable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
+
+ /* Enable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
+
+ /* Enable the TIM Output Capture/Compare 3 request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
+
+ /* Enable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM PWM signal generation in DMA mode.
+ * @param htim TIM handle
+ * @param Channel TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
+ * @brief Time Input Capture functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Time Input Capture functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM Input Capture.
+ (+) De-initialize the TIM Input Capture.
+ (+) Start the Time Input Capture.
+ (+) Stop the Time Input Capture.
+ (+) Start the Time Input Capture and enable interrupt.
+ (+) Stop the Time Input Capture and disable interrupt.
+ (+) Start the Time Input Capture and enable DMA transfer.
+ (+) Stop the Time Input Capture and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM Input Capture Time base according to the specified
+ * parameters in the TIM_HandleTypeDef and create the associated handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
+ * @param htim TIM Input Capture handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
+{
+ /* Check the TIM handle allocation */
+ if(htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+ if(htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_IC_MspInit(htim);
+ }
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Init the base time for the input capture */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Initialize the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM peripheral
+ * @param htim TIM Input Capture handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_IC_MspDeInit(htim);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Input Capture MSP.
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_IC_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM Input Capture MSP.
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_IC_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the TIM Input Capture measurement.
+ * @param htim TIM Input Capture handle
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Enable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Input Capture measurement.
+ * @param htim TIM handle
+ * @param Channel TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Disable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Input Capture measurement in interrupt mode.
+ * @param htim TIM Input Capture handle
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Enable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Enable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+ /* Enable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Input Capture measurement in interrupt mode.
+ * @param htim TIM handle
+ * @param Channel TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Input Capture measurement in DMA mode.
+ * @param htim TIM Input Capture handle
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param pData The destination Buffer address.
+ * @param Length The length of data to be transferred from TIM peripheral to memory.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if((pData == 0U ) && (Length > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
+
+ /* Enable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
+
+ /* Enable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
+
+ /* Enable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
+
+ /* Enable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Input Capture measurement in DMA mode.
+ * @param htim TIM Input Capture handle
+ * @param Channel TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
+ * @brief Time One Pulse functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Time One Pulse functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM One Pulse.
+ (+) De-initialize the TIM One Pulse.
+ (+) Start the Time One Pulse.
+ (+) Stop the Time One Pulse.
+ (+) Start the Time One Pulse and enable interrupt.
+ (+) Stop the Time One Pulse and disable interrupt.
+ (+) Start the Time One Pulse and enable DMA transfer.
+ (+) Stop the Time One Pulse and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM One Pulse Time Base according to the specified
+ * parameters in the TIM_HandleTypeDef and create the associated handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
+ * @param htim TIM OnePulse handle
+ * @param OnePulseMode Select the One pulse mode.
+ * This parameter can be one of the following values:
+ * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
+ * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
+{
+ /* Check the TIM handle allocation */
+ if(htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_OPM_MODE(OnePulseMode));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+ if(htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_OnePulse_MspInit(htim);
+ }
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Configure the Time base in the One Pulse Mode */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Reset the OPM Bit */
+ htim->Instance->CR1 &= ~TIM_CR1_OPM;
+
+ /* Configure the OPM Mode */
+ htim->Instance->CR1 |= OnePulseMode;
+
+ /* Initialize the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM One Pulse
+ * @param htim TIM One Pulse handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_TIM_OnePulse_MspDeInit(htim);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM One Pulse MSP.
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_OnePulse_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM One Pulse MSP.
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the TIM One Pulse signal generation.
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ /* Enable the Capture compare and the Input Capture channels
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+
+ No need to enable the counter, it's enabled automatically by hardware
+ (the counter starts in response to a stimulus and generate a pulse */
+
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM One Pulse signal generation.
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel TIM Channels to be disable
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ /* Disable the Capture compare and the Input Capture channels
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM One Pulse signal generation in interrupt mode.
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ /* Enable the Capture compare and the Input Capture channels
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+
+ No need to enable the counter, it's enabled automatically by hardware
+ (the counter starts in response to a stimulus and generate a pulse */
+
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM One Pulse signal generation in interrupt mode.
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+
+ /* Disable the Capture compare and the Input Capture channels
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
+ * @brief Time Encoder functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Time Encoder functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM Encoder.
+ (+) De-initialize the TIM Encoder.
+ (+) Start the Time Encoder.
+ (+) Stop the Time Encoder.
+ (+) Start the Time Encoder and enable interrupt.
+ (+) Stop the Time Encoder and disable interrupt.
+ (+) Start the Time Encoder and enable DMA transfer.
+ (+) Stop the Time Encoder and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM Encoder Interface and create the associated handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
+ * @param htim TIM Encoder Interface handle
+ * @param sConfig TIM Encoder Interface configuration structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig)
+{
+ uint32_t tmpsmcr = 0U;
+ uint32_t tmpccmr1 = 0U;
+ uint32_t tmpccer = 0U;
+
+ /* Check the TIM handle allocation */
+ if(htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+ assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
+ assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
+ assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
+ assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
+ assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
+ assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+ assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
+
+ if(htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_Encoder_MspInit(htim);
+ }
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Reset the SMS bits */
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+
+ /* Configure the Time base in the Encoder Mode */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = htim->Instance->SMCR;
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = htim->Instance->CCMR1;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = htim->Instance->CCER;
+
+ /* Set the encoder Mode */
+ tmpsmcr |= sConfig->EncoderMode;
+
+ /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+ tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
+ tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
+
+ /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
+ tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
+ tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
+ tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
+ tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
+
+ /* Set the TI1 and the TI2 Polarities */
+ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
+ tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
+ tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
+
+ /* Write to TIMx SMCR */
+ htim->Instance->SMCR = tmpsmcr;
+
+ /* Write to TIMx CCMR1 */
+ htim->Instance->CCMR1 = tmpccmr1;
+
+ /* Write to TIMx CCER */
+ htim->Instance->CCER = tmpccer;
+
+ /* Initialize the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief DeInitializes the TIM Encoder interface
+ * @param htim TIM Encoder handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_TIM_Encoder_MspDeInit(htim);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Encoder Interface MSP.
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_Encoder_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM Encoder Interface MSP.
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the TIM Encoder Interface.
+ * @param htim TIM Encoder Interface handle
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Enable the encoder interface channels */
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ break;
+ }
+ case TIM_CHANNEL_2:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ break;
+ }
+ default :
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ break;
+ }
+ }
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Encoder Interface.
+ * @param htim TIM Encoder Interface handle
+ * @param Channel TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channels 1 and 2
+ (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ break;
+ }
+ case TIM_CHANNEL_2:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ break;
+ }
+ default :
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ break;
+ }
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Encoder Interface in interrupt mode.
+ * @param htim TIM Encoder Interface handle
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Enable the encoder interface channels */
+ /* Enable the capture compare Interrupts 1 and/or 2U */
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ break;
+ }
+ case TIM_CHANNEL_2:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+ default :
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+ }
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Encoder Interface in interrupt mode.
+ * @param htim TIM Encoder Interface handle
+ * @param Channel TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channels 1 and 2
+ (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+ if(Channel == TIM_CHANNEL_1)
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare Interrupts 1U */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ }
+ else if(Channel == TIM_CHANNEL_2)
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare Interrupts 2U */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ }
+ else
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare Interrupts 1 and 2U */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Encoder Interface in DMA mode.
+ * @param htim TIM Encoder Interface handle
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @param pData1: The destination Buffer address for IC1.
+ * @param pData2: The destination Buffer address for IC2.
+ * @param Length The length of data to be transferred from TIM peripheral to memory.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if((((pData1 == 0U) || (pData2 == 0U) )) && (Length > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
+
+ /* Enable the TIM Input Capture DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
+
+ /* Enable the TIM Input Capture DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ }
+ break;
+
+ case TIM_CHANNEL_ALL:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
+
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+ /* Enable the TIM Input Capture DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ /* Enable the TIM Input Capture DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ default:
+ break;
+ }
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Encoder Interface in DMA mode.
+ * @param htim TIM Encoder Interface handle
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channels 1 and 2
+ (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+ if(Channel == TIM_CHANNEL_1)
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare DMA Request 1U */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ else if(Channel == TIM_CHANNEL_2)
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare DMA Request 2U */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ else
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare DMA Request 1 and 2U */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
+ * @brief IRQ handler management
+ *
+@verbatim
+ ==============================================================================
+ ##### IRQ handler management #####
+ ==============================================================================
+ [..]
+ This section provides Timer IRQ handler function.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief This function handles TIM interrupts requests.
+ * @param htim TIM handle
+ * @retval None
+ */
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
+{
+ /* Capture compare 1 event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
+ {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
+ {
+ {
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+
+ /* Input capture event */
+ if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
+ {
+ HAL_TIM_IC_CaptureCallback(htim);
+ }
+ /* Output compare event */
+ else
+ {
+ HAL_TIM_OC_DelayElapsedCallback(htim);
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+ }
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ }
+ }
+ }
+ /* Capture compare 2 event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
+ {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
+ {
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ /* Input capture event */
+ if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
+ {
+ HAL_TIM_IC_CaptureCallback(htim);
+ }
+ /* Output compare event */
+ else
+ {
+ HAL_TIM_OC_DelayElapsedCallback(htim);
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+ }
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ }
+ }
+ /* Capture compare 3 event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
+ {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
+ {
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ /* Input capture event */
+ if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
+ {
+ HAL_TIM_IC_CaptureCallback(htim);
+ }
+ /* Output compare event */
+ else
+ {
+ HAL_TIM_OC_DelayElapsedCallback(htim);
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+ }
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ }
+ }
+ /* Capture compare 4 event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
+ {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
+ {
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ /* Input capture event */
+ if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
+ {
+ HAL_TIM_IC_CaptureCallback(htim);
+ }
+ /* Output compare event */
+ else
+ {
+ HAL_TIM_OC_DelayElapsedCallback(htim);
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+ }
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ }
+ }
+ /* TIM Update event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
+ {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
+ {
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
+ HAL_TIM_PeriodElapsedCallback(htim);
+ }
+ }
+ /* TIM Break input event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
+ {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
+ {
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK);
+ HAL_TIMEx_BreakCallback(htim);
+ }
+ }
+
+#if defined(TIM_FLAG_BREAK2)
+ /* TIM Break input 2 event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
+ {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
+ {
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
+ HAL_TIMEx_Break2Callback(htim);
+ }
+ }
+#endif
+
+ /* TIM Trigger detection event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
+ {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
+ {
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
+ HAL_TIM_TriggerCallback(htim);
+ }
+ }
+ /* TIM commutation event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
+ {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
+ {
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
+ HAL_TIMEx_CommutationCallback(htim);
+ }
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
+ (+) Configure External Clock source.
+ (+) Configure Complementary channels, break features and dead time.
+ (+) Configure Master and the Slave synchronization.
+ (+) Configure the DMA Burst Mode.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the TIM Output Compare Channels according to the specified
+ * parameters in the TIM_OC_InitTypeDef.
+ * @param htim TIM Output Compare handle
+ * @param sConfig TIM Output Compare configuration structure
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CHANNELS(Channel));
+ assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
+ assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+
+ /* Check input state */
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ /* Configure the TIM Channel 1 in Output Compare */
+ TIM_OC1_SetConfig(htim->Instance, sConfig);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ /* Configure the TIM Channel 2 in Output Compare */
+ TIM_OC2_SetConfig(htim->Instance, sConfig);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+ /* Configure the TIM Channel 3 in Output Compare */
+ TIM_OC3_SetConfig(htim->Instance, sConfig);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+ /* Configure the TIM Channel 4 in Output Compare */
+ TIM_OC4_SetConfig(htim->Instance, sConfig);
+ }
+ break;
+
+ default:
+ break;
+ }
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Input Capture Channels according to the specified
+ * parameters in the TIM_IC_InitTypeDef.
+ * @param htim TIM IC handle
+ * @param sConfig TIM Input Capture configuration structure
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
+ assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
+ assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
+
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ if (Channel == TIM_CHANNEL_1)
+ {
+ /* TI1 Configuration */
+ TIM_TI1_SetConfig(htim->Instance,
+ sConfig->ICPolarity,
+ sConfig->ICSelection,
+ sConfig->ICFilter);
+
+ /* Reset the IC1PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+
+ /* Set the IC1PSC value */
+ htim->Instance->CCMR1 |= sConfig->ICPrescaler;
+ }
+ else if (Channel == TIM_CHANNEL_2)
+ {
+ /* TI2 Configuration */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ TIM_TI2_SetConfig(htim->Instance,
+ sConfig->ICPolarity,
+ sConfig->ICSelection,
+ sConfig->ICFilter);
+
+ /* Reset the IC2PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
+
+ /* Set the IC2PSC value */
+ htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
+ }
+ else if (Channel == TIM_CHANNEL_3)
+ {
+ /* TI3 Configuration */
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+ TIM_TI3_SetConfig(htim->Instance,
+ sConfig->ICPolarity,
+ sConfig->ICSelection,
+ sConfig->ICFilter);
+
+ /* Reset the IC3PSC Bits */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
+
+ /* Set the IC3PSC value */
+ htim->Instance->CCMR2 |= sConfig->ICPrescaler;
+ }
+ else
+ {
+ /* TI4 Configuration */
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+ TIM_TI4_SetConfig(htim->Instance,
+ sConfig->ICPolarity,
+ sConfig->ICSelection,
+ sConfig->ICFilter);
+
+ /* Reset the IC4PSC Bits */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
+
+ /* Set the IC4PSC value */
+ htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
+ }
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM PWM channels according to the specified
+ * parameters in the TIM_OC_InitTypeDef.
+ * @param htim TIM handle
+ * @param sConfig TIM PWM configuration structure
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
+{
+ __HAL_LOCK(htim);
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CHANNELS(Channel));
+ assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
+ assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+ assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ /* Configure the Channel 1 in PWM mode */
+ TIM_OC1_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel1 */
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
+ htim->Instance->CCMR1 |= sConfig->OCFastMode;
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ /* Configure the Channel 2 in PWM mode */
+ TIM_OC2_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel2 */
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
+ htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+ /* Configure the Channel 3 in PWM mode */
+ TIM_OC3_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel3 */
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
+ htim->Instance->CCMR2 |= sConfig->OCFastMode;
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+ /* Configure the Channel 4 in PWM mode */
+ TIM_OC4_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel4 */
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
+ htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM One Pulse Channels according to the specified
+ * parameters in the TIM_OnePulse_InitTypeDef.
+ * @param htim TIM One Pulse handle
+ * @param sConfig TIM One Pulse configuration structure
+ * @param OutputChannel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @param InputChannel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel)
+{
+ TIM_OC_InitTypeDef temp1;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
+ assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
+
+ if(OutputChannel != InputChannel)
+ {
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Extract the Ouput compare configuration from sConfig structure */
+ temp1.OCMode = sConfig->OCMode;
+ temp1.Pulse = sConfig->Pulse;
+ temp1.OCPolarity = sConfig->OCPolarity;
+ temp1.OCNPolarity = sConfig->OCNPolarity;
+ temp1.OCIdleState = sConfig->OCIdleState;
+ temp1.OCNIdleState = sConfig->OCNIdleState;
+
+ switch (OutputChannel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+ TIM_OC1_SetConfig(htim->Instance, &temp1);
+ }
+ break;
+ case TIM_CHANNEL_2:
+ {
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ TIM_OC2_SetConfig(htim->Instance, &temp1);
+ }
+ break;
+ default:
+ break;
+ }
+ switch (InputChannel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+ TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
+ sConfig->ICSelection, sConfig->ICFilter);
+
+ /* Reset the IC1PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+
+ /* Select the Trigger source */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= TIM_TS_TI1FP1;
+
+ /* Select the Slave Mode */
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+ htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+ }
+ break;
+ case TIM_CHANNEL_2:
+ {
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
+ sConfig->ICSelection, sConfig->ICFilter);
+
+ /* Reset the IC2PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
+
+ /* Select the Trigger source */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= TIM_TS_TI2FP2;
+
+ /* Select the Slave Mode */
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+ htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
+ * @param htim TIM handle
+ * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
+ * This parameter can be one of the following values:
+ * @arg TIM_DMABASE_CR1
+ * @arg TIM_DMABASE_CR2
+ * @arg TIM_DMABASE_SMCR
+ * @arg TIM_DMABASE_DIER
+ * @arg TIM_DMABASE_SR
+ * @arg TIM_DMABASE_EGR
+ * @arg TIM_DMABASE_CCMR1
+ * @arg TIM_DMABASE_CCMR2
+ * @arg TIM_DMABASE_CCER
+ * @arg TIM_DMABASE_CNT
+ * @arg TIM_DMABASE_PSC
+ * @arg TIM_DMABASE_ARR
+ * @arg TIM_DMABASE_RCR
+ * @arg TIM_DMABASE_CCR1
+ * @arg TIM_DMABASE_CCR2
+ * @arg TIM_DMABASE_CCR3
+ * @arg TIM_DMABASE_CCR4
+ * @arg TIM_DMABASE_BDTR
+ * @arg TIM_DMABASE_DCR
+ * @param BurstRequestSrc TIM DMA Request sources
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: TIM update Interrupt source
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+ * @arg TIM_DMA_COM: TIM Commutation DMA source
+ * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+ * @param BurstBuffer The Buffer address.
+ * @param BurstLength DMA Burst length. This parameter can be one value
+ * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
+ uint32_t *BurstBuffer, uint32_t BurstLength)
+{
+return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, ((BurstLength) >> 8U) + 1U);
+}
+
+/**
+ * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
+ * @param htim TIM handle
+ * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
+ * This parameter can be one of the following values:
+ * @arg TIM_DMABASE_CR1
+ * @arg TIM_DMABASE_CR2
+ * @arg TIM_DMABASE_SMCR
+ * @arg TIM_DMABASE_DIER
+ * @arg TIM_DMABASE_SR
+ * @arg TIM_DMABASE_EGR
+ * @arg TIM_DMABASE_CCMR1
+ * @arg TIM_DMABASE_CCMR2
+ * @arg TIM_DMABASE_CCER
+ * @arg TIM_DMABASE_CNT
+ * @arg TIM_DMABASE_PSC
+ * @arg TIM_DMABASE_ARR
+ * @arg TIM_DMABASE_RCR
+ * @arg TIM_DMABASE_CCR1
+ * @arg TIM_DMABASE_CCR2
+ * @arg TIM_DMABASE_CCR3
+ * @arg TIM_DMABASE_CCR4
+ * @arg TIM_DMABASE_BDTR
+ * @arg TIM_DMABASE_DCR
+ * @param BurstRequestSrc TIM DMA Request sources
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: TIM update Interrupt source
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+ * @arg TIM_DMA_COM: TIM Commutation DMA source
+ * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+ * @param BurstBuffer The Buffer address.
+ * @param BurstLength DMA Burst length. This parameter can be one value
+ * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+ * @param DataLength Data length. This parameter can be one value
+ * between 1 and 0xFFFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
+ uint32_t* BurstBuffer, uint32_t BurstLength, uint32_t DataLength)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+ assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+ assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if((BurstBuffer == 0U ) && (BurstLength > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ switch(BurstRequestSrc)
+ {
+ case TIM_DMA_UPDATE:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
+ }
+ break;
+ case TIM_DMA_CC1:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
+ }
+ break;
+ case TIM_DMA_CC2:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
+ }
+ break;
+ case TIM_DMA_CC3:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
+ }
+ break;
+ case TIM_DMA_CC4:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
+ }
+ break;
+ case TIM_DMA_COM:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
+ }
+ break;
+ case TIM_DMA_TRIGGER:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
+ }
+ break;
+ default:
+ break;
+ }
+ /* configure the DMA Burst Mode */
+ htim->Instance->DCR = BurstBaseAddress | BurstLength;
+
+ /* Enable the TIM DMA Request */
+ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM DMA Burst mode
+ * @param htim TIM handle
+ * @param BurstRequestSrc TIM DMA Request sources to disable
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+
+ /* Abort the DMA transfer (at least disable the DMA channel) */
+ switch(BurstRequestSrc)
+ {
+ case TIM_DMA_UPDATE:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
+ }
+ break;
+ case TIM_DMA_CC1:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
+ }
+ break;
+ case TIM_DMA_CC2:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
+ }
+ break;
+ case TIM_DMA_CC3:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
+ }
+ break;
+ case TIM_DMA_CC4:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
+ }
+ break;
+ case TIM_DMA_COM:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+ }
+ break;
+ case TIM_DMA_TRIGGER:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* Disable the TIM Update DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
+ * @param htim TIM handle
+ * @param BurstBaseAddress TIM Base address from where the DMA will starts the Data read
+ * This parameter can be one of the following values:
+ * @arg TIM_DMABASE_CR1
+ * @arg TIM_DMABASE_CR2
+ * @arg TIM_DMABASE_SMCR
+ * @arg TIM_DMABASE_DIER
+ * @arg TIM_DMABASE_SR
+ * @arg TIM_DMABASE_EGR
+ * @arg TIM_DMABASE_CCMR1
+ * @arg TIM_DMABASE_CCMR2
+ * @arg TIM_DMABASE_CCER
+ * @arg TIM_DMABASE_CNT
+ * @arg TIM_DMABASE_PSC
+ * @arg TIM_DMABASE_ARR
+ * @arg TIM_DMABASE_RCR
+ * @arg TIM_DMABASE_CCR1
+ * @arg TIM_DMABASE_CCR2
+ * @arg TIM_DMABASE_CCR3
+ * @arg TIM_DMABASE_CCR4
+ * @arg TIM_DMABASE_BDTR
+ * @arg TIM_DMABASE_DCR
+ * @param BurstRequestSrc TIM DMA Request sources
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: TIM update Interrupt source
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+ * @arg TIM_DMA_COM: TIM Commutation DMA source
+ * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+ * @param BurstBuffer The Buffer address.
+ * @param BurstLength DMA Burst length. This parameter can be one value
+ * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
+ uint32_t *BurstBuffer, uint32_t BurstLength)
+{
+return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, ((BurstLength) >> 8U) + 1U);
+}
+
+/**
+ * @brief Configure the DMA Burst to transfer multiple Data from the TIM peripheral to the memory
+ * @param htim TIM handle
+ * @param BurstBaseAddress TIM Base address from where the DMA will starts the Data read
+ * This parameter can be one of the following values:
+ * @arg TIM_DMABASE_CR1
+ * @arg TIM_DMABASE_CR2
+ * @arg TIM_DMABASE_SMCR
+ * @arg TIM_DMABASE_DIER
+ * @arg TIM_DMABASE_SR
+ * @arg TIM_DMABASE_EGR
+ * @arg TIM_DMABASE_CCMR1
+ * @arg TIM_DMABASE_CCMR2
+ * @arg TIM_DMABASE_CCER
+ * @arg TIM_DMABASE_CNT
+ * @arg TIM_DMABASE_PSC
+ * @arg TIM_DMABASE_ARR
+ * @arg TIM_DMABASE_RCR
+ * @arg TIM_DMABASE_CCR1
+ * @arg TIM_DMABASE_CCR2
+ * @arg TIM_DMABASE_CCR3
+ * @arg TIM_DMABASE_CCR4
+ * @arg TIM_DMABASE_BDTR
+ * @arg TIM_DMABASE_DCR
+ * @param BurstRequestSrc TIM DMA Request sources
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: TIM update Interrupt source
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+ * @arg TIM_DMA_COM: TIM Commutation DMA source
+ * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+ * @param BurstBuffer The Buffer address.
+ * @param BurstLength DMA Burst length. This parameter can be one value
+ * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+ * @param DataLength Data length. This parameter can be one value
+ * between 1 and 0xFFFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
+ uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+ assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+ assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if((BurstBuffer == 0U ) && (BurstLength > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ switch(BurstRequestSrc)
+ {
+ case TIM_DMA_UPDATE:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
+ }
+ break;
+ case TIM_DMA_CC1:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
+ }
+ break;
+ case TIM_DMA_CC2:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
+ }
+ break;
+ case TIM_DMA_CC3:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
+ }
+ break;
+ case TIM_DMA_CC4:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
+ }
+ break;
+ case TIM_DMA_COM:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
+ }
+ break;
+ case TIM_DMA_TRIGGER:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* configure the DMA Burst Mode */
+ htim->Instance->DCR = BurstBaseAddress | BurstLength;
+
+ /* Enable the TIM DMA Request */
+ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the DMA burst reading
+ * @param htim TIM handle
+ * @param BurstRequestSrc TIM DMA Request sources to disable.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+
+ /* Abort the DMA transfer (at least disable the DMA channel) */
+ switch(BurstRequestSrc)
+ {
+ case TIM_DMA_UPDATE:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
+ }
+ break;
+ case TIM_DMA_CC1:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
+ }
+ break;
+ case TIM_DMA_CC2:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
+ }
+ break;
+ case TIM_DMA_CC3:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
+ }
+ break;
+ case TIM_DMA_CC4:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
+ }
+ break;
+ case TIM_DMA_COM:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+ }
+ break;
+ case TIM_DMA_TRIGGER:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* Disable the TIM Update DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Generate a software event
+ * @param htim TIM handle
+ * @param EventSource specifies the event source.
+ * This parameter can be one of the following values:
+ * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
+ * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
+ * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
+ * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
+ * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
+ * @arg TIM_EVENTSOURCE_COM: Timer COM event source
+ * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
+ * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
+ * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
+ * @retval HAL status
+ * @note TIM_EVENTSOURCE_BREAK2 isn't relevant for STM32F37xx and STM32F38xx
+ * devices
+ */
+
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_EVENT_SOURCE(EventSource));
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ /* Change the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Set the event sources */
+ htim->Instance->EGR = EventSource;
+
+ /* Change the TIM state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the OCRef clear feature
+ * @param htim TIM handle
+ * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
+ * contains the OCREF clear feature and parameters for the TIM peripheral.
+ * @param Channel specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1
+ * @arg TIM_CHANNEL_2: TIM Channel 2
+ * @arg TIM_CHANNEL_3: TIM Channel 3
+ * @arg TIM_CHANNEL_4: TIM Channel 4
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_CHANNELS(Channel));
+ assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR)
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
+ assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
+ assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
+
+ TIM_ETR_SetConfig(htim->Instance,
+ sClearInputConfig->ClearInputPrescaler,
+ sClearInputConfig->ClearInputPolarity,
+ sClearInputConfig->ClearInputFilter);
+ }
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ if(sClearInputConfig->ClearInputState != RESET)
+ {
+ /* Enable the Ocref clear feature for Channel 1U */
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
+ }
+ else
+ {
+ /* Disable the Ocref clear feature for Channel 1U */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
+ }
+ }
+ break;
+ case TIM_CHANNEL_2:
+ {
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ if(sClearInputConfig->ClearInputState != RESET)
+ {
+ /* Enable the Ocref clear feature for Channel 2U */
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
+ }
+ else
+ {
+ /* Disable the Ocref clear feature for Channel 2U */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
+ }
+ }
+ break;
+ case TIM_CHANNEL_3:
+ {
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+ if(sClearInputConfig->ClearInputState != RESET)
+ {
+ /* Enable the Ocref clear feature for Channel 3U */
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
+ }
+ else
+ {
+ /* Disable the Ocref clear feature for Channel 3U */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
+ }
+ }
+ break;
+ case TIM_CHANNEL_4:
+ {
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+ if(sClearInputConfig->ClearInputState != RESET)
+ {
+ /* Enable the Ocref clear feature for Channel 4U */
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
+ }
+ else
+ {
+ /* Disable the Ocref clear feature for Channel 4U */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the clock source to be used
+ * @param htim TIM handle
+ * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
+ * contains the clock source information for the TIM peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
+{
+ uint32_t tmpsmcr = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
+
+ /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
+ tmpsmcr = htim->Instance->SMCR;
+ tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
+ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+ htim->Instance->SMCR = tmpsmcr;
+
+ switch (sClockSourceConfig->ClockSource)
+ {
+ case TIM_CLOCKSOURCE_INTERNAL:
+ {
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ /* Disable slave mode to clock the prescaler directly with the internal clock */
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+ }
+ break;
+
+ case TIM_CLOCKSOURCE_ETRMODE1:
+ {
+ /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
+ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
+
+ /* Check ETR input conditioning related parameters */
+ assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+ /* Configure the ETR Clock source */
+ TIM_ETR_SetConfig(htim->Instance,
+ sClockSourceConfig->ClockPrescaler,
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = htim->Instance->SMCR;
+ /* Reset the SMS and TS Bits */
+ tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
+ /* Select the External clock mode1 and the ETRF trigger */
+ tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
+ /* Write to TIMx SMCR */
+ htim->Instance->SMCR = tmpsmcr;
+ }
+ break;
+
+ case TIM_CLOCKSOURCE_ETRMODE2:
+ {
+ /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
+ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
+
+ /* Check ETR input conditioning related parameters */
+ assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+ /* Configure the ETR Clock source */
+ TIM_ETR_SetConfig(htim->Instance,
+ sClockSourceConfig->ClockPrescaler,
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
+ /* Enable the External clock mode2 */
+ htim->Instance->SMCR |= TIM_SMCR_ECE;
+ }
+ break;
+
+ case TIM_CLOCKSOURCE_TI1:
+ {
+ /* Check whether or not the timer instance supports external clock mode 1U */
+ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+ /* Check TI1 input conditioning related parameters */
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+ TIM_TI1_ConfigInputStage(htim->Instance,
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
+ }
+ break;
+ case TIM_CLOCKSOURCE_TI2:
+ {
+ /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
+ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+ /* Check TI2 input conditioning related parameters */
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+ TIM_TI2_ConfigInputStage(htim->Instance,
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
+ }
+ break;
+ case TIM_CLOCKSOURCE_TI1ED:
+ {
+ /* Check whether or not the timer instance supports external clock mode 1U */
+ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+ /* Check TI1 input conditioning related parameters */
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+ TIM_TI1_ConfigInputStage(htim->Instance,
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
+ }
+ break;
+ case TIM_CLOCKSOURCE_ITR0:
+ {
+ /* Check whether or not the timer instance supports external clock mode 1U */
+ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
+
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
+ }
+ break;
+ case TIM_CLOCKSOURCE_ITR1:
+ {
+ /* Check whether or not the timer instance supports external clock mode 1U */
+ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
+
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
+ }
+ break;
+ case TIM_CLOCKSOURCE_ITR2:
+ {
+ /* Check whether or not the timer instance supports external clock mode 1U */
+ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
+
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
+ }
+ break;
+ case TIM_CLOCKSOURCE_ITR3:
+ {
+ /* Check whether or not the timer instance supports external clock mode 1U */
+ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
+
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
+ }
+ break;
+
+ default:
+ break;
+ }
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Selects the signal connected to the TI1 input: direct from CH1_input
+ * or a XOR combination between CH1_input, CH2_input & CH3_input
+ * @param htim TIM handle.
+ * @param TI1_Selection: Indicate whether or not channel 1 is connected to the
+ * output of a XOR gate.
+ * This parameter can be one of the following values:
+ * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
+ * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
+ * pins are connected to the TI1 input (XOR combination)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
+{
+ uint32_t tmpcr2 = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = htim->Instance->CR2;
+
+ /* Reset the TI1 selection */
+ tmpcr2 &= ~TIM_CR2_TI1S;
+
+ /* Set the the TI1 selection */
+ tmpcr2 |= TI1_Selection;
+
+ /* Write to TIMxCR2 */
+ htim->Instance->CR2 = tmpcr2;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the TIM in Slave mode
+ * @param htim TIM handle.
+ * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
+ * contains the selected trigger (internal trigger input, filtered
+ * timer input or external trigger input) and the ) and the Slave
+ * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+ assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
+
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
+
+ /* Disable Trigger Interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
+
+ /* Disable Trigger DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the TIM in Slave mode in interrupt mode
+ * @param htim TIM handle.
+ * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
+ * contains the selected trigger (internal trigger input, filtered
+ * timer input or external trigger input) and the ) and the Slave
+ * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
+ TIM_SlaveConfigTypeDef * sSlaveConfig)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+ assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
+
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
+
+ /* Enable Trigger Interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
+
+ /* Disable Trigger DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Read the captured value from Capture Compare unit
+ * @param htim TIM handle.
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval Captured value
+ */
+uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ uint32_t tmpreg = 0U;
+
+ __HAL_LOCK(htim);
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+ /* Return the capture 1 value */
+ tmpreg = htim->Instance->CCR1;
+
+ break;
+ }
+ case TIM_CHANNEL_2:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Return the capture 2 value */
+ tmpreg = htim->Instance->CCR2;
+
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+ /* Return the capture 3 value */
+ tmpreg = htim->Instance->CCR3;
+
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+ /* Return the capture 4 value */
+ tmpreg = htim->Instance->CCR4;
+
+ break;
+ }
+
+ default:
+ break;
+ }
+
+ __HAL_UNLOCK(htim);
+ return tmpreg;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
+ * @brief TIM Callbacks functions
+ *
+@verbatim
+ ==============================================================================
+ ##### TIM Callbacks functions #####
+ ==============================================================================
+ [..]
+ This section provides TIM callback functions:
+ (+) Timer Period elapsed callback
+ (+) Timer Output Compare callback
+ (+) Timer Input capture callback
+ (+) Timer Trigger callback
+ (+) Timer Error callback
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Period elapsed callback in non blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
+ */
+
+}
+/**
+ * @brief Output Compare callback in non blocking mode
+ * @param htim TIM OC handle
+ * @retval None
+ */
+__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
+ */
+}
+/**
+ * @brief Input Capture callback in non blocking mode
+ * @param htim TIM IC handle
+ * @retval None
+ */
+__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief PWM Pulse finished callback in non blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Hall Trigger detection callback in non blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_TriggerCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Timer error callback in non blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State functions #####
+ ==============================================================================
+ [..]
+ This subsection permit to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the TIM Base state
+ * @param htim TIM Base handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM OC state
+ * @param htim TIM Ouput Compare handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM PWM state
+ * @param htim TIM handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM Input Capture state
+ * @param htim TIM IC handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM One Pulse Mode state
+ * @param htim TIM OPM handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM Encoder Mode state
+ * @param htim TIM Encoder handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Private_Functions TIM_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief TIM DMA error callback
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void TIM_DMAError(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ htim->State= HAL_TIM_STATE_READY;
+
+ HAL_TIM_ErrorCallback(htim);
+}
+
+/**
+ * @brief TIM DMA Delay Pulse complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ htim->State= HAL_TIM_STATE_READY;
+
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ }
+
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+/**
+ * @brief TIM DMA Capture complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ htim->State= HAL_TIM_STATE_READY;
+
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ }
+
+ HAL_TIM_IC_CaptureCallback(htim);
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+ * @brief TIM DMA Period Elapse complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ htim->State= HAL_TIM_STATE_READY;
+
+ HAL_TIM_PeriodElapsedCallback(htim);
+}
+
+/**
+ * @brief TIM DMA Trigger callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ htim->State= HAL_TIM_STATE_READY;
+
+ HAL_TIM_TriggerCallback(htim);
+}
+
+/**
+ * @brief Time Base configuration
+ * @param TIMx TIM periheral
+ * @param Structure TIM Base configuration structure
+ * @retval None
+ */
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
+{
+ uint32_t tmpcr1 = 0U;
+ tmpcr1 = TIMx->CR1;
+
+ /* Set TIM Time Base Unit parameters ---------------------------------------*/
+ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
+ {
+ /* Select the Counter Mode */
+ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
+ tmpcr1 |= Structure->CounterMode;
+ }
+
+ if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
+ {
+ /* Set the clock division */
+ tmpcr1 &= ~TIM_CR1_CKD;
+ tmpcr1 |= (uint32_t)Structure->ClockDivision;
+ }
+
+ /* Set the auto-reload preload */
+ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
+
+ TIMx->CR1 = tmpcr1;
+
+ /* Set the Autoreload value */
+ TIMx->ARR = (uint32_t)Structure->Period ;
+
+ /* Set the Prescaler value */
+ TIMx->PSC = (uint32_t)Structure->Prescaler;
+
+ if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
+ {
+ /* Set the Repetition Counter value */
+ TIMx->RCR = Structure->RepetitionCounter;
+ }
+
+ /* Generate an update event to reload the Prescaler
+ and the repetition counter(only for TIM1 and TIM8) value immediatly */
+ TIMx->EGR = TIM_EGR_UG;
+}
+
+/**
+ * @brief Time Ouput Compare 1 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config The ouput configuration structure
+ * @retval None
+ */
+void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+ uint32_t tmpccmrx = 0U;
+ uint32_t tmpccer = 0U;
+ uint32_t tmpcr2 = 0U;
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC1E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmrx = TIMx->CCMR1;
+
+ /* Reset the Output Compare Mode Bits */
+ tmpccmrx &= ~TIM_CCMR1_OC1M;
+ tmpccmrx &= ~TIM_CCMR1_CC1S;
+ /* Select the Output Compare Mode */
+ tmpccmrx |= OC_Config->OCMode;
+
+ /* Reset the Output Polarity level */
+ tmpccer &= ~TIM_CCER_CC1P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= OC_Config->OCPolarity;
+
+ if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
+ {
+ /* Check parameters */
+ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= ~TIM_CCER_CC1NP;
+ /* Set the Output N Polarity */
+ tmpccer |= OC_Config->OCNPolarity;
+ /* Reset the Output N State */
+ tmpccer &= ~TIM_CCER_CC1NE;
+ }
+
+ if(IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ /* Check parameters */
+ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS1;
+ tmpcr2 &= ~TIM_CR2_OIS1N;
+ /* Set the Output Idle state */
+ tmpcr2 |= OC_Config->OCIdleState;
+ /* Set the Output N Idle state */
+ tmpcr2 |= OC_Config->OCNIdleState;
+ }
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR1 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Time Ouput Compare 2 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config The ouput configuration structure
+ * @retval None
+ */
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+ uint32_t tmpccmrx = 0U;
+ uint32_t tmpccer = 0U;
+ uint32_t tmpcr2 = 0U;
+
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC2E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmrx = TIMx->CCMR1;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= ~TIM_CCMR1_OC2M;
+ tmpccmrx &= ~TIM_CCMR1_CC2S;
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (OC_Config->OCMode << 8U);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= ~TIM_CCER_CC2P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (OC_Config->OCPolarity << 4U);
+
+ if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
+ {
+ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= ~TIM_CCER_CC2NP;
+ /* Set the Output N Polarity */
+ tmpccer |= (OC_Config->OCNPolarity << 4U);
+ /* Reset the Output N State */
+ tmpccer &= ~TIM_CCER_CC2NE;
+
+ }
+
+ if(IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ /* Check parameters */
+ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+ /* Reset the Output Compare IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS2;
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#else
+ /* Reset the Output Compare N IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS2N;
+#endif
+ /* Set the Output Idle state */
+ tmpcr2 |= (OC_Config->OCIdleState << 2U);
+ /* Set the Output N Idle state */
+ tmpcr2 |= (OC_Config->OCNIdleState << 2U);
+ }
+
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR2 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Time Ouput Compare 3 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config The ouput configuration structure
+ * @retval None
+ */
+void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+ uint32_t tmpccmrx = 0U;
+ uint32_t tmpccer = 0U;
+ uint32_t tmpcr2 = 0U;
+
+ /* Disable the Channel 3: Reset the CC2E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC3E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR2 register value */
+ tmpccmrx = TIMx->CCMR2;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= ~TIM_CCMR2_OC3M;
+ tmpccmrx &= ~TIM_CCMR2_CC3S;
+ /* Select the Output Compare Mode */
+ tmpccmrx |= OC_Config->OCMode;
+
+ /* Reset the Output Polarity level */
+ tmpccer &= ~TIM_CCER_CC3P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (OC_Config->OCPolarity << 8U);
+
+ if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
+ {
+ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= ~TIM_CCER_CC3NP;
+ /* Set the Output N Polarity */
+ tmpccer |= (OC_Config->OCNPolarity << 8U);
+ /* Reset the Output N State */
+ tmpccer &= ~TIM_CCER_CC3NE;
+ }
+
+ if(IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ /* Check parameters */
+ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#else
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS3;
+ tmpcr2 &= ~TIM_CR2_OIS3N;
+#endif
+ /* Set the Output Idle state */
+ tmpcr2 |= (OC_Config->OCIdleState << 4U);
+ /* Set the Output N Idle state */
+ tmpcr2 |= (OC_Config->OCNIdleState << 4U);
+ }
+
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR2 */
+ TIMx->CCMR2 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR3 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Time Ouput Compare 4 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config The ouput configuration structure
+ * @retval None
+ */
+void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+ uint32_t tmpccmrx = 0U;
+ uint32_t tmpccer = 0U;
+ uint32_t tmpcr2 = 0U;
+
+ /* Disable the Channel 4: Reset the CC4E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC4E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR2 register value */
+ tmpccmrx = TIMx->CCMR2;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= ~TIM_CCMR2_OC4M;
+ tmpccmrx &= ~TIM_CCMR2_CC4S;
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (OC_Config->OCMode << 8U);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= ~TIM_CCER_CC4P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (OC_Config->OCPolarity << 12U);
+
+ if(IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#else
+ /* Reset the Output Compare IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS4;
+#endif
+ /* Set the Output Idle state */
+ tmpcr2 |= (OC_Config->OCIdleState << 6U);
+ }
+
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR2 */
+ TIMx->CCMR2 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR4 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+ TIM_SlaveConfigTypeDef * sSlaveConfig)
+{
+ uint32_t tmpsmcr = 0U;
+ uint32_t tmpccmr1 = 0U;
+ uint32_t tmpccer = 0U;
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = htim->Instance->SMCR;
+
+ /* Reset the Trigger Selection Bits */
+ tmpsmcr &= ~TIM_SMCR_TS;
+ /* Set the Input Trigger source */
+ tmpsmcr |= sSlaveConfig->InputTrigger;
+
+ /* Reset the slave mode Bits */
+ tmpsmcr &= ~TIM_SMCR_SMS;
+ /* Set the slave mode */
+ tmpsmcr |= sSlaveConfig->SlaveMode;
+
+ /* Write to TIMx SMCR */
+ htim->Instance->SMCR = tmpsmcr;
+
+ /* Configure the trigger prescaler, filter, and polarity */
+ switch (sSlaveConfig->InputTrigger)
+ {
+ case TIM_TS_ETRF:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+ /* Configure the ETR Trigger source */
+ TIM_ETR_SetConfig(htim->Instance,
+ sSlaveConfig->TriggerPrescaler,
+ sSlaveConfig->TriggerPolarity,
+ sSlaveConfig->TriggerFilter);
+ }
+ break;
+
+ case TIM_TS_TI1F_ED:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ tmpccer = htim->Instance->CCER;
+ htim->Instance->CCER &= ~TIM_CCER_CC1E;
+ tmpccmr1 = htim->Instance->CCMR1;
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC1F;
+ tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ htim->Instance->CCMR1 = tmpccmr1;
+ htim->Instance->CCER = tmpccer;
+
+ }
+ break;
+
+ case TIM_TS_TI1FP1:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+ /* Configure TI1 Filter and Polarity */
+ TIM_TI1_ConfigInputStage(htim->Instance,
+ sSlaveConfig->TriggerPolarity,
+ sSlaveConfig->TriggerFilter);
+ }
+ break;
+
+ case TIM_TS_TI2FP2:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+ /* Configure TI2 Filter and Polarity */
+ TIM_TI2_ConfigInputStage(htim->Instance,
+ sSlaveConfig->TriggerPolarity,
+ sSlaveConfig->TriggerFilter);
+ }
+ break;
+
+ case TIM_TS_ITR0:
+ {
+ /* Check the parameter */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ }
+ break;
+
+ case TIM_TS_ITR1:
+ {
+ /* Check the parameter */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ }
+ break;
+
+ case TIM_TS_ITR2:
+ {
+ /* Check the parameter */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ }
+ break;
+
+ case TIM_TS_ITR3:
+ {
+ /* Check the parameter */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ }
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Configure the TI1 as Input.
+ * @param TIMx to select the TIM peripheral.
+ * @param TIM_ICPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @param TIM_ICSelection specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
+ * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
+ * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
+ * protected against un-initialized filter and polarity values.
+ */
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter)
+{
+ uint32_t tmpccmr1 = 0U;
+ uint32_t tmpccer = 0U;
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC1E;
+ tmpccmr1 = TIMx->CCMR1;
+ tmpccer = TIMx->CCER;
+
+ /* Select the Input */
+ if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
+ {
+ tmpccmr1 &= ~TIM_CCMR1_CC1S;
+ tmpccmr1 |= TIM_ICSelection;
+ }
+ else
+ {
+ tmpccmr1 |= TIM_CCMR1_CC1S_0;
+ }
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC1F;
+ tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
+
+ /* Select the Polarity and set the CC1E Bit */
+ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+ tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the Polarity and Filter for TI1.
+ * @param TIMx to select the TIM peripheral.
+ * @param TIM_ICPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ */
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+{
+ uint32_t tmpccmr1 = 0U;
+ uint32_t tmpccer = 0U;
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ tmpccer = TIMx->CCER;
+ TIMx->CCER &= ~TIM_CCER_CC1E;
+ tmpccmr1 = TIMx->CCMR1;
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC1F;
+ tmpccmr1 |= (TIM_ICFilter << 4U);
+
+ /* Select the Polarity and set the CC1E Bit */
+ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+ tmpccer |= TIM_ICPolarity;
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the TI2 as Input.
+ * @param TIMx to select the TIM peripheral
+ * @param TIM_ICPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @param TIM_ICSelection specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
+ * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
+ * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
+ * protected against un-initialized filter and polarity values.
+ */
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter)
+{
+ uint32_t tmpccmr1 = 0U;
+ uint32_t tmpccer = 0U;
+
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC2E;
+ tmpccmr1 = TIMx->CCMR1;
+ tmpccer = TIMx->CCER;
+
+ /* Select the Input */
+ tmpccmr1 &= ~TIM_CCMR1_CC2S;
+ tmpccmr1 |= (TIM_ICSelection << 8U);
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC2F;
+ tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
+
+ /* Select the Polarity and set the CC2E Bit */
+ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+ tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1 ;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the Polarity and Filter for TI2.
+ * @param TIMx to select the TIM peripheral.
+ * @param TIM_ICPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ */
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+{
+ uint32_t tmpccmr1 = 0U;
+ uint32_t tmpccer = 0U;
+
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC2E;
+ tmpccmr1 = TIMx->CCMR1;
+ tmpccer = TIMx->CCER;
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC2F;
+ tmpccmr1 |= (TIM_ICFilter << 12U);
+
+ /* Select the Polarity and set the CC2E Bit */
+ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+ tmpccer |= (TIM_ICPolarity << 4U);
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1 ;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the TI3 as Input.
+ * @param TIMx to select the TIM peripheral
+ * @param TIM_ICPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @param TIM_ICSelection specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
+ * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
+ * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
+ * protected against un-initialized filter and polarity values.
+ */
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter)
+{
+ uint32_t tmpccmr2 = 0U;
+ uint32_t tmpccer = 0U;
+
+ /* Disable the Channel 3: Reset the CC3E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC3E;
+ tmpccmr2 = TIMx->CCMR2;
+ tmpccer = TIMx->CCER;
+
+ /* Select the Input */
+ tmpccmr2 &= ~TIM_CCMR2_CC3S;
+ tmpccmr2 |= TIM_ICSelection;
+
+ /* Set the filter */
+ tmpccmr2 &= ~TIM_CCMR2_IC3F;
+ tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
+
+ /* Select the Polarity and set the CC3E Bit */
+ tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
+ tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
+
+ /* Write to TIMx CCMR2 and CCER registers */
+ TIMx->CCMR2 = tmpccmr2;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the TI4 as Input.
+ * @param TIMx to select the TIM peripheral
+ * @param TIM_ICPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @param TIM_ICSelection specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
+ * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
+ * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
+ * protected against un-initialized filter and polarity values.
+ * @retval None
+ */
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter)
+{
+ uint32_t tmpccmr2 = 0U;
+ uint32_t tmpccer = 0U;
+
+ /* Disable the Channel 4: Reset the CC4E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC4E;
+ tmpccmr2 = TIMx->CCMR2;
+ tmpccer = TIMx->CCER;
+
+ /* Select the Input */
+ tmpccmr2 &= ~TIM_CCMR2_CC4S;
+ tmpccmr2 |= (TIM_ICSelection << 8U);
+
+ /* Set the filter */
+ tmpccmr2 &= ~TIM_CCMR2_IC4F;
+ tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
+
+ /* Select the Polarity and set the CC4E Bit */
+ tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
+ tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
+
+ /* Write to TIMx CCMR2 and CCER registers */
+ TIMx->CCMR2 = tmpccmr2;
+ TIMx->CCER = tmpccer ;
+}
+
+/**
+ * @brief Selects the Input Trigger source
+ * @param TIMx to select the TIM peripheral
+ * @param InputTriggerSource The Input Trigger source.
+ * This parameter can be one of the following values:
+ * @arg TIM_TS_ITR0: Internal Trigger 0
+ * @arg TIM_TS_ITR1: Internal Trigger 1
+ * @arg TIM_TS_ITR2: Internal Trigger 2
+ * @arg TIM_TS_ITR3: Internal Trigger 3
+ * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
+ * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
+ * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
+ * @arg TIM_TS_ETRF: External Trigger input
+ * @retval None
+ */
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
+{
+ uint32_t tmpsmcr = 0U;
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = TIMx->SMCR;
+ /* Reset the TS Bits */
+ tmpsmcr &= ~TIM_SMCR_TS;
+ /* Set the Input Trigger source and the slave mode*/
+ tmpsmcr |= InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1;
+ /* Write to TIMx SMCR */
+ TIMx->SMCR = tmpsmcr;
+}
+/**
+ * @brief Configures the TIMx External Trigger (ETR).
+ * @param TIMx to select the TIM peripheral
+ * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
+ * This parameter can be one of the following values:
+ * @arg TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF.
+ * @arg TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2.
+ * @arg TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4.
+ * @arg TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8.
+ * @param TIM_ExtTRGPolarity The external Trigger Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ETRPOLARITY_INVERTED : active low or falling edge active.
+ * @arg TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active.
+ * @param ExtTRGFilter External Trigger Filter.
+ * This parameter must be a value between 0x00 and 0x0F
+ * @retval None
+ */
+void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
+ uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
+{
+ uint32_t tmpsmcr = 0U;
+
+ tmpsmcr = TIMx->SMCR;
+
+ /* Reset the ETR Bits */
+ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+
+ /* Set the Prescaler, the Filter value and the Polarity */
+ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
+
+ /* Write to TIMx SMCR */
+ TIMx->SMCR = tmpsmcr;
+}
+
+/**
+ * @brief Enables or disables the TIM Capture Compare Channel x.
+ * @param TIMx to select the TIM peripheral
+ * @param Channel specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1
+ * @arg TIM_CHANNEL_2: TIM Channel 2
+ * @arg TIM_CHANNEL_3: TIM Channel 3
+ * @arg TIM_CHANNEL_4: TIM Channel 4
+ * @param ChannelState specifies the TIM Channel CCxE bit new state.
+ * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
+ * @retval None
+ */
+void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
+{
+ uint32_t tmp = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+ assert_param(IS_TIM_CHANNELS(Channel));
+
+ tmp = TIM_CCER_CC1E << Channel;
+
+ /* Reset the CCxE Bit */
+ TIMx->CCER &= ~tmp;
+
+ /* Set or reset the CCxE Bit */
+ TIMx->CCER |= (uint32_t)(ChannelState << Channel);
+}
+
+
+/**
+ * @}
+ */
+
+#endif /* HAL_TIM_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_tim_ex.c b/Src/stm32f3xx_hal_tim_ex.c
new file mode 100644
index 0000000..fee5d93
--- /dev/null
+++ b/Src/stm32f3xx_hal_tim_ex.c
@@ -0,0 +1,2716 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_tim_ex.c
+ * @author MCD Application Team
+ * @brief TIM HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Timer Extended peripheral:
+ * + Time Hall Sensor Interface Initialization
+ * + Time Hall Sensor Interface Start
+ * + Time Complementary signal bread and dead time configuration
+ * + Time Master and Slave synchronization configuration
+ * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
+ * + Time OCRef clear configuration
+ * + Timer remapping capabilities configuration
+ @verbatim
+ ==============================================================================
+ ##### TIMER Extended features #####
+ ==============================================================================
+ [..]
+ The Timer Extended features include:
+ (#) Complementary outputs with programmable dead-time for :
+ (++) Output Compare
+ (++) PWM generation (Edge and Center-aligned Mode)
+ (++) One-pulse mode output
+ (#) Synchronization circuit to control the timer with external signals and to
+ interconnect several timers together.
+ (#) Break input to put the timer output signals in reset state or in a known state.
+ (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
+ positioning purposes
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Initialize the TIM low level resources by implementing the following functions
+ depending from feature used :
+ (++) Complementary Output Compare : HAL_TIM_OC_MspInit()
+ (++) Complementary PWM generation : HAL_TIM_PWM_MspInit()
+ (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit()
+ (++) Hall Sensor output : HAL_TIM_HallSensor_MspInit()
+
+ (#) Initialize the TIM low level resources :
+ (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE ();
+ (##) TIM pins configuration
+ (+++) Enable the clock for the TIM GPIOs using the following function:
+ __HAL_RCC_GPIOx_CLK_ENABLE();
+ (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
+
+ (#) The external Clock can be configured, if needed (the default clock is the
+ internal clock from the APBx), using the following function:
+ HAL_TIM_ConfigClockSource, the clock configuration should be done before
+ any start function.
+
+ (#) Configure the TIM in the desired functioning mode using one of the
+ initialization function of this driver:
+ (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the
+ Timer Hall Sensor Interface and the commutation event with the corresponding
+ Interrupt and DMA request if needed (Note that One Timer is used to interface
+ with the Hall sensor Interface and another Timer should be used to use
+ the commutation event).
+
+ (#) Activate the TIM peripheral using one of the start functions:
+ (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT()
+ (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
+ (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
+ (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
+
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup TIMEx TIMEx
+ * @brief TIM Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+
+#define BDTR_BKF_SHIFT (16U)
+#define BDTR_BK2F_SHIFT (20U)
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
+ * @{
+ */
+static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
+ TIM_OC_InitTypeDef *OC_Config);
+
+static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
+ TIM_OC_InitTypeDef *OC_Config);
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup TIMEx_Exported_Functions TIMEx Exported Functions
+ * @{
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group1 Timer Hall Sensor functions
+ * @brief Timer Hall Sensor functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Timer Hall Sensor functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure TIM HAL Sensor.
+ (+) De-initialize TIM HAL Sensor.
+ (+) Start the Hall Sensor Interface.
+ (+) Stop the Hall Sensor Interface.
+ (+) Start the Hall Sensor Interface and enable interrupts.
+ (+) Stop the Hall Sensor Interface and disable interrupts.
+ (+) Start the Hall Sensor Interface and enable DMA transfers.
+ (+) Stop the Hall Sensor Interface and disable DMA transfers.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM Hall Sensor Interface and create the associated handle.
+ * @param htim TIM Encoder Interface handle
+ * @param sConfig TIM Hall Sensor configuration structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)
+{
+ TIM_OC_InitTypeDef OC_Config;
+
+ /* Check the TIM handle allocation */
+ if(htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+ assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+ assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+
+ if(htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIMEx_HallSensor_MspInit(htim);
+ }
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Configure the Time base in the Encoder Mode */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */
+ TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
+
+ /* Reset the IC1PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+ /* Set the IC1PSC value */
+ htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
+
+ /* Enable the Hall sensor interface (XOR function of the three inputs) */
+ htim->Instance->CR2 |= TIM_CR2_TI1S;
+
+ /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= TIM_TS_TI1F_ED;
+
+ /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+ htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
+
+ /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
+ OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
+ OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
+ OC_Config.OCMode = TIM_OCMODE_PWM2;
+ OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
+ OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
+ OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
+ OC_Config.Pulse = sConfig->Commutation_Delay;
+
+ TIM_OC2_SetConfig(htim->Instance, &OC_Config);
+
+ /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
+ register to 101U */
+ htim->Instance->CR2 &= ~TIM_CR2_MMS;
+ htim->Instance->CR2 |= TIM_TRGO_OC2REF;
+
+ /* Initialize the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM Hall Sensor interface
+ * @param htim TIM Hall Sensor handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_TIMEx_HallSensor_MspDeInit(htim);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Hall Sensor MSP.
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM Hall Sensor MSP.
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the TIM Hall Sensor Interface.
+ * @param htim TIM Hall Sensor handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Enable the Input Capture channel 1
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Hall sensor Interface.
+ * @param htim TIM Hall Sensor handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channels 1U, 2 and 3
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Hall Sensor Interface in interrupt mode.
+ * @param htim TIM Hall Sensor handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Enable the capture compare Interrupts 1 event */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+ /* Enable the Input Capture channel 1
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Hall Sensor Interface in interrupt mode.
+ * @param htim TIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channel 1
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare Interrupts event */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Hall Sensor Interface in DMA mode.
+ * @param htim TIM Hall Sensor handle
+ * @param pData The destination Buffer address.
+ * @param Length The length of data to be transferred from TIM peripheral to memory.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if(((uint32_t)pData == 0U ) && (Length > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ /* Enable the Input Capture channel 1
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+ /* Set the DMA Input Capture 1 Callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel for Capture 1U*/
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
+
+ /* Enable the capture compare 1 Interrupt */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Hall Sensor Interface in DMA mode.
+ * @param htim TIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channel 1
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+
+ /* Disable the capture compare Interrupts 1 event */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group2 Timer Complementary Output Compare functions
+ * @brief Timer Complementary Output Compare functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Timer Complementary Output Compare functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Start the Complementary Output Compare.
+ (+) Stop the Complementary Output Compare.
+ (+) Start the Complementary Output Compare and enable interrupts.
+ (+) Stop the Complementary Output Compare and disable interrupts.
+ (+) Start the Complementary Output Compare and enable DMA transfers.
+ (+) Stop the Complementary Output Compare and disable DMA transfers.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Starts the TIM Output Compare signal generation on the complementary
+ * output.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ /* Enable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Ouput */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation on the complementary
+ * output.
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ /* Disable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Output Compare signal generation in interrupt mode
+ * on the complementary output.
+ * @param htim TIM OC handle
+ * @param Channel TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Enable the TIM Output Compare interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Enable the TIM Output Compare interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Enable the TIM Output Compare interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable the TIM Break interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+
+ /* Enable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Ouput */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation in interrupt mode
+ * on the complementary output.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ uint32_t tmpccer = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Output Compare interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Output Compare interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Output Compare interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the TIM Break interrupt (only if no more channel is active) */
+ tmpccer = htim->Instance->CCER;
+ if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
+ {
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+ }
+
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Output Compare signal generation in DMA mode
+ * on the complementary output.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @param pData The source Buffer address.
+ * @param Length The length of data to be transferred from memory to TIM peripheral
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if(((uint32_t)pData == 0U ) && (Length > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
+
+ /* Enable the TIM Output Compare DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
+
+ /* Enable the TIM Output Compare DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
+
+ /* Enable the TIM Output Compare DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Ouput */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation in DMA mode
+ * on the complementary output.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Output Compare DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Output Compare DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Output Compare DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group3 Timer Complementary PWM functions
+ * @brief Timer Complementary PWM functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Timer Complementary PWM functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Start the Complementary PWM.
+ (+) Stop the Complementary PWM.
+ (+) Start the Complementary PWM and enable interrupts.
+ (+) Stop the Complementary PWM and disable interrupts.
+ (+) Start the Complementary PWM and enable DMA transfers.
+ (+) Stop the Complementary PWM and disable DMA transfers.
+ (+) Start the Complementary Input Capture measurement.
+ (+) Stop the Complementary Input Capture.
+ (+) Start the Complementary Input Capture and enable interrupts.
+ (+) Stop the Complementary Input Capture and disable interrupts.
+ (+) Start the Complementary Input Capture and enable DMA transfers.
+ (+) Stop the Complementary Input Capture and disable DMA transfers.
+ (+) Start the Complementary One Pulse generation.
+ (+) Stop the Complementary One Pulse.
+ (+) Start the Complementary One Pulse and enable interrupts.
+ (+) Stop the Complementary One Pulse and disable interrupts.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Starts the PWM signal generation on the complementary output.
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ /* Enable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Ouput */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the PWM signal generation on the complementary output.
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ /* Disable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the PWM signal generation in interrupt mode on the
+ * complementary output.
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Enable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable the TIM Break interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+
+ /* Enable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Ouput */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the PWM signal generation in interrupt mode on the
+ * complementary output.
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ uint32_t tmpccer = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the TIM Break interrupt (only if no more channel is active) */
+ tmpccer = htim->Instance->CCER;
+ if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
+ {
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+ }
+
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM PWM signal generation in DMA mode on the
+ * complementary output
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @param pData The source Buffer address.
+ * @param Length The length of data to be transferred from memory to TIM peripheral
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if(((uint32_t)pData == 0U ) && (Length > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
+
+ /* Enable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
+
+ /* Enable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
+
+ /* Enable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Ouput */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM PWM signal generation in DMA mode on the complementary
+ * output
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group4 Timer Complementary One Pulse functions
+ * @brief Timer Complementary One Pulse functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Timer Complementary One Pulse functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Start the Complementary One Pulse generation.
+ (+) Stop the Complementary One Pulse.
+ (+) Start the Complementary One Pulse and enable interrupts.
+ (+) Stop the Complementary One Pulse and disable interrupts.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Starts the TIM One Pulse signal generation on the complemetary
+ * output.
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+ /* Enable the complementary One Pulse output */
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Ouput */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM One Pulse signal generation on the complementary
+ * output.
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+ /* Disable the complementary One Pulse output */
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM One Pulse signal generation in interrupt mode on the
+ * complementary channel.
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+
+ /* Enable the complementary One Pulse output */
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Ouput */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM One Pulse signal generation in interrupt mode on the
+ * complementary channel.
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+
+ /* Disable the complementary One Pulse output */
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+/** @defgroup TIMEx_Exported_Functions_Group5 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Configure the commutation event in case of use of the Hall sensor interface.
+ (+) Configure Output channels for OC and PWM mode.
+
+ (+) Configure Complementary channels, break features and dead time.
+ (+) Configure Master synchronization.
+ (+) Configure timer remapping capabilities.
+ (+) Enable or disable channel grouping
+
+@endverbatim
+ * @{
+ */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Configure the TIM commutation event sequence.
+ * @note this function is mandatory to use the commutation event in order to
+ * update the configuration at each commutation detection on the TRGI input of the Timer,
+ * the typical use of this feature is with the use of another Timer(interface Timer)
+ * configured in Hall sensor interface, this interface Timer will generate the
+ * commutation at its TRGO output (connected to Timer used in this function) each time
+ * the TI1 of the Interface Timer detect a commutation at its input TI1.
+ * @param htim TIM handle
+ * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+ * This parameter can be one of the following values:
+ * @arg TIM_TS_ITR0: Internal trigger 0 selected
+ * @arg TIM_TS_ITR1: Internal trigger 1 selected
+ * @arg TIM_TS_ITR2: Internal trigger 2 selected
+ * @arg TIM_TS_ITR3: Internal trigger 3 selected
+ * @arg TIM_TS_NONE: No trigger is needed
+ * @param CommutationSource the Commutation Event source
+ * This parameter can be one of the following values:
+ * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+ * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+
+ __HAL_LOCK(htim);
+
+ if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+ (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
+ {
+ /* Select the Input trigger */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= InputTrigger;
+ }
+
+ /* Select the Capture Compare preload feature */
+ htim->Instance->CR2 |= TIM_CR2_CCPC;
+ /* Select the Commutation event source */
+ htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+ htim->Instance->CR2 |= CommutationSource;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the TIM commutation event sequence with interrupt.
+ * @note this function is mandatory to use the commutation event in order to
+ * update the configuration at each commutation detection on the TRGI input of the Timer,
+ * the typical use of this feature is with the use of another Timer(interface Timer)
+ * configured in Hall sensor interface, this interface Timer will generate the
+ * commutation at its TRGO output (connected to Timer used in this function) each time
+ * the TI1 of the Interface Timer detect a commutation at its input TI1.
+ * @param htim TIM handle
+ * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+ * This parameter can be one of the following values:
+ * @arg TIM_TS_ITR0: Internal trigger 0 selected
+ * @arg TIM_TS_ITR1: Internal trigger 1 selected
+ * @arg TIM_TS_ITR2: Internal trigger 2 selected
+ * @arg TIM_TS_ITR3: Internal trigger 3 selected
+ * @arg TIM_TS_NONE: No trigger is needed
+ * @param CommutationSource the Commutation Event source
+ * This parameter can be one of the following values:
+ * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+ * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+
+ __HAL_LOCK(htim);
+
+ if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+ (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
+ {
+ /* Select the Input trigger */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= InputTrigger;
+ }
+
+ /* Select the Capture Compare preload feature */
+ htim->Instance->CR2 |= TIM_CR2_CCPC;
+ /* Select the Commutation event source */
+ htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+ htim->Instance->CR2 |= CommutationSource;
+
+ /* Enable the Commutation Interrupt Request */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the TIM commutation event sequence with DMA.
+ * @note this function is mandatory to use the commutation event in order to
+ * update the configuration at each commutation detection on the TRGI input of the Timer,
+ * the typical use of this feature is with the use of another Timer(interface Timer)
+ * configured in Hall sensor interface, this interface Timer will generate the
+ * commutation at its TRGO output (connected to Timer used in this function) each time
+ * the TI1 of the Interface Timer detect a commutation at its input TI1.
+ * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set
+ * @param htim TIM handle
+ * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+ * This parameter can be one of the following values:
+ * @arg TIM_TS_ITR0: Internal trigger 0 selected
+ * @arg TIM_TS_ITR1: Internal trigger 1 selected
+ * @arg TIM_TS_ITR2: Internal trigger 2 selected
+ * @arg TIM_TS_ITR3: Internal trigger 3 selected
+ * @arg TIM_TS_NONE: No trigger is needed
+ * @param CommutationSource the Commutation Event source
+ * This parameter can be one of the following values:
+ * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+ * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+
+ __HAL_LOCK(htim);
+
+ if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+ (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
+ {
+ /* Select the Input trigger */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= InputTrigger;
+ }
+
+ /* Select the Capture Compare preload feature */
+ htim->Instance->CR2 |= TIM_CR2_CCPC;
+ /* Select the Commutation event source */
+ htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+ htim->Instance->CR2 |= CommutationSource;
+
+ /* Enable the Commutation DMA Request */
+ /* Set the DMA Commutation Callback */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
+
+ /* Enable the Commutation DMA Request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Output Compare Channels according to the specified
+ * parameters in the TIM_OC_InitTypeDef.
+ * @param htim TIM Output Compare handle
+ * @param sConfig TIM Output Compare configuration structure
+ * @param Channel TIM Channels to configure
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @note For STM32F302xC, STM32F302xE, STM32F303xC, STM32F303xE, STM32F358xx,
+ * STM32F398xx and STM32F303x8 up to 6 OC channels can be configured
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
+ TIM_OC_InitTypeDef* sConfig,
+ uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CHANNELS(Channel));
+ assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
+ assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+
+ /* Check input state */
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+ /* Configure the TIM Channel 1 in Output Compare */
+ TIM_OC1_SetConfig(htim->Instance, sConfig);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Configure the TIM Channel 2 in Output Compare */
+ TIM_OC2_SetConfig(htim->Instance, sConfig);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+ /* Configure the TIM Channel 3 in Output Compare */
+ TIM_OC3_SetConfig(htim->Instance, sConfig);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+ /* Configure the TIM Channel 4 in Output Compare */
+ TIM_OC4_SetConfig(htim->Instance, sConfig);
+ }
+ break;
+
+ case TIM_CHANNEL_5:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
+
+ /* Configure the TIM Channel 5 in Output Compare */
+ TIM_OC5_SetConfig(htim->Instance, sConfig);
+ }
+ break;
+
+ case TIM_CHANNEL_6:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
+
+ /* Configure the TIM Channel 6 in Output Compare */
+ TIM_OC6_SetConfig(htim->Instance, sConfig);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM PWM channels according to the specified
+ * parameters in the TIM_OC_InitTypeDef.
+ * @param htim TIM PWM handle
+ * @param sConfig TIM PWM configuration structure
+ * @param Channel TIM Channels to be configured
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @note For STM32F302xC, STM32F302xE, STM32F303xC, STM32F303xE, STM32F358xx,
+ * STM32F398xx and STM32F303x8 up to 6 PWM channels can be configured
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
+ TIM_OC_InitTypeDef* sConfig,
+ uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CHANNELS(Channel));
+ assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
+ assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+ assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
+
+ /* Check input state */
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+ /* Configure the Channel 1 in PWM mode */
+ TIM_OC1_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel1 */
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
+ htim->Instance->CCMR1 |= sConfig->OCFastMode;
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Configure the Channel 2 in PWM mode */
+ TIM_OC2_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel2 */
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
+ htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+ /* Configure the Channel 3 in PWM mode */
+ TIM_OC3_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel3 */
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
+ htim->Instance->CCMR2 |= sConfig->OCFastMode;
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+ /* Configure the Channel 4 in PWM mode */
+ TIM_OC4_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel4 */
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
+ htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
+ }
+ break;
+
+ case TIM_CHANNEL_5:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
+
+ /* Configure the Channel 5 in PWM mode */
+ TIM_OC5_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel5*/
+ htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
+ htim->Instance->CCMR3 |= sConfig->OCFastMode;
+ }
+ break;
+
+ case TIM_CHANNEL_6:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
+
+ /* Configure the Channel 5 in PWM mode */
+ TIM_OC6_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel6 */
+ htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
+ htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Configures the TIM in master mode.
+ * @param htim TIM handle.
+ * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
+ * contains the selected trigger output (TRGO) and the Master/Slave
+ * mode.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
+ TIM_MasterConfigTypeDef * sMasterConfig)
+{
+ uint32_t tmpcr2;
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
+ assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
+
+ /* Check input state */
+ __HAL_LOCK(htim);
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = htim->Instance->CR2;
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = htim->Instance->SMCR;
+
+ /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2U */
+ if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
+
+ /* Clear the MMS2 bits */
+ tmpcr2 &= ~TIM_CR2_MMS2;
+ /* Select the TRGO2 source*/
+ tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
+ }
+
+ /* Reset the MMS Bits */
+ tmpcr2 &= ~TIM_CR2_MMS;
+ /* Select the TRGO source */
+ tmpcr2 |= sMasterConfig->MasterOutputTrigger;
+
+ /* Reset the MSM Bit */
+ tmpsmcr &= ~TIM_SMCR_MSM;
+ /* Set master mode */
+ tmpsmcr |= sMasterConfig->MasterSlaveMode;
+
+ /* Update TIMx CR2 */
+ htim->Instance->CR2 = tmpcr2;
+
+ /* Update TIMx SMCR */
+ htim->Instance->SMCR = tmpsmcr;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Configures the TIM in master mode.
+ * @param htim TIM handle.
+ * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
+ * contains the selected trigger output (TRGO) and the Master/Slave
+ * mode.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
+ assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
+
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Reset the MMS Bits */
+ htim->Instance->CR2 &= ~TIM_CR2_MMS;
+ /* Select the TRGO source */
+ htim->Instance->CR2 |= sMasterConfig->MasterOutputTrigger;
+
+ /* Reset the MSM Bit */
+ htim->Instance->SMCR &= ~TIM_SMCR_MSM;
+ /* Set or Reset the MSM Bit */
+ htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode;
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
+ * and the AOE(automatic output enable).
+ * @param htim TIM handle
+ * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef
+ structure that contains the BDTR Register configuration information
+ for the TIM peripheral.
+ * @note For STM32F302xC, STM32F302xE, STM32F303xC, STM32F358xx, STM32F303xE,
+ STM32F398xx and STM32F303x8 two break inputs can be configured.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
+ TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)
+{
+ uint32_t tmpbdtr = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
+ assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
+ assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
+ assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
+ assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
+ assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
+ assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
+ assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
+
+ /* Check input state */
+ __HAL_LOCK(htim);
+
+ /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
+ the OSSI State, the dead time value and the Automatic Output Enable Bit */
+
+ /* Set the BDTR bits */
+ MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, sBreakDeadTimeConfig->AutomaticOutput);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT));
+
+ if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
+ {
+ assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
+ assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
+ assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
+
+ /* Set the BREAK2 input related BDTR bits */
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << BDTR_BK2F_SHIFT));
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
+ }
+
+ /* Set TIMx_BDTR */
+ htim->Instance->BDTR = tmpbdtr;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
+ * and the AOE(automatic output enable).
+ * @param htim TIM handle
+ * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
+ * contains the BDTR Register configuration information for the TIM peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
+ TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
+{
+ uint32_t tmpbdtr = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
+ assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
+ assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
+ assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
+ assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
+ assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
+ assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
+ the OSSI State, the dead time value and the Automatic Output Enable Bit */
+
+ /* Set the BDTR bits */
+ MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, sBreakDeadTimeConfig->AutomaticOutput);
+
+ /* Set TIMx_BDTR */
+ htim->Instance->BDTR = tmpbdtr;
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F334x8)
+#if defined(STM32F303xE) || defined(STM32F398xx)
+/**
+ * @brief Configures the TIM1, TIM8, TIM16 and TIM20 Remapping input capabilities.
+ * @param htim TIM handle.
+ * @param Remap1: specifies the first TIM remapping source.
+ * This parameter can be one of the following values:
+ * @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any ADC1 AWD (analog watchdog)
+ * @arg TIM_TIM1_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
+ * @arg TIM_TIM1_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
+ * @arg TIM_TIM1_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
+ * @arg TIM_TIM8_ADC2_NONE: TIM8_ETR is not connected to any ADC2 AWD
+ * @arg TIM_TIM8_ADC2_AWD1: TIM8_ETR is connected to ADC2 AWD1
+ * @arg TIM_TIM8_ADC2_AWD2: TIM8_ETR is connected to ADC2 AWD2
+ * @arg TIM_TIM8_ADC2_AWD3: TIM8_ETR is connected to ADC2 AWD3
+ * @arg TIM_TIM16_GPIO: TIM16 TI1 is connected to GPIO
+ * @arg TIM_TIM16_RTC: TIM16 TI1 is connected to RTC clock
+ * @arg TIM_TIM16_HSE: TIM16 TI1 is connected to HSE/32
+ * @arg TIM_TIM16_MCO: TIM16 TI1 is connected to MCO
+ * @arg TIM_TIM20_ADC3_NONE: TIM20_ETR is not connected to any AWD (analog watchdog)
+ * @arg TIM_TIM20_ADC3_AWD1: TIM20_ETR is connected to ADC3 AWD1
+ * @arg TIM_TIM20_ADC3_AWD2: TIM20_ETR is connected to ADC3 AWD2
+ * @arg TIM_TIM20_ADC3_AWD3: TIM20_ETR is connected to ADC3 AWD3
+ * @param Remap2: specifies the second TIMremapping source (if any).
+ * This parameter can be one of the following values:
+ * @arg TIM_TIM1_ADC4_NONE: TIM1_ETR is not connected to any ADC4 AWD (analog watchdog)
+ * @arg TIM_TIM1_ADC4_AWD1: TIM1_ETR is connected to ADC4 AWD1
+ * @arg TIM_TIM1_ADC4_AWD2: TIM1_ETR is connected to ADC4 AWD2
+ * @arg TIM_TIM1_ADC4_AWD3: TIM1_ETR is connected to ADC4 AWD3
+ * @arg TIM_TIM8_ADC3_NONE: TIM8_ETR is not connected to any ADC3 AWD
+ * @arg TIM_TIM8_ADC3_AWD1: TIM8_ETR is connected to ADC3 AWD1
+ * @arg TIM_TIM8_ADC3_AWD2: TIM8_ETR is connected to ADC3 AWD2
+ * @arg TIM_TIM8_ADC3_AWD3: TIM8_ETR is connected to ADC3 AWD3
+ * @arg TIM_TIM16_NONE: Non significant value for TIM16
+ * @arg TIM_TIM20_ADC4_NONE: TIM20_ETR is not connected to any ADC4 AWD
+ * @arg TIM_TIM20_ADC4_AWD1: TIM20_ETR is connected to ADC4 AWD1
+ * @arg TIM_TIM20_ADC4_AWD2: TIM20_ETR is connected to ADC4 AWD2
+ * @arg TIM_TIM20_ADC4_AWD3: TIM20_ETR is connected to ADC4 AWD3
+ * @retval HAL status
+ */
+#elif defined(STM32F303xC) || defined(STM32F358xx)
+/**
+ * @brief Configures the TIM1, TIM8 and TIM16 Remapping input capabilities.
+ * @param htim TIM handle.
+ * @param Remap1: specifies the first TIM remapping source.
+ * This parameter can be one of the following values:
+ * @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any AWD (analog watchdog)
+ * @arg TIM_TIM1_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
+ * @arg TIM_TIM1_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
+ * @arg TIM_TIM1_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
+ * @arg TIM_TIM8_ADC2_NONE: TIM8_ETR is not connected to any AWD
+ * @arg TIM_TIM8_ADC2_AWD1: TIM8_ETR is connected to ADC2 AWD1
+ * @arg TIM_TIM8_ADC2_AWD2: TIM8_ETR is connected to ADC2 AWD2
+ * @arg TIM_TIM8_ADC2_AWD3: TIM8_ETR is connected to ADC2 AWD3
+ * @arg TIM_TIM16_GPIO: TIM16 TI1 is connected to GPIO
+ * @arg TIM_TIM16_RTC: TIM16 TI1 is connected to RTC clock
+ * @arg TIM_TIM16_HSE: TIM16 TI1 is connected to HSE/32
+ * @arg TIM_TIM16_MCO: TIM16 TI1 is connected to MCO
+ * @param Remap2: specifies the second TIMremapping source (if any).
+ * This parameter can be one of the following values:
+ * @arg TIM_TIM1_ADC4_NONE: TIM1_ETR is not connected to any AWD (analog watchdog)
+ * @arg TIM_TIM1_ADC4_AWD1: TIM1_ETR is connected to ADC4 AWD1
+ * @arg TIM_TIM1_ADC4_AWD2: TIM1_ETR is connected to ADC4 AWD2
+ * @arg TIM_TIM1_ADC4_AWD3: TIM1_ETR is connected to ADC4 AWD3
+ * @arg TIM_TIM8_ADC3_NONE: TIM8_ETR is not connected to any AWD
+ * @arg TIM_TIM8_ADC3_AWD1: TIM8_ETR is connected to ADC3 AWD1
+ * @arg TIM_TIM8_ADC3_AWD2: TIM8_ETR is connected to ADC3 AWD2
+ * @arg TIM_TIM8_ADC3_AWD3: TIM8_ETR is connected to ADC3 AWD3
+ * @retval HAL status
+ */
+#else /* STM32F334x8 */
+/**
+ * @brief Configures the TIM1, TIM8 and TIM16 Remapping input capabilities.
+ * @param htim TIM handle.
+ * @param Remap1: specifies the first TIM remapping source.
+ * This parameter can be one of the following values:
+ * @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any AWD (analog watchdog)
+ * @arg TIM_TIM1_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
+ * @arg TIM_TIM1_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
+ * @arg TIM_TIM1_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
+ * @arg TIM_TIM16_GPIO: TIM16 TI1 is connected to GPIO
+ * @arg TIM_TIM16_RTC: TIM16 TI1 is connected to RTC clock
+ * @arg TIM_TIM16_HSE: TIM16 TI1 is connected to HSE/32
+ * @arg TIM_TIM16_MCO: TIM16 TI1 is connected to MCO
+ * @param Remap2: specifies the second TIMremapping source (if any).
+ * This parameter can be one of the following values:
+ * @arg TIM_TIM1_ADC2_NONE: TIM1_ETR is not connected to any AWD (analog watchdog)
+ * @arg TIM_TIM1_ADC2_AWD1: TIM1_ETR is connected to ADC2 AWD1
+ * @arg TIM_TIM1_ADC2_AWD2: TIM1_ETR is connected to ADC2 AWD2
+ * @arg TIM_TIM1_ADC2_AWD3: TIM1_ETR is connected to ADC2 AWD3
+ * @retval HAL status
+ */
+#endif /* STM32F303xE || STM32F398xx || */
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap1, uint32_t Remap2)
+{
+ __HAL_LOCK(htim);
+
+ /* Check parameters */
+ assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_REMAP(Remap1));
+ assert_param(IS_TIM_REMAP2(Remap2));
+
+ /* Set the Timer remapping configuration */
+ htim->Instance->OR = Remap1 | Remap2;
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx || STM32F334x8 */
+
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC) || \
+ defined(STM32F303x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC) || \
+ defined(STM32F303x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Configures the TIM1 and TIM16 Remapping input capabilities.
+ * @param htim TIM handle.
+ * @param Remap specifies the TIM remapping source.
+ * This parameter can be one of the following values:
+ * @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any AWD (analog watchdog)
+ * @arg TIM_TIM1_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
+ * @arg TIM_TIM1_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
+ * @arg TIM_TIM1_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
+ * @arg TIM_TIM16_GPIO: TIM16 TI1 is connected to GPIO
+ * @arg TIM_TIM16_RTC: TIM16 TI1 is connected to RTC_clock
+ * @arg TIM_TIM16_HSE: TIM16 TI1 is connected to HSE/32
+ * @arg TIM_TIM16_MCO: TIM16 TI1 is connected to MCO
+ * @retval HAL status
+ */
+#else /* STM32F373xC || STM32F378xx */
+/**
+ * @brief Configures the TIM2 and TIM14 Remapping input capabilities.
+ * @param htim TIM handle.
+ * @param Remap specifies the TIM remapping source.
+ * This parameter can be one of the following values:
+ * STM32F373xC, STM32F378xx:
+ * @arg TIM_TIM2_TIM8_TRGO: TIM8 TRGOUT is connected to TIM2_ITR1
+ * @arg TIM_TIM2_ETH_PTP: PTP trigger output is connected to TIM2_ITR1
+ * @arg TIM_TIM2_USBFS_SOF: OTG FS SOF is connected to the TIM2_ITR1 input
+ * @arg TIM_TIM2_USBHS_SOF: OTG HS SOF is connected to the TIM2_ITR1 input
+ * @arg TIM_TIM14_GPIO: TIM14 TI1 is connected to GPIO
+ * @arg TIM_TIM14_RTC: TIM14 TI1 is connected to RTC_clock
+ * @arg TIM_TIM14_HSE: TIM14 TI1 is connected to HSE/32
+ * @arg TIM_TIM14_MCO: TIM14 TI1 is connected to MCO
+ * @retval HAL status
+ */
+#endif /* STM32F302xE || */
+ /* STM32F302xC || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
+{
+ __HAL_LOCK(htim);
+
+ /* Check parameters */
+ assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_REMAP(Remap));
+
+ /* Set the Timer remapping configuration */
+ htim->Instance->OR = Remap;
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+#endif /* STM32F302xE || */
+ /* STM32F302xC || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
+ /* STM32F373xC || STM32F378xx */
+
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Group channel 5 and channel 1, 2 or 3
+ * @param htim TIM handle.
+ * @param Channels specifies the reference signal(s) the OC5REF is combined with.
+ * This parameter can be any combination of the following values:
+ * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
+ * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
+ * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
+ * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels)
+{
+ /* Check parameters */
+ assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_GROUPCH5(Channels));
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Clear GC5Cx bit fields */
+ htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3|TIM_CCR5_GC5C2|TIM_CCR5_GC5C1);
+
+ /* Set GC5Cx bit fields */
+ htim->Instance->CCR5 |= Channels;
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group8
+ * @{
+ */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Configures the OCRef clear feature
+ * @param htim TIM handle
+ * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
+ * contains the OCREF clear feature and parameters for the TIM peripheral.
+ * @param Channel specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1
+ * @arg TIM_CHANNEL_2: TIM Channel 2
+ * @arg TIM_CHANNEL_3: TIM Channel 3
+ * @arg TIM_CHANNEL_4: TIM Channel 4
+ * @arg TIM_Channel_5: TIM Channel 5
+ * @arg TIM_Channel_6: TIM Channel 6
+ * @note For STM32F302xC, STM32F302xE, STM32F303xC, STM32F303xE, STM32F358xx,
+ * STM32F398xx and STM32F303x8 up to 6 OC channels can be configured
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
+ TIM_ClearInputConfigTypeDef *sClearInputConfig,
+ uint32_t Channel)
+{
+ uint32_t tmpsmcr = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
+
+ /* Check input state */
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ switch (sClearInputConfig->ClearInputSource)
+ {
+ case TIM_CLEARINPUTSOURCE_NONE:
+ {
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = htim->Instance->SMCR;
+
+ /* Clear the OCREF clear selection bit */
+ tmpsmcr &= ~TIM_SMCR_OCCS;
+
+ /* Clear the ETR Bits */
+ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+
+ /* Set TIMx_SMCR */
+ htim->Instance->SMCR = tmpsmcr;
+ }
+ break;
+
+ case TIM_CLEARINPUTSOURCE_OCREFCLR:
+ {
+ /* Clear the OCREF clear selection bit */
+ htim->Instance->SMCR &= ~TIM_SMCR_OCCS;
+ }
+ break;
+
+ case TIM_CLEARINPUTSOURCE_ETR:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
+ assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
+ assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
+
+ TIM_ETR_SetConfig(htim->Instance,
+ sClearInputConfig->ClearInputPrescaler,
+ sClearInputConfig->ClearInputPolarity,
+ sClearInputConfig->ClearInputFilter);
+
+ /* Set the OCREF clear selection bit */
+ htim->Instance->SMCR |= TIM_SMCR_OCCS;
+ }
+ break;
+ default:
+ break;
+ }
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ if(sClearInputConfig->ClearInputState != RESET)
+ {
+ /* Enable the Ocref clear feature for Channel 1U */
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
+ }
+ else
+ {
+ /* Disable the Ocref clear feature for Channel 1U */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
+ }
+ }
+ break;
+ case TIM_CHANNEL_2:
+ {
+ if(sClearInputConfig->ClearInputState != RESET)
+ {
+ /* Enable the Ocref clear feature for Channel 2U */
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
+ }
+ else
+ {
+ /* Disable the Ocref clear feature for Channel 2U */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
+ }
+ }
+ break;
+ case TIM_CHANNEL_3:
+ {
+ if(sClearInputConfig->ClearInputState != RESET)
+ {
+ /* Enable the Ocref clear feature for Channel 3U */
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
+ }
+ else
+ {
+ /* Disable the Ocref clear feature for Channel 3U */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
+ }
+ }
+ break;
+ case TIM_CHANNEL_4:
+ {
+ if(sClearInputConfig->ClearInputState != RESET)
+ {
+ /* Enable the Ocref clear feature for Channel 4U */
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
+ }
+ else
+ {
+ /* Disable the Ocref clear feature for Channel 4U */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
+ }
+ }
+ break;
+ case TIM_CHANNEL_5:
+ {
+ if(sClearInputConfig->ClearInputState != RESET)
+ {
+ /* Enable the Ocref clear feature for Channel 1U */
+ htim->Instance->CCMR3 |= TIM_CCMR3_OC5CE;
+ }
+ else
+ {
+ /* Disable the Ocref clear feature for Channel 1U */
+ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5CE;
+ }
+ }
+ break;
+ case TIM_CHANNEL_6:
+ {
+ if(sClearInputConfig->ClearInputState != RESET)
+ {
+ /* Enable the Ocref clear feature for Channel 1U */
+ htim->Instance->CCMR3 |= TIM_CCMR3_OC6CE;
+ }
+ else
+ {
+ /* Disable the Ocref clear feature for Channel 1U */
+ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6CE;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group6 Extension Callbacks functions
+ * @brief Extension Callbacks functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Extended Callbacks functions #####
+ ==============================================================================
+ [..]
+ This section provides Extended TIM callback functions:
+ (+) Timer Commutation callback
+ (+) Timer Break callback
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Hall commutation changed callback in non blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIMEx_CommutationCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Hall Break detection callback in non blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIMEx_BreakCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Hall Break2 detection callback in non blocking mode
+ * @param htim: TIM handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIMEx_Break2Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
+ * @brief Extended Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Extended Peripheral State functions #####
+ ==============================================================================
+ [..]
+ This subsection permit to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the TIM Hall Sensor interface state
+ * @param htim TIM Hall Sensor handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Private_Functions
+ * @{
+ */
+/**
+ * @brief TIM DMA Commutation callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ htim->State= HAL_TIM_STATE_READY;
+
+ HAL_TIMEx_CommutationCallback(htim);
+}
+
+/**
+ * @brief Enables or disables the TIM Capture Compare Channel xN.
+ * @param TIMx to select the TIM peripheral
+ * @param Channel specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1
+ * @arg TIM_CHANNEL_2: TIM Channel 2
+ * @arg TIM_CHANNEL_3: TIM Channel 3
+ * @param ChannelNState specifies the TIM Channel CCxNE bit new state.
+ * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
+ * @retval None
+ */
+static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
+{
+ uint32_t tmp = 0U;
+
+ tmp = TIM_CCER_CC1NE << Channel;
+
+ /* Reset the CCxNE Bit */
+ TIMx->CCER &= ~tmp;
+
+ /* Set or reset the CCxNE Bit */
+ TIMx->CCER |= (uint32_t)(ChannelNState << Channel);
+}
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Timer Ouput Compare 5 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config The ouput configuration structure
+ * @retval None
+ */
+static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
+ TIM_OC_InitTypeDef *OC_Config)
+{
+ uint32_t tmpccmrx = 0U;
+ uint32_t tmpccer = 0U;
+ uint32_t tmpcr2 = 0U;
+
+ /* Disable the output: Reset the CCxE Bit */
+ TIMx->CCER &= ~TIM_CCER_CC5E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+ /* Get the TIMx CCMR1 register value */
+ tmpccmrx = TIMx->CCMR3;
+
+ /* Reset the Output Compare Mode Bits */
+ tmpccmrx &= ~(TIM_CCMR3_OC5M);
+ /* Select the Output Compare Mode */
+ tmpccmrx |= OC_Config->OCMode;
+
+ /* Reset the Output Polarity level */
+ tmpccer &= ~TIM_CCER_CC5P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (OC_Config->OCPolarity << 16U);
+
+ if(IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ /* Reset the Output Compare IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS5;
+ /* Set the Output Idle state */
+ tmpcr2 |= (OC_Config->OCIdleState << 8U);
+ }
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR3 */
+ TIMx->CCMR3 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR5 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Timer Ouput Compare 6 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config The ouput configuration structure
+ * @retval None
+ */
+static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
+ TIM_OC_InitTypeDef *OC_Config)
+{
+ uint32_t tmpccmrx = 0U;
+ uint32_t tmpccer = 0U;
+ uint32_t tmpcr2 = 0U;
+
+ /* Disable the output: Reset the CCxE Bit */
+ TIMx->CCER &= ~TIM_CCER_CC6E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+ /* Get the TIMx CCMR1 register value */
+ tmpccmrx = TIMx->CCMR3;
+
+ /* Reset the Output Compare Mode Bits */
+ tmpccmrx &= ~(TIM_CCMR3_OC6M);
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (OC_Config->OCMode << 8U);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= (uint32_t)~TIM_CCER_CC6P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (OC_Config->OCPolarity << 20U);
+
+ if(IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ /* Reset the Output Compare IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS6;
+ /* Set the Output Idle state */
+ tmpcr2 |= (OC_Config->OCIdleState << 10U);
+ }
+
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR3 */
+ TIMx->CCMR3 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR6 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+/**
+ * @}
+ */
+
+#endif /* HAL_TIM_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_timebase_rtc_alarm_template.c b/Src/stm32f3xx_hal_timebase_rtc_alarm_template.c
new file mode 100644
index 0000000..8f288b7
--- /dev/null
+++ b/Src/stm32f3xx_hal_timebase_rtc_alarm_template.c
@@ -0,0 +1,315 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_timebase_rtc_alarm_template.c
+ * @brief HAL time base based on the hardware RTC_ALARM Template.
+ *
+ * This file override the native HAL time base functions (defined as weak)
+ * to use the RTC ALARM for time base generation:
+ * + Intializes the RTC peripheral to increment the seconds registers each 1ms
+ * + The alarm is configured to assert an interrupt when the RTC reaches 1ms
+ * + HAL_IncTick is called at each Alarm event and the time is reset to 00:00:00
+ * + HSE (default), LSE or LSI can be selected as RTC clock source
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ This file must be copied to the application folder and modified as follows:
+ (#) Rename it to 'stm32f3xx_hal_timebase_rtc_alarm.c'
+ (#) Add this file and the RTC HAL drivers to your project and uncomment
+ HAL_RTC_MODULE_ENABLED define in stm32f3xx_hal_conf.h
+
+ [..]
+ (@) HAL RTC alarm and HAL RTC wakeup drivers canÂ’t be used with low power modes:
+ The wake up capability of the RTC may be intrusive in case of prior low power mode
+ configuration requiring different wake up sources.
+ Application/Example behavior is no more guaranteed
+ (@) The stm32f3xx_hal_timebase_tim use is recommended for the Applications/Examples
+ requiring low power modes
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup HAL_TimeBase_RTC_Alarm_Template HAL TimeBase RTC Alarm Template
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* Uncomment the line below to select the appropriate RTC Clock source for your application:
+ + RTC_CLOCK_SOURCE_HSE: can be selected for applications requiring timing precision.
+ + RTC_CLOCK_SOURCE_LSE: can be selected for applications with low constraint on timing
+ precision.
+ + RTC_CLOCK_SOURCE_LSI: can be selected for applications with low constraint on timing
+ precision.
+ */
+#define RTC_CLOCK_SOURCE_HSE
+/* #define RTC_CLOCK_SOURCE_LSE */
+/* #define RTC_CLOCK_SOURCE_LSI */
+
+#if defined(RTC_CLOCK_SOURCE_HSE)
+ #define RTC_ASYNCH_PREDIV 49U
+ #define RTC_SYNCH_PREDIV 4U
+#elif defined(RTC_CLOCK_SOURCE_LSE)
+ #define RTC_ASYNCH_PREDIV 0U
+ #define RTC_SYNCH_PREDIV 31U
+#else /*RTC_CLOCK_SOURCE_LSI */
+ #define RTC_ASYNCH_PREDIV 0U
+ #define RTC_SYNCH_PREDIV 39U
+#endif /* RTC_CLOCK_SOURCE_HSE */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+RTC_HandleTypeDef hRTC_Handle;
+/* Private function prototypes -----------------------------------------------*/
+void RTC_Alarm_IRQHandler(void);
+/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @brief This function configures the RTC_ALARMA as a time base source.
+ * The time source is configured to have 1ms time base with a dedicated
+ * Tick interrupt priority.
+ * @note This function is called automatically at the beginning of program after
+ * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
+ * @param TickPriority Tick interrupt priority.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority)
+{
+ __IO uint32_t counter = 0U;
+
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
+
+#ifdef RTC_CLOCK_SOURCE_LSE
+ /* Configue LSE as RTC clock soucre */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+ RCC_OscInitStruct.LSEState = RCC_LSE_ON;
+ PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
+#elif defined (RTC_CLOCK_SOURCE_LSI)
+ /* Configue LSI as RTC clock soucre */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+ RCC_OscInitStruct.LSIState = RCC_LSI_ON;
+ PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
+#elif defined (RTC_CLOCK_SOURCE_HSE)
+ /* Configue HSE as RTC clock soucre */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+ PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_HSE_DIV32;
+#else
+#error Please select the RTC Clock source
+#endif /* RTC_CLOCK_SOURCE_LSE */
+
+ if(HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK)
+ {
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
+ if(HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) == HAL_OK)
+ {
+ /* Enable RTC Clock */
+ __HAL_RCC_RTC_ENABLE();
+ /* The time base should be 1ms
+ Time base = ((RTC_ASYNCH_PREDIV + 1U) * (RTC_SYNCH_PREDIV + 1U)) / RTC_CLOCK
+ HSE/32 as RTC clock and HSE 8MHz
+ Time base = ((49U + 1U) * (4U + 1U)) / 250kHz
+ = 1ms
+ LSE as RTC clock
+ Time base = ((31U + 1U) * (0U + 1U)) / 32.768KHz
+ = ~1ms
+ LSI as RTC clock
+ Time base = ((39U + 1U) * (0U + 1U)) / 40KHz
+ = 1ms
+ */
+ hRTC_Handle.Instance = RTC;
+ hRTC_Handle.Init.HourFormat = RTC_HOURFORMAT_24;
+ hRTC_Handle.Init.AsynchPrediv = RTC_ASYNCH_PREDIV;
+ hRTC_Handle.Init.SynchPrediv = RTC_SYNCH_PREDIV;
+ hRTC_Handle.Init.OutPut = RTC_OUTPUT_DISABLE;
+ hRTC_Handle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
+ hRTC_Handle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
+ HAL_RTC_Init(&hRTC_Handle);
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
+
+ /* Disable the Alarm A interrupt */
+ __HAL_RTC_ALARMA_DISABLE(&hRTC_Handle);
+
+ /* Clear flag alarm A */
+ __HAL_RTC_ALARM_CLEAR_FLAG(&hRTC_Handle, RTC_FLAG_ALRAF);
+
+ counter = 0U;
+ /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
+ while(__HAL_RTC_ALARM_GET_FLAG(&hRTC_Handle, RTC_FLAG_ALRAWF) == RESET)
+ {
+ if(counter++ == (SystemCoreClock /48U)) /* Timeout = ~ 1s */
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ hRTC_Handle.Instance->ALRMAR = 0x01U;
+
+ /* Configure the Alarm state: Enable Alarm */
+ __HAL_RTC_ALARMA_ENABLE(&hRTC_Handle);
+ /* Configure the Alarm interrupt */
+ __HAL_RTC_ALARM_ENABLE_IT(&hRTC_Handle, RTC_IT_ALRA);
+
+ /* RTC Alarm Interrupt Configuration: EXTI configuration */
+ __HAL_RTC_ALARM_EXTI_ENABLE_IT();
+ __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();
+
+ /* Check if the Initialization mode is set */
+ if((hRTC_Handle.Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
+ {
+ /* Set the Initialization mode */
+ hRTC_Handle.Instance->ISR = (uint32_t)RTC_INIT_MASK;
+ counter = 0U;
+ while((hRTC_Handle.Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
+ {
+ if(counter++ == (SystemCoreClock /48U)) /* Timeout = ~ 1s */
+ {
+ return HAL_ERROR;
+ }
+ }
+ }
+ hRTC_Handle.Instance->DR = 0U;
+ hRTC_Handle.Instance->TR = 0U;
+
+ hRTC_Handle.Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
+
+ HAL_NVIC_SetPriority(RTC_Alarm_IRQn, TickPriority, 0U);
+ HAL_NVIC_EnableIRQ(RTC_Alarm_IRQn);
+ return HAL_OK;
+ }
+ }
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Suspend Tick increment.
+ * @note Disable the tick increment by disabling RTC ALARM interrupt.
+ * @param None
+ * @retval None
+ */
+void HAL_SuspendTick(void)
+{
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
+ /* Disable RTC ALARM update Interrupt */
+ __HAL_RTC_ALARM_DISABLE_IT(&hRTC_Handle, RTC_IT_ALRA);
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
+}
+
+/**
+ * @brief Resume Tick increment.
+ * @note Enable the tick increment by Enabling RTC ALARM interrupt.
+ * @param None
+ * @retval None
+ */
+void HAL_ResumeTick(void)
+{
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
+ /* Enable RTC ALARM Update interrupt */
+ __HAL_RTC_ALARM_ENABLE_IT(&hRTC_Handle, RTC_IT_ALRA);
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
+}
+
+/**
+ * @brief ALARM A Event Callback in non blocking mode
+ * @note This function is called when RTC_ALARM interrupt took place, inside
+ * RTC_Alarm_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
+ * a global variable "uwTick" used as application time base.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
+{
+ __IO uint32_t counter = 0U;
+
+ HAL_IncTick();
+
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Set the Initialization mode */
+ hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK;
+
+ while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
+ {
+ if(counter++ == (SystemCoreClock /48U)) /* Timeout = ~ 1s */
+ {
+ break;
+ }
+ }
+
+ hrtc->Instance->DR = 0U;
+ hrtc->Instance->TR = 0U;
+
+ hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+}
+
+/**
+ * @brief This function handles RTC ALARM interrupt request.
+ * @param None
+ * @retval None
+ */
+void RTC_Alarm_IRQHandler(void)
+{
+ HAL_RTC_AlarmIRQHandler(&hRTC_Handle);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_timebase_rtc_wakeup_template.c b/Src/stm32f3xx_hal_timebase_rtc_wakeup_template.c
new file mode 100644
index 0000000..c823c9f
--- /dev/null
+++ b/Src/stm32f3xx_hal_timebase_rtc_wakeup_template.c
@@ -0,0 +1,294 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_timebase_rtc_wakeup_template.c
+ * @brief HAL time base based on the hardware RTC_WAKEUP Template.
+ *
+ * This file overrides the native HAL time base functions (defined as weak)
+ * to use the RTC WAKEUP for the time base generation:
+ * + Intializes the RTC peripheral and configures the wakeup timer to be
+ * incremented each 1ms
+ * + The wakeup feature is configured to assert an interrupt each 1ms
+ * + HAL_IncTick is called inside the HAL_RTCEx_WakeUpTimerEventCallback
+ * + HSE (default), LSE or LSI can be selected as RTC clock source
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ This file must be copied to the application folder and modified as follows:
+ (#) Rename it to 'stm32f3xx_hal_timebase_rtc_wakeup.c'
+ (#) Add this file and the RTC HAL drivers to your project and uncomment
+ HAL_RTC_MODULE_ENABLED define in stm32f3xx_hal_conf.h
+
+ [..]
+ (@) HAL RTC alarm and HAL RTC wakeup drivers canÂ’t be used with low power modes:
+ The wake up capability of the RTC may be intrusive in case of prior low power mode
+ configuration requiring different wake up sources.
+ Application/Example behavior is no more guaranteed
+ (@) The stm32f3xx_hal_timebase_tim use is recommended for the Applications/Examples
+ requiring low power modes
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup HAL_TimeBase_RTC_WakeUp_Template HAL TimeBase RTC WakeUp Template
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* Uncomment the line below to select the appropriate RTC Clock source for your application:
+ + RTC_CLOCK_SOURCE_HSE: can be selected for applications requiring timing precision.
+ + RTC_CLOCK_SOURCE_LSE: can be selected for applications with low constraint on timing
+ precision.
+ + RTC_CLOCK_SOURCE_LSI: can be selected for applications with low constraint on timing
+ precision.
+ */
+#define RTC_CLOCK_SOURCE_HSE
+/* #define RTC_CLOCK_SOURCE_LSE */
+/* #define RTC_CLOCK_SOURCE_LSI */
+
+#if defined(RTC_CLOCK_SOURCE_HSE)
+ #define RTC_ASYNCH_PREDIV 49U
+ #define RTC_SYNCH_PREDIV 4U
+#elif define(RTC_CLOCK_SOURCE_LSE)
+ #define RTC_ASYNCH_PREDIV 0U
+ #define RTC_SYNCH_PREDIV 31U
+#else /* RTC_CLOCK_SOURCE_LSI */
+ #define RTC_ASYNCH_PREDIV 0U
+ #define RTC_SYNCH_PREDIV 39U
+#endif /* RTC_CLOCK_SOURCE_HSE */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+RTC_HandleTypeDef hRTC_Handle;
+
+/* Private function prototypes -----------------------------------------------*/
+void RTC_WKUP_IRQHandler(void);
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @brief This function configures the RTC_WKUP as a time base source.
+ * The time source is configured to have 1ms time base with a dedicated
+ * Tick interrupt priority.
+ * Wakeup Time base = ((RTC_ASYNCH_PREDIV + 1) * (RTC_SYNCH_PREDIV + 1)) / RTC_CLOCK
+ = 1ms
+ * Wakeup Time = WakeupTimebase * WakeUpCounter (0 + 1)
+ = 1 ms
+ * @note This function is called automatically at the beginning of program after
+ * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
+ * @param TickPriority Tick interrupt priority.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority)
+{
+ __IO uint32_t counter = 0U;
+
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
+
+#ifdef RTC_CLOCK_SOURCE_LSE
+ /* Configue LSE as RTC clock soucre */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+ RCC_OscInitStruct.LSEState = RCC_LSE_ON;
+ PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
+#elif defined (RTC_CLOCK_SOURCE_LSI)
+ /* Configue LSI as RTC clock soucre */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+ RCC_OscInitStruct.LSIState = RCC_LSI_ON;
+ PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
+#elif defined (RTC_CLOCK_SOURCE_HSE)
+ /* Configue HSE as RTC clock soucre */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+ PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_HSE_DIV32;
+#else
+#error Please select the RTC Clock source
+#endif /* RTC_CLOCK_SOURCE_LSE */
+
+ if(HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK)
+ {
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
+ if(HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) == HAL_OK)
+ {
+ /* Enable RTC Clock */
+ __HAL_RCC_RTC_ENABLE();
+ /* The time base should be 1ms
+ Time base = ((RTC_ASYNCH_PREDIV + 1U) * (RTC_SYNCH_PREDIV + 1U)) / RTC_CLOCK
+ HSE/32 as RTC clock and HSE 8MHz
+ Time base = ((49U + 1U) * (4U + 1U)) / 250kHz
+ = 1ms
+ LSE as RTC clock
+ Time base = ((31U + 1U) * (0U + 1U)) / 32.768Khz
+ = ~1ms
+ LSI as RTC clock
+ Time base = ((39U + 1U) * (0U + 1U)) / 40Khz
+ = 1ms
+ */
+ hRTC_Handle.Instance = RTC;
+ hRTC_Handle.Init.HourFormat = RTC_HOURFORMAT_24;
+ hRTC_Handle.Init.AsynchPrediv = RTC_ASYNCH_PREDIV;
+ hRTC_Handle.Init.SynchPrediv = RTC_SYNCH_PREDIV;
+ hRTC_Handle.Init.OutPut = RTC_OUTPUT_DISABLE;
+ hRTC_Handle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
+ hRTC_Handle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
+ HAL_RTC_Init(&hRTC_Handle);
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
+
+ /* Disable the Wake-up Timer */
+ __HAL_RTC_WAKEUPTIMER_DISABLE(&hRTC_Handle);
+
+ /* In case of interrupt mode is used, the interrupt source must disabled */
+ __HAL_RTC_WAKEUPTIMER_DISABLE_IT(&hRTC_Handle,RTC_IT_WUT);
+
+ /* Wait till RTC WUTWF flag is set */
+ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hRTC_Handle, RTC_FLAG_WUTWF) == RESET)
+ {
+ if(counter++ == (SystemCoreClock /48U))
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /* Clear PWR wake up Flag */
+ __HAL_PWR_CLEAR_FLAG(PWR_FLAG_WU);
+
+ /* Clear RTC Wake Up timer Flag */
+ __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&hRTC_Handle, RTC_FLAG_WUTF);
+
+ /* Configure the Wake-up Timer counter */
+ hRTC_Handle.Instance->WUTR = 0U;
+
+ /* Clear the Wake-up Timer clock source bits in CR register */
+ hRTC_Handle.Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
+
+ /* Configure the clock source */
+ hRTC_Handle.Instance->CR |= (uint32_t)RTC_WAKEUPCLOCK_CK_SPRE_16BITS;
+
+ /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */
+ __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
+
+ __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
+
+ /* Configure the Interrupt in the RTC_CR register */
+ __HAL_RTC_WAKEUPTIMER_ENABLE_IT(&hRTC_Handle,RTC_IT_WUT);
+
+ /* Enable the Wake-up Timer */
+ __HAL_RTC_WAKEUPTIMER_ENABLE(&hRTC_Handle);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
+
+ HAL_NVIC_SetPriority(RTC_WKUP_IRQn, TickPriority, 0U);
+ HAL_NVIC_EnableIRQ(RTC_WKUP_IRQn);
+ return HAL_OK;
+ }
+ }
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Suspend Tick increment.
+ * @note Disable the tick increment by disabling RTC_WKUP interrupt.
+ * @param None
+ * @retval None
+ */
+void HAL_SuspendTick(void)
+{
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
+ /* Disable WAKE UP TIMER Interrupt */
+ __HAL_RTC_WAKEUPTIMER_DISABLE_IT(&hRTC_Handle, RTC_IT_WUT);
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
+}
+
+/**
+ * @brief Resume Tick increment.
+ * @note Enable the tick increment by Enabling RTC_WKUP interrupt.
+ * @param None
+ * @retval None
+ */
+void HAL_ResumeTick(void)
+{
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
+ /* Enable WAKE UP TIMER interrupt */
+ __HAL_RTC_WAKEUPTIMER_ENABLE_IT(&hRTC_Handle, RTC_IT_WUT);
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
+}
+
+/**
+ * @brief Wake Up Timer Event Callback in non blocking mode
+ * @note This function is called when RTC_WKUP interrupt took place, inside
+ * RTC_WKUP_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
+ * a global variable "uwTick" used as application time base.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
+{
+ HAL_IncTick();
+}
+
+/**
+ * @brief This function handles WAKE UP TIMER interrupt request.
+ * @param None
+ * @retval None
+ */
+void RTC_WKUP_IRQHandler(void)
+{
+ HAL_RTCEx_WakeUpTimerIRQHandler(&hRTC_Handle);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_timebase_tim_template.c b/Src/stm32f3xx_hal_timebase_tim_template.c
new file mode 100644
index 0000000..e33dd82
--- /dev/null
+++ b/Src/stm32f3xx_hal_timebase_tim_template.c
@@ -0,0 +1,184 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_timebase_tim_template.c
+ * @brief HAL time base based on the hardware TIM Template.
+ *
+ * This file override the native HAL time base functions (defined as weak)
+ * the TIM time base:
+ * + Intializes the TIM peripheral generate a Period elapsed Event each 1ms
+ * + HAL_IncTick is called inside HAL_TIM_PeriodElapsedCallback ie each 1ms
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup HAL_TimeBase_TIM
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+TIM_HandleTypeDef TimHandle;
+/* Private function prototypes -----------------------------------------------*/
+void TIM6_DAC_IRQHandler(void);
+/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @brief This function configures the TIM6 as a time base source.
+ * The time source is configured to have 1ms time base with a dedicated
+ * Tick interrupt priority.
+ * @note This function is called automatically at the beginning of program after
+ * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
+ * @param TickPriority Tick interrupt priority.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority)
+{
+ RCC_ClkInitTypeDef clkconfig;
+ uint32_t uwTimclock, uwAPB1Prescaler = 0U;
+ uint32_t uwPrescalerValue = 0U;
+ uint32_t pFLatency;
+
+ /*Configure the TIM6 IRQ priority */
+ HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority ,0U);
+
+ /* Enable the TIM6 global Interrupt */
+ HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
+
+ /* Enable TIM6 clock */
+ __HAL_RCC_TIM6_CLK_ENABLE();
+
+ /* Get clock configuration */
+ HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
+
+ /* Get APB1 prescaler */
+ uwAPB1Prescaler = clkconfig.APB1CLKDivider;
+
+ /* Compute TIM6 clock */
+ if (uwAPB1Prescaler == RCC_HCLK_DIV1)
+ {
+ uwTimclock = HAL_RCC_GetPCLK1Freq();
+ }
+ else
+ {
+ uwTimclock = 2U*HAL_RCC_GetPCLK1Freq();
+ }
+
+ /* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */
+ uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);
+
+ /* Initialize TIM6 */
+ TimHandle.Instance = TIM6;
+
+ /* Initialize TIMx peripheral as follow:
+ + Period = [(TIM6CLK/1000U) - 1]. to have a (1U/1000U) s time base.
+ + Prescaler = (uwTimclock/1000000U - 1U) to have a 1MHz counter clock.
+ + ClockDivision = 0
+ + Counter direction = Up
+ */
+ TimHandle.Init.Period = (1000000U / 1000U) - 1U;
+ TimHandle.Init.Prescaler = uwPrescalerValue;
+ TimHandle.Init.ClockDivision = 0U;
+ TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
+ TimHandle.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+ if(HAL_TIM_Base_Init(&TimHandle) == HAL_OK)
+ {
+ /* Start the TIM time Base generation in interrupt mode */
+ return HAL_TIM_Base_Start_IT(&TimHandle);
+ }
+
+ /* Return function status */
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Suspend Tick increment.
+ * @note Disable the tick increment by disabling TIM6 update interrupt.
+ * @param None
+ * @retval None
+ */
+void HAL_SuspendTick(void)
+{
+ /* Disable TIM6 update Interrupt */
+ __HAL_TIM_DISABLE_IT(&TimHandle, TIM_IT_UPDATE);
+}
+
+/**
+ * @brief Resume Tick increment.
+ * @note Enable the tick increment by Enabling TIM6 update interrupt.
+ * @param None
+ * @retval None
+ */
+void HAL_ResumeTick(void)
+{
+ /* Enable TIM6 Update interrupt */
+ __HAL_TIM_ENABLE_IT(&TimHandle, TIM_IT_UPDATE);
+}
+
+/**
+ * @brief Period elapsed callback in non blocking mode
+ * @note This function is called when TIM6 interrupt took place, inside
+ * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
+ * a global variable "uwTick" used as application time base.
+ * @param htim TIM handle
+ * @retval None
+ */
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
+{
+ HAL_IncTick();
+}
+
+/**
+ * @brief This function handles TIM interrupt request.
+ * @param None
+ * @retval None
+ */
+void TIM6_DAC_IRQHandler(void)
+{
+ HAL_TIM_IRQHandler(&TimHandle);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_tsc.c b/Src/stm32f3xx_hal_tsc.c
new file mode 100644
index 0000000..62704a0
--- /dev/null
+++ b/Src/stm32f3xx_hal_tsc.c
@@ -0,0 +1,873 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_tsc.c
+ * @author MCD Application Team
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Touch Sensing Controller (TSC) peripheral:
+ * + Initialization and De-initialization
+ * + Channel IOs, Shield IOs and Sampling IOs configuration
+ * + Start and Stop an acquisition
+ * + Read acquisition result
+ * + Interrupts and flags management
+ *
+ @verbatim
+================================================================================
+ ##### TSC specific features #####
+================================================================================
+ [..]
+ (#) Proven and robust surface charge transfer acquisition principle
+
+ (#) Supports up to 3 capacitive sensing channels per group
+
+ (#) Capacitive sensing channels can be acquired in parallel offering a very good
+ response time
+
+ (#) Spread spectrum feature to improve system robustness in noisy environments
+
+ (#) Full hardware management of the charge transfer acquisition sequence
+
+ (#) Programmable charge transfer frequency
+
+ (#) Programmable sampling capacitor I/O pin
+
+ (#) Programmable channel I/O pin
+
+ (#) Programmable max count value to avoid long acquisition when a channel is faulty
+
+ (#) Dedicated end of acquisition and max count error flags with interrupt capability
+
+ (#) One sampling capacitor for up to 3 capacitive sensing channels to reduce the system
+ components
+
+ (#) Compatible with proximity, touchkey, linear and rotary touch sensor implementation
+
+
+ ##### How to use this driver #####
+================================================================================
+ [..]
+ (#) Enable the TSC interface clock using __HAL_RCC_TSC_CLK_ENABLE() macro.
+
+ (#) GPIO pins configuration
+ (++) Enable the clock for the TSC GPIOs using __HAL_RCC_GPIOx_CLK_ENABLE() macro.
+ (++) Configure the TSC pins used as sampling IOs in alternate function output Open-Drain mode,
+ and TSC pins used as channel/shield IOs in alternate function output Push-Pull mode
+ using HAL_GPIO_Init() function.
+
+ (#) Interrupts configuration
+ (++) Configure the NVIC (if the interrupt model is used) using HAL_NVIC_SetPriority()
+ and HAL_NVIC_EnableIRQ() and function.
+
+ (#) TSC configuration
+ (++) Configure all TSC parameters and used TSC IOs using HAL_TSC_Init() function.
+
+
+ *** Acquisition sequence ***
+ ===================================
+ [..]
+ (+) Discharge all IOs using HAL_TSC_IODischarge() function.
+ (+) Wait a certain time allowing a good discharge of all capacitors. This delay depends
+ of the sampling capacitor and electrodes design.
+ (+) Select the channel IOs to be acquired using HAL_TSC_IOConfig() function.
+ (+) Launch the acquisition using either HAL_TSC_Start() or HAL_TSC_Start_IT() function.
+ If the synchronized mode is selected, the acquisition will start as soon as the signal
+ is received on the synchro pin.
+ (+) Wait the end of acquisition using either HAL_TSC_PollForAcquisition() or
+ HAL_TSC_GetState() function or using WFI instruction for example.
+ (+) Check the group acquisition status using HAL_TSC_GroupGetStatus() function.
+ (+) Read the acquisition value using HAL_TSC_GroupGetValue() function.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*
+ Addition Table:
+ Table 1. IOs for the STM32F3xx devices
+ +--------------------------------+
+ | IOs | TSC functions |
+ |--------------|-----------------|
+ | PA0 (AF) | TSC_G1_IO1 |
+ | PA1 (AF) | TSC_G1_IO2 |
+ | PA2 (AF) | TSC_G1_IO3 |
+ | PA3 (AF) | TSC_G1_IO4 |
+ |--------------|-----------------|
+ | PA4 (AF) | TSC_G2_IO1 |
+ | PA5 (AF) | TSC_G2_IO2 |
+ | PA6 (AF) | TSC_G2_IO3 |
+ | PA7 (AF) | TSC_G2_IO4 |
+ |--------------|-----------------|
+ | PC5 (AF) | TSC_G3_IO1 |
+ | PB0 (AF) | TSC_G3_IO2 |
+ | PB1 (AF) | TSC_G3_IO3 |
+ | PB2 (AF) | TSC_G3_IO4 |
+ |--------------|-----------------|
+ | PA9 (AF) | TSC_G4_IO1 |
+ | PA10 (AF) | TSC_G4_IO2 |
+ | PA13 (AF) | TSC_G4_IO3 |
+ | PA14 (AF) | TSC_G4_IO4 |
+ |--------------|-----------------|
+ | PB3 (AF) | TSC_G5_IO1 |
+ | PB4 (AF) | TSC_G5_IO2 |
+ | PB6 (AF) | TSC_G5_IO3 |
+ | PB7 (AF) | TSC_G5_IO4 |
+ |--------------|-----------------|
+ | PB11 (AF) | TSC_G6_IO1 |
+ | PB12 (AF) | TSC_G6_IO2 |
+ | PB13 (AF) | TSC_G6_IO3 |
+ | PB14 (AF) | TSC_G6_IO4 |
+ |--------------|-----------------|
+ | PE2 (AF) | TSC_G7_IO1 |
+ | PE3 (AF) | TSC_G7_IO2 |
+ | PE4 (AF) | TSC_G7_IO3 |
+ | PE5 (AF) | TSC_G7_IO4 |
+ |--------------|-----------------|
+ | PD12 (AF) | TSC_G8_IO1 |
+ | PD13 (AF) | TSC_G8_IO2 |
+ | PD14 (AF) | TSC_G8_IO3 |
+ | PD15 (AF) | TSC_G8_IO4 |
+ |--------------|-----------------|
+ | PB8 (AF) | TSC_SYNC |
+ | PB10 (AF) | |
+ +--------------------------------+
+ TSC peripheral alternate functions are mapped on AF3.
+
+*/
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup TSC TSC
+ * @brief HAL TSC module driver
+ * @{
+ */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static uint32_t TSC_extract_groups(uint32_t iomask);
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup TSC_Exported_Functions Exported Functions
+ * @{
+ */
+
+/** @defgroup TSC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize and configure the TSC.
+ (+) De-initialize the TSC.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the TSC peripheral according to the specified parameters
+ * in the TSC_InitTypeDef structure and initialize the associated handle.
+ * @param htsc TSC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc)
+{
+ /* Check TSC handle allocation */
+ if (htsc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+ assert_param(IS_TSC_CTPH(htsc->Init.CTPulseHighLength));
+ assert_param(IS_TSC_CTPL(htsc->Init.CTPulseLowLength));
+ assert_param(IS_TSC_SS(htsc->Init.SpreadSpectrum));
+ assert_param(IS_TSC_SSD(htsc->Init.SpreadSpectrumDeviation));
+ assert_param(IS_TSC_SS_PRESC(htsc->Init.SpreadSpectrumPrescaler));
+ assert_param(IS_TSC_PG_PRESC(htsc->Init.PulseGeneratorPrescaler));
+ assert_param(IS_TSC_MCV(htsc->Init.MaxCountValue));
+ assert_param(IS_TSC_IODEF(htsc->Init.IODefaultMode));
+ assert_param(IS_TSC_SYNC_POL(htsc->Init.SynchroPinPolarity));
+ assert_param(IS_TSC_ACQ_MODE(htsc->Init.AcquisitionMode));
+ assert_param(IS_TSC_MCE_IT(htsc->Init.MaxCountInterrupt));
+
+ if(htsc->State == HAL_TSC_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htsc->Lock = HAL_UNLOCKED;
+ }
+
+ /* Initialize the TSC state */
+ htsc->State = HAL_TSC_STATE_BUSY;
+
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX */
+ HAL_TSC_MspInit(htsc);
+
+ /*--------------------------------------------------------------------------*/
+ /* Set TSC parameters */
+
+ /* Enable TSC */
+ htsc->Instance->CR = TSC_CR_TSCE;
+
+ /* Set all functions */
+ htsc->Instance->CR |= (htsc->Init.CTPulseHighLength |
+ htsc->Init.CTPulseLowLength |
+ (uint32_t)(htsc->Init.SpreadSpectrumDeviation << 17U) |
+ htsc->Init.SpreadSpectrumPrescaler |
+ htsc->Init.PulseGeneratorPrescaler |
+ htsc->Init.MaxCountValue |
+ htsc->Init.SynchroPinPolarity |
+ htsc->Init.AcquisitionMode);
+
+ /* Spread spectrum */
+ if (htsc->Init.SpreadSpectrum == ENABLE)
+ {
+ htsc->Instance->CR |= TSC_CR_SSE;
+ }
+
+ /* Disable Schmitt trigger hysteresis on all used TSC IOs */
+ htsc->Instance->IOHCR = (uint32_t)(~(htsc->Init.ChannelIOs | htsc->Init.ShieldIOs | htsc->Init.SamplingIOs));
+
+ /* Set channel and shield IOs */
+ htsc->Instance->IOCCR = (htsc->Init.ChannelIOs | htsc->Init.ShieldIOs);
+
+ /* Set sampling IOs */
+ htsc->Instance->IOSCR = htsc->Init.SamplingIOs;
+
+ /* Set the groups to be acquired */
+ htsc->Instance->IOGCSR = TSC_extract_groups(htsc->Init.ChannelIOs);
+
+ /* Disable interrupts */
+ htsc->Instance->IER &= (uint32_t)(~(TSC_IT_EOA | TSC_IT_MCE));
+
+ /* Clear flags */
+ htsc->Instance->ICR = (TSC_FLAG_EOA | TSC_FLAG_MCE);
+
+ /*--------------------------------------------------------------------------*/
+
+ /* Initialize the TSC state */
+ htsc->State = HAL_TSC_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Deinitialize the TSC peripheral registers to their default reset values.
+ * @param htsc TSC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef* htsc)
+{
+ /* Check TSC handle allocation */
+ if (htsc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+
+ /* Change TSC state */
+ htsc->State = HAL_TSC_STATE_BUSY;
+
+ /* DeInit the low level hardware */
+ HAL_TSC_MspDeInit(htsc);
+
+ /* Change TSC state */
+ htsc->State = HAL_TSC_STATE_RESET;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(htsc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the TSC MSP.
+ * @param htsc pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @retval None
+ */
+__weak void HAL_TSC_MspInit(TSC_HandleTypeDef* htsc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htsc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TSC_MspInit could be implemented in the user file.
+ */
+}
+
+/**
+ * @brief DeInitialize the TSC MSP.
+ * @param htsc pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @retval None
+ */
+__weak void HAL_TSC_MspDeInit(TSC_HandleTypeDef* htsc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htsc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TSC_MspDeInit could be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TSC_Exported_Functions_Group2 Input and Output operation functions
+ * @brief Input and Output operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO Operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Start acquisition in polling mode.
+ (+) Start acquisition in interrupt mode.
+ (+) Stop conversion in polling mode.
+ (+) Stop conversion in interrupt mode.
+ (+) Poll for acquisition completed.
+ (+) Get group acquisition status.
+ (+) Get group acquisition value.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Start the acquisition.
+ * @param htsc pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef* htsc)
+{
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(htsc);
+
+ /* Change TSC state */
+ htsc->State = HAL_TSC_STATE_BUSY;
+
+ /* Clear interrupts */
+ __HAL_TSC_DISABLE_IT(htsc, (TSC_IT_EOA | TSC_IT_MCE));
+
+ /* Clear flags */
+ __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
+
+ /* Set touch sensing IOs not acquired to the specified IODefaultMode */
+ if (htsc->Init.IODefaultMode == TSC_IODEF_OUT_PP_LOW)
+ {
+ __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
+ }
+ else
+ {
+ __HAL_TSC_SET_IODEF_INFLOAT(htsc);
+ }
+
+ /* Launch the acquisition */
+ __HAL_TSC_START_ACQ(htsc);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(htsc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Start the acquisition in interrupt mode.
+ * @param htsc pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef* htsc)
+{
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+ assert_param(IS_TSC_MCE_IT(htsc->Init.MaxCountInterrupt));
+
+ /* Process locked */
+ __HAL_LOCK(htsc);
+
+ /* Change TSC state */
+ htsc->State = HAL_TSC_STATE_BUSY;
+
+ /* Enable end of acquisition interrupt */
+ __HAL_TSC_ENABLE_IT(htsc, TSC_IT_EOA);
+
+ /* Enable max count error interrupt (optional) */
+ if (htsc->Init.MaxCountInterrupt == ENABLE)
+ {
+ __HAL_TSC_ENABLE_IT(htsc, TSC_IT_MCE);
+ }
+ else
+ {
+ __HAL_TSC_DISABLE_IT(htsc, TSC_IT_MCE);
+ }
+
+ /* Clear flags */
+ __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
+
+ /* Set touch sensing IOs not acquired to the specified IODefaultMode */
+ if (htsc->Init.IODefaultMode == TSC_IODEF_OUT_PP_LOW)
+ {
+ __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
+ }
+ else
+ {
+ __HAL_TSC_SET_IODEF_INFLOAT(htsc);
+ }
+
+ /* Launch the acquisition */
+ __HAL_TSC_START_ACQ(htsc);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(htsc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the acquisition previously launched in polling mode.
+ * @param htsc pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef* htsc)
+{
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(htsc);
+
+ /* Stop the acquisition */
+ __HAL_TSC_STOP_ACQ(htsc);
+
+ /* Set touch sensing IOs in low power mode (output push-pull) */
+ __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
+
+ /* Clear flags */
+ __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
+
+ /* Change TSC state */
+ htsc->State = HAL_TSC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(htsc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the acquisition previously launched in interrupt mode.
+ * @param htsc pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef* htsc)
+{
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(htsc);
+
+ /* Stop the acquisition */
+ __HAL_TSC_STOP_ACQ(htsc);
+
+ /* Set touch sensing IOs in low power mode (output push-pull) */
+ __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
+
+ /* Disable interrupts */
+ __HAL_TSC_DISABLE_IT(htsc, (TSC_IT_EOA | TSC_IT_MCE));
+
+ /* Clear flags */
+ __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
+
+ /* Change TSC state */
+ htsc->State = HAL_TSC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(htsc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Start acquisition and wait until completion.
+ * @note There is no need of a timeout parameter as the max count error is already
+ * managed by the TSC peripheral.
+ * @param htsc pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @retval HAL state
+ */
+HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef* htsc)
+{
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(htsc);
+
+ /* Check end of acquisition */
+ while (HAL_TSC_GetState(htsc) == HAL_TSC_STATE_BUSY)
+ {
+ /* The timeout (max count error) is managed by the TSC peripheral itself. */
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(htsc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get the acquisition status for a group.
+ * @param htsc pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @param gx_index Index of the group
+ * @retval Group status
+ */
+TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef* htsc, uint32_t gx_index)
+{
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+ assert_param(IS_TSC_GROUP_INDEX(gx_index));
+
+ /* Return the group status */
+ return(__HAL_TSC_GET_GROUP_STATUS(htsc, gx_index));
+}
+
+/**
+ * @brief Get the acquisition measure for a group.
+ * @param htsc pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @param gx_index Index of the group
+ * @retval Acquisition measure
+ */
+uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef* htsc, uint32_t gx_index)
+{
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+ assert_param(IS_TSC_GROUP_INDEX(gx_index));
+
+ /* Return the group acquisition counter */
+ return htsc->Instance->IOGXCR[gx_index];
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TSC_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure TSC IOs
+ (+) Discharge TSC IOs
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure TSC IOs.
+ * @param htsc pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @param config pointer to the configuration structure.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef* htsc, TSC_IOConfigTypeDef* config)
+{
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(htsc);
+
+ /* Stop acquisition */
+ __HAL_TSC_STOP_ACQ(htsc);
+
+ /* Disable Schmitt trigger hysteresis on all used TSC IOs */
+ htsc->Instance->IOHCR = (uint32_t)(~(config->ChannelIOs | config->ShieldIOs | config->SamplingIOs));
+
+ /* Set channel and shield IOs */
+ htsc->Instance->IOCCR = (config->ChannelIOs | config->ShieldIOs);
+
+ /* Set sampling IOs */
+ htsc->Instance->IOSCR = config->SamplingIOs;
+
+ /* Set groups to be acquired */
+ htsc->Instance->IOGCSR = TSC_extract_groups(config->ChannelIOs);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(htsc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Discharge TSC IOs.
+ * @param htsc pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @param choice enable or disable
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef* htsc, uint32_t choice)
+{
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(htsc);
+
+ if (choice == ENABLE)
+ {
+ __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
+ }
+ else
+ {
+ __HAL_TSC_SET_IODEF_INFLOAT(htsc);
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(htsc);
+
+ /* Return the group acquisition counter */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TSC_Exported_Functions_Group4 Peripheral State and Errors functions
+ * @brief Peripheral State and Errors functions
+ *
+@verbatim
+ ===============================================================================
+ ##### State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Get TSC state.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the TSC handle state.
+ * @param htsc pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @retval HAL state
+ */
+HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef* htsc)
+{
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+
+ if (htsc->State == HAL_TSC_STATE_BUSY)
+ {
+ /* Check end of acquisition flag */
+ if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_EOA) != RESET)
+ {
+ /* Check max count error flag */
+ if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_MCE) != RESET)
+ {
+ /* Change TSC state */
+ htsc->State = HAL_TSC_STATE_ERROR;
+ }
+ else
+ {
+ /* Change TSC state */
+ htsc->State = HAL_TSC_STATE_READY;
+ }
+ }
+ }
+
+ /* Return TSC state */
+ return htsc->State;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TSC_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+
+/**
+ * @brief Handle TSC interrupt request.
+ * @param htsc pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @retval None
+ */
+void HAL_TSC_IRQHandler(TSC_HandleTypeDef* htsc)
+{
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+
+ /* Check if the end of acquisition occurred */
+ if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_EOA) != RESET)
+ {
+ /* Clear EOA flag */
+ __HAL_TSC_CLEAR_FLAG(htsc, TSC_FLAG_EOA);
+ }
+
+ /* Check if max count error occurred */
+ if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_MCE) != RESET)
+ {
+ /* Clear MCE flag */
+ __HAL_TSC_CLEAR_FLAG(htsc, TSC_FLAG_MCE);
+ /* Change TSC state */
+ htsc->State = HAL_TSC_STATE_ERROR;
+ /* Conversion completed callback */
+ HAL_TSC_ErrorCallback(htsc);
+ }
+ else
+ {
+ /* Change TSC state */
+ htsc->State = HAL_TSC_STATE_READY;
+ /* Conversion completed callback */
+ HAL_TSC_ConvCpltCallback(htsc);
+ }
+}
+
+/**
+ * @brief Acquisition completed callback in non-blocking mode.
+ * @param htsc pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @retval None
+ */
+__weak void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef* htsc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htsc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TSC_ConvCpltCallback could be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Error callback in non-blocking mode.
+ * @param htsc pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @retval None
+ */
+__weak void HAL_TSC_ErrorCallback(TSC_HandleTypeDef* htsc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htsc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TSC_ErrorCallback could be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup TSC_Private_Functions Private Functions
+ * @{
+ */
+
+/**
+ * @brief Utility function used to set the acquired groups mask.
+ * @param iomask Channels IOs mask
+ * @retval Acquired groups mask
+ */
+static uint32_t TSC_extract_groups(uint32_t iomask)
+{
+ uint32_t groups = 0U;
+ uint32_t idx;
+
+ for (idx = 0U; idx < TSC_NB_OF_GROUPS; idx++)
+ {
+ if ((iomask & (0x0FU << (idx * 4U))) != RESET)
+ {
+ groups |= (1U << idx);
+ }
+ }
+
+ return groups;
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_uart.c b/Src/stm32f3xx_hal_uart.c
new file mode 100644
index 0000000..62f4dd9
--- /dev/null
+++ b/Src/stm32f3xx_hal_uart.c
@@ -0,0 +1,2795 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_uart.c
+ * @author MCD Application Team
+ * @brief UART HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State and Errors functions
+ *
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ The UART HAL driver can be used as follows:
+
+ (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart).
+ (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
+ (++) Enable the USARTx interface clock.
+ (++) UART pins configuration:
+ (+++) Enable the clock for the UART GPIOs.
+ (+++) Configure these UART pins as alternate function pull-up.
+ (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
+ and HAL_UART_Receive_IT() APIs):
+ (+++) Configure the USARTx interrupt priority.
+ (+++) Enable the NVIC USART IRQ handle.
+ (++) UART interrupts handling:
+ -@@- The specific UART interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) are managed using the macros
+ __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit and receive processes.
+ (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
+ and HAL_UART_Receive_DMA() APIs):
+ (+++) Declare a DMA handle structure for the Tx/Rx channel.
+ (+++) Enable the DMAx interface clock.
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+ (+++) Configure the DMA Tx/Rx channel.
+ (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
+
+ (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
+ flow control and Mode (Receiver/Transmitter) in the huart handle Init structure.
+
+ (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...)
+ in the huart handle AdvancedInit structure.
+
+ (#) For the UART asynchronous mode, initialize the UART registers by calling
+ the HAL_UART_Init() API.
+
+ (#) For the UART Half duplex mode, initialize the UART registers by calling
+ the HAL_HalfDuplex_Init() API.
+
+ (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers
+ by calling the HAL_LIN_Init() API.
+
+ (#) For the UART Multiprocessor mode, initialize the UART registers
+ by calling the HAL_MultiProcessor_Init() API.
+
+ (#) For the UART RS485 Driver Enabled mode, initialize the UART registers
+ by calling the HAL_RS485Ex_Init() API.
+
+ [..]
+ (@) These APIs (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_MultiProcessor_Init(),
+ also configure the low level Hardware (GPIO, CLOCK, CORTEX...etc) by
+ calling the customized HAL_UART_MspInit() API.
+
+ [..]
+ [..] Three operation modes are available within this driver :
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Send an amount of data in blocking mode using HAL_UART_Transmit()
+ (+) Receive an amount of data in blocking mode using HAL_UART_Receive()
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT()
+ (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback
+ (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_UART_TxCpltCallback
+ (+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT()
+ (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback
+ (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_UART_RxCpltCallback
+ (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_UART_ErrorCallback
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA()
+ (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback
+ (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_UART_TxCpltCallback
+ (+) Receive an amount of data in non blocking mode (DMA) using HAL_UART_Receive_DMA()
+ (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback
+ (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_UART_RxCpltCallback
+ (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_UART_ErrorCallback
+ (+) Pause the DMA Transfer using HAL_UART_DMAPause()
+ (+) Resume the DMA Transfer using HAL_UART_DMAResume()
+ (+) Stop the DMA Transfer using HAL_UART_DMAStop()
+
+ *** UART HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in UART HAL driver.
+
+ (+) __HAL_UART_ENABLE: Enable the UART peripheral
+ (+) __HAL_UART_DISABLE: Disable the UART peripheral
+ (+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not
+ (+) __HAL_UART_CLEAR_FLAG : Clear the specified UART pending flag
+ (+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt
+ (+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt
+
+ [..]
+ (@) You can refer to the UART HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup UART UART
+ * @brief UART HAL module driver
+ * @{
+ */
+
+#ifdef HAL_UART_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup UART_Private_Constants UART Private Constants
+ * @{
+ */
+#define UART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
+ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup UART_Private_Functions
+ * @{
+ */
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMAError(DMA_HandleTypeDef *hdma);
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup UART_Exported_Functions UART Exported Functions
+ * @{
+ */
+
+/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
+ in asynchronous mode.
+ (+) For the asynchronous mode the parameters below can be configured:
+ (++) Baud Rate
+ (++) Word Length
+ (++) Stop Bit
+ (++) Parity
+ (++) Hardware flow control
+ (++) Receiver/transmitter modes
+ (++) Over Sampling Method
+ (++) One-Bit Sampling Method
+ (+) For the asynchronous mode, the following advanced features can be configured as well:
+ (++) TX and/or RX pin level inversion
+ (++) data logical level inversion
+ (++) RX and TX pins swap
+ (++) RX overrun detection disabling
+ (++) DMA disabling on RX error
+ (++) MSB first on communication line
+ (++) auto Baud rate detection
+ [..]
+ The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init()
+ API follow respectively the UART asynchronous, UART Half duplex, UART LIN mode and
+ multiprocessor configuration procedures (details for the procedures are available in reference manual).
+
+@endverbatim
+ * @{
+ */
+
+/*
+ Additional Table: If the parity is enabled, then the MSB bit of the data written
+ in the data register is transmitted but is changed by the parity bit.
+ According to device capability (support or not of 7-bit word length),
+ frame length is either defined by the M bit (8-bits or 9-bits)
+ or by the M1 and M0 bits (7-bit, 8-bit or 9-bit).
+ Possible UART frame formats are as listed in the following table:
+
+ Table 1. UART frame format.
+ +-----------------------------------------------------------------------+
+ | M bit | PCE bit | UART frame |
+ |-------------------|-----------|---------------------------------------|
+ | 0 | 0 | | SB | 8-bit data | STB | |
+ |-------------------|-----------|---------------------------------------|
+ | 0 | 1 | | SB | 7-bit data | PB | STB | |
+ |-------------------|-----------|---------------------------------------|
+ | 1 | 0 | | SB | 9-bit data | STB | |
+ |-------------------|-----------|---------------------------------------|
+ | 1 | 1 | | SB | 8-bit data | PB | STB | |
+ +-----------------------------------------------------------------------+
+ | M1 bit | M0 bit | PCE bit | UART frame |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 0 | 0 | | SB | 8 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 1 | 0 | | SB | 9 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 1 | 0 | 0 | | SB | 7 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
+ +-----------------------------------------------------------------------+
+
+*/
+
+/**
+ * @brief Initialize the UART mode according to the specified
+ * parameters in the UART_InitTypeDef and initialize the associated handle.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
+{
+ /* Check the UART handle allocation */
+ if(huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
+ {
+ /* Check the parameters */
+ assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
+ }
+ else
+ {
+ /* Check the parameters */
+ assert_param(IS_UART_INSTANCE(huart->Instance));
+ }
+
+ if(huart->gState == HAL_UART_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_UART_MspInit(huart);
+ }
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the UART Communication parameters */
+ if (UART_SetConfig(huart) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ {
+ UART_AdvFeatureConfig(huart);
+ }
+
+ /* In asynchronous mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
+ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+
+ /* Enable the Peripheral */
+ __HAL_UART_ENABLE(huart);
+
+ /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+ return (UART_CheckIdleState(huart));
+}
+
+/**
+ * @brief Initialize the half-duplex mode according to the specified
+ * parameters in the UART_InitTypeDef and creates the associated handle.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
+{
+ /* Check the UART handle allocation */
+ if(huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check UART instance */
+ assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance));
+
+ if(huart->gState == HAL_UART_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_UART_MspInit(huart);
+ }
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the UART Communication parameters */
+ if (UART_SetConfig(huart) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ {
+ UART_AdvFeatureConfig(huart);
+ }
+
+ /* In half-duplex mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - SCEN and IREN bits in the USART_CR3 register.*/
+ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN));
+
+ /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
+ SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
+
+ /* Enable the Peripheral */
+ __HAL_UART_ENABLE(huart);
+
+ /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+ return (UART_CheckIdleState(huart));
+}
+
+
+/**
+ * @brief Initialize the LIN mode according to the specified
+ * parameters in the UART_InitTypeDef and creates the associated handle .
+ * @param huart UART handle.
+ * @param BreakDetectLength specifies the LIN break detection length.
+ * This parameter can be one of the following values:
+ * @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection
+ * @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
+{
+ /* Check the UART handle allocation */
+ if(huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the LIN UART instance */
+ assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
+ /* Check the Break detection length parameter */
+ assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
+
+ /* LIN mode limited to 16-bit oversampling only */
+ if(huart->Init.OverSampling == UART_OVERSAMPLING_8)
+ {
+ return HAL_ERROR;
+ }
+ /* LIN mode limited to 8-bit data length */
+ if(huart->Init.WordLength != UART_WORDLENGTH_8B)
+ {
+ return HAL_ERROR;
+ }
+
+ if(huart->gState == HAL_UART_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_UART_MspInit(huart);
+ }
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the UART Communication parameters */
+ if (UART_SetConfig(huart) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ {
+ UART_AdvFeatureConfig(huart);
+ }
+
+ /* In LIN mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - SCEN and IREN bits in the USART_CR3 register.*/
+ CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN));
+
+ /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
+ SET_BIT(huart->Instance->CR2, USART_CR2_LINEN);
+
+ /* Set the USART LIN Break detection length. */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength);
+
+ /* Enable the Peripheral */
+ __HAL_UART_ENABLE(huart);
+
+ /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+ return (UART_CheckIdleState(huart));
+}
+
+
+/**
+ * @brief Initialize the multiprocessor mode according to the specified
+ * parameters in the UART_InitTypeDef and initialize the associated handle.
+ * @param huart UART handle.
+ * @param Address UART node address (4-, 6-, 7- or 8-bit long).
+ * @param WakeUpMethod specifies the UART wakeup method.
+ * This parameter can be one of the following values:
+ * @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection
+ * @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark
+ * @note If the user resorts to idle line detection wake up, the Address parameter
+ * is useless and ignored by the initialization function.
+ * @note If the user resorts to address mark wake up, the address length detection
+ * is configured by default to 4 bits only. For the UART to be able to
+ * manage 6-, 7- or 8-bit long addresses detection, the API
+ * HAL_MultiProcessorEx_AddressLength_Set() must be called after
+ * HAL_MultiProcessor_Init().
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
+{
+ /* Check the UART handle allocation */
+ if(huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the wake up method parameter */
+ assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
+
+ if(huart->gState == HAL_UART_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_UART_MspInit(huart);
+ }
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the UART Communication parameters */
+ if (UART_SetConfig(huart) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ {
+ UART_AdvFeatureConfig(huart);
+ }
+
+ /* In multiprocessor mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - SCEN, HDSEL and IREN bits in the USART_CR3 register. */
+ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+
+ if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK)
+ {
+ /* If address mark wake up method is chosen, set the USART address node */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS));
+ }
+
+ /* Set the wake up method by setting the WAKE bit in the CR1 register */
+ MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod);
+
+ /* Enable the Peripheral */
+ __HAL_UART_ENABLE(huart);
+
+ /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+ return (UART_CheckIdleState(huart));
+}
+
+
+/**
+ * @brief DeInitialize the UART peripheral.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
+{
+ /* Check the UART handle allocation */
+ if(huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_UART_INSTANCE(huart->Instance));
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ huart->Instance->CR1 = 0x0U;
+ huart->Instance->CR2 = 0x0U;
+ huart->Instance->CR3 = 0x0U;
+
+ /* DeInit the low level hardware */
+ HAL_UART_MspDeInit(huart);
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->gState = HAL_UART_STATE_RESET;
+ huart->RxState = HAL_UART_STATE_RESET;
+
+ /* Process Unlock */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the UART MSP.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the UART MSP.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_MspDeInit can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup UART_Exported_Functions_Group2 IO operation functions
+ * @brief UART Transmit/Receive functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ This subsection provides a set of functions allowing to manage the UART asynchronous
+ and Half duplex data transfers.
+
+ (#) There are two mode of transfer:
+ (++) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) Non-Blocking mode: The communication is performed using Interrupts
+ or DMA, These API's return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
+ will be executed respectively at the end of the transmit or Receive process
+ The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected
+
+ (#) Blocking mode API's are :
+ (++) HAL_UART_Transmit()
+ (++) HAL_UART_Receive()
+
+ (#) Non-Blocking mode API's with Interrupt are :
+ (++) HAL_UART_Transmit_IT()
+ (++) HAL_UART_Receive_IT()
+ (++) HAL_UART_IRQHandler()
+
+ (#) Non-Blocking mode API's with DMA are :
+ (++) HAL_UART_Transmit_DMA()
+ (++) HAL_UART_Receive_DMA()
+ (++) HAL_UART_DMAPause()
+ (++) HAL_UART_DMAResume()
+ (++) HAL_UART_DMAStop()
+
+ (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
+ (++) HAL_UART_TxHalfCpltCallback()
+ (++) HAL_UART_TxCpltCallback()
+ (++) HAL_UART_RxHalfCpltCallback()
+ (++) HAL_UART_RxCpltCallback()
+ (++) HAL_UART_ErrorCallback()
+
+ (#) Non-Blocking mode transfers could be aborted using Abort API's :
+ (++) HAL_UART_Abort()
+ (++) HAL_UART_AbortTransmit()
+ (++) HAL_UART_AbortReceive()
+ (++) HAL_UART_Abort_IT()
+ (++) HAL_UART_AbortTransmit_IT()
+ (++) HAL_UART_AbortReceive_IT()
+
+ (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
+ (++) HAL_UART_AbortCpltCallback()
+ (++) HAL_UART_AbortTransmitCpltCallback()
+ (++) HAL_UART_AbortReceiveCpltCallback()
+
+ (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
+ Errors are handled as follows :
+ (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+ to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
+ Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
+ and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side.
+ If user wants to abort it, Abort services should be called by user.
+ (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+ This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
+ Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed.
+
+ -@- In the Half duplex communication, it is forbidden to run the transmit
+ and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Send an amount of data in blocking mode.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer.
+ * @param Size Amount of data to be sent.
+ * @param Timeout Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint16_t* tmp;
+ uint32_t tickstart = 0U;
+
+ /* Check that a Tx process is not already ongoing */
+ if(huart->gState == HAL_UART_STATE_READY)
+ {
+ if((pData == NULL ) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->gState = HAL_UART_STATE_BUSY_TX;
+
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
+
+ huart->TxXferSize = Size;
+ huart->TxXferCount = Size;
+ while(huart->TxXferCount > 0U)
+ {
+ huart->TxXferCount--;
+ if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ tmp = (uint16_t*) pData;
+ huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
+ pData += 2U;
+ }
+ else
+ {
+ huart->Instance->TDR = (*pData++ & (uint8_t)0xFFU);
+ }
+ }
+ if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* At end of Tx process, restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode.
+ * @param huart UART handle.
+ * @param pData pointer to data buffer.
+ * @param Size amount of data to be received.
+ * @param Timeout Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint16_t* tmp;
+ uint16_t uhMask;
+ uint32_t tickstart = 0U;
+
+ /* Check that a Rx process is not already ongoing */
+ if(huart->RxState == HAL_UART_STATE_READY)
+ {
+ if((pData == NULL ) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->RxState = HAL_UART_STATE_BUSY_RX;
+
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
+
+ huart->RxXferSize = Size;
+ huart->RxXferCount = Size;
+
+ /* Computation of UART mask to apply to RDR register */
+ UART_MASK_COMPUTATION(huart);
+ uhMask = huart->Mask;
+
+ /* as long as data have to be received */
+ while(huart->RxXferCount > 0U)
+ {
+ huart->RxXferCount--;
+ if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ tmp = (uint16_t*) pData ;
+ *tmp = (uint16_t)(huart->Instance->RDR & uhMask);
+ pData +=2U;
+ }
+ else
+ {
+ *pData++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
+ }
+ }
+
+ /* At end of Rx process, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in interrupt mode.
+ * @param huart UART handle.
+ * @param pData pointer to data buffer.
+ * @param Size amount of data to be sent.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ /* Check that a Tx process is not already ongoing */
+ if(huart->gState == HAL_UART_STATE_READY)
+ {
+ if((pData == NULL ) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->pTxBuffPtr = pData;
+ huart->TxXferSize = Size;
+ huart->TxXferCount = Size;
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->gState = HAL_UART_STATE_BUSY_TX;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ /* Enable the UART Transmit Data Register Empty Interrupt */
+ SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in interrupt mode.
+ * @param huart UART handle.
+ * @param pData pointer to data buffer.
+ * @param Size amount of data to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ /* Check that a Rx process is not already ongoing */
+ if(huart->RxState == HAL_UART_STATE_READY)
+ {
+ if((pData == NULL ) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->pRxBuffPtr = pData;
+ huart->RxXferSize = Size;
+ huart->RxXferCount = Size;
+
+ /* Computation of UART mask to apply to RDR register */
+ UART_MASK_COMPUTATION(huart);
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->RxState = HAL_UART_STATE_BUSY_RX;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the UART Parity Error and Data Register not empty Interrupts */
+ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in DMA mode.
+ * @param huart UART handle.
+ * @param pData pointer to data buffer.
+ * @param Size amount of data to be sent.
+ * @note This function starts a DMA transfer in interrupt mode meaning that
+ * DMA half transfer complete, DMA transfer complete and DMA transfer
+ * error interrupts are enabled
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ /* Check if UART instance supports continuous communication using DMA */
+ assert_param(IS_UART_DMA_INSTANCE(huart->Instance));
+
+ /* Check that a Tx process is not already ongoing */
+ if(huart->gState == HAL_UART_STATE_READY)
+ {
+ if((pData == NULL ) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->pTxBuffPtr = pData;
+ huart->TxXferSize = Size;
+ huart->TxXferCount = Size;
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->gState = HAL_UART_STATE_BUSY_TX;
+
+ /* Set the UART DMA transfer complete callback */
+ huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
+
+ /* Set the UART DMA Half transfer complete callback */
+ huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
+
+ /* Set the DMA error callback */
+ huart->hdmatx->XferErrorCallback = UART_DMAError;
+
+ /* Set the DMA abort callback */
+ huart->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the UART transmit DMA channel */
+ HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size);
+
+ /* Clear the TC flag in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the UART CR3 register */
+ SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in DMA mode.
+ * @param huart UART handle.
+ * @param pData pointer to data buffer.
+ * @param Size amount of data to be received.
+ * @note When the UART parity is enabled (PCE = 1), the received data contain
+ * the parity bit (MSB position).
+ * @note This function starts a DMA transfer in interrupt mode meaning that
+ * DMA half transfer complete, DMA transfer complete and DMA transfer
+ * error interrupts are enabled
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ /* Check if UART instance supports continuous communication using DMA */
+ assert_param(IS_UART_DMA_INSTANCE(huart->Instance));
+
+ /* Check that a Rx process is not already ongoing */
+ if(huart->RxState == HAL_UART_STATE_READY)
+ {
+ if((pData == NULL ) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->pRxBuffPtr = pData;
+ huart->RxXferSize = Size;
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->RxState = HAL_UART_STATE_BUSY_RX;
+
+ /* Set the UART DMA transfer complete callback */
+ huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
+
+ /* Set the UART DMA Half transfer complete callback */
+ huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
+
+ /* Set the DMA error callback */
+ huart->hdmarx->XferErrorCallback = UART_DMAError;
+
+ /* Set the DMA abort callback */
+ huart->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ /* Enable the UART Parity Error Interrupt */
+ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+
+ /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the UART CR3 register */
+ SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Pause the DMA Transfer.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
+{
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ if ((huart->gState == HAL_UART_STATE_BUSY_TX) &&
+ (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)))
+ {
+ /* Disable the UART DMA Tx request */
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+ }
+ if ((huart->RxState == HAL_UART_STATE_BUSY_RX) &&
+ (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))
+ {
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the UART DMA Rx request */
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resume the DMA Transfer.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
+{
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ if(huart->gState == HAL_UART_STATE_BUSY_TX)
+ {
+ /* Enable the UART DMA Tx request */
+ SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+ }
+ if(huart->RxState == HAL_UART_STATE_BUSY_RX)
+ {
+ /* Clear the Overrun flag before resuming the Rx transfer */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
+
+ /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the UART DMA Rx request */
+ SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the DMA Transfer.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
+{
+ /* The Lock is not implemented on this API to allow the user application
+ to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() /
+ HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback:
+ indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
+ interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
+ the stream and the corresponding call back is executed. */
+
+ /* Stop UART DMA Tx request if ongoing */
+ if ((huart->gState == HAL_UART_STATE_BUSY_TX) &&
+ (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the UART DMA Tx channel */
+ if(huart->hdmatx != NULL)
+ {
+ HAL_DMA_Abort(huart->hdmatx);
+ }
+
+ UART_EndTxTransfer(huart);
+ }
+
+ /* Stop UART DMA Rx request if ongoing */
+ if ((huart->RxState == HAL_UART_STATE_BUSY_RX) &&
+ (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the UART DMA Rx channel */
+ if(huart->hdmarx != NULL)
+ {
+ HAL_DMA_Abort(huart->hdmarx);
+ }
+
+ UART_EndRxTransfer(huart);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing transfers (blocking mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable UART Interrupts (Tx and Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
+{
+ /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the UART DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if(huart->hdmatx != NULL)
+ {
+ /* Set the UART DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ huart->hdmatx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(huart->hdmatx);
+ }
+ }
+
+ /* Disable the UART DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if(huart->hdmarx != NULL)
+ {
+ /* Set the UART DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ huart->hdmarx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(huart->hdmarx);
+ }
+ }
+
+ /* Reset Tx and Rx transfer counters */
+ huart->TxXferCount = 0U;
+ huart->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Restore huart->gState and huart->RxState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* Reset Handle ErrorCode to No Error */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Transmit transfer (blocking mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable UART Interrupts (Tx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
+{
+ /* Disable TXEIE and TCIE interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+ /* Disable the UART DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if(huart->hdmatx != NULL)
+ {
+ /* Set the UART DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ huart->hdmatx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(huart->hdmatx);
+ }
+ }
+
+ /* Reset Tx transfer counter */
+ huart->TxXferCount = 0U;
+
+ /* Restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Receive transfer (blocking mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable UART Interrupts (Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the UART DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if(huart->hdmarx != NULL)
+ {
+ /* Set the UART DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ huart->hdmarx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(huart->hdmarx);
+ }
+ }
+
+ /* Reset Rx transfer counter */
+ huart->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing transfers (Interrupt mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable UART Interrupts (Tx and Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
+{
+ uint32_t abortcplt = 1U;
+
+ /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised
+ before any call to DMA Abort functions */
+ /* DMA Tx Handle is valid */
+ if(huart->hdmatx != NULL)
+ {
+ /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
+ Otherwise, set it to NULL */
+ if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+ {
+ huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback;
+ }
+ else
+ {
+ huart->hdmatx->XferAbortCallback = NULL;
+ }
+ }
+ /* DMA Rx Handle is valid */
+ if(huart->hdmarx != NULL)
+ {
+ /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
+ Otherwise, set it to NULL */
+ if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback;
+ }
+ else
+ {
+ huart->hdmarx->XferAbortCallback = NULL;
+ }
+ }
+
+ /* Disable the UART DMA Tx request if enabled */
+ if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+ {
+ /* Disable DMA Tx at UART level */
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
+ if(huart->hdmatx != NULL)
+ {
+ /* UART Tx DMA Abort callback has already been initialised :
+ will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA TX */
+ if(HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
+ {
+ huart->hdmatx->XferAbortCallback = NULL;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+
+ /* Disable the UART DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
+ if(huart->hdmarx != NULL)
+ {
+ /* UART Rx DMA Abort callback has already been initialised :
+ will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA RX */
+ if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+ {
+ huart->hdmarx->XferAbortCallback = NULL;
+ abortcplt = 1U;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+
+ /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+ if (abortcplt == 1U)
+ {
+ /* Reset Tx and Rx transfer counters */
+ huart->TxXferCount = 0U;
+ huart->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Restore huart->gState and huart->RxState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_UART_AbortCpltCallback(huart);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Transmit transfer (Interrupt mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable UART Interrupts (Tx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
+{
+ /* Disable TXEIE and TCIE interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+ /* Disable the UART DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
+ if(huart->hdmatx != NULL)
+ {
+ /* Set the UART DMA Abort callback :
+ will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+ huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback;
+
+ /* Abort DMA TX */
+ if(HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
+ {
+ /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */
+ huart->hdmatx->XferAbortCallback(huart->hdmatx);
+ }
+ }
+ else
+ {
+ /* Reset Tx transfer counter */
+ huart->TxXferCount = 0U;
+
+ /* Restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_UART_AbortTransmitCpltCallback(huart);
+ }
+ }
+ else
+ {
+ /* Reset Tx transfer counter */
+ huart->TxXferCount = 0U;
+
+ /* Restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_UART_AbortTransmitCpltCallback(huart);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Receive transfer (Interrupt mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable UART Interrupts (Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the UART DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
+ if(huart->hdmarx != NULL)
+ {
+ /* Set the UART DMA Abort callback :
+ will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+ huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback;
+
+ /* Abort DMA RX */
+ if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+ {
+ /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
+ huart->hdmarx->XferAbortCallback(huart->hdmarx);
+ }
+ }
+ else
+ {
+ /* Reset Rx transfer counter */
+ huart->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_UART_AbortReceiveCpltCallback(huart);
+ }
+ }
+ else
+ {
+ /* Reset Rx transfer counter */
+ huart->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_UART_AbortReceiveCpltCallback(huart);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle UART interrupt request.
+ * @param huart UART handle.
+ * @retval None
+ */
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
+{
+ uint32_t isrflags = READ_REG(huart->Instance->ISR);
+ uint32_t cr1its = READ_REG(huart->Instance->CR1);
+ uint32_t cr3its;
+ uint32_t errorflags;
+
+ /* If no error occurs */
+ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
+ if (errorflags == RESET)
+ {
+ /* UART in mode Receiver ---------------------------------------------------*/
+ if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ {
+ UART_Receive_IT(huart);
+ return;
+ }
+ }
+
+ /* If some errors occur */
+ cr3its = READ_REG(huart->Instance->CR3);
+ if( (errorflags != RESET)
+ && ( ((cr3its & USART_CR3_EIE) != RESET)
+ || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) )
+ {
+ /* UART parity error interrupt occurred -------------------------------------*/
+ if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
+ {
+ __HAL_UART_CLEAR_IT(huart, UART_CLEAR_PEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_PE;
+ }
+
+ /* UART frame error interrupt occurred --------------------------------------*/
+ if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ {
+ __HAL_UART_CLEAR_IT(huart, UART_CLEAR_FEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_FE;
+ }
+
+ /* UART noise error interrupt occurred --------------------------------------*/
+ if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ {
+ __HAL_UART_CLEAR_IT(huart, UART_CLEAR_NEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_NE;
+ }
+
+ /* UART Over-Run interrupt occurred -----------------------------------------*/
+ if(((isrflags & USART_ISR_ORE) != RESET) &&
+ (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
+ {
+ __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_ORE;
+ }
+
+ /* Call UART Error Call back function if need be --------------------------*/
+ if(huart->ErrorCode != HAL_UART_ERROR_NONE)
+ {
+ /* UART in mode Receiver ---------------------------------------------------*/
+ if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ {
+ UART_Receive_IT(huart);
+ }
+
+ /* If Overrun error occurs, or if any error occurs in DMA mode reception,
+ consider error as blocking */
+ if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) ||
+ (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))
+ {
+ /* Blocking error : transfer is aborted
+ Set the UART state ready to be able to start again the process,
+ Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+ UART_EndRxTransfer(huart);
+
+ /* Disable the UART DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the UART DMA Rx channel */
+ if(huart->hdmarx != NULL)
+ {
+ /* Set the UART DMA Abort callback :
+ will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
+ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
+
+ /* Abort DMA RX */
+ if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+ {
+ /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
+ huart->hdmarx->XferAbortCallback(huart->hdmarx);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+ HAL_UART_ErrorCallback(huart);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+ HAL_UART_ErrorCallback(huart);
+ }
+ }
+ else
+ {
+ /* Non Blocking error : transfer could go on.
+ Error is notified to user through user error callback */
+ HAL_UART_ErrorCallback(huart);
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ }
+ }
+ return;
+
+ } /* End if some error occurs */
+
+ /* UART wakeup from Stop mode interrupt occurred ---------------------------*/
+ if(((isrflags & USART_ISR_WUF) != RESET) && ((cr3its & USART_CR3_WUFIE) != RESET))
+ {
+ __HAL_UART_CLEAR_IT(huart, UART_CLEAR_WUF);
+ /* Set the UART state ready to be able to start again the process */
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+ HAL_UARTEx_WakeupCallback(huart);
+ return;
+ }
+
+ /* UART in mode Transmitter ------------------------------------------------*/
+ if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
+ {
+ UART_Transmit_IT(huart);
+ return;
+ }
+
+ /* UART in mode Transmitter (transmission end) -----------------------------*/
+ if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
+ {
+ UART_EndTransmit_IT(huart);
+ return;
+ }
+
+}
+
+/**
+ * @brief Tx Transfer completed callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_TxCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Tx Half Transfer completed callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_UART_TxHalfCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_RxCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Rx Half Transfer completed callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_UART_RxHalfCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief UART error callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_ErrorCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief UART Abort Complete callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_AbortCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief UART Abort Complete callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief UART Abort Receive Complete callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions
+ * @brief UART control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the UART.
+ (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
+ (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode
+ (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode
+ (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter
+ (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver
+ (+) HAL_LIN_SendBreak() API transmits the break characters
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enable UART in mute mode (does not mean UART enters mute mode;
+ * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)
+{
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Enable USART mute mode by setting the MME bit in the CR1 register */
+ SET_BIT(huart->Instance->CR1, USART_CR1_MME);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ return (UART_CheckIdleState(huart));
+}
+
+/**
+ * @brief Disable UART mute mode (does not mean the UART actually exits mute mode
+ * as it may not have been in mute mode at this very moment).
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart)
+{
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Disable USART mute mode by clearing the MME bit in the CR1 register */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ return (UART_CheckIdleState(huart));
+}
+
+/**
+ * @brief Enter UART mute mode (means UART actually enters mute mode).
+ * @note To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called.
+ * @param huart UART handle.
+ * @retval None
+ */
+void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
+{
+ __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST);
+}
+
+/**
+ * @brief Enable the UART transmitter and disable the UART receiver.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
+{
+ /* Process Locked */
+ __HAL_LOCK(huart);
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Clear TE and RE bits */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
+ /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
+ SET_BIT(huart->Instance->CR1, USART_CR1_TE);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable the UART receiver and disable the UART transmitter.
+ * @param huart UART handle.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
+{
+ /* Process Locked */
+ __HAL_LOCK(huart);
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Clear TE and RE bits */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
+ /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
+ SET_BIT(huart->Instance->CR1, USART_CR1_RE);
+
+ huart->gState = HAL_UART_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Transmit break characters.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
+{
+ /* Check the parameters */
+ assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Send break characters */
+ huart->Instance->RQR |= UART_SENDBREAK_REQUEST;
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions
+ * @brief UART Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State and Error functions #####
+ ==============================================================================
+ [..]
+ This subsection provides functions allowing to :
+ (+) Return the UART handle state.
+ (+) Return the UART handle error code
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the UART handle state.
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART.
+ * @retval HAL state
+ */
+HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
+{
+ uint32_t temp1= 0x00U, temp2 = 0x00U;
+ temp1 = huart->gState;
+ temp2 = huart->RxState;
+
+ return (HAL_UART_StateTypeDef)(temp1 | temp2);
+}
+
+/**
+ * @brief Return the UART handle error code.
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART.
+ * @retval UART Error Code
+ */
+uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
+{
+ return huart->ErrorCode;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup UART_Private_Functions UART Private Functions
+ * @{
+ */
+
+/**
+ * @brief Configure the UART peripheral.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
+{
+ uint32_t tmpreg = 0x00000000U;
+ UART_ClockSourceTypeDef clocksource = UART_CLOCKSOURCE_UNDEFINED;
+ uint16_t brrtemp = 0x0000U;
+ uint16_t usartdiv = 0x0000U;
+ HAL_StatusTypeDef ret = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
+ assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
+ assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
+ assert_param(IS_UART_PARITY(huart->Init.Parity));
+ assert_param(IS_UART_MODE(huart->Init.Mode));
+ assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
+ assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling));
+ assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
+
+
+ /*-------------------------- USART CR1 Configuration -----------------------*/
+ /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure
+ * the UART Word Length, Parity, Mode and oversampling:
+ * set the M bits according to huart->Init.WordLength value
+ * set PCE and PS bits according to huart->Init.Parity value
+ * set TE and RE bits according to huart->Init.Mode value
+ * set OVER8 bit according to huart->Init.OverSampling value */
+ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
+ MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg);
+
+ /*-------------------------- USART CR2 Configuration -----------------------*/
+ /* Configure the UART Stop Bits: Set STOP[13:12] bits according
+ * to huart->Init.StopBits value */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
+
+ /*-------------------------- USART CR3 Configuration -----------------------*/
+ /* Configure
+ * - UART HardWare Flow Control: set CTSE and RTSE bits according
+ * to huart->Init.HwFlowCtl value
+ * - one-bit sampling method versus three samples' majority rule according
+ * to huart->Init.OneBitSampling */
+ tmpreg = (uint32_t)huart->Init.HwFlowCtl | huart->Init.OneBitSampling ;
+ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT), tmpreg);
+
+ /*-------------------------- USART BRR Configuration -----------------------*/
+ UART_GETCLOCKSOURCE(huart, clocksource);
+
+ /* Check UART Over Sampling to set Baud Rate Register */
+ if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
+ {
+ switch (clocksource)
+ {
+ case UART_CLOCKSOURCE_PCLK1:
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
+ break;
+ case UART_CLOCKSOURCE_PCLK2:
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
+ break;
+ case UART_CLOCKSOURCE_HSI:
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate));
+ break;
+ case UART_CLOCKSOURCE_SYSCLK:
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
+ break;
+ case UART_CLOCKSOURCE_LSE:
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate));
+ break;
+ case UART_CLOCKSOURCE_UNDEFINED:
+ default:
+ ret = HAL_ERROR;
+ break;
+ }
+
+ brrtemp = usartdiv & 0xFFF0U;
+ brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+ huart->Instance->BRR = brrtemp;
+ }
+ else
+ {
+ switch (clocksource)
+ {
+ case UART_CLOCKSOURCE_PCLK1:
+ huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
+ break;
+ case UART_CLOCKSOURCE_PCLK2:
+ huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
+ break;
+ case UART_CLOCKSOURCE_HSI:
+ huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate));
+ break;
+ case UART_CLOCKSOURCE_SYSCLK:
+ huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
+ break;
+ case UART_CLOCKSOURCE_LSE:
+ huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate));
+ break;
+ case UART_CLOCKSOURCE_UNDEFINED:
+ default:
+ ret = HAL_ERROR;
+ break;
+ }
+ }
+
+ return ret;
+
+}
+
+/**
+ * @brief Configure the UART peripheral advanced features.
+ * @param huart UART handle.
+ * @retval None
+ */
+void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
+{
+ /* Check whether the set of advanced features to configure is properly set */
+ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
+
+ /* if required, configure TX pin active level inversion */
+ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
+ {
+ assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
+ }
+
+ /* if required, configure RX pin active level inversion */
+ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
+ {
+ assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
+ }
+
+ /* if required, configure data inversion */
+ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
+ {
+ assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
+ }
+
+ /* if required, configure RX/TX pins swap */
+ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
+ {
+ assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
+ }
+
+ /* if required, configure RX overrun detection disabling */
+ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
+ {
+ assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
+ }
+
+ /* if required, configure DMA disabling on reception error */
+ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
+ {
+ assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
+ }
+
+ /* if required, configure auto Baud rate detection scheme */
+ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
+ {
+ assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
+ assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
+ /* set auto Baudrate detection parameters if detection is enabled */
+ if(huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
+ {
+ assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
+ }
+ }
+
+ /* if required, configure MSB first on communication line */
+ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
+ {
+ assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
+ }
+}
+
+/**
+ * @brief Check the UART Idle State.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
+{
+ uint32_t tickstart = 0U;
+
+ /* Initialize the UART ErrorCode */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
+
+ /* Check if the Transmitter is enabled */
+ if((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+ {
+ /* Wait until TEACK flag is set */
+ if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+ {
+ /* Timeout Occured */
+ return HAL_TIMEOUT;
+ }
+ }
+ /* Check if the Receiver is enabled */
+ if((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+ {
+ /* Wait until REACK flag is set */
+ if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+ {
+ /* Timeout Occured */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Initialize the UART State */
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle UART Communication Timeout.
+ * @param huart UART handle.
+ * @param Flag Specifies the UART flag to check
+ * @param Status Flag status (SET or RESET)
+ * @param Tickstart Tick start value
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
+{
+ /* Wait until flag is set */
+ while((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+
+/**
+ * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
+{
+ /* Disable TXEIE and TCIE interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+ /* At end of Tx process, restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+}
+
+
+/**
+ * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* At end of Rx process, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+}
+
+
+/**
+ * @brief DMA UART transmit process complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
+
+ /* DMA Normal mode */
+ if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
+ {
+ huart->TxXferCount = 0U;
+
+ /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+ in the UART CR3 register */
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Enable the UART Transmit Complete Interrupt */
+ SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+ }
+ /* DMA Circular mode */
+ else
+ {
+ HAL_UART_TxCpltCallback(huart);
+ }
+
+}
+
+/**
+ * @brief DMA UART transmit process half complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
+
+ HAL_UART_TxHalfCpltCallback(huart);
+}
+
+/**
+ * @brief DMA UART receive process complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
+
+ /* DMA Normal mode */
+ if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
+ {
+ huart->RxXferCount = 0U;
+
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+ in the UART CR3 register */
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* At end of Rx process, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+ }
+
+ HAL_UART_RxCpltCallback(huart);
+}
+
+/**
+ * @brief DMA UART receive process half complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
+
+ HAL_UART_RxHalfCpltCallback(huart);
+}
+
+/**
+ * @brief DMA UART communication error callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMAError(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
+
+ /* Stop UART DMA Tx request if ongoing */
+ if ( (huart->gState == HAL_UART_STATE_BUSY_TX)
+ &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) )
+ {
+ huart->TxXferCount = 0U;
+ UART_EndTxTransfer(huart);
+ }
+
+ /* Stop UART DMA Rx request if ongoing */
+ if ( (huart->RxState == HAL_UART_STATE_BUSY_RX)
+ &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) )
+ {
+ huart->RxXferCount = 0U;
+ UART_EndRxTransfer(huart);
+ }
+
+ huart->ErrorCode |= HAL_UART_ERROR_DMA;
+ HAL_UART_ErrorCallback(huart);
+}
+
+/**
+ * @brief DMA UART communication abort callback, when initiated by HAL services on Error
+ * (To be called at end of DMA Abort procedure following error occurrence).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
+ huart->RxXferCount = 0U;
+ huart->TxXferCount = 0U;
+
+ HAL_UART_ErrorCallback(huart);
+}
+
+/**
+ * @brief DMA UART Tx communication abort callback, when initiated by user
+ * (To be called at end of DMA Tx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Rx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef* huart = (UART_HandleTypeDef* )(hdma->Parent);
+
+ huart->hdmatx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if(huart->hdmarx != NULL)
+ {
+ if(huart->hdmarx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ huart->TxXferCount = 0U;
+ huart->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Restore huart->gState and huart->RxState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_UART_AbortCpltCallback(huart);
+}
+
+
+/**
+ * @brief DMA UART Rx communication abort callback, when initiated by user
+ * (To be called at end of DMA Rx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Tx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef* huart = (UART_HandleTypeDef* )(hdma->Parent);
+
+ huart->hdmarx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if(huart->hdmatx != NULL)
+ {
+ if(huart->hdmatx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ huart->TxXferCount = 0U;
+ huart->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Restore huart->gState and huart->RxState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_UART_AbortCpltCallback(huart);
+}
+
+
+/**
+ * @brief DMA UART Tx communication abort callback, when initiated by user by a call to
+ * HAL_UART_AbortTransmit_IT API (Abort only Tx transfer)
+ * (This callback is executed at end of DMA Tx Abort procedure following user abort request,
+ * and leads to user Tx Abort Complete callback execution).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
+
+ huart->TxXferCount = 0U;
+
+ /* Restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_UART_AbortTransmitCpltCallback(huart);
+}
+
+/**
+ * @brief DMA UART Rx communication abort callback, when initiated by user by a call to
+ * HAL_UART_AbortReceive_IT API (Abort only Rx transfer)
+ * (This callback is executed at end of DMA Rx Abort procedure following user abort request,
+ * and leads to user Rx Abort Complete callback execution).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ huart->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_UART_AbortReceiveCpltCallback(huart);
+}
+
+/**
+ * @brief Send an amount of data in interrupt mode.
+ * @note Function is called under interruption only, once
+ * interruptions have been enabled by HAL_UART_Transmit_IT().
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
+{
+ uint16_t* tmp;
+
+ /* Check that a Tx process is ongoing */
+ if (huart->gState == HAL_UART_STATE_BUSY_TX)
+ {
+ if(huart->TxXferCount == 0U)
+ {
+ /* Disable the UART Transmit Data Register Empty Interrupt */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
+
+ /* Enable the UART Transmit Complete Interrupt */
+ SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ tmp = (uint16_t*) huart->pTxBuffPtr;
+ huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
+ huart->pTxBuffPtr += 2U;
+ }
+ else
+ {
+ huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFFU);
+ }
+ huart->TxXferCount--;
+
+ return HAL_OK;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Wrap up transmission in non-blocking mode.
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
+{
+ /* Disable the UART Transmit Complete Interrupt */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+
+ /* Tx process is ended, restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ HAL_UART_TxCpltCallback(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Receive an amount of data in interrupt mode.
+ * @note Function is called under interruption only, once
+ * interruptions have been enabled by HAL_UART_Receive_IT()
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
+{
+ uint16_t* tmp;
+ uint16_t uhMask = huart->Mask;
+ uint16_t uhdata;
+
+ /* Check that a Rx process is ongoing */
+ if(huart->RxState == HAL_UART_STATE_BUSY_RX)
+ {
+ uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ tmp = (uint16_t*) huart->pRxBuffPtr ;
+ *tmp = (uint16_t)(uhdata & uhMask);
+ huart->pRxBuffPtr +=2U;
+ }
+ else
+ {
+ *huart->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask);
+ }
+
+ if(--huart->RxXferCount == 0U)
+ {
+ /* Disable the UART Parity Error Interrupt and RXNE interrupt*/
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+
+ /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Rx process is completed, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ HAL_UART_RxCpltCallback(huart);
+
+ return HAL_OK;
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Clear RXNE interrupt flag */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection.
+ * @param huart UART handle.
+ * @param WakeUpSelection UART wake up from stop mode parameters.
+ * @retval None
+ */
+void UART_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
+{
+ assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength));
+
+ /* Set the USART address length */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength);
+
+ /* Set the USART address node */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS));
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_UART_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_uart_ex.c b/Src/stm32f3xx_hal_uart_ex.c
new file mode 100644
index 0000000..b94c738
--- /dev/null
+++ b/Src/stm32f3xx_hal_uart_ex.c
@@ -0,0 +1,469 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_uart_ex.c
+ * @author MCD Application Team
+ * @brief Extended UART HAL module driver.
+ * This file provides firmware functions to manage the following extended
+ * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
+ * + Initialization and de-initialization functions
+ * + Peripheral Control functions
+ *
+ *
+ @verbatim
+ ==============================================================================
+ ##### UART peripheral extended features #####
+ ==============================================================================
+
+ (#) Declare a UART_HandleTypeDef handle structure.
+
+ (#) For the UART RS485 Driver Enable mode, initialize the UART registers
+ by calling the HAL_RS485Ex_Init() API.
+
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup UARTEx UARTEx
+ * @brief UART Extension HAL module driver
+ * @{
+ */
+
+#ifdef HAL_UART_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup UARTEx_Exported_Functions UARTEx Exported Functions
+ * @{
+ */
+
+/** @defgroup UARTEx_Exported_Functions_Group1 Extended Initialization and de-initialization functions
+ * @brief Extended Initialization and Configuration Functions
+ *
+@verbatim
+===============================================================================
+ ##### Initialization and Configuration functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
+ in asynchronous mode.
+ (+) For the asynchronous mode the parameters below can be configured:
+ (++) Baud Rate
+ (++) Word Length (Fixed to 8-bits only for LIN mode)
+ (++) Stop Bit
+ (++) Parity
+ (++) Hardware flow control
+ (++) Receiver/transmitter modes
+ (++) Over Sampling Method
+ (++) One-Bit Sampling Method
+ (+) For the asynchronous mode, the following advanced features can be configured as well:
+ (++) TX and/or RX pin level inversion
+ (++) data logical level inversion
+ (++) RX and TX pins swap
+ (++) RX overrun detection disabling
+ (++) DMA disabling on RX error
+ (++) MSB first on communication line
+ (++) auto Baud rate detection
+ [..]
+ The HAL_RS485Ex_Init() API follows respectively the UART RS485 mode
+ configuration procedures (details for the procedures are available in reference manual).
+
+@endverbatim
+ * @{
+ */
+
+/*
+ Additional Table: If the parity is enabled, then the MSB bit of the data written
+ in the data register is transmitted but is changed by the parity bit.
+ According to device capability (support or not of 7-bit word length),
+ frame length is either defined by the M bit (8-bits or 9-bits)
+ or by the M1 and M0 bits (7-bit, 8-bit or 9-bit).
+ Possible UART frame formats are as listed in the following table:
+
+ Table 1. UART frame format.
+ +-----------------------------------------------------------------------+
+ | M bit | PCE bit | UART frame |
+ |-------------------|-----------|---------------------------------------|
+ | 0 | 0 | | SB | 8-bit data | STB | |
+ |-------------------|-----------|---------------------------------------|
+ | 0 | 1 | | SB | 7-bit data | PB | STB | |
+ |-------------------|-----------|---------------------------------------|
+ | 1 | 0 | | SB | 9-bit data | STB | |
+ |-------------------|-----------|---------------------------------------|
+ | 1 | 1 | | SB | 8-bit data | PB | STB | |
+ +-----------------------------------------------------------------------+
+ | M1 bit | M0 bit | PCE bit | UART frame |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 0 | 0 | | SB | 8 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 1 | 0 | | SB | 9 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 1 | 0 | 0 | | SB | 7 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
+ +-----------------------------------------------------------------------+
+
+*/
+
+/**
+ * @brief Initialize the RS485 Driver enable feature according to the specified
+ * parameters in the UART_InitTypeDef and creates the associated handle.
+ * @param huart UART handle.
+ * @param Polarity select the driver enable polarity.
+ * This parameter can be one of the following values:
+ * @arg @ref UART_DE_POLARITY_HIGH DE signal is active high
+ * @arg @ref UART_DE_POLARITY_LOW DE signal is active low
+ * @param AssertionTime Driver Enable assertion time:
+ * 5-bit value defining the time between the activation of the DE (Driver Enable)
+ * signal and the beginning of the start bit. It is expressed in sample time
+ * units (1/8 or 1/16 bit time, depending on the oversampling rate)
+ * @param DeassertionTime Driver Enable deassertion time:
+ * 5-bit value defining the time between the end of the last stop bit, in a
+ * transmitted message, and the de-activation of the DE (Driver Enable) signal.
+ * It is expressed in sample time units (1/8 or 1/16 bit time, depending on the
+ * oversampling rate).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime)
+{
+ uint32_t temp = 0x0U;
+
+ /* Check the UART handle allocation */
+ if(huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+ /* Check the Driver Enable UART instance */
+ assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance));
+
+ /* Check the Driver Enable polarity */
+ assert_param(IS_UART_DE_POLARITY(Polarity));
+
+ /* Check the Driver Enable assertion time */
+ assert_param(IS_UART_ASSERTIONTIME(AssertionTime));
+
+ /* Check the Driver Enable deassertion time */
+ assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime));
+
+ if(huart->gState == HAL_UART_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX */
+ HAL_UART_MspInit(huart);
+ }
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the UART Communication parameters */
+ if (UART_SetConfig(huart) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ if(huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ {
+ UART_AdvFeatureConfig(huart);
+ }
+
+ /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
+ SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
+
+ /* Set the Driver Enable polarity */
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);
+
+ /* Set the Driver Enable assertion and deassertion times */
+ temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);
+ temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
+ MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT|USART_CR1_DEAT), temp);
+
+ /* Enable the Peripheral */
+ __HAL_UART_ENABLE(huart);
+
+ /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+ return (UART_CheckIdleState(huart));
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup UARTEx_Exported_Functions_Group2 Extended IO operation function
+ * @brief Extended UART Interrupt handling function
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation function #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to manage the UART interrupts
+ and to handle Wake up interrupt call-back.
+
+ (#) Callback provided in No_Blocking mode:
+ (++) HAL_UARTEx_WakeupCallback()
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief UART wakeup from Stop mode callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UARTEx_WakeupCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup UARTEx_Exported_Functions_Group3 Extended Peripheral Control functions
+ * @brief Extended Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides extended functions allowing to control the UART.
+ (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API sets Wakeup from Stop mode interrupt flag selection
+ (+) HAL_UARTEx_EnableStopMode() API allows the UART to wake up the MCU from Stop mode as
+ long as UART clock is HSI or LSE
+ (+) HAL_UARTEx_DisableStopMode() API disables the above feature
+ (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
+ detection length to more than 4 bits for multiprocessor address mark wake up.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Set Wakeup from Stop mode interrupt flag selection.
+ * @param huart UART handle.
+ * @param WakeUpSelection address match, Start Bit detection or RXNE bit status.
+ * This parameter can be one of the following values:
+ * @arg @ref UART_WAKEUP_ON_ADDRESS
+ * @arg @ref UART_WAKEUP_ON_STARTBIT
+ * @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tickstart = 0U;
+
+ /* check the wake-up from stop mode UART instance */
+ assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));
+ /* check the wake-up selection parameter */
+ assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent));
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the wake-up selection scheme */
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent);
+
+ if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS)
+ {
+ UART_Wakeup_AddressConfig(huart, WakeUpSelection);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_UART_ENABLE(huart);
+
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
+
+ /* Wait until REACK flag is set */
+ if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+ {
+ status = HAL_TIMEOUT;
+ }
+ else
+ {
+ /* Initialize the UART State */
+ huart->gState = HAL_UART_STATE_READY;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return status;
+}
+
+
+/**
+ * @brief Enable UART Stop Mode.
+ * @note The UART is able to wake up the MCU from Stop mode as long as UART clock is HSI or LSE.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart)
+{
+ /* Check parameter */
+ assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Set UESM bit */
+ SET_BIT(huart->Instance->CR1, USART_CR1_UESM);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable UART Stop Mode.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart)
+{
+ /* Check parameter */
+ assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Clear UESM bit */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief By default in multiprocessor mode, when the wake up method is set
+ * to address mark, the UART handles only 4-bit long addresses detection;
+ * this API allows to enable longer addresses detection (6-, 7- or 8-bit
+ * long).
+ * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode,
+ * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.
+ * @param huart UART handle.
+ * @param AddressLength this parameter can be one of the following values:
+ * @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address
+ * @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength)
+{
+ /* Check the UART handle allocation */
+ if(huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the address length parameter */
+ assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength));
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the address length */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength);
+
+ /* Enable the Peripheral */
+ __HAL_UART_ENABLE(huart);
+
+ /* TEACK and/or REACK to check before moving huart->gState to Ready */
+ return (UART_CheckIdleState(huart));
+}
+
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_UART_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_usart.c b/Src/stm32f3xx_hal_usart.c
new file mode 100644
index 0000000..0a1181f
--- /dev/null
+++ b/Src/stm32f3xx_hal_usart.c
@@ -0,0 +1,2383 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_usart.c
+ * @author MCD Application Team
+ * @brief USART HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Universal Synchronous Asynchronous Receiver Transmitter
+ * Peripheral (USART).
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State and Error functions
+ *
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ The USART HAL driver can be used as follows:
+
+ (#) Declare a USART_HandleTypeDef handle structure (eg. USART_HandleTypeDef husart).
+ (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit() API:
+ (++) Enable the USARTx interface clock.
+ (++) USART pins configuration:
+ (+++) Enable the clock for the USART GPIOs.
+ (+++) Configure these USART pins as alternate function pull-up.
+ (++) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),
+ HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
+ (+++) Configure the USARTx interrupt priority.
+ (+++) Enable the NVIC USART IRQ handle.
+ (++) USART interrupts handling:
+ -@@- The specific USART interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.
+ (++) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()
+ HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs):
+ (+++) Declare a DMA handle structure for the Tx/Rx channel.
+ (+++) Enable the DMAx interface clock.
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+ (+++) Configure the DMA Tx/Rx channel.
+ (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
+
+ (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
+ flow control and Mode (Receiver/Transmitter) in the husart handle Init structure.
+
+ (#) Initialize the USART registers by calling the HAL_USART_Init() API:
+ (++) This API configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)
+ by calling the customized HAL_USART_MspInit(&husart) API.
+
+ (#) Three operation modes are available within this driver :
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Send an amount of data in blocking mode using HAL_USART_Transmit()
+ (+) Receive an amount of data in blocking mode using HAL_USART_Receive()
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Send an amount of data in non blocking mode using HAL_USART_Transmit_IT()
+ (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback
+ (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_USART_TxCpltCallback
+ (+) Receive an amount of data in non blocking mode using HAL_USART_Receive_IT()
+ (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback
+ (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_USART_RxCpltCallback
+ (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_USART_ErrorCallback
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Send an amount of data in non blocking mode (DMA) using HAL_USART_Transmit_DMA()
+ (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback
+ (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_USART_TxCpltCallback
+ (+) Receive an amount of data in non blocking mode (DMA) using HAL_USART_Receive_DMA()
+ (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback
+ (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_USART_RxCpltCallback
+ (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_USART_ErrorCallback
+ (+) Pause the DMA Transfer using HAL_USART_DMAPause()
+ (+) Resume the DMA Transfer using HAL_USART_DMAResume()
+ (+) Stop the DMA Transfer using HAL_USART_DMAStop()
+
+ *** USART HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in USART HAL driver.
+
+ (+) __HAL_USART_ENABLE: Enable the USART peripheral
+ (+) __HAL_USART_DISABLE: Disable the USART peripheral
+ (+) __HAL_USART_GET_FLAG : Check whether the specified USART flag is set or not
+ (+) __HAL_USART_CLEAR_FLAG : Clear the specified USART pending flag
+ (+) __HAL_USART_ENABLE_IT: Enable the specified USART interrupt
+ (+) __HAL_USART_DISABLE_IT: Disable the specified USART interrupt
+
+ [..]
+ (@) You can refer to the USART HAL driver header file for more useful macros
+ [..]
+ (@) To configure and enable/disable the USART to wake up the MCU from stop mode, resort to UART API's
+ HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_UARTEx_EnableStopMode() and
+ HAL_UARTEx_DisableStopMode() in casting the USART handle to UART type UART_HandleTypeDef.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup USART USART
+ * @brief USART HAL module driver
+ * @{
+ */
+
+#ifdef HAL_USART_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup USART_Private_Constants USART Private Constants
+ * @{
+ */
+#define USART_DUMMY_DATA ((uint16_t) 0xFFFFU) /*!< USART transmitted dummy data */
+#define USART_TEACK_REACK_TIMEOUT ( 1000U) /*!< USART TX or RX enable acknowledge time-out value */
+#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
+ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< USART CR1 fields of parameters set by USART_SetConfig API */
+#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | \
+ USART_CR2_CLKEN | USART_CR2_LBCL | USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by USART_SetConfig API */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup USART_Private_Functions
+ * @{
+ */
+static void USART_EndTransfer(USART_HandleTypeDef *husart);
+static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void USART_DMAError(DMA_HandleTypeDef *hdma);
+static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
+static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart);
+static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart);
+static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart);
+static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart);
+static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart);
+static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup USART_Exported_Functions USART Exported Functions
+ * @{
+ */
+
+/** @defgroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the USART
+ in asynchronous and in synchronous modes.
+ (+) For the asynchronous mode only these parameters can be configured:
+ (++) Baud Rate
+ (++) Word Length
+ (++) Stop Bit
+ (++) Parity
+ (++) USART polarity
+ (++) USART phase
+ (++) USART LastBit
+ (++) Receiver/transmitter modes
+
+ [..]
+ The HAL_USART_Init() function follows the USART synchronous configuration
+ procedure (details for the procedure are available in reference manual).
+
+@endverbatim
+ * @{
+ */
+
+/*
+ Additional Table: If the parity is enabled, then the MSB bit of the data written
+ in the data register is transmitted but is changed by the parity bit.
+ According to device capability (support or not of 7-bit word length),
+ frame length is either defined by the M bit (8-bits or 9-bits)
+ or by the M1 and M0 bits (7-bit, 8-bit or 9-bit).
+ Possible USART frame formats are as listed in the following table:
+
+ Table 1. USART frame format.
+ +-----------------------------------------------------------------------+
+ | M bit | PCE bit | USART frame |
+ |-------------------|-----------|---------------------------------------|
+ | 0 | 0 | | SB | 8-bit data | STB | |
+ |-------------------|-----------|---------------------------------------|
+ | 0 | 1 | | SB | 7-bit data | PB | STB | |
+ |-------------------|-----------|---------------------------------------|
+ | 1 | 0 | | SB | 9-bit data | STB | |
+ |-------------------|-----------|---------------------------------------|
+ | 1 | 1 | | SB | 8-bit data | PB | STB | |
+ +-----------------------------------------------------------------------+
+ | M1 bit | M0 bit | PCE bit | USART frame |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 0 | 0 | | SB | 8 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 1 | 0 | | SB | 9 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 1 | 0 | 0 | | SB | 7 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
+ +-----------------------------------------------------------------------+
+
+*/
+
+/**
+ * @brief Initialize the USART mode according to the specified
+ * parameters in the USART_InitTypeDef and initialize the associated handle.
+ * @param husart USART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
+{
+ /* Check the USART handle allocation */
+ if(husart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_USART_INSTANCE(husart->Instance));
+
+ if(husart->State == HAL_USART_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ husart->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_USART_MspInit(husart);
+ }
+
+ husart->State = HAL_USART_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_USART_DISABLE(husart);
+
+ /* Set the Usart Communication parameters */
+ if (USART_SetConfig(husart) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ /* In Synchronous mode, the following bits must be kept cleared:
+ - LINEN bit in the USART_CR2 register
+ - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/
+ husart->Instance->CR2 &= ~USART_CR2_LINEN;
+ husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
+
+ /* Enable the Peripheral */
+ __HAL_USART_ENABLE(husart);
+
+ /* TEACK and/or REACK to check before moving husart->State to Ready */
+ return (USART_CheckIdleState(husart));
+}
+
+/**
+ * @brief DeInitialize the USART peripheral.
+ * @param husart USART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
+{
+ /* Check the USART handle allocation */
+ if(husart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_USART_INSTANCE(husart->Instance));
+
+ husart->State = HAL_USART_STATE_BUSY;
+
+ husart->Instance->CR1 = 0x0U;
+ husart->Instance->CR2 = 0x0U;
+ husart->Instance->CR3 = 0x0U;
+
+ /* DeInit the low level hardware */
+ HAL_USART_MspDeInit(husart);
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_RESET;
+
+ /* Process Unlock */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the USART MSP.
+ * @param husart USART handle.
+ * @retval None
+ */
+__weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_USART_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the USART MSP.
+ * @param husart USART handle.
+ * @retval None
+ */
+__weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_USART_MspDeInit can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Exported_Functions_Group2 IO operation functions
+ * @brief USART Transmit and Receive functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to manage the USART synchronous
+ data transfers.
+
+ [..] The USART supports master mode only: it cannot receive or send data related to an input
+ clock (SCLK is always an output).
+
+ (#) There are two modes of transfer:
+ (++) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode: The communication is performed using Interrupts
+ or DMA, These APIs return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks
+ will be executed respectively at the end of the transmit or Receive process
+ The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected
+
+ (#) Blocking mode APIs are :
+ (++) HAL_USART_Transmit() in simplex mode
+ (++) HAL_USART_Receive() in full duplex receive only
+ (++) HAL_USART_TransmitReceive() in full duplex mode
+
+ (#) No-Blocking mode APIs with Interrupt are :
+ (++) HAL_USART_Transmit_IT() in simplex mode
+ (++) HAL_USART_Receive_IT() in full duplex receive only
+ (++) HAL_USART_TransmitReceive_IT()in full duplex mode
+ (++) HAL_USART_IRQHandler()
+
+ (#) No-Blocking mode APIs with DMA are :
+ (++) HAL_USART_Transmit_DMA() in simplex mode
+ (++) HAL_USART_Receive_DMA() in full duplex receive only
+ (++) HAL_USART_TransmitReceive_DMA() in full duplex mode
+ (++) HAL_USART_DMAPause()
+ (++) HAL_USART_DMAResume()
+ (++) HAL_USART_DMAStop()
+
+ (#) A set of Transfer Complete Callbacks are provided in No-Blocking mode:
+ (++) HAL_USART_TxCpltCallback()
+ (++) HAL_USART_RxCpltCallback()
+ (++) HAL_USART_TxHalfCpltCallback()
+ (++) HAL_USART_RxHalfCpltCallback()
+ (++) HAL_USART_ErrorCallback()
+ (++) HAL_USART_TxRxCpltCallback()
+
+ (#) Non-Blocking mode transfers could be aborted using Abort API's :
+ (++) HAL_USART_Abort()
+ (++) HAL_USART_Abort_IT()
+
+ (#) For Abort services based on interrupts (HAL_USART_Abort_IT), a Abort Complete Callbacks is provided:
+ (++) HAL_USART_AbortCpltCallback()
+
+ (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
+ Errors are handled as follows :
+ (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+ to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
+ Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
+ and HAL_USART_ErrorCallback() user callback is executed. Transfer is kept ongoing on USART side.
+ If user wants to abort it, Abort services should be called by user.
+ (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+ This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
+ Error code is set to allow user to identify error type, and HAL_USART_ErrorCallback() user callback is executed.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Simplex send an amount of data in blocking mode.
+ * @param husart USART handle.
+ * @param pTxData Pointer to data buffer.
+ * @param Size Amount of data to be sent.
+ * @param Timeout Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
+{
+ uint16_t* tmp=0U;
+ uint32_t tickstart = 0U;
+
+ if(husart->State == HAL_USART_STATE_READY)
+ {
+ if((pTxData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_TX;
+
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
+
+ husart->TxXferSize = Size;
+ husart->TxXferCount = Size;
+
+ /* Check the remaining data to be sent */
+ while(husart->TxXferCount > 0U)
+ {
+ husart->TxXferCount--;
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ tmp = (uint16_t*) pTxData;
+ husart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
+ pTxData += 2U;
+ }
+ else
+ {
+ husart->Instance->TDR = (*pTxData++ & (uint8_t)0xFFU);
+ }
+ }
+
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* At end of Tx process, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode.
+ * @note To receive synchronous data, dummy data are simultaneously transmitted.
+ * @param husart USART handle.
+ * @param pRxData Pointer to data buffer.
+ * @param Size Amount of data to be received.
+ * @param Timeout Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
+{
+ uint16_t* tmp=0U;
+ uint16_t uhMask;
+ uint32_t tickstart = 0U;
+
+ if(husart->State == HAL_USART_STATE_READY)
+ {
+ if((pRxData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_RX;
+
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
+
+ husart->RxXferSize = Size;
+ husart->RxXferCount = Size;
+
+ /* Computation of USART mask to apply to RDR register */
+ USART_MASK_COMPUTATION(husart);
+ uhMask = husart->Mask;
+
+ /* as long as data have to be received */
+ while(husart->RxXferCount > 0U)
+ {
+ husart->RxXferCount--;
+
+ /* Wait until TC flag is set to send dummy byte in order to generate the
+ * clock for the slave to send data.
+ * Whatever the frame length (7, 8 or 9-bit long), the same dummy value
+ * can be written for all the cases. */
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x0FFU);
+
+ /* Wait for RXNE Flag */
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ tmp = (uint16_t*) pRxData ;
+ *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
+ pRxData +=2U;
+ }
+ else
+ {
+ *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
+ }
+ }
+
+ /* At end of Rx process, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Full-Duplex Send and Receive an amount of data in blocking mode.
+ * @param husart USART handle.
+ * @param pTxData pointer to TX data buffer.
+ * @param pRxData pointer to RX data buffer.
+ * @param Size amount of data to be sent (same amount to be received).
+ * @param Timeout Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
+{
+ uint16_t* tmp=0U;
+ uint16_t uhMask;
+ uint32_t tickstart = 0U;
+
+ if(husart->State == HAL_USART_STATE_READY)
+ {
+ if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_RX;
+
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
+
+ husart->RxXferSize = Size;
+ husart->TxXferSize = Size;
+ husart->TxXferCount = Size;
+ husart->RxXferCount = Size;
+
+ /* Computation of USART mask to apply to RDR register */
+ USART_MASK_COMPUTATION(husart);
+ uhMask = husart->Mask;
+
+ /* Check the remain data to be sent */
+ while(husart->TxXferCount > 0U)
+ {
+ husart->TxXferCount--;
+ husart->RxXferCount--;
+
+ /* Wait until TC flag is set to send data */
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ tmp = (uint16_t*) pTxData;
+ husart->Instance->TDR = (*tmp & uhMask);
+ pTxData += 2U;
+ }
+ else
+ {
+ husart->Instance->TDR = (*pTxData++ & (uint8_t)uhMask);
+ }
+
+ /* Wait for RXNE Flag */
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ tmp = (uint16_t*) pRxData ;
+ *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
+ pRxData +=2U;
+ }
+ else
+ {
+ *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
+ }
+ }
+
+ /* At end of TxRx process, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in interrupt mode.
+ * @param husart USART handle.
+ * @param pTxData pointer to data buffer.
+ * @param Size amount of data to be sent.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
+{
+ if(husart->State == HAL_USART_STATE_READY)
+ {
+ if((pTxData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->pTxBuffPtr = pTxData;
+ husart->TxXferSize = Size;
+ husart->TxXferCount = Size;
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_TX;
+
+ /* The USART Error Interrupts: (Frame error, noise error, overrun error)
+ are not managed by the USART Transmit Process to avoid the overrun interrupt
+ when the usart mode is configured for transmit and receive "USART_MODE_TX_RX"
+ to benefit for the frame error and noise interrupts the usart mode should be
+ configured only for transmit "USART_MODE_TX" */
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ /* Enable the USART Transmit Data Register Empty Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in interrupt mode.
+ * @note To receive synchronous data, dummy data are simultaneously transmitted.
+ * @param husart USART handle.
+ * @param pRxData pointer to data buffer.
+ * @param Size amount of data to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
+{
+ if(husart->State == HAL_USART_STATE_READY)
+ {
+ if((pRxData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->pRxBuffPtr = pRxData;
+ husart->RxXferSize = Size;
+ husart->RxXferCount = Size;
+
+ USART_MASK_COMPUTATION(husart);
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_RX;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ /* Enable the USART Parity Error and Data Register not empty Interrupts */
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
+
+ /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* Send dummy byte in order to generate the clock for the Slave to send the next data */
+ if(husart->Init.WordLength == USART_WORDLENGTH_9B)
+ {
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x01FFU);
+ }
+ else
+ {
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FFU);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Full-Duplex Send and Receive an amount of data in interrupt mode.
+ * @param husart USART handle.
+ * @param pTxData pointer to TX data buffer.
+ * @param pRxData pointer to RX data buffer.
+ * @param Size amount of data to be sent (same amount to be received).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
+{
+
+ if(husart->State == HAL_USART_STATE_READY)
+ {
+ if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->pRxBuffPtr = pRxData;
+ husart->RxXferSize = Size;
+ husart->RxXferCount = Size;
+ husart->pTxBuffPtr = pTxData;
+ husart->TxXferSize = Size;
+ husart->TxXferCount = Size;
+
+ /* Computation of USART mask to apply to RDR register */
+ USART_MASK_COMPUTATION(husart);
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_TX_RX;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the USART Parity Error and USART Data Register not empty Interrupts */
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
+
+ /* Enable the USART Transmit Data Register Empty Interrupt */
+ SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in DMA mode.
+ * @param husart USART handle.
+ * @param pTxData pointer to data buffer.
+ * @param Size amount of data to be sent.
+ * @note This function starts a DMA transfer in interrupt mode meaning that
+ * DMA half transfer complete, DMA transfer complete and DMA transfer
+ * error interrupts are enabled
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
+{
+ uint32_t *tmp=0U;
+
+ if(husart->State == HAL_USART_STATE_READY)
+ {
+ if((pTxData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->pTxBuffPtr = pTxData;
+ husart->TxXferSize = Size;
+ husart->TxXferCount = Size;
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_TX;
+
+ /* Set the USART DMA transfer complete callback */
+ husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
+
+ /* Set the USART DMA Half transfer complete callback */
+ husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
+
+ /* Set the DMA error callback */
+ husart->hdmatx->XferErrorCallback = USART_DMAError;
+
+ /* Enable the USART transmit DMA channel */
+ tmp = (uint32_t*)&pTxData;
+ HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
+
+ /* Clear the TC flag in the ICR register */
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the USART CR3 register */
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in DMA mode.
+ * @param husart USART handle.
+ * @param pRxData pointer to data buffer.
+ * @param Size amount of data to be received.
+ * @note When the USART parity is enabled (PCE = 1), the received data contain
+ * the parity bit (MSB position).
+ * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave.
+ * @note This function starts a DMA transfer in interrupt mode meaning that
+ * DMA half transfer complete, DMA transfer complete and DMA transfer
+ * error interrupts are enabled
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
+{
+ uint32_t *tmp;
+
+ /* Check that a Rx process is not already ongoing */
+ if(husart->State == HAL_USART_STATE_READY)
+ {
+ if((pRxData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->pRxBuffPtr = pRxData;
+ husart->RxXferSize = Size;
+ husart->pTxBuffPtr = pRxData;
+ husart->TxXferSize = Size;
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_RX;
+
+ /* Set the USART DMA Rx transfer complete callback */
+ husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
+
+ /* Set the USART DMA Half transfer complete callback */
+ husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
+
+ /* Set the USART DMA Rx transfer error callback */
+ husart->hdmarx->XferErrorCallback = USART_DMAError;
+
+ /* Enable the USART receive DMA channel */
+ tmp = (uint32_t*)&pRxData;
+ HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size);
+
+ /* Enable the USART transmit DMA channel: the transmit channel is used in order
+ to generate in the non-blocking mode the clock to the slave device,
+ this mode isn't a simplex receive mode but a full-duplex receive mode */
+ /* Set the USART DMA Tx Complete and Error callback to Null */
+ husart->hdmatx->XferErrorCallback = NULL;
+ husart->hdmatx->XferHalfCpltCallback = NULL;
+ husart->hdmatx->XferCpltCallback = NULL;
+ HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ /* Enable the USART Parity Error Interrupt */
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+
+ /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the USART CR3 register */
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the USART CR3 register */
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode.
+ * @param husart USART handle.
+ * @param pTxData pointer to TX data buffer.
+ * @param pRxData pointer to RX data buffer.
+ * @param Size amount of data to be received/sent.
+ * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
+ * @note This function starts a 2 DMA transfers in interrupt mode meaning that
+ * DMA half transfer complete, DMA transfer complete and DMA transfer
+ * error interrupts are enabled
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
+{
+ uint32_t *tmp;
+
+ if(husart->State == HAL_USART_STATE_READY)
+ {
+ if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->pRxBuffPtr = pRxData;
+ husart->RxXferSize = Size;
+ husart->pTxBuffPtr = pTxData;
+ husart->TxXferSize = Size;
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_TX_RX;
+
+ /* Set the USART DMA Rx transfer complete callback */
+ husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
+
+ /* Set the USART DMA Half transfer complete callback */
+ husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
+
+ /* Set the USART DMA Tx transfer complete callback */
+ husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
+
+ /* Set the USART DMA Half transfer complete callback */
+ husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
+
+ /* Set the USART DMA Tx transfer error callback */
+ husart->hdmatx->XferErrorCallback = USART_DMAError;
+
+ /* Set the USART DMA Rx transfer error callback */
+ husart->hdmarx->XferErrorCallback = USART_DMAError;
+
+ /* Enable the USART receive DMA channel */
+ tmp = (uint32_t*)&pRxData;
+ HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size);
+
+ /* Enable the USART transmit DMA channel */
+ tmp = (uint32_t*)&pTxData;
+ HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ /* Enable the USART Parity Error Interrupt */
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+
+ /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* Clear the TC flag in the ICR register */
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the USART CR3 register */
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the USART CR3 register */
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Pause the DMA Transfer.
+ * @param husart USART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart)
+{
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ if( (husart->State == HAL_USART_STATE_BUSY_TX) &&
+ (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)))
+ {
+ /* Disable the USART DMA Tx request */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+ }
+ else if( (husart->State == HAL_USART_STATE_BUSY_RX) ||
+ (husart->State == HAL_USART_STATE_BUSY_TX_RX) )
+ {
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
+ {
+ /* Disable the USART DMA Tx request */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+ }
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+ {
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the USART DMA Rx request */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resume the DMA Transfer.
+ * @param husart USART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)
+{
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ if(husart->State == HAL_USART_STATE_BUSY_TX)
+ {
+ /* Enable the USART DMA Tx request */
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+ }
+ else if( (husart->State == HAL_USART_STATE_BUSY_RX) ||
+ (husart->State == HAL_USART_STATE_BUSY_TX_RX) )
+ {
+ /* Clear the Overrun flag before resuming the Rx transfer*/
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF);
+
+ /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+ SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the USART DMA Rx request before the DMA Tx request */
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Enable the USART DMA Tx request */
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the DMA Transfer.
+ * @param husart USART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
+{
+ /* The Lock is not implemented on this API to allow the user application
+ to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback() /
+ HAL_USART_TxHalfCpltCallback() / HAL_USART_RxHalfCpltCallback ():
+ indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete interrupt is
+ generated if the DMA transfer interruption occurs at the middle or at the end of the stream
+ and the corresponding call back is executed.
+ */
+
+ /* Disable the USART Tx/Rx DMA requests */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the USART DMA tx channel */
+ if(husart->hdmatx != NULL)
+ {
+ HAL_DMA_Abort(husart->hdmatx);
+ }
+ /* Abort the USART DMA rx channel */
+ if(husart->hdmarx != NULL)
+ {
+ HAL_DMA_Abort(husart->hdmarx);
+ }
+
+ USART_EndTransfer(husart);
+ husart->State = HAL_USART_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing transfers (blocking mode).
+ * @param husart USART handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable USART Interrupts (Tx and Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart)
+{
+ /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the USART DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if(husart->hdmatx != NULL)
+ {
+ /* Set the USART DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ husart->hdmatx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(husart->hdmatx);
+ }
+ }
+
+ /* Disable the USART DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if(husart->hdmarx != NULL)
+ {
+ /* Set the USART DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ husart->hdmarx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(husart->hdmarx);
+ }
+ }
+
+ /* Reset Tx and Rx transfer counters */
+ husart->TxXferCount = 0U;
+ husart->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
+
+ /* Restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Reset Handle ErrorCode to No Error */
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing transfers (Interrupt mode).
+ * @param husart USART handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable USART Interrupts (Tx and Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart)
+{
+ uint32_t abortcplt = 1U;
+
+ /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* If DMA Tx and/or DMA Rx Handles are associated to USART Handle, DMA Abort complete callbacks should be initialised
+ before any call to DMA Abort functions */
+ /* DMA Tx Handle is valid */
+ if(husart->hdmatx != NULL)
+ {
+ /* Set DMA Abort Complete callback if USART DMA Tx request if enabled.
+ Otherwise, set it to NULL */
+ if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
+ {
+ husart->hdmatx->XferAbortCallback = USART_DMATxAbortCallback;
+ }
+ else
+ {
+ husart->hdmatx->XferAbortCallback = NULL;
+ }
+ }
+ /* DMA Rx Handle is valid */
+ if(husart->hdmarx != NULL)
+ {
+ /* Set DMA Abort Complete callback if USART DMA Rx request if enabled.
+ Otherwise, set it to NULL */
+ if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+ {
+ husart->hdmarx->XferAbortCallback = USART_DMARxAbortCallback;
+ }
+ else
+ {
+ husart->hdmarx->XferAbortCallback = NULL;
+ }
+ }
+
+ /* Disable the USART DMA Tx request if enabled */
+ if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
+ {
+ /* Disable DMA Tx at USART level */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the USART DMA Tx channel : use non blocking DMA Abort API (callback) */
+ if(husart->hdmatx != NULL)
+ {
+ /* USART Tx DMA Abort callback has already been initialised :
+ will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA TX */
+ if(HAL_DMA_Abort_IT(husart->hdmatx) != HAL_OK)
+ {
+ husart->hdmatx->XferAbortCallback = NULL;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+
+ /* Disable the USART DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */
+ if(husart->hdmarx != NULL)
+ {
+ /* USART Rx DMA Abort callback has already been initialised :
+ will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA RX */
+ if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
+ {
+ husart->hdmarx->XferAbortCallback = NULL;
+ abortcplt = 1U;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+
+ /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+ if (abortcplt == 1U)
+ {
+ /* Reset Tx and Rx transfer counters */
+ husart->TxXferCount = 0U;
+ husart->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
+
+ /* Restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_USART_AbortCpltCallback(husart);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle USART interrupt request.
+ * @param husart USART handle.
+ * @retval None
+ */
+void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
+{
+ uint32_t isrflags = READ_REG(husart->Instance->ISR);
+ uint32_t cr1its = READ_REG(husart->Instance->CR1);
+ uint32_t cr3its;
+ uint32_t errorflags;
+
+ /* If no error occurs */
+ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
+ if (errorflags == RESET)
+ {
+ /* USART in mode Receiver ---------------------------------------------------*/
+ if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ {
+ if(husart->State == HAL_USART_STATE_BUSY_RX)
+ {
+ USART_Receive_IT(husart);
+ }
+ else
+ {
+ USART_TransmitReceive_IT(husart);
+ }
+ return;
+ }
+ }
+
+ /* If some errors occur */
+ cr3its = READ_REG(husart->Instance->CR3);
+ if( (errorflags != RESET)
+ && ( ((cr3its & USART_CR3_EIE) != RESET)
+ || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) )
+ {
+ /* USART parity error interrupt occurred -------------------------------------*/
+ if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
+ {
+ __HAL_USART_CLEAR_IT(husart, USART_CLEAR_PEF);
+
+ husart->ErrorCode |= HAL_USART_ERROR_PE;
+ }
+
+ /* USART frame error interrupt occurred --------------------------------------*/
+ if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ {
+ __HAL_USART_CLEAR_IT(husart, USART_CLEAR_FEF);
+
+ husart->ErrorCode |= HAL_USART_ERROR_FE;
+ }
+
+ /* USART noise error interrupt occurred --------------------------------------*/
+ if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ {
+ __HAL_USART_CLEAR_IT(husart, USART_CLEAR_NEF);
+
+ husart->ErrorCode |= HAL_USART_ERROR_NE;
+ }
+
+ /* USART Over-Run interrupt occurred -----------------------------------------*/
+ if(((isrflags & USART_ISR_ORE) != RESET) &&
+ (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
+ {
+ __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF);
+
+ husart->ErrorCode |= HAL_USART_ERROR_ORE;
+ }
+
+ /* Call USART Error Call back function if need be --------------------------*/
+ if(husart->ErrorCode != HAL_USART_ERROR_NONE)
+ {
+ /* USART in mode Receiver ---------------------------------------------------*/
+ if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ {
+ if(husart->State == HAL_USART_STATE_BUSY_RX)
+ {
+ USART_Receive_IT(husart);
+ }
+ else
+ {
+ USART_TransmitReceive_IT(husart);
+ }
+ }
+
+ /* If Overrun error occurs, or if any error occurs in DMA mode reception,
+ consider error as blocking */
+ if (((husart->ErrorCode & HAL_USART_ERROR_ORE) != RESET) ||
+ (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)))
+ {
+ /* Blocking error : transfer is aborted
+ Set the USART state ready to be able to start again the process,
+ Disable Interrupts, and disable DMA requests, if ongoing */
+ USART_EndTransfer(husart);
+
+ /* Disable the USART DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR | USART_CR3_DMAR);
+
+ /* Abort the USART DMA Tx channel */
+ if(husart->hdmatx != NULL)
+ {
+ /* Set the USART Tx DMA Abort callback to NULL : no callback
+ executed at end of DMA abort procedure */
+ husart->hdmatx->XferAbortCallback = NULL;
+
+ /* Abort DMA TX */
+ HAL_DMA_Abort_IT(husart->hdmatx);
+ }
+
+ /* Abort the USART DMA Rx channel */
+ if(husart->hdmarx != NULL)
+ {
+ /* Set the USART Rx DMA Abort callback :
+ will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */
+ husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError;
+
+ /* Abort DMA RX */
+ if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
+ {
+ /* Call Directly husart->hdmarx->XferAbortCallback function in case of error */
+ husart->hdmarx->XferAbortCallback(husart->hdmarx);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+ HAL_USART_ErrorCallback(husart);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+ HAL_USART_ErrorCallback(husart);
+ }
+ }
+ else
+ {
+ /* Non Blocking error : transfer could go on.
+ Error is notified to user through user error callback */
+ HAL_USART_ErrorCallback(husart);
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ }
+ }
+ return;
+
+ } /* End if some error occurs */
+
+
+ /* USART in mode Transmitter ------------------------------------------------*/
+ if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
+ {
+ if(husart->State == HAL_USART_STATE_BUSY_TX)
+ {
+ USART_Transmit_IT(husart);
+ }
+ else
+ {
+ USART_TransmitReceive_IT(husart);
+ }
+ return;
+ }
+
+ /* USART in mode Transmitter (transmission end) -----------------------------*/
+ if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
+ {
+ USART_EndTransmit_IT(husart);
+ return;
+ }
+
+}
+
+/**
+ * @brief Tx Transfer completed callback.
+ * @param husart USART handle.
+ * @retval None
+ */
+__weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_USART_TxCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Tx Half Transfer completed callback.
+ * @param husart USART handle.
+ * @retval None
+ */
+__weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_USART_TxHalfCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callback.
+ * @param husart USART handle.
+ * @retval None
+ */
+__weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_USART_RxCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Rx Half Transfer completed callback.
+ * @param husart USART handle.
+ * @retval None
+ */
+__weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_USART_RxHalfCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx/Rx Transfers completed callback for the non-blocking process.
+ * @param husart USART handle.
+ * @retval None
+ */
+__weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_USART_TxRxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief USART error callback.
+ * @param husart USART handle.
+ * @retval None
+ */
+__weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_USART_ErrorCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief USART Abort Complete callback.
+ * @param husart USART handle.
+ * @retval None
+ */
+__weak void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_USART_AbortCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Exported_Functions_Group3 Peripheral State and Error functions
+ * @brief USART Peripheral State and Error functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State and Error functions #####
+ ==============================================================================
+ [..]
+ This subsection provides functions allowing to :
+ (+) Return the USART handle state
+ (+) Return the USART handle error code
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Return the USART handle state.
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART.
+ * @retval USART handle state
+ */
+HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart)
+{
+ return husart->State;
+}
+
+/**
+ * @brief Return the USART error code.
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART.
+ * @retval USART handle Error Code
+ */
+uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart)
+{
+ return husart->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Private_Functions USART Private Functions
+ * @brief USART Private functions
+ *
+@verbatim
+ [..]
+ This subsection provides a set of functions allowing to control the USART.
+ (+) USART_SetConfig() API is used to set the USART communication parameters.
+ (+) USART_CheckIdleState() APi ensures that TEACK and/or REACK bits are set after initialization
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief End ongoing transfer on USART peripheral (following error detection or Transfer completion).
+ * @param husart USART handle.
+ * @retval None
+ */
+static void USART_EndTransfer(USART_HandleTypeDef *husart)
+{
+ /* Disable TXEIE and TCIE interrupts */
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* At end of process, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+}
+
+/**
+ * @brief DMA USART transmit process complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
+
+ /* DMA Normal mode */
+ if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
+ {
+ husart->TxXferCount = 0U;
+
+ if(husart->State == HAL_USART_STATE_BUSY_TX)
+ {
+ /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+ in the USART CR3 register */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Enable the USART Transmit Complete Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
+ }
+ }
+ /* DMA Circular mode */
+ else
+ {
+ if(husart->State == HAL_USART_STATE_BUSY_TX)
+ {
+ HAL_USART_TxCpltCallback(husart);
+ }
+ }
+}
+
+/**
+ * @brief DMA USART transmit process half complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
+
+ HAL_USART_TxHalfCpltCallback(husart);
+}
+
+/**
+ * @brief DMA USART receive process complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
+
+ /* DMA Normal mode */
+ if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
+ {
+ husart->RxXferCount = 0U;
+
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit
+ in USART CR3 register */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+ /* similarly, disable the DMA TX transfer that was started to provide the
+ clock to the slave device */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+ if(husart->State == HAL_USART_STATE_BUSY_RX)
+ {
+ HAL_USART_RxCpltCallback(husart);
+ }
+ /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
+ else
+ {
+ HAL_USART_TxRxCpltCallback(husart);
+ }
+ husart->State= HAL_USART_STATE_READY;
+ }
+ /* DMA circular mode */
+ else
+ {
+ if(husart->State == HAL_USART_STATE_BUSY_RX)
+ {
+ HAL_USART_RxCpltCallback(husart);
+ }
+ /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
+ else
+ {
+ HAL_USART_TxRxCpltCallback(husart);
+ }
+ }
+
+}
+
+/**
+ * @brief DMA USART receive process half complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
+
+ HAL_USART_RxHalfCpltCallback(husart);
+}
+
+/**
+ * @brief DMA USART communication error callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void USART_DMAError(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
+
+ husart->RxXferCount = 0U;
+ husart->TxXferCount = 0U;
+ USART_EndTransfer(husart);
+
+ husart->ErrorCode |= HAL_USART_ERROR_DMA;
+ husart->State= HAL_USART_STATE_READY;
+
+ HAL_USART_ErrorCallback(husart);
+}
+
+/**
+ * @brief DMA USART communication abort callback, when initiated by HAL services on Error
+ * (To be called at end of DMA Abort procedure following error occurrence).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
+ husart->RxXferCount = 0U;
+ husart->TxXferCount = 0U;
+
+ HAL_USART_ErrorCallback(husart);
+}
+
+/**
+ * @brief DMA USART Tx communication abort callback, when initiated by user
+ * (To be called at end of DMA Tx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Rx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef* husart = (USART_HandleTypeDef* )(hdma->Parent);
+
+ husart->hdmatx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if(husart->hdmarx != NULL)
+ {
+ if(husart->hdmarx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ husart->TxXferCount = 0U;
+ husart->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
+
+ /* Restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_USART_AbortCpltCallback(husart);
+}
+
+
+/**
+ * @brief DMA USART Rx communication abort callback, when initiated by user
+ * (To be called at end of DMA Rx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Tx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef* husart = (USART_HandleTypeDef* )(hdma->Parent);
+
+ husart->hdmarx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if(husart->hdmatx != NULL)
+ {
+ if(husart->hdmatx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ husart->TxXferCount = 0U;
+ husart->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
+
+ /* Restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_USART_AbortCpltCallback(husart);
+}
+
+
+/**
+ * @brief Handle USART Communication Timeout.
+ * @param husart USART handle.
+ * @param Flag Specifies the USART flag to check.
+ * @param Status the Flag status (SET or RESET).
+ * @param Tickstart Tick start value
+ * @param Timeout timeout duration.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
+{
+ /* Wait until flag is set */
+ while((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ husart->State= HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Configure the USART peripheral.
+ * @param husart USART handle.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart)
+{
+ uint32_t tmpreg = 0x0U;
+ USART_ClockSourceTypeDef clocksource = USART_CLOCKSOURCE_UNDEFINED;
+ HAL_StatusTypeDef ret = HAL_OK;
+ uint16_t brrtemp = 0x0000U;
+ uint16_t usartdiv = 0x0000U;
+
+ /* Check the parameters */
+ assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity));
+ assert_param(IS_USART_PHASE(husart->Init.CLKPhase));
+ assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit));
+ assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate));
+ assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength));
+ assert_param(IS_USART_STOPBITS(husart->Init.StopBits));
+ assert_param(IS_USART_PARITY(husart->Init.Parity));
+ assert_param(IS_USART_MODE(husart->Init.Mode));
+
+
+ /*-------------------------- USART CR1 Configuration -----------------------*/
+ /* Clear M, PCE, PS, TE and RE bits and configure
+ * the USART Word Length, Parity and Mode:
+ * set the M bits according to husart->Init.WordLength value
+ * set PCE and PS bits according to husart->Init.Parity value
+ * set TE and RE bits according to husart->Init.Mode value
+ * force OVER8 to 1 to allow to reach the maximum speed (Fclock/8) */
+ tmpreg = (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8;
+ MODIFY_REG(husart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
+
+ /*---------------------------- USART CR2 Configuration ---------------------*/
+ /* Clear and configure the USART Clock, CPOL, CPHA, LBCL and STOP bits:
+ * set CPOL bit according to husart->Init.CLKPolarity value
+ * set CPHA bit according to husart->Init.CLKPhase value
+ * set LBCL bit according to husart->Init.CLKLastBit value
+ * set STOP[13:12] bits according to husart->Init.StopBits value */
+ tmpreg = (uint32_t)(USART_CLOCK_ENABLE);
+ tmpreg |= ((uint32_t)husart->Init.CLKPolarity | (uint32_t)husart->Init.CLKPhase);
+ tmpreg |= ((uint32_t)husart->Init.CLKLastBit | (uint32_t)husart->Init.StopBits);
+ MODIFY_REG(husart->Instance->CR2, USART_CR2_FIELDS, tmpreg);
+
+ /*-------------------------- USART CR3 Configuration -----------------------*/
+ /* no CR3 register configuration */
+
+ /*-------------------------- USART BRR Configuration -----------------------*/
+ /* BRR is filled-up according to OVER8 bit setting which is forced to 1 */
+ USART_GETCLOCKSOURCE(husart, clocksource);
+ switch (clocksource)
+ {
+ case USART_CLOCKSOURCE_PCLK1:
+ usartdiv = (uint16_t)(((2U*HAL_RCC_GetPCLK1Freq()) + (husart->Init.BaudRate/2U)) / husart->Init.BaudRate);
+ break;
+ case USART_CLOCKSOURCE_PCLK2:
+ usartdiv = (uint16_t)(((2U*HAL_RCC_GetPCLK2Freq()) + (husart->Init.BaudRate/2U)) / husart->Init.BaudRate);
+ break;
+ case USART_CLOCKSOURCE_HSI:
+ usartdiv = (uint16_t)(((2U*HSI_VALUE) + (husart->Init.BaudRate/2U)) / husart->Init.BaudRate);
+ break;
+ case USART_CLOCKSOURCE_SYSCLK:
+ usartdiv = (uint16_t)(((2U*HAL_RCC_GetSysClockFreq()) + (husart->Init.BaudRate/2U)) / husart->Init.BaudRate);
+ break;
+ case USART_CLOCKSOURCE_LSE:
+ usartdiv = (uint16_t)(((2U*LSE_VALUE) + (husart->Init.BaudRate/2U)) / husart->Init.BaudRate);
+ break;
+ case USART_CLOCKSOURCE_UNDEFINED:
+ default:
+ ret = HAL_ERROR;
+ break;
+ }
+
+ brrtemp = usartdiv & 0xFFF0U;
+ brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+ husart->Instance->BRR = brrtemp;
+
+ return ret;
+}
+
+/**
+ * @brief Check the USART Idle State.
+ * @param husart USART handle.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart)
+{
+ uint32_t tickstart = 0U;
+
+ /* Initialize the USART ErrorCode */
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
+
+ /* Check if the Transmitter is enabled */
+ if((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+ {
+ /* Wait until TEACK flag is set */
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ /* Timeout Occured */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* REACK bit in ISR is checked only when available (not to be checked on all instances).
+ Bit is defined only for USART instances supporting WakeUp from Stop Mode feature.
+ */
+ if (IS_UART_WAKEUP_FROMSTOP_INSTANCE(husart->Instance))
+ {
+ /* Check if the Receiver is enabled */
+ if((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+ {
+ /* Wait until REACK flag is set */
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ /* Timeout occurred */
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Initialize the USART state*/
+ husart->State= HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Simplex send an amount of data in non-blocking mode.
+ * @note Function called under interruption only, once
+ * interruptions have been enabled by HAL_USART_Transmit_IT().
+ * @note The USART errors are not managed to avoid the overrun error.
+ * @param husart USART handle.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart)
+{
+ uint16_t* tmp=0U;
+
+ /* Check that a Tx process is ongoing */
+ if(husart->State == HAL_USART_STATE_BUSY_TX)
+ {
+
+ if(husart->TxXferCount == 0U)
+ {
+ /* Disable the USART Transmit data register empty interrupt */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
+
+ /* Enable the USART Transmit Complete Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
+
+ return HAL_OK;
+ }
+ else
+ {
+ if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ tmp = (uint16_t*) husart->pTxBuffPtr;
+ husart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
+ husart->pTxBuffPtr += 2U;
+ }
+ else
+ {
+ husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0xFFU);
+ }
+
+ husart->TxXferCount--;
+
+ return HAL_OK;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+
+/**
+ * @brief Wraps up transmission in non-blocking mode.
+ * @param husart Pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart)
+{
+ /* Disable the USART Transmit Complete Interrupt */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TC);
+
+ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
+
+ /* Tx process is ended, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ HAL_USART_TxCpltCallback(husart);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Simplex receive an amount of data in non-blocking mode.
+ * @note Function called under interruption only, once
+ * interruptions have been enabled by HAL_USART_Receive_IT().
+ * @param husart USART handle
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)
+{
+ uint16_t* tmp=0U;
+ uint16_t uhMask = husart->Mask;
+
+ if(husart->State == HAL_USART_STATE_BUSY_RX)
+ {
+
+ if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ tmp = (uint16_t*) husart->pRxBuffPtr;
+ *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
+ husart->pRxBuffPtr += 2U;
+ }
+ else
+ {
+ *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
+ }
+
+ /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FFU);
+
+ if(--husart->RxXferCount == 0U)
+ {
+ /* Disable the USART Parity Error Interrupt and RXNE interrupt*/
+ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+
+ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* Rx process is completed, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ HAL_USART_RxCpltCallback(husart);
+
+ return HAL_OK;
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
+ * @note Function called under interruption only, once
+ * interruptions have been enabled by HAL_USART_TransmitReceive_IT().
+ * @param husart USART handle.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
+{
+ uint16_t* tmp=0U;
+ uint16_t uhMask = husart->Mask;
+
+ if(husart->State == HAL_USART_STATE_BUSY_TX_RX)
+ {
+
+ if(husart->TxXferCount != 0x00U)
+ {
+ if(__HAL_USART_GET_FLAG(husart, USART_FLAG_TXE) != RESET)
+ {
+ if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ tmp = (uint16_t*) husart->pTxBuffPtr;
+ husart->Instance->TDR = (uint16_t)(*tmp & uhMask);
+ husart->pTxBuffPtr += 2U;
+ }
+ else
+ {
+ husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)uhMask);
+ }
+ husart->TxXferCount--;
+
+ /* Check the latest data transmitted */
+ if(husart->TxXferCount == 0U)
+ {
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
+ }
+ }
+ }
+
+ if(husart->RxXferCount != 0x00U)
+ {
+ if(__HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE) != RESET)
+ {
+ if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ tmp = (uint16_t*) husart->pRxBuffPtr;
+ *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
+ husart->pRxBuffPtr += 2U;
+ }
+ else
+ {
+ *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
+ }
+ husart->RxXferCount--;
+ }
+ }
+
+ /* Check the latest data received */
+ if(husart->RxXferCount == 0U)
+ {
+ /* Disable the USART Parity Error Interrupt and RXNE interrupt*/
+ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+
+ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* Rx process is completed, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ HAL_USART_TxRxCpltCallback(husart);
+
+ return HAL_OK;
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_USART_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_hal_wwdg.c b/Src/stm32f3xx_hal_wwdg.c
new file mode 100644
index 0000000..2f2ef5d
--- /dev/null
+++ b/Src/stm32f3xx_hal_wwdg.c
@@ -0,0 +1,319 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_wwdg.c
+ * @author MCD Application Team
+ * @brief WWDG HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Window Watchdog (WWDG) peripheral:
+ * + Initialization and Configuration function
+ * + IO operation functions
+ @verbatim
+ ==============================================================================
+ ##### WWDG specific features #####
+ ==============================================================================
+ [..]
+ Once enabled the WWDG generates a system reset on expiry of a programmed
+ time period, unless the program refreshes the counter (T[6U;0] downcounter)
+ before reaching 0x3F value (i.e. a reset is generated when the counter
+ value rolls over from 0x40 to 0x3FU).
+
+ (+) An MCU reset is also generated if the counter value is refreshed
+ before the counter has reached the refresh window value. This
+ implies that the counter must be refreshed in a limited window.
+
+ (+) Once enabled the WWDG cannot be disabled except by a system reset.
+
+ (+) WWDGRST flag in RCC_CSR register informs when a WWDG reset has
+ occurred (check available with __HAL_RCC_GET_FLAG(RCC_FLAG_WWDGRST)).
+
+ (+) The WWDG downcounter input clock is derived from the APB clock divided
+ by a programmable prescaler.
+
+ (+) WWDG downcounter clock (Hz) = PCLK1 / (4096U * Prescaler)
+
+ (+) WWDG timeout (ms) = (1000U * (T[5U;0] + 1U)) / (WWDG downcounter clock)
+ where T[5U;0] are the lowest 6 bits of downcounter.
+
+ (+) WWDG Counter refresh is allowed between the following limits :
+ (++) min time (ms) = (1000U * (T[5U;0] - Window)) / (WWDG downcounter clock)
+ (++) max time (ms) = (1000U * (T[5U;0] - 0x40U)) / (WWDG downcounter clock)
+
+ (+) Min-max timeout value @42 MHz(PCLK1): ~97.5 us / ~49.9 ms
+
+ (+) The Early Wakeup Interrupt (EWI) can be used if specific safety
+ operations or data logging must be performed before the actual reset is
+ generated. When the downcounter reaches the value 0x40U, an EWI interrupt
+ is generated and the corresponding interrupt service routine (ISR) can
+ be used to trigger specific actions (such as communications or data
+ logging), before resetting the device.
+ In some applications, the EWI interrupt can be used to manage a software
+ system check and/or system recovery/graceful degradation, without
+ generating a WWDG reset. In this case, the corresponding interrupt
+ service routine (ISR) should reload the WWDG counter to avoid the WWDG
+ reset, then trigger the required actions.
+ Note:When the EWI interrupt cannot be served, e.g. due to a system lock
+ in a higher priority task, the WWDG reset will eventually be generated.
+
+ (+) Debug mode : When the microcontroller enters debug mode (core halted),
+ the WWDG counter either continues to work normally or stops, depending
+ on DBG_WWDG_STOP configuration bit in DBG module, accessible through
+ __HAL_DBGMCU_FREEZE_WWDG() and __HAL_DBGMCU_UNFREEZE_WWDG() macros
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
+
+ (+) Set the WWDG prescaler, refresh window, counter value and Early Wakeup
+ Interrupt mode using using HAL_WWDG_Init() function.
+ This enables WWDG peripheral and the downcounter starts downcounting
+ from given counter value.
+ Init function can be called again to modify all watchdog parameters,
+ however if EWI mode has been set once, it can't be clear until next
+ reset.
+
+ (+) The application program must refresh the WWDG counter at regular
+ intervals during normal operation to prevent an MCU reset using
+ HAL_WWDG_Refresh() function. This operation must occur only when
+ the counter is lower than the window value already programmed.
+
+ (+) if Early Wakeup Interrupt mode is enable an interrupt is generated when
+ the counter reaches 0x40. User can add his own code in weak function
+ HAL_WWDG_EarlyWakeupCallback().
+
+ *** WWDG HAL driver macros list ***
+ ==================================
+ [..]
+ Below the list of most used macros in WWDG HAL driver.
+
+ (+) __HAL_WWDG_GET_IT_SOURCE: Check the selected WWDG's interrupt source.
+ (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status.
+ (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+/** @defgroup WWDG WWDG
+ * @brief WWDG HAL module driver.
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup WWDG_Exported_Functions WWDG Exported Functions
+ * @{
+ */
+
+/** @defgroup WWDG_Exported_Functions_Group1 Initialization and Configuration functions
+ * @brief Initialization and Configuration functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and Configuration functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and start the WWDG according to the specified parameters
+ in the WWDG_InitTypeDef of associated handle.
+ (+) Initialize the WWDG MSP.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the WWDG according to the specified.
+ * parameters in the WWDG_InitTypeDef of associated handle.
+ * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
+{
+ /* Check the WWDG handle allocation */
+ if(hwwdg == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));
+ assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler));
+ assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window));
+ assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter));
+ assert_param(IS_WWDG_EWI_MODE(hwwdg->Init.EWIMode));
+
+ /* Init the low level hardware */
+ HAL_WWDG_MspInit(hwwdg);
+
+ /* Set WWDG Counter */
+ WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter));
+
+ /* Set WWDG Prescaler and Window */
+ WRITE_REG(hwwdg->Instance->CFR, (hwwdg->Init.EWIMode | hwwdg->Init.Prescaler | hwwdg->Init.Window));
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Initialize the WWDG MSP.
+ * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
+ * @note When rewriting this function in user file, mechanism may be added
+ * to avoid multiple initialize when HAL_WWDG_Init function is called
+ * again to change parameters.
+ * @retval None
+ */
+__weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hwwdg);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_WWDG_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions
+ * @brief IO operation functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Refresh the WWDG.
+ (+) Handle WWDG interrupt request and associated function callback.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Refresh the WWDG.
+ * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg)
+{
+ /* Write to WWDG CR the WWDG Counter value to refresh with */
+ WRITE_REG(hwwdg->Instance->CR, (hwwdg->Init.Counter));
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle WWDG interrupt request.
+ * @note The Early Wakeup Interrupt (EWI) can be used if specific safety operations
+ * or data logging must be performed before the actual reset is generated.
+ * The EWI interrupt is enabled by calling HAL_WWDG_Init function with
+ * EWIMode set to WWDG_EWI_ENABLE.
+ * When the downcounter reaches the value 0x40, and EWI interrupt is
+ * generated and the corresponding Interrupt Service Routine (ISR) can
+ * be used to trigger specific actions (such as communications or data
+ * logging), before resetting the device.
+ * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
+ * @retval None
+ */
+void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
+{
+ /* Check if Early Wakeup Interrupt is enable */
+ if(__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)
+ {
+ /* Check if WWDG Early Wakeup Interrupt occurred */
+ if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
+ {
+ /* Clear the WWDG Early Wakeup flag */
+ __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);
+
+ /* Early Wakeup callback */
+ HAL_WWDG_EarlyWakeupCallback(hwwdg);
+ }
+ }
+}
+
+/**
+ * @brief WWDG Early Wakeup callback.
+ * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
+ * @retval None
+ */
+__weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hwwdg);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_WWDG_EarlyWakeupCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_WWDG_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_ll_adc.c b/Src/stm32f3xx_ll_adc.c
new file mode 100644
index 0000000..6dc3487
--- /dev/null
+++ b/Src/stm32f3xx_ll_adc.c
@@ -0,0 +1,2009 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_adc.c
+ * @author MCD Application Team
+ * @brief ADC LL module driver
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_ll_adc.h"
+#include "stm32f3xx_ll_bus.h"
+
+#ifdef USE_FULL_ASSERT
+ #include "stm32_assert.h"
+#else
+ #define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+/* Note: Devices of STM32F3 serie embed 1 out of 2 different ADC IP. b */
+/* - STM32F30x, STM32F31x, STM32F32x, STM32F33x, STM32F35x, STM32F39x: */
+/* ADC IP 5Msamples/sec, from 1 to 4 ADC instances and other specific */
+/* features (refer to reference manual). */
+/* - STM32F37x: */
+/* ADC IP 1Msamples/sec, 1 ADC instance */
+/* This file contains the drivers of these ADC IP, located in 2 area */
+/* delimited by compilation switches. */
+
+#if defined(ADC5_V1_1)
+
+#if defined (ADC1) || defined (ADC2) || defined (ADC3) || defined (ADC4)
+
+/** @addtogroup ADC_LL ADC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup ADC_LL_Private_Constants
+ * @{
+ */
+
+/* Definitions of ADC hardware constraints delays */
+/* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
+/* not timeout values: */
+/* Timeout values for ADC operations are dependent to device clock */
+/* configuration (system clock versus ADC clock), */
+/* and therefore must be defined in user application. */
+/* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */
+/* values definition. */
+/* Note: ADC timeout values are defined here in CPU cycles to be independent */
+/* of device clock setting. */
+/* In user application, ADC timeout values should be defined with */
+/* temporal values, in function of device clock settings. */
+/* Highest ratio CPU clock frequency vs ADC clock frequency: */
+/* - ADC clock from synchronous clock with AHB prescaler 512, */
+/* APB prescaler 16, ADC prescaler 4. */
+/* - ADC clock from asynchronous clock (PLL) with prescaler 1, */
+/* with highest ratio CPU clock frequency vs HSI clock frequency: */
+/* CPU clock frequency max 72MHz, PLL frequency 72MHz: ratio 1. */
+/* Unit: CPU cycles. */
+#define ADC_CLOCK_RATIO_VS_CPU_HIGHEST ((uint32_t) 512U * 16U * 4U)
+#define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U)
+#define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U)
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @addtogroup ADC_LL_Private_Macros
+ * @{
+ */
+
+/* Check of parameters for configuration of ADC hierarchical scope: */
+/* common to several ADC instances. */
+#define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
+ ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \
+ )
+
+/* Check of parameters for configuration of ADC hierarchical scope: */
+/* ADC instance. */
+#define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
+ ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
+ || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
+ || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
+ || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
+ )
+
+#define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
+ ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
+ || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
+ )
+
+#define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
+ ( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
+ || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
+ )
+
+/* Check of parameters for configuration of ADC hierarchical scope: */
+/* ADC group regular */
+#if defined(STM32F303xE) || defined(STM32F398xx)
+#define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \
+ ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \
+ ? ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1_ADC12) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2_ADC12) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2_ADC12) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO_ADC12) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4_ADC12) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11_ADC12) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC12) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO_ADC12) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC12) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4_ADC12) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRG0_ADC12) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRG02_ADC12) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH1_ADC12) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH2_ADC12) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH3_ADC12) \
+ ) \
+ : \
+ ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1_ADC34) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3_ADC34) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1_ADC34) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO__ADC34) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2_ADC34) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1_ADC34) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO__ADC34) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO__ADC34) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO_ADC34) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1_ADC34) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRG0_ADC34) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRG02_ADC34) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH1_ADC34) \
+ ) \
+ )
+#elif defined(STM32F303xC) || defined(STM32F358xx)
+#define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \
+ ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \
+ ? ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1_ADC12) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2_ADC12) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2_ADC12) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO_ADC12) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4_ADC12) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11_ADC12) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC12) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO_ADC12) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC12) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4_ADC12) \
+ ) \
+ : \
+ ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1_ADC34) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3_ADC34) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1_ADC34) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO__ADC34) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2_ADC34) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1_ADC34) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO__ADC34) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO__ADC34) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO_ADC34) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1_ADC34) \
+ ) \
+ )
+#elif defined(STM32F303x8) || defined(STM32F328xx)
+#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
+ ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \
+ )
+#elif defined(STM32F334x8)
+#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
+ ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG1) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG3) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \
+ )
+#elif defined(STM32F302xC) || defined(STM32F302xE)
+#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
+ ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \
+ )
+#elif defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
+ ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
+ )
+#endif
+
+#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
+ ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
+ || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
+ )
+
+#define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
+ ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
+ || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
+ || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
+ )
+
+#define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \
+ ( ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \
+ || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \
+ )
+
+#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
+ ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \
+ )
+
+#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
+ ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \
+ )
+
+/* Check of parameters for configuration of ADC hierarchical scope: */
+/* ADC group injected */
+#if defined(STM32F303xE) || defined(STM32F398xx)
+#define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \
+ ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \
+ ? ( ((__INJ_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO_ADC12) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1_ADC12) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4_ADC12) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO_ADC12) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15_ADC12) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC12) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3_ADC12) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1_ADC12) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO_ADC12) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO_ADC12) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2_ADC12) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH4_ADC12) \
+ ) \
+ : \
+ ( ((__INJ_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3_ADC34) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2_ADC34) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4__ADC34) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4_ADC34) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO__ADC34) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3_ADC34) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO__ADC34) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO_ADC34) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRG_ADC34) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRG2_ADC34) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH2) \
+ ) \
+ )
+#elif defined(STM32F303xC) || defined(STM32F358xx)
+#define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \
+ ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \
+ ? ( ((__INJ_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO_ADC12) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1_ADC12) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4_ADC12) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO_ADC12) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15_ADC12) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC12) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3_ADC12) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1_ADC12) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO_ADC12) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
+ ) \
+ : \
+ ( ((__INJ_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3_ADC34) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2_ADC34) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4__ADC34) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4_ADC34) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO__ADC34) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3_ADC34) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO__ADC34) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO_ADC34) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
+ ) \
+ )
+
+#elif defined(STM32F303x8) || defined(STM32F328xx)
+#define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
+ ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
+ )
+#elif defined(STM32F334x8)
+#define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
+ ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
+ )
+#elif defined(STM32F302xC) || defined(STM32F302xE)
+#define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
+ ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
+ )
+#elif defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
+ ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
+ )
+#endif
+
+#define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \
+ ( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \
+ || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \
+ || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \
+ )
+
+#define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
+ ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
+ || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \
+ )
+
+#define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
+ ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
+ || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
+ || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
+ || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \
+ )
+
+#define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
+ ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
+ || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \
+ )
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/* Check of parameters for configuration of ADC hierarchical scope: */
+/* multimode. */
+#define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
+ ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
+ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
+ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \
+ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
+ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
+ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
+ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
+ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \
+ )
+
+#define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \
+ ( ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \
+ || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B) \
+ || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B) \
+ || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B) \
+ || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B) \
+ )
+
+#define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \
+ ( ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) \
+ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) \
+ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) \
+ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) \
+ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) \
+ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) \
+ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) \
+ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) \
+ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) \
+ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) \
+ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) \
+ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) \
+ )
+
+#define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \
+ ( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \
+ || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \
+ || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \
+ )
+
+#endif /* ADC_MULTIMODE_SUPPORT */
+/**
+ * @}
+ */
+
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADC_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup ADC_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize registers of all ADC instances belonging to
+ * the same ADC common instance to their default reset values.
+ * @note This function is performing a hard reset, using high level
+ * clock source RCC ADC reset.
+ * Caution: On this STM32 serie, if several ADC instances are available
+ * on the selected device, RCC ADC reset will reset
+ * all ADC instances belonging to the common ADC instance.
+ * To de-initialize only 1 ADC instance, use
+ * function @ref LL_ADC_DeInit().
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC common registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
+
+ /* Force reset of ADC clock (core clock) */
+ #if defined(ADC1) && defined(ADC2) && defined(ADC3) && defined(ADC4)
+ if(ADCxy_COMMON == ADC12_COMMON)
+ {
+ LL_AHB1_GRP1_ForceReset (LL_AHB1_GRP1_PERIPH_ADC12);
+ }
+ else
+ {
+ LL_AHB1_GRP1_ForceReset (LL_AHB1_GRP1_PERIPH_ADC34);
+ }
+ #elif defined(ADC1) && defined(ADC2)
+ LL_AHB1_GRP1_ForceReset (LL_AHB1_GRP1_PERIPH_ADC12);
+ #elif defined(ADC1)
+ LL_AHB1_GRP1_ForceReset (LL_AHB1_GRP1_PERIPH_ADC1);
+ #endif
+
+ /* Release reset of ADC clock (core clock) */
+ #if defined(ADC1) && defined(ADC2) && defined(ADC3) && defined(ADC4)
+ if(ADCxy_COMMON == ADC12_COMMON)
+ {
+ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ADC12);
+ }
+ else
+ {
+ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ADC34);
+ }
+ #elif defined(ADC1) && defined(ADC2)
+ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ADC12);
+ #elif defined(ADC1)
+ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ADC1);
+ #endif
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Initialize some features of ADC common parameters
+ * (all ADC instances belonging to the same ADC common instance)
+ * and multimode (for devices with several ADC instances available).
+ * @note The setting of ADC common parameters is conditioned to
+ * ADC instances state:
+ * All ADC instances belonging to the same ADC common instance
+ * must be disabled.
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC common registers are initialized
+ * - ERROR: ADC common registers are not initialized
+ */
+ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
+ assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock));
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+ assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode));
+ if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
+ {
+ assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer));
+ assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay));
+ }
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ /* Note: Hardware constraint (refer to description of functions */
+ /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */
+ /* On this STM32 serie, setting of these features is conditioned to */
+ /* ADC state: */
+ /* All ADC instances of the ADC common group must be disabled. */
+ if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U)
+ {
+ /* Configuration of ADC hierarchical scope: */
+ /* - common to several ADC */
+ /* (all ADC instances belonging to the same ADC common instance) */
+ /* - Set ADC clock (conversion clock) */
+ /* - multimode (if several ADC instances available on the */
+ /* selected device) */
+ /* - Set ADC multimode configuration */
+ /* - Set ADC multimode DMA transfer */
+ /* - Set ADC multimode: delay between 2 sampling phases */
+#if defined(ADC_MULTIMODE_SUPPORT)
+ if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
+ {
+ MODIFY_REG(ADCxy_COMMON->CCR,
+ ADC_CCR_CKMODE
+ | ADC_CCR_DUAL
+ | ADC_CCR_MDMA
+ | ADC_CCR_DELAY
+ ,
+ ADC_CommonInitStruct->CommonClock
+ | ADC_CommonInitStruct->Multimode
+ | ADC_CommonInitStruct->MultiDMATransfer
+ | ADC_CommonInitStruct->MultiTwoSamplingDelay
+ );
+ }
+ else
+ {
+ MODIFY_REG(ADCxy_COMMON->CCR,
+ ADC_CCR_CKMODE
+ | ADC_CCR_DUAL
+ | ADC_CCR_MDMA
+ | ADC_CCR_DELAY
+ ,
+ ADC_CommonInitStruct->CommonClock
+ | LL_ADC_MULTI_INDEPENDENT
+ );
+ }
+#else
+ LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock);
+#endif
+ }
+ else
+ {
+ /* Initialization error: One or several ADC instances belonging to */
+ /* the same ADC common instance are not disabled. */
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
+ * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
+{
+ /* Set ADC_CommonInitStruct fields to default values */
+ /* Set fields of ADC common */
+ /* (all ADC instances belonging to the same ADC common instance) */
+ ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+ /* Set fields of ADC multimode */
+ ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT;
+ ADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC;
+ ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE;
+#endif /* ADC_MULTIMODE_SUPPORT */
+}
+
+/**
+ * @brief De-initialize registers of the selected ADC instance
+ * to their default reset values.
+ * @note To reset all ADC instances quickly (perform a hard reset),
+ * use function @ref LL_ADC_CommonDeInit().
+ * @note If this functions returns error status, it means that ADC instance
+ * is in an unknown state.
+ * In this case, perform a hard reset using high level
+ * clock source RCC ADC reset.
+ * Caution: On this STM32 serie, if several ADC instances are available
+ * on the selected device, RCC ADC reset will reset
+ * all ADC instances belonging to the common ADC instance.
+ * Refer to function @ref LL_ADC_CommonDeInit().
+ * @param ADCx ADC instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC registers are de-initialized
+ * - ERROR: ADC registers are not de-initialized
+ */
+ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
+{
+ ErrorStatus status = SUCCESS;
+
+ __IO uint32_t timeout_cpu_cycles = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+
+ /* Disable ADC instance if not already disabled. */
+ if(LL_ADC_IsEnabled(ADCx) == 1U)
+ {
+ /* Set ADC group regular trigger source to SW start to ensure to not */
+ /* have an external trigger event occurring during the conversion stop */
+ /* ADC disable process. */
+ LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
+
+ /* Stop potential ADC conversion on going on ADC group regular. */
+ if(LL_ADC_REG_IsConversionOngoing(ADCx) != 0U)
+ {
+ if(LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0U)
+ {
+ LL_ADC_REG_StopConversion(ADCx);
+ }
+ }
+
+ /* Set ADC group injected trigger source to SW start to ensure to not */
+ /* have an external trigger event occurring during the conversion stop */
+ /* ADC disable process. */
+ LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
+
+ /* Stop potential ADC conversion on going on ADC group injected. */
+ if(LL_ADC_INJ_IsConversionOngoing(ADCx) != 0U)
+ {
+ if(LL_ADC_INJ_IsStopConversionOngoing(ADCx) == 0U)
+ {
+ LL_ADC_INJ_StopConversion(ADCx);
+ }
+ }
+
+ /* Wait for ADC conversions are effectively stopped */
+ timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
+ while (( LL_ADC_REG_IsStopConversionOngoing(ADCx)
+ | LL_ADC_INJ_IsStopConversionOngoing(ADCx)) == 1U)
+ {
+ if(timeout_cpu_cycles-- == 0U)
+ {
+ /* Time-out error */
+ status = ERROR;
+ }
+ }
+
+ /* Flush group injected contexts queue (register JSQR): */
+ /* Note: Bit JQM must be set to empty the contexts queue (otherwise */
+ /* contexts queue is maintained with the last active context). */
+ LL_ADC_INJ_SetQueueMode(ADCx, LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY);
+
+ /* Disable the ADC instance */
+ LL_ADC_Disable(ADCx);
+
+ /* Wait for ADC instance is effectively disabled */
+ timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
+ while (LL_ADC_IsDisableOngoing(ADCx) == 1U)
+ {
+ if(timeout_cpu_cycles-- == 0U)
+ {
+ /* Time-out error */
+ status = ERROR;
+ }
+ }
+ }
+
+ /* Check whether ADC state is compliant with expected state */
+ if(READ_BIT(ADCx->CR,
+ ( ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
+ | ADC_CR_ADDIS | ADC_CR_ADEN )
+ )
+ == 0U)
+ {
+ /* ========== Reset ADC registers ========== */
+ /* Reset register IER */
+ CLEAR_BIT(ADCx->IER,
+ ( LL_ADC_IT_ADRDY
+ | LL_ADC_IT_EOC
+ | LL_ADC_IT_EOS
+ | LL_ADC_IT_OVR
+ | LL_ADC_IT_EOSMP
+ | LL_ADC_IT_JEOC
+ | LL_ADC_IT_JEOS
+ | LL_ADC_IT_JQOVF
+ | LL_ADC_IT_AWD1
+ | LL_ADC_IT_AWD2
+ | LL_ADC_IT_AWD3 )
+ );
+
+ /* Reset register ISR */
+ SET_BIT(ADCx->ISR,
+ ( LL_ADC_FLAG_ADRDY
+ | LL_ADC_FLAG_EOC
+ | LL_ADC_FLAG_EOS
+ | LL_ADC_FLAG_OVR
+ | LL_ADC_FLAG_EOSMP
+ | LL_ADC_FLAG_JEOC
+ | LL_ADC_FLAG_JEOS
+ | LL_ADC_FLAG_JQOVF
+ | LL_ADC_FLAG_AWD1
+ | LL_ADC_FLAG_AWD2
+ | LL_ADC_FLAG_AWD3 )
+ );
+
+ /* Reset register CR */
+ /* - Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, */
+ /* ADC_CR_ADCAL, ADC_CR_ADDIS, ADC_CR_ADEN are in */
+ /* access mode "read-set": no direct reset applicable. */
+ /* - Reset Calibration mode to default setting (single ended). */
+ /* - Disable ADC internal voltage regulator. */
+ /* Note: ADC internal voltage regulator disable is conditioned to */
+ /* ADC state disabled: already done above. */
+ /* Sequence to disable voltage regulator: */
+ /* 1. Set the intermediate state before moving the ADC voltage regulator */
+ /* to disable state. */
+ CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN_1 | ADC_CR_ADVREGEN_0 | ADC_CR_ADCALDIF);
+ /* 2. Set ADVREGEN bits to 0x10 */
+ SET_BIT(ADCx->CR, ADC_CR_ADVREGEN_1);
+
+ /* Reset register CFGR */
+ CLEAR_BIT(ADCx->CFGR,
+ ( ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN
+ | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM
+ | ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN
+ | ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD
+ | ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN
+ | ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN )
+ );
+
+ /* Reset register SMPR1 */
+ CLEAR_BIT(ADCx->SMPR1,
+ ( ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7
+ | ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4
+ | ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1)
+ );
+
+ /* Reset register SMPR2 */
+ CLEAR_BIT(ADCx->SMPR2,
+ ( ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16
+ | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13
+ | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10)
+ );
+
+ /* Reset register TR1 */
+ MODIFY_REG(ADCx->TR1, ADC_TR1_HT1 | ADC_TR1_LT1, ADC_TR1_HT1);
+
+ /* Reset register TR2 */
+ MODIFY_REG(ADCx->TR2, ADC_TR2_HT2 | ADC_TR2_LT2, ADC_TR2_HT2);
+
+ /* Reset register TR3 */
+ MODIFY_REG(ADCx->TR3, ADC_TR3_HT3 | ADC_TR3_LT3, ADC_TR3_HT3);
+
+ /* Reset register SQR1 */
+ CLEAR_BIT(ADCx->SQR1,
+ ( ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2
+ | ADC_SQR1_SQ1 | ADC_SQR1_L)
+ );
+
+ /* Reset register SQR2 */
+ CLEAR_BIT(ADCx->SQR2,
+ ( ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7
+ | ADC_SQR2_SQ6 | ADC_SQR2_SQ5)
+ );
+
+ /* Reset register SQR3 */
+ CLEAR_BIT(ADCx->SQR3,
+ ( ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12
+ | ADC_SQR3_SQ11 | ADC_SQR3_SQ10)
+ );
+
+ /* Reset register SQR4 */
+ CLEAR_BIT(ADCx->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
+
+ /* Reset register JSQR */
+ CLEAR_BIT(ADCx->JSQR,
+ ( ADC_JSQR_JL
+ | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN
+ | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3
+ | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 )
+ );
+
+ /* Flush ADC group injected contexts queue */
+ SET_BIT(ADCx->CFGR, ADC_CFGR_JQM);
+ CLEAR_BIT(ADCx->CFGR, ADC_CFGR_JQM);
+ /* Reset register ISR bit JQOVF (set by previous operation on JSQR) */
+ SET_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF);
+
+ /* Reset register DR */
+ /* Note: bits in access mode read only, no direct reset applicable */
+
+ /* Reset register OFR1 */
+ CLEAR_BIT(ADCx->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1);
+ /* Reset register OFR2 */
+ CLEAR_BIT(ADCx->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2);
+ /* Reset register OFR3 */
+ CLEAR_BIT(ADCx->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3);
+ /* Reset register OFR4 */
+ CLEAR_BIT(ADCx->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4);
+
+ /* Reset registers JDR1, JDR2, JDR3, JDR4 */
+ /* Note: bits in access mode read only, no direct reset applicable */
+
+ /* Reset register AWD2CR */
+ CLEAR_BIT(ADCx->AWD2CR, ADC_AWD2CR_AWD2CH);
+
+ /* Reset register AWD3CR */
+ CLEAR_BIT(ADCx->AWD3CR, ADC_AWD3CR_AWD3CH);
+
+ /* Reset register DIFSEL */
+ CLEAR_BIT(ADCx->DIFSEL, ADC_DIFSEL_DIFSEL);
+
+ /* Reset register CALFACT */
+ CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
+ }
+ else
+ {
+ /* ADC instance is in an unknown state */
+ /* Need to performing a hard reset of ADC instance, using high level */
+ /* clock source RCC ADC reset. */
+ /* Caution: On this STM32 serie, if several ADC instances are available */
+ /* on the selected device, RCC ADC reset will reset */
+ /* all ADC instances belonging to the common ADC instance. */
+ /* Caution: On this STM32 serie, if several ADC instances are available */
+ /* on the selected device, RCC ADC reset will reset */
+ /* all ADC instances belonging to the common ADC instance. */
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Initialize some features of ADC instance.
+ * @note These parameters have an impact on ADC scope: ADC instance.
+ * Affects both group regular and group injected (availability
+ * of ADC group injected depends on STM32 families).
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Instance .
+ * @note The setting of these parameters by function @ref LL_ADC_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 families. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ * @note After using this function, some other features must be configured
+ * using LL unitary functions.
+ * The minimum configuration remaining to be done is:
+ * - Set ADC group regular or group injected sequencer:
+ * map channel on the selected sequencer rank.
+ * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
+ * - Set ADC channel sampling time
+ * Refer to function LL_ADC_SetChannelSamplingTime();
+ * @param ADCx ADC instance
+ * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC registers are initialized
+ * - ERROR: ADC registers are not initialized
+ */
+ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+
+ assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
+ assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
+ assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode));
+
+ /* Note: Hardware constraint (refer to description of this function): */
+ /* ADC instance must be disabled. */
+ if(LL_ADC_IsEnabled(ADCx) == 0U)
+ {
+ /* Configuration of ADC hierarchical scope: */
+ /* - ADC instance */
+ /* - Set ADC data resolution */
+ /* - Set ADC conversion data alignment */
+ /* - Set ADC low power mode */
+ MODIFY_REG(ADCx->CFGR,
+ ADC_CFGR_RES
+ | ADC_CFGR_ALIGN
+ | ADC_CFGR_AUTDLY
+ ,
+ ADC_InitStruct->Resolution
+ | ADC_InitStruct->DataAlignment
+ | ADC_InitStruct->LowPowerMode
+ );
+
+ }
+ else
+ {
+ /* Initialization error: ADC instance is not disabled. */
+ status = ERROR;
+ }
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
+ * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
+{
+ /* Set ADC_InitStruct fields to default values */
+ /* Set fields of ADC instance */
+ ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
+ ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
+ ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE;
+
+}
+
+/**
+ * @brief Initialize some features of ADC group regular.
+ * @note These parameters have an impact on ADC scope: ADC group regular.
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+ * (functions with prefix "REG").
+ * @note The setting of these parameters by function @ref LL_ADC_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 families. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ * @note After using this function, other features must be configured
+ * using LL unitary functions.
+ * The minimum configuration remaining to be done is:
+ * - Set ADC group regular or group injected sequencer:
+ * map channel on the selected sequencer rank.
+ * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
+ * - Set ADC channel sampling time
+ * Refer to function LL_ADC_SetChannelSamplingTime();
+ * @param ADCx ADC instance
+ * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC registers are initialized
+ * - ERROR: ADC registers are not initialized
+ */
+ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+#if defined(ADC1) && defined(ADC2) && defined(ADC3) && defined(ADC4)
+ assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADCx, ADC_REG_InitStruct->TriggerSource));
+#else
+ assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
+#endif
+ assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
+ if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
+ {
+ assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
+ }
+ assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
+ assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
+ assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun));
+
+ /* Note: Hardware constraint (refer to description of this function): */
+ /* ADC instance must be disabled. */
+ if(LL_ADC_IsEnabled(ADCx) == 0U)
+ {
+ /* Configuration of ADC hierarchical scope: */
+ /* - ADC group regular */
+ /* - Set ADC group regular trigger source */
+ /* - Set ADC group regular sequencer length */
+ /* - Set ADC group regular sequencer discontinuous mode */
+ /* - Set ADC group regular continuous mode */
+ /* - Set ADC group regular conversion data transfer: no transfer or */
+ /* transfer by DMA, and DMA requests mode */
+ /* - Set ADC group regular overrun behavior */
+ /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
+ /* setting of trigger source to SW start. */
+ if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
+ {
+ MODIFY_REG(ADCx->CFGR,
+ ADC_CFGR_EXTSEL
+ | ADC_CFGR_EXTEN
+ | ADC_CFGR_DISCEN
+ | ADC_CFGR_DISCNUM
+ | ADC_CFGR_CONT
+ | ADC_CFGR_DMAEN
+ | ADC_CFGR_DMACFG
+ | ADC_CFGR_OVRMOD
+ ,
+ ADC_REG_InitStruct->TriggerSource
+ | ADC_REG_InitStruct->SequencerDiscont
+ | ADC_REG_InitStruct->ContinuousMode
+ | ADC_REG_InitStruct->DMATransfer
+ | ADC_REG_InitStruct->Overrun
+ );
+ }
+ else
+ {
+ MODIFY_REG(ADCx->CFGR,
+ ADC_CFGR_EXTSEL
+ | ADC_CFGR_EXTEN
+ | ADC_CFGR_DISCEN
+ | ADC_CFGR_DISCNUM
+ | ADC_CFGR_CONT
+ | ADC_CFGR_DMAEN
+ | ADC_CFGR_DMACFG
+ | ADC_CFGR_OVRMOD
+ ,
+ ADC_REG_InitStruct->TriggerSource
+ | LL_ADC_REG_SEQ_DISCONT_DISABLE
+ | ADC_REG_InitStruct->ContinuousMode
+ | ADC_REG_InitStruct->DMATransfer
+ | ADC_REG_InitStruct->Overrun
+ );
+ }
+
+ /* Set ADC group regular sequencer length and scan direction */
+ LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
+ }
+ else
+ {
+ /* Initialization error: ADC instance is not disabled. */
+ status = ERROR;
+ }
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
+ * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
+{
+ /* Set ADC_REG_InitStruct fields to default values */
+ /* Set fields of ADC group regular */
+ /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
+ /* setting of trigger source to SW start. */
+ ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
+ ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
+ ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
+ ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
+ ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
+ ADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
+}
+
+/**
+ * @brief Initialize some features of ADC group injected.
+ * @note These parameters have an impact on ADC scope: ADC group injected.
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+ * (functions with prefix "INJ").
+ * @note The setting of these parameters by function @ref LL_ADC_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 families. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ * @note After using this function, other features must be configured
+ * using LL unitary functions.
+ * The minimum configuration remaining to be done is:
+ * - Set ADC group injected sequencer:
+ * map channel on the selected sequencer rank.
+ * Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
+ * - Set ADC channel sampling time
+ * Refer to function LL_ADC_SetChannelSamplingTime();
+ * @note Caution to ADC group injected contexts queue: On this STM32 serie,
+ * using successively several times this function will appear has
+ * having no effect.
+ * This is due to ADC group injected contexts queue (this feature
+ * cannot be disabled on this STM32 serie).
+ * To set several features of ADC group injected, use
+ * function @ref LL_ADC_INJ_ConfigQueueContext().
+ * @param ADCx ADC instance
+ * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC registers are initialized
+ * - ERROR: ADC registers are not initialized
+ */
+ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+#if defined(ADC1) && defined(ADC2) && defined(ADC3) && defined(ADC4)
+ assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADCx, ADC_INJ_InitStruct->TriggerSource));
+#else
+ assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource));
+#endif
+ assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
+ if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
+ {
+ assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
+ }
+ assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
+
+ /* Note: Hardware constraint (refer to description of this function): */
+ /* ADC instance must be disabled. */
+ if(LL_ADC_IsEnabled(ADCx) == 0U)
+ {
+ /* Configuration of ADC hierarchical scope: */
+ /* - ADC group injected */
+ /* - Set ADC group injected trigger source */
+ /* - Set ADC group injected sequencer length */
+ /* - Set ADC group injected sequencer discontinuous mode */
+ /* - Set ADC group injected conversion trigger: independent or */
+ /* from ADC group regular */
+ /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
+ /* setting of trigger source to SW start. */
+ if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
+ {
+ MODIFY_REG(ADCx->CFGR,
+ ADC_CFGR_JDISCEN
+ | ADC_CFGR_JAUTO
+ ,
+ ADC_INJ_InitStruct->SequencerDiscont
+ | ADC_INJ_InitStruct->TrigAuto
+ );
+ }
+ else
+ {
+ MODIFY_REG(ADCx->CFGR,
+ ADC_CFGR_JDISCEN
+ | ADC_CFGR_JAUTO
+ ,
+ LL_ADC_REG_SEQ_DISCONT_DISABLE
+ | ADC_INJ_InitStruct->TrigAuto
+ );
+ }
+
+ MODIFY_REG(ADCx->JSQR,
+ ADC_JSQR_JEXTSEL
+ | ADC_JSQR_JEXTEN
+ | ADC_JSQR_JL
+ ,
+ ADC_INJ_InitStruct->TriggerSource
+ | ADC_INJ_InitStruct->SequencerLength
+ );
+ }
+ else
+ {
+ /* Initialization error: ADC instance is not disabled. */
+ status = ERROR;
+ }
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
+ * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
+{
+ /* Set ADC_INJ_InitStruct fields to default values */
+ /* Set fields of ADC group injected */
+ ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
+ ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE;
+ ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
+ ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* ADC1 || ADC2 || ADC3 || ADC4 */
+
+
+#endif /* STM32F301x8 || STM32F302x8 || STM32F302xC || STM32F302xE || STM32F303x8 || STM32F303xC || STM32F303xE || STM32F318xx || STM32F328xx || STM32F334x8 || STM32F358xx || STM32F398xx */
+
+#if defined (ADC1_V2_5)
+
+#if defined (ADC1)
+
+/** @addtogroup ADC_LL ADC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/** @addtogroup ADC_LL_Private_Macros
+ * @{
+ */
+
+/* Check of parameters for configuration of ADC hierarchical scope: */
+/* common to several ADC instances. */
+/* Check of parameters for configuration of ADC hierarchical scope: */
+/* ADC instance. */
+#define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
+ ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
+ || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) )
+
+#define IS_LL_ADC_SCAN_SELECTION(__SCAN_SELECTION__) \
+ ( ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_DISABLE) \
+ || ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_ENABLE) )
+
+#define IS_LL_ADC_SEQ_SCAN_MODE(__SEQ_SCAN_MODE__) \
+ ( ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_DISABLE) \
+ || ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_ENABLE) )
+
+/* Check of parameters for configuration of ADC hierarchical scope: */
+/* ADC group regular */
+#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
+ ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM19_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM19_CH3) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM19_CH4) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11))
+
+#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
+ ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
+ || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS))
+
+#define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
+ ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
+ || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED))
+
+#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
+ ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS))
+
+#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
+ ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) )
+
+/* Check of parameters for configuration of ADC hierarchical scope: */
+/* ADC group injected */
+#define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
+ ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM19_CH1) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM19_CH2) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15))
+
+#define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
+ ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
+ || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR))
+
+#define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
+ ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
+ || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
+ || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
+ || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS))
+
+#define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
+ ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
+ || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) )
+
+/**
+ * @}
+ */
+
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADC_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup ADC_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize registers of all ADC instances belonging to
+ * the same ADC common instance to their default reset values.
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC common registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
+
+ /* Force reset of ADC clock (core clock) */
+ LL_APB2_GRP1_ForceReset (LL_APB2_GRP1_PERIPH_ADC1);
+
+ /* Release reset of ADC clock (core clock) */
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC1);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief De-initialize registers of the selected ADC instance
+ * to their default reset values.
+ * @note To reset all ADC instances quickly (perform a hard reset),
+ * use function @ref LL_ADC_CommonDeInit().
+ * @param ADCx ADC instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC registers are de-initialized
+ * - ERROR: ADC registers are not de-initialized
+ */
+ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+
+ /* Disable ADC instance if not already disabled. */
+ if(LL_ADC_IsEnabled(ADCx) == 1U)
+ {
+ /* Set ADC group regular trigger source to SW start to ensure to not */
+ /* have an external trigger event occurring during the conversion stop */
+ /* ADC disable process. */
+ LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
+
+ /* Set ADC group injected trigger source to SW start to ensure to not */
+ /* have an external trigger event occurring during the conversion stop */
+ /* ADC disable process. */
+ LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
+
+ /* Disable the ADC instance */
+ LL_ADC_Disable(ADCx);
+ }
+
+ /* Check whether ADC state is compliant with expected state */
+ /* (hardware requirements of bits state to reset registers below) */
+ if(READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0U)
+ {
+ /* ========== Reset ADC registers ========== */
+ /* Reset register SR */
+ CLEAR_BIT(ADCx->SR,
+ ( LL_ADC_FLAG_STRT
+ | LL_ADC_FLAG_JSTRT
+ | LL_ADC_FLAG_EOS
+ | LL_ADC_FLAG_JEOS
+ | LL_ADC_FLAG_AWD1 )
+ );
+
+ /* Reset register CR1 */
+ CLEAR_BIT(ADCx->CR1,
+ ( ADC_CR1_AWDEN | ADC_CR1_JAWDEN
+ | ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN
+ | ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN
+ | ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE
+ | ADC_CR1_AWDCH )
+ );
+
+ /* Reset register CR2 */
+ CLEAR_BIT(ADCx->CR2,
+ ( ADC_CR2_TSVREFE
+ | ADC_CR2_SWSTART | ADC_CR2_EXTTRIG | ADC_CR2_EXTSEL
+ | ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL
+ | ADC_CR2_ALIGN | ADC_CR2_DMA
+ | ADC_CR2_RSTCAL | ADC_CR2_CAL
+ | ADC_CR2_CONT | ADC_CR2_ADON )
+ );
+
+ /* Reset register SMPR1 */
+ CLEAR_BIT(ADCx->SMPR1,
+ ( ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16
+ | ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13
+ | ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10)
+ );
+
+ /* Reset register SMPR2 */
+ CLEAR_BIT(ADCx->SMPR2,
+ ( ADC_SMPR2_SMP9
+ | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 | ADC_SMPR2_SMP6
+ | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | ADC_SMPR2_SMP3
+ | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | ADC_SMPR2_SMP0)
+ );
+
+ /* Reset register JOFR1 */
+ CLEAR_BIT(ADCx->JOFR1, ADC_JOFR1_JOFFSET1);
+ /* Reset register JOFR2 */
+ CLEAR_BIT(ADCx->JOFR2, ADC_JOFR2_JOFFSET2);
+ /* Reset register JOFR3 */
+ CLEAR_BIT(ADCx->JOFR3, ADC_JOFR3_JOFFSET3);
+ /* Reset register JOFR4 */
+ CLEAR_BIT(ADCx->JOFR4, ADC_JOFR4_JOFFSET4);
+
+ /* Reset register HTR */
+ SET_BIT(ADCx->HTR, ADC_HTR_HT);
+ /* Reset register LTR */
+ CLEAR_BIT(ADCx->LTR, ADC_LTR_LT);
+
+ /* Reset register SQR1 */
+ CLEAR_BIT(ADCx->SQR1,
+ ( ADC_SQR1_L
+ | ADC_SQR1_SQ16
+ | ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13)
+ );
+
+ /* Reset register SQR2 */
+ CLEAR_BIT(ADCx->SQR2,
+ ( ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10
+ | ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7)
+ );
+
+
+ /* Reset register JSQR */
+ CLEAR_BIT(ADCx->JSQR,
+ ( ADC_JSQR_JL
+ | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3
+ | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 )
+ );
+
+ /* Reset register DR */
+ /* bits in access mode read only, no direct reset applicable */
+
+ /* Reset registers JDR1, JDR2, JDR3, JDR4 */
+ /* bits in access mode read only, no direct reset applicable */
+
+ }
+
+ return status;
+}
+
+/**
+ * @brief Initialize some features of ADC instance.
+ * @note These parameters have an impact on ADC scope: ADC instance.
+ * Affects both group regular and group injected (availability
+ * of ADC group injected depends on STM32 families).
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Instance .
+ * @note The setting of these parameters by function @ref LL_ADC_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 families. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ * @note After using this function, some other features must be configured
+ * using LL unitary functions.
+ * The minimum configuration remaining to be done is:
+ * - Set ADC group regular or group injected sequencer:
+ * map channel on the selected sequencer rank.
+ * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
+ * - Set ADC channel sampling time
+ * Refer to function LL_ADC_SetChannelSamplingTime();
+ * @param ADCx ADC instance
+ * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC registers are initialized
+ * - ERROR: ADC registers are not initialized
+ */
+ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+
+ assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
+ assert_param(IS_LL_ADC_SCAN_SELECTION(ADC_InitStruct->SequencersScanMode));
+
+ /* Note: Hardware constraint (refer to description of this function): */
+ /* ADC instance must be disabled. */
+ if(LL_ADC_IsEnabled(ADCx) == 0U)
+ {
+ /* Configuration of ADC hierarchical scope: */
+ /* - ADC instance */
+ /* - Set ADC conversion data alignment */
+ MODIFY_REG(ADCx->CR1,
+ ADC_CR1_SCAN
+ ,
+ ADC_InitStruct->SequencersScanMode
+ );
+
+ MODIFY_REG(ADCx->CR2,
+ ADC_CR2_ALIGN
+ ,
+ ADC_InitStruct->DataAlignment
+ );
+
+ }
+ else
+ {
+ /* Initialization error: ADC instance is not disabled. */
+ status = ERROR;
+ }
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
+ * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
+{
+ /* Set ADC_InitStruct fields to default values */
+ /* Set fields of ADC instance */
+ ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
+
+ /* Enable scan mode to have a generic behavior with ADC of other */
+ /* STM32 families, without this setting available: */
+ /* ADC group regular sequencer and ADC group injected sequencer depend */
+ /* only of their own configuration. */
+ ADC_InitStruct->SequencersScanMode = LL_ADC_SEQ_SCAN_ENABLE;
+
+}
+
+/**
+ * @brief Initialize some features of ADC group regular.
+ * @note These parameters have an impact on ADC scope: ADC group regular.
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+ * (functions with prefix "REG").
+ * @note The setting of these parameters by function @ref LL_ADC_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 families. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ * @note After using this function, other features must be configured
+ * using LL unitary functions.
+ * The minimum configuration remaining to be done is:
+ * - Set ADC group regular or group injected sequencer:
+ * map channel on the selected sequencer rank.
+ * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
+ * - Set ADC channel sampling time
+ * Refer to function LL_ADC_SetChannelSamplingTime();
+ * @param ADCx ADC instance
+ * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC registers are initialized
+ * - ERROR: ADC registers are not initialized
+ */
+ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+ assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
+ assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
+ if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
+ {
+ assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
+ }
+ assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
+ assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
+
+ /* Note: Hardware constraint (refer to description of this function): */
+ /* ADC instance must be disabled. */
+ if(LL_ADC_IsEnabled(ADCx) == 0U)
+ {
+ /* Configuration of ADC hierarchical scope: */
+ /* - ADC group regular */
+ /* - Set ADC group regular trigger source */
+ /* - Set ADC group regular sequencer length */
+ /* - Set ADC group regular sequencer discontinuous mode */
+ /* - Set ADC group regular continuous mode */
+ /* - Set ADC group regular conversion data transfer: no transfer or */
+ /* transfer by DMA, and DMA requests mode */
+ /* Note: On this STM32 serie, ADC trigger edge is set when starting */
+ /* ADC conversion. */
+ /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
+ if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
+ {
+ MODIFY_REG(ADCx->CR1,
+ ADC_CR1_DISCEN
+ | ADC_CR1_DISCNUM
+ ,
+ ADC_REG_InitStruct->SequencerLength
+ | ADC_REG_InitStruct->SequencerDiscont
+ );
+ }
+ else
+ {
+ MODIFY_REG(ADCx->CR1,
+ ADC_CR1_DISCEN
+ | ADC_CR1_DISCNUM
+ ,
+ ADC_REG_InitStruct->SequencerLength
+ | LL_ADC_REG_SEQ_DISCONT_DISABLE
+ );
+ }
+
+ MODIFY_REG(ADCx->CR2,
+ ADC_CR2_EXTSEL
+ | ADC_CR2_CONT
+ | ADC_CR2_DMA
+ ,
+ ADC_REG_InitStruct->TriggerSource
+ | ADC_REG_InitStruct->ContinuousMode
+ | ADC_REG_InitStruct->DMATransfer
+ );
+
+ /* Set ADC group regular sequencer length and scan direction */
+ /* Note: Hardware constraint (refer to description of this function): */
+ /* Note: If ADC instance feature scan mode is disabled */
+ /* (refer to ADC instance initialization structure */
+ /* parameter @ref SequencersScanMode */
+ /* or function @ref LL_ADC_SetSequencersScanMode() ), */
+ /* this parameter is discarded. */
+ LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
+ }
+ else
+ {
+ /* Initialization error: ADC instance is not disabled. */
+ status = ERROR;
+ }
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
+ * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
+{
+ /* Set ADC_REG_InitStruct fields to default values */
+ /* Set fields of ADC group regular */
+ /* Note: On this STM32 serie, ADC trigger edge is set when starting */
+ /* ADC conversion. */
+ /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
+ ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
+ ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
+ ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
+ ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
+ ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
+}
+
+/**
+ * @brief Initialize some features of ADC group injected.
+ * @note These parameters have an impact on ADC scope: ADC group injected.
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+ * (functions with prefix "INJ").
+ * @note The setting of these parameters by function @ref LL_ADC_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 families. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ * @note After using this function, other features must be configured
+ * using LL unitary functions.
+ * The minimum configuration remaining to be done is:
+ * - Set ADC group injected sequencer:
+ * map channel on the selected sequencer rank.
+ * Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
+ * - Set ADC channel sampling time
+ * Refer to function LL_ADC_SetChannelSamplingTime();
+ * @param ADCx ADC instance
+ * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC registers are initialized
+ * - ERROR: ADC registers are not initialized
+ */
+ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+ assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource));
+ assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
+ if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
+ {
+ assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
+ }
+ assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
+
+ /* Note: Hardware constraint (refer to description of this function): */
+ /* ADC instance must be disabled. */
+ if(LL_ADC_IsEnabled(ADCx) == 0U)
+ {
+ /* Configuration of ADC hierarchical scope: */
+ /* - ADC group injected */
+ /* - Set ADC group injected trigger source */
+ /* - Set ADC group injected sequencer length */
+ /* - Set ADC group injected sequencer discontinuous mode */
+ /* - Set ADC group injected conversion trigger: independent or */
+ /* from ADC group regular */
+ /* Note: On this STM32 serie, ADC trigger edge is set when starting */
+ /* ADC conversion. */
+ /* Refer to function @ref LL_ADC_INJ_StartConversionExtTrig(). */
+ if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
+ {
+ MODIFY_REG(ADCx->CR1,
+ ADC_CR1_JDISCEN
+ | ADC_CR1_JAUTO
+ ,
+ ADC_INJ_InitStruct->SequencerDiscont
+ | ADC_INJ_InitStruct->TrigAuto
+ );
+ }
+ else
+ {
+ MODIFY_REG(ADCx->CR1,
+ ADC_CR1_JDISCEN
+ | ADC_CR1_JAUTO
+ ,
+ LL_ADC_REG_SEQ_DISCONT_DISABLE
+ | ADC_INJ_InitStruct->TrigAuto
+ );
+ }
+
+ MODIFY_REG(ADCx->CR2,
+ ADC_CR2_JEXTSEL
+ ,
+ ADC_INJ_InitStruct->TriggerSource
+ );
+
+ /* Note: Hardware constraint (refer to description of this function): */
+ /* Note: If ADC instance feature scan mode is disabled */
+ /* (refer to ADC instance initialization structure */
+ /* parameter @ref SequencersScanMode */
+ /* or function @ref LL_ADC_SetSequencersScanMode() ), */
+ /* this parameter is discarded. */
+ LL_ADC_INJ_SetSequencerLength(ADCx, ADC_INJ_InitStruct->SequencerLength);
+ }
+ else
+ {
+ /* Initialization error: ADC instance is not disabled. */
+ status = ERROR;
+ }
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
+ * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
+{
+ /* Set ADC_INJ_InitStruct fields to default values */
+ /* Set fields of ADC group injected */
+ ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
+ ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE;
+ ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
+ ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* ADC1 */
+
+
+#endif /* STM32F373xC || STM32F378xx */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_ll_comp.c b/Src/stm32f3xx_ll_comp.c
new file mode 100644
index 0000000..98b7ffd
--- /dev/null
+++ b/Src/stm32f3xx_ll_comp.c
@@ -0,0 +1,1051 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_comp.c
+ * @author MCD Application Team
+ * @brief COMP LL module driver
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_ll_comp.h"
+
+#ifdef USE_FULL_ASSERT
+ #include "stm32_assert.h"
+#else
+ #define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+/* Note: Devices of STM32F3 serie embed 1 out of 2 different comparator IP. */
+/* - STM32F30x, STM32F31x, STM32F32x, STM32F33x, STM32F35x, STM32F39x: */
+/* COMP IP from 3 to 7 instances and other specific features */
+/* (comparator output blanking, ...) (refer to reference manual). */
+/* - STM32F37x: */
+/* COMP IP with 2 instances */
+/* This file contains the drivers of these COMP IP, located in 2 area */
+/* delimited by compilation switches. */
+
+#if defined(COMP_V1_3_0_0)
+
+#if defined (COMP1) || defined (COMP2) || defined (COMP3) || defined (COMP4) || defined (COMP5) || defined (COMP6) || defined (COMP7)
+
+/** @addtogroup COMP_LL COMP
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/** @addtogroup COMP_LL_Private_Macros
+ * @{
+ */
+
+/* Check of parameters for configuration of COMP hierarchical scope: */
+/* COMP instance. */
+
+#if defined(COMP_CSR_COMPxMODE)
+#define IS_LL_COMP_POWER_MODE(__POWER_MODE__) \
+ ( ((__POWER_MODE__) == LL_COMP_POWERMODE_HIGHSPEED) \
+ || ((__POWER_MODE__) == LL_COMP_POWERMODE_MEDIUMSPEED) \
+ || ((__POWER_MODE__) == LL_COMP_POWERMODE_LOWPOWER) \
+ || ((__POWER_MODE__) == LL_COMP_POWERMODE_ULTRALOWPOWER) \
+ )
+#else
+#define IS_LL_COMP_POWER_MODE(__POWER_MODE__) \
+ ((__POWER_MODE__) == LL_COMP_POWERMODE_HIGHSPEED)
+#endif
+
+/* Note: On this STM32 serie, comparator input plus parameters are */
+/* the same on all COMP instances. */
+/* However, comparator instance kept as macro parameter for */
+/* compatibility with other STM32 families. */
+#if defined(COMP_CSR_COMPxNONINSEL) && defined(LL_COMP_INPUT_PLUS_DAC1_CH1_COMP1)
+/* Note: On devices where bit COMP_CSR_COMPxNONINSEL is available, */
+/* feature LL_COMP_INPUT_PLUS_DAC1_CH1_COMP1 is also available. */
+#define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) \
+ ( ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1) \
+ || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2) \
+ || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_DAC1_CH1_COMP1) \
+ )
+#elif defined(COMP_CSR_COMPxNONINSEL) && defined(LL_COMP_INPUT_PLUS_DAC1_CH1_COMP2)
+/* Note: On devices where bit COMP_CSR_COMPxNONINSEL is available, */
+/* feature LL_COMP_INPUT_PLUS_DAC1_CH1_COMP1 is also available. */
+#define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) \
+ ( ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1) \
+ || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2) \
+ || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_DAC1_CH1_COMP2) \
+ )
+#elif defined(COMP_CSR_COMPxNONINSEL)
+#define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) \
+ ( ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1) \
+ || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2) \
+ )
+#elif defined(LL_COMP_INPUT_PLUS_DAC1_CH1_COMP2)
+/* Note: On devices where bit COMP_CSR_COMPxNONINSEL is available, */
+/* feature LL_COMP_INPUT_PLUS_DAC1_CH1_COMP1 is also available. */
+#define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) \
+ ( ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1) \
+ || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_DAC1_CH1_COMP2) \
+ )
+#else
+/* Note: Device without comparator input plus configurable: corresponds to */
+/* setting "LL_COMP_INPUT_PLUS_IO1" or "LL_COMP_INPUT_PLUS_IO2" */
+/* compared to other STM32F3 devices, depending on comparator instance */
+/* (refer to reference manual). */
+#define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) \
+ ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1)
+#endif
+
+#if defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F303xE) || defined(STM32F398xx)
+#define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \
+ ( ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO3) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO4) \
+ )
+#elif defined(STM32F303x8) || defined(STM32F328xx) || defined(STM32F334x8)
+#define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \
+ ( ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO4) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC2_CH1) \
+ )
+#elif defined(STM32F302xC) || defined(STM32F302xE)
+#define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \
+ ( ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO3) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO4) \
+ )
+#else /* STM32F301x8 || STM32F318xx || STM32F302x8 */
+#define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \
+ ( ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO4) \
+ )
+#endif
+
+#if defined(COMP_CSR_COMPxHYST)
+#define IS_LL_COMP_INPUT_HYSTERESIS(__INPUT_HYSTERESIS__) \
+ ( ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_NONE) \
+ || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_LOW) \
+ || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_MEDIUM) \
+ || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_HIGH) \
+ )
+#else
+#define IS_LL_COMP_INPUT_HYSTERESIS(__INPUT_HYSTERESIS__) \
+ ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_NONE)
+#endif
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define IS_LL_COMP_OUTPUT_SELECTION(__COMP_INSTANCE__, __OUTPUT_SELECTION__) \
+ (( ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_NONE) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_BKIN) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_BKIN2) \
+ ) \
+ ? ( \
+ (1U) \
+ ) \
+ : \
+ (((__COMP_INSTANCE__) == COMP2) \
+ ? ( \
+ ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_IC1_COMP2) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC4_COMP2) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_OCCLR_COMP2) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP2) \
+ ) \
+ : \
+ (((__COMP_INSTANCE__) == COMP4) \
+ ? ( \
+ ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_IC2_COMP4) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_OCCLR_COMP4) \
+ ) \
+ : \
+ ( \
+ ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC2_COMP6) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP6) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_IC1_COMP6) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_OCCLR_COMP6) \
+ ) \
+ ) \
+ ) \
+ )
+#elif defined(STM32F303x8) || defined(STM32F328xx) || defined(STM32F334x8)
+#define IS_LL_COMP_OUTPUT_SELECTION(__COMP_INSTANCE__, __OUTPUT_SELECTION__) \
+ (( ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_NONE) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_BKIN) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_BKIN2) \
+ ) \
+ ? ( \
+ (1U) \
+ ) \
+ : \
+ (((__COMP_INSTANCE__) == COMP2) \
+ ? ( \
+ ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP2_4) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_IC1_COMP2) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC4_COMP2) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_OCCLR_COMP2) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP2) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC1_COMP2) \
+ ) \
+ : \
+ (((__COMP_INSTANCE__) == COMP4) \
+ ? ( \
+ ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP2_4)\
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC3_COMP4) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_IC2_COMP4) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_OCCLR_COMP4) \
+ ) \
+ : \
+ ( \
+ ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC2_COMP6) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP6) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_IC1_COMP6) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_OCCLR_COMP6) \
+ ) \
+ ) \
+ ) \
+ )
+#elif defined(STM32F302xC) || defined(STM32F302xE)
+#define IS_LL_COMP_OUTPUT_SELECTION(__COMP_INSTANCE__, __OUTPUT_SELECTION__) \
+ (( ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_NONE) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_BKIN) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_BKIN2) \
+ ) \
+ ? ( \
+ (1U) \
+ ) \
+ : \
+ ((((__COMP_INSTANCE__) == COMP1) || ((__COMP_INSTANCE__) == COMP2)) \
+ ? ( \
+ ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_IC1_COMP1_2) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC4_COMP1_2) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC1_COMP1_2) \
+ ) \
+ : \
+ (((__COMP_INSTANCE__) == COMP4) \
+ ? ( \
+ ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC3_COMP4) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_IC2_COMP4) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_IC2_COMP4) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_OCCLR_COMP4) \
+ ) \
+ : \
+ ( \
+ ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC2_COMP6) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP6) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_IC4_COMP6) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_IC1_COMP6) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_OCCLR_COMP6) \
+ ) \
+ ) \
+ ) \
+ )
+#elif defined(STM32F303xC) || defined(STM32F358xx)
+#define IS_LL_COMP_OUTPUT_SELECTION(__COMP_INSTANCE__, __OUTPUT_SELECTION__) \
+ (( ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_NONE) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_BKIN) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_BKIN2) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_TIM8_BKIN2) \
+ ) \
+ ? ( \
+ (1U) \
+ ) \
+ : \
+ ((((__COMP_INSTANCE__) == COMP1) || ((__COMP_INSTANCE__) == COMP2)) \
+ ? ( \
+ ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2_3_7) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4_5) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_IC1_COMP1_2) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC4_COMP1_2) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC1_COMP1_2) \
+ ) \
+ : \
+ (((__COMP_INSTANCE__) == COMP3) \
+ ? ( \
+ ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2_3_7) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC2_COMP3) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_IC1_COMP3) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_IC1_COMP3) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_BKIN) \
+ ) \
+ : \
+ (((__COMP_INSTANCE__) == COMP4) \
+ ? ( \
+ ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4_5) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC3_COMP4) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_IC2_COMP4) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_IC2_COMP4) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_OCCLR_COMP4) \
+ ) \
+ : \
+ (((__COMP_INSTANCE__) == COMP5) \
+ ? ( \
+ ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4_5) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM8_OCCLR_COMP4_5_6_7) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC1_COMP5) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_IC3_COMP5) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM17_IC1_COMP5) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_BKIN) \
+ ) \
+ : \
+ (((__COMP_INSTANCE__) == COMP6) \
+ ? ( \
+ ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM8_OCCLR_COMP4_5_6_7) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC2_COMP6) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP6) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_IC4_COMP6) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_IC1_COMP6) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_OCCLR_COMP6) \
+ ) \
+ : \
+ ( \
+ ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2_3_7) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM8_OCCLR_COMP4_5_6_7) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_IC2_COMP7) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC3_COMP7) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM17_OCCLR_COMP7) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM17_BKIN) \
+ ) \
+ ) \
+ ) \
+ ) \
+ ) \
+ ) \
+ )
+#elif defined(STM32F303xE) || defined(STM32F398xx)
+#define IS_LL_COMP_OUTPUT_SELECTION(__COMP_INSTANCE__, __OUTPUT_SELECTION__) \
+ (( ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_NONE) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_BKIN) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_BKIN2) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_TIM8_BKIN2) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM20_BKIN) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM20_BKIN2) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_TIM8_TIM20_BKIN2) \
+ ) \
+ ? ( \
+ (1U) \
+ ) \
+ : \
+ ((((__COMP_INSTANCE__) == COMP1) || ((__COMP_INSTANCE__) == COMP2)) \
+ ? ( \
+ ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2_3_7) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4_5) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_IC1_COMP1_2) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC4_COMP1_2) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC1_COMP1_2) \
+ || (((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM20_OCCLR_COMP2) \
+ && ((__COMP_INSTANCE__) == COMP2) ) \
+ ) \
+ : \
+ (((__COMP_INSTANCE__) == COMP3) \
+ ? ( \
+ ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2_3_7) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC2_COMP3) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_IC1_COMP3) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_IC1_COMP3) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_BKIN) \
+ ) \
+ : \
+ (((__COMP_INSTANCE__) == COMP4) \
+ ? ( \
+ ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4_5) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC3_COMP4) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_IC2_COMP4) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_IC2_COMP4) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_OCCLR_COMP4) \
+ ) \
+ : \
+ (((__COMP_INSTANCE__) == COMP5) \
+ ? ( \
+ ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4_5) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM8_OCCLR_COMP4_5_6_7) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC1_COMP5) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_IC3_COMP5) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM17_IC1_COMP5) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_BKIN) \
+ ) \
+ : \
+ (((__COMP_INSTANCE__) == COMP6) \
+ ? ( \
+ ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM8_OCCLR_COMP4_5_6_7) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC2_COMP6) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP6) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_IC4_COMP6) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_IC1_COMP6) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_OCCLR_COMP6) \
+ ) \
+ : \
+ ( \
+ ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2_3_7) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM8_OCCLR_COMP4_5_6_7) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_IC2_COMP7) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC3_COMP7) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM17_OCCLR_COMP7) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM17_BKIN) \
+ ) \
+ ) \
+ ) \
+ ) \
+ ) \
+ ) \
+ )
+#endif
+
+#define IS_LL_COMP_OUTPUT_POLARITY(__POLARITY__) \
+ ( ((__POLARITY__) == LL_COMP_OUTPUTPOL_NONINVERTED) \
+ || ((__POLARITY__) == LL_COMP_OUTPUTPOL_INVERTED) \
+ )
+
+#if defined(COMP_CSR_COMPxBLANKING)
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__COMP_INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \
+ (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) \
+ ? ( \
+ (1U) \
+ ) \
+ : \
+ (((__COMP_INSTANCE__) == COMP2) \
+ ? ( \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2) \
+ ) \
+ : \
+ (((__COMP_INSTANCE__) == COMP4) \
+ ? ( \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4) \
+ ) \
+ : \
+ ( \
+ (((__COMP_INSTANCE__) == COMP6) \
+ ? ( \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6) \
+ ) \
+ : \
+ ( \
+ (0U) \
+ ) \
+ ) \
+ ) \
+ ) \
+ ) \
+ )
+#elif defined(STM32F302xE) || defined(STM32F302xC)
+#define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__COMP_INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \
+ (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) \
+ ? ( \
+ (1U) \
+ ) \
+ : \
+ ((((__COMP_INSTANCE__) == COMP1) || ((__COMP_INSTANCE__) == COMP2)) \
+ ? ( \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1_2) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1_2) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1_2) \
+ ) \
+ : \
+ (((__COMP_INSTANCE__) == COMP4) \
+ ? ( \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4) \
+ ) \
+ : \
+ ( \
+ (((__COMP_INSTANCE__) == COMP6) \
+ ? ( \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6) \
+ ) \
+ : \
+ ( \
+ (0U) \
+ ) \
+ ) \
+ ) \
+ ) \
+ ) \
+ )
+#elif defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
+#define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__COMP_INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \
+ (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) \
+ ? ( \
+ (1U) \
+ ) \
+ : \
+ ((((__COMP_INSTANCE__) == COMP1) || ((__COMP_INSTANCE__) == COMP2)) \
+ ? ( \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1_2_7) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1_2) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1_2) \
+ ) \
+ : \
+ (((__COMP_INSTANCE__) == COMP3) \
+ ? ( \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3_6) \
+ ) \
+ : \
+ (((__COMP_INSTANCE__) == COMP4) \
+ ? ( \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4_5_6_7) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4) \
+ ) \
+ : \
+ (((__COMP_INSTANCE__) == COMP5) \
+ ? ( \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4_5_6_7) \
+ ) \
+ : \
+ (((__COMP_INSTANCE__) == COMP6) \
+ ? ( \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4_5_6_7) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3_6) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6_7) \
+ ) \
+ : \
+ ( \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4_5_6_7) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1_2_7) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6_7) \
+ ) \
+ ) \
+ ) \
+ ) \
+ ) \
+ ) \
+ )
+#endif
+#else
+#define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__COMP_INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE)
+#endif
+/**
+ * @}
+ */
+
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup COMP_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup COMP_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize registers of the selected COMP instance
+ * to their default reset values.
+ * @note If comparator is locked, de-initialization by software is
+ * not possible.
+ * The only way to unlock the comparator is a device hardware reset.
+ * @param COMPx COMP instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: COMP registers are de-initialized
+ * - ERROR: COMP registers are not de-initialized
+ */
+ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_COMP_ALL_INSTANCE(COMPx));
+
+ /* Note: Hardware constraint (refer to description of this function): */
+ /* COMP instance must not be locked. */
+ if (LL_COMP_IsLocked(COMPx) == 0U)
+ {
+ LL_COMP_WriteReg(COMPx, CSR, 0x00000000U);
+ }
+ else
+ {
+ /* Comparator instance is locked: de-initialization by software is */
+ /* not possible. */
+ /* The only way to unlock the comparator is a device hardware reset. */
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Initialize some features of COMP instance.
+ * @note This function configures features of the selected COMP instance.
+ * Some features are also available at scope COMP common instance
+ * (common to several COMP instances).
+ * Refer to functions having argument "COMPxy_COMMON" as parameter.
+ * @param COMPx COMP instance
+ * @param COMP_InitStruct Pointer to a @ref LL_COMP_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: COMP registers are initialized
+ * - ERROR: COMP registers are not initialized
+ */
+ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_COMP_ALL_INSTANCE(COMPx));
+ assert_param(IS_LL_COMP_POWER_MODE(COMP_InitStruct->PowerMode));
+ assert_param(IS_LL_COMP_INPUT_PLUS(COMPx, COMP_InitStruct->InputPlus));
+ assert_param(IS_LL_COMP_INPUT_MINUS(COMPx, COMP_InitStruct->InputMinus));
+ assert_param(IS_LL_COMP_INPUT_HYSTERESIS(COMP_InitStruct->InputHysteresis));
+ assert_param(IS_LL_COMP_OUTPUT_SELECTION(COMPx, COMP_InitStruct->OutputSelection));
+ assert_param(IS_LL_COMP_OUTPUT_POLARITY(COMP_InitStruct->OutputPolarity));
+ assert_param(IS_LL_COMP_OUTPUT_BLANKING_SOURCE(COMPx, COMP_InitStruct->OutputBlankingSource));
+
+ /* Note: Hardware constraint (refer to description of this function) */
+ /* COMP instance must not be locked. */
+ if (LL_COMP_IsLocked(COMPx) == 0U)
+ {
+ /* Configuration of comparator instance : */
+ /* - PowerMode */
+ /* - InputPlus */
+ /* - InputMinus */
+ /* - InputHysteresis */
+ /* - OutputSelection */
+ /* - OutputPolarity */
+ /* - OutputBlankingSource */
+ MODIFY_REG(COMPx->CSR,
+ ((uint32_t)0x00000000U)
+#if defined(COMP_CSR_COMPxMODE)
+ | COMP_CSR_COMPxMODE
+#endif
+#if defined(COMP_CSR_COMPxNONINSEL)
+ | COMP_CSR_COMPxNONINSEL
+#endif
+ | COMP_CSR_COMPxINSEL
+#if defined(COMP_CSR_COMPxHYST)
+ | COMP_CSR_COMPxHYST
+#endif
+ | COMP_CSR_COMPxOUTSEL
+ | COMP_CSR_COMPxPOL
+ | COMP_CSR_COMPxBLANKING
+ ,
+ ((uint32_t)0x00000000U)
+#if defined(COMP_CSR_COMPxMODE)
+ | COMP_InitStruct->PowerMode
+#endif
+#if defined(COMP_CSR_COMPxNONINSEL)
+ | COMP_InitStruct->InputPlus
+#endif
+ | COMP_InitStruct->InputMinus
+#if defined(COMP_CSR_COMPxHYST)
+ | COMP_InitStruct->InputHysteresis
+#endif
+ | COMP_InitStruct->OutputSelection
+ | COMP_InitStruct->OutputPolarity
+ | COMP_InitStruct->OutputBlankingSource
+ );
+
+ }
+ else
+ {
+ /* Initialization error: COMP instance is locked. */
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_COMP_InitTypeDef field to default value.
+ * @param COMP_InitStruct pointer to a @ref LL_COMP_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct)
+{
+ /* Set COMP_InitStruct fields to default values */
+ /* Note: Comparator power mode "high speed" is the only mode */
+ /* available on all STMF3 devices. */
+ COMP_InitStruct->PowerMode = LL_COMP_POWERMODE_HIGHSPEED;
+ COMP_InitStruct->InputPlus = LL_COMP_INPUT_PLUS_IO1;
+ COMP_InitStruct->InputMinus = LL_COMP_INPUT_MINUS_VREFINT;
+ COMP_InitStruct->InputHysteresis = LL_COMP_HYSTERESIS_NONE;
+ COMP_InitStruct->OutputSelection = LL_COMP_OUTPUT_NONE;
+ COMP_InitStruct->OutputPolarity = LL_COMP_OUTPUTPOL_NONINVERTED;
+ COMP_InitStruct->OutputBlankingSource = LL_COMP_BLANKINGSRC_NONE;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* COMP1 || COMP2 || COMP3 || COMP4 || COMP5 || COMP6 || COMP7 */
+
+
+#endif /* STM32F301x8 || STM32F302x8 || STM32F302xC || STM32F302xE || STM32F303x8 || STM32F303xC || STM32F303xE || STM32F318xx || STM32F328xx || STM32F334x8 || STM32F358xx || STM32F398xx */
+
+#if defined (COMP_V1_1_0_0)
+
+#if defined (COMP1) || defined (COMP2)
+
+/** @addtogroup COMP_LL COMP
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/** @addtogroup COMP_LL_Private_Macros
+ * @{
+ */
+
+/* Check of parameters for configuration of COMP hierarchical scope: */
+/* COMP instance. */
+
+#define IS_LL_COMP_POWER_MODE(__POWER_MODE__) \
+ ( ((__POWER_MODE__) == LL_COMP_POWERMODE_HIGHSPEED) \
+ || ((__POWER_MODE__) == LL_COMP_POWERMODE_MEDIUMSPEED) \
+ || ((__POWER_MODE__) == LL_COMP_POWERMODE_LOWPOWER) \
+ || ((__POWER_MODE__) == LL_COMP_POWERMODE_ULTRALOWPOWER) \
+ )
+
+/* Note: On this STM32 serie, comparator input plus parameters are */
+/* the different depending on COMP instances. */
+#define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) \
+ (((__COMP_INSTANCE__) == COMP1) \
+ ? ( \
+ ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1) \
+ || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_DAC1_CH1) \
+ ) \
+ : \
+ ( \
+ ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1) \
+ ) \
+ )
+
+/* Note: On this STM32 serie, comparator input minus parameters are */
+/* the same on all COMP instances. */
+/* However, comparator instance kept as macro parameter for */
+/* compatibility with other STM32 families. */
+#define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \
+ ( ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO3) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO4) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC2_CH1) \
+ )
+
+#define IS_LL_COMP_INPUT_HYSTERESIS(__INPUT_HYSTERESIS__) \
+ ( ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_NONE) \
+ || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_LOW) \
+ || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_MEDIUM) \
+ || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_HIGH) \
+ )
+
+/* Note: Output redirection is specific to COMP instances but is checked */
+/* with literals of instance COMP2 (no differentiation possible since */
+/* literals of COMP1 and COMP2 share the same values range). */
+#define IS_LL_COMP_OUTPUT_SELECTION(__OUTPUT_SELECTION__) \
+ ( ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_NONE) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_BKIN) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_IC1) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_OCCLR) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC4) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC1_COMP2) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP2) \
+ )
+
+#define IS_LL_COMP_OUTPUT_POLARITY(__POLARITY__) \
+ ( ((__POLARITY__) == LL_COMP_OUTPUTPOL_NONINVERTED) \
+ || ((__POLARITY__) == LL_COMP_OUTPUTPOL_INVERTED) \
+ )
+
+/**
+ * @}
+ */
+
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup COMP_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup COMP_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize registers of the selected COMP instance
+ * to their default reset values.
+ * @note If comparator is locked, de-initialization by software is
+ * not possible.
+ * The only way to unlock the comparator is a device hardware reset.
+ * @param COMPx COMP instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: COMP registers are de-initialized
+ * - ERROR: COMP registers are not de-initialized
+ */
+ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_COMP_ALL_INSTANCE(COMPx));
+
+ /* Note: Hardware constraint (refer to description of this function): */
+ /* COMP instance must not be locked. */
+ if (LL_COMP_IsLocked(COMPx) == 0U)
+ {
+ /* Note: Connection switch is applicable only to COMP instance COMP1, */
+ /* therefore is COMP2 is selected the equivalent bit is */
+ /* kept unmodified. */
+ if (COMPx == COMP1)
+ {
+ CLEAR_BIT(COMP->CSR,
+ ( COMP_CSR_COMP1MODE
+ | COMP_CSR_COMP1INSEL
+ | COMP_CSR_COMP1SW1
+ | COMP_CSR_COMP1OUTSEL
+ | COMP_CSR_COMP1HYST
+ | COMP_CSR_COMP1POL
+ | COMP_CSR_COMP1EN
+ ) << __COMP_BITOFFSET_INSTANCE(COMPx)
+ );
+ }
+ else
+ {
+ CLEAR_BIT(COMP->CSR,
+ ( COMP_CSR_COMP1MODE
+ | COMP_CSR_COMP1INSEL
+ | COMP_CSR_COMP1OUTSEL
+ | COMP_CSR_COMP1HYST
+ | COMP_CSR_COMP1POL
+ | COMP_CSR_COMP1EN
+ ) << __COMP_BITOFFSET_INSTANCE(COMPx)
+ );
+ }
+
+ }
+ else
+ {
+ /* Comparator instance is locked: de-initialization by software is */
+ /* not possible. */
+ /* The only way to unlock the comparator is a device hardware reset. */
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Initialize some features of COMP instance.
+ * @note This function configures features of the selected COMP instance.
+ * Some features are also available at scope COMP common instance
+ * (common to several COMP instances).
+ * Refer to functions having argument "COMPxy_COMMON" as parameter.
+ * @param COMPx COMP instance
+ * @param COMP_InitStruct Pointer to a @ref LL_COMP_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: COMP registers are initialized
+ * - ERROR: COMP registers are not initialized
+ */
+ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_COMP_ALL_INSTANCE(COMPx));
+ assert_param(IS_LL_COMP_POWER_MODE(COMP_InitStruct->PowerMode));
+ assert_param(IS_LL_COMP_INPUT_PLUS(COMPx, COMP_InitStruct->InputPlus));
+ assert_param(IS_LL_COMP_INPUT_MINUS(COMPx, COMP_InitStruct->InputMinus));
+ assert_param(IS_LL_COMP_INPUT_HYSTERESIS(COMP_InitStruct->InputHysteresis));
+ assert_param(IS_LL_COMP_OUTPUT_SELECTION(COMP_InitStruct->OutputSelection));
+ assert_param(IS_LL_COMP_OUTPUT_POLARITY(COMP_InitStruct->OutputPolarity));
+
+ /* Note: Hardware constraint (refer to description of this function) */
+ /* COMP instance must not be locked. */
+ if (LL_COMP_IsLocked(COMPx) == 0U)
+ {
+ /* Configuration of comparator instance : */
+ /* - PowerMode */
+ /* - InputPlus */
+ /* - InputMinus */
+ /* - InputHysteresis */
+ /* - OutputSelection */
+ /* - OutputPolarity */
+ /* Note: Connection switch is applicable only to COMP instance COMP1, */
+ /* therefore is COMP2 is selected the equivalent bit is */
+ /* kept unmodified. */
+ if (COMPx == COMP1)
+ {
+ MODIFY_REG(COMP->CSR,
+ ( COMP_CSR_COMP1MODE
+ | COMP_CSR_COMP1INSEL
+ | COMP_CSR_COMP1SW1
+ | COMP_CSR_COMP1OUTSEL
+ | COMP_CSR_COMP1HYST
+ | COMP_CSR_COMP1POL
+ ) << __COMP_BITOFFSET_INSTANCE(COMPx)
+ ,
+ ( COMP_InitStruct->PowerMode
+ | COMP_InitStruct->InputPlus
+ | COMP_InitStruct->InputMinus
+ | COMP_InitStruct->InputHysteresis
+ | COMP_InitStruct->OutputSelection
+ | COMP_InitStruct->OutputPolarity
+ ) << __COMP_BITOFFSET_INSTANCE(COMPx)
+ );
+ }
+ else
+ {
+ MODIFY_REG(COMP->CSR,
+ ( COMP_CSR_COMP1MODE
+ | COMP_CSR_COMP1INSEL
+ | COMP_CSR_COMP1OUTSEL
+ | COMP_CSR_COMP1HYST
+ | COMP_CSR_COMP1POL
+ ) << __COMP_BITOFFSET_INSTANCE(COMPx)
+ ,
+ ( COMP_InitStruct->PowerMode
+ | COMP_InitStruct->InputPlus
+ | COMP_InitStruct->InputMinus
+ | COMP_InitStruct->InputHysteresis
+ | COMP_InitStruct->OutputSelection
+ | COMP_InitStruct->OutputPolarity
+ ) << __COMP_BITOFFSET_INSTANCE(COMPx)
+ );
+ }
+
+ }
+ else
+ {
+ /* Initialization error: COMP instance is locked. */
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_COMP_InitTypeDef field to default value.
+ * @param COMP_InitStruct pointer to a @ref LL_COMP_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct)
+{
+ /* Set COMP_InitStruct fields to default values */
+ COMP_InitStruct->PowerMode = LL_COMP_POWERMODE_ULTRALOWPOWER;
+ COMP_InitStruct->InputPlus = LL_COMP_INPUT_PLUS_IO1;
+ COMP_InitStruct->InputMinus = LL_COMP_INPUT_MINUS_VREFINT;
+ COMP_InitStruct->InputHysteresis = LL_COMP_HYSTERESIS_NONE;
+ COMP_InitStruct->OutputSelection = LL_COMP_OUTPUT_NONE;
+ COMP_InitStruct->OutputPolarity = LL_COMP_OUTPUTPOL_NONINVERTED;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* COMP1 || COMP2 */
+
+
+#endif /* STM32F373xC || STM32F378xx */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_ll_crc.c b/Src/stm32f3xx_ll_crc.c
new file mode 100644
index 0000000..82b7925
--- /dev/null
+++ b/Src/stm32f3xx_ll_crc.c
@@ -0,0 +1,135 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_crc.c
+ * @author MCD Application Team
+ * @brief CRC LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_ll_crc.h"
+
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined (CRC)
+
+/** @addtogroup CRC_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CRC_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup CRC_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize CRC registers (Registers restored to their default values).
+ * @param CRCx CRC Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: CRC registers are de-initialized
+ * - ERROR: CRC registers are not de-initialized
+ */
+ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_CRC_ALL_INSTANCE(CRCx));
+
+ if (CRCx == CRC)
+ {
+ /* Set programmable polynomial size in CR register to reset value (32 bits)*/
+ LL_CRC_SetPolynomialSize(CRCx, LL_CRC_POLYLENGTH_32B);
+
+ /* Set programmable polynomial in POL register to reset value */
+ LL_CRC_SetPolynomialCoef(CRCx, LL_CRC_DEFAULT_CRC32_POLY);
+
+ /* Set INIT register to reset value */
+ LL_CRC_SetInitialData(CRCx, LL_CRC_DEFAULT_CRC_INITVALUE);
+
+ /* Set Reversibility options on I/O data values in CR register to reset value */
+ LL_CRC_SetInputDataReverseMode(CRCx, LL_CRC_INDATA_REVERSE_NONE);
+ LL_CRC_SetOutputDataReverseMode(CRCx, LL_CRC_OUTDATA_REVERSE_NONE);
+
+ /* Reset the CRC calculation unit */
+ LL_CRC_ResetCRCCalculationUnit(CRCx);
+
+ /* Reset IDR register */
+ LL_CRC_Write_IDR(CRCx, 0x00U);
+ }
+ else
+ {
+ status = ERROR;
+ }
+
+ return (status);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (CRC) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Src/stm32f3xx_ll_dac.c b/Src/stm32f3xx_ll_dac.c
new file mode 100644
index 0000000..6a5f393
--- /dev/null
+++ b/Src/stm32f3xx_ll_dac.c
@@ -0,0 +1,352 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_dac.c
+ * @author MCD Application Team
+ * @brief DAC LL module driver
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_ll_dac.h"
+#include "stm32f3xx_ll_bus.h"
+
+#ifdef USE_FULL_ASSERT
+ #include "stm32_assert.h"
+#else
+ #define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined (DAC1) || defined (DAC2)
+
+/** @addtogroup DAC_LL DAC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/** @addtogroup DAC_LL_Private_Macros
+ * @{
+ */
+
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__) \
+ ( \
+ ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \
+ || ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2) \
+ )
+#else
+#define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__) \
+ ( \
+ ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \
+ )
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
+#define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \
+ ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \
+ )
+
+#elif defined(STM32F303x8) || defined(STM32F328xx)
+#define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \
+ ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \
+ )
+
+#elif defined(STM32F302xE) || defined(STM32F302xC) || defined(STM32F302x8)
+#define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \
+ ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \
+ )
+
+#elif defined(STM32F301x8) || defined(STM32F318xx)
+#define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \
+ ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \
+ )
+
+#elif defined(STM32F373xC) || defined(STM32F378xx)
+#define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \
+ ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM5_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \
+ )
+
+#elif defined(STM32F334x8)
+#define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \
+ ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIGGER_HRTIM1_DACTRG2) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIGGER_HRTIM1_DACTRG3) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \
+ )
+#endif
+
+#define IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__) \
+ ( ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE) \
+ || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \
+ || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \
+ )
+
+#define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_CONFIG__) \
+ ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095) \
+ )
+
+#define IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__) \
+ ( ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE) \
+ || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE) \
+ )
+
+/**
+ * @}
+ */
+
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DAC_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DAC_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize registers of the selected DAC instance
+ * to their default reset values.
+ * @param DACx DAC instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: DAC registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_ALL_INSTANCE(DACx));
+
+ if(DACx == DAC1)
+ {
+ /* Force reset of DAC clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_DAC1);
+
+ /* Release reset of DAC clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_DAC1);
+ }
+#if defined(DAC2)
+ else
+ {
+ /* Force reset of DAC clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_DAC2);
+
+ /* Release reset of DAC clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_DAC2);
+ }
+#endif
+ return SUCCESS;
+}
+
+/**
+ * @brief Initialize some features of DAC instance.
+ * @note The setting of these parameters by function @ref LL_DAC_Init()
+ * is conditioned to DAC state:
+ * DAC instance must be disabled.
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @param DAC_InitStruct Pointer to a @ref LL_DAC_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: DAC registers are initialized
+ * - ERROR: DAC registers are not initialized
+ */
+ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_ALL_INSTANCE(DACx));
+ assert_param(IS_LL_DAC_CHANNEL(DACx, DAC_Channel));
+ assert_param(IS_LL_DAC_TRIGGER_SOURCE(DAC_InitStruct->TriggerSource));
+ assert_param(IS_LL_DAC_OUTPUT_BUFFER(DAC_InitStruct->OutputBuffer));
+ assert_param(IS_LL_DAC_WAVE_AUTO_GENER_MODE(DAC_InitStruct->WaveAutoGeneration));
+ if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE)
+ {
+ assert_param(IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(DAC_InitStruct->WaveAutoGenerationConfig));
+ }
+
+ /* Note: Hardware constraint (refer to description of this function) */
+ /* DAC instance must be disabled. */
+ if(LL_DAC_IsEnabled(DACx, DAC_Channel) == 0U)
+ {
+ /* Configuration of DAC channel: */
+ /* - TriggerSource */
+ /* - WaveAutoGeneration */
+ /* - OutputBuffer */
+ if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE)
+ {
+ MODIFY_REG(DACx->CR,
+ ( DAC_CR_TSEL1
+ | DAC_CR_WAVE1
+ | DAC_CR_MAMP1
+ | DAC_CR_BOFF1
+ ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ ,
+ ( DAC_InitStruct->TriggerSource
+ | DAC_InitStruct->WaveAutoGeneration
+ | DAC_InitStruct->WaveAutoGenerationConfig
+ | DAC_InitStruct->OutputBuffer
+ ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ );
+ }
+ else
+ {
+ MODIFY_REG(DACx->CR,
+ ( DAC_CR_TSEL1
+ | DAC_CR_WAVE1
+ | DAC_CR_BOFF1
+ ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ ,
+ ( DAC_InitStruct->TriggerSource
+ | LL_DAC_WAVE_AUTO_GENERATION_NONE
+ | DAC_InitStruct->OutputBuffer
+ ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ );
+ }
+ }
+ else
+ {
+ /* Initialization error: DAC instance is not disabled. */
+ status = ERROR;
+ }
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_DAC_InitTypeDef field to default value.
+ * @param DAC_InitStruct pointer to a @ref LL_DAC_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct)
+{
+ /* Set DAC_InitStruct fields to default values */
+ DAC_InitStruct->TriggerSource = LL_DAC_TRIG_SOFTWARE;
+ DAC_InitStruct->WaveAutoGeneration = LL_DAC_WAVE_AUTO_GENERATION_NONE;
+ /* Note: Parameter discarded if wave auto generation is disabled, */
+ /* set anyway to its default value. */
+ DAC_InitStruct->WaveAutoGenerationConfig = LL_DAC_NOISE_LFSR_UNMASK_BIT0;
+ DAC_InitStruct->OutputBuffer = LL_DAC_OUTPUT_BUFFER_ENABLE;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* DAC1 || DAC2 */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_ll_dma.c b/Src/stm32f3xx_ll_dma.c
new file mode 100644
index 0000000..99b1d5d
--- /dev/null
+++ b/Src/stm32f3xx_ll_dma.c
@@ -0,0 +1,352 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_dma.c
+ * @author MCD Application Team
+ * @brief DMA LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_ll_dma.h"
+#include "stm32f3xx_ll_bus.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined (DMA1) || defined (DMA2)
+
+/** @defgroup DMA_LL DMA
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup DMA_LL_Private_Macros
+ * @{
+ */
+#define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
+ ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
+ ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
+
+#define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
+ ((__VALUE__) == LL_DMA_MODE_CIRCULAR))
+
+#define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
+ ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
+
+#define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
+ ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
+
+#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \
+ ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \
+ ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
+
+#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \
+ ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \
+ ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
+
+#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
+
+
+#define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \
+ ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
+ ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \
+ ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
+
+#if defined (DMA2)
+#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
+#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
+ (((CHANNEL) == LL_DMA_CHANNEL_1) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_2) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_3) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_4) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_5) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_6) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
+ (((INSTANCE) == DMA2) && \
+ (((CHANNEL) == LL_DMA_CHANNEL_1) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_2) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_3) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_4) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_5) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_6) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_7))))
+#else
+#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
+ (((CHANNEL) == LL_DMA_CHANNEL_1) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_2) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_3) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_4) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_5) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_6) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
+ (((INSTANCE) == DMA2) && \
+ (((CHANNEL) == LL_DMA_CHANNEL_1) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_2) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_3) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_4) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_5))))
+#endif
+#else
+#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
+ (((CHANNEL) == LL_DMA_CHANNEL_1)|| \
+ ((CHANNEL) == LL_DMA_CHANNEL_2) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_3) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_4) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_5) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_6) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_7))))
+#endif
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DMA_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DMA_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize the DMA registers to their default reset values.
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: DMA registers are de-initialized
+ * - ERROR: DMA registers are not de-initialized
+ */
+uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ DMA_Channel_TypeDef *tmp = (DMA_Channel_TypeDef *)DMA1_Channel1;
+ ErrorStatus status = SUCCESS;
+
+ /* Check the DMA Instance DMAx and Channel parameters*/
+ assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
+
+ tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
+
+ /* Disable the selected DMAx_Channely */
+ CLEAR_BIT(tmp->CCR, DMA_CCR_EN);
+
+ /* Reset DMAx_Channely control register */
+ LL_DMA_WriteReg(tmp, CCR, 0U);
+
+ /* Reset DMAx_Channely remaining bytes register */
+ LL_DMA_WriteReg(tmp, CNDTR, 0U);
+
+ /* Reset DMAx_Channely peripheral address register */
+ LL_DMA_WriteReg(tmp, CPAR, 0U);
+
+ /* Reset DMAx_Channely memory address register */
+ LL_DMA_WriteReg(tmp, CMAR, 0U);
+
+
+ if (Channel == LL_DMA_CHANNEL_1)
+ {
+ /* Reset interrupt pending bits for DMAx Channel1 */
+ LL_DMA_ClearFlag_GI1(DMAx);
+ }
+ else if (Channel == LL_DMA_CHANNEL_2)
+ {
+ /* Reset interrupt pending bits for DMAx Channel2 */
+ LL_DMA_ClearFlag_GI2(DMAx);
+ }
+ else if (Channel == LL_DMA_CHANNEL_3)
+ {
+ /* Reset interrupt pending bits for DMAx Channel3 */
+ LL_DMA_ClearFlag_GI3(DMAx);
+ }
+ else if (Channel == LL_DMA_CHANNEL_4)
+ {
+ /* Reset interrupt pending bits for DMAx Channel4 */
+ LL_DMA_ClearFlag_GI4(DMAx);
+ }
+ else if (Channel == LL_DMA_CHANNEL_5)
+ {
+ /* Reset interrupt pending bits for DMAx Channel5 */
+ LL_DMA_ClearFlag_GI5(DMAx);
+ }
+
+ else if (Channel == LL_DMA_CHANNEL_6)
+ {
+ /* Reset interrupt pending bits for DMAx Channel6 */
+ LL_DMA_ClearFlag_GI6(DMAx);
+ }
+ else if (Channel == LL_DMA_CHANNEL_7)
+ {
+ /* Reset interrupt pending bits for DMAx Channel7 */
+ LL_DMA_ClearFlag_GI7(DMAx);
+ }
+ else
+ {
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
+ * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
+ * @arg @ref __LL_DMA_GET_INSTANCE
+ * @arg @ref __LL_DMA_GET_CHANNEL
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: DMA registers are initialized
+ * - ERROR: Not applicable
+ */
+uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
+{
+ /* Check the DMA Instance DMAx and Channel parameters*/
+ assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
+
+ /* Check the DMA parameters from DMA_InitStruct */
+ assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
+ assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
+ assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
+ assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
+ assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
+ assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
+ assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
+ assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
+
+ /*---------------------------- DMAx CCR Configuration ------------------------
+ * Configure DMAx_Channely: data transfer direction, data transfer mode,
+ * peripheral and memory increment mode,
+ * data size alignment and priority level with parameters :
+ * - Direction: DMA_CCR_DIR and DMA_CCR_MEM2MEM bits
+ * - Mode: DMA_CCR_CIRC bit
+ * - PeriphOrM2MSrcIncMode: DMA_CCR_PINC bit
+ * - MemoryOrM2MDstIncMode: DMA_CCR_MINC bit
+ * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits
+ * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits
+ * - Priority: DMA_CCR_PL[1:0] bits
+ */
+ LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction | \
+ DMA_InitStruct->Mode | \
+ DMA_InitStruct->PeriphOrM2MSrcIncMode | \
+ DMA_InitStruct->MemoryOrM2MDstIncMode | \
+ DMA_InitStruct->PeriphOrM2MSrcDataSize | \
+ DMA_InitStruct->MemoryOrM2MDstDataSize | \
+ DMA_InitStruct->Priority);
+
+ /*-------------------------- DMAx CMAR Configuration -------------------------
+ * Configure the memory or destination base address with parameter :
+ * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits
+ */
+ LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress);
+
+ /*-------------------------- DMAx CPAR Configuration -------------------------
+ * Configure the peripheral or source base address with parameter :
+ * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits
+ */
+ LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress);
+
+ /*--------------------------- DMAx CNDTR Configuration -----------------------
+ * Configure the peripheral base address with parameter :
+ * - NbData: DMA_CNDTR_NDT[15:0] bits
+ */
+ LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData);
+
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Set each @ref LL_DMA_InitTypeDef field to default value.
+ * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
+ * @retval None
+ */
+void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
+{
+ /* Set DMA_InitStruct fields to default values */
+ DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
+ DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
+ DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
+ DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
+ DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
+ DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
+ DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
+ DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
+ DMA_InitStruct->NbData = 0x00000000U;
+ DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* DMA1 || DMA2 */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_ll_exti.c b/Src/stm32f3xx_ll_exti.c
new file mode 100644
index 0000000..c21ffed
--- /dev/null
+++ b/Src/stm32f3xx_ll_exti.c
@@ -0,0 +1,317 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_exti.c
+ * @author MCD Application Team
+ * @brief EXTI LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_ll_exti.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined (EXTI)
+
+/** @defgroup EXTI_LL EXTI
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup EXTI_LL_Private_Macros
+ * @{
+ */
+
+#define IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
+#if defined(EXTI_32_63_SUPPORT)
+#define IS_LL_EXTI_LINE_32_63(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_32_63) == 0x00000000U)
+#endif
+
+#define IS_LL_EXTI_MODE(__VALUE__) (((__VALUE__) == LL_EXTI_MODE_IT) \
+ || ((__VALUE__) == LL_EXTI_MODE_EVENT) \
+ || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))
+
+
+#define IS_LL_EXTI_TRIGGER(__VALUE__) (((__VALUE__) == LL_EXTI_TRIGGER_NONE) \
+ || ((__VALUE__) == LL_EXTI_TRIGGER_RISING) \
+ || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING) \
+ || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup EXTI_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup EXTI_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize the EXTI registers to their default reset values.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: EXTI registers are de-initialized
+ * - ERROR: not applicable
+ */
+uint32_t LL_EXTI_DeInit(void)
+{
+ /* Interrupt mask register set to default reset values */
+ LL_EXTI_WriteReg(IMR, 0x1F800000U);
+ /* Event mask register set to default reset values */
+ LL_EXTI_WriteReg(EMR, 0x00000000U);
+ /* Rising Trigger selection register set to default reset values */
+ LL_EXTI_WriteReg(RTSR, 0x00000000U);
+ /* Falling Trigger selection register set to default reset values */
+ LL_EXTI_WriteReg(FTSR, 0x00000000U);
+ /* Software interrupt event register set to default reset values */
+ LL_EXTI_WriteReg(SWIER, 0x00000000U);
+ /* Pending register clear */
+ LL_EXTI_WriteReg(PR, 0x007FFFFFU);
+
+#if defined(EXTI_32_63_SUPPORT)
+ /* Interrupt mask register 2 set to default reset values */
+#if defined(STM32F334x8)
+ LL_EXTI_WriteReg(IMR2, 0xFFFFFFFEU);
+#else
+ LL_EXTI_WriteReg(IMR2, 0xFFFFFFFCU);
+#endif
+ /* Event mask register 2 set to default reset values */
+ LL_EXTI_WriteReg(EMR2, 0x00000000U);
+ /* Rising Trigger selection register 2 set to default reset values */
+ LL_EXTI_WriteReg(RTSR2, 0x00000000U);
+ /* Falling Trigger selection register 2 set to default reset values */
+ LL_EXTI_WriteReg(FTSR2, 0x00000000U);
+ /* Software interrupt event register 2 set to default reset values */
+ LL_EXTI_WriteReg(SWIER2, 0x00000000U);
+ /* Pending register 2 clear */
+ LL_EXTI_WriteReg(PR2, 0x00000003U);
+
+#endif
+ return SUCCESS;
+}
+
+/**
+ * @brief Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
+ * @param EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: EXTI registers are initialized
+ * - ERROR: not applicable
+ */
+uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
+{
+ ErrorStatus status = SUCCESS;
+ /* Check the parameters */
+ assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31));
+#if defined(EXTI_32_63_SUPPORT)
+ assert_param(IS_LL_EXTI_LINE_32_63(EXTI_InitStruct->Line_32_63));
+#endif
+ assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand));
+ assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode));
+
+ /* ENABLE LineCommand */
+ if (EXTI_InitStruct->LineCommand != DISABLE)
+ {
+ assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger));
+
+ /* Configure EXTI Lines in range from 0 to 31 */
+ if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE)
+ {
+ switch (EXTI_InitStruct->Mode)
+ {
+ case LL_EXTI_MODE_IT:
+ /* First Disable Event on provided Lines */
+ LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
+ /* Then Enable IT on provided Lines */
+ LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
+ break;
+ case LL_EXTI_MODE_EVENT:
+ /* First Disable IT on provided Lines */
+ LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
+ /* Then Enable Event on provided Lines */
+ LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
+ break;
+ case LL_EXTI_MODE_IT_EVENT:
+ /* Directly Enable IT & Event on provided Lines */
+ LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
+ LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
+ break;
+ default:
+ status = ERROR;
+ break;
+ }
+ if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
+ {
+ switch (EXTI_InitStruct->Trigger)
+ {
+ case LL_EXTI_TRIGGER_RISING:
+ /* First Disable Falling Trigger on provided Lines */
+ LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ /* Then Enable Rising Trigger on provided Lines */
+ LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ break;
+ case LL_EXTI_TRIGGER_FALLING:
+ /* First Disable Rising Trigger on provided Lines */
+ LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ /* Then Enable Falling Trigger on provided Lines */
+ LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ break;
+ case LL_EXTI_TRIGGER_RISING_FALLING:
+ LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ break;
+ default:
+ status = ERROR;
+ break;
+ }
+ }
+ }
+#if defined(EXTI_32_63_SUPPORT)
+ /* Configure EXTI Lines in range from 32 to 63 */
+ if (EXTI_InitStruct->Line_32_63 != LL_EXTI_LINE_NONE)
+ {
+ switch (EXTI_InitStruct->Mode)
+ {
+ case LL_EXTI_MODE_IT:
+ /* First Disable Event on provided Lines */
+ LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
+ /* Then Enable IT on provided Lines */
+ LL_EXTI_EnableIT_32_63(EXTI_InitStruct->Line_32_63);
+ break;
+ case LL_EXTI_MODE_EVENT:
+ /* First Disable IT on provided Lines */
+ LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63);
+ /* Then Enable Event on provided Lines */
+ LL_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63);
+ break;
+ case LL_EXTI_MODE_IT_EVENT:
+ /* Directly Enable IT & Event on provided Lines */
+ LL_EXTI_EnableIT_32_63(EXTI_InitStruct->Line_32_63);
+ LL_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63);
+ break;
+ default:
+ status = ERROR;
+ break;
+ }
+ if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
+ {
+ switch (EXTI_InitStruct->Trigger)
+ {
+ case LL_EXTI_TRIGGER_RISING:
+ /* First Disable Falling Trigger on provided Lines */
+ LL_EXTI_DisableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
+ /* Then Enable IT on provided Lines */
+ LL_EXTI_EnableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
+ break;
+ case LL_EXTI_TRIGGER_FALLING:
+ /* First Disable Rising Trigger on provided Lines */
+ LL_EXTI_DisableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
+ /* Then Enable Falling Trigger on provided Lines */
+ LL_EXTI_EnableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
+ break;
+ case LL_EXTI_TRIGGER_RISING_FALLING:
+ LL_EXTI_EnableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
+ LL_EXTI_EnableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
+ break;
+ default:
+ status = ERROR;
+ break;
+ }
+ }
+ }
+#endif
+ }
+ /* DISABLE LineCommand */
+ else
+ {
+ /* De-configure EXTI Lines in range from 0 to 31 */
+ LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
+ LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
+#if defined(EXTI_32_63_SUPPORT)
+ /* De-configure EXTI Lines in range from 32 to 63 */
+ LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63);
+ LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
+#endif
+ }
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_EXTI_InitTypeDef field to default value.
+ * @param EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure.
+ * @retval None
+ */
+void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct)
+{
+ EXTI_InitStruct->Line_0_31 = LL_EXTI_LINE_NONE;
+#if defined(EXTI_32_63_SUPPORT)
+ EXTI_InitStruct->Line_32_63 = LL_EXTI_LINE_NONE;
+#endif
+ EXTI_InitStruct->LineCommand = DISABLE;
+ EXTI_InitStruct->Mode = LL_EXTI_MODE_IT;
+ EXTI_InitStruct->Trigger = LL_EXTI_TRIGGER_FALLING;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (EXTI) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_ll_fmc.c b/Src/stm32f3xx_ll_fmc.c
new file mode 100644
index 0000000..c525979
--- /dev/null
+++ b/Src/stm32f3xx_ll_fmc.c
@@ -0,0 +1,997 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_fmc.c
+ * @author MCD Application Team
+ * @brief FMC Low Layer HAL module driver.
+ *
+ * This file provides firmware functions to manage the following
+ * functionalities of the Flexible Memory Controller (FMC) peripheral memories:
+ * + Initialization/de-initialization functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ @verbatim
+ =============================================================================
+ ##### FMC peripheral features #####
+ =============================================================================
+ [..] The Flexible memory controller (FMC) includes following memory controllers:
+ (+) The NOR/PSRAM memory controller
+ (+) The PC Card memory controller
+ (+) The NAND memory controller
+
+ [..] The FMC functional block makes the interface with synchronous and asynchronous static
+ memories and 16-bit PC memory cards. Its main purposes are:
+ (+) to translate AHB transactions into the appropriate external device protocol.
+ (+) to meet the access time requirements of the external memory devices.
+
+ [..] All external memories share the addresses, data and control signals with the controller.
+ Each external device is accessed by means of a unique Chip Select. The FMC performs
+ only one access at a time to an external device.
+ The main features of the FMC controller are the following:
+ (+) Interface with static-memory mapped devices including:
+ (++) Static random access memory (SRAM).
+ (++) NOR Flash memory.
+ (++) PSRAM (4 memory banks).
+ (++) 16-bit PC Card compatible devices
+ (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
+ data
+ (+) Independent Chip Select control for each memory bank
+ (+) Independent configuration for each memory bank
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+#if defined(FMC_BANK1)
+
+#if defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED)
+
+/** @defgroup FMC_LL FMC Low Layer
+ * @brief FMC driver modules
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup FMC_LL_Private_Constants FMC Low Layer Private Constants
+ * @{
+ */
+
+/* ----------------------- FMC registers bit mask --------------------------- */
+/* --- PCR Register ---*/
+/* PCR register clear mask */
+#define PCR_CLEAR_MASK ((uint32_t)(FMC_PCRx_PWAITEN | FMC_PCRx_PBKEN | \
+ FMC_PCRx_PTYP | FMC_PCRx_PWID | \
+ FMC_PCRx_ECCEN | FMC_PCRx_TCLR | \
+ FMC_PCRx_TAR | FMC_PCRx_ECCPS))
+
+/* --- PMEM Register ---*/
+/* PMEM register clear mask */
+#define PMEM_CLEAR_MASK ((uint32_t)(FMC_PMEMx_MEMSETx | FMC_PMEMx_MEMWAITx |\
+ FMC_PMEMx_MEMHOLDx | FMC_PMEMx_MEMHIZx))
+
+/* --- PATT Register ---*/
+/* PATT register clear mask */
+#define PATT_CLEAR_MASK ((uint32_t)(FMC_PATTx_ATTSETx | FMC_PATTx_ATTWAITx |\
+ FMC_PATTx_ATTHOLDx | FMC_PATTx_ATTHIZx))
+
+/* --- BCR Register ---*/
+/* BCR register clear mask */
+#define BCR_CLEAR_MASK ((uint32_t)(FMC_BCRx_MBKEN | FMC_BCRx_MUXEN |\
+ FMC_BCRx_MTYP | FMC_BCRx_MWID |\
+ FMC_BCRx_FACCEN | FMC_BCRx_BURSTEN |\
+ FMC_BCRx_WAITPOL | FMC_BCRx_WRAPMOD |\
+ FMC_BCRx_WAITCFG | FMC_BCRx_WREN |\
+ FMC_BCRx_WAITEN | FMC_BCRx_EXTMOD |\
+ FMC_BCRx_ASYNCWAIT | FMC_BCRx_CBURSTRW |\
+ FMC_BCR1_CCLKEN))
+
+/* --- BTR Register ---*/
+/* BTR register clear mask */
+#define BTR_CLEAR_MASK ((uint32_t)(FMC_BTRx_ADDSET | FMC_BTRx_ADDHLD |\
+ FMC_BTRx_DATAST | FMC_BTRx_BUSTURN |\
+ FMC_BTRx_CLKDIV | FMC_BTRx_DATLAT |\
+ FMC_BTRx_ACCMOD))
+
+/* --- BWTR Register ---*/
+/* BWTR register clear mask */
+#define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD |\
+ FMC_BWTRx_DATAST | FMC_BWTRx_ACCMOD))
+
+/* --- PIO4 Register ---*/
+/* PIO4 register clear mask */
+#define PIO4_CLEAR_MASK ((uint32_t)(FMC_PIO4_IOSET4 | FMC_PIO4_IOWAIT4 | \
+ FMC_PIO4_IOHOLD4 | FMC_PIO4_IOHIZ4))
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup FMC_LL_Private_Macros FMC Low Layer Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions
+ * @{
+ */
+
+/** @defgroup FMC_NORSRAM FMC NORSRAM Controller functions
+ * @brief NORSRAM Controller functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use NORSRAM device driver #####
+ ==============================================================================
+
+ [..]
+ This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
+ to run the NORSRAM external devices.
+
+ (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit()
+ (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
+ (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
+ (+) FMC NORSRAM bank extended timing configuration using the function
+ FMC_NORSRAM_Extended_Timing_Init()
+ (+) FMC NORSRAM bank enable/disable write operation using the functions
+ FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
+
+
+@endverbatim
+ * @{
+ */
+
+/** @defgroup FMC_NORSRAM_Group1 Initialization/de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### Initialization and de_initialization functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the FMC NORSRAM interface
+ (+) De-initialize the FMC NORSRAM interface
+ (+) Configure the FMC clock and associated GPIOs
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the FMC_NORSRAM device according to the specified
+ * control parameters in the FMC_NORSRAM_InitTypeDef
+ * @param Device Pointer to NORSRAM device instance
+ * @param Init Pointer to NORSRAM Initialization structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_NORSRAM_DEVICE(Device));
+ assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
+ assert_param(IS_FMC_MUX(Init->DataAddressMux));
+ assert_param(IS_FMC_MEMORY(Init->MemoryType));
+ assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
+ assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
+ assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
+ assert_param(IS_FMC_WRAP_MODE(Init->WrapMode));
+ assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
+ assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
+ assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
+ assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
+ assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
+ assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
+ assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
+
+ /* Disable NORSRAM Device */
+ __FMC_NORSRAM_DISABLE(Device, Init->NSBank);
+
+ /* Set NORSRAM device control parameters */
+ if (Init->MemoryType == FMC_MEMORY_TYPE_NOR)
+ {
+ MODIFY_REG(Device->BTCR[Init->NSBank], BCR_CLEAR_MASK, (uint32_t)(FMC_NORSRAM_FLASH_ACCESS_ENABLE
+ | Init->DataAddressMux
+ | Init->MemoryType
+ | Init->MemoryDataWidth
+ | Init->BurstAccessMode
+ | Init->WaitSignalPolarity
+ | Init->WrapMode
+ | Init->WaitSignalActive
+ | Init->WriteOperation
+ | Init->WaitSignal
+ | Init->ExtendedMode
+ | Init->AsynchronousWait
+ | Init->WriteBurst
+ | Init->ContinuousClock
+ )
+ );
+ }
+ else
+ {
+ MODIFY_REG(Device->BTCR[Init->NSBank], BCR_CLEAR_MASK, (uint32_t)(FMC_NORSRAM_FLASH_ACCESS_DISABLE
+ | Init->DataAddressMux
+ | Init->MemoryType
+ | Init->MemoryDataWidth
+ | Init->BurstAccessMode
+ | Init->WaitSignalPolarity
+ | Init->WrapMode
+ | Init->WaitSignalActive
+ | Init->WriteOperation
+ | Init->WaitSignal
+ | Init->ExtendedMode
+ | Init->AsynchronousWait
+ | Init->WriteBurst
+ | Init->ContinuousClock
+ )
+ );
+ }
+
+ /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
+ if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
+ {
+ MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock);
+ }
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief DeInitialize the FMC_NORSRAM peripheral
+ * @param Device Pointer to NORSRAM device instance
+ * @param ExDevice Pointer to NORSRAM extended mode device instance
+ * @param Bank NORSRAM bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_NORSRAM_DEVICE(Device));
+ assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
+ assert_param(IS_FMC_NORSRAM_BANK(Bank));
+
+ /* Disable the FMC_NORSRAM device */
+ __FMC_NORSRAM_DISABLE(Device, Bank);
+
+ /* De-initialize the FMC_NORSRAM device */
+ /* FMC_NORSRAM_BANK1 */
+ if (Bank == FMC_NORSRAM_BANK1)
+ {
+ Device->BTCR[Bank] = 0x000030DB;
+ }
+ /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
+ else
+ {
+ Device->BTCR[Bank] = 0x000030D2;
+ }
+
+ Device->BTCR[Bank + 1] = 0x0FFFFFFF;
+ ExDevice->BWTR[Bank] = 0x0FFFFFFF;
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Initialize the FMC_NORSRAM Timing according to the specified
+ * parameters in the FMC_NORSRAM_TimingTypeDef
+ * @param Device Pointer to NORSRAM device instance
+ * @param Timing Pointer to NORSRAM Timing structure
+ * @param Bank NORSRAM bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
+{
+ uint32_t tmpr = 0;
+
+ /* Check the parameters */
+ assert_param(IS_FMC_NORSRAM_DEVICE(Device));
+ assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
+ assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
+ assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
+ assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
+ assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
+ assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
+ assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
+ assert_param(IS_FMC_NORSRAM_BANK(Bank));
+
+ /* Set FMC_NORSRAM device timing parameters */
+ MODIFY_REG(Device->BTCR[Bank + 1], \
+ BTR_CLEAR_MASK, \
+ (uint32_t)(Timing->AddressSetupTime | \
+ ((Timing->AddressHoldTime) << POSITION_VAL(FMC_BTRx_ADDHLD)) | \
+ ((Timing->DataSetupTime) << POSITION_VAL(FMC_BTRx_DATAST)) | \
+ ((Timing->BusTurnAroundDuration) << POSITION_VAL(FMC_BTRx_BUSTURN)) | \
+ (((Timing->CLKDivision) - 1) << POSITION_VAL(FMC_BTRx_CLKDIV)) | \
+ (((Timing->DataLatency) - 2) << POSITION_VAL(FMC_BTRx_DATLAT)) | \
+ (Timing->AccessMode)));
+
+ /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
+ if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
+ {
+ tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1] & ~(((uint32_t)0x0F) << POSITION_VAL(FMC_BTRx_CLKDIV)));
+ tmpr |= (uint32_t)(((Timing->CLKDivision) - 1) << POSITION_VAL(FMC_BTRx_CLKDIV));
+ MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1], FMC_BTRx_CLKDIV, tmpr);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified
+ * parameters in the FMC_NORSRAM_TimingTypeDef
+ * @param Device Pointer to NORSRAM device instance
+ * @param Timing Pointer to NORSRAM Timing structure
+ * @param Bank NORSRAM bank number
+ * @param ExtendedMode FMC Extended Mode
+ * This parameter can be one of the following values:
+ * @arg FMC_EXTENDED_MODE_DISABLE
+ * @arg FMC_EXTENDED_MODE_ENABLE
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
+
+ /* Set NORSRAM device timing register for write configuration, if extended mode is used */
+ if (ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
+ {
+ /* Check the parameters */
+ assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
+ assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
+ assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
+ assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
+ assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
+ assert_param(IS_FMC_NORSRAM_BANK(Bank));
+
+ /* Set NORSRAM device timing register for write configuration, if extended mode is used */
+ MODIFY_REG(Device->BWTR[Bank], \
+ BWTR_CLEAR_MASK, \
+ (uint32_t)(Timing->AddressSetupTime | \
+ ((Timing->AddressHoldTime) << POSITION_VAL(FMC_BWTRx_ADDHLD)) | \
+ ((Timing->DataSetupTime) << POSITION_VAL(FMC_BWTRx_DATAST)) | \
+ (Timing->AccessMode)));
+ }
+ else
+ {
+ Device->BWTR[Bank] = 0x0FFFFFFF;
+ }
+
+ return HAL_OK;
+}
+
+
+/**
+ * @}
+ */
+
+
+/** @defgroup FMC_NORSRAM_Group2 Control functions
+ * @brief management functions
+ *
+@verbatim
+ ==============================================================================
+ ##### FMC_NORSRAM Control functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control dynamically
+ the FMC NORSRAM interface.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables dynamically FMC_NORSRAM write operation.
+ * @param Device Pointer to NORSRAM device instance
+ * @param Bank NORSRAM bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_NORSRAM_DEVICE(Device));
+ assert_param(IS_FMC_NORSRAM_BANK(Bank));
+
+ /* Enable write operation */
+ SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables dynamically FMC_NORSRAM write operation.
+ * @param Device Pointer to NORSRAM device instance
+ * @param Bank NORSRAM bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_NORSRAM_DEVICE(Device));
+ assert_param(IS_FMC_NORSRAM_BANK(Bank));
+
+ /* Disable write operation */
+ CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/** @defgroup FMC_NAND FMC NAND Controller functions
+ * @brief NAND Controller functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use NAND device driver #####
+ ==============================================================================
+ [..]
+ This driver contains a set of APIs to interface with the FMC NAND banks in order
+ to run the NAND external devices.
+
+ (+) FMC NAND bank reset using the function FMC_NAND_DeInit()
+ (+) FMC NAND bank control configuration using the function FMC_NAND_Init()
+ (+) FMC NAND bank common space timing configuration using the function
+ FMC_NAND_CommonSpace_Timing_Init()
+ (+) FMC NAND bank attribute space timing configuration using the function
+ FMC_NAND_AttributeSpace_Timing_Init()
+ (+) FMC NAND bank enable/disable ECC correction feature using the functions
+ FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
+ (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()
+
+@endverbatim
+ * @{
+ */
+
+/** @defgroup FMC_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de_initialization functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the FMC NAND interface
+ (+) De-initialize the FMC NAND interface
+ (+) Configure the FMC clock and associated GPIOs
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the FMC_NAND device according to the specified
+ * control parameters in the FMC_NAND_HandleTypeDef
+ * @param Device Pointer to NAND device instance
+ * @param Init Pointer to NAND Initialization structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
+ assert_param(IS_FMC_NAND_BANK(Init->NandBank));
+ assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
+ assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
+ assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
+ assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
+ assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
+ assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
+
+ /* Set NAND device control parameters */
+ if (Init->NandBank == FMC_NAND_BANK2)
+ {
+ /* NAND bank 2 registers configuration */
+ MODIFY_REG(Device->PCR2, PCR_CLEAR_MASK, (Init->Waitfeature |
+ FMC_PCR_MEMORY_TYPE_NAND |
+ Init->MemoryDataWidth |
+ Init->EccComputation |
+ Init->ECCPageSize |
+ ((Init->TCLRSetupTime) << POSITION_VAL(FMC_PCRx_TCLR)) |
+ ((Init->TARSetupTime) << POSITION_VAL(FMC_PCRx_TAR))));
+ }
+ else
+ {
+ /* NAND bank 3 registers configuration */
+ MODIFY_REG(Device->PCR3, PCR_CLEAR_MASK, (Init->Waitfeature |
+ FMC_PCR_MEMORY_TYPE_NAND |
+ Init->MemoryDataWidth |
+ Init->EccComputation |
+ Init->ECCPageSize |
+ ((Init->TCLRSetupTime) << POSITION_VAL(FMC_PCRx_TCLR)) |
+ ((Init->TARSetupTime) << POSITION_VAL(FMC_PCRx_TAR))));
+ }
+
+ return HAL_OK;
+
+}
+
+/**
+ * @brief Initializes the FMC_NAND Common space Timing according to the specified
+ * parameters in the FMC_NAND_PCC_TimingTypeDef
+ * @param Device Pointer to NAND device instance
+ * @param Timing Pointer to NAND timing structure
+ * @param Bank NAND bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
+ assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
+ assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
+ assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
+ assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
+ assert_param(IS_FMC_NAND_BANK(Bank));
+
+ /* Set FMC_NAND device timing parameters */
+ if (Bank == FMC_NAND_BANK2)
+ {
+ /* NAND bank 2 registers configuration */
+ MODIFY_REG(Device->PMEM2, PMEM_CLEAR_MASK, (Timing->SetupTime | \
+ ((Timing->WaitSetupTime) << POSITION_VAL(FMC_PMEMx_MEMWAITx)) | \
+ ((Timing->HoldSetupTime) << POSITION_VAL(FMC_PMEMx_MEMHOLDx)) | \
+ ((Timing->HiZSetupTime) << POSITION_VAL(FMC_PMEMx_MEMHIZx))));
+ }
+ else
+ {
+ /* NAND bank 3 registers configuration */
+ MODIFY_REG(Device->PMEM3, PMEM_CLEAR_MASK, (Timing->SetupTime | \
+ ((Timing->WaitSetupTime) << POSITION_VAL(FMC_PMEMx_MEMWAITx)) | \
+ ((Timing->HoldSetupTime) << POSITION_VAL(FMC_PMEMx_MEMHOLDx)) | \
+ ((Timing->HiZSetupTime) << POSITION_VAL(FMC_PMEMx_MEMHIZx))));
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the FMC_NAND Attribute space Timing according to the specified
+ * parameters in the FMC_NAND_PCC_TimingTypeDef
+ * @param Device Pointer to NAND device instance
+ * @param Timing Pointer to NAND timing structure
+ * @param Bank NAND bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
+ assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
+ assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
+ assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
+ assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
+ assert_param(IS_FMC_NAND_BANK(Bank));
+
+ /* Set FMC_NAND device timing parameters */
+ if (Bank == FMC_NAND_BANK2)
+ {
+ /* NAND bank 2 registers configuration */
+ MODIFY_REG(Device->PATT2, PATT_CLEAR_MASK, (Timing->SetupTime | \
+ ((Timing->WaitSetupTime) << POSITION_VAL(FMC_PATTx_ATTWAITx)) | \
+ ((Timing->HoldSetupTime) << POSITION_VAL(FMC_PATTx_ATTHOLDx)) | \
+ ((Timing->HiZSetupTime) << POSITION_VAL(FMC_PATTx_ATTHIZx))));
+ }
+ else
+ {
+ /* NAND bank 3 registers configuration */
+ MODIFY_REG(Device->PATT3, PATT_CLEAR_MASK, (Timing->SetupTime | \
+ ((Timing->WaitSetupTime) << POSITION_VAL(FMC_PATTx_ATTWAITx)) | \
+ ((Timing->HoldSetupTime) << POSITION_VAL(FMC_PATTx_ATTHOLDx)) | \
+ ((Timing->HiZSetupTime) << POSITION_VAL(FMC_PATTx_ATTHIZx))));
+ }
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief DeInitialize the FMC_NAND device
+ * @param Device Pointer to NAND device instance
+ * @param Bank NAND bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
+ assert_param(IS_FMC_NAND_BANK(Bank));
+
+ /* Disable the NAND Bank */
+ __FMC_NAND_DISABLE(Device, Bank);
+
+ /* De-initialize the NAND Bank */
+ if (Bank == FMC_NAND_BANK2)
+ {
+ /* Set the FMC_NAND_BANK2 registers to their reset values */
+ WRITE_REG(Device->PCR2, 0x00000018);
+ WRITE_REG(Device->SR2, 0x00000040);
+ WRITE_REG(Device->PMEM2, 0xFCFCFCFC);
+ WRITE_REG(Device->PATT2, 0xFCFCFCFC);
+ }
+ /* FMC_Bank3_NAND */
+ else
+ {
+ /* Set the FMC_NAND_BANK3 registers to their reset values */
+ WRITE_REG(Device->PCR3, 0x00000018);
+ WRITE_REG(Device->SR3, 0x00000040);
+ WRITE_REG(Device->PMEM3, 0xFCFCFCFC);
+ WRITE_REG(Device->PATT3, 0xFCFCFCFC);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup FMC_NAND_Exported_Functions_Group2 Peripheral Control functions
+ * @brief management functions
+ *
+@verbatim
+ ==============================================================================
+ ##### FMC_NAND Control functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control dynamically
+ the FMC NAND interface.
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Enables dynamically FMC_NAND ECC feature.
+ * @param Device Pointer to NAND device instance
+ * @param Bank NAND bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
+ assert_param(IS_FMC_NAND_BANK(Bank));
+
+ /* Enable ECC feature */
+ if (Bank == FMC_NAND_BANK2)
+ {
+ SET_BIT(Device->PCR2, FMC_PCRx_ECCEN);
+ }
+ else
+ {
+ SET_BIT(Device->PCR3, FMC_PCRx_ECCEN);
+ }
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Disables dynamically FMC_NAND ECC feature.
+ * @param Device Pointer to NAND device instance
+ * @param Bank NAND bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
+ assert_param(IS_FMC_NAND_BANK(Bank));
+
+ /* Disable ECC feature */
+ if (Bank == FMC_NAND_BANK2)
+ {
+ CLEAR_BIT(Device->PCR2, FMC_PCRx_ECCEN);
+ }
+ else
+ {
+ CLEAR_BIT(Device->PCR3, FMC_PCRx_ECCEN);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables dynamically FMC_NAND ECC feature.
+ * @param Device Pointer to NAND device instance
+ * @param ECCval Pointer to ECC value
+ * @param Bank NAND bank number
+ * @param Timeout Timeout wait value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
+{
+ uint32_t tickstart = 0;
+
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
+ assert_param(IS_FMC_NAND_BANK(Bank));
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until FIFO is empty */
+ while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if ((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ if (Bank == FMC_NAND_BANK2)
+ {
+ /* Get the ECCR2 register value */
+ *ECCval = (uint32_t)Device->ECCR2;
+ }
+ else
+ {
+ /* Get the ECCR3 register value */
+ *ECCval = (uint32_t)Device->ECCR3;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_PCCARD FMC PCCARD Controller functions
+ * @brief PCCARD Controller functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use PCCARD device driver #####
+ ==============================================================================
+ [..]
+ This driver contains a set of APIs to interface with the FMC PCCARD bank in order
+ to run the PCCARD/compact flash external devices.
+
+ (+) FMC PCCARD bank reset using the function FMC_PCCARD_DeInit()
+ (+) FMC PCCARD bank control configuration using the function FMC_PCCARD_Init()
+ (+) FMC PCCARD bank common space timing configuration using the function
+ FMC_PCCARD_CommonSpace_Timing_Init()
+ (+) FMC PCCARD bank attribute space timing configuration using the function
+ FMC_PCCARD_AttributeSpace_Timing_Init()
+ (+) FMC PCCARD bank IO space timing configuration using the function
+ FMC_PCCARD_IOSpace_Timing_Init()
+
+
+@endverbatim
+ * @{
+ */
+
+/** @defgroup FMC_PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de_initialization functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the FMC PCCARD interface
+ (+) De-initialize the FMC PCCARD interface
+ (+) Configure the FMC clock and associated GPIOs
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the FMC_PCCARD device according to the specified
+ * control parameters in the FMC_PCCARD_HandleTypeDef
+ * @param Device Pointer to PCCARD device instance
+ * @param Init Pointer to PCCARD Initialization structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_PCCARD_DEVICE(Device));
+ assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
+ assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
+ assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
+
+ /* Set FMC_PCCARD device control parameters */
+ MODIFY_REG(Device->PCR4,
+ (FMC_PCRx_PTYP | FMC_PCRx_PWAITEN | FMC_PCRx_PWID |
+ FMC_PCRx_TCLR | FMC_PCRx_TAR),
+ (FMC_PCR_MEMORY_TYPE_PCCARD |
+ Init->Waitfeature |
+ FMC_NAND_PCC_MEM_BUS_WIDTH_16 |
+ (Init->TCLRSetupTime << POSITION_VAL(FMC_PCRx_TCLR)) |
+ (Init->TARSetupTime << POSITION_VAL(FMC_PCRx_TAR))));
+
+ return HAL_OK;
+
+}
+
+/**
+ * @brief Initializes the FMC_PCCARD Common space Timing according to the specified
+ * parameters in the FMC_NAND_PCC_TimingTypeDef
+ * @param Device Pointer to PCCARD device instance
+ * @param Timing Pointer to PCCARD timing structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_PCCARD_DEVICE(Device));
+ assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
+ assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
+ assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
+ assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
+
+ /* Set PCCARD timing parameters */
+ MODIFY_REG(Device->PMEM4, PMEM_CLEAR_MASK,
+ (Timing->SetupTime |
+ ((Timing->WaitSetupTime) << POSITION_VAL(FMC_PMEMx_MEMWAITx)) |
+ ((Timing->HoldSetupTime) << POSITION_VAL(FMC_PMEMx_MEMHOLDx)) |
+ ((Timing->HiZSetupTime) << POSITION_VAL(FMC_PMEMx_MEMHIZx))));
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the FMC_PCCARD Attribute space Timing according to the specified
+ * parameters in the FMC_NAND_PCC_TimingTypeDef
+ * @param Device Pointer to PCCARD device instance
+ * @param Timing Pointer to PCCARD timing structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_PCCARD_DEVICE(Device));
+ assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
+ assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
+ assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
+ assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
+
+ /* Set PCCARD timing parameters */
+ MODIFY_REG(Device->PATT4, PATT_CLEAR_MASK, \
+ (Timing->SetupTime | \
+ ((Timing->WaitSetupTime) << POSITION_VAL(FMC_PATTx_ATTWAITx)) | \
+ ((Timing->HoldSetupTime) << POSITION_VAL(FMC_PATTx_ATTHOLDx)) | \
+ ((Timing->HiZSetupTime) << POSITION_VAL(FMC_PATTx_ATTHIZx))));
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the FMC_PCCARD IO space Timing according to the specified
+ * parameters in the FMC_NAND_PCC_TimingTypeDef
+ * @param Device Pointer to PCCARD device instance
+ * @param Timing Pointer to PCCARD timing structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_PCCARD_DEVICE(Device));
+ assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
+ assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
+ assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
+ assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
+
+ /* Set FMC_PCCARD device timing parameters */
+ MODIFY_REG(Device->PIO4, PIO4_CLEAR_MASK, \
+ (Timing->SetupTime | \
+ (Timing->WaitSetupTime << POSITION_VAL(FMC_PIO4_IOWAIT4)) | \
+ (Timing->HoldSetupTime << POSITION_VAL(FMC_PIO4_IOHOLD4)) | \
+ (Timing->HiZSetupTime << POSITION_VAL(FMC_PIO4_IOHIZ4))));
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitialize the FMC_PCCARD device
+ * @param Device Pointer to PCCARD device instance
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_PCCARD_DEVICE(Device));
+
+ /* Disable the FMC_PCCARD device */
+ __FMC_PCCARD_DISABLE(Device);
+
+ /* De-initialize the FMC_PCCARD device */
+ WRITE_REG(Device->PCR4, 0x00000018);
+ WRITE_REG(Device->SR4, 0x00000040);
+ WRITE_REG(Device->PMEM4, 0xFCFCFCFC);
+ WRITE_REG(Device->PATT4, 0xFCFCFCFC);
+ WRITE_REG(Device->PIO4, 0xFCFCFCFC);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) */
+
+#endif /* FMC_BANK1 */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_ll_gpio.c b/Src/stm32f3xx_ll_gpio.c
new file mode 100644
index 0000000..9766eed
--- /dev/null
+++ b/Src/stm32f3xx_ll_gpio.c
@@ -0,0 +1,301 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_gpio.c
+ * @author MCD Application Team
+ * @brief GPIO LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_ll_gpio.h"
+#include "stm32f3xx_ll_bus.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH)
+
+/** @addtogroup GPIO_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup GPIO_LL_Private_Macros
+ * @{
+ */
+#define IS_LL_GPIO_PIN(__VALUE__) (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
+
+#define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_INPUT) ||\
+ ((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\
+ ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\
+ ((__VALUE__) == LL_GPIO_MODE_ANALOG))
+
+#define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__) (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL) ||\
+ ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN))
+
+#define IS_LL_GPIO_SPEED(__VALUE__) (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW) ||\
+ ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM) ||\
+ ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH))
+
+#define IS_LL_GPIO_PULL(__VALUE__) (((__VALUE__) == LL_GPIO_PULL_NO) ||\
+ ((__VALUE__) == LL_GPIO_PULL_UP) ||\
+ ((__VALUE__) == LL_GPIO_PULL_DOWN))
+
+#define IS_LL_GPIO_ALTERNATE(__VALUE__) (((__VALUE__) == LL_GPIO_AF_0 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_1 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_2 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_3 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_4 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_5 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_6 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_7 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_8 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_9 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_10 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_11 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_12 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_13 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_14 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_15 ))
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup GPIO_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup GPIO_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize GPIO registers (Registers restored to their default values).
+ * @param GPIOx GPIO Port
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: GPIO registers are de-initialized
+ * - ERROR: Wrong GPIO Port
+ */
+ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+
+ /* Force and Release reset on clock of GPIOx Port */
+ if (GPIOx == GPIOA)
+ {
+ LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOA);
+ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOA);
+ }
+ else if (GPIOx == GPIOB)
+ {
+ LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOB);
+ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOB);
+ }
+ else if (GPIOx == GPIOC)
+ {
+ LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOC);
+ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOC);
+ }
+#if defined(GPIOD)
+ else if (GPIOx == GPIOD)
+ {
+ LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOD);
+ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOD);
+ }
+#endif /* GPIOD */
+#if defined(GPIOE)
+ else if (GPIOx == GPIOE)
+ {
+ LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOE);
+ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOE);
+ }
+#endif /* GPIOE */
+#if defined(GPIOF)
+ else if (GPIOx == GPIOF)
+ {
+ LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOF);
+ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOF);
+ }
+#endif /* GPIOF */
+#if defined(GPIOG)
+ else if (GPIOx == GPIOG)
+ {
+ LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOG);
+ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOG);
+ }
+#endif /* GPIOG */
+#if defined(GPIOH)
+ else if (GPIOx == GPIOH)
+ {
+ LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOH);
+ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOH);
+ }
+#endif /* GPIOH */
+ else
+ {
+ status = ERROR;
+ }
+
+ return (status);
+}
+
+/**
+ * @brief Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
+ * @param GPIOx GPIO Port
+ * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
+ * that contains the configuration information for the specified GPIO peripheral.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
+ * - ERROR: Not applicable
+ */
+ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
+{
+ uint32_t pinpos = 0x00000000U;
+ uint32_t currentpin = 0x00000000U;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+ assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin));
+ assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode));
+ assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull));
+
+ /* ------------------------- Configure the port pins ---------------- */
+ /* Initialize pinpos on first pin set */
+ pinpos = POSITION_VAL(GPIO_InitStruct->Pin);
+
+ /* Configure the port pins */
+ while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U)
+ {
+ /* Get current io position */
+ currentpin = (GPIO_InitStruct->Pin) & (0x00000001U << pinpos);
+
+ if (currentpin)
+ {
+ /* Pin Mode configuration */
+ LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
+
+ if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
+ {
+ /* Check Speed mode parameters */
+ assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed));
+
+ /* Speed mode configuration */
+ LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
+ }
+
+ /* Pull-up Pull down resistor configuration*/
+ LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull);
+
+ if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)
+ {
+ /* Check Alternate parameter */
+ assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate));
+
+ /* Speed mode configuration */
+ if (POSITION_VAL(currentpin) < 0x00000008U)
+ {
+ LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate);
+ }
+ else
+ {
+ LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate);
+ }
+ }
+ }
+ pinpos++;
+ }
+
+ if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
+ {
+ /* Check Output mode parameters */
+ assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
+
+ /* Output mode configuration*/
+ LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType);
+
+ }
+ return (SUCCESS);
+}
+
+/**
+ * @brief Set each @ref LL_GPIO_InitTypeDef field to default value.
+ * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+
+void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct)
+{
+ /* Reset GPIO init structure parameters values */
+ GPIO_InitStruct->Pin = LL_GPIO_PIN_ALL;
+ GPIO_InitStruct->Mode = LL_GPIO_MODE_ANALOG;
+ GPIO_InitStruct->Speed = LL_GPIO_SPEED_FREQ_LOW;
+ GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ GPIO_InitStruct->Pull = LL_GPIO_PULL_NO;
+ GPIO_InitStruct->Alternate = LL_GPIO_AF_0;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_ll_hrtim.c b/Src/stm32f3xx_ll_hrtim.c
new file mode 100644
index 0000000..8088b64
--- /dev/null
+++ b/Src/stm32f3xx_ll_hrtim.c
@@ -0,0 +1,101 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_hrtim.c
+ * @author MCD Application Team
+ * @brief HRTIM LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_ll_hrtim.h"
+#include "stm32f3xx_ll_bus.h"
+
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined (HRTIM1)
+
+/** @addtogroup HRTIM_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup HRTIM_LL_Exported_Functions
+ * @{
+ */
+/**
+ * @brief Set HRTIM instance registers to their reset values.
+ * @param HRTIMx High Resolution Timer instance
+ * @retval ErrorStatus enumeration value:
+ * - SUCCESS: HRTIMx registers are de-initialized
+ * - ERROR: invalid HRTIMx instance
+ */
+ErrorStatus LL_HRTIM_DeInit(HRTIM_TypeDef* HRTIMx)
+{
+ ErrorStatus result = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_HRTIM_ALL_INSTANCE(HRTIMx));
+
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_HRTIM1);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_HRTIM1);
+
+ return result;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HRTIM1 */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_ll_i2c.c b/Src/stm32f3xx_ll_i2c.c
new file mode 100644
index 0000000..6d4e635
--- /dev/null
+++ b/Src/stm32f3xx_ll_i2c.c
@@ -0,0 +1,255 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_i2c.c
+ * @author MCD Application Team
+ * @brief I2C LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_ll_i2c.h"
+#include "stm32f3xx_ll_bus.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined (I2C1) || defined (I2C2) || defined (I2C3)
+
+/** @defgroup I2C_LL I2C
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup I2C_LL_Private_Macros
+ * @{
+ */
+
+#define IS_LL_I2C_PERIPHERAL_MODE(__VALUE__) (((__VALUE__) == LL_I2C_MODE_I2C) || \
+ ((__VALUE__) == LL_I2C_MODE_SMBUS_HOST) || \
+ ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE) || \
+ ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE_ARP))
+
+#define IS_LL_I2C_ANALOG_FILTER(__VALUE__) (((__VALUE__) == LL_I2C_ANALOGFILTER_ENABLE) || \
+ ((__VALUE__) == LL_I2C_ANALOGFILTER_DISABLE))
+
+#define IS_LL_I2C_DIGITAL_FILTER(__VALUE__) ((__VALUE__) <= 0x0000000FU)
+
+#define IS_LL_I2C_OWN_ADDRESS1(__VALUE__) ((__VALUE__) <= 0x000003FFU)
+
+#define IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__) (((__VALUE__) == LL_I2C_ACK) || \
+ ((__VALUE__) == LL_I2C_NACK))
+
+#define IS_LL_I2C_OWN_ADDRSIZE(__VALUE__) (((__VALUE__) == LL_I2C_OWNADDRESS1_7BIT) || \
+ ((__VALUE__) == LL_I2C_OWNADDRESS1_10BIT))
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2C_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup I2C_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize the I2C registers to their default reset values.
+ * @param I2Cx I2C Instance.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: I2C registers are de-initialized
+ * - ERROR: I2C registers are not de-initialized
+ */
+uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the I2C Instance I2Cx */
+ assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
+
+ if (I2Cx == I2C1)
+ {
+ /* Force reset of I2C clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1);
+
+ /* Release reset of I2C clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1);
+ }
+#if defined(I2C2)
+ else if (I2Cx == I2C2)
+ {
+ /* Force reset of I2C clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C2);
+
+ /* Release reset of I2C clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C2);
+
+ }
+#endif
+#if defined(I2C3)
+ else if (I2Cx == I2C3)
+ {
+ /* Force reset of I2C clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C3);
+
+ /* Release reset of I2C clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C3);
+ }
+#endif
+ else
+ {
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Initialize the I2C registers according to the specified parameters in I2C_InitStruct.
+ * @param I2Cx I2C Instance.
+ * @param I2C_InitStruct pointer to a @ref LL_I2C_InitTypeDef structure.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: I2C registers are initialized
+ * - ERROR: Not applicable
+ */
+uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
+{
+ /* Check the I2C Instance I2Cx */
+ assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
+
+ /* Check the I2C parameters from I2C_InitStruct */
+ assert_param(IS_LL_I2C_PERIPHERAL_MODE(I2C_InitStruct->PeripheralMode));
+ assert_param(IS_LL_I2C_ANALOG_FILTER(I2C_InitStruct->AnalogFilter));
+ assert_param(IS_LL_I2C_DIGITAL_FILTER(I2C_InitStruct->DigitalFilter));
+ assert_param(IS_LL_I2C_OWN_ADDRESS1(I2C_InitStruct->OwnAddress1));
+ assert_param(IS_LL_I2C_TYPE_ACKNOWLEDGE(I2C_InitStruct->TypeAcknowledge));
+ assert_param(IS_LL_I2C_OWN_ADDRSIZE(I2C_InitStruct->OwnAddrSize));
+
+ /* Disable the selected I2Cx Peripheral */
+ LL_I2C_Disable(I2Cx);
+
+ /*---------------------------- I2Cx CR1 Configuration ------------------------
+ * Configure the analog and digital noise filters with parameters :
+ * - AnalogFilter: I2C_CR1_ANFOFF bit
+ * - DigitalFilter: I2C_CR1_DNF[3:0] bits
+ */
+ LL_I2C_ConfigFilters(I2Cx, I2C_InitStruct->AnalogFilter, I2C_InitStruct->DigitalFilter);
+
+ /*---------------------------- I2Cx TIMINGR Configuration --------------------
+ * Configure the SDA setup, hold time and the SCL high, low period with parameter :
+ * - Timing: I2C_TIMINGR_PRESC[3:0], I2C_TIMINGR_SCLDEL[3:0], I2C_TIMINGR_SDADEL[3:0],
+ * I2C_TIMINGR_SCLH[7:0] and I2C_TIMINGR_SCLL[7:0] bits
+ */
+ LL_I2C_SetTiming(I2Cx, I2C_InitStruct->Timing);
+
+ /* Enable the selected I2Cx Peripheral */
+ LL_I2C_Enable(I2Cx);
+
+ /*---------------------------- I2Cx OAR1 Configuration -----------------------
+ * Disable, Configure and Enable I2Cx device own address 1 with parameters :
+ * - OwnAddress1: I2C_OAR1_OA1[9:0] bits
+ * - OwnAddrSize: I2C_OAR1_OA1MODE bit
+ */
+ LL_I2C_DisableOwnAddress1(I2Cx);
+ LL_I2C_SetOwnAddress1(I2Cx, I2C_InitStruct->OwnAddress1, I2C_InitStruct->OwnAddrSize);
+
+ /* OwnAdress1 == 0 is reserved for General Call address */
+ if (I2C_InitStruct->OwnAddress1 != 0U)
+ {
+ LL_I2C_EnableOwnAddress1(I2Cx);
+ }
+
+ /*---------------------------- I2Cx MODE Configuration -----------------------
+ * Configure I2Cx peripheral mode with parameter :
+ * - PeripheralMode: I2C_CR1_SMBDEN and I2C_CR1_SMBHEN bits
+ */
+ LL_I2C_SetMode(I2Cx, I2C_InitStruct->PeripheralMode);
+
+ /*---------------------------- I2Cx CR2 Configuration ------------------------
+ * Configure the ACKnowledge or Non ACKnowledge condition
+ * after the address receive match code or next received byte with parameter :
+ * - TypeAcknowledge: I2C_CR2_NACK bit
+ */
+ LL_I2C_AcknowledgeNextData(I2Cx, I2C_InitStruct->TypeAcknowledge);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Set each @ref LL_I2C_InitTypeDef field to default value.
+ * @param I2C_InitStruct Pointer to a @ref LL_I2C_InitTypeDef structure.
+ * @retval None
+ */
+void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct)
+{
+ /* Set I2C_InitStruct fields to default values */
+ I2C_InitStruct->PeripheralMode = LL_I2C_MODE_I2C;
+ I2C_InitStruct->Timing = 0U;
+ I2C_InitStruct->AnalogFilter = LL_I2C_ANALOGFILTER_ENABLE;
+ I2C_InitStruct->DigitalFilter = 0U;
+ I2C_InitStruct->OwnAddress1 = 0U;
+ I2C_InitStruct->TypeAcknowledge = LL_I2C_NACK;
+ I2C_InitStruct->OwnAddrSize = LL_I2C_OWNADDRESS1_7BIT;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* I2C1 || I2C2 || I2C3 */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_ll_opamp.c b/Src/stm32f3xx_ll_opamp.c
new file mode 100644
index 0000000..8fea1ce
--- /dev/null
+++ b/Src/stm32f3xx_ll_opamp.c
@@ -0,0 +1,254 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_opamp.c
+ * @author MCD Application Team
+ * @brief OPAMP LL module driver
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_ll_opamp.h"
+
+#ifdef USE_FULL_ASSERT
+ #include "stm32_assert.h"
+#else
+ #define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined (OPAMP1) || defined (OPAMP2) || defined (OPAMP3) || defined (OPAMP4)
+
+/** @addtogroup OPAMP_LL OPAMP
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/** @addtogroup OPAMP_LL_Private_Macros
+ * @{
+ */
+
+/* Check of parameters for configuration of OPAMP hierarchical scope: */
+/* OPAMP instance. */
+
+#define IS_LL_OPAMP_FUNCTIONAL_MODE(__FUNCTIONAL_MODE__) \
+ ( ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_STANDALONE) \
+ || ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_FOLLOWER) \
+ || ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_PGA) \
+ )
+
+/* Note: Comparator non-inverting inputs parameters are the same on all */
+/* OPAMP instances. */
+/* However, comparator instance kept as macro parameter for */
+/* compatibility with other STM32 families. */
+#define IS_LL_OPAMP_INPUT_NONINVERTING(__OPAMPX__, __INPUT_NONINVERTING__) \
+ ( ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_IO0) \
+ || ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_IO1) \
+ || ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_IO2) \
+ || ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_IO3) \
+ )
+
+/* Note: Comparator non-inverting inputs parameters are the same on all */
+/* OPAMP instances. */
+/* However, comparator instance kept as macro parameter for */
+/* compatibility with other STM32 families. */
+#define IS_LL_OPAMP_INPUT_INVERTING(__OPAMPX__, __INPUT_INVERTING__) \
+ ( ((__INPUT_INVERTING__) == LL_OPAMP_INPUT_INVERT_IO0) \
+ || ((__INPUT_INVERTING__) == LL_OPAMP_INPUT_INVERT_IO1) \
+ || ((__INPUT_INVERTING__) == LL_OPAMP_INPUT_INVERT_CONNECT_NO) \
+ )
+
+/**
+ * @}
+ */
+
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup OPAMP_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup OPAMP_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize registers of the selected OPAMP instance
+ * to their default reset values.
+ * @note If comparator is locked, de-initialization by software is
+ * not possible.
+ * The only way to unlock the comparator is a device hardware reset.
+ * @param OPAMPx OPAMP instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: OPAMP registers are de-initialized
+ * - ERROR: OPAMP registers are not de-initialized
+ */
+ErrorStatus LL_OPAMP_DeInit(OPAMP_TypeDef* OPAMPx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_OPAMP_ALL_INSTANCE(OPAMPx));
+
+ /* Note: Hardware constraint (refer to description of this function): */
+ /* OPAMP instance must not be locked. */
+ if(LL_OPAMP_IsLocked(OPAMPx) == 0U)
+ {
+ LL_OPAMP_WriteReg(OPAMPx, CSR, 0x00000000U);
+ }
+ else
+ {
+ /* OPAMP instance is locked: de-initialization by software is */
+ /* not possible. */
+ /* The only way to unlock the OPAMP is a device hardware reset. */
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Initialize some features of OPAMP instance.
+ * @note This function reset bit of calibration mode to ensure
+ * to be in functional mode, in order to have OPAMP parameters
+ * (inputs selection, ...) set with the corresponding OPAMP mode
+ * to be effective.
+ * @param OPAMPx OPAMP instance
+ * @param OPAMP_InitStruct Pointer to a @ref LL_OPAMP_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: OPAMP registers are initialized
+ * - ERROR: OPAMP registers are not initialized
+ */
+ErrorStatus LL_OPAMP_Init(OPAMP_TypeDef *OPAMPx, LL_OPAMP_InitTypeDef *OPAMP_InitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_OPAMP_ALL_INSTANCE(OPAMPx));
+ assert_param(IS_LL_OPAMP_FUNCTIONAL_MODE(OPAMP_InitStruct->FunctionalMode));
+ assert_param(IS_LL_OPAMP_INPUT_NONINVERTING(OPAMPx, OPAMP_InitStruct->InputNonInverting));
+
+ /* Note: OPAMP inverting input can be used with OPAMP in mode standalone */
+ /* or PGA with external capacitors for filtering circuit. */
+ /* Otherwise (OPAMP in mode follower), OPAMP inverting input is */
+ /* not used (not connected to GPIO pin). */
+ if(OPAMP_InitStruct->FunctionalMode != LL_OPAMP_MODE_FOLLOWER)
+ {
+ assert_param(IS_LL_OPAMP_INPUT_INVERTING(OPAMPx, OPAMP_InitStruct->InputInverting));
+ }
+
+ /* Note: Hardware constraint (refer to description of this function): */
+ /* OPAMP instance must not be locked. */
+ if(LL_OPAMP_IsLocked(OPAMPx) == 0U)
+ {
+ /* Configuration of OPAMP instance : */
+ /* - Functional mode */
+ /* - Input non-inverting */
+ /* - Input inverting */
+ /* Note: Bit OPAMP_CSR_CALON reset to ensure to be in functional mode. */
+ if(OPAMP_InitStruct->FunctionalMode != LL_OPAMP_MODE_FOLLOWER)
+ {
+ MODIFY_REG(OPAMPx->CSR,
+ OPAMP_CSR_CALON
+ | OPAMP_CSR_VMSEL
+ | OPAMP_CSR_VPSEL
+ ,
+ OPAMP_InitStruct->FunctionalMode
+ | OPAMP_InitStruct->InputNonInverting
+ | OPAMP_InitStruct->InputInverting
+ );
+ }
+ else
+ {
+ MODIFY_REG(OPAMPx->CSR,
+ OPAMP_CSR_CALON
+ | OPAMP_CSR_VMSEL
+ | OPAMP_CSR_VPSEL
+ ,
+ LL_OPAMP_MODE_FOLLOWER
+ | OPAMP_InitStruct->InputNonInverting
+ );
+ }
+ }
+ else
+ {
+ /* Initialization error: OPAMP instance is locked. */
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_OPAMP_InitTypeDef field to default value.
+ * @param OPAMP_InitStruct pointer to a @ref LL_OPAMP_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_OPAMP_StructInit(LL_OPAMP_InitTypeDef *OPAMP_InitStruct)
+{
+ /* Set OPAMP_InitStruct fields to default values */
+ OPAMP_InitStruct->FunctionalMode = LL_OPAMP_MODE_FOLLOWER;
+ OPAMP_InitStruct->InputNonInverting = LL_OPAMP_INPUT_NONINVERT_IO0;
+ /* Note: Parameter discarded if OPAMP in functional mode follower, */
+ /* set anyway to its default value. */
+ OPAMP_InitStruct->InputInverting = LL_OPAMP_INPUT_INVERT_CONNECT_NO;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* OPAMP1 || OPAMP2 || OPAMP3 || OPAMP4 */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_ll_pwr.c b/Src/stm32f3xx_ll_pwr.c
new file mode 100644
index 0000000..6ea12bd
--- /dev/null
+++ b/Src/stm32f3xx_ll_pwr.c
@@ -0,0 +1,101 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_pwr.c
+ * @author MCD Application Team
+ * @brief PWR LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_ll_pwr.h"
+#include "stm32f3xx_ll_bus.h"
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined(PWR)
+
+/** @defgroup PWR_LL PWR
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PWR_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup PWR_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize the PWR registers to their default reset values.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: PWR registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_PWR_DeInit(void)
+{
+ /* Force reset of PWR clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_PWR);
+
+ /* Release reset of PWR clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_PWR);
+
+ return SUCCESS;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* defined(PWR) */
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_ll_rcc.c b/Src/stm32f3xx_ll_rcc.c
new file mode 100644
index 0000000..bcf5a19
--- /dev/null
+++ b/Src/stm32f3xx_ll_rcc.c
@@ -0,0 +1,1134 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_rcc.c
+ * @author MCD Application Team
+ * @brief RCC LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_ll_rcc.h"
+#ifdef USE_FULL_ASSERT
+ #include "stm32_assert.h"
+#else
+ #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined(RCC)
+
+/** @defgroup RCC_LL RCC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @addtogroup RCC_LL_Private_Variables
+ * @{
+ */
+#if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
+const uint16_t aADCPrescTable[16] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U, 256U, 256U, 256U, 256U};
+#endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */
+#if defined(RCC_CFGR_SDPRE)
+const uint8_t aSDADCPrescTable[16] = {2U, 4U, 6U, 8U, 10U, 12U, 14U, 16U, 20U, 24U, 28U, 32U, 36U, 40U, 44U, 48U};
+#endif /* RCC_CFGR_SDPRE */
+/**
+ * @}
+ */
+
+
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup RCC_LL_Private_Macros
+ * @{
+ */
+#if defined(RCC_CFGR3_USART2SW) && defined(RCC_CFGR3_USART3SW)
+#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE))
+#elif defined(RCC_CFGR3_USART2SW) && !defined(RCC_CFGR3_USART3SW)
+#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE))
+#elif defined(RCC_CFGR3_USART3SW) && !defined(RCC_CFGR3_USART2SW)
+#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE))
+#else
+#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE))
+#endif /* RCC_CFGR3_USART2SW && RCC_CFGR3_USART3SW */
+
+#if defined(UART4) && defined(UART5)
+#define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_UART4_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_UART5_CLKSOURCE))
+#elif defined(UART4)
+#define IS_LL_RCC_UART_INSTANCE(__VALUE__) ((__VALUE__) == LL_RCC_UART4_CLKSOURCE)
+#elif defined(UART5)
+#define IS_LL_RCC_UART_INSTANCE(__VALUE__) ((__VALUE__) == LL_RCC_UART5_CLKSOURCE)
+#endif /* UART4 && UART5*/
+
+#if defined(RCC_CFGR3_I2C2SW) && defined(RCC_CFGR3_I2C3SW)
+#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))
+
+#elif defined(RCC_CFGR3_I2C2SW) && !defined(RCC_CFGR3_I2C3SW)
+#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE))
+
+#elif defined(RCC_CFGR3_I2C3SW) && !defined(RCC_CFGR3_I2C2SW)
+#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))
+
+#else
+#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2C1_CLKSOURCE)
+#endif /* RCC_CFGR3_I2C2SW && RCC_CFGR3_I2C3SW */
+
+#define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2S_CLKSOURCE)
+
+#if defined(USB)
+#define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
+#endif /* USB */
+
+#if defined(RCC_CFGR_ADCPRE)
+#define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))
+#else
+#if defined(RCC_CFGR2_ADC1PRES)
+#define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC1_CLKSOURCE))
+#elif defined(RCC_CFGR2_ADCPRE12) && defined(RCC_CFGR2_ADCPRE34)
+#define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC12_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_ADC34_CLKSOURCE))
+#else /* RCC_CFGR2_ADCPRE12 */
+#define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC12_CLKSOURCE))
+#endif /* RCC_CFGR2_ADC1PRES */
+#endif /* RCC_CFGR_ADCPRE */
+
+#if defined(RCC_CFGR_SDPRE)
+#define IS_LL_RCC_SDADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDADC_CLKSOURCE))
+#endif /* RCC_CFGR_SDPRE */
+
+#if defined(CEC)
+#define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CEC_CLKSOURCE))
+#endif /* CEC */
+
+#if defined(RCC_CFGR3_TIMSW)
+#if defined(RCC_CFGR3_TIM8SW) && defined(RCC_CFGR3_TIM15SW) && defined(RCC_CFGR3_TIM16SW) \
+ && defined(RCC_CFGR3_TIM17SW) && defined(RCC_CFGR3_TIM20SW) && defined(RCC_CFGR3_TIM2SW) \
+ && defined(RCC_CFGR3_TIM34SW)
+
+#define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_TIM2_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_TIM8_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_TIM15_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_TIM16_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_TIM17_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_TIM20_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_TIM34_CLKSOURCE))
+
+#elif !defined(RCC_CFGR3_TIM8SW) && defined(RCC_CFGR3_TIM15SW) && defined(RCC_CFGR3_TIM16SW) \
+ && defined(RCC_CFGR3_TIM17SW) && !defined(RCC_CFGR3_TIM20SW) && defined(RCC_CFGR3_TIM2SW) \
+ && defined(RCC_CFGR3_TIM34SW)
+
+#define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_TIM2_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_TIM15_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_TIM16_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_TIM17_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_TIM34_CLKSOURCE))
+
+#elif defined(RCC_CFGR3_TIM8SW) && !defined(RCC_CFGR3_TIM15SW) && !defined(RCC_CFGR3_TIM16SW) \
+ && !defined(RCC_CFGR3_TIM17SW) && !defined(RCC_CFGR3_TIM20SW) && !defined(RCC_CFGR3_TIM2SW) \
+ && !defined(RCC_CFGR3_TIM34SW)
+
+#define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_TIM8_CLKSOURCE))
+
+#elif !defined(RCC_CFGR3_TIM8SW) && defined(RCC_CFGR3_TIM15SW) && defined(RCC_CFGR3_TIM16SW) \
+ && defined(RCC_CFGR3_TIM17SW) && !defined(RCC_CFGR3_TIM20SW) && !defined(RCC_CFGR3_TIM2SW) \
+ && !defined(RCC_CFGR3_TIM34SW)
+
+#define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_TIM15_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_TIM16_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_TIM17_CLKSOURCE))
+
+#elif !defined(RCC_CFGR3_TIM8SW) && !defined(RCC_CFGR3_TIM15SW) && !defined(RCC_CFGR3_TIM16SW) \
+ && !defined(RCC_CFGR3_TIM17SW) && !defined(RCC_CFGR3_TIM20SW) && !defined(RCC_CFGR3_TIM2SW) \
+ && !defined(RCC_CFGR3_TIM34SW)
+
+#define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE))
+
+#else
+#error "Miss macro"
+#endif /* RCC_CFGR3_TIMxSW */
+#endif /* RCC_CFGR3_TIMSW */
+
+#if defined(HRTIM1)
+#define IS_LL_RCC_HRTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_HRTIM1_CLKSOURCE))
+#endif /* HRTIM1 */
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup RCC_LL_Private_Functions RCC Private functions
+ * @{
+ */
+uint32_t RCC_GetSystemClockFreq(void);
+uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
+uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
+uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
+uint32_t RCC_PLL_GetFreqDomain_SYS(void);
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RCC_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup RCC_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief Reset the RCC clock configuration to the default reset state.
+ * @note The default reset state of the clock configuration is given below:
+ * - HSI ON and used as system clock source
+ * - HSE and PLL OFF
+ * - AHB, APB1 and APB2 prescaler set to 1.
+ * - CSS, MCO OFF
+ * - All interrupts disabled
+ * @note This function doesn't modify the configuration of the
+ * - Peripheral clocks
+ * - LSI, LSE and RTC clocks
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RCC registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_RCC_DeInit(void)
+{
+ uint32_t vl_mask = 0U;
+
+ /* Set HSION bit */
+ LL_RCC_HSI_Enable();
+
+ /* Wait for HSI READY bit */
+ while(LL_RCC_HSI_IsReady() != 1U)
+ {}
+
+ /* Set HSITRIM bits to the reset value*/
+ LL_RCC_HSI_SetCalibTrimming(0x10U);
+
+ /* Reset SW, HPRE, PPRE and MCOSEL bits */
+ vl_mask = 0xFFFFFFFFU;
+ CLEAR_BIT(vl_mask, (RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2 | RCC_CFGR_MCOSEL));
+ LL_RCC_WriteReg(CFGR, vl_mask);
+
+ /* Wait till system clock source is ready */
+ while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI)
+ {}
+
+ /* Reset HSEON, CSSON, PLLON bits */
+ vl_mask = 0xFFFFFFFFU;
+ CLEAR_BIT(vl_mask, (RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON));
+ LL_RCC_WriteReg(CR, vl_mask);
+
+ /* Wait for PLL READY bit to be reset */
+ while(LL_RCC_PLL_IsReady() != 0U)
+ {}
+
+ /* Reset HSEBYP bit */
+ LL_RCC_HSE_DisableBypass();
+
+ /* Reset CFGR register */
+ LL_RCC_WriteReg(CFGR, 0x00000000U);
+
+ /* Reset CFGR2 register */
+ LL_RCC_WriteReg(CFGR2, 0x00000000U);
+
+ /* Reset CFGR3 register */
+ LL_RCC_WriteReg(CFGR3, 0x00000000U);
+
+ /* Clear pending flags */
+ vl_mask = (LL_RCC_CIR_LSIRDYC | LL_RCC_CIR_LSERDYC | LL_RCC_CIR_HSIRDYC | LL_RCC_CIR_HSERDYC | LL_RCC_CIR_PLLRDYC | LL_RCC_CIR_CSSC);
+ SET_BIT(RCC->CIR, vl_mask);
+
+ /* Disable all interrupts */
+ LL_RCC_WriteReg(CIR, 0x00000000U);
+
+ /* Clear reset flags */
+ LL_RCC_ClearResetFlags();
+
+ return SUCCESS;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_LL_EF_Get_Freq
+ * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
+ * and different peripheral clocks available on the device.
+ * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
+ * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
+ * @note If SYSCLK source is PLL, function returns values based on
+ * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
+ * @note (**) HSI_VALUE is a defined constant but the real value may vary
+ * depending on the variations in voltage and temperature.
+ * @note (***) HSE_VALUE is a defined constant, user has to ensure that
+ * HSE_VALUE is same as the real frequency of the crystal used.
+ * Otherwise, this function may have wrong result.
+ * @note The result of this function could be incorrect when using fractional
+ * value for HSE crystal.
+ * @note This function can be used by the user application to compute the
+ * baud-rate for the communication peripherals or configure other parameters.
+ * @{
+ */
+
+/**
+ * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
+ * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
+ * must be called to update structure fields. Otherwise, any
+ * configuration based on this function will be incorrect.
+ * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
+ * @retval None
+ */
+void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
+{
+ /* Get SYSCLK frequency */
+ RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
+
+ /* HCLK clock frequency */
+ RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
+
+ /* PCLK1 clock frequency */
+ RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
+
+ /* PCLK2 clock frequency */
+ RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
+}
+
+/**
+ * @brief Return USARTx clock frequency
+ * @param USARTxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_USART1_CLKSOURCE
+ * @arg @ref LL_RCC_USART2_CLKSOURCE (*)
+ * @arg @ref LL_RCC_USART3_CLKSOURCE (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval USART clock frequency (in Hz)
+ * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
+ */
+uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
+{
+ uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
+#if defined(RCC_CFGR3_USART1SW)
+ if (USARTxSource == LL_RCC_USART1_CLKSOURCE)
+ {
+ /* USART1CLK clock frequency */
+ switch (LL_RCC_GetUSARTClockSource(USARTxSource))
+ {
+ case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */
+ usart_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */
+ if (LL_RCC_HSI_IsReady())
+ {
+ usart_frequency = HSI_VALUE;
+ }
+ break;
+
+ case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */
+ if (LL_RCC_LSE_IsReady())
+ {
+ usart_frequency = LSE_VALUE;
+ }
+ break;
+
+#if defined(RCC_CFGR3_USART1SW_PCLK1)
+ case LL_RCC_USART1_CLKSOURCE_PCLK1: /* USART1 Clock is PCLK1 */
+ default:
+ usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+#else
+ case LL_RCC_USART1_CLKSOURCE_PCLK2: /* USART1 Clock is PCLK2 */
+ default:
+ usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+#endif /* RCC_CFGR3_USART1SW_PCLK1 */
+ break;
+ }
+ }
+#endif /* RCC_CFGR3_USART1SW */
+
+#if defined(RCC_CFGR3_USART2SW)
+ if (USARTxSource == LL_RCC_USART2_CLKSOURCE)
+ {
+ /* USART2CLK clock frequency */
+ switch (LL_RCC_GetUSARTClockSource(USARTxSource))
+ {
+ case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */
+ usart_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */
+ if (LL_RCC_HSI_IsReady())
+ {
+ usart_frequency = HSI_VALUE;
+ }
+ break;
+
+ case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */
+ if (LL_RCC_LSE_IsReady())
+ {
+ usart_frequency = LSE_VALUE;
+ }
+ break;
+
+ case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */
+ default:
+ usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ break;
+ }
+ }
+#endif /* RCC_CFGR3_USART2SW */
+
+#if defined(RCC_CFGR3_USART3SW)
+ if (USARTxSource == LL_RCC_USART3_CLKSOURCE)
+ {
+ /* USART3CLK clock frequency */
+ switch (LL_RCC_GetUSARTClockSource(USARTxSource))
+ {
+ case LL_RCC_USART3_CLKSOURCE_SYSCLK: /* USART3 Clock is System Clock */
+ usart_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_USART3_CLKSOURCE_HSI: /* USART3 Clock is HSI Osc. */
+ if (LL_RCC_HSI_IsReady())
+ {
+ usart_frequency = HSI_VALUE;
+ }
+ break;
+
+ case LL_RCC_USART3_CLKSOURCE_LSE: /* USART3 Clock is LSE Osc. */
+ if (LL_RCC_LSE_IsReady())
+ {
+ usart_frequency = LSE_VALUE;
+ }
+ break;
+
+ case LL_RCC_USART3_CLKSOURCE_PCLK1: /* USART3 Clock is PCLK1 */
+ default:
+ usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ break;
+ }
+ }
+
+#endif /* RCC_CFGR3_USART3SW */
+ return usart_frequency;
+}
+
+#if defined(UART4) || defined(UART5)
+/**
+ * @brief Return UARTx clock frequency
+ * @param UARTxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_UART4_CLKSOURCE
+ * @arg @ref LL_RCC_UART5_CLKSOURCE
+ * @retval UART clock frequency (in Hz)
+ * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
+ */
+uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)
+{
+ uint32_t uart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_UART_CLKSOURCE(UARTxSource));
+
+#if defined(UART4)
+ if (UARTxSource == LL_RCC_UART4_CLKSOURCE)
+ {
+ /* UART4CLK clock frequency */
+ switch (LL_RCC_GetUARTClockSource(UARTxSource))
+ {
+ case LL_RCC_UART4_CLKSOURCE_SYSCLK: /* UART4 Clock is System Clock */
+ uart_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_UART4_CLKSOURCE_HSI: /* UART4 Clock is HSI Osc. */
+ if (LL_RCC_HSI_IsReady())
+ {
+ uart_frequency = HSI_VALUE;
+ }
+ break;
+
+ case LL_RCC_UART4_CLKSOURCE_LSE: /* UART4 Clock is LSE Osc. */
+ if (LL_RCC_LSE_IsReady())
+ {
+ uart_frequency = LSE_VALUE;
+ }
+ break;
+
+ case LL_RCC_UART4_CLKSOURCE_PCLK1: /* UART4 Clock is PCLK1 */
+ default:
+ uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ break;
+ }
+ }
+#endif /* UART4 */
+
+#if defined(UART5)
+ if (UARTxSource == LL_RCC_UART5_CLKSOURCE)
+ {
+ /* UART5CLK clock frequency */
+ switch (LL_RCC_GetUARTClockSource(UARTxSource))
+ {
+ case LL_RCC_UART5_CLKSOURCE_SYSCLK: /* UART5 Clock is System Clock */
+ uart_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_UART5_CLKSOURCE_HSI: /* UART5 Clock is HSI Osc. */
+ if (LL_RCC_HSI_IsReady())
+ {
+ uart_frequency = HSI_VALUE;
+ }
+ break;
+
+ case LL_RCC_UART5_CLKSOURCE_LSE: /* UART5 Clock is LSE Osc. */
+ if (LL_RCC_LSE_IsReady())
+ {
+ uart_frequency = LSE_VALUE;
+ }
+ break;
+
+ case LL_RCC_UART5_CLKSOURCE_PCLK1: /* UART5 Clock is PCLK1 */
+ default:
+ uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ break;
+ }
+ }
+#endif /* UART5 */
+
+ return uart_frequency;
+}
+#endif /* UART4 || UART5 */
+
+/**
+ * @brief Return I2Cx clock frequency
+ * @param I2CxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_I2C1_CLKSOURCE
+ * @arg @ref LL_RCC_I2C2_CLKSOURCE (*)
+ * @arg @ref LL_RCC_I2C3_CLKSOURCE (*)
+ *
+ * (*) value not defined in all devices
+ * @retval I2C clock frequency (in Hz)
+ * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
+ */
+uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
+{
+ uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
+
+ /* I2C1 CLK clock frequency */
+ if (I2CxSource == LL_RCC_I2C1_CLKSOURCE)
+ {
+ switch (LL_RCC_GetI2CClockSource(I2CxSource))
+ {
+ case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */
+ i2c_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */
+ default:
+ if (LL_RCC_HSI_IsReady())
+ {
+ i2c_frequency = HSI_VALUE;
+ }
+ break;
+ }
+ }
+
+#if defined(RCC_CFGR3_I2C2SW)
+ /* I2C2 CLK clock frequency */
+ if (I2CxSource == LL_RCC_I2C2_CLKSOURCE)
+ {
+ switch (LL_RCC_GetI2CClockSource(I2CxSource))
+ {
+ case LL_RCC_I2C2_CLKSOURCE_SYSCLK: /* I2C2 Clock is System Clock */
+ i2c_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_I2C2_CLKSOURCE_HSI: /* I2C2 Clock is HSI Osc. */
+ default:
+ if (LL_RCC_HSI_IsReady())
+ {
+ i2c_frequency = HSI_VALUE;
+ }
+ break;
+ }
+ }
+#endif /*RCC_CFGR3_I2C2SW*/
+
+#if defined(RCC_CFGR3_I2C3SW)
+ /* I2C3 CLK clock frequency */
+ if (I2CxSource == LL_RCC_I2C3_CLKSOURCE)
+ {
+ switch (LL_RCC_GetI2CClockSource(I2CxSource))
+ {
+ case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */
+ i2c_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_I2C3_CLKSOURCE_HSI: /* I2C3 Clock is HSI Osc. */
+ default:
+ if (LL_RCC_HSI_IsReady())
+ {
+ i2c_frequency = HSI_VALUE;
+ }
+ break;
+ }
+ }
+#endif /*RCC_CFGR3_I2C3SW*/
+
+ return i2c_frequency;
+}
+
+#if defined(RCC_CFGR_I2SSRC)
+/**
+ * @brief Return I2Sx clock frequency
+ * @param I2SxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_I2S_CLKSOURCE
+ * @retval I2S clock frequency (in Hz)
+ * @arg @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used */
+uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)
+{
+ uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource));
+
+ /* I2S1CLK clock frequency */
+ switch (LL_RCC_GetI2SClockSource(I2SxSource))
+ {
+ case LL_RCC_I2S_CLKSOURCE_SYSCLK: /*!< System clock selected as I2S clock source */
+ i2s_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_I2S_CLKSOURCE_PIN: /*!< External clock selected as I2S clock source */
+ default:
+ i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
+ break;
+ }
+
+ return i2s_frequency;
+}
+#endif /* RCC_CFGR_I2SSRC */
+#if defined(USB)
+/**
+ * @brief Return USBx clock frequency
+ * @param USBxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_USB_CLKSOURCE
+ * @retval USB clock frequency (in Hz)
+ * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI48) or PLL is not ready
+ * @arg @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
+ */
+uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
+{
+ uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
+
+ /* USBCLK clock frequency */
+ switch (LL_RCC_GetUSBClockSource(USBxSource))
+ {
+ case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */
+ if (LL_RCC_PLL_IsReady())
+ {
+ usb_frequency = RCC_PLL_GetFreqDomain_SYS();
+ }
+ break;
+
+ case LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5: /* PLL clock used as USB clock source */
+ default:
+ if (LL_RCC_PLL_IsReady())
+ {
+ usb_frequency = (RCC_PLL_GetFreqDomain_SYS() * 3U) / 2U;
+ }
+ break;
+ }
+
+ return usb_frequency;
+}
+#endif /* USB */
+
+#if defined(RCC_CFGR_ADCPRE) || defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
+/**
+ * @brief Return ADCx clock frequency
+ * @param ADCxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_ADC_CLKSOURCE (*)
+ * @arg @ref LL_RCC_ADC1_CLKSOURCE (*)
+ * @arg @ref LL_RCC_ADC12_CLKSOURCE (*)
+ * @arg @ref LL_RCC_ADC34_CLKSOURCE (*)
+ *
+ * (*) value not defined in all devices
+ * @retval ADC clock frequency (in Hz)
+ */
+uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
+{
+ uint32_t adc_prescaler = 0U;
+ uint32_t adc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource));
+
+ /* Get ADC prescaler */
+ adc_prescaler = LL_RCC_GetADCClockSource(ADCxSource);
+
+#if defined(RCC_CFGR_ADCPRE)
+ /* ADC frequency = PCLK2 frequency / ADC prescaler (2, 4, 6 or 8) */
+ adc_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()))
+ / (((adc_prescaler >> POSITION_VAL(ADCxSource)) + 1U) * 2U);
+#else
+ if ((adc_prescaler & 0x0000FFFFU) == ((uint32_t)0x00000000U))
+ {
+ /* ADC frequency = HCLK frequency */
+ adc_frequency = RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq());
+ }
+ else
+ {
+ /* ADC frequency = PCLK2 frequency / ADC prescaler (from 1 to 256) */
+ adc_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()))
+ / (aADCPrescTable[((adc_prescaler & 0x0000FFFFU) >> POSITION_VAL(ADCxSource)) & 0xFU]);
+ }
+#endif /* RCC_CFGR_ADCPRE */
+
+ return adc_frequency;
+}
+#endif /*RCC_CFGR_ADCPRE || RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */
+
+#if defined(RCC_CFGR_SDPRE)
+/**
+ * @brief Return SDADCx clock frequency
+ * @param SDADCxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SDADC_CLKSOURCE
+ * @retval SDADC clock frequency (in Hz)
+ */
+uint32_t LL_RCC_GetSDADCClockFreq(uint32_t SDADCxSource)
+{
+ uint32_t sdadc_prescaler = 0U;
+ uint32_t sdadc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_SDADC_CLKSOURCE(SDADCxSource));
+
+ /* Get SDADC prescaler */
+ sdadc_prescaler = LL_RCC_GetSDADCClockSource(SDADCxSource);
+
+ /* SDADC frequency = SYSTEM frequency / SDADC prescaler (from 2 to 48) */
+ sdadc_frequency = RCC_GetSystemClockFreq()
+ / (aSDADCPrescTable[(sdadc_prescaler >> POSITION_VAL(SDADCxSource)) & 0xFU]);
+
+ return sdadc_frequency;
+}
+#endif /*RCC_CFGR_SDPRE */
+
+#if defined(CEC)
+/**
+ * @brief Return CECx clock frequency
+ * @param CECxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_CEC_CLKSOURCE
+ * @retval CEC clock frequency (in Hz)
+ * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillators (HSI or LSE) are not ready
+ */
+uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource)
+{
+ uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_CEC_CLKSOURCE(CECxSource));
+
+ /* CECCLK clock frequency */
+ switch (LL_RCC_GetCECClockSource(CECxSource))
+ {
+ case LL_RCC_CEC_CLKSOURCE_HSI_DIV244: /* HSI / 244 clock used as CEC clock source */
+ if (LL_RCC_HSI_IsReady())
+ {
+ cec_frequency = HSI_VALUE / 244U;
+ }
+ break;
+
+ case LL_RCC_CEC_CLKSOURCE_LSE: /* LSE clock used as CEC clock source */
+ default:
+ if (LL_RCC_LSE_IsReady())
+ {
+ cec_frequency = LSE_VALUE;
+ }
+ break;
+ }
+
+ return cec_frequency;
+}
+#endif /* CEC */
+
+#if defined(RCC_CFGR3_TIMSW)
+/**
+ * @brief Return TIMx clock frequency
+ * @param TIMxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_TIM1_CLKSOURCE
+ * @arg @ref LL_RCC_TIM8_CLKSOURCE (*)
+ * @arg @ref LL_RCC_TIM15_CLKSOURCE (*)
+ * @arg @ref LL_RCC_TIM16_CLKSOURCE (*)
+ * @arg @ref LL_RCC_TIM17_CLKSOURCE (*)
+ * @arg @ref LL_RCC_TIM20_CLKSOURCE (*)
+ * @arg @ref LL_RCC_TIM2_CLKSOURCE (*)
+ * @arg @ref LL_RCC_TIM34_CLKSOURCE (*)
+ *
+ * (*) value not defined in all devices
+ * @retval TIM clock frequency (in Hz)
+ */
+uint32_t LL_RCC_GetTIMClockFreq(uint32_t TIMxSource)
+{
+ uint32_t tim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_TIM_CLKSOURCE(TIMxSource));
+
+ if (TIMxSource == LL_RCC_TIM1_CLKSOURCE)
+ {
+ /* TIM1CLK clock frequency */
+ if (LL_RCC_GetTIMClockSource(LL_RCC_TIM1_CLKSOURCE) == LL_RCC_TIM1_CLKSOURCE_PCLK2)
+ {
+ /* PCLK2 used as TIM1 clock source */
+ tim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ }
+ else /* LL_RCC_TIM1_CLKSOURCE_PLL */
+ {
+ /* PLL clock used as TIM1 clock source */
+ tim_frequency = RCC_PLL_GetFreqDomain_SYS();
+ }
+ }
+
+#if defined(RCC_CFGR3_TIM8SW)
+ if (TIMxSource == LL_RCC_TIM8_CLKSOURCE)
+ {
+ /* TIM8CLK clock frequency */
+ if (LL_RCC_GetTIMClockSource(LL_RCC_TIM8_CLKSOURCE) == LL_RCC_TIM8_CLKSOURCE_PCLK2)
+ {
+ /* PCLK2 used as TIM8 clock source */
+ tim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ }
+ else /* LL_RCC_TIM8_CLKSOURCE_PLL */
+ {
+ /* PLL clock used as TIM8 clock source */
+ tim_frequency = RCC_PLL_GetFreqDomain_SYS();
+ }
+ }
+#endif /*RCC_CFGR3_TIM8SW*/
+
+#if defined(RCC_CFGR3_TIM15SW)
+ if (TIMxSource == LL_RCC_TIM15_CLKSOURCE)
+ {
+ /* TIM15CLK clock frequency */
+ if (LL_RCC_GetTIMClockSource(LL_RCC_TIM15_CLKSOURCE) == LL_RCC_TIM15_CLKSOURCE_PCLK2)
+ {
+ /* PCLK2 used as TIM15 clock source */
+ tim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ }
+ else /* LL_RCC_TIM15_CLKSOURCE_PLL */
+ {
+ /* PLL clock used as TIM15 clock source */
+ tim_frequency = RCC_PLL_GetFreqDomain_SYS();
+ }
+ }
+#endif /*RCC_CFGR3_TIM15SW*/
+
+#if defined(RCC_CFGR3_TIM16SW)
+ if (TIMxSource == LL_RCC_TIM16_CLKSOURCE)
+ {
+ /* TIM16CLK clock frequency */
+ if (LL_RCC_GetTIMClockSource(LL_RCC_TIM16_CLKSOURCE) == LL_RCC_TIM16_CLKSOURCE_PCLK2)
+ {
+ /* PCLK2 used as TIM16 clock source */
+ tim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ }
+ else /* LL_RCC_TIM16_CLKSOURCE_PLL */
+ {
+ /* PLL clock used as TIM16 clock source */
+ tim_frequency = RCC_PLL_GetFreqDomain_SYS();
+ }
+ }
+#endif /*RCC_CFGR3_TIM16SW*/
+
+#if defined(RCC_CFGR3_TIM17SW)
+ if (TIMxSource == LL_RCC_TIM17_CLKSOURCE)
+ {
+ /* TIM17CLK clock frequency */
+ if (LL_RCC_GetTIMClockSource(LL_RCC_TIM17_CLKSOURCE) == LL_RCC_TIM17_CLKSOURCE_PCLK2)
+ {
+ /* PCLK2 used as TIM17 clock source */
+ tim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ }
+ else /* LL_RCC_TIM17_CLKSOURCE_PLL */
+ {
+ /* PLL clock used as TIM17 clock source */
+ tim_frequency = RCC_PLL_GetFreqDomain_SYS();
+ }
+ }
+#endif /*RCC_CFGR3_TIM17SW*/
+
+#if defined(RCC_CFGR3_TIM20SW)
+ if (TIMxSource == LL_RCC_TIM20_CLKSOURCE)
+ {
+ /* TIM20CLK clock frequency */
+ if (LL_RCC_GetTIMClockSource(LL_RCC_TIM20_CLKSOURCE) == LL_RCC_TIM20_CLKSOURCE_PCLK2)
+ {
+ /* PCLK2 used as TIM20 clock source */
+ tim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ }
+ else /* LL_RCC_TIM20_CLKSOURCE_PLL */
+ {
+ /* PLL clock used as TIM20 clock source */
+ tim_frequency = RCC_PLL_GetFreqDomain_SYS();
+ }
+ }
+#endif /*RCC_CFGR3_TIM20SW*/
+
+#if defined(RCC_CFGR3_TIM2SW)
+ if (TIMxSource == LL_RCC_TIM2_CLKSOURCE)
+ {
+ /* TIM2CLK clock frequency */
+ if (LL_RCC_GetTIMClockSource(LL_RCC_TIM2_CLKSOURCE) == LL_RCC_TIM2_CLKSOURCE_PCLK1)
+ {
+ /* PCLK1 used as TIM2 clock source */
+ tim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ }
+ else /* LL_RCC_TIM2_CLKSOURCE_PLL */
+ {
+ /* PLL clock used as TIM2 clock source */
+ tim_frequency = RCC_PLL_GetFreqDomain_SYS();
+ }
+ }
+#endif /*RCC_CFGR3_TIM2SW*/
+
+#if defined(RCC_CFGR3_TIM34SW)
+ if (TIMxSource == LL_RCC_TIM34_CLKSOURCE)
+ {
+ /* TIM3/4 CLK clock frequency */
+ if (LL_RCC_GetTIMClockSource(LL_RCC_TIM34_CLKSOURCE) == LL_RCC_TIM34_CLKSOURCE_PCLK1)
+ {
+ /* PCLK1 used as TIM3/4 clock source */
+ tim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ }
+ else /* LL_RCC_TIM34_CLKSOURCE_PLL */
+ {
+ /* PLL clock used as TIM3/4 clock source */
+ tim_frequency = RCC_PLL_GetFreqDomain_SYS();
+ }
+ }
+#endif /*RCC_CFGR3_TIM34SW*/
+
+ return tim_frequency;
+}
+#endif /*RCC_CFGR3_TIMSW*/
+
+#if defined(HRTIM1)
+/**
+ * @brief Return HRTIMx clock frequency
+ * @param HRTIMxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_HRTIM1_CLKSOURCE
+ * @retval HRTIM clock frequency (in Hz)
+ */
+uint32_t LL_RCC_GetHRTIMClockFreq(uint32_t HRTIMxSource)
+{
+ uint32_t hrtim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_HRTIM_CLKSOURCE(HRTIMxSource));
+
+ /* HRTIM1CLK clock frequency */
+ if (LL_RCC_GetHRTIMClockSource(LL_RCC_HRTIM1_CLKSOURCE) == LL_RCC_HRTIM1_CLKSOURCE_PCLK2)
+ {
+ /* PCLK2 used as HRTIM1 clock source */
+ hrtim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ }
+ else /* LL_RCC_HRTIM1_CLKSOURCE_PLL */
+ {
+ /* PLL clock used as HRTIM1 clock source */
+ hrtim_frequency = RCC_PLL_GetFreqDomain_SYS();
+ }
+
+ return hrtim_frequency;
+}
+#endif /* HRTIM1 */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_LL_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Return SYSTEM clock frequency
+ * @retval SYSTEM clock frequency (in Hz)
+ */
+uint32_t RCC_GetSystemClockFreq(void)
+{
+ uint32_t frequency = 0U;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ switch (LL_RCC_GetSysClkSource())
+ {
+ case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
+ frequency = HSI_VALUE;
+ break;
+
+ case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
+ frequency = HSE_VALUE;
+ break;
+
+ case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */
+ frequency = RCC_PLL_GetFreqDomain_SYS();
+ break;
+
+ default:
+ frequency = HSI_VALUE;
+ break;
+ }
+
+ return frequency;
+}
+
+/**
+ * @brief Return HCLK clock frequency
+ * @param SYSCLK_Frequency SYSCLK clock frequency
+ * @retval HCLK clock frequency (in Hz)
+ */
+uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
+{
+ /* HCLK clock frequency */
+ return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
+}
+
+/**
+ * @brief Return PCLK1 clock frequency
+ * @param HCLK_Frequency HCLK clock frequency
+ * @retval PCLK1 clock frequency (in Hz)
+ */
+uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
+{
+ /* PCLK1 clock frequency */
+ return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
+}
+
+/**
+ * @brief Return PCLK2 clock frequency
+ * @param HCLK_Frequency HCLK clock frequency
+ * @retval PCLK2 clock frequency (in Hz)
+ */
+uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
+{
+ /* PCLK2 clock frequency */
+ return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
+}
+
+/**
+ * @brief Return PLL clock frequency used for system domain
+ * @retval PLL clock frequency (in Hz)
+ */
+uint32_t RCC_PLL_GetFreqDomain_SYS(void)
+{
+ uint32_t pllinputfreq = 0U, pllsource = 0U;
+
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL divider) * PLL Multiplicator */
+
+ /* Get PLL source */
+ pllsource = LL_RCC_PLL_GetMainSource();
+
+ switch (pllsource)
+ {
+#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
+ case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
+ pllinputfreq = HSI_VALUE;
+#else
+ case LL_RCC_PLLSOURCE_HSI_DIV_2: /* HSI used as PLL clock source */
+ pllinputfreq = HSI_VALUE / 2U;
+#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
+ break;
+
+ case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
+ pllinputfreq = HSE_VALUE;
+ break;
+
+ default:
+#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
+ pllinputfreq = HSI_VALUE;
+#else
+ pllinputfreq = HSI_VALUE / 2U;
+#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
+ break;
+ }
+#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
+ return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator(), LL_RCC_PLL_GetPrediv());
+#else
+ return __LL_RCC_CALC_PLLCLK_FREQ((pllinputfreq / (LL_RCC_PLL_GetPrediv() + 1U)), LL_RCC_PLL_GetMultiplicator());
+#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(RCC) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_ll_rtc.c b/Src/stm32f3xx_ll_rtc.c
new file mode 100644
index 0000000..c26cc8d
--- /dev/null
+++ b/Src/stm32f3xx_ll_rtc.c
@@ -0,0 +1,892 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_rtc.c
+ * @author MCD Application Team
+ * @brief RTC LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_ll_rtc.h"
+#include "stm32f3xx_ll_cortex.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined(RTC)
+
+/** @addtogroup RTC_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup RTC_LL_Private_Constants
+ * @{
+ */
+/* Default values used for prescaler */
+#define RTC_ASYNCH_PRESC_DEFAULT 0x0000007FU
+#define RTC_SYNCH_PRESC_DEFAULT 0x000000FFU
+
+/* Values used for timeout */
+#define RTC_INITMODE_TIMEOUT 1000U /* 1s when tick set to 1ms */
+#define RTC_SYNCHRO_TIMEOUT 1000U /* 1s when tick set to 1ms */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup RTC_LL_Private_Macros
+ * @{
+ */
+
+#define IS_LL_RTC_HOURFORMAT(__VALUE__) (((__VALUE__) == LL_RTC_HOURFORMAT_24HOUR) \
+ || ((__VALUE__) == LL_RTC_HOURFORMAT_AMPM))
+
+#define IS_LL_RTC_ASYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FU)
+
+#define IS_LL_RTC_SYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FFFU)
+
+#define IS_LL_RTC_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_FORMAT_BIN) \
+ || ((__VALUE__) == LL_RTC_FORMAT_BCD))
+
+#define IS_LL_RTC_TIME_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_TIME_FORMAT_AM_OR_24) \
+ || ((__VALUE__) == LL_RTC_TIME_FORMAT_PM))
+
+#define IS_LL_RTC_HOUR12(__HOUR__) (((__HOUR__) > 0U) && ((__HOUR__) <= 12U))
+#define IS_LL_RTC_HOUR24(__HOUR__) ((__HOUR__) <= 23U)
+#define IS_LL_RTC_MINUTES(__MINUTES__) ((__MINUTES__) <= 59U)
+#define IS_LL_RTC_SECONDS(__SECONDS__) ((__SECONDS__) <= 59U)
+
+#define IS_LL_RTC_WEEKDAY(__VALUE__) (((__VALUE__) == LL_RTC_WEEKDAY_MONDAY) \
+ || ((__VALUE__) == LL_RTC_WEEKDAY_TUESDAY) \
+ || ((__VALUE__) == LL_RTC_WEEKDAY_WEDNESDAY) \
+ || ((__VALUE__) == LL_RTC_WEEKDAY_THURSDAY) \
+ || ((__VALUE__) == LL_RTC_WEEKDAY_FRIDAY) \
+ || ((__VALUE__) == LL_RTC_WEEKDAY_SATURDAY) \
+ || ((__VALUE__) == LL_RTC_WEEKDAY_SUNDAY))
+
+#define IS_LL_RTC_DAY(__DAY__) (((__DAY__) >= 1U) && ((__DAY__) <= 31U))
+
+#define IS_LL_RTC_MONTH(__VALUE__) (((__VALUE__) == LL_RTC_MONTH_JANUARY) \
+ || ((__VALUE__) == LL_RTC_MONTH_FEBRUARY) \
+ || ((__VALUE__) == LL_RTC_MONTH_MARCH) \
+ || ((__VALUE__) == LL_RTC_MONTH_APRIL) \
+ || ((__VALUE__) == LL_RTC_MONTH_MAY) \
+ || ((__VALUE__) == LL_RTC_MONTH_JUNE) \
+ || ((__VALUE__) == LL_RTC_MONTH_JULY) \
+ || ((__VALUE__) == LL_RTC_MONTH_AUGUST) \
+ || ((__VALUE__) == LL_RTC_MONTH_SEPTEMBER) \
+ || ((__VALUE__) == LL_RTC_MONTH_OCTOBER) \
+ || ((__VALUE__) == LL_RTC_MONTH_NOVEMBER) \
+ || ((__VALUE__) == LL_RTC_MONTH_DECEMBER))
+
+#define IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U)
+
+#define IS_LL_RTC_ALMA_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMA_MASK_NONE) \
+ || ((__VALUE__) == LL_RTC_ALMA_MASK_DATEWEEKDAY) \
+ || ((__VALUE__) == LL_RTC_ALMA_MASK_HOURS) \
+ || ((__VALUE__) == LL_RTC_ALMA_MASK_MINUTES) \
+ || ((__VALUE__) == LL_RTC_ALMA_MASK_SECONDS) \
+ || ((__VALUE__) == LL_RTC_ALMA_MASK_ALL))
+
+#define IS_LL_RTC_ALMB_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMB_MASK_NONE) \
+ || ((__VALUE__) == LL_RTC_ALMB_MASK_DATEWEEKDAY) \
+ || ((__VALUE__) == LL_RTC_ALMB_MASK_HOURS) \
+ || ((__VALUE__) == LL_RTC_ALMB_MASK_MINUTES) \
+ || ((__VALUE__) == LL_RTC_ALMB_MASK_SECONDS) \
+ || ((__VALUE__) == LL_RTC_ALMB_MASK_ALL))
+
+
+#define IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) || \
+ ((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY))
+
+#define IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) || \
+ ((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY))
+
+
+/**
+ * @}
+ */
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RTC_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup RTC_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-Initializes the RTC registers to their default reset values.
+ * @note This function doesn't reset the RTC Clock source and RTC Backup Data
+ * registers.
+ * @param RTCx RTC Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC registers are de-initialized
+ * - ERROR: RTC registers are not de-initialized
+ */
+ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx)
+{
+ ErrorStatus status = ERROR;
+
+ /* Check the parameter */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+
+ /* Disable the write protection for RTC registers */
+ LL_RTC_DisableWriteProtection(RTCx);
+
+ /* Set Initialization mode */
+ if (LL_RTC_EnterInitMode(RTCx) != ERROR)
+ {
+ /* Reset TR, DR and CR registers */
+ LL_RTC_WriteReg(RTCx, TR, 0x00000000U);
+#if defined(RTC_WAKEUP_SUPPORT)
+ LL_RTC_WriteReg(RTCx, WUTR, RTC_WUTR_WUT);
+#endif /* RTC_WAKEUP_SUPPORT */
+ LL_RTC_WriteReg(RTCx, DR , (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0));
+ /* Reset All CR bits except CR[2:0] */
+#if defined(RTC_WAKEUP_SUPPORT)
+ LL_RTC_WriteReg(RTCx, CR, (LL_RTC_ReadReg(RTCx, CR) & RTC_CR_WUCKSEL));
+#else
+ LL_RTC_WriteReg(RTCx, CR, 0x00000000U);
+#endif /* RTC_WAKEUP_SUPPORT */
+ LL_RTC_WriteReg(RTCx, PRER, (RTC_PRER_PREDIV_A | RTC_SYNCH_PRESC_DEFAULT));
+ LL_RTC_WriteReg(RTCx, ALRMAR, 0x00000000U);
+ LL_RTC_WriteReg(RTCx, ALRMBR, 0x00000000U);
+ LL_RTC_WriteReg(RTCx, SHIFTR, 0x00000000U);
+ LL_RTC_WriteReg(RTCx, CALR, 0x00000000U);
+ LL_RTC_WriteReg(RTCx, ALRMASSR, 0x00000000U);
+ LL_RTC_WriteReg(RTCx, ALRMBSSR, 0x00000000U);
+
+ /* Reset ISR register and exit initialization mode */
+ LL_RTC_WriteReg(RTCx, ISR, 0x00000000U);
+
+ /* Reset Tamper and alternate functions configuration register */
+ LL_RTC_WriteReg(RTCx, TAFCR, 0x00000000U);
+
+ /* Wait till the RTC RSF flag is set */
+ status = LL_RTC_WaitForSynchro(RTCx);
+ }
+
+ /* Enable the write protection for RTC registers */
+ LL_RTC_EnableWriteProtection(RTCx);
+
+ return status;
+}
+
+/**
+ * @brief Initializes the RTC registers according to the specified parameters
+ * in RTC_InitStruct.
+ * @param RTCx RTC Instance
+ * @param RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure that contains
+ * the configuration information for the RTC peripheral.
+ * @note The RTC Prescaler register is write protected and can be written in
+ * initialization mode only.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC registers are initialized
+ * - ERROR: RTC registers are not initialized
+ */
+ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct)
+{
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+ assert_param(IS_LL_RTC_HOURFORMAT(RTC_InitStruct->HourFormat));
+ assert_param(IS_LL_RTC_ASYNCH_PREDIV(RTC_InitStruct->AsynchPrescaler));
+ assert_param(IS_LL_RTC_SYNCH_PREDIV(RTC_InitStruct->SynchPrescaler));
+
+ /* Disable the write protection for RTC registers */
+ LL_RTC_DisableWriteProtection(RTCx);
+
+ /* Set Initialization mode */
+ if (LL_RTC_EnterInitMode(RTCx) != ERROR)
+ {
+ /* Set Hour Format */
+ LL_RTC_SetHourFormat(RTCx, RTC_InitStruct->HourFormat);
+
+ /* Configure Synchronous and Asynchronous prescaler factor */
+ LL_RTC_SetSynchPrescaler(RTCx, RTC_InitStruct->SynchPrescaler);
+ LL_RTC_SetAsynchPrescaler(RTCx, RTC_InitStruct->AsynchPrescaler);
+
+ /* Exit Initialization mode */
+ LL_RTC_DisableInitMode(RTCx);
+
+ status = SUCCESS;
+ }
+ /* Enable the write protection for RTC registers */
+ LL_RTC_EnableWriteProtection(RTCx);
+
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_RTC_InitTypeDef field to default value.
+ * @param RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure which will be initialized.
+ * @retval None
+ */
+void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct)
+{
+ /* Set RTC_InitStruct fields to default values */
+ RTC_InitStruct->HourFormat = LL_RTC_HOURFORMAT_24HOUR;
+ RTC_InitStruct->AsynchPrescaler = RTC_ASYNCH_PRESC_DEFAULT;
+ RTC_InitStruct->SynchPrescaler = RTC_SYNCH_PRESC_DEFAULT;
+}
+
+/**
+ * @brief Set the RTC current time.
+ * @param RTCx RTC Instance
+ * @param RTC_Format This parameter can be one of the following values:
+ * @arg @ref LL_RTC_FORMAT_BIN
+ * @arg @ref LL_RTC_FORMAT_BCD
+ * @param RTC_TimeStruct pointer to a RTC_TimeTypeDef structure that contains
+ * the time configuration information for the RTC.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC Time register is configured
+ * - ERROR: RTC Time register is not configured
+ */
+ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct)
+{
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+ assert_param(IS_LL_RTC_FORMAT(RTC_Format));
+
+ if (RTC_Format == LL_RTC_FORMAT_BIN)
+ {
+ if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+ {
+ assert_param(IS_LL_RTC_HOUR12(RTC_TimeStruct->Hours));
+ assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat));
+ }
+ else
+ {
+ RTC_TimeStruct->TimeFormat = 0x00U;
+ assert_param(IS_LL_RTC_HOUR24(RTC_TimeStruct->Hours));
+ }
+ assert_param(IS_LL_RTC_MINUTES(RTC_TimeStruct->Minutes));
+ assert_param(IS_LL_RTC_SECONDS(RTC_TimeStruct->Seconds));
+ }
+ else
+ {
+ if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+ {
+ assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)));
+ assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat));
+ }
+ else
+ {
+ RTC_TimeStruct->TimeFormat = 0x00U;
+ assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)));
+ }
+ assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Minutes)));
+ assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Seconds)));
+ }
+
+ /* Disable the write protection for RTC registers */
+ LL_RTC_DisableWriteProtection(RTCx);
+
+ /* Set Initialization mode */
+ if (LL_RTC_EnterInitMode(RTCx) != ERROR)
+ {
+ /* Check the input parameters format */
+ if (RTC_Format != LL_RTC_FORMAT_BIN)
+ {
+ LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, RTC_TimeStruct->Hours,
+ RTC_TimeStruct->Minutes, RTC_TimeStruct->Seconds);
+ }
+ else
+ {
+ LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Hours),
+ __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Minutes),
+ __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Seconds));
+ }
+
+ /* Exit Initialization mode */
+ LL_RTC_DisableInitMode(RTC);
+
+ /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+ if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U)
+ {
+ status = LL_RTC_WaitForSynchro(RTCx);
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+ /* Enable the write protection for RTC registers */
+ LL_RTC_EnableWriteProtection(RTCx);
+
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec).
+ * @param RTC_TimeStruct pointer to a @ref LL_RTC_TimeTypeDef structure which will be initialized.
+ * @retval None
+ */
+void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct)
+{
+ /* Time = 00h:00min:00sec */
+ RTC_TimeStruct->TimeFormat = LL_RTC_TIME_FORMAT_AM_OR_24;
+ RTC_TimeStruct->Hours = 0U;
+ RTC_TimeStruct->Minutes = 0U;
+ RTC_TimeStruct->Seconds = 0U;
+}
+
+/**
+ * @brief Set the RTC current date.
+ * @param RTCx RTC Instance
+ * @param RTC_Format This parameter can be one of the following values:
+ * @arg @ref LL_RTC_FORMAT_BIN
+ * @arg @ref LL_RTC_FORMAT_BCD
+ * @param RTC_DateStruct pointer to a RTC_DateTypeDef structure that contains
+ * the date configuration information for the RTC.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC Day register is configured
+ * - ERROR: RTC Day register is not configured
+ */
+ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct)
+{
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+ assert_param(IS_LL_RTC_FORMAT(RTC_Format));
+
+ if ((RTC_Format == LL_RTC_FORMAT_BIN) && ((RTC_DateStruct->Month & 0x10U) == 0x10U))
+ {
+ RTC_DateStruct->Month = (RTC_DateStruct->Month & (uint32_t)~(0x10U)) + 0x0AU;
+ }
+ if (RTC_Format == LL_RTC_FORMAT_BIN)
+ {
+ assert_param(IS_LL_RTC_YEAR(RTC_DateStruct->Year));
+ assert_param(IS_LL_RTC_MONTH(RTC_DateStruct->Month));
+ assert_param(IS_LL_RTC_DAY(RTC_DateStruct->Day));
+ }
+ else
+ {
+ assert_param(IS_LL_RTC_YEAR(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Year)));
+ assert_param(IS_LL_RTC_MONTH(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Month)));
+ assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Day)));
+ }
+ assert_param(IS_LL_RTC_WEEKDAY(RTC_DateStruct->WeekDay));
+
+ /* Disable the write protection for RTC registers */
+ LL_RTC_DisableWriteProtection(RTCx);
+
+ /* Set Initialization mode */
+ if (LL_RTC_EnterInitMode(RTCx) != ERROR)
+ {
+ /* Check the input parameters format */
+ if (RTC_Format != LL_RTC_FORMAT_BIN)
+ {
+ LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, RTC_DateStruct->Day, RTC_DateStruct->Month, RTC_DateStruct->Year);
+ }
+ else
+ {
+ LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Day),
+ __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Month), __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Year));
+ }
+
+ /* Exit Initialization mode */
+ LL_RTC_DisableInitMode(RTC);
+
+ /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+ if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U)
+ {
+ status = LL_RTC_WaitForSynchro(RTCx);
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+ /* Enable the write protection for RTC registers */
+ LL_RTC_EnableWriteProtection(RTCx);
+
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00)
+ * @param RTC_DateStruct pointer to a @ref LL_RTC_DateTypeDef structure which will be initialized.
+ * @retval None
+ */
+void LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct)
+{
+ /* Monday, January 01 xx00 */
+ RTC_DateStruct->WeekDay = LL_RTC_WEEKDAY_MONDAY;
+ RTC_DateStruct->Day = 1U;
+ RTC_DateStruct->Month = LL_RTC_MONTH_JANUARY;
+ RTC_DateStruct->Year = 0U;
+}
+
+/**
+ * @brief Set the RTC Alarm A.
+ * @note The Alarm register can only be written when the corresponding Alarm
+ * is disabled (Use @ref LL_RTC_ALMA_Disable function).
+ * @param RTCx RTC Instance
+ * @param RTC_Format This parameter can be one of the following values:
+ * @arg @ref LL_RTC_FORMAT_BIN
+ * @arg @ref LL_RTC_FORMAT_BCD
+ * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that
+ * contains the alarm configuration parameters.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ALARMA registers are configured
+ * - ERROR: ALARMA registers are not configured
+ */
+ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+ assert_param(IS_LL_RTC_FORMAT(RTC_Format));
+ assert_param(IS_LL_RTC_ALMA_MASK(RTC_AlarmStruct->AlarmMask));
+ assert_param(IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel));
+
+ if (RTC_Format == LL_RTC_FORMAT_BIN)
+ {
+ if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+ {
+ assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours));
+ assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
+ }
+ else
+ {
+ RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
+ assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours));
+ }
+ assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes));
+ assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds));
+
+ if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
+ {
+ assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay));
+ }
+ else
+ {
+ assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay));
+ }
+ }
+ else
+ {
+ if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+ {
+ assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
+ assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
+ }
+ else
+ {
+ RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
+ assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
+ }
+
+ assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes)));
+ assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds)));
+
+ if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
+ {
+ assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
+ }
+ else
+ {
+ assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
+ }
+ }
+
+ /* Disable the write protection for RTC registers */
+ LL_RTC_DisableWriteProtection(RTCx);
+
+ /* Select weekday selection */
+ if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
+ {
+ /* Set the date for ALARM */
+ LL_RTC_ALMA_DisableWeekday(RTCx);
+ if (RTC_Format != LL_RTC_FORMAT_BIN)
+ {
+ LL_RTC_ALMA_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
+ }
+ else
+ {
+ LL_RTC_ALMA_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay));
+ }
+ }
+ else
+ {
+ /* Set the week day for ALARM */
+ LL_RTC_ALMA_EnableWeekday(RTCx);
+ LL_RTC_ALMA_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
+ }
+
+ /* Configure the Alarm register */
+ if (RTC_Format != LL_RTC_FORMAT_BIN)
+ {
+ LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime.Hours,
+ RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds);
+ }
+ else
+ {
+ LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat,
+ __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours),
+ __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes),
+ __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds));
+ }
+ /* Set ALARM mask */
+ LL_RTC_ALMA_SetMask(RTCx, RTC_AlarmStruct->AlarmMask);
+
+ /* Enable the write protection for RTC registers */
+ LL_RTC_EnableWriteProtection(RTCx);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Set the RTC Alarm B.
+ * @note The Alarm register can only be written when the corresponding Alarm
+ * is disabled (@ref LL_RTC_ALMB_Disable function).
+ * @param RTCx RTC Instance
+ * @param RTC_Format This parameter can be one of the following values:
+ * @arg @ref LL_RTC_FORMAT_BIN
+ * @arg @ref LL_RTC_FORMAT_BCD
+ * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that
+ * contains the alarm configuration parameters.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ALARMB registers are configured
+ * - ERROR: ALARMB registers are not configured
+ */
+ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+ assert_param(IS_LL_RTC_FORMAT(RTC_Format));
+ assert_param(IS_LL_RTC_ALMB_MASK(RTC_AlarmStruct->AlarmMask));
+ assert_param(IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel));
+
+ if (RTC_Format == LL_RTC_FORMAT_BIN)
+ {
+ if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+ {
+ assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours));
+ assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
+ }
+ else
+ {
+ RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
+ assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours));
+ }
+ assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes));
+ assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds));
+
+ if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
+ {
+ assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay));
+ }
+ else
+ {
+ assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay));
+ }
+ }
+ else
+ {
+ if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+ {
+ assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
+ assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
+ }
+ else
+ {
+ RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
+ assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
+ }
+
+ assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes)));
+ assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds)));
+
+ if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
+ {
+ assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
+ }
+ else
+ {
+ assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
+ }
+ }
+
+ /* Disable the write protection for RTC registers */
+ LL_RTC_DisableWriteProtection(RTCx);
+
+ /* Select weekday selection */
+ if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
+ {
+ /* Set the date for ALARM */
+ LL_RTC_ALMB_DisableWeekday(RTCx);
+ if (RTC_Format != LL_RTC_FORMAT_BIN)
+ {
+ LL_RTC_ALMB_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
+ }
+ else
+ {
+ LL_RTC_ALMB_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay));
+ }
+ }
+ else
+ {
+ /* Set the week day for ALARM */
+ LL_RTC_ALMB_EnableWeekday(RTCx);
+ LL_RTC_ALMB_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
+ }
+
+ /* Configure the Alarm register */
+ if (RTC_Format != LL_RTC_FORMAT_BIN)
+ {
+ LL_RTC_ALMB_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime.Hours,
+ RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds);
+ }
+ else
+ {
+ LL_RTC_ALMB_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat,
+ __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours),
+ __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes),
+ __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds));
+ }
+ /* Set ALARM mask */
+ LL_RTC_ALMB_SetMask(RTCx, RTC_AlarmStruct->AlarmMask);
+
+ /* Enable the write protection for RTC registers */
+ LL_RTC_EnableWriteProtection(RTCx);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec /
+ * Day = 1st day of the month/Mask = all fields are masked).
+ * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized.
+ * @retval None
+ */
+void LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
+{
+ /* Alarm Time Settings : Time = 00h:00mn:00sec */
+ RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMA_TIME_FORMAT_AM;
+ RTC_AlarmStruct->AlarmTime.Hours = 0U;
+ RTC_AlarmStruct->AlarmTime.Minutes = 0U;
+ RTC_AlarmStruct->AlarmTime.Seconds = 0U;
+
+ /* Alarm Day Settings : Day = 1st day of the month */
+ RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMA_DATEWEEKDAYSEL_DATE;
+ RTC_AlarmStruct->AlarmDateWeekDay = 1U;
+
+ /* Alarm Masks Settings : Mask = all fields are not masked */
+ RTC_AlarmStruct->AlarmMask = LL_RTC_ALMA_MASK_NONE;
+}
+
+/**
+ * @brief Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec /
+ * Day = 1st day of the month/Mask = all fields are masked).
+ * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized.
+ * @retval None
+ */
+void LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
+{
+ /* Alarm Time Settings : Time = 00h:00mn:00sec */
+ RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMB_TIME_FORMAT_AM;
+ RTC_AlarmStruct->AlarmTime.Hours = 0U;
+ RTC_AlarmStruct->AlarmTime.Minutes = 0U;
+ RTC_AlarmStruct->AlarmTime.Seconds = 0U;
+
+ /* Alarm Day Settings : Day = 1st day of the month */
+ RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMB_DATEWEEKDAYSEL_DATE;
+ RTC_AlarmStruct->AlarmDateWeekDay = 1U;
+
+ /* Alarm Masks Settings : Mask = all fields are not masked */
+ RTC_AlarmStruct->AlarmMask = LL_RTC_ALMB_MASK_NONE;
+}
+
+/**
+ * @brief Enters the RTC Initialization mode.
+ * @note The RTC Initialization mode is write protected, use the
+ * @ref LL_RTC_DisableWriteProtection before calling this function.
+ * @param RTCx RTC Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC is in Init mode
+ * - ERROR: RTC is not in Init mode
+ */
+ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx)
+{
+ __IO uint32_t timeout = RTC_INITMODE_TIMEOUT;
+ ErrorStatus status = SUCCESS;
+ uint32_t tmp = 0U;
+
+ /* Check the parameter */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+
+ /* Check if the Initialization mode is set */
+ if (LL_RTC_IsActiveFlag_INIT(RTCx) == 0U)
+ {
+ /* Set the Initialization mode */
+ LL_RTC_EnableInitMode(RTCx);
+
+ /* Wait till RTC is in INIT state and if Time out is reached exit */
+ tmp = LL_RTC_IsActiveFlag_INIT(RTCx);
+ while ((timeout != 0U) && (tmp != 1U))
+ {
+ if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
+ {
+ timeout --;
+ }
+ tmp = LL_RTC_IsActiveFlag_INIT(RTCx);
+ if (timeout == 0U)
+ {
+ status = ERROR;
+ }
+ }
+ }
+ return status;
+}
+
+/**
+ * @brief Exit the RTC Initialization mode.
+ * @note When the initialization sequence is complete, the calendar restarts
+ * counting after 4 RTCCLK cycles.
+ * @note The RTC Initialization mode is write protected, use the
+ * @ref LL_RTC_DisableWriteProtection before calling this function.
+ * @param RTCx RTC Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC exited from in Init mode
+ * - ERROR: Not applicable
+ */
+ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx)
+{
+ /* Check the parameter */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+
+ /* Disable initialization mode */
+ LL_RTC_DisableInitMode(RTCx);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are
+ * synchronized with RTC APB clock.
+ * @note The RTC Resynchronization mode is write protected, use the
+ * @ref LL_RTC_DisableWriteProtection before calling this function.
+ * @note To read the calendar through the shadow registers after Calendar
+ * initialization, calendar update or after wakeup from low power modes
+ * the software must first clear the RSF flag.
+ * The software must then wait until it is set again before reading
+ * the calendar, which means that the calendar registers have been
+ * correctly copied into the RTC_TR and RTC_DR shadow registers.
+ * @param RTCx RTC Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC registers are synchronised
+ * - ERROR: RTC registers are not synchronised
+ */
+ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx)
+{
+ __IO uint32_t timeout = RTC_SYNCHRO_TIMEOUT;
+ ErrorStatus status = SUCCESS;
+ uint32_t tmp = 0U;
+
+ /* Check the parameter */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+
+ /* Clear RSF flag */
+ LL_RTC_ClearFlag_RS(RTCx);
+
+ /* Wait the registers to be synchronised */
+ tmp = LL_RTC_IsActiveFlag_RS(RTCx);
+ while ((timeout != 0U) && (tmp != 0U))
+ {
+ if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
+ {
+ timeout--;
+ }
+ tmp = LL_RTC_IsActiveFlag_RS(RTCx);
+ if (timeout == 0U)
+ {
+ status = ERROR;
+ }
+ }
+
+ if (status != ERROR)
+ {
+ timeout = RTC_SYNCHRO_TIMEOUT;
+ tmp = LL_RTC_IsActiveFlag_RS(RTCx);
+ while ((timeout != 0U) && (tmp != 1U))
+ {
+ if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
+ {
+ timeout--;
+ }
+ tmp = LL_RTC_IsActiveFlag_RS(RTCx);
+ if (timeout == 0U)
+ {
+ status = ERROR;
+ }
+ }
+ }
+
+ return (status);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(RTC) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_ll_spi.c b/Src/stm32f3xx_ll_spi.c
new file mode 100644
index 0000000..db2e222
--- /dev/null
+++ b/Src/stm32f3xx_ll_spi.c
@@ -0,0 +1,635 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_spi.c
+ * @author MCD Application Team
+ * @brief SPI LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_ll_spi.h"
+#include "stm32f3xx_ll_bus.h"
+#include "stm32f3xx_ll_rcc.h"
+
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4)
+
+/** @addtogroup SPI_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SPI_LL_Private_Constants SPI Private Constants
+ * @{
+ */
+/* SPI registers Masks */
+#define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \
+ SPI_CR1_BR | SPI_CR1_LSBFIRST | SPI_CR1_SSI | \
+ SPI_CR1_SSM | SPI_CR1_RXONLY | SPI_CR1_CRCL | \
+ SPI_CR1_CRCNEXT | SPI_CR1_CRCEN | SPI_CR1_BIDIOE | \
+ SPI_CR1_BIDIMODE)
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SPI_LL_Private_Macros SPI Private Macros
+ * @{
+ */
+#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \
+ || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \
+ || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
+ || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
+
+#define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
+ || ((__VALUE__) == LL_SPI_MODE_SLAVE))
+
+#define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
+
+#define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
+ || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
+
+#define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
+ || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
+
+#define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
+ || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
+ || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
+
+#define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
+
+#define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
+ || ((__VALUE__) == LL_SPI_MSB_FIRST))
+
+#define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
+ || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
+
+#define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SPI_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup SPI_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize the SPI registers to their default reset values.
+ * @param SPIx SPI Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: SPI registers are de-initialized
+ * - ERROR: SPI registers are not de-initialized
+ */
+ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
+{
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_INSTANCE(SPIx));
+
+#if defined(SPI1)
+ if (SPIx == SPI1)
+ {
+ /* Force reset of SPI clock */
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
+
+ /* Release reset of SPI clock */
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
+
+ status = SUCCESS;
+ }
+#endif /* SPI1 */
+#if defined(SPI2)
+ if (SPIx == SPI2)
+ {
+ /* Force reset of SPI clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
+
+ /* Release reset of SPI clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
+
+ status = SUCCESS;
+ }
+#endif /* SPI2 */
+#if defined(SPI3)
+ if (SPIx == SPI3)
+ {
+ /* Force reset of SPI clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
+
+ /* Release reset of SPI clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
+
+ status = SUCCESS;
+ }
+#endif /* SPI3 */
+#if defined(SPI4)
+ if (SPIx == SPI4)
+ {
+ /* Force reset of SPI clock */
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI4);
+
+ /* Release reset of SPI clock */
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI4);
+
+ status = SUCCESS;
+ }
+#endif /* SPI4 */
+
+ return status;
+}
+
+/**
+ * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
+ * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
+ * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+ * @param SPIx SPI Instance
+ * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
+ */
+ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
+{
+ ErrorStatus status = ERROR;
+
+ /* Check the SPI Instance SPIx*/
+ assert_param(IS_SPI_ALL_INSTANCE(SPIx));
+
+ /* Check the SPI parameters from SPI_InitStruct*/
+ assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
+ assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
+ assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
+ assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
+ assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
+ assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
+ assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
+ assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
+ assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
+
+ if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
+ {
+ /*---------------------------- SPIx CR1 Configuration ------------------------
+ * Configure SPIx CR1 with parameters:
+ * - TransferDirection: SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
+ * - Master/Slave Mode: SPI_CR1_MSTR bit
+ * - ClockPolarity: SPI_CR1_CPOL bit
+ * - ClockPhase: SPI_CR1_CPHA bit
+ * - NSS management: SPI_CR1_SSM bit
+ * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
+ * - BitOrder: SPI_CR1_LSBFIRST bit
+ * - CRCCalculation: SPI_CR1_CRCEN bit
+ */
+ MODIFY_REG(SPIx->CR1,
+ SPI_CR1_CLEAR_MASK,
+ SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode |
+ SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
+ SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
+ SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
+
+ /*---------------------------- SPIx CR2 Configuration ------------------------
+ * Configure SPIx CR2 with parameters:
+ * - DataWidth: DS[3:0] bits
+ * - NSS management: SSOE bit
+ */
+ MODIFY_REG(SPIx->CR2,
+ SPI_CR2_DS | SPI_CR2_SSOE,
+ SPI_InitStruct->DataWidth | (SPI_InitStruct->NSS >> 16U));
+
+ /*---------------------------- SPIx CRCPR Configuration ----------------------
+ * Configure SPIx CRCPR with parameters:
+ * - CRCPoly: CRCPOLY[15:0] bits
+ */
+ if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
+ {
+ assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
+ LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
+ }
+ status = SUCCESS;
+ }
+
+#if defined (SPI_I2S_SUPPORT)
+ /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
+ CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
+#endif /* SPI_I2S_SUPPORT */
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_SPI_InitTypeDef field to default value.
+ * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
+{
+ /* Set SPI_InitStruct fields to default values */
+ SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
+ SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE;
+ SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT;
+ SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW;
+ SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE;
+ SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT;
+ SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2;
+ SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST;
+ SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
+ SPI_InitStruct->CRCPoly = 7U;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#if defined(SPI_I2S_SUPPORT)
+/** @addtogroup I2S_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2S_LL_Private_Constants I2S Private Constants
+ * @{
+ */
+/* I2S registers Masks */
+#define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
+ SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \
+ SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD )
+
+#define I2S_I2SPR_CLEAR_MASK 0x0002U
+/**
+ * @}
+ */
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2S_LL_Private_Macros I2S Private Macros
+ * @{
+ */
+
+#define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \
+ || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
+ || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \
+ || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
+
+#define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \
+ || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
+
+#define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \
+ || ((__VALUE__) == LL_I2S_STANDARD_MSB) \
+ || ((__VALUE__) == LL_I2S_STANDARD_LSB) \
+ || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
+ || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
+
+#define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \
+ || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \
+ || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
+ || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
+
+#define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
+ || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
+
+#define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \
+ && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
+ || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
+
+#define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U)
+
+#define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
+ || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2S_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup I2S_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize the SPI/I2S registers to their default reset values.
+ * @param SPIx SPI Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: SPI registers are de-initialized
+ * - ERROR: SPI registers are not de-initialized
+ */
+ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_DeInit(SPIx);
+}
+
+/**
+ * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
+ * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
+ * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+ * @param SPIx SPI Instance
+ * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: SPI registers are Initialized
+ * - ERROR: SPI registers are not Initialized
+ */
+ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
+{
+ uint16_t i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
+ uint32_t tmp = 0U;
+ LL_RCC_ClocksTypeDef rcc_clocks;
+ uint32_t sourceclock = 0U;
+ ErrorStatus status = ERROR;
+
+ /* Check the I2S parameters */
+ assert_param(IS_I2S_ALL_INSTANCE(SPIx));
+ assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
+ assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
+ assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
+ assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
+ assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
+ assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
+
+ if (LL_I2S_IsEnabled(SPIx) == 0x00000000U)
+ {
+ /*---------------------------- SPIx I2SCFGR Configuration --------------------
+ * Configure SPIx I2SCFGR with parameters:
+ * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit
+ * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
+ * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
+ * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
+ */
+
+ /* Write to SPIx I2SCFGR */
+ MODIFY_REG(SPIx->I2SCFGR,
+ I2S_I2SCFGR_CLEAR_MASK,
+ I2S_InitStruct->Mode | I2S_InitStruct->Standard |
+ I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
+ SPI_I2SCFGR_I2SMOD);
+
+ /*---------------------------- SPIx I2SPR Configuration ----------------------
+ * Configure SPIx I2SPR with parameters:
+ * - MCLKOutput: SPI_I2SPR_MCKOE bit
+ * - AudioFreq: SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
+ */
+
+ /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
+ * else, default values are used: i2sodd = 0U, i2sdiv = 2U.
+ */
+ if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
+ {
+ /* Check the frame length (For the Prescaler computing)
+ * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
+ */
+ if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
+ {
+ /* Packet length is 32 bits */
+ packetlength = 2U;
+ }
+
+ /* I2S Clock source is System clock: Get System Clock frequency */
+ LL_RCC_GetSystemClocksFreq(&rcc_clocks);
+
+ /* Get the source clock value: based on System Clock value */
+ sourceclock = rcc_clocks.SYSCLK_Frequency;
+
+ /* Compute the Real divider depending on the MCLK output state with a floating point */
+ if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
+ {
+ /* MCLK output is enabled */
+ tmp = (uint16_t)(((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
+ }
+ else
+ {
+ /* MCLK output is disabled */
+ tmp = (uint16_t)(((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
+ }
+
+ /* Remove the floating point */
+ tmp = tmp / 10U;
+
+ /* Check the parity of the divider */
+ i2sodd = (uint16_t)(tmp & (uint16_t)0x0001U);
+
+ /* Compute the i2sdiv prescaler */
+ i2sdiv = (uint16_t)((tmp - i2sodd) / 2U);
+
+ /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
+ i2sodd = (uint16_t)(i2sodd << 8U);
+ }
+
+ /* Test if the divider is 1 or 0 or greater than 0xFF */
+ if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
+ {
+ /* Set the default values */
+ i2sdiv = 2U;
+ i2sodd = 0U;
+ }
+
+ /* Write to SPIx I2SPR register the computed value */
+ WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput);
+
+ status = SUCCESS;
+ }
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_I2S_InitTypeDef field to default value.
+ * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
+{
+ /*--------------- Reset I2S init structure parameters values -----------------*/
+ I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX;
+ I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS;
+ I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B;
+ I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE;
+ I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT;
+ I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW;
+}
+
+/**
+ * @brief Set linear and parity prescaler.
+ * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
+ * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
+ * @param SPIx SPI Instance
+ * @param PrescalerLinear value: Min_Data=0x02 and Max_Data=0xFF.
+ * @param PrescalerParity This parameter can be one of the following values:
+ * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
+ * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
+ * @retval None
+ */
+void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
+{
+ /* Check the I2S parameters */
+ assert_param(IS_I2S_ALL_INSTANCE(SPIx));
+ assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
+ assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
+
+ /* Write to SPIx I2SPR */
+ MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U));
+}
+
+#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
+/**
+ * @brief Configures the full duplex mode for the I2Sx peripheral using its extension
+ * I2Sxext according to the specified parameters in the I2S_InitStruct.
+ * @note The structure pointed by I2S_InitStruct parameter should be the same
+ * used for the master I2S peripheral. In this case, if the master is
+ * configured as transmitter, the slave will be receiver and vice versa.
+ * Or you can force a different mode by modifying the field I2S_Mode to the
+ * value I2S_SlaveRx or I2S_SlaveTx independently of the master configuration.
+ * @param I2Sxext SPI Instance
+ * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: I2Sxext registers are Initialized
+ * - ERROR: I2Sxext registers are not Initialized
+ */
+ErrorStatus LL_I2S_InitFullDuplex(SPI_TypeDef *I2Sxext, LL_I2S_InitTypeDef *I2S_InitStruct)
+{
+ uint16_t mode = 0U;
+ ErrorStatus status = ERROR;
+
+ /* Check the I2S parameters */
+ assert_param(IS_I2S_EXT_ALL_INSTANCE(I2Sxext));
+ assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
+ assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
+ assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
+ assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
+
+ if (LL_I2S_IsEnabled(I2Sxext) == 0x00000000U)
+ {
+ /*---------------------------- SPIx I2SCFGR Configuration --------------------
+ * Configure SPIx I2SCFGR with parameters:
+ * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit
+ * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
+ * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
+ * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
+ */
+
+ /* Reset I2SPR registers */
+ WRITE_REG(I2Sxext->I2SPR, I2S_I2SPR_CLEAR_MASK);
+
+ /* Get the mode to be configured for the extended I2S */
+ if ((I2S_InitStruct->Mode == LL_I2S_MODE_MASTER_TX) || (I2S_InitStruct->Mode == LL_I2S_MODE_SLAVE_TX))
+ {
+ mode = LL_I2S_MODE_SLAVE_RX;
+ }
+ else
+ {
+ if ((I2S_InitStruct->Mode == LL_I2S_MODE_MASTER_RX) || (I2S_InitStruct->Mode == LL_I2S_MODE_SLAVE_RX))
+ {
+ mode = LL_I2S_MODE_SLAVE_TX;
+ }
+ }
+
+ /* Write to SPIx I2SCFGR */
+ MODIFY_REG(I2Sxext->I2SCFGR,
+ I2S_I2SCFGR_CLEAR_MASK,
+ I2S_InitStruct->Standard |
+ I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
+ SPI_I2SCFGR_I2SMOD | mode);
+
+ status = SUCCESS;
+ }
+ return status;
+}
+#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* SPI_I2S_SUPPORT */
+
+#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_ll_tim.c b/Src/stm32f3xx_ll_tim.c
new file mode 100644
index 0000000..24c9346
--- /dev/null
+++ b/Src/stm32f3xx_ll_tim.c
@@ -0,0 +1,1465 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_tim.c
+ * @author MCD Application Team
+ * @brief TIM LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_ll_tim.h"
+#include "stm32f3xx_ll_bus.h"
+
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM18) || defined (TIM19) || defined (TIM20)
+
+/** @addtogroup TIM_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup TIM_LL_Private_Macros
+ * @{
+ */
+#define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
+ || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
+ || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
+ || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
+ || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
+
+#define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
+ || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
+ || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
+
+#if defined(TIM_CCMR1_OC1M_3)
+#define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
+ || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
+ || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
+ || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
+ || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
+ || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
+ || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
+ || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
+ || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2))
+#else
+#define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
+ || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
+ || ((__VALUE__) == LL_TIM_OCMODE_PWM2))
+#endif
+
+#define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
+ || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
+
+#define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
+ || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
+
+#define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
+ || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
+
+#define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
+ || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
+ || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
+
+#define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
+ || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
+ || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
+ || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
+
+#define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
+
+#define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
+ || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
+ || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
+
+#define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
+ || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
+ || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
+
+#define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
+ || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
+
+#define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
+ || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
+
+#define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
+ || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
+
+#define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
+ || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
+ || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
+ || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
+
+#define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
+ || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
+
+#define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
+ || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
+#if defined(TIM_BDTR_BKF)
+
+#define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
+#endif /* TIM_BDTR_BKF */
+#if defined(TIM_BDTR_BK2E)
+
+#define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
+ || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
+
+#define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
+ || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
+
+#define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
+#endif /* TIM_BDTR_BK2E */
+
+#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
+ || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
+/**
+ * @}
+ */
+
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup TIM_LL_Private_Functions TIM Private Functions
+ * @{
+ */
+static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+#if defined(TIM_CCER_CC5E)
+static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+#endif /* TIM_CCER_CC5E */
+#if defined(TIM_CCER_CC6E)
+static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+#endif /* TIM_CCER_CC6E */
+static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIM_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup TIM_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief Set TIMx registers to their reset values.
+ * @param TIMx Timer instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: invalid TIMx instance
+ */
+ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
+{
+ ErrorStatus result = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(TIMx));
+
+
+ if (TIMx == TIM2)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
+ }
+
+#if defined(TIM1)
+ else if (TIMx == TIM1)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
+ }
+#endif
+#if defined(TIM3)
+ else if (TIMx == TIM3)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
+ }
+#endif
+#if defined(TIM4)
+ else if (TIMx == TIM4)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
+ }
+#endif
+#if defined(TIM5)
+ else if (TIMx == TIM5)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
+ }
+#endif
+#if defined(TIM6)
+ else if (TIMx == TIM6)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
+ }
+#endif
+#if defined(TIM7)
+ else if (TIMx == TIM7)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
+ }
+#endif
+#if defined(TIM8)
+ else if (TIMx == TIM8)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
+ }
+#endif
+#if defined(TIM12)
+ else if (TIMx == TIM12)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12);
+ }
+#endif
+#if defined(TIM13)
+ else if (TIMx == TIM13)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13);
+ }
+#endif
+#if defined(TIM14)
+ else if (TIMx == TIM14)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
+ }
+#endif
+#if defined(TIM15)
+ else if (TIMx == TIM15)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15);
+ }
+#endif
+#if defined(TIM16)
+ else if (TIMx == TIM16)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
+ }
+#endif
+#if defined(TIM17)
+ else if (TIMx == TIM17)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
+ }
+#endif
+#if defined(TIM18)
+ else if (TIMx == TIM18)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM18);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM18);
+ }
+#endif
+#if defined(TIM19)
+ else if (TIMx == TIM19)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM19);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM19);
+ }
+#endif
+#if defined(TIM20)
+ else if (TIMx == TIM20)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM20);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM20);
+ }
+#endif
+ else
+ {
+ result = ERROR;
+ }
+
+
+ return result;
+}
+
+/**
+ * @brief Set the fields of the time base unit configuration data structure
+ * to their default values.
+ * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
+ * @retval None
+ */
+void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
+{
+ /* Set the default configuration */
+ TIM_InitStruct->Prescaler = (uint16_t)0x0000U;
+ TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
+ TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
+ TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
+ TIM_InitStruct->RepetitionCounter = (uint8_t)0x00U;
+}
+
+/**
+ * @brief Configure the TIMx time base unit.
+ * @param TIMx Timer Instance
+ * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
+{
+ uint32_t tmpcr1 = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
+ assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
+
+ tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
+
+ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
+ {
+ /* Select the Counter Mode */
+ MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
+ }
+
+ if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
+ {
+ /* Set the clock division */
+ MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
+ }
+
+ /* Write to TIMx CR1 */
+ LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
+
+ /* Set the Autoreload value */
+ LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
+
+ /* Set the Prescaler value */
+ LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
+
+ if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
+ {
+ /* Set the Repetition Counter value */
+ LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
+ }
+
+ /* Generate an update event to reload the Prescaler
+ and the repetition counter value (if applicable) immediately */
+ LL_TIM_GenerateEvent_UPDATE(TIMx);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Set the fields of the TIMx output channel configuration data
+ * structure to their default values.
+ * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
+ * @retval None
+ */
+void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
+{
+ /* Set the default configuration */
+ TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
+ TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
+ TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
+ TIM_OC_InitStruct->CompareValue = 0x00000000U;
+ TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
+ TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
+ TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
+ TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
+}
+
+/**
+ * @brief Configure the TIMx output channel.
+ * @param TIMx Timer Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
+ * @note OC5 and OC6 are not available for all F3 devices
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx output channel is initialized
+ * - ERROR: TIMx output channel is not initialized
+ */
+ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
+{
+ ErrorStatus result = ERROR;
+
+ switch (Channel)
+ {
+ case LL_TIM_CHANNEL_CH1:
+ result = OC1Config(TIMx, TIM_OC_InitStruct);
+ break;
+ case LL_TIM_CHANNEL_CH2:
+ result = OC2Config(TIMx, TIM_OC_InitStruct);
+ break;
+ case LL_TIM_CHANNEL_CH3:
+ result = OC3Config(TIMx, TIM_OC_InitStruct);
+ break;
+ case LL_TIM_CHANNEL_CH4:
+ result = OC4Config(TIMx, TIM_OC_InitStruct);
+ break;
+#if defined(TIM_CCER_CC5E)
+ case LL_TIM_CHANNEL_CH5:
+ result = OC5Config(TIMx, TIM_OC_InitStruct);
+ break;
+ case LL_TIM_CHANNEL_CH6:
+ result = OC6Config(TIMx, TIM_OC_InitStruct);
+ break;
+#endif /* TIM_CCER_CC5E */
+ default:
+ break;
+ }
+
+ return result;
+}
+
+/**
+ * @brief Set the fields of the TIMx input channel configuration data
+ * structure to their default values.
+ * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
+ * @retval None
+ */
+void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+ /* Set the default configuration */
+ TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
+ TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
+ TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
+ TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
+}
+
+/**
+ * @brief Configure the TIMx input channel.
+ * @param TIMx Timer Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx output channel is initialized
+ * - ERROR: TIMx output channel is not initialized
+ */
+ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
+{
+ ErrorStatus result = ERROR;
+
+ switch (Channel)
+ {
+ case LL_TIM_CHANNEL_CH1:
+ result = IC1Config(TIMx, TIM_IC_InitStruct);
+ break;
+ case LL_TIM_CHANNEL_CH2:
+ result = IC2Config(TIMx, TIM_IC_InitStruct);
+ break;
+ case LL_TIM_CHANNEL_CH3:
+ result = IC3Config(TIMx, TIM_IC_InitStruct);
+ break;
+ case LL_TIM_CHANNEL_CH4:
+ result = IC4Config(TIMx, TIM_IC_InitStruct);
+ break;
+ default:
+ break;
+ }
+
+ return result;
+}
+
+/**
+ * @brief Fills each TIM_EncoderInitStruct field with its default value
+ * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
+ * @retval None
+ */
+void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
+{
+ /* Set the default configuration */
+ TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
+ TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
+ TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
+ TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
+ TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
+ TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
+ TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
+ TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
+ TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
+}
+
+/**
+ * @brief Configure the encoder interface of the timer instance.
+ * @param TIMx Timer Instance
+ * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
+{
+ uint32_t tmpccmr1 = 0U;
+ uint32_t tmpccer = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
+ assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
+ assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
+ assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
+ assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
+ assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
+ assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
+ assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
+ assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
+
+ /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
+ TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Configure TI1 */
+ tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
+ tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
+ tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
+ tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
+
+ /* Configure TI2 */
+ tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC);
+ tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
+ tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
+ tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
+
+ /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
+ tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
+ tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
+ tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
+ tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
+
+ /* Set encoder mode */
+ LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
+
+ /* Write to TIMx CCMR1 */
+ LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ return SUCCESS;
+}
+
+#if defined TIM_CR2_MMS2
+/**
+ * @brief Set the fields of the TIMx Hall sensor interface configuration data
+ * structure to their default values.
+ * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure)
+ * @retval None
+ */
+void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
+{
+ /* Set the default configuration */
+ TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
+ TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
+ TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
+ TIM_HallSensorInitStruct->CommutationDelay = 0U;
+}
+
+/**
+ * @brief Configure the Hall sensor interface of the timer instance.
+ * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
+ * to the TI1 input channel
+ * @note TIMx slave mode controller is configured in reset mode.
+ Selected internal trigger is TI1F_ED.
+ * @note Channel 1 is configured as input, IC1 is mapped on TRC.
+ * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
+ * between 2 changes on the inputs. It gives information about motor speed.
+ * @note Channel 2 is configured in output PWM 2 mode.
+ * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
+ * @note OC2REF is selected as trigger output on TRGO.
+ * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
+ * when TIMx operates in Hall sensor interface mode.
+ * @param TIMx Timer Instance
+ * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure)
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
+{
+ uint32_t tmpcr2 = 0U;
+ uint32_t tmpccmr1 = 0U;
+ uint32_t tmpccer = 0U;
+ uint32_t tmpsmcr = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
+ assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
+ assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
+
+ /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
+ TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
+
+ /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
+ tmpcr2 |= TIM_CR2_TI1S;
+
+ /* OC2REF signal is used as trigger output (TRGO) */
+ tmpcr2 |= LL_TIM_TRGO_OC2REF;
+
+ /* Configure the slave mode controller */
+ tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
+ tmpsmcr |= LL_TIM_TS_TI1F_ED;
+ tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
+
+ /* Configure input channel 1 */
+ tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
+ tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
+ tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
+ tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
+
+ /* Configure input channel 2 */
+ tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE);
+ tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
+
+ /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
+ tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
+ tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
+ tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
+
+ /* Write to TIMx CR2 */
+ LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+ /* Write to TIMx SMCR */
+ LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
+
+ /* Write to TIMx CCMR1 */
+ LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ /* Write to TIMx CCR2 */
+ LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
+
+ return SUCCESS;
+}
+#endif /* TIM_CR2_MMS2 */
+
+/**
+ * @brief Set the fields of the Break and Dead Time configuration data structure
+ * to their default values.
+ * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
+ * @retval None
+ */
+void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
+{
+ /* Set the default configuration */
+ TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
+ TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
+ TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
+ TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00U;
+ TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
+ TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
+#if defined(TIM_BDTR_BKF)
+ TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1;
+#endif /* TIM_BDTR_BKF */
+#if defined(TIM_BDTR_BK2E)
+ TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE;
+ TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW;
+ TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1;
+#endif /* TIM_BDTR_BK2E */
+ TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
+}
+
+/**
+ * @brief Configure the Break and Dead Time feature of the timer instance.
+ * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
+ * and DTG[7:0] can be write-locked depending on the LOCK configuration, it
+ * can be necessary to configure all of them during the first write access to
+ * the TIMx_BDTR register.
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a second break input.
+ * @param TIMx Timer Instance
+ * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure(Break and Dead Time configuration data structure)
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: Break and Dead Time is initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
+{
+ uint32_t tmpbdtr = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
+ assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
+ assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
+ assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
+ assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
+ assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
+
+ /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
+ the OSSI State, the dead time value and the Automatic Output Enable Bit */
+
+ /* Set the BDTR bits */
+ MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
+#if defined(TIM_BDTR_BKF)
+ if (IS_TIM_ADVANCED_INSTANCE(TIMx))
+ {
+ assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
+ }
+#endif /* TIM_BDTR_BKF */
+#if defined(TIM_BDTR_BK2E)
+
+ if (IS_TIM_BKIN2_INSTANCE(TIMx))
+ {
+ assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
+ assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
+ assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
+
+ /* Set the BREAK2 input related BDTR bit-fields */
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
+ }
+#endif /* TIM_BDTR_BK2E */
+
+ /* Set TIMx_BDTR */
+ LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
+
+ return SUCCESS;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_LL_Private_Functions TIM Private Functions
+ * @brief Private functions
+ * @{
+ */
+/**
+ * @brief Configure the TIMx output channel 1.
+ * @param TIMx Timer Instance
+ * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+ uint32_t tmpccmr1 = 0U;
+ uint32_t tmpccer = 0U;
+ uint32_t tmpcr2 = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
+
+ /* Reset Capture/Compare selection Bits */
+ CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
+
+ /* Set the Output Compare Mode */
+ MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
+
+ /* Set the Output Compare Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
+
+ /* Set the Output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+
+ /* Set the complementary output Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
+
+ /* Set the complementary output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
+
+ /* Set the Output Idle state */
+ MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
+
+ /* Set the complementary output Idle state */
+ MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
+ }
+
+ /* Write to TIMx CR2 */
+ LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+ /* Write to TIMx CCMR1 */
+ LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
+
+ /* Set the Capture Compare Register value */
+ LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx output channel 2.
+ * @param TIMx Timer Instance
+ * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+ uint32_t tmpccmr1 = 0U;
+ uint32_t tmpccer = 0U;
+ uint32_t tmpcr2 = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
+
+ /* Reset Capture/Compare selection Bits */
+ CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
+
+ /* Select the Output Compare Mode */
+ MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
+
+ /* Set the Output Compare Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
+
+ /* Set the Output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+
+ /* Set the complementary output Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
+
+ /* Set the complementary output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
+
+ /* Set the Output Idle state */
+ MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#else
+ /* Set the complementary output Idle state */
+ MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
+#endif
+ }
+
+ /* Write to TIMx CR2 */
+ LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+ /* Write to TIMx CCMR1 */
+ LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
+
+ /* Set the Capture Compare Register value */
+ LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx output channel 3.
+ * @param TIMx Timer Instance
+ * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+ uint32_t tmpccmr2 = 0U;
+ uint32_t tmpccer = 0U;
+ uint32_t tmpcr2 = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC3_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+
+ /* Disable the Channel 3: Reset the CC3E Bit */
+ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+
+ /* Get the TIMx CCMR2 register value */
+ tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
+
+ /* Reset Capture/Compare selection Bits */
+ CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
+
+ /* Select the Output Compare Mode */
+ MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
+
+ /* Set the Output Compare Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
+
+ /* Set the Output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+
+ /* Set the complementary output Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
+
+ /* Set the complementary output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#else
+ /* Set the Output Idle state */
+ MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
+
+ /* Set the complementary output Idle state */
+ MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
+#endif
+ }
+
+ /* Write to TIMx CR2 */
+ LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+ /* Write to TIMx CCMR2 */
+ LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
+
+ /* Set the Capture Compare Register value */
+ LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx output channel 4.
+ * @param TIMx Timer Instance
+ * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+ uint32_t tmpccmr2 = 0U;
+ uint32_t tmpccer = 0U;
+ uint32_t tmpcr2 = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC4_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+
+ /* Disable the Channel 4: Reset the CC4E Bit */
+ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+
+ /* Get the TIMx CCMR2 register value */
+ tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
+
+ /* Reset Capture/Compare selection Bits */
+ CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
+
+ /* Select the Output Compare Mode */
+ MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
+
+ /* Set the Output Compare Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
+
+ /* Set the Output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#else
+ /* Set the Output Idle state */
+ MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
+#endif
+ }
+
+ /* Write to TIMx CR2 */
+ LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+ /* Write to TIMx CCMR2 */
+ LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
+
+ /* Set the Capture Compare Register value */
+ LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ return SUCCESS;
+}
+
+#if defined(TIM_CCER_CC5E)
+/**
+ * @brief Configure the TIMx output channel 5.
+ * @param TIMx Timer Instance
+ * @param TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
+ * @note OC5 is not available for all F3 devices
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+ uint32_t tmpccmr3 = 0U;
+ uint32_t tmpccer = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC5_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+
+ /* Disable the Channel 5: Reset the CC5E Bit */
+ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Get the TIMx CCMR3 register value */
+ tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
+
+ /* Select the Output Compare Mode */
+ MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
+
+ /* Set the Output Compare Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
+
+ /* Set the Output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+
+ /* Set the Output Idle state */
+ MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
+
+ }
+
+ /* Write to TIMx CCMR3 */
+ LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
+
+ /* Set the Capture Compare Register value */
+ LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx output channel 6.
+ * @param TIMx Timer Instance
+ * @param TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
+ * @note OC6 is not available for all F3 devices
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+ uint32_t tmpccmr3 = 0U;
+ uint32_t tmpccer = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC6_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+
+ /* Disable the Channel 5: Reset the CC6E Bit */
+ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Get the TIMx CCMR3 register value */
+ tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
+
+ /* Select the Output Compare Mode */
+ MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
+
+ /* Set the Output Compare Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
+
+ /* Set the Output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+
+ /* Set the Output Idle state */
+ MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
+ }
+
+ /* Write to TIMx CCMR3 */
+ LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
+
+ /* Set the Capture Compare Register value */
+ LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ return SUCCESS;
+}
+#endif /* TIM_CCER_CC5E */
+
+/**
+ * @brief Configure the TIMx input channel 1.
+ * @param TIMx Timer Instance
+ * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
+ assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
+ assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
+ assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
+
+ /* Select the Input and set the filter and the prescaler value */
+ MODIFY_REG(TIMx->CCMR1,
+ (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
+ (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
+
+ /* Select the Polarity and set the CC1E Bit */
+ MODIFY_REG(TIMx->CCER,
+ (TIM_CCER_CC1P | TIM_CCER_CC1NP),
+ (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx input channel 2.
+ * @param TIMx Timer Instance
+ * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
+ assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
+ assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
+ assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
+
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
+
+ /* Select the Input and set the filter and the prescaler value */
+ MODIFY_REG(TIMx->CCMR1,
+ (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
+ (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
+
+ /* Select the Polarity and set the CC2E Bit */
+ MODIFY_REG(TIMx->CCER,
+ (TIM_CCER_CC2P | TIM_CCER_CC2NP),
+ ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx input channel 3.
+ * @param TIMx Timer Instance
+ * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC3_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
+ assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
+ assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
+ assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
+
+ /* Disable the Channel 3: Reset the CC3E Bit */
+ TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
+
+ /* Select the Input and set the filter and the prescaler value */
+ MODIFY_REG(TIMx->CCMR2,
+ (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
+ (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
+
+ /* Select the Polarity and set the CC3E Bit */
+ MODIFY_REG(TIMx->CCER,
+ (TIM_CCER_CC3P | TIM_CCER_CC3NP),
+ ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx input channel 4.
+ * @param TIMx Timer Instance
+ * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC4_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
+ assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
+ assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
+ assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
+
+ /* Disable the Channel 4: Reset the CC4E Bit */
+ TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
+
+ /* Select the Input and set the filter and the prescaler value */
+ MODIFY_REG(TIMx->CCMR2,
+ (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
+ (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
+
+ /* Select the Polarity and set the CC2E Bit */
+ MODIFY_REG(TIMx->CCER,
+ (TIM_CCER_CC4P | TIM_CCER_CC4NP),
+ ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
+
+ return SUCCESS;
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 || TIM18 || TIM19 || TIM20 */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f3xx_ll_usart.c b/Src/stm32f3xx_ll_usart.c
new file mode 100644
index 0000000..48d09dd
--- /dev/null
+++ b/Src/stm32f3xx_ll_usart.c
@@ -0,0 +1,458 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_usart.c
+ * @author MCD Application Team
+ * @brief USART LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_ll_usart.h"
+#include "stm32f3xx_ll_rcc.h"
+#include "stm32f3xx_ll_bus.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5)
+
+/** @addtogroup USART_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup USART_LL_Private_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup USART_LL_Private_Macros
+ * @{
+ */
+
+/* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
+ * divided by the smallest oversampling used on the USART (i.e. 8) */
+#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 9000000U)
+
+/* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */
+#define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
+
+/* __VALUE__ BRR content must be lower than or equal to 0xFFFF. */
+#define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
+
+#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
+ || ((__VALUE__) == LL_USART_DIRECTION_RX) \
+ || ((__VALUE__) == LL_USART_DIRECTION_TX) \
+ || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
+
+#define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
+ || ((__VALUE__) == LL_USART_PARITY_EVEN) \
+ || ((__VALUE__) == LL_USART_PARITY_ODD))
+
+#if defined(USART_7BITS_SUPPORT)
+#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \
+ || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \
+ || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
+#else
+#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_8B) \
+ || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
+#endif
+
+#define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
+ || ((__VALUE__) == LL_USART_OVERSAMPLING_8))
+
+#define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
+ || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
+
+#define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
+ || ((__VALUE__) == LL_USART_PHASE_2EDGE))
+
+#define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
+ || ((__VALUE__) == LL_USART_POLARITY_HIGH))
+
+#define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
+ || ((__VALUE__) == LL_USART_CLOCK_ENABLE))
+
+#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
+ || ((__VALUE__) == LL_USART_STOPBITS_1) \
+ || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
+ || ((__VALUE__) == LL_USART_STOPBITS_2))
+
+#define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
+ || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
+ || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
+ || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup USART_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup USART_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize USART registers (Registers restored to their default values).
+ * @param USARTx USART Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: USART registers are de-initialized
+ * - ERROR: USART registers are not de-initialized
+ */
+ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_UART_INSTANCE(USARTx));
+
+ if (USARTx == USART1)
+ {
+ /* Force reset of USART clock */
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);
+
+ /* Release reset of USART clock */
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);
+ }
+ else if (USARTx == USART2)
+ {
+ /* Force reset of USART clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);
+
+ /* Release reset of USART clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);
+ }
+ else if (USARTx == USART3)
+ {
+ /* Force reset of USART clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3);
+
+ /* Release reset of USART clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3);
+ }
+#if defined(UART4)
+ else if (USARTx == UART4)
+ {
+ /* Force reset of UART clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4);
+
+ /* Release reset of UART clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4);
+ }
+#endif /* UART4 */
+#if defined(UART5)
+ else if (USARTx == UART5)
+ {
+ /* Force reset of UART clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5);
+
+ /* Release reset of UART clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5);
+ }
+#endif /* UART5 */
+ else
+ {
+ status = ERROR;
+ }
+
+ return (status);
+}
+
+/**
+ * @brief Initialize USART registers according to the specified
+ * parameters in USART_InitStruct.
+ * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
+ * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+ * @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
+ * @param USARTx USART Instance
+ * @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure
+ * that contains the configuration information for the specified USART peripheral.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: USART registers are initialized according to USART_InitStruct content
+ * - ERROR: Problem occurred during USART Registers initialization
+ */
+ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
+{
+ ErrorStatus status = ERROR;
+ uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
+#if defined(STM32F303x8)||defined(STM32F334x8)||defined(STM32F328xx)||defined(STM32F301x8)||defined(STM32F302x8)||defined(STM32F318xx)
+ LL_RCC_ClocksTypeDef RCC_Clocks;
+#endif
+
+ /* Check the parameters */
+ assert_param(IS_UART_INSTANCE(USARTx));
+ assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));
+ assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
+ assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));
+ assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));
+ assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));
+ assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
+ assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
+
+ /* USART needs to be in disabled state, in order to be able to configure some bits in
+ CRx registers */
+ if (LL_USART_IsEnabled(USARTx) == 0U)
+ {
+ /*---------------------------- USART CR1 Configuration ---------------------
+ * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
+ * - DataWidth: USART_CR1_M bits according to USART_InitStruct->DataWidth value
+ * - Parity: USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
+ * - TransferDirection: USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value
+ * - Oversampling: USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.
+ */
+ MODIFY_REG(USARTx->CR1,
+ (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
+ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
+ (USART_InitStruct->DataWidth | USART_InitStruct->Parity |
+ USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
+
+ /*---------------------------- USART CR2 Configuration ---------------------
+ * Configure USARTx CR2 (Stop bits) with parameters:
+ * - Stop Bits: USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
+ * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
+ */
+ LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
+
+ /*---------------------------- USART CR3 Configuration ---------------------
+ * Configure USARTx CR3 (Hardware Flow Control) with parameters:
+ * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value.
+ */
+ LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
+
+ /*---------------------------- USART BRR Configuration ---------------------
+ * Retrieve Clock frequency used for USART Peripheral
+ */
+ if (USARTx == USART1)
+ {
+ periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART1_CLKSOURCE);
+ }
+ else if (USARTx == USART2)
+ {
+#if defined (RCC_CFGR3_USART2SW)
+ periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART2_CLKSOURCE);
+#else
+ /* USART2 clock is PCLK */
+ LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
+ periphclk = RCC_Clocks.PCLK1_Frequency;
+#endif
+ }
+ else if (USARTx == USART3)
+ {
+#if defined (RCC_CFGR3_USART3SW)
+ periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART3_CLKSOURCE);
+#else
+ /* USART3 clock is PCLK */
+ LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
+ periphclk = RCC_Clocks.PCLK1_Frequency;
+#endif
+ }
+#if defined(UART4)
+ else if (USARTx == UART4)
+ {
+ periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART4_CLKSOURCE);
+ }
+#endif /* UART4 */
+#if defined(UART5)
+ else if (USARTx == UART5)
+ {
+ periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART5_CLKSOURCE);
+ }
+#endif /* UART5 */
+ else
+ {
+ /* Nothing to do, as error code is already assigned to ERROR value */
+ }
+
+ /* Configure the USART Baud Rate :
+ - valid baud rate value (different from 0) is required
+ - Peripheral clock as returned by RCC service, should be valid (different from 0).
+ */
+ if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
+ && (USART_InitStruct->BaudRate != 0U))
+ {
+ status = SUCCESS;
+ LL_USART_SetBaudRate(USARTx,
+ periphclk,
+ USART_InitStruct->OverSampling,
+ USART_InitStruct->BaudRate);
+
+ /* Check BRR is greater than or equal to 16d */
+ assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR));
+
+ /* Check BRR is greater than or equal to 16d */
+ assert_param(IS_LL_USART_BRR_MAX(USARTx->BRR));
+ }
+ }
+ /* Endif (=> USART not in Disabled state => return ERROR) */
+
+ return (status);
+}
+
+/**
+ * @brief Set each @ref LL_USART_InitTypeDef field to default value.
+ * @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+
+void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
+{
+ /* Set USART_InitStruct fields to default values */
+ USART_InitStruct->BaudRate = 9600U;
+ USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B;
+ USART_InitStruct->StopBits = LL_USART_STOPBITS_1;
+ USART_InitStruct->Parity = LL_USART_PARITY_NONE ;
+ USART_InitStruct->TransferDirection = LL_USART_DIRECTION_TX_RX;
+ USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;
+ USART_InitStruct->OverSampling = LL_USART_OVERSAMPLING_16;
+}
+
+/**
+ * @brief Initialize USART Clock related settings according to the
+ * specified parameters in the USART_ClockInitStruct.
+ * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
+ * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+ * @param USARTx USART Instance
+ * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
+ * that contains the Clock configuration information for the specified USART peripheral.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
+ * - ERROR: Problem occurred during USART Registers initialization
+ */
+ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check USART Instance and Clock signal output parameters */
+ assert_param(IS_UART_INSTANCE(USARTx));
+ assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
+
+ /* USART needs to be in disabled state, in order to be able to configure some bits in
+ CRx registers */
+ if (LL_USART_IsEnabled(USARTx) == 0U)
+ {
+ /*---------------------------- USART CR2 Configuration -----------------------*/
+ /* If Clock signal has to be output */
+ if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE)
+ {
+ /* Deactivate Clock signal delivery :
+ * - Disable Clock Output: USART_CR2_CLKEN cleared
+ */
+ LL_USART_DisableSCLKOutput(USARTx);
+ }
+ else
+ {
+ /* Ensure USART instance is USART capable */
+ assert_param(IS_USART_INSTANCE(USARTx));
+
+ /* Check clock related parameters */
+ assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
+ assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
+ assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
+
+ /*---------------------------- USART CR2 Configuration -----------------------
+ * Configure USARTx CR2 (Clock signal related bits) with parameters:
+ * - Enable Clock Output: USART_CR2_CLKEN set
+ * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
+ * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
+ * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
+ */
+ MODIFY_REG(USARTx->CR2,
+ USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
+ USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity |
+ USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
+ }
+ }
+ /* Else (USART not in Disabled state => return ERROR */
+ else
+ {
+ status = ERROR;
+ }
+
+ return (status);
+}
+
+/**
+ * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
+ * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
+{
+ /* Set LL_USART_ClockInitStruct fields with default values */
+ USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE;
+ USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
+ USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
+ USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* USART1 || USART2|| USART3 || UART4 || UART5 */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Src/stm32f3xx_ll_utils.c b/Src/stm32f3xx_ll_utils.c
new file mode 100644
index 0000000..9e9e11f
--- /dev/null
+++ b/Src/stm32f3xx_ll_utils.c
@@ -0,0 +1,583 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_utils.c
+ * @author MCD Application Team
+ * @brief UTILS LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_ll_rcc.h"
+#include "stm32f3xx_ll_utils.h"
+#include "stm32f3xx_ll_system.h"
+#include "stm32f3xx_ll_pwr.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+/** @addtogroup UTILS_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup UTILS_LL_Private_Constants
+ * @{
+ */
+
+/* Defines used for PLL range */
+#define UTILS_PLL_OUTPUT_MAX 72000000U /*!< Frequency max for PLL output, in Hz */
+
+/* Defines used for HSE range */
+#define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */
+#define UTILS_HSE_FREQUENCY_MAX 32000000U /*!< Frequency max for HSE frequency, in Hz */
+
+/* Defines used for FLASH latency according to SYSCLK Frequency */
+#define UTILS_LATENCY1_FREQ 24000000U /*!< SYSCLK frequency to set FLASH latency 1 */
+#define UTILS_LATENCY2_FREQ 48000000U /*!< SYSCLK frequency to set FLASH latency 2 */
+/**
+ * @}
+ */
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup UTILS_LL_Private_Macros
+ * @{
+ */
+#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
+
+#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
+ || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
+ || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
+ || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
+ || ((__VALUE__) == LL_RCC_APB1_DIV_16))
+
+#define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
+ || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
+ || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
+ || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
+ || ((__VALUE__) == LL_RCC_APB2_DIV_16))
+
+#define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_2) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_3) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_4) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_5) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_6) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_7) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_8) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_9) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_10) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_11) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_12) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_13) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_14) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_15) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_16))
+
+#define IS_LL_UTILS_PREDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1) || ((__VALUE__) == LL_RCC_PREDIV_DIV_2) || \
+ ((__VALUE__) == LL_RCC_PREDIV_DIV_3) || ((__VALUE__) == LL_RCC_PREDIV_DIV_4) || \
+ ((__VALUE__) == LL_RCC_PREDIV_DIV_5) || ((__VALUE__) == LL_RCC_PREDIV_DIV_6) || \
+ ((__VALUE__) == LL_RCC_PREDIV_DIV_7) || ((__VALUE__) == LL_RCC_PREDIV_DIV_8) || \
+ ((__VALUE__) == LL_RCC_PREDIV_DIV_9) || ((__VALUE__) == LL_RCC_PREDIV_DIV_10) || \
+ ((__VALUE__) == LL_RCC_PREDIV_DIV_11) || ((__VALUE__) == LL_RCC_PREDIV_DIV_12) || \
+ ((__VALUE__) == LL_RCC_PREDIV_DIV_13) || ((__VALUE__) == LL_RCC_PREDIV_DIV_14) || \
+ ((__VALUE__) == LL_RCC_PREDIV_DIV_15) || ((__VALUE__) == LL_RCC_PREDIV_DIV_16))
+
+#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((__VALUE__) <= UTILS_PLL_OUTPUT_MAX)
+
+
+#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
+ || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
+
+#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
+/**
+ * @}
+ */
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup UTILS_LL_Private_Functions UTILS Private functions
+ * @{
+ */
+static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
+ LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
+#if defined(FLASH_ACR_LATENCY)
+static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency);
+#endif /* FLASH_ACR_LATENCY */
+static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+static ErrorStatus UTILS_PLL_IsBusy(void);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UTILS_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup UTILS_LL_EF_DELAY
+ * @{
+ */
+
+/**
+ * @brief This function configures the Cortex-M SysTick source to have 1ms time base.
+ * @note When a RTOS is used, it is recommended to avoid changing the Systick
+ * configuration by calling this function, for a delay use rather osDelay RTOS service.
+ * @param HCLKFrequency HCLK frequency in Hz
+ * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
+ * @retval None
+ */
+void LL_Init1msTick(uint32_t HCLKFrequency)
+{
+ /* Use frequency provided in argument */
+ LL_InitTick(HCLKFrequency, 1000U);
+}
+
+/**
+ * @brief This function provides accurate delay (in milliseconds) based
+ * on SysTick counter flag
+ * @note When a RTOS is used, it is recommended to avoid using blocking delay
+ * and use rather osDelay service.
+ * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which
+ * will configure Systick to 1ms
+ * @param Delay specifies the delay time length, in milliseconds.
+ * @retval None
+ */
+void LL_mDelay(uint32_t Delay)
+{
+ __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
+ /* Add this code to indicate that local variable is not used */
+ ((void)tmp);
+
+ /* Add a period to guaranty minimum wait */
+ if (Delay < LL_MAX_DELAY)
+ {
+ Delay++;
+ }
+
+ while (Delay)
+ {
+ if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
+ {
+ Delay--;
+ }
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup UTILS_EF_SYSTEM
+ * @brief System Configuration functions
+ *
+ @verbatim
+ ===============================================================================
+ ##### System Configuration functions #####
+ ===============================================================================
+ [..]
+ System, AHB and APB buses clocks configuration
+
+ (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 72000000 Hz.
+ @endverbatim
+ @internal
+ Depending on the SYSCLK frequency, the flash latency should be adapted accordingly:
+ (++) +-----------------------------------------------+
+ (++) | Latency | SYSCLK clock frequency (MHz) |
+ (++) |---------------|-------------------------------|
+ (++) |0WS(1CPU cycle)| 0 < SYSCLK <= 24 |
+ (++) |---------------|-------------------------------|
+ (++) |1WS(2CPU cycle)| 24 < SYSCLK <= 48 |
+ (++) |---------------|-------------------------------|
+ (++) |2WS(3CPU cycle)| 48 < SYSCLK <= 72 |
+ (++) +-----------------------------------------------+
+ @endinternal
+ * @{
+ */
+
+/**
+ * @brief This function sets directly SystemCoreClock CMSIS variable.
+ * @note Variable can be calculated also through SystemCoreClockUpdate function.
+ * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
+ * @retval None
+ */
+void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
+{
+ /* HCLK clock frequency */
+ SystemCoreClock = HCLKFrequency;
+}
+
+/**
+ * @brief This function configures system clock with HSI as clock source of the PLL
+ * @note The application need to ensure that PLL is disabled.
+ * @note Function is based on the following formula:
+ * - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL)
+ * - PREDIV: Set to 2 for few devices
+ * - PLLMUL: The application software must set correctly the PLL multiplication factor to
+ * not exceed 72MHz
+ * @note FLASH latency can be modified through this function.
+ * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
+ * the configuration information for the PLL.
+ * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
+ * the configuration information for the BUS prescalers.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: Max frequency configuration done
+ * - ERROR: Max frequency configuration not done
+ */
+ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
+ LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
+{
+ ErrorStatus status = SUCCESS;
+ uint32_t pllfreq = 0U;
+
+ /* Check if one of the PLL is enabled */
+ if (UTILS_PLL_IsBusy() == SUCCESS)
+ {
+#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
+ /* Check PREDIV value */
+ assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv));
+#else
+ /* Force PREDIV value to 2 */
+ UTILS_PLLInitStruct->Prediv = LL_RCC_PREDIV_DIV_2;
+#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
+ /* Calculate the new PLL output frequency */
+ pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
+
+ /* Enable HSI if not enabled */
+ if (LL_RCC_HSI_IsReady() != 1U)
+ {
+ LL_RCC_HSI_Enable();
+ while (LL_RCC_HSI_IsReady() != 1U)
+ {
+ /* Wait for HSI ready */
+ }
+ }
+
+ /* Configure PLL */
+#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
+ LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
+#else
+ LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI_DIV_2, UTILS_PLLInitStruct->PLLMul);
+#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
+
+ /* Enable PLL and switch system clock to PLL */
+ status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
+ }
+ else
+ {
+ /* Current PLL configuration cannot be modified */
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief This function configures system clock with HSE as clock source of the PLL
+ * @note The application need to ensure that PLL is disabled.
+ * @note Function is based on the following formula:
+ * - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL)
+ * - PREDIV: Set to 2 for few devices
+ * - PLLMUL: The application software must set correctly the PLL multiplication factor to
+ * not exceed @ref UTILS_PLL_OUTPUT_MAX
+ * @note FLASH latency can be modified through this function.
+ * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 32000000
+ * @param HSEBypass This parameter can be one of the following values:
+ * @arg @ref LL_UTILS_HSEBYPASS_ON
+ * @arg @ref LL_UTILS_HSEBYPASS_OFF
+ * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
+ * the configuration information for the PLL.
+ * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
+ * the configuration information for the BUS prescalers.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: Max frequency configuration done
+ * - ERROR: Max frequency configuration not done
+ */
+ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
+ LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
+{
+ ErrorStatus status = SUCCESS;
+ uint32_t pllfreq = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
+ assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
+
+ /* Check if one of the PLL is enabled */
+ if (UTILS_PLL_IsBusy() == SUCCESS)
+ {
+ /* Check PREDIV value */
+#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
+ assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv));
+#else
+ assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->Prediv));
+#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
+
+ /* Calculate the new PLL output frequency */
+ pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
+
+ /* Enable HSE if not enabled */
+ if (LL_RCC_HSE_IsReady() != 1U)
+ {
+ /* Check if need to enable HSE bypass feature or not */
+ if (HSEBypass == LL_UTILS_HSEBYPASS_ON)
+ {
+ LL_RCC_HSE_EnableBypass();
+ }
+ else
+ {
+ LL_RCC_HSE_DisableBypass();
+ }
+
+ /* Enable HSE */
+ LL_RCC_HSE_Enable();
+ while (LL_RCC_HSE_IsReady() != 1U)
+ {
+ /* Wait for HSE ready */
+ }
+ }
+
+ /* Configure PLL */
+#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
+ LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
+#else
+ LL_RCC_PLL_ConfigDomain_SYS((RCC_CFGR_PLLSRC_HSE_PREDIV | UTILS_PLLInitStruct->Prediv), UTILS_PLLInitStruct->PLLMul);
+#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
+
+ /* Enable PLL and switch system clock to PLL */
+ status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
+ }
+ else
+ {
+ /* Current PLL configuration cannot be modified */
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup UTILS_LL_Private_Functions
+ * @{
+ */
+/**
+ * @brief Update number of Flash wait states in line with new frequency and current
+ voltage range.
+ * @param Frequency SYSCLK frequency
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: Latency has been modified
+ * - ERROR: Latency cannot be modified
+ */
+#if defined(FLASH_ACR_LATENCY)
+static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency)
+{
+ ErrorStatus status = SUCCESS;
+
+ uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
+
+ /* Frequency cannot be equal to 0 */
+ if (Frequency == 0U)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ if (Frequency > UTILS_LATENCY2_FREQ)
+ {
+ /* 48 < SYSCLK <= 72 => 2WS (3 CPU cycles) */
+ latency = LL_FLASH_LATENCY_2;
+ }
+ else
+ {
+ if (Frequency > UTILS_LATENCY1_FREQ)
+ {
+ /* 24 < SYSCLK <= 48 => 1WS (2 CPU cycles) */
+ latency = LL_FLASH_LATENCY_1;
+ }
+ /* else SYSCLK < 24MHz default LL_FLASH_LATENCY_0 0WS */
+ }
+
+ LL_FLASH_SetLatency(latency);
+
+ /* Check that the new number of wait states is taken into account to access the Flash
+ memory by reading the FLASH_ACR register */
+ if (LL_FLASH_GetLatency() != latency)
+ {
+ status = ERROR;
+ }
+ }
+ return status;
+}
+#endif /* FLASH_ACR_LATENCY */
+
+/**
+ * @brief Function to check that PLL can be modified
+ * @param PLL_InputFrequency PLL input frequency (in Hz)
+ * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
+ * the configuration information for the PLL.
+ * @retval PLL output frequency (in Hz)
+ */
+static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
+{
+ uint32_t pllfreq = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_LL_UTILS_PLLMUL_VALUE(UTILS_PLLInitStruct->PLLMul));
+
+ /* Check different PLL parameters according to RM */
+ /* The application software must set correctly the PLL multiplication factor to
+ not exceed @ref UTILS_PLL_OUTPUT_MAX */
+#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
+ pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
+#else
+ pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / (UTILS_PLLInitStruct->Prediv + 1U), UTILS_PLLInitStruct->PLLMul);
+#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
+ assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
+
+ return pllfreq;
+}
+
+/**
+ * @brief Function to check that PLL can be modified
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: PLL modification can be done
+ * - ERROR: PLL is busy
+ */
+static ErrorStatus UTILS_PLL_IsBusy(void)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check if PLL is busy*/
+ if (LL_RCC_PLL_IsReady() != 0U)
+ {
+ /* PLL configuration cannot be modified */
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Function to enable PLL and switch system clock to PLL
+ * @param SYSCLK_Frequency SYSCLK frequency
+ * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
+ * the configuration information for the BUS prescalers.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: No problem to switch system to PLL
+ * - ERROR: Problem to switch system to PLL
+ */
+static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
+{
+ ErrorStatus status = SUCCESS;
+ uint32_t sysclk_frequency_current = 0U;
+
+ assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
+ assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
+ assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
+
+ /* Calculate current SYSCLK frequency */
+ sysclk_frequency_current = (SystemCoreClock << AHBPrescTable[LL_RCC_GetAHBPrescaler() >> RCC_POSITION_HPRE]);
+
+ /* Increasing the number of wait states because of higher CPU frequency */
+ if (sysclk_frequency_current < SYSCLK_Frequency)
+ {
+ /* Set FLASH latency to highest latency */
+ status = UTILS_SetFlashLatency(SYSCLK_Frequency);
+ }
+
+ /* Update system clock configuration */
+ if (status == SUCCESS)
+ {
+ /* Enable PLL */
+ LL_RCC_PLL_Enable();
+ while (LL_RCC_PLL_IsReady() != 1U)
+ {
+ /* Wait for PLL ready */
+ }
+
+ /* Sysclk activation on the main PLL */
+ LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
+ LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
+ while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
+ {
+ /* Wait for system clock switch to PLL */
+ }
+
+ /* Set APB1 & APB2 prescaler*/
+ LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
+ LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
+ }
+
+ /* Decreasing the number of wait states because of lower CPU frequency */
+ if (sysclk_frequency_current > SYSCLK_Frequency)
+ {
+ /* Set FLASH latency to lowest latency */
+ status = UTILS_SetFlashLatency(SYSCLK_Frequency);
+ }
+
+ /* Update SystemCoreClock variable */
+ if (status == SUCCESS)
+ {
+ LL_SetSystemCoreClock(__LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider));
+ }
+
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/_htmresc/mini-st.css b/_htmresc/mini-st.css
new file mode 100644
index 0000000..71fbc14
--- /dev/null
+++ b/_htmresc/mini-st.css
@@ -0,0 +1,1700 @@
+@charset "UTF-8";
+/*
+ Flavor name: Default (mini-default)
+ Author: Angelos Chalaris (chalarangelo@gmail.com)
+ Maintainers: Angelos Chalaris
+ mini.css version: v3.0.0-alpha.3
+*/
+/*
+ Browsers resets and base typography.
+*/
+/* Core module CSS variable definitions */
+:root {
+ --fore-color: #111;
+ --secondary-fore-color: #444;
+ --back-color: #f8f8f8;
+ --secondary-back-color: #f0f0f0;
+ --blockquote-color: #f57c00;
+ --pre-color: #1565c0;
+ --border-color: #aaa;
+ --secondary-border-color: #ddd;
+ --heading-ratio: 1.19;
+ --universal-margin: 0.5rem;
+ --universal-padding: 0.125rem;
+ --universal-border-radius: 0.125rem;
+ --a-link-color: #0277bd;
+ --a-visited-color: #01579b; }
+
+html {
+ font-size: 14px; }
+
+a, b, del, em, i, ins, q, span, strong, u {
+ font-size: 1em; }
+
+html, * {
+ font-family: -apple-system, BlinkMacSystemFont, "Segoe UI", Roboto, Ubuntu, "Helvetica Neue", Helvetica, sans-serif;
+ line-height: 1.4;
+ -webkit-text-size-adjust: 100%; }
+
+* {
+ font-size: 1rem; }
+
+body {
+ margin: 0;
+ color: var(--fore-color);
+ background: var(--back-color); }
+
+details {
+ display: block; }
+
+summary {
+ display: list-item; }
+
+abbr[title] {
+ border-bottom: none;
+ text-decoration: underline dotted; }
+
+input {
+ overflow: visible; }
+
+img {
+ max-width: 100%;
+ height: auto; }
+
+h1, h2, h3, h4, h5, h6 {
+ line-height: 1.2;
+ margin: calc(1.5 * var(--universal-margin)) var(--universal-margin);
+ font-weight: 500; }
+ h1 small, h2 small, h3 small, h4 small, h5 small, h6 small {
+ color: var(--secondary-fore-color);
+ display: block;
+ margin-top: -0.25rem; }
+
+h1 {
+ font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) * var(--heading-ratio)); }
+
+h2 {
+ font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio); );
+ background: var(--mark-back-color);
+ font-weight: 600;
+ padding: 0.1em 0.5em 0.2em 0.5em;
+ color: var(--mark-fore-color); }
+
+h3 {
+ font-size: calc(1rem * var(--heading-ratio));
+ padding-left: calc(2 * var(--universal-margin));
+ /* background: var(--border-color); */
+ }
+
+h4 {
+ font-size: 1rem;);
+ padding-left: calc(4 * var(--universal-margin)); }
+
+h5 {
+ font-size: 1rem; }
+
+h6 {
+ font-size: calc(1rem / var(--heading-ratio)); }
+
+p {
+ margin: var(--universal-margin); }
+
+ol, ul {
+ margin: var(--universal-margin);
+ padding-left: calc(6 * var(--universal-margin)); }
+
+b, strong {
+ font-weight: 700; }
+
+hr {
+ box-sizing: content-box;
+ border: 0;
+ line-height: 1.25em;
+ margin: var(--universal-margin);
+ height: 0.0625rem;
+ background: linear-gradient(to right, transparent, var(--border-color) 20%, var(--border-color) 80%, transparent); }
+
+blockquote {
+ display: block;
+ position: relative;
+ font-style: italic;
+ color: var(--secondary-fore-color);
+ margin: var(--universal-margin);
+ padding: calc(3 * var(--universal-padding));
+ border: 0.0625rem solid var(--secondary-border-color);
+ border-left: 0.375rem solid var(--blockquote-color);
+ border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; }
+ blockquote:before {
+ position: absolute;
+ top: calc(0rem - var(--universal-padding));
+ left: 0;
+ font-family: sans-serif;
+ font-size: 3rem;
+ font-weight: 700;
+ content: "\201c";
+ color: var(--blockquote-color); }
+ blockquote[cite]:after {
+ font-style: normal;
+ font-size: 0.75em;
+ font-weight: 700;
+ content: "\a— " attr(cite);
+ white-space: pre; }
+
+code, kbd, pre, samp {
+ font-family: Menlo, Consolas, monospace;
+ font-size: 0.85em; }
+
+code {
+ background: var(--secondary-back-color);
+ border-radius: var(--universal-border-radius);
+ padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); }
+
+kbd {
+ background: var(--fore-color);
+ color: var(--back-color);
+ border-radius: var(--universal-border-radius);
+ padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); }
+
+pre {
+ overflow: auto;
+ background: var(--secondary-back-color);
+ padding: calc(1.5 * var(--universal-padding));
+ margin: var(--universal-margin);
+ border: 0.0625rem solid var(--secondary-border-color);
+ border-left: 0.25rem solid var(--pre-color);
+ border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; }
+
+sup, sub, code, kbd {
+ line-height: 0;
+ position: relative;
+ vertical-align: baseline; }
+
+small, sup, sub, figcaption {
+ font-size: 0.75em; }
+
+sup {
+ top: -0.5em; }
+
+sub {
+ bottom: -0.25em; }
+
+figure {
+ margin: var(--universal-margin); }
+
+figcaption {
+ color: var(--secondary-fore-color); }
+
+a {
+ text-decoration: none; }
+ a:link {
+ color: var(--a-link-color); }
+ a:visited {
+ color: var(--a-visited-color); }
+ a:hover, a:focus {
+ text-decoration: underline; }
+
+/*
+ Definitions for the grid system, cards and containers.
+*/
+.container {
+ margin: 0 auto;
+ padding: 0 calc(1.5 * var(--universal-padding)); }
+
+.row {
+ box-sizing: border-box;
+ display: flex;
+ flex: 0 1 auto;
+ flex-flow: row wrap; }
+
+.col-sm,
+[class^='col-sm-'],
+[class^='col-sm-offset-'],
+.row[class*='cols-sm-'] > * {
+ box-sizing: border-box;
+ flex: 0 0 auto;
+ padding: 0 calc(var(--universal-padding) / 2); }
+
+.col-sm,
+.row.cols-sm > * {
+ max-width: 100%;
+ flex-grow: 1;
+ flex-basis: 0; }
+
+.col-sm-1,
+.row.cols-sm-1 > * {
+ max-width: 8.3333333333%;
+ flex-basis: 8.3333333333%; }
+
+.col-sm-offset-0 {
+ margin-left: 0; }
+
+.col-sm-2,
+.row.cols-sm-2 > * {
+ max-width: 16.6666666667%;
+ flex-basis: 16.6666666667%; }
+
+.col-sm-offset-1 {
+ margin-left: 8.3333333333%; }
+
+.col-sm-3,
+.row.cols-sm-3 > * {
+ max-width: 25%;
+ flex-basis: 25%; }
+
+.col-sm-offset-2 {
+ margin-left: 16.6666666667%; }
+
+.col-sm-4,
+.row.cols-sm-4 > * {
+ max-width: 33.3333333333%;
+ flex-basis: 33.3333333333%; }
+
+.col-sm-offset-3 {
+ margin-left: 25%; }
+
+.col-sm-5,
+.row.cols-sm-5 > * {
+ max-width: 41.6666666667%;
+ flex-basis: 41.6666666667%; }
+
+.col-sm-offset-4 {
+ margin-left: 33.3333333333%; }
+
+.col-sm-6,
+.row.cols-sm-6 > * {
+ max-width: 50%;
+ flex-basis: 50%; }
+
+.col-sm-offset-5 {
+ margin-left: 41.6666666667%; }
+
+.col-sm-7,
+.row.cols-sm-7 > * {
+ max-width: 58.3333333333%;
+ flex-basis: 58.3333333333%; }
+
+.col-sm-offset-6 {
+ margin-left: 50%; }
+
+.col-sm-8,
+.row.cols-sm-8 > * {
+ max-width: 66.6666666667%;
+ flex-basis: 66.6666666667%; }
+
+.col-sm-offset-7 {
+ margin-left: 58.3333333333%; }
+
+.col-sm-9,
+.row.cols-sm-9 > * {
+ max-width: 75%;
+ flex-basis: 75%; }
+
+.col-sm-offset-8 {
+ margin-left: 66.6666666667%; }
+
+.col-sm-10,
+.row.cols-sm-10 > * {
+ max-width: 83.3333333333%;
+ flex-basis: 83.3333333333%; }
+
+.col-sm-offset-9 {
+ margin-left: 75%; }
+
+.col-sm-11,
+.row.cols-sm-11 > * {
+ max-width: 91.6666666667%;
+ flex-basis: 91.6666666667%; }
+
+.col-sm-offset-10 {
+ margin-left: 83.3333333333%; }
+
+.col-sm-12,
+.row.cols-sm-12 > * {
+ max-width: 100%;
+ flex-basis: 100%; }
+
+.col-sm-offset-11 {
+ margin-left: 91.6666666667%; }
+
+.col-sm-normal {
+ order: initial; }
+
+.col-sm-first {
+ order: -999; }
+
+.col-sm-last {
+ order: 999; }
+
+@media screen and (min-width: 500px) {
+ .col-md,
+ [class^='col-md-'],
+ [class^='col-md-offset-'],
+ .row[class*='cols-md-'] > * {
+ box-sizing: border-box;
+ flex: 0 0 auto;
+ padding: 0 calc(var(--universal-padding) / 2); }
+
+ .col-md,
+ .row.cols-md > * {
+ max-width: 100%;
+ flex-grow: 1;
+ flex-basis: 0; }
+
+ .col-md-1,
+ .row.cols-md-1 > * {
+ max-width: 8.3333333333%;
+ flex-basis: 8.3333333333%; }
+
+ .col-md-offset-0 {
+ margin-left: 0; }
+
+ .col-md-2,
+ .row.cols-md-2 > * {
+ max-width: 16.6666666667%;
+ flex-basis: 16.6666666667%; }
+
+ .col-md-offset-1 {
+ margin-left: 8.3333333333%; }
+
+ .col-md-3,
+ .row.cols-md-3 > * {
+ max-width: 25%;
+ flex-basis: 25%; }
+
+ .col-md-offset-2 {
+ margin-left: 16.6666666667%; }
+
+ .col-md-4,
+ .row.cols-md-4 > * {
+ max-width: 33.3333333333%;
+ flex-basis: 33.3333333333%; }
+
+ .col-md-offset-3 {
+ margin-left: 25%; }
+
+ .col-md-5,
+ .row.cols-md-5 > * {
+ max-width: 41.6666666667%;
+ flex-basis: 41.6666666667%; }
+
+ .col-md-offset-4 {
+ margin-left: 33.3333333333%; }
+
+ .col-md-6,
+ .row.cols-md-6 > * {
+ max-width: 50%;
+ flex-basis: 50%; }
+
+ .col-md-offset-5 {
+ margin-left: 41.6666666667%; }
+
+ .col-md-7,
+ .row.cols-md-7 > * {
+ max-width: 58.3333333333%;
+ flex-basis: 58.3333333333%; }
+
+ .col-md-offset-6 {
+ margin-left: 50%; }
+
+ .col-md-8,
+ .row.cols-md-8 > * {
+ max-width: 66.6666666667%;
+ flex-basis: 66.6666666667%; }
+
+ .col-md-offset-7 {
+ margin-left: 58.3333333333%; }
+
+ .col-md-9,
+ .row.cols-md-9 > * {
+ max-width: 75%;
+ flex-basis: 75%; }
+
+ .col-md-offset-8 {
+ margin-left: 66.6666666667%; }
+
+ .col-md-10,
+ .row.cols-md-10 > * {
+ max-width: 83.3333333333%;
+ flex-basis: 83.3333333333%; }
+
+ .col-md-offset-9 {
+ margin-left: 75%; }
+
+ .col-md-11,
+ .row.cols-md-11 > * {
+ max-width: 91.6666666667%;
+ flex-basis: 91.6666666667%; }
+
+ .col-md-offset-10 {
+ margin-left: 83.3333333333%; }
+
+ .col-md-12,
+ .row.cols-md-12 > * {
+ max-width: 100%;
+ flex-basis: 100%; }
+
+ .col-md-offset-11 {
+ margin-left: 91.6666666667%; }
+
+ .col-md-normal {
+ order: initial; }
+
+ .col-md-first {
+ order: -999; }
+
+ .col-md-last {
+ order: 999; } }
+@media screen and (min-width: 1280px) {
+ .col-lg,
+ [class^='col-lg-'],
+ [class^='col-lg-offset-'],
+ .row[class*='cols-lg-'] > * {
+ box-sizing: border-box;
+ flex: 0 0 auto;
+ padding: 0 calc(var(--universal-padding) / 2); }
+
+ .col-lg,
+ .row.cols-lg > * {
+ max-width: 100%;
+ flex-grow: 1;
+ flex-basis: 0; }
+
+ .col-lg-1,
+ .row.cols-lg-1 > * {
+ max-width: 8.3333333333%;
+ flex-basis: 8.3333333333%; }
+
+ .col-lg-offset-0 {
+ margin-left: 0; }
+
+ .col-lg-2,
+ .row.cols-lg-2 > * {
+ max-width: 16.6666666667%;
+ flex-basis: 16.6666666667%; }
+
+ .col-lg-offset-1 {
+ margin-left: 8.3333333333%; }
+
+ .col-lg-3,
+ .row.cols-lg-3 > * {
+ max-width: 25%;
+ flex-basis: 25%; }
+
+ .col-lg-offset-2 {
+ margin-left: 16.6666666667%; }
+
+ .col-lg-4,
+ .row.cols-lg-4 > * {
+ max-width: 33.3333333333%;
+ flex-basis: 33.3333333333%; }
+
+ .col-lg-offset-3 {
+ margin-left: 25%; }
+
+ .col-lg-5,
+ .row.cols-lg-5 > * {
+ max-width: 41.6666666667%;
+ flex-basis: 41.6666666667%; }
+
+ .col-lg-offset-4 {
+ margin-left: 33.3333333333%; }
+
+ .col-lg-6,
+ .row.cols-lg-6 > * {
+ max-width: 50%;
+ flex-basis: 50%; }
+
+ .col-lg-offset-5 {
+ margin-left: 41.6666666667%; }
+
+ .col-lg-7,
+ .row.cols-lg-7 > * {
+ max-width: 58.3333333333%;
+ flex-basis: 58.3333333333%; }
+
+ .col-lg-offset-6 {
+ margin-left: 50%; }
+
+ .col-lg-8,
+ .row.cols-lg-8 > * {
+ max-width: 66.6666666667%;
+ flex-basis: 66.6666666667%; }
+
+ .col-lg-offset-7 {
+ margin-left: 58.3333333333%; }
+
+ .col-lg-9,
+ .row.cols-lg-9 > * {
+ max-width: 75%;
+ flex-basis: 75%; }
+
+ .col-lg-offset-8 {
+ margin-left: 66.6666666667%; }
+
+ .col-lg-10,
+ .row.cols-lg-10 > * {
+ max-width: 83.3333333333%;
+ flex-basis: 83.3333333333%; }
+
+ .col-lg-offset-9 {
+ margin-left: 75%; }
+
+ .col-lg-11,
+ .row.cols-lg-11 > * {
+ max-width: 91.6666666667%;
+ flex-basis: 91.6666666667%; }
+
+ .col-lg-offset-10 {
+ margin-left: 83.3333333333%; }
+
+ .col-lg-12,
+ .row.cols-lg-12 > * {
+ max-width: 100%;
+ flex-basis: 100%; }
+
+ .col-lg-offset-11 {
+ margin-left: 91.6666666667%; }
+
+ .col-lg-normal {
+ order: initial; }
+
+ .col-lg-first {
+ order: -999; }
+
+ .col-lg-last {
+ order: 999; } }
+/* Card component CSS variable definitions */
+:root {
+ --card-back-color: #f8f8f8;
+ --card-fore-color: #111;
+ --card-border-color: #ddd; }
+
+.card {
+ display: flex;
+ flex-direction: column;
+ justify-content: space-between;
+ align-self: center;
+ position: relative;
+ width: 100%;
+ background: var(--card-back-color);
+ color: var(--card-fore-color);
+ border: 0.0625rem solid var(--card-border-color);
+ border-radius: var(--universal-border-radius);
+ margin: var(--universal-margin);
+ overflow: hidden; }
+ @media screen and (min-width: 320px) {
+ .card {
+ max-width: 320px; } }
+ .card > .sectione {
+ background: var(--card-back-color);
+ color: var(--card-fore-color);
+ box-sizing: border-box;
+ margin: 0;
+ border: 0;
+ border-radius: 0;
+ border-bottom: 0.0625rem solid var(--card-border-color);
+ padding: var(--universal-padding);
+ width: 100%; }
+ .card > .sectione.media {
+ height: 200px;
+ padding: 0;
+ -o-object-fit: cover;
+ object-fit: cover; }
+ .card > .sectione:last-child {
+ border-bottom: 0; }
+
+/*
+ Custom elements for card elements.
+*/
+@media screen and (min-width: 240px) {
+ .card.small {
+ max-width: 240px; } }
+@media screen and (min-width: 480px) {
+ .card.large {
+ max-width: 480px; } }
+.card.fluid {
+ max-width: 100%;
+ width: auto; }
+
+.card.warning {
+/* --card-back-color: #ffca28; */
+ --card-back-color: #e5b8b7;
+ --card-border-color: #e8b825; }
+
+.card.error {
+ --card-back-color: #b71c1c;
+ --card-fore-color: #f8f8f8;
+ --card-border-color: #a71a1a; }
+
+.card > .sectione.dark {
+ --card-back-color: #e0e0e0; }
+
+.card > .sectione.double-padded {
+ padding: calc(1.5 * var(--universal-padding)); }
+
+/*
+ Definitions for forms and input elements.
+*/
+/* Input_control module CSS variable definitions */
+:root {
+ --form-back-color: #f0f0f0;
+ --form-fore-color: #111;
+ --form-border-color: #ddd;
+ --input-back-color: #f8f8f8;
+ --input-fore-color: #111;
+ --input-border-color: #ddd;
+ --input-focus-color: #0288d1;
+ --input-invalid-color: #d32f2f;
+ --button-back-color: #e2e2e2;
+ --button-hover-back-color: #dcdcdc;
+ --button-fore-color: #212121;
+ --button-border-color: transparent;
+ --button-hover-border-color: transparent;
+ --button-group-border-color: rgba(124, 124, 124, 0.54); }
+
+form {
+ background: var(--form-back-color);
+ color: var(--form-fore-color);
+ border: 0.0625rem solid var(--form-border-color);
+ border-radius: var(--universal-border-radius);
+ margin: var(--universal-margin);
+ padding: calc(2 * var(--universal-padding)) var(--universal-padding); }
+
+fieldset {
+ border: 0.0625rem solid var(--form-border-color);
+ border-radius: var(--universal-border-radius);
+ margin: calc(var(--universal-margin) / 4);
+ padding: var(--universal-padding); }
+
+legend {
+ box-sizing: border-box;
+ display: table;
+ max-width: 100%;
+ white-space: normal;
+ font-weight: 700;
+ padding: calc(var(--universal-padding) / 2); }
+
+label {
+ padding: calc(var(--universal-padding) / 2) var(--universal-padding); }
+
+.input-group {
+ display: inline-block; }
+ .input-group.fluid {
+ display: flex;
+ align-items: center;
+ justify-content: center; }
+ .input-group.fluid > input {
+ max-width: 100%;
+ flex-grow: 1;
+ flex-basis: 0px; }
+ @media screen and (max-width: 499px) {
+ .input-group.fluid {
+ align-items: stretch;
+ flex-direction: column; } }
+ .input-group.vertical {
+ display: flex;
+ align-items: stretch;
+ flex-direction: column; }
+ .input-group.vertical > input {
+ max-width: 100%;
+ flex-grow: 1;
+ flex-basis: 0px; }
+
+[type="number"]::-webkit-inner-spin-button, [type="number"]::-webkit-outer-spin-button {
+ height: auto; }
+
+[type="search"] {
+ -webkit-appearance: textfield;
+ outline-offset: -2px; }
+
+[type="search"]::-webkit-search-cancel-button,
+[type="search"]::-webkit-search-decoration {
+ -webkit-appearance: none; }
+
+input:not([type]), [type="text"], [type="email"], [type="number"], [type="search"],
+[type="password"], [type="url"], [type="tel"], [type="checkbox"], [type="radio"], textarea, select {
+ box-sizing: border-box;
+ background: var(--input-back-color);
+ color: var(--input-fore-color);
+ border: 0.0625rem solid var(--input-border-color);
+ border-radius: var(--universal-border-radius);
+ margin: calc(var(--universal-margin) / 2);
+ padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); }
+
+input:not([type="button"]):not([type="submit"]):not([type="reset"]):hover, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus, textarea:hover, textarea:focus, select:hover, select:focus {
+ border-color: var(--input-focus-color);
+ box-shadow: none; }
+input:not([type="button"]):not([type="submit"]):not([type="reset"]):invalid, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus:invalid, textarea:invalid, textarea:focus:invalid, select:invalid, select:focus:invalid {
+ border-color: var(--input-invalid-color);
+ box-shadow: none; }
+input:not([type="button"]):not([type="submit"]):not([type="reset"])[readonly], textarea[readonly], select[readonly] {
+ background: var(--secondary-back-color); }
+
+select {
+ max-width: 100%; }
+
+option {
+ overflow: hidden;
+ text-overflow: ellipsis; }
+
+[type="checkbox"], [type="radio"] {
+ -webkit-appearance: none;
+ -moz-appearance: none;
+ appearance: none;
+ position: relative;
+ height: calc(1rem + var(--universal-padding) / 2);
+ width: calc(1rem + var(--universal-padding) / 2);
+ vertical-align: text-bottom;
+ padding: 0;
+ flex-basis: calc(1rem + var(--universal-padding) / 2) !important;
+ flex-grow: 0 !important; }
+ [type="checkbox"]:checked:before, [type="radio"]:checked:before {
+ position: absolute; }
+
+[type="checkbox"]:checked:before {
+ content: '\2713';
+ font-family: sans-serif;
+ font-size: calc(1rem + var(--universal-padding) / 2);
+ top: calc(0rem - var(--universal-padding));
+ left: calc(var(--universal-padding) / 4); }
+
+[type="radio"] {
+ border-radius: 100%; }
+ [type="radio"]:checked:before {
+ border-radius: 100%;
+ content: '';
+ top: calc(0.0625rem + var(--universal-padding) / 2);
+ left: calc(0.0625rem + var(--universal-padding) / 2);
+ background: var(--input-fore-color);
+ width: 0.5rem;
+ height: 0.5rem; }
+
+:placeholder-shown {
+ color: var(--input-fore-color); }
+
+::-ms-placeholder {
+ color: var(--input-fore-color);
+ opacity: 0.54; }
+
+button::-moz-focus-inner, [type="button"]::-moz-focus-inner, [type="reset"]::-moz-focus-inner, [type="submit"]::-moz-focus-inner {
+ border-style: none;
+ padding: 0; }
+
+button, html [type="button"], [type="reset"], [type="submit"] {
+ -webkit-appearance: button; }
+
+button {
+ overflow: visible;
+ text-transform: none; }
+
+button, [type="button"], [type="submit"], [type="reset"],
+a.button, label.button, .button,
+a[role="button"], label[role="button"], [role="button"] {
+ display: inline-block;
+ background: var(--button-back-color);
+ color: var(--button-fore-color);
+ border: 0.0625rem solid var(--button-border-color);
+ border-radius: var(--universal-border-radius);
+ padding: var(--universal-padding) calc(1.5 * var(--universal-padding));
+ margin: var(--universal-margin);
+ text-decoration: none;
+ cursor: pointer;
+ transition: background 0.3s; }
+ button:hover, button:focus, [type="button"]:hover, [type="button"]:focus, [type="submit"]:hover, [type="submit"]:focus, [type="reset"]:hover, [type="reset"]:focus,
+ a.button:hover,
+ a.button:focus, label.button:hover, label.button:focus, .button:hover, .button:focus,
+ a[role="button"]:hover,
+ a[role="button"]:focus, label[role="button"]:hover, label[role="button"]:focus, [role="button"]:hover, [role="button"]:focus {
+ background: var(--button-hover-back-color);
+ border-color: var(--button-hover-border-color); }
+
+input:disabled, input[disabled], textarea:disabled, textarea[disabled], select:disabled, select[disabled], button:disabled, button[disabled], .button:disabled, .button[disabled], [role="button"]:disabled, [role="button"][disabled] {
+ cursor: not-allowed;
+ opacity: 0.75; }
+
+.button-group {
+ display: flex;
+ border: 0.0625rem solid var(--button-group-border-color);
+ border-radius: var(--universal-border-radius);
+ margin: var(--universal-margin); }
+ .button-group > button, .button-group [type="button"], .button-group > [type="submit"], .button-group > [type="reset"], .button-group > .button, .button-group > [role="button"] {
+ margin: 0;
+ max-width: 100%;
+ flex: 1 1 auto;
+ text-align: center;
+ border: 0;
+ border-radius: 0;
+ box-shadow: none; }
+ .button-group > :not(:first-child) {
+ border-left: 0.0625rem solid var(--button-group-border-color); }
+ @media screen and (max-width: 499px) {
+ .button-group {
+ flex-direction: column; }
+ .button-group > :not(:first-child) {
+ border: 0;
+ border-top: 0.0625rem solid var(--button-group-border-color); } }
+
+/*
+ Custom elements for forms and input elements.
+*/
+button.primary, [type="button"].primary, [type="submit"].primary, [type="reset"].primary, .button.primary, [role="button"].primary {
+ --button-back-color: #1976d2;
+ --button-fore-color: #f8f8f8; }
+ button.primary:hover, button.primary:focus, [type="button"].primary:hover, [type="button"].primary:focus, [type="submit"].primary:hover, [type="submit"].primary:focus, [type="reset"].primary:hover, [type="reset"].primary:focus, .button.primary:hover, .button.primary:focus, [role="button"].primary:hover, [role="button"].primary:focus {
+ --button-hover-back-color: #1565c0; }
+
+button.secondary, [type="button"].secondary, [type="submit"].secondary, [type="reset"].secondary, .button.secondary, [role="button"].secondary {
+ --button-back-color: #d32f2f;
+ --button-fore-color: #f8f8f8; }
+ button.secondary:hover, button.secondary:focus, [type="button"].secondary:hover, [type="button"].secondary:focus, [type="submit"].secondary:hover, [type="submit"].secondary:focus, [type="reset"].secondary:hover, [type="reset"].secondary:focus, .button.secondary:hover, .button.secondary:focus, [role="button"].secondary:hover, [role="button"].secondary:focus {
+ --button-hover-back-color: #c62828; }
+
+button.tertiary, [type="button"].tertiary, [type="submit"].tertiary, [type="reset"].tertiary, .button.tertiary, [role="button"].tertiary {
+ --button-back-color: #308732;
+ --button-fore-color: #f8f8f8; }
+ button.tertiary:hover, button.tertiary:focus, [type="button"].tertiary:hover, [type="button"].tertiary:focus, [type="submit"].tertiary:hover, [type="submit"].tertiary:focus, [type="reset"].tertiary:hover, [type="reset"].tertiary:focus, .button.tertiary:hover, .button.tertiary:focus, [role="button"].tertiary:hover, [role="button"].tertiary:focus {
+ --button-hover-back-color: #277529; }
+
+button.inverse, [type="button"].inverse, [type="submit"].inverse, [type="reset"].inverse, .button.inverse, [role="button"].inverse {
+ --button-back-color: #212121;
+ --button-fore-color: #f8f8f8; }
+ button.inverse:hover, button.inverse:focus, [type="button"].inverse:hover, [type="button"].inverse:focus, [type="submit"].inverse:hover, [type="submit"].inverse:focus, [type="reset"].inverse:hover, [type="reset"].inverse:focus, .button.inverse:hover, .button.inverse:focus, [role="button"].inverse:hover, [role="button"].inverse:focus {
+ --button-hover-back-color: #111; }
+
+button.small, [type="button"].small, [type="submit"].small, [type="reset"].small, .button.small, [role="button"].small {
+ padding: calc(0.5 * var(--universal-padding)) calc(0.75 * var(--universal-padding));
+ margin: var(--universal-margin); }
+
+button.large, [type="button"].large, [type="submit"].large, [type="reset"].large, .button.large, [role="button"].large {
+ padding: calc(1.5 * var(--universal-padding)) calc(2 * var(--universal-padding));
+ margin: var(--universal-margin); }
+
+/*
+ Definitions for navigation elements.
+*/
+/* Navigation module CSS variable definitions */
+:root {
+ --header-back-color: #f8f8f8;
+ --header-hover-back-color: #f0f0f0;
+ --header-fore-color: #444;
+ --header-border-color: #ddd;
+ --nav-back-color: #f8f8f8;
+ --nav-hover-back-color: #f0f0f0;
+ --nav-fore-color: #444;
+ --nav-border-color: #ddd;
+ --nav-link-color: #0277bd;
+ --footer-fore-color: #444;
+ --footer-back-color: #f8f8f8;
+ --footer-border-color: #ddd;
+ --footer-link-color: #0277bd;
+ --drawer-back-color: #f8f8f8;
+ --drawer-hover-back-color: #f0f0f0;
+ --drawer-border-color: #ddd;
+ --drawer-close-color: #444; }
+
+header {
+ height: 3.1875rem;
+ background: var(--header-back-color);
+ color: var(--header-fore-color);
+ border-bottom: 0.0625rem solid var(--header-border-color);
+ padding: calc(var(--universal-padding) / 4) 0;
+ white-space: nowrap;
+ overflow-x: auto;
+ overflow-y: hidden; }
+ header.row {
+ box-sizing: content-box; }
+ header .logo {
+ color: var(--header-fore-color);
+ font-size: 1.75rem;
+ padding: var(--universal-padding) calc(2 * var(--universal-padding));
+ text-decoration: none; }
+ header button, header [type="button"], header .button, header [role="button"] {
+ box-sizing: border-box;
+ position: relative;
+ top: calc(0rem - var(--universal-padding) / 4);
+ height: calc(3.1875rem + var(--universal-padding) / 2);
+ background: var(--header-back-color);
+ line-height: calc(3.1875rem - var(--universal-padding) * 1.5);
+ text-align: center;
+ color: var(--header-fore-color);
+ border: 0;
+ border-radius: 0;
+ margin: 0;
+ text-transform: uppercase; }
+ header button:hover, header button:focus, header [type="button"]:hover, header [type="button"]:focus, header .button:hover, header .button:focus, header [role="button"]:hover, header [role="button"]:focus {
+ background: var(--header-hover-back-color); }
+
+nav {
+ background: var(--nav-back-color);
+ color: var(--nav-fore-color);
+ border: 0.0625rem solid var(--nav-border-color);
+ border-radius: var(--universal-border-radius);
+ margin: var(--universal-margin); }
+ nav * {
+ padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); }
+ nav a, nav a:visited {
+ display: block;
+ color: var(--nav-link-color);
+ border-radius: var(--universal-border-radius);
+ transition: background 0.3s; }
+ nav a:hover, nav a:focus, nav a:visited:hover, nav a:visited:focus {
+ text-decoration: none;
+ background: var(--nav-hover-back-color); }
+ nav .sublink-1 {
+ position: relative;
+ margin-left: calc(2 * var(--universal-padding)); }
+ nav .sublink-1:before {
+ position: absolute;
+ left: calc(var(--universal-padding) - 1 * var(--universal-padding));
+ top: -0.0625rem;
+ content: '';
+ height: 100%;
+ border: 0.0625rem solid var(--nav-border-color);
+ border-left: 0; }
+ nav .sublink-2 {
+ position: relative;
+ margin-left: calc(4 * var(--universal-padding)); }
+ nav .sublink-2:before {
+ position: absolute;
+ left: calc(var(--universal-padding) - 3 * var(--universal-padding));
+ top: -0.0625rem;
+ content: '';
+ height: 100%;
+ border: 0.0625rem solid var(--nav-border-color);
+ border-left: 0; }
+
+footer {
+ background: var(--footer-back-color);
+ color: var(--footer-fore-color);
+ border-top: 0.0625rem solid var(--footer-border-color);
+ padding: calc(2 * var(--universal-padding)) var(--universal-padding);
+ font-size: 0.875rem; }
+ footer a, footer a:visited {
+ color: var(--footer-link-color); }
+
+header.sticky {
+ position: -webkit-sticky;
+ position: sticky;
+ z-index: 1101;
+ top: 0; }
+
+footer.sticky {
+ position: -webkit-sticky;
+ position: sticky;
+ z-index: 1101;
+ bottom: 0; }
+
+.drawer-toggle:before {
+ display: inline-block;
+ position: relative;
+ vertical-align: bottom;
+ content: '\00a0\2261\00a0';
+ font-family: sans-serif;
+ font-size: 1.5em; }
+@media screen and (min-width: 500px) {
+ .drawer-toggle:not(.persistent) {
+ display: none; } }
+
+[type="checkbox"].drawer {
+ height: 1px;
+ width: 1px;
+ margin: -1px;
+ overflow: hidden;
+ position: absolute;
+ clip: rect(0 0 0 0);
+ -webkit-clip-path: inset(100%);
+ clip-path: inset(100%); }
+ [type="checkbox"].drawer + * {
+ display: block;
+ box-sizing: border-box;
+ position: fixed;
+ top: 0;
+ width: 320px;
+ height: 100vh;
+ overflow-y: auto;
+ background: var(--drawer-back-color);
+ border: 0.0625rem solid var(--drawer-border-color);
+ border-radius: 0;
+ margin: 0;
+ z-index: 1110;
+ right: -320px;
+ transition: right 0.3s; }
+ [type="checkbox"].drawer + * .drawer-close {
+ position: absolute;
+ top: var(--universal-margin);
+ right: var(--universal-margin);
+ z-index: 1111;
+ width: 2rem;
+ height: 2rem;
+ border-radius: var(--universal-border-radius);
+ padding: var(--universal-padding);
+ margin: 0;
+ cursor: pointer;
+ transition: background 0.3s; }
+ [type="checkbox"].drawer + * .drawer-close:before {
+ display: block;
+ content: '\00D7';
+ color: var(--drawer-close-color);
+ position: relative;
+ font-family: sans-serif;
+ font-size: 2rem;
+ line-height: 1;
+ text-align: center; }
+ [type="checkbox"].drawer + * .drawer-close:hover, [type="checkbox"].drawer + * .drawer-close:focus {
+ background: var(--drawer-hover-back-color); }
+ @media screen and (max-width: 320px) {
+ [type="checkbox"].drawer + * {
+ width: 100%; } }
+ [type="checkbox"].drawer:checked + * {
+ right: 0; }
+ @media screen and (min-width: 500px) {
+ [type="checkbox"].drawer:not(.persistent) + * {
+ position: static;
+ height: 100%;
+ z-index: 1100; }
+ [type="checkbox"].drawer:not(.persistent) + * .drawer-close {
+ display: none; } }
+
+/*
+ Definitions for the responsive table component.
+*/
+/* Table module CSS variable definitions. */
+:root {
+ --table-border-color: #aaa;
+ --table-border-separator-color: #666;
+ --table-head-back-color: #e6e6e6;
+ --table-head-fore-color: #111;
+ --table-body-back-color: #f8f8f8;
+ --table-body-fore-color: #111;
+ --table-body-alt-back-color: #eee; }
+
+table {
+ border-collapse: separate;
+ border-spacing: 0;
+ : margin: calc(1.5 * var(--universal-margin)) var(--universal-margin);
+ display: flex;
+ flex: 0 1 auto;
+ flex-flow: row wrap;
+ padding: var(--universal-padding);
+ padding-top: 0;
+ margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); }
+ table caption {
+ font-size: 1.25 * rem;
+ margin: calc(2 * var(--universal-margin)) 0;
+ max-width: 100%;
+ flex: 0 0 100%;
+ text-align: left;}
+ table thead, table tbody {
+ display: flex;
+ flex-flow: row wrap;
+ border: 0.0625rem solid var(--table-border-color); }
+ table thead {
+ z-index: 999;
+ border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0;
+ border-bottom: 0.0625rem solid var(--table-border-separator-color); }
+ table tbody {
+ border-top: 0;
+ margin-top: calc(0 - var(--universal-margin));
+ border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); }
+ table tr {
+ display: flex;
+ padding: 0; }
+ table th, table td {
+ padding: calc(0.5 * var(--universal-padding));
+ font-size: 0.9rem; }
+ table th {
+ text-align: left;
+ background: var(--table-head-back-color);
+ color: var(--table-head-fore-color); }
+ table td {
+ background: var(--table-body-back-color);
+ color: var(--table-body-fore-color);
+ border-top: 0.0625rem solid var(--table-border-color); }
+
+table:not(.horizontal) {
+ overflow: auto;
+ max-height: 850px; }
+ table:not(.horizontal) thead, table:not(.horizontal) tbody {
+ max-width: 100%;
+ flex: 0 0 100%; }
+ table:not(.horizontal) tr {
+ flex-flow: row wrap;
+ flex: 0 0 100%; }
+ table:not(.horizontal) th, table:not(.horizontal) td {
+ flex: 1 0 0%;
+ overflow: hidden;
+ text-overflow: ellipsis; }
+ table:not(.horizontal) thead {
+ position: sticky;
+ top: 0; }
+ table:not(.horizontal) tbody tr:first-child td {
+ border-top: 0; }
+
+table.horizontal {
+ border: 0; }
+ table.horizontal thead, table.horizontal tbody {
+ border: 0;
+ flex-flow: row nowrap; }
+ table.horizontal tbody {
+ overflow: auto;
+ justify-content: space-between;
+ flex: 1 0 0;
+ margin-left: calc( 4 * var(--universal-margin));
+ padding-bottom: calc(var(--universal-padding) / 4); }
+ table.horizontal tr {
+ flex-direction: column;
+ flex: 1 0 auto; }
+ table.horizontal th, table.horizontal td {
+ width: 100%;
+ border: 0;
+ border-bottom: 0.0625rem solid var(--table-border-color); }
+ table.horizontal th:not(:first-child), table.horizontal td:not(:first-child) {
+ border-top: 0; }
+ table.horizontal th {
+ text-align: right;
+ border-left: 0.0625rem solid var(--table-border-color);
+ border-right: 0.0625rem solid var(--table-border-separator-color); }
+ table.horizontal thead tr:first-child {
+ padding-left: 0; }
+ table.horizontal th:first-child, table.horizontal td:first-child {
+ border-top: 0.0625rem solid var(--table-border-color); }
+ table.horizontal tbody tr:last-child td {
+ border-right: 0.0625rem solid var(--table-border-color); }
+ table.horizontal tbody tr:last-child td:first-child {
+ border-top-right-radius: 0.25rem; }
+ table.horizontal tbody tr:last-child td:last-child {
+ border-bottom-right-radius: 0.25rem; }
+ table.horizontal thead tr:first-child th:first-child {
+ border-top-left-radius: 0.25rem; }
+ table.horizontal thead tr:first-child th:last-child {
+ border-bottom-left-radius: 0.25rem; }
+
+@media screen and (max-width: 499px) {
+ table, table.horizontal {
+ border-collapse: collapse;
+ border: 0;
+ width: 100%;
+ display: table; }
+ table thead, table th, table.horizontal thead, table.horizontal th {
+ border: 0;
+ height: 1px;
+ width: 1px;
+ margin: -1px;
+ overflow: hidden;
+ padding: 0;
+ position: absolute;
+ clip: rect(0 0 0 0);
+ -webkit-clip-path: inset(100%);
+ clip-path: inset(100%); }
+ table tbody, table.horizontal tbody {
+ border: 0;
+ display: table-row-group; }
+ table tr, table.horizontal tr {
+ display: block;
+ border: 0.0625rem solid var(--table-border-color);
+ border-radius: var(--universal-border-radius);
+ background: #fafafa;
+ padding: var(--universal-padding);
+ margin: var(--universal-margin);
+ margin-bottom: calc(2 * var(--universal-margin)); }
+ table th, table td, table.horizontal th, table.horizontal td {
+ width: auto; }
+ table td, table.horizontal td {
+ display: block;
+ border: 0;
+ text-align: right; }
+ table td:before, table.horizontal td:before {
+ content: attr(data-label);
+ float: left;
+ font-weight: 600; }
+ table th:first-child, table td:first-child, table.horizontal th:first-child, table.horizontal td:first-child {
+ border-top: 0; }
+ table tbody tr:last-child td, table.horizontal tbody tr:last-child td {
+ border-right: 0; } }
+:root {
+ --table-body-alt-back-color: #eee; }
+
+table tr:nth-of-type(2n) > td {
+ background: var(--table-body-alt-back-color); }
+
+@media screen and (max-width: 500px) {
+ table tr:nth-of-type(2n) {
+ background: var(--table-body-alt-back-color); } }
+:root {
+ --table-body-hover-back-color: #90caf9; }
+
+table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td {
+ background: var(--table-body-hover-back-color); }
+
+@media screen and (max-width: 500px) {
+ table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td {
+ background: var(--table-body-hover-back-color); } }
+/*
+ Definitions for contextual background elements, toasts and tooltips.
+*/
+/* Contextual module CSS variable definitions */
+:root {
+ --mark-back-color: #0277bd;
+ --mark-fore-color: #fafafa; }
+
+mark {
+ background: var(--mark-back-color);
+ color: var(--mark-fore-color);
+ font-size: 0.95em;
+ line-height: 1em;
+ border-radius: var(--universal-border-radius);
+ padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); }
+ mark.inline-block {
+ display: inline-block;
+ font-size: 1em;
+ line-height: 1.5;
+ padding: calc(var(--universal-padding) / 2) var(--universal-padding); }
+
+:root {
+ --toast-back-color: #424242;
+ --toast-fore-color: #fafafa; }
+
+.toast {
+ position: fixed;
+ bottom: calc(var(--universal-margin) * 3);
+ left: 50%;
+ transform: translate(-50%, -50%);
+ z-index: 1111;
+ color: var(--toast-fore-color);
+ background: var(--toast-back-color);
+ border-radius: calc(var(--universal-border-radius) * 16);
+ padding: var(--universal-padding) calc(var(--universal-padding) * 3); }
+
+:root {
+ --tooltip-back-color: #212121;
+ --tooltip-fore-color: #fafafa; }
+
+.tooltip {
+ position: relative;
+ display: inline-block; }
+ .tooltip:before, .tooltip:after {
+ position: absolute;
+ opacity: 0;
+ clip: rect(0 0 0 0);
+ -webkit-clip-path: inset(100%);
+ clip-path: inset(100%);
+ transition: all 0.3s;
+ z-index: 1010;
+ left: 50%; }
+ .tooltip:not(.bottom):before, .tooltip:not(.bottom):after {
+ bottom: 75%; }
+ .tooltip.bottom:before, .tooltip.bottom:after {
+ top: 75%; }
+ .tooltip:hover:before, .tooltip:hover:after, .tooltip:focus:before, .tooltip:focus:after {
+ opacity: 1;
+ clip: auto;
+ -webkit-clip-path: inset(0%);
+ clip-path: inset(0%); }
+ .tooltip:before {
+ content: '';
+ background: transparent;
+ border: var(--universal-margin) solid transparent;
+ left: calc(50% - var(--universal-margin)); }
+ .tooltip:not(.bottom):before {
+ border-top-color: #212121; }
+ .tooltip.bottom:before {
+ border-bottom-color: #212121; }
+ .tooltip:after {
+ content: attr(aria-label);
+ color: var(--tooltip-fore-color);
+ background: var(--tooltip-back-color);
+ border-radius: var(--universal-border-radius);
+ padding: var(--universal-padding);
+ white-space: nowrap;
+ transform: translateX(-50%); }
+ .tooltip:not(.bottom):after {
+ margin-bottom: calc(2 * var(--universal-margin)); }
+ .tooltip.bottom:after {
+ margin-top: calc(2 * var(--universal-margin)); }
+
+:root {
+ --modal-overlay-color: rgba(0, 0, 0, 0.45);
+ --modal-close-color: #444;
+ --modal-close-hover-color: #f0f0f0; }
+
+[type="checkbox"].modal {
+ height: 1px;
+ width: 1px;
+ margin: -1px;
+ overflow: hidden;
+ position: absolute;
+ clip: rect(0 0 0 0);
+ -webkit-clip-path: inset(100%);
+ clip-path: inset(100%); }
+ [type="checkbox"].modal + div {
+ position: fixed;
+ top: 0;
+ left: 0;
+ display: none;
+ width: 100vw;
+ height: 100vh;
+ background: var(--modal-overlay-color); }
+ [type="checkbox"].modal + div .card {
+ margin: 0 auto;
+ max-height: 50vh;
+ overflow: auto; }
+ [type="checkbox"].modal + div .card .modal-close {
+ position: absolute;
+ top: 0;
+ right: 0;
+ width: 1.75rem;
+ height: 1.75rem;
+ border-radius: var(--universal-border-radius);
+ padding: var(--universal-padding);
+ margin: 0;
+ cursor: pointer;
+ transition: background 0.3s; }
+ [type="checkbox"].modal + div .card .modal-close:before {
+ display: block;
+ content: '\00D7';
+ color: var(--modal-close-color);
+ position: relative;
+ font-family: sans-serif;
+ font-size: 1.75rem;
+ line-height: 1;
+ text-align: center; }
+ [type="checkbox"].modal + div .card .modal-close:hover, [type="checkbox"].modal + div .card .modal-close:focus {
+ background: var(--modal-close-hover-color); }
+ [type="checkbox"].modal:checked + div {
+ display: flex;
+ flex: 0 1 auto;
+ z-index: 1200; }
+ [type="checkbox"].modal:checked + div .card .modal-close {
+ z-index: 1211; }
+
+:root {
+ --collapse-label-back-color: #e8e8e8;
+ --collapse-label-fore-color: #212121;
+ --collapse-label-hover-back-color: #f0f0f0;
+ --collapse-selected-label-back-color: #ececec;
+ --collapse-border-color: #ddd;
+ --collapse-content-back-color: #fafafa;
+ --collapse-selected-label-border-color: #0277bd; }
+
+.collapse {
+ width: calc(100% - 2 * var(--universal-margin));
+ opacity: 1;
+ display: flex;
+ flex-direction: column;
+ margin: var(--universal-margin);
+ border-radius: var(--universal-border-radius); }
+ .collapse > [type="radio"], .collapse > [type="checkbox"] {
+ height: 1px;
+ width: 1px;
+ margin: -1px;
+ overflow: hidden;
+ position: absolute;
+ clip: rect(0 0 0 0);
+ -webkit-clip-path: inset(100%);
+ clip-path: inset(100%); }
+ .collapse > label {
+ flex-grow: 1;
+ display: inline-block;
+ height: 1.5rem;
+ cursor: pointer;
+ transition: background 0.3s;
+ color: var(--collapse-label-fore-color);
+ background: var(--collapse-label-back-color);
+ border: 0.0625rem solid var(--collapse-border-color);
+ padding: calc(1.5 * var(--universal-padding)); }
+ .collapse > label:hover, .collapse > label:focus {
+ background: var(--collapse-label-hover-back-color); }
+ .collapse > label + div {
+ flex-basis: auto;
+ height: 1px;
+ width: 1px;
+ margin: -1px;
+ overflow: hidden;
+ position: absolute;
+ clip: rect(0 0 0 0);
+ -webkit-clip-path: inset(100%);
+ clip-path: inset(100%);
+ transition: max-height 0.3s;
+ max-height: 1px; }
+ .collapse > :checked + label {
+ background: var(--collapse-selected-label-back-color);
+ border-bottom-color: var(--collapse-selected-label-border-color); }
+ .collapse > :checked + label + div {
+ box-sizing: border-box;
+ position: relative;
+ width: 100%;
+ height: auto;
+ overflow: auto;
+ margin: 0;
+ background: var(--collapse-content-back-color);
+ border: 0.0625rem solid var(--collapse-border-color);
+ border-top: 0;
+ padding: var(--universal-padding);
+ clip: auto;
+ -webkit-clip-path: inset(0%);
+ clip-path: inset(0%);
+ max-height: 850px; }
+ .collapse > label:not(:first-of-type) {
+ border-top: 0; }
+ .collapse > label:first-of-type {
+ border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; }
+ .collapse > label:last-of-type:not(:first-of-type) {
+ border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); }
+ .collapse > label:last-of-type:first-of-type {
+ border-radius: var(--universal-border-radius); }
+ .collapse > :checked:last-of-type:not(:first-of-type) + label {
+ border-radius: 0; }
+ .collapse > :checked:last-of-type + label + div {
+ border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); }
+
+/*
+ Custom elements for contextual background elements, toasts and tooltips.
+*/
+mark.secondary {
+ --mark-back-color: #d32f2f; }
+
+mark.tertiary {
+ --mark-back-color: #308732; }
+
+mark.tag {
+ padding: calc(var(--universal-padding)/2) var(--universal-padding);
+ border-radius: 1em; }
+
+/*
+ Definitions for progress elements and spinners.
+*/
+/* Progess module CSS variable definitions */
+:root {
+ --progress-back-color: #ddd;
+ --progress-fore-color: #555; }
+
+progress {
+ display: block;
+ vertical-align: baseline;
+ -webkit-appearance: none;
+ -moz-appearance: none;
+ appearance: none;
+ height: 0.75rem;
+ width: calc(100% - 2 * var(--universal-margin));
+ margin: var(--universal-margin);
+ border: 0;
+ border-radius: calc(2 * var(--universal-border-radius));
+ background: var(--progress-back-color);
+ color: var(--progress-fore-color); }
+ progress::-webkit-progress-value {
+ background: var(--progress-fore-color);
+ border-top-left-radius: calc(2 * var(--universal-border-radius));
+ border-bottom-left-radius: calc(2 * var(--universal-border-radius)); }
+ progress::-webkit-progress-bar {
+ background: var(--progress-back-color); }
+ progress::-moz-progress-bar {
+ background: var(--progress-fore-color);
+ border-top-left-radius: calc(2 * var(--universal-border-radius));
+ border-bottom-left-radius: calc(2 * var(--universal-border-radius)); }
+ progress[value="1000"]::-webkit-progress-value {
+ border-radius: calc(2 * var(--universal-border-radius)); }
+ progress[value="1000"]::-moz-progress-bar {
+ border-radius: calc(2 * var(--universal-border-radius)); }
+ progress.inline {
+ display: inline-block;
+ vertical-align: middle;
+ width: 60%; }
+
+:root {
+ --spinner-back-color: #ddd;
+ --spinner-fore-color: #555; }
+
+@keyframes spinner-donut-anim {
+ 0% {
+ transform: rotate(0deg); }
+ 100% {
+ transform: rotate(360deg); } }
+.spinner {
+ display: inline-block;
+ margin: var(--universal-margin);
+ border: 0.25rem solid var(--spinner-back-color);
+ border-left: 0.25rem solid var(--spinner-fore-color);
+ border-radius: 50%;
+ width: 1.25rem;
+ height: 1.25rem;
+ animation: spinner-donut-anim 1.2s linear infinite; }
+
+/*
+ Custom elements for progress bars and spinners.
+*/
+progress.primary {
+ --progress-fore-color: #1976d2; }
+
+progress.secondary {
+ --progress-fore-color: #d32f2f; }
+
+progress.tertiary {
+ --progress-fore-color: #308732; }
+
+.spinner.primary {
+ --spinner-fore-color: #1976d2; }
+
+.spinner.secondary {
+ --spinner-fore-color: #d32f2f; }
+
+.spinner.tertiary {
+ --spinner-fore-color: #308732; }
+
+/*
+ Definitions for icons - powered by Feather (https://feathericons.com/).
+*/
+span[class^='icon-'] {
+ display: inline-block;
+ height: 1em;
+ width: 1em;
+ vertical-align: -0.125em;
+ background-size: contain;
+ margin: 0 calc(var(--universal-margin) / 4); }
+ span[class^='icon-'].secondary {
+ -webkit-filter: invert(25%);
+ filter: invert(25%); }
+ span[class^='icon-'].inverse {
+ -webkit-filter: invert(100%);
+ filter: invert(100%); }
+
+span.icon-alert {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-bookmark {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-calendar {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-credit {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-edit {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); }
+span.icon-link {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-help {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-home {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); }
+span.icon-info {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-lock {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-mail {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); }
+span.icon-location {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); }
+span.icon-phone {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M22 16.92v3a2 2 0 0 1-2.18 2 19.79 19.79 0 0 1-8.63-3.07 19.5 19.5 0 0 1-6-6 19.79 19.79 0 0 1-3.07-8.67A2 2 0 0 1 4.11 2h3a2 2 0 0 1 2 1.72 12.84 12.84 0 0 0 .7 2.81 2 2 0 0 1-.45 2.11L8.09 9.91a16 16 0 0 0 6 6l1.27-1.27a2 2 0 0 1 2.11-.45 12.84 12.84 0 0 0 2.81.7A2 2 0 0 1 22 16.92z'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-rss {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 11a9 9 0 0 1 9 9'%3E%3C/path%3E%3Cpath d='M4 4a16 16 0 0 1 16 16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); }
+span.icon-search {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-settings {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='3'%3E%3C/circle%3E%3Cpath d='M19.4 15a1.65 1.65 0 0 0 .33 1.82l.06.06a2 2 0 0 1 0 2.83 2 2 0 0 1-2.83 0l-.06-.06a1.65 1.65 0 0 0-1.82-.33 1.65 1.65 0 0 0-1 1.51V21a2 2 0 0 1-2 2 2 2 0 0 1-2-2v-.09A1.65 1.65 0 0 0 9 19.4a1.65 1.65 0 0 0-1.82.33l-.06.06a2 2 0 0 1-2.83 0 2 2 0 0 1 0-2.83l.06-.06a1.65 1.65 0 0 0 .33-1.82 1.65 1.65 0 0 0-1.51-1H3a2 2 0 0 1-2-2 2 2 0 0 1 2-2h.09A1.65 1.65 0 0 0 4.6 9a1.65 1.65 0 0 0-.33-1.82l-.06-.06a2 2 0 0 1 0-2.83 2 2 0 0 1 2.83 0l.06.06a1.65 1.65 0 0 0 1.82.33H9a1.65 1.65 0 0 0 1-1.51V3a2 2 0 0 1 2-2 2 2 0 0 1 2 2v.09a1.65 1.65 0 0 0 1 1.51 1.65 1.65 0 0 0 1.82-.33l.06-.06a2 2 0 0 1 2.83 0 2 2 0 0 1 0 2.83l-.06.06a1.65 1.65 0 0 0-.33 1.82V9a1.65 1.65 0 0 0 1.51 1H21a2 2 0 0 1 2 2 2 2 0 0 1-2 2h-.09a1.65 1.65 0 0 0-1.51 1z'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-share {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='18' cy='5' r='3'%3E%3C/circle%3E%3Ccircle cx='6' cy='12' r='3'%3E%3C/circle%3E%3Ccircle cx='18' cy='19' r='3'%3E%3C/circle%3E%3Cline x1='8.59' y1='13.51' x2='15.42' y2='17.49'%3E%3C/line%3E%3Cline x1='15.41' y1='6.51' x2='8.59' y2='10.49'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-cart {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-upload {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-user {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); }
+
+/*
+ Definitions for utilities and helper classes.
+*/
+/* Utility module CSS variable definitions */
+:root {
+ --generic-border-color: rgba(0, 0, 0, 0.3);
+ --generic-box-shadow: 0 0.25rem 0.25rem 0 rgba(0, 0, 0, 0.125), 0 0.125rem 0.125rem -0.125rem rgba(0, 0, 0, 0.25); }
+
+.hidden {
+ display: none !important; }
+
+.visually-hidden {
+ position: absolute !important;
+ width: 1px !important;
+ height: 1px !important;
+ margin: -1px !important;
+ border: 0 !important;
+ padding: 0 !important;
+ clip: rect(0 0 0 0) !important;
+ -webkit-clip-path: inset(100%) !important;
+ clip-path: inset(100%) !important;
+ overflow: hidden !important; }
+
+.bordered {
+ border: 0.0625rem solid var(--generic-border-color) !important; }
+
+.rounded {
+ border-radius: var(--universal-border-radius) !important; }
+
+.circular {
+ border-radius: 50% !important; }
+
+.shadowed {
+ box-shadow: var(--generic-box-shadow) !important; }
+
+.responsive-margin {
+ margin: calc(var(--universal-margin) / 4) !important; }
+ @media screen and (min-width: 500px) {
+ .responsive-margin {
+ margin: calc(var(--universal-margin) / 2) !important; } }
+ @media screen and (min-width: 1280px) {
+ .responsive-margin {
+ margin: var(--universal-margin) !important; } }
+
+.responsive-padding {
+ padding: calc(var(--universal-padding) / 4) !important; }
+ @media screen and (min-width: 500px) {
+ .responsive-padding {
+ padding: calc(var(--universal-padding) / 2) !important; } }
+ @media screen and (min-width: 1280px) {
+ .responsive-padding {
+ padding: var(--universal-padding) !important; } }
+
+@media screen and (max-width: 499px) {
+ .hidden-sm {
+ display: none !important; } }
+@media screen and (min-width: 500px) and (max-width: 1279px) {
+ .hidden-md {
+ display: none !important; } }
+@media screen and (min-width: 1280px) {
+ .hidden-lg {
+ display: none !important; } }
+@media screen and (max-width: 499px) {
+ .visually-hidden-sm {
+ position: absolute !important;
+ width: 1px !important;
+ height: 1px !important;
+ margin: -1px !important;
+ border: 0 !important;
+ padding: 0 !important;
+ clip: rect(0 0 0 0) !important;
+ -webkit-clip-path: inset(100%) !important;
+ clip-path: inset(100%) !important;
+ overflow: hidden !important; } }
+@media screen and (min-width: 500px) and (max-width: 1279px) {
+ .visually-hidden-md {
+ position: absolute !important;
+ width: 1px !important;
+ height: 1px !important;
+ margin: -1px !important;
+ border: 0 !important;
+ padding: 0 !important;
+ clip: rect(0 0 0 0) !important;
+ -webkit-clip-path: inset(100%) !important;
+ clip-path: inset(100%) !important;
+ overflow: hidden !important; } }
+@media screen and (min-width: 1280px) {
+ .visually-hidden-lg {
+ position: absolute !important;
+ width: 1px !important;
+ height: 1px !important;
+ margin: -1px !important;
+ border: 0 !important;
+ padding: 0 !important;
+ clip: rect(0 0 0 0) !important;
+ -webkit-clip-path: inset(100%) !important;
+ clip-path: inset(100%) !important;
+ overflow: hidden !important; } }
+
+/*# sourceMappingURL=mini-default.css.map */
diff --git a/_htmresc/st_logo.png b/_htmresc/st_logo.png
new file mode 100644
index 0000000..8b80057
--- /dev/null
+++ b/_htmresc/st_logo.png
Binary files differ
