Release v1.5.8
diff --git a/Inc/Legacy/stm32_hal_legacy.h b/Inc/Legacy/stm32_hal_legacy.h
index d990f8b..eef1d01 100644
--- a/Inc/Legacy/stm32_hal_legacy.h
+++ b/Inc/Legacy/stm32_hal_legacy.h
@@ -7,7 +7,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2023 STMicroelectronics.
+ * Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
@@ -37,16 +37,12 @@
#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
-#if defined(STM32U5) || defined(STM32H7) || defined(STM32MP1)
+#if defined(STM32H7) || defined(STM32MP1)
#define CRYP_DATATYPE_32B CRYP_NO_SWAP
#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP
#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP
#define CRYP_DATATYPE_1B CRYP_BIT_SWAP
-#if defined(STM32U5)
-#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF
-#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF
-#endif /* STM32U5 */
-#endif /* STM32U5 || STM32H7 || STM32MP1 */
+#endif /* STM32H7 || STM32MP1 */
/**
* @}
*/
@@ -279,7 +275,7 @@
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
-#if defined(STM32G4) || defined(STM32L5) || defined(STM32H7) || defined (STM32U5)
+#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5)
#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
#endif
@@ -552,6 +548,16 @@
#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE
#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE
#endif /* STM32U5 */
+#if defined(STM32U0)
+#define OB_USER_nRST_STOP OB_USER_NRST_STOP
+#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
+#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW
+#define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL
+#define OB_USER_nBOOT0 OB_USER_NBOOT0
+#define OB_USER_nBOOT1 OB_USER_NBOOT1
+#define OB_nBOOT0_RESET OB_NBOOT0_RESET
+#define OB_nBOOT0_SET OB_NBOOT0_SET
+#endif /* STM32U0 */
/**
* @}
@@ -1243,10 +1249,10 @@
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
-#if defined(STM32H5)
+#if defined(STM32H5) || defined(STM32H7RS)
#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM
-#endif /* STM32H5 */
+#endif /* STM32H5 || STM32H7RS */
#if defined(STM32WBA)
#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
@@ -1258,10 +1264,10 @@
#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL
#endif /* STM32WBA */
-#if defined(STM32H5) || defined(STM32WBA)
+#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE
#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL
-#endif /* STM32H5 || STM32WBA */
+#endif /* STM32H5 || STM32WBA || STM32H7RS */
#if defined(STM32F7)
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK
@@ -1599,6 +1605,8 @@
#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */
#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */
+#define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */
+
/**
* @}
*/
@@ -1991,12 +1999,12 @@
/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose
* @{
*/
-#if defined(STM32H5) || defined(STM32WBA)
+#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey
#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock
#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock
#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets
-#endif /* STM32H5 || STM32WBA */
+#endif /* STM32H5 || STM32WBA || STM32H7RS */
/**
* @}
@@ -2311,8 +2319,8 @@
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F302xE) || defined(STM32F302xC)
+#endif
+#if defined(STM32F302xE) || defined(STM32F302xC)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
@@ -2345,8 +2353,8 @@
((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
+#endif
+#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
@@ -2403,8 +2411,8 @@
((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F373xC) ||defined(STM32F378xx)
+#endif
+#if defined(STM32F373xC) ||defined(STM32F378xx)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
@@ -2421,7 +2429,7 @@
__HAL_COMP_COMP2_EXTI_GET_FLAG())
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
-# endif
+#endif
#else
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
@@ -2723,6 +2731,12 @@
#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
+#if defined(STM32C0)
+#define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET
+#define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET
+#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET
+#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET
+#endif /* STM32C0 */
#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
@@ -3646,8 +3660,12 @@
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
+#if defined(STM32U0)
+#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK
+#endif
+
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \
- defined(STM32WL) || defined(STM32C0)
+ defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
@@ -3749,8 +3767,10 @@
#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
+#if !defined(STM32U0)
#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
+#endif
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
@@ -3896,7 +3916,8 @@
*/
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \
defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
- defined (STM32WBA) || defined (STM32H5) || defined (STM32C0)
+ defined (STM32WBA) || defined (STM32H5) || \
+ defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
@@ -3931,6 +3952,13 @@
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
#endif /* STM32F1 */
+#if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \
+ defined (STM32H7) || \
+ defined (STM32L0) || defined (STM32L1) || \
+ defined (STM32WB)
+#define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG
+#endif
+
#define IS_ALARM IS_RTC_ALARM
#define IS_ALARM_MASK IS_RTC_ALARM_MASK
#define IS_TAMPER IS_RTC_TAMPER
diff --git a/Inc/stm32f3xx_hal_can.h b/Inc/stm32f3xx_hal_can.h
index 164d912..6c8028a 100644
--- a/Inc/stm32f3xx_hal_can.h
+++ b/Inc/stm32f3xx_hal_can.h
@@ -204,7 +204,11 @@
/**
* @brief CAN handle Structure definition
*/
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
typedef struct __CAN_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
{
CAN_TypeDef *Instance; /*!< Register base address */
diff --git a/Inc/stm32f3xx_hal_cortex.h b/Inc/stm32f3xx_hal_cortex.h
index 1350620..b705d11 100644
--- a/Inc/stm32f3xx_hal_cortex.h
+++ b/Inc/stm32f3xx_hal_cortex.h
@@ -271,6 +271,8 @@
*/
/* Peripheral Control functions ***********************************************/
#if (__MPU_PRESENT == 1U)
+void HAL_MPU_EnableRegion(uint32_t RegionNumber);
+void HAL_MPU_DisableRegion(uint32_t RegionNumber);
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
#endif /* __MPU_PRESENT */
uint32_t HAL_NVIC_GetPriorityGrouping(void);
diff --git a/Inc/stm32f3xx_hal_crc.h b/Inc/stm32f3xx_hal_crc.h
index 198cb4c..1630415 100644
--- a/Inc/stm32f3xx_hal_crc.h
+++ b/Inc/stm32f3xx_hal_crc.h
@@ -318,7 +318,7 @@
/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
* @{
*/
-HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
+HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc);
/**
* @}
*/
diff --git a/Inc/stm32f3xx_hal_i2c.h b/Inc/stm32f3xx_hal_i2c.h
index 814cb37..50642aa 100644
--- a/Inc/stm32f3xx_hal_i2c.h
+++ b/Inc/stm32f3xx_hal_i2c.h
@@ -118,8 +118,6 @@
HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
process is ongoing */
HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
- HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
- HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
} HAL_I2C_StateTypeDef;
diff --git a/Inc/stm32f3xx_hal_nand.h b/Inc/stm32f3xx_hal_nand.h
index 19d809b..9554233 100644
--- a/Inc/stm32f3xx_hal_nand.h
+++ b/Inc/stm32f3xx_hal_nand.h
@@ -24,10 +24,10 @@
extern "C" {
#endif
+#if defined(FMC_BANK3)
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_ll_fmc.h"
-#if defined(FMC_BANK3)
/** @addtogroup STM32F3xx_HAL_Driver
* @{
@@ -105,7 +105,6 @@
FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This
parameter is mandatory for some NAND parts after the read
command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
- Example: Toshiba THTH58BYG3S0HBAI6.
This parameter could be ENABLE or DISABLE
Please check the Read Mode sequence in the NAND device datasheet */
} NAND_DeviceConfigTypeDef;
diff --git a/Inc/stm32f3xx_hal_nor.h b/Inc/stm32f3xx_hal_nor.h
index 7ae9d56..992613f 100644
--- a/Inc/stm32f3xx_hal_nor.h
+++ b/Inc/stm32f3xx_hal_nor.h
@@ -24,10 +24,10 @@
extern "C" {
#endif
+#if defined(FMC_BANK1)
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_ll_fmc.h"
-#if defined(FMC_BANK1)
/** @addtogroup STM32F3xx_HAL_Driver
* @{
@@ -184,7 +184,7 @@
HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
-void HAL_NOR_MspWait(const NOR_HandleTypeDef *hnor, uint32_t Timeout);
+void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
/**
* @}
*/
@@ -235,7 +235,7 @@
/* NOR State functions ********************************************************/
HAL_NOR_StateTypeDef HAL_NOR_GetState(const NOR_HandleTypeDef *hnor);
-HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(const NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
+HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
/**
* @}
*/
diff --git a/Inc/stm32f3xx_hal_pcd.h b/Inc/stm32f3xx_hal_pcd.h
index 3a7a105..2d70b91 100644
--- a/Inc/stm32f3xx_hal_pcd.h
+++ b/Inc/stm32f3xx_hal_pcd.h
@@ -334,7 +334,7 @@
HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
-uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr);
/**
* @}
*/
@@ -343,7 +343,7 @@
/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
* @{
*/
-PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
+PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd);
/**
* @}
*/
@@ -801,20 +801,17 @@
\
*(pdwReg) &= 0x3FFU; \
\
- if ((wCount) > 62U) \
+ if ((wCount) == 0U) \
{ \
- PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \
+ *(pdwReg) |= USB_CNTRX_BLSIZE; \
+ } \
+ else if ((wCount) <= 62U) \
+ { \
+ PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \
} \
else \
{ \
- if ((wCount) == 0U) \
- { \
- *(pdwReg) |= USB_CNTRX_BLSIZE; \
- } \
- else \
- { \
- PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \
- } \
+ PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \
} \
} while(0) /* PCD_SET_EP_CNT_RX_REG */
diff --git a/Inc/stm32f3xx_hal_rtc.h b/Inc/stm32f3xx_hal_rtc.h
index 7591894..e0bcfc9 100644
--- a/Inc/stm32f3xx_hal_rtc.h
+++ b/Inc/stm32f3xx_hal_rtc.h
@@ -795,7 +795,7 @@
#define RTC_TIMEOUT_VALUE 1000U
-#define RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR_MR17 /*!< External interrupt line 17 Connected to the RTC Alarm event */
+#define RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR_MR17 /*!< External interrupt line 17 connected to the RTC Alarm event */
/**
* @}
*/
diff --git a/Inc/stm32f3xx_hal_rtc_ex.h b/Inc/stm32f3xx_hal_rtc_ex.h
index f7a1834..9642cc8 100644
--- a/Inc/stm32f3xx_hal_rtc_ex.h
+++ b/Inc/stm32f3xx_hal_rtc_ex.h
@@ -651,19 +651,6 @@
#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAFCR &= ~(__INTERRUPT__))
/**
- * @brief Check whether the specified RTC Tamper interrupt has occurred or not.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC Tamper interrupt to check.
- * This parameter can be:
- * @arg RTC_IT_TAMP1: Tamper 1 interrupt
- * @arg RTC_IT_TAMP2: Tamper 2 interrupt
- * @arg RTC_IT_TAMP3: Tamper 3 interrupt
- * @note RTC_IT_TAMP3 is not applicable to all devices.
- * @retval None
- */
-#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__) >> 4U)) != 0U) ? 1U : 0U)
-
-/**
* @brief Check whether the specified RTC Tamper interrupt has been enabled or not.
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC Tamper interrupt source to check.
@@ -680,8 +667,9 @@
* This parameter can be:
* @arg RTC_FLAG_TAMP1F: Tamper 1 interrupt flag
* @arg RTC_FLAG_TAMP2F: Tamper 2 interrupt flag
- * @arg RTC_FLAG_TAMP3F: Tamper 3 interrupt flag
- * @note RTC_FLAG_TAMP3F is not applicable to all devices.
+ * @arg RTC_FLAG_TAMP3F: Tamper 3 interrupt flag (*)
+ *
+ * (*) value not applicable to all devices.
* @retval None
*/
#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U)? 1U : 0U)
@@ -693,8 +681,9 @@
* This parameter can be:
* @arg RTC_FLAG_TAMP1F: Tamper 1 interrupt flag
* @arg RTC_FLAG_TAMP2F: Tamper 2 interrupt flag
- * @arg RTC_FLAG_TAMP3F: Tamper 3 interrupt flag
- * @note RTC_FLAG_TAMP3F is not applicable to all devices.
+ * @arg RTC_FLAG_TAMP3F: Tamper 3 interrupt flag (*)
+ *
+ * (*) value not applicable to all devices.
* @retval None
*/
#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
@@ -723,13 +712,13 @@
* @brief Enable event on the RTC Tamper and Timestamp associated EXTI line.
* @retval None.
*/
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
/**
* @brief Disable event on the RTC Tamper and Timestamp associated EXTI line.
* @retval None.
*/
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
/**
* @brief Enable falling edge trigger on the RTC Tamper and Timestamp associated EXTI line.
@@ -920,7 +909,7 @@
* @{
*/
/* Extended RTC features functions *******************************************/
-void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
/**
* @}
diff --git a/Inc/stm32f3xx_hal_smbus.h b/Inc/stm32f3xx_hal_smbus.h
index 19cef04..ef98eaa 100644
--- a/Inc/stm32f3xx_hal_smbus.h
+++ b/Inc/stm32f3xx_hal_smbus.h
@@ -100,8 +100,6 @@
#define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */
#define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */
#define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */
-#define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */
-#define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */
#define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */
/**
* @}
diff --git a/Inc/stm32f3xx_hal_spi_ex.h b/Inc/stm32f3xx_hal_spi_ex.h
index cd0f537..f4f3d00 100644
--- a/Inc/stm32f3xx_hal_spi_ex.h
+++ b/Inc/stm32f3xx_hal_spi_ex.h
@@ -48,7 +48,7 @@
/** @addtogroup SPIEx_Exported_Functions_Group1
* @{
*/
-HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi);
/**
* @}
*/
diff --git a/Inc/stm32f3xx_hal_sram.h b/Inc/stm32f3xx_hal_sram.h
index a130231..9063ecd 100644
--- a/Inc/stm32f3xx_hal_sram.h
+++ b/Inc/stm32f3xx_hal_sram.h
@@ -24,10 +24,10 @@
extern "C" {
#endif
+#if defined(FMC_BANK1)
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_ll_fmc.h"
-#if defined(FMC_BANK1)
/** @addtogroup STM32F3xx_HAL_Driver
* @{
diff --git a/Inc/stm32f3xx_hal_tim.h b/Inc/stm32f3xx_hal_tim.h
index b4ac3d4..3161101 100644
--- a/Inc/stm32f3xx_hal_tim.h
+++ b/Inc/stm32f3xx_hal_tim.h
@@ -398,7 +398,7 @@
void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */
#if defined(TIM_BDTR_BK2E)
void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */
-#endif /* */
+#endif /* TIM_BDTR_BK2E */
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
} TIM_HandleTypeDef;
@@ -408,29 +408,28 @@
*/
typedef enum
{
- HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
- , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
- , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
- , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
- , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
- , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
- , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
- , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
- , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
- , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
- , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
- , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
- , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
- , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
+ HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
+ , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
+ , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
+ , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
+ , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
+ , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
+ , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
+ , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
+ , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
+ , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
+ , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
+ , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
+ , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
+ , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
, HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
, HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
, HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
, HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
-
, HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
, HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
, HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
- , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
+ , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
, HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
, HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
, HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
@@ -1330,7 +1329,7 @@
* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
* @arg TIM_FLAG_CC5: Capture/Compare 5 interrupt flag (*)
- * @arg TIM_FLAG_CC5: Capture/Compare 6 interrupt flag (*)
+ * @arg TIM_FLAG_CC6: Capture/Compare 6 interrupt flag (*)
* @arg TIM_FLAG_COM: Commutation interrupt flag
* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
* @arg TIM_FLAG_BREAK: Break interrupt flag
@@ -1354,7 +1353,7 @@
* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
* @arg TIM_FLAG_CC5: Capture/Compare 5 interrupt flag (*)
- * @arg TIM_FLAG_CC5: Capture/Compare 6 interrupt flag (*)
+ * @arg TIM_FLAG_CC6: Capture/Compare 6 interrupt flag (*)
* @arg TIM_FLAG_COM: Commutation interrupt flag
* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
* @arg TIM_FLAG_BREAK: Break interrupt flag
@@ -1931,6 +1930,14 @@
((__PRESCALER__) == TIM_ICPSC_DIV4) || \
((__PRESCALER__) == TIM_ICPSC_DIV8))
+#if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E)
+#define IS_TIM_CCX_CHANNEL(__INSTANCE__, __CHANNEL__) (IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) && \
+ ((__CHANNEL__) != (TIM_CHANNEL_5)) && \
+ ((__CHANNEL__) != (TIM_CHANNEL_6)))
+#else
+#define IS_TIM_CCX_CHANNEL(__INSTANCE__, __CHANNEL__) (IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__))
+#endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */
+
#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \
((__MODE__) == TIM_OPMODE_REPETITIVE))
@@ -1959,8 +1966,9 @@
#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
((__CHANNEL__) == TIM_CHANNEL_2))
-#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) \
- ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : ((__PERIOD__) > 0U))
+#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \
+ (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \
+ ((__PERIOD__) > 0U))
#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
((__CHANNEL__) == TIM_CHANNEL_2) || \
@@ -2013,7 +2021,6 @@
#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
-
#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \
((__STATE__) == TIM_BREAK_DISABLE))
@@ -2450,7 +2457,8 @@
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
- uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength);
+ uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
+ uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
uint32_t BurstLength, uint32_t DataLength);
diff --git a/Inc/stm32f3xx_hal_uart_ex.h b/Inc/stm32f3xx_hal_uart_ex.h
index 058c49e..e5d9e72 100644
--- a/Inc/stm32f3xx_hal_uart_ex.h
+++ b/Inc/stm32f3xx_hal_uart_ex.h
@@ -139,7 +139,7 @@
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart);
+HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart);
/**
diff --git a/Inc/stm32f3xx_hal_usart.h b/Inc/stm32f3xx_hal_usart.h
index e4f6046..a55d1cc 100644
--- a/Inc/stm32f3xx_hal_usart.h
+++ b/Inc/stm32f3xx_hal_usart.h
@@ -469,7 +469,6 @@
#define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF)
-
/** @brief Enable the specified USART interrupt.
* @param __HANDLE__ specifies the USART Handle.
* @param __INTERRUPT__ specifies the USART interrupt source to enable.
diff --git a/Inc/stm32f3xx_hal_usart_ex.h b/Inc/stm32f3xx_hal_usart_ex.h
index aec3688..2bc28b9 100644
--- a/Inc/stm32f3xx_hal_usart_ex.h
+++ b/Inc/stm32f3xx_hal_usart_ex.h
@@ -46,10 +46,10 @@
*/
#if defined(USART_CR1_M0)&& defined(USART_CR1_M1)
#define USART_WORDLENGTH_7B (USART_CR1_M1) /*!< 7-bit long USART frame */
-#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */
+#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */
#define USART_WORDLENGTH_9B (USART_CR1_M0) /*!< 9-bit long USART frame */
#elif defined(USART_CR1_M)
-#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */
+#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */
#define USART_WORDLENGTH_9B (USART_CR1_M) /*!< 9-bit long USART frame */
#endif /* USART_CR1_M0 && USART_CR1_M */
/**
diff --git a/Inc/stm32f3xx_hal_wwdg.h b/Inc/stm32f3xx_hal_wwdg.h
index 1960f39..f238507 100644
--- a/Inc/stm32f3xx_hal_wwdg.h
+++ b/Inc/stm32f3xx_hal_wwdg.h
@@ -183,7 +183,7 @@
/**
* @brief Enable the WWDG early wakeup interrupt.
- * @param __HANDLE__ WWDG handle
+ * @param __HANDLE__: WWDG handle
* @param __INTERRUPT__ specifies the interrupt to enable.
* This parameter can be one of the following values:
* @arg WWDG_IT_EWI: Early wakeup interrupt
@@ -296,3 +296,4 @@
#endif
#endif /* STM32F3xx_HAL_WWDG_H */
+
diff --git a/Inc/stm32f3xx_ll_adc.h b/Inc/stm32f3xx_ll_adc.h
index fa1d43e..2c11ee9 100644
--- a/Inc/stm32f3xx_ll_adc.h
+++ b/Inc/stm32f3xx_ll_adc.h
@@ -8072,8 +8072,9 @@
#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ((uint32_t) 10U) /*!< Delay for internal voltage reference stabilization time */
/* Delay required between ADC disable and ADC calibration start. */
-/* Note: On this STM32 series, before starting a calibration, */
-/* ADC must be disabled. */
+/* Note: On this STM32 series, before starting a calibration, */
+/* ADC must be enabled on STM32F37x and disabled on */
+/* other STM32F3 devices. */
/* A minimum number of ADC clock cycles are required */
/* between ADC disable state and calibration start. */
/* Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES. */
diff --git a/Inc/stm32f3xx_ll_crc.h b/Inc/stm32f3xx_ll_crc.h
index f7e195a..0f818b8 100644
--- a/Inc/stm32f3xx_ll_crc.h
+++ b/Inc/stm32f3xx_ll_crc.h
@@ -184,7 +184,7 @@
* @arg @ref LL_CRC_POLYLENGTH_8B
* @arg @ref LL_CRC_POLYLENGTH_7B
*/
-__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(CRC_TypeDef *CRCx)
+__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(const CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_POLYSIZE));
}
@@ -215,7 +215,7 @@
* @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
* @arg @ref LL_CRC_INDATA_REVERSE_WORD
*/
-__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(CRC_TypeDef *CRCx)
+__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(const CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_IN));
}
@@ -242,7 +242,7 @@
* @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
* @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
*/
-__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(CRC_TypeDef *CRCx)
+__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(const CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_OUT));
}
@@ -270,7 +270,7 @@
* @param CRCx CRC Instance
* @retval Value programmed in Programmable initial CRC value register
*/
-__STATIC_INLINE uint32_t LL_CRC_GetInitialData(CRC_TypeDef *CRCx)
+__STATIC_INLINE uint32_t LL_CRC_GetInitialData(const CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_REG(CRCx->INIT));
}
@@ -301,7 +301,7 @@
* @param CRCx CRC Instance
* @retval Value programmed in Programmable Polynomial value register
*/
-__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(CRC_TypeDef *CRCx)
+__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(const CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_REG(CRCx->POL));
}
@@ -359,7 +359,7 @@
* @param CRCx CRC Instance
* @retval Current CRC calculation result as stored in CRC_DR register (32 bits).
*/
-__STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx)
+__STATIC_INLINE uint32_t LL_CRC_ReadData32(const CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_REG(CRCx->DR));
}
@@ -371,7 +371,7 @@
* @param CRCx CRC Instance
* @retval Current CRC calculation result as stored in CRC_DR register (16 bits).
*/
-__STATIC_INLINE uint16_t LL_CRC_ReadData16(CRC_TypeDef *CRCx)
+__STATIC_INLINE uint16_t LL_CRC_ReadData16(const CRC_TypeDef *CRCx)
{
return (uint16_t)READ_REG(CRCx->DR);
}
@@ -383,7 +383,7 @@
* @param CRCx CRC Instance
* @retval Current CRC calculation result as stored in CRC_DR register (8 bits).
*/
-__STATIC_INLINE uint8_t LL_CRC_ReadData8(CRC_TypeDef *CRCx)
+__STATIC_INLINE uint8_t LL_CRC_ReadData8(const CRC_TypeDef *CRCx)
{
return (uint8_t)READ_REG(CRCx->DR);
}
@@ -395,7 +395,7 @@
* @param CRCx CRC Instance
* @retval Current CRC calculation result as stored in CRC_DR register (7 bits).
*/
-__STATIC_INLINE uint8_t LL_CRC_ReadData7(CRC_TypeDef *CRCx)
+__STATIC_INLINE uint8_t LL_CRC_ReadData7(const CRC_TypeDef *CRCx)
{
return (uint8_t)(READ_REG(CRCx->DR) & 0x7FU);
}
diff --git a/Inc/stm32f3xx_ll_iwdg.h b/Inc/stm32f3xx_ll_iwdg.h
index 1f8f53c..e910704 100644
--- a/Inc/stm32f3xx_ll_iwdg.h
+++ b/Inc/stm32f3xx_ll_iwdg.h
@@ -208,7 +208,7 @@
* @arg @ref LL_IWDG_PRESCALER_128
* @arg @ref LL_IWDG_PRESCALER_256
*/
-__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx)
+__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(const IWDG_TypeDef *IWDGx)
{
return (READ_REG(IWDGx->PR));
}
@@ -231,7 +231,7 @@
* @param IWDGx IWDG Instance
* @retval Value between Min_Data=0 and Max_Data=0x0FFF
*/
-__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx)
+__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(const IWDG_TypeDef *IWDGx)
{
return (READ_REG(IWDGx->RLR));
}
@@ -254,7 +254,7 @@
* @param IWDGx IWDG Instance
* @retval Value between Min_Data=0 and Max_Data=0x0FFF
*/
-__STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx)
+__STATIC_INLINE uint32_t LL_IWDG_GetWindow(const IWDG_TypeDef *IWDGx)
{
return (READ_REG(IWDGx->WINR));
}
@@ -273,7 +273,7 @@
* @param IWDGx IWDG Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx)
+__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(const IWDG_TypeDef *IWDGx)
{
return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)) ? 1UL : 0UL);
}
@@ -284,7 +284,7 @@
* @param IWDGx IWDG Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx)
+__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(const IWDG_TypeDef *IWDGx)
{
return ((READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)) ? 1UL : 0UL);
}
@@ -295,7 +295,7 @@
* @param IWDGx IWDG Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx)
+__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(const IWDG_TypeDef *IWDGx)
{
return ((READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU)) ? 1UL : 0UL);
}
@@ -308,7 +308,7 @@
* @param IWDGx IWDG Instance
* @retval State of bits (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
+__STATIC_INLINE uint32_t LL_IWDG_IsReady(const IWDG_TypeDef *IWDGx)
{
return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU) == 0U) ? 1UL : 0UL);
}
diff --git a/Inc/stm32f3xx_ll_rtc.h b/Inc/stm32f3xx_ll_rtc.h
index 505d411..f39c392 100644
--- a/Inc/stm32f3xx_ll_rtc.h
+++ b/Inc/stm32f3xx_ll_rtc.h
@@ -415,8 +415,8 @@
/** @defgroup RTC_LL_EC_TIMESTAMP_EDGE TIMESTAMP EDGE
* @{
*/
-#define LL_RTC_TIMESTAMP_EDGE_RISING 0x00000000U /*!< RTC_TS input rising edge generates a time-stamp event */
-#define LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE /*!< RTC_TS input falling edge generates a time-stamp even */
+#define LL_RTC_TIMESTAMP_EDGE_RISING 0x00000000U /*!< RTC_TS input rising edge generates a time-stamp event */
+#define LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE /*!< RTC_TS input falling edge generates a time-stamp event */
/**
* @}
*/
diff --git a/Inc/stm32f3xx_ll_tim.h b/Inc/stm32f3xx_ll_tim.h
index dbf763a..e799626 100644
--- a/Inc/stm32f3xx_ll_tim.h
+++ b/Inc/stm32f3xx_ll_tim.h
@@ -577,7 +577,9 @@
#define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
#define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
#define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
+#if defined(TIM_SR_B2IF)
#define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */
+#endif /* TIM_SR_B2IF */
#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
@@ -654,10 +656,10 @@
/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
* @{
*/
-#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */
+#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as upcounter */
#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
-#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
+#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
/**
* @}
@@ -722,8 +724,12 @@
#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
+#if defined(TIM_CCER_CC5E)
#define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */
+#endif /* TIM_CCER_CC5E */
+#if defined(TIM_CCER_CC6E)
#define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */
+#endif /* TIM_CCER_CC6E */
#else
#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
@@ -989,11 +995,11 @@
#define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
#define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
#define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */
-#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=6 */
-#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=8 */
#define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
#define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
#define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
@@ -1854,6 +1860,17 @@
}
/**
+ * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled.
+ * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL);
+}
+
+/**
* @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
* @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
* whether or not a timer instance is able to generate a commutation event.
diff --git a/Inc/stm32f3xx_ll_usb.h b/Inc/stm32f3xx_ll_usb.h
index cd73e72..7bfaeb3 100644
--- a/Inc/stm32f3xx_ll_usb.h
+++ b/Inc/stm32f3xx_ll_usb.h
@@ -53,26 +53,26 @@
*/
typedef struct
{
- uint32_t dev_endpoints; /*!< Device Endpoints number.
+ uint8_t dev_endpoints; /*!< Device Endpoints number.
This parameter depends on the used USB core.
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
- uint32_t speed; /*!< USB Core speed.
- This parameter can be any value of @ref PCD_Speed/HCD_Speed
- (HCD_SPEED_xxx, HCD_SPEED_xxx) */
+ uint8_t speed; /*!< USB Core speed.
+ This parameter can be any value of @ref PCD_Speed/HCD_Speed
+ (HCD_SPEED_xxx, HCD_SPEED_xxx) */
- uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
+ uint8_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
- uint32_t phy_itface; /*!< Select the used PHY interface.
- This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */
+ uint8_t phy_itface; /*!< Select the used PHY interface.
+ This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */
- uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
+ uint8_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
- uint32_t low_power_enable; /*!< Enable or disable the low Power Mode. */
+ uint8_t low_power_enable; /*!< Enable or disable the low Power Mode. */
- uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */
+ uint8_t lpm_enable; /*!< Enable or disable Link Power Management. */
- uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */
+ uint8_t battery_charging_enable; /*!< Enable or disable Battery charging. */
} USB_CfgTypeDef;
typedef struct
@@ -203,6 +203,9 @@
HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode);
+HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef const *USBx);
+HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef const *USBx, uint32_t num);
+
#if defined (HAL_PCD_MODULE_ENABLED)
HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
@@ -216,14 +219,14 @@
HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx);
-uint32_t USB_ReadInterrupts(USB_TypeDef *USBx);
+uint32_t USB_ReadInterrupts(USB_TypeDef const *USBx);
HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx);
-void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf,
+void USB_WritePMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf,
uint16_t wPMABufAddr, uint16_t wNBytes);
-void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf,
+void USB_ReadPMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf,
uint16_t wPMABufAddr, uint16_t wNBytes);
/**
diff --git a/Inc/stm32f3xx_ll_wwdg.h b/Inc/stm32f3xx_ll_wwdg.h
index a486d00..4740766 100644
--- a/Inc/stm32f3xx_ll_wwdg.h
+++ b/Inc/stm32f3xx_ll_wwdg.h
@@ -131,7 +131,7 @@
* @param WWDGx WWDG Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx)
+__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(const WWDG_TypeDef *WWDGx)
{
return ((READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)) ? 1UL : 0UL);
}
@@ -158,7 +158,7 @@
* @param WWDGx WWDG Instance
* @retval 7 bit Watchdog Counter value
*/
-__STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)
+__STATIC_INLINE uint32_t LL_WWDG_GetCounter(const WWDG_TypeDef *WWDGx)
{
return (READ_BIT(WWDGx->CR, WWDG_CR_T));
}
@@ -191,7 +191,7 @@
* @arg @ref LL_WWDG_PRESCALER_4
* @arg @ref LL_WWDG_PRESCALER_8
*/
-__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx)
+__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(const WWDG_TypeDef *WWDGx)
{
return (READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
}
@@ -223,7 +223,7 @@
* @param WWDGx WWDG Instance
* @retval 7 bit Watchdog Window value
*/
-__STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
+__STATIC_INLINE uint32_t LL_WWDG_GetWindow(const WWDG_TypeDef *WWDGx)
{
return (READ_BIT(WWDGx->CFR, WWDG_CFR_W));
}
@@ -244,7 +244,7 @@
* @param WWDGx WWDG Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx)
+__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(const WWDG_TypeDef *WWDGx)
{
return ((READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)) ? 1UL : 0UL);
}
@@ -286,7 +286,7 @@
* @param WWDGx WWDG Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx)
+__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(const WWDG_TypeDef *WWDGx)
{
return ((READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)) ? 1UL : 0UL);
}
diff --git a/Release_Notes.html b/Release_Notes.html
index dc1e461..cc683a7 100644
--- a/Release_Notes.html
+++ b/Release_Notes.html
@@ -39,17 +39,128 @@
<div class="col-sm-12 col-lg-8">
<h1 id="update-history"><strong>Update History</strong></h1>
<div class="collapse">
-<input type="checkbox" id="collapse-section1_5_7" checked aria-hidden="true"> <label for="collapse-section1_5_7" aria-hidden="true"><strong>V1.5.7 / 27-January-2023</strong></label>
+<input type="checkbox" id="collapse-section1_5_8" checked aria-hidden="true"> <label for="collapse-section1_5_8" aria-hidden="true"><strong>V1.5.8 / 29-March-2024</strong></label>
<div>
<h2 id="main-changes">Main Changes</h2>
<ul>
<li>General updates to fix known defects and implementation enhancements.</li>
-<li>HAL code quality enhancement for MISRA-C Rule-8.13 by adding const qualifiers</li>
</ul>
<h2 id="contents">Contents</h2>
<ul>
<li><strong>HAL Generic</strong> update
<ul>
+<li>Add missing call to UNUSED() macro to avoid compilation warnings related to the unused arguments for the following HAL drivers: <strong>ADC, PWR, RCC</strong></li>
+<li>HAL code quality enhancement for MISRA-C Rule-8.13 by adding const qualifiers.</li>
+</ul></li>
+<li><strong>HAL FLASH</strong>
+<ul>
+<li>Correct the setting of option byte OB->WRPx in FLASH_OB_DisableWRP() API and apply MCUAstyle fixes</li>
+</ul></li>
+<li><strong>HAL CORTEX</strong>
+<ul>
+<li>Updated HAL_MPU_ConfigRegion() to allow the configuration of the MPU registers independently of the value of Enable/Disable field.</li>
+<li>Add new APIs HAL_MPU_EnableRegion() / HAL_MPU_DisableRegion().</li>
+</ul></li>
+<li><strong>HAL GPIO</strong>
+<ul>
+<li>Replace GPIO_Pin_x with GPIO_PIN_x to be compliant with macros definition</li>
+</ul></li>
+<li><strong>LL/HAL RTC_BKP</strong>
+<ul>
+<li>Remove macro __HAL_RTC_TAMPER_GET_IT() as it is redundant with macro __HAL_RTC_TAMPER_GET_FLAG() and create an alias into the hal_legacy.h file</li>
+<li>Correct misleading note about shadow registers</li>
+</ul></li>
+<li><strong>LL/HAL ADC</strong>
+<ul>
+<li>Update description of LL_ADC_DELAY_DISABLE_CALIB_ADC_CYCLES to be aligned with STM32F3 reference manual</li>
+</ul></li>
+<li><strong>HAL COMP</strong>
+<ul>
+<li>Update APIs HAL_COMP_Init() and HAL_COMP_Start() to add a delay for startup time as mentioned in the datasheet</li>
+</ul></li>
+<li><strong>LL/HAL I2C</strong>
+<ul>
+<li>Update HAL I2C driver to prefetch data before starting the transmission: implementation of errata sheet workaround I2C2-190208 : Transmission stalled after first byte</li>
+<li>Update HAL I2C driver to disable all interrupts after end of transaction.</li>
+<li>Update HAL_I2C_Init API to clear ADD10 bit in 7 bit addressing mode.</li>
+<li>Update HAL_I2C_Mem_Write_IT API to initialize XferSize at 0.</li>
+<li>Update I2C_Slave_ISR_IT, I2C_Slave_ISR_DMA and I2C_ITSlaveCplt to prevent the call of HAL_I2C_ListenCpltCallback twice.</li>
+<li>Update I2C_WaitOnRXNEFlagUntilTimeout to check I2C_FLAG_AF independently from I2C_FLAG_RXNE.</li>
+<li>In function HAL_I2C_IsDeviceReady, remove the unusable code.</li>
+<li>Update I2C_WaitOnFlagUntilTimeout to handle error case.</li>
+<li>Update the HAL I2C driver to implement the errata workaround "Last-received byte loss in reload mode"</li>
+<li>Update HAL_I2C_Slave_Transmit to check if the received NACK is the good one.</li>
+<li>Update LL_I2C_HandleTranfer() function to prevent undefined behavior of volatile before updating the CR2 register.</li>
+</ul></li>
+<li><strong>HAL SMBUS</strong>
+<ul>
+<li>Update HAL SMBUS driver to prefetch data before starting the transmission: implementation of errata sheet workaround I2C2-190208 : Transmission stalled after first byte</li>
+<li>Update SMBUS_ITErrorHandler to flash TXDR just in case of error</li>
+</ul></li>
+<li><strong>HAL UART</strong>
+<ul>
+<li>Update initialisation sequence for TXINV, RXINV and TXRXSWAP settings</li>
+<li>Fix incorrect gState check in HAL_UART_RegisterRxEventCallback/HAL_UART_UnRegisterRxEventCallback to allow user Rx Event Callback registration when a transmit is ongoing</li>
+<li>Avoid RTOF flag to be cleared by a transmit process in polling mode</li>
+</ul></li>
+<li><strong>HAL SPI</strong>
+<ul>
+<li>Update HAL_SPI_TransmitReceive API to set the bit CRCNEXT in case of one byte transaction.</li>
+<li>Update IT API to enable interrupts after process unlock.</li>
+</ul></li>
+<li><strong>HAL I2S</strong>
+<ul>
+<li>Update HAL I2S driver to fix misplaced __HAL_LOCK and remove ‘go to’ instruction</li>
+</ul></li>
+<li><strong>LL/HAL TIM</strong>
+<ul>
+<li>Remove multiple volatile reads from interrupt handler for better performance.</li>
+<li>Assert check for the right channels.</li>
+<li>Update interrupt flag is cleared when the update event is generated by software.</li>
+<li>Improved period configuration parameter check</li>
+<li>HAL TIM driver’s operational behavior improvement</li>
+<li>Minor typo correction in hal_tim header file</li>
+<li>Fix typo in PWM symmetric mode related constants names</li>
+<li>Remove unnecessary change of MOE bitfield in LL_TIM_BDTR_Init()</li>
+<li>Remove useless check on IS_TIM_ADVANCED_INSTANCE() within LL_TIM_BDTR_Init() to fix Break Filter configuration problem with specific TIM instances</li>
+<li>LL_TIM UM generation fix</li>
+<li>User manual quality improvement</li>
+<li>MISRA warning fix</li>
+<li>Add LL_TIM_CC_IsEnabledPreload() function</li>
+<li>Add system break interrupt handling in IRQ handler</li>
+<li>Make APIs HAL_TIMEx_OCN_Stop_IT() and HAL_TIMEx_PWMN_Stop_IT() more generic</li>
+<li>Assert check for the right channels</li>
+<li>Improve CH4N support handling</li>
+<li>Improve API LL_TIM_BDTR_Init() implementation consistency</li>
+</ul></li>
+<li><strong>HAL CAN</strong>
+<ul>
+<li>Clarify pin configuration in driver header by removing open-drain info</li>
+<li>Put __CAN_HandleTypeDef definition under a compilation condition to avoid MISRAC2012-Rule-2.4 violation</li>
+</ul></li>
+<li><strong>HAL USB_OTG</strong>
+<ul>
+<li>Add new HAL_PCD_EP_Abort() API to abort current USB endpoint transfer.</li>
+</ul></li>
+<li><strong>LL UTILS</strong>
+<ul>
+<li>Fix a note about Ticks parameter</li>
+</ul></li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section1_5_7" aria-hidden="true"> <label for="collapse-section1_5_7" aria-hidden="true"><strong>V1.5.7 / 27-January-2023</strong></label>
+<div>
+<h2 id="main-changes-1">Main Changes</h2>
+<ul>
+<li>General updates to fix known defects and implementation enhancements.</li>
+<li>HAL code quality enhancement for MISRA-C Rule-8.13 by adding const qualifiers</li>
+</ul>
+<h2 id="contents-1">Contents</h2>
+<ul>
+<li><strong>HAL Generic</strong> update
+<ul>
<li>Allow redefinition of macro UNUSED(x).</li>
</ul></li>
<li><strong>HAL RCC</strong> update
@@ -76,9 +187,12 @@
<ul>
<li>Better performance by removing multiple volatile reads or writes in interrupt handler.</li>
</ul></li>
-<li><strong>LL/HAL TIM</strong> update
+<li><strong>HAL TIM</strong> update
<ul>
<li>Fix HAL_TIMEx_RemapConfig() lock issue: __HAL_LOCK is called before calls to assert_param().</li>
+</ul></li>
+<li><strong>LL TIM</strong> update
+<ul>
<li>__LL_TIM_CALC_PSC() macro update to round up the evaluate value when the fractional part of the division is greater than 0.5.</li>
<li>Remove useless check on IS_TIM_ADVANCED_INSTANCE() within LL_TIM_BDTR_Init() to fix Break Filter configuration problem with specific TIM instances</li>
</ul></li>
@@ -87,6 +201,7 @@
<li>Removal of never reached code</li>
<li>Improve protection against bad inputs</li>
</ul></li>
+<li><strong>HAL TSC</strong> update</li>
<li><strong>HAL RTC_BKP</strong> update
<ul>
<li>Use bits definitions from CMSIS Device header file instead of hard-coded values.</li>
@@ -130,11 +245,14 @@
<li>Add const qualifier for read only pointers.</li>
<li>Fix wrong cast when computing the USARTDIV value in IRDA_SetConfig().</li>
</ul></li>
-<li><strong>LL/HAL USART</strong> update
+<li><strong>HAL USART</strong> update
<ul>
<li>Improve header description of USART_WaitOnFlagUntilTimeout() function</li>
<li>Add a check on the USART parity before enabling the parity error interrupt.</li>
<li>Add const qualifier for read only pointers.</li>
+</ul></li>
+<li><strong>LL USART</strong> update
+<ul>
<li>Fix compilation warnings generated with ARMV6 compiler.</li>
</ul></li>
<li><strong>HAL SPI</strong> update
@@ -171,11 +289,11 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_5_6" aria-hidden="true"> <label for="collapse-section1_5_6" aria-hidden="true"><strong>V1.5.6 / 23-July-2021</strong></label>
<div>
-<h2 id="main-changes-1">Main Changes</h2>
+<h2 id="main-changes-2">Main Changes</h2>
<ul>
<li>General updates to fix known defects and enhancements implementation.</li>
</ul>
-<h2 id="contents-1">Contents</h2>
+<h2 id="contents-2">Contents</h2>
<ul>
<li><strong>HAL GPIO</strong> driver
<ul>
@@ -268,11 +386,11 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_5_5" aria-hidden="true"> <label for="collapse-section1_5_5" aria-hidden="true"><strong>V1.5.5 / 10-November-2020</strong></label>
<div>
-<h2 id="main-changes-2">Main Changes</h2>
+<h2 id="main-changes-3">Main Changes</h2>
<ul>
<li>General updates to fix known defects and enhancements implementation.</li>
</ul>
-<h2 id="contents-2">Contents</h2>
+<h2 id="contents-3">Contents</h2>
<ul>
<li><strong>HAL</strong> driver update
<ul>
@@ -496,11 +614,11 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_5_4" aria-hidden="true"> <label for="collapse-section1_5_4" aria-hidden="true"><strong>V1.5.4 / 23-July-2020</strong></label>
<div>
-<h2 id="main-changes-3">Main Changes</h2>
+<h2 id="main-changes-4">Main Changes</h2>
<ul>
<li>General updates to fix known defects and enhancements implementation</li>
</ul>
-<h2 id="contents-3">Contents</h2>
+<h2 id="contents-4">Contents</h2>
<ul>
<li><strong>HAL/LL GPIO</strong> update
<ul>
@@ -538,7 +656,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_5_3" aria-hidden="true"> <label for="collapse-section1_5_3" aria-hidden="true"><strong>V1.5.3 / 12-September-2019</strong></label>
<div>
-<h2 id="main-changes-4">Main Changes</h2>
+<h2 id="main-changes-5">Main Changes</h2>
<ul>
<li>General updates to fix known defects and enhancements implementation</li>
<li>Add support of HAL callback registration feature</li>
@@ -568,7 +686,7 @@
</ul></li>
<li><strong>HAL CRC</strong> update
<ul>
-<li>Remove extra call to HAL_LOCK/HAL_UNLOCK from the following API’s:
+<li>Remove extra call to HAL_LOCK/HAL_UNLOCK from the followings API’s:
<ul>
<li>HAL_CRC_Accumulate()</li>
<li>HAL_CRC_Calculate()</li>
@@ -804,7 +922,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_5_2" aria-hidden="true"> <label for="collapse-section1_5_2" aria-hidden="true"><strong>V1.5.2 / 12-June-2018</strong></label>
<div>
-<h2 id="main-changes-5">Main Changes</h2>
+<h2 id="main-changes-6">Main Changes</h2>
<ul>
<li><strong>Maintenance release to fix known defects and enhancements implementation</strong></li>
<li><strong>Generic drivers changes</strong></li>
@@ -900,7 +1018,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_5_1" aria-hidden="true"> <label for="collapse-section1_5_1" aria-hidden="true"><strong>V1.5.1 / 11-May-2018</strong></label>
<div>
-<h2 id="main-changes-6">Main Changes</h2>
+<h2 id="main-changes-7">Main Changes</h2>
<ul>
<li>General updates to fix known defects and enhancements implementation</li>
<li><strong>HAL Drivers changes</strong></li>
@@ -1001,7 +1119,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_5_0" aria-hidden="true"> <label for="collapse-section1_5_0" aria-hidden="true"><strong>V1.5.0 / 23-June-2017</strong></label>
<div>
-<h2 id="main-changes-7">Main Changes</h2>
+<h2 id="main-changes-8">Main Changes</h2>
<ul>
<li><strong>Maintenance release to fix known defects and enhancements implementation</strong></li>
<li><strong>Generic drivers changes</strong></li>
@@ -1140,7 +1258,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_4_0" aria-hidden="true"> <label for="collapse-section1_4_0" aria-hidden="true"><strong>V1.4.0 / 16-December-2016</strong></label>
<div>
-<h2 id="main-changes-8">Main Changes</h2>
+<h2 id="main-changes-9">Main Changes</h2>
<ul>
<li><strong>Maintenance release to fix known defects and enhancements implementation</strong></li>
<li><strong>HAL Drivers changes</strong></li>
@@ -1352,7 +1470,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_3_0" aria-hidden="true"> <label for="collapse-section1_3_0" aria-hidden="true"><strong>V1.3.0 / 01-July-2016</strong></label>
<div>
-<h2 id="main-changes-9">Main Changes</h2>
+<h2 id="main-changes-10">Main Changes</h2>
<ul>
<li><strong>First official release supporting the Low Level drivers for the STM32F3xx series:</strong>
<ul>
@@ -1438,7 +1556,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_2_1" aria-hidden="true"> <label for="collapse-section1_2_1" aria-hidden="true"><strong>V1.2.1 / 29-April-2016</strong></label>
<div>
-<h2 id="main-changes-10">Main Changes</h2>
+<h2 id="main-changes-11">Main Changes</h2>
<ul>
<li><strong>Maintenance release to fix known defects and enhancements implementation.</strong></li>
<li><strong>HAL generic</strong>
@@ -1524,7 +1642,7 @@
<li>Modified reset of Backup domain only if the RTC Clock source selection is modified from reset value.</li>
<li>Updated HAL_RCC_OscConfig() function (Reset HSEON/LSEON and HSEBYP/LSEBYP bits before configuring the HSE/LSE).</li>
<li>Corrected updates of SystemCoreClock variable within the HAL drivers.</li>
-<li>Corrected inversion in LSE drive capability Bit definition.</li>
+<li>Corrected invertion in LSE drive capability Bit definition.</li>
<li>Modified AHBPrescTable and APBPrescTable in HAL.</li>
<li>Removed RCC_CFGR_PLLNODIV bit definition from STM32F358xx, STM32F303xC and STM32F302xC devices.</li>
<li>Removed RCC_CSR_VREGRSTF bit definition in RCC_CSR register for STM32F303xC and STM32F303xE devices.</li>
@@ -1585,7 +1703,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_2_0" aria-hidden="true"> <label for="collapse-section1_2_0" aria-hidden="true"><strong>V1.2.0 / 13-November-2015</strong></label>
<div>
-<h2 id="main-changes-11">Main Changes</h2>
+<h2 id="main-changes-12">Main Changes</h2>
<ul>
<li><strong>Performed HAL API alignment (macros/functions/constants renaming).</strong></li>
<li><strong>HAL generic</strong>
@@ -1767,7 +1885,7 @@
</ul></li>
<li><strong>HAL SDADC</strong>
<ul>
-<li>Applied ReferenceVoltage parameter in HAL_SDADC_Init() whatever instance.</li>
+<li>Applied ReferenceVoltage parameter in HAL_SDADC_Init() wathever instance.</li>
<li>Added new macros __HAL_SDADC_ENABLE_IT(), __HAL_SDADC_GET_IT_SOURCE(), __HAL_SDADC_GET_FLAG().</li>
</ul></li>
<li><strong>HAL SMARTCARD</strong>
@@ -1848,7 +1966,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_1_1" aria-hidden="true"> <label for="collapse-section1_1_1" aria-hidden="true"><strong>V1.1.1 / 19-June-2015</strong></label>
<div>
-<h2 id="main-changes-12">Main Changes</h2>
+<h2 id="main-changes-13">Main Changes</h2>
<ul>
<li>Fixed compilation warnings reported by TrueSTUDIO and SW4STM32 toolchains.</li>
</ul>
@@ -1857,7 +1975,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_1_0" aria-hidden="true"> <label for="collapse-section1_1_0" aria-hidden="true"><strong>V1.1.0 / 12-September-2014</strong></label>
<div>
-<h2 id="main-changes-13">Main Changes</h2>
+<h2 id="main-changes-14">Main Changes</h2>
<ul>
<li><strong>First official release of STM32F3xx HAL drivers for STM32F303xE, STM32F302xE and STM32F398xx devices.</strong></li>
<li><strong>HAL generic</strong> update
@@ -1910,7 +2028,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_1_0_rc2" aria-hidden="true"> <label for="collapse-section1_1_0_rc2" aria-hidden="true"><strong>V1.5.2RC2 / 25-August-2014</strong></label>
<div>
-<h2 id="main-changes-14">Main Changes</h2>
+<h2 id="main-changes-15">Main Changes</h2>
<ul>
<li><strong>HAL generic</strong> update
<ul>
@@ -2049,7 +2167,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_0_1" aria-hidden="true"> <label for="collapse-section1_0_1" aria-hidden="true"><strong>V1.0.1 / 18-June-2014</strong></label>
<div>
-<h2 id="main-changes-15">Main Changes</h2>
+<h2 id="main-changes-16">Main Changes</h2>
<ul>
<li><strong>HAL generic</strong> update
<ul>
@@ -2163,7 +2281,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_0_0" aria-hidden="true"> <label for="collapse-section1_0_0" aria-hidden="true"><strong>V1.0.0 / 06-May-2014</strong></label>
<div>
-<h2 id="main-changes-16">Main Changes</h2>
+<h2 id="main-changes-17">Main Changes</h2>
<ul>
<li>First official release of STM32F3xx HAL drivers for <strong>STM32F301x6/x8, STM32F302x6/x8, STM32F302xB/xC, STM32F303x6/x8, STM32F373xB/xC, STM32F334x4/x6/x8, STM32F318xx, STM32F328xx, STM32F358xx and STM32F378xx devices.</strong></li>
</ul>
diff --git a/Src/stm32f3xx_hal.c b/Src/stm32f3xx_hal.c
index 68d8338..04f2a0b 100644
--- a/Src/stm32f3xx_hal.c
+++ b/Src/stm32f3xx_hal.c
@@ -56,7 +56,7 @@
*/
#define __STM32F3xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32F3xx_HAL_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */
-#define __STM32F3xx_HAL_VERSION_SUB2 (0x07U) /*!< [15:8] sub2 version */
+#define __STM32F3xx_HAL_VERSION_SUB2 (0x08U) /*!< [15:8] sub2 version */
#define __STM32F3xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F3xx_HAL_VERSION ((__STM32F3xx_HAL_VERSION_MAIN << 24U)\
|(__STM32F3xx_HAL_VERSION_SUB1 << 16U)\
diff --git a/Src/stm32f3xx_hal_comp.c b/Src/stm32f3xx_hal_comp.c
index 0300186..7bcc140 100644
--- a/Src/stm32f3xx_hal_comp.c
+++ b/Src/stm32f3xx_hal_comp.c
@@ -301,6 +301,20 @@
*/
#define COMP_LOCK_DISABLE (0x00000000U)
#define COMP_LOCK_ENABLE COMP_CSR_COMPxLOCK
+
+/* Delay for COMP startup time. */
+/* Note: Delay required to reach propagation delay specification. */
+/* Literal set to maximum value (refer to device datasheet, */
+/* parameter "tSTART"). */
+/* Unit: us */
+#define COMP_DELAY_STARTUP_US (80UL) /*!< Delay for COMP startup time */
+
+/* Delay for COMP voltage scaler stabilization time. */
+/* Literal set to maximum value (refer to device datasheet, */
+/* parameter "tSTART_SCALER"). */
+/* Unit: us */
+#define COMP_DELAY_VOLTAGE_SCALER_STAB_US (200UL) /*!< Delay for COMP voltage scaler stabilization time */
+
/**
* @}
*/
@@ -337,6 +351,8 @@
*/
HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
{
+ uint32_t comp_voltage_scaler_initialized; /* Value "0" if comparator voltage scaler is not initialized */
+ __IO uint32_t wait_loop_index = 0UL;
HAL_StatusTypeDef status = HAL_OK;
/* Check the COMP handle allocation and lock status */
@@ -385,6 +401,9 @@
HAL_COMP_MspInit(hcomp);
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
+ /* Memorize voltage scaler state before initialization */
+ comp_voltage_scaler_initialized = READ_BIT(hcomp->Instance->CSR, (COMP_CSR_COMPxINSEL_1 | COMP_CSR_COMPxINSEL_0));
+
if (hcomp->State == HAL_COMP_STATE_RESET)
{
/* Allocate lock resource and initialize it */
@@ -405,6 +424,22 @@
/* Set COMPxMODE bits according to hcomp->Init.Mode value */
COMP_INIT(hcomp);
+ /* Delay for COMP scaler bridge voltage stabilization */
+ /* Apply the delay if voltage scaler bridge is required and not already enabled */
+ if ((READ_BIT(hcomp->Instance->CSR, (COMP_CSR_COMPxINSEL_1 | COMP_CSR_COMPxINSEL_0)) != 0UL) &&
+ (comp_voltage_scaler_initialized == 0UL))
+ {
+ /* Wait loop initialization and execution */
+ /* Note: Variable divided by 2 to compensate partially */
+ /* CPU processing cycles, scaling in us split to not */
+ /* exceed 32 bits register capacity and handle low frequency. */
+ wait_loop_index = ((COMP_DELAY_VOLTAGE_SCALER_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
+ while (wait_loop_index != 0UL)
+ {
+ wait_loop_index--;
+ }
+ }
+
/* Initialize the COMP state*/
hcomp->State = HAL_COMP_STATE_READY;
}
@@ -677,6 +712,7 @@
*/
HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
{
+ __IO uint32_t wait_loop_index = 0UL;
HAL_StatusTypeDef status = HAL_OK;
uint32_t extiline = 0U;
@@ -729,6 +765,17 @@
__HAL_COMP_ENABLE(hcomp);
hcomp->State = HAL_COMP_STATE_BUSY;
+
+ /* Delay for COMP startup time */
+ /* Wait loop initialization and execution */
+ /* Note: Variable divided by 2 to compensate partially */
+ /* CPU processing cycles, scaling in us split to not */
+ /* exceed 32 bits register capacity and handle low frequency. */
+ wait_loop_index = ((COMP_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
+ while (wait_loop_index != 0UL)
+ {
+ wait_loop_index--;
+ }
}
else
{
diff --git a/Src/stm32f3xx_hal_cortex.c b/Src/stm32f3xx_hal_cortex.c
index 0998036..086ab87 100644
--- a/Src/stm32f3xx_hal_cortex.c
+++ b/Src/stm32f3xx_hal_cortex.c
@@ -309,10 +309,42 @@
/* Enable fault exceptions */
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
}
-
- /**
+
+/**
+ * @brief Enables the MPU Region.
+ * @retval None
+ */
+void HAL_MPU_EnableRegion(uint32_t RegionNumber)
+{
+ /* Check the parameters */
+ assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
+
+ /* Set the Region number */
+ MPU->RNR = RegionNumber;
+
+ /* Enable the Region */
+ SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
+/**
+ * @brief Disables the MPU Region.
+ * @retval None
+ */
+void HAL_MPU_DisableRegion(uint32_t RegionNumber)
+{
+ /* Check the parameters */
+ assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
+
+ /* Set the Region number */
+ MPU->RNR = RegionNumber;
+
+ /* Disable the Region */
+ CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
+/**
* @brief Initializes and configures the Region and the memory to be protected.
- * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
+ * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
* the initialization and configuration information.
* @retval None
*/
@@ -321,38 +353,32 @@
/* Check the parameters */
assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
+ assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
+ assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
+ assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
+ assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
+ assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
+ assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
+ assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
+ assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
/* Set the Region number */
MPU->RNR = MPU_Init->Number;
- if ((MPU_Init->Enable) != RESET)
- {
- /* Check the parameters */
- assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
- assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
- assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
- assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
- assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
- assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
- assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
- assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
-
- MPU->RBAR = MPU_Init->BaseAddress;
- MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
- ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
- ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
- ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
- ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
- ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
- ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
- ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
- ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
- }
- else
- {
- MPU->RBAR = 0x00U;
- MPU->RASR = 0x00U;
- }
+ /* Disable the Region */
+ CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+
+ /* Apply configuration */
+ MPU->RBAR = MPU_Init->BaseAddress;
+ MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
+ ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
+ ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
+ ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
+ ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
+ ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
+ ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
+ ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
+ ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
}
#endif /* __MPU_PRESENT */
diff --git a/Src/stm32f3xx_hal_crc.c b/Src/stm32f3xx_hal_crc.c
index b41de22..8701b61 100644
--- a/Src/stm32f3xx_hal_crc.c
+++ b/Src/stm32f3xx_hal_crc.c
@@ -403,7 +403,7 @@
* @param hcrc CRC handle
* @retval HAL state
*/
-HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
+HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc)
{
/* Return CRC handle state */
return hcrc->State;
diff --git a/Src/stm32f3xx_hal_crc_ex.c b/Src/stm32f3xx_hal_crc_ex.c
index 0a82d93..3ed0824 100644
--- a/Src/stm32f3xx_hal_crc_ex.c
+++ b/Src/stm32f3xx_hal_crc_ex.c
@@ -210,8 +210,6 @@
}
-
-
/**
* @}
*/
diff --git a/Src/stm32f3xx_hal_dma.c b/Src/stm32f3xx_hal_dma.c
index 252d1df..76add6e 100644
--- a/Src/stm32f3xx_hal_dma.c
+++ b/Src/stm32f3xx_hal_dma.c
@@ -3,61 +3,61 @@
* @file stm32f3xx_hal_dma.c
* @author MCD Application Team
* @brief DMA HAL module driver.
- *
- * This file provides firmware functions to manage the following
+ *
+ * This file provides firmware functions to manage the following
* functionalities of the Direct Memory Access (DMA) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral State and errors functions
- @verbatim
- ==============================================================================
+ @verbatim
+ ==============================================================================
##### How to use this driver #####
- ==============================================================================
+ ==============================================================================
[..]
(#) Enable and configure the peripheral to be connected to the DMA Channel
- (except for internal SRAM / FLASH memories: no initialization is
+ (except for internal SRAM / FLASH memories: no initialization is
necessary). Please refer to Reference manual for connection between peripherals
and DMA requests .
- (#) For a given Channel, program the required configuration through the following parameters:
- Transfer Direction, Source and Destination data formats,
- Circular or Normal mode, Channel Priority level, Source and Destination Increment mode,
+ (#) For a given Channel, program the required configuration through the following parameters:
+ Transfer Direction, Source and Destination data formats,
+ Circular or Normal mode, Channel Priority level, Source and Destination Increment mode,
using HAL_DMA_Init() function.
- (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
+ (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
detection.
-
+
(#) Use HAL_DMA_Abort() function to abort the current transfer
-
+
-@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
*** Polling mode IO operation ***
- =================================
- [..]
- (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
+ =================================
+ [..]
+ (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
address and destination address and the Length of data to be transferred
- (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
+ (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
case a fixed Timeout can be configured by User depending from his application.
- *** Interrupt mode IO operation ***
- ===================================
+ *** Interrupt mode IO operation ***
+ ===================================
[..]
(+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
- (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
- (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
- Source address and destination address and the Length of data to be transferred.
- In this case the DMA interrupt is configured
+ (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
+ (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
+ Source address and destination address and the Length of data to be transferred.
+ In this case the DMA interrupt is configured
(+) Use HAL_DMA_Channel_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
- (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
- add his own function by customization of function pointer XferCpltCallback and
- XferErrorCallback (i.e a member of DMA handle structure).
+ (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
+ add his own function by customization of function pointer XferCpltCallback and
+ XferErrorCallback (i.e a member of DMA handle structure).
*** DMA HAL driver macros list ***
- =============================================
+ =============================================
[..]
Below the list of most used macros in DMA HAL driver.
- [..]
- (@) You can refer to the DMA HAL driver header file for more useful macros
+ [..]
+ (@) You can refer to the DMA HAL driver header file for more useful macros
@endverbatim
******************************************************************************
@@ -71,7 +71,7 @@
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
- */
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal.h"
@@ -108,41 +108,41 @@
*/
/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and de-initialization functions
+ * @brief Initialization and de-initialization functions
*
-@verbatim
+@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
- ===============================================================================
+ ===============================================================================
[..]
This section provides functions allowing to initialize the DMA Channel source
- and destination addresses, incrementation and data sizes, transfer direction,
+ and destination addresses, incrementation and data sizes, transfer direction,
circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
[..]
The HAL_DMA_Init() function follows the DMA configuration procedures as described in
- reference manual.
+ reference manual.
@endverbatim
* @{
*/
-
+
/**
* @brief Initialize the DMA according to the specified
* parameters in the DMA_InitTypeDef and initialize the associated handle.
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
+ * the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
-{
+{
uint32_t tmp = 0U;
-
+
/* Check the DMA handle allocation */
if(NULL == hdma)
{
return HAL_ERROR;
}
-
+
/* Check the parameters */
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
@@ -152,18 +152,18 @@
assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
assert_param(IS_DMA_MODE(hdma->Init.Mode));
assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
-
+
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
/* Get the CR register value */
tmp = hdma->Instance->CCR;
-
+
/* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */
tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
DMA_CCR_DIR));
-
+
/* Prepare the DMA Channel configuration */
tmp |= hdma->Init.Direction |
hdma->Init.PeriphInc | hdma->Init.MemInc |
@@ -171,28 +171,28 @@
hdma->Init.Mode | hdma->Init.Priority;
/* Write to DMA Channel CR register */
- hdma->Instance->CCR = tmp;
-
- /* Initialize DmaBaseAddress and ChannelIndex parameters used
+ hdma->Instance->CCR = tmp;
+
+ /* Initialize DmaBaseAddress and ChannelIndex parameters used
by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
DMA_CalcBaseAndBitshift(hdma);
-
+
/* Initialise the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
/* Initialize the DMA state*/
hdma->State = HAL_DMA_STATE_READY;
-
+
/* Allocate lock resource and initialize it */
hdma->Lock = HAL_UNLOCKED;
-
+
return HAL_OK;
-}
-
+}
+
/**
- * @brief DeInitialize the DMA peripheral
+ * @brief DeInitialize the DMA peripheral
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
+ * the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
@@ -202,7 +202,7 @@
{
return HAL_ERROR;
}
-
+
/* Check the parameters */
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
@@ -217,11 +217,11 @@
/* Reset DMA Channel peripheral address register */
hdma->Instance->CPAR = 0U;
-
+
/* Reset DMA Channel memory address register */
hdma->Instance->CMAR = 0U;
- /* Get DMA Base Address */
+ /* Get DMA Base Address */
DMA_CalcBaseAndBitshift(hdma);
/* Clear all flags */
@@ -249,20 +249,20 @@
* @}
*/
-/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
- * @brief I/O operation functions
+/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
+ * @brief I/O operation functions
*
-@verbatim
+@verbatim
===============================================================================
##### IO operation functions #####
- ===============================================================================
+ ===============================================================================
[..] This section provides functions allowing to:
(+) Configure the source, destination address and data length and Start DMA transfer
- (+) Configure the source, destination address and data length and
+ (+) Configure the source, destination address and data length and
Start DMA transfer with interrupt
(+) Abort DMA transfer
(+) Poll for transfer complete
- (+) Handle DMA interrupt request
+ (+) Handle DMA interrupt request
@endverbatim
* @{
@@ -271,7 +271,7 @@
/**
* @brief Start the DMA Transfer.
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
+ * the configuration information for the specified DMA Channel.
* @param SrcAddress The source memory Buffer address
* @param DstAddress The destination memory Buffer address
* @param DataLength The length of data to be transferred from source to destination
@@ -279,46 +279,46 @@
*/
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
- HAL_StatusTypeDef status = HAL_OK;
+ HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
-
+
/* Process locked */
__HAL_LOCK(hdma);
-
+
if(HAL_DMA_STATE_READY == hdma->State)
{
- /* Change DMA peripheral state */
- hdma->State = HAL_DMA_STATE_BUSY;
-
- hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-
- /* Disable the peripheral */
- hdma->Instance->CCR &= ~DMA_CCR_EN;
-
- /* Configure the source, destination address and the data length */
- DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
-
- /* Enable the Peripheral */
- hdma->Instance->CCR |= DMA_CCR_EN;
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_BUSY;
+
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ /* Disable the peripheral */
+ hdma->Instance->CCR &= ~DMA_CCR_EN;
+
+ /* Configure the source, destination address and the data length */
+ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+ /* Enable the Peripheral */
+ hdma->Instance->CCR |= DMA_CCR_EN;
}
else
{
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- /* Remain BUSY */
- status = HAL_BUSY;
- }
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
- return status;
-}
+ /* Remain BUSY */
+ status = HAL_BUSY;
+ }
+
+ return status;
+}
/**
* @brief Start the DMA Transfer with interrupt enabled.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
+ * the configuration information for the specified DMA Channel.
* @param SrcAddress The source memory Buffer address
* @param DstAddress The destination memory Buffer address
* @param DataLength The length of data to be transferred from source to destination
@@ -326,53 +326,53 @@
*/
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
- HAL_StatusTypeDef status = HAL_OK;
+ HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
-
+
/* Process locked */
__HAL_LOCK(hdma);
-
+
if(HAL_DMA_STATE_READY == hdma->State)
{
- /* Change DMA peripheral state */
- hdma->State = HAL_DMA_STATE_BUSY;
-
- hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-
- /* Disable the peripheral */
- hdma->Instance->CCR &= ~DMA_CCR_EN;
-
- /* Configure the source, destination address and the data length */
- DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
-
- /* Enable the transfer complete, & transfer error interrupts */
- /* Half transfer interrupt is optional: enable it only if associated callback is available */
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_BUSY;
+
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ /* Disable the peripheral */
+ hdma->Instance->CCR &= ~DMA_CCR_EN;
+
+ /* Configure the source, destination address and the data length */
+ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+ /* Enable the transfer complete, & transfer error interrupts */
+ /* Half transfer interrupt is optional: enable it only if associated callback is available */
if(NULL != hdma->XferHalfCpltCallback )
{
hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
}
- else
- {
- hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_TE);
- hdma->Instance->CCR &= ~DMA_IT_HT;
- }
-
- /* Enable the Peripheral */
- hdma->Instance->CCR |= DMA_CCR_EN;
+ else
+ {
+ hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_TE);
+ hdma->Instance->CCR &= ~DMA_IT_HT;
+ }
+
+ /* Enable the Peripheral */
+ hdma->Instance->CCR |= DMA_CCR_EN;
}
else
{
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
/* Remain BUSY */
status = HAL_BUSY;
- }
-
- return status;
-}
+ }
+
+ return status;
+}
/**
* @brief Abort the DMA Transfer.
@@ -382,33 +382,39 @@
*/
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
{
+ /* Check the DMA handle allocation */
+ if(NULL == hdma)
+ {
+ return HAL_ERROR;
+ }
+
if(hdma->State != HAL_DMA_STATE_BUSY)
{
/* no transfer ongoing */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hdma);
-
+
return HAL_ERROR;
}
else
{
/* Disable DMA IT */
- hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
-
+ hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
+
/* Disable the channel */
hdma->Instance->CCR &= ~DMA_CCR_EN;
-
+
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex);
}
/* Change the DMA state*/
- hdma->State = HAL_DMA_STATE_READY;
-
+ hdma->State = HAL_DMA_STATE_READY;
+
/* Process Unlocked */
__HAL_UNLOCK(hdma);
-
+
return HAL_OK;
}
@@ -419,39 +425,38 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
-{
+{
HAL_StatusTypeDef status = HAL_OK;
-
+
if(HAL_DMA_STATE_BUSY != hdma->State)
{
/* no transfer ongoing */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
-
+
status = HAL_ERROR;
}
else
- {
-
+ {
/* Disable DMA IT */
hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
-
+
/* Disable the channel */
hdma->Instance->CCR &= ~DMA_CCR_EN;
-
+
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
-
+
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hdma);
-
- /* Call User Abort callback */
+
+ /* Call User Abort callback */
if(hdma->XferAbortCallback != NULL)
{
hdma->XferAbortCallback(hdma);
- }
+ }
}
return status;
}
@@ -460,7 +465,7 @@
* @brief Polling for transfer complete.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
- * @param CompleteLevel Specifies the DMA level complete.
+ * @param CompleteLevel Specifies the DMA level complete.
* @param Timeout Timeout duration.
* @retval HAL status
*/
@@ -468,7 +473,7 @@
{
uint32_t temp;
uint32_t tickstart = 0U;
-
+
if(HAL_DMA_STATE_BUSY != hdma->State)
{
/* no transfer ongoing */
@@ -476,14 +481,14 @@
__HAL_UNLOCK(hdma);
return HAL_ERROR;
}
-
+
/* Polling mode not supported in circular mode */
if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC))
{
hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
return HAL_ERROR;
}
-
+
/* Get the level transfer complete flag */
if(HAL_DMA_FULL_TRANSFER == CompleteLevel)
{
@@ -502,23 +507,23 @@
while(RESET == (hdma->DmaBaseAddress->ISR & temp))
{
if(RESET != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << hdma->ChannelIndex)))
- {
+ {
/* When a DMA transfer error occurs */
/* A hardware clear of its EN bits is performed */
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
-
+
/* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_TE;
/* Change the DMA state */
- hdma->State= HAL_DMA_STATE_READY;
-
+ hdma->State= HAL_DMA_STATE_READY;
+
/* Process Unlocked */
__HAL_UNLOCK(hdma);
-
- return HAL_ERROR;
- }
+
+ return HAL_ERROR;
+ }
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
@@ -526,7 +531,7 @@
{
/* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
-
+
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
@@ -543,18 +548,18 @@
/* Clear the transfer complete flag */
hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex;
- /* The selected Channelx EN bit is cleared (DMA is disabled and
+ /* The selected Channelx EN bit is cleared (DMA is disabled and
all transfers are complete) */
hdma->State = HAL_DMA_STATE_READY;
}
else
- {
+ {
/* Clear the half transfer complete flag */
hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex;
}
-
+
/* Process unlocked */
- __HAL_UNLOCK(hdma);
+ __HAL_UNLOCK(hdma);
return HAL_OK;
}
@@ -562,90 +567,90 @@
/**
* @brief Handle DMA interrupt request.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
+ * the configuration information for the specified DMA Channel.
* @retval None
*/
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
{
- uint32_t flag_it = hdma->DmaBaseAddress->ISR;
+ uint32_t flag_it = hdma->DmaBaseAddress->ISR;
uint32_t source_it = hdma->Instance->CCR;
-
+
/* Half Transfer Complete Interrupt management ******************************/
if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_HT)))
{
- /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
- if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
- {
- /* Disable the half transfer interrupt */
- hdma->Instance->CCR &= ~DMA_IT_HT;
- }
-
- /* Clear the half transfer complete flag */
- hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex;
-
- /* DMA peripheral state is not updated in Half Transfer */
- /* State is updated only in Transfer Complete case */
-
- if(hdma->XferHalfCpltCallback != NULL)
- {
- /* Half transfer callback */
- hdma->XferHalfCpltCallback(hdma);
- }
+ /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
+ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
+ {
+ /* Disable the half transfer interrupt */
+ hdma->Instance->CCR &= ~DMA_IT_HT;
+ }
+
+ /* Clear the half transfer complete flag */
+ hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex;
+
+ /* DMA peripheral state is not updated in Half Transfer */
+ /* State is updated only in Transfer Complete case */
+
+ if(hdma->XferHalfCpltCallback != NULL)
+ {
+ /* Half transfer callback */
+ hdma->XferHalfCpltCallback(hdma);
+ }
}
-
+
/* Transfer Complete Interrupt management ***********************************/
else if ((RESET != (flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TC)))
{
- if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
- {
- /* Disable the transfer complete & transfer error interrupts */
- /* if the DMA mode is not CIRCULAR */
- hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_TE);
-
- /* Change the DMA state */
- hdma->State = HAL_DMA_STATE_READY;
- }
-
- /* Clear the transfer complete flag */
- hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- if(hdma->XferCpltCallback != NULL)
- {
- /* Transfer complete callback */
- hdma->XferCpltCallback(hdma);
- }
+ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
+ {
+ /* Disable the transfer complete & transfer error interrupts */
+ /* if the DMA mode is not CIRCULAR */
+ hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_TE);
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_READY;
+ }
+
+ /* Clear the transfer complete flag */
+ hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ if(hdma->XferCpltCallback != NULL)
+ {
+ /* Transfer complete callback */
+ hdma->XferCpltCallback(hdma);
+ }
}
-
+
/* Transfer Error Interrupt management ***************************************/
else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE)))
{
- /* When a DMA transfer error occurs */
+ /* When a DMA transfer error occurs */
/* A hardware clear of its EN bits is performed */
/* Then, disable all DMA interrupts */
hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
-
+
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
-
+
/* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_TE;
-
+
/* Change the DMA state */
- hdma->State = HAL_DMA_STATE_READY;
-
+ hdma->State = HAL_DMA_STATE_READY;
+
/* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
+ __HAL_UNLOCK(hdma);
+
if(hdma->XferErrorCallback != NULL)
{
- /* Transfer error callback */
- hdma->XferErrorCallback(hdma);
+ /* Transfer error callback */
+ hdma->XferErrorCallback(hdma);
}
}
-}
+}
/**
* @brief Register callbacks
@@ -653,17 +658,17 @@
* the configuration information for the specified DMA Stream.
* @param CallbackID User Callback identifier
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
- * @param pCallback pointer to private callback function which has pointer to
+ * @param pCallback pointer to private callback function which has pointer to
* a DMA_HandleTypeDef structure as parameter.
* @retval HAL status
- */
+ */
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma))
{
HAL_StatusTypeDef status = HAL_OK;
-
+
/* Process locked */
__HAL_LOCK(hdma);
-
+
if(HAL_DMA_STATE_READY == hdma->State)
{
switch (CallbackID)
@@ -671,32 +676,32 @@
case HAL_DMA_XFER_CPLT_CB_ID:
hdma->XferCpltCallback = pCallback;
break;
-
+
case HAL_DMA_XFER_HALFCPLT_CB_ID:
hdma->XferHalfCpltCallback = pCallback;
- break;
+ break;
case HAL_DMA_XFER_ERROR_CB_ID:
hdma->XferErrorCallback = pCallback;
- break;
-
+ break;
+
case HAL_DMA_XFER_ABORT_CB_ID:
hdma->XferAbortCallback = pCallback;
- break;
-
+ break;
+
default:
status = HAL_ERROR;
- break;
+ break;
}
}
else
{
status = HAL_ERROR;
- }
-
+ }
+
/* Release Lock */
__HAL_UNLOCK(hdma);
-
+
return status;
}
@@ -707,14 +712,14 @@
* @param CallbackID User Callback identifier
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
* @retval HAL status
- */
+ */
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
+ /* Process locked */
__HAL_LOCK(hdma);
-
+
if(HAL_DMA_STATE_READY == hdma->State)
{
switch (CallbackID)
@@ -722,39 +727,39 @@
case HAL_DMA_XFER_CPLT_CB_ID:
hdma->XferCpltCallback = NULL;
break;
-
+
case HAL_DMA_XFER_HALFCPLT_CB_ID:
hdma->XferHalfCpltCallback = NULL;
- break;
+ break;
case HAL_DMA_XFER_ERROR_CB_ID:
hdma->XferErrorCallback = NULL;
- break;
-
+ break;
+
case HAL_DMA_XFER_ABORT_CB_ID:
hdma->XferAbortCallback = NULL;
- break;
-
+ break;
+
case HAL_DMA_XFER_ALL_CB_ID:
hdma->XferCpltCallback = NULL;
hdma->XferHalfCpltCallback = NULL;
hdma->XferErrorCallback = NULL;
hdma->XferAbortCallback = NULL;
- break;
-
+ break;
+
default:
status = HAL_ERROR;
- break;
+ break;
}
}
else
{
status = HAL_ERROR;
- }
-
+ }
+
/* Release Lock */
__HAL_UNLOCK(hdma);
-
+
return status;
}
@@ -763,12 +768,12 @@
*/
/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
- * @brief Peripheral State functions
+ * @brief Peripheral State functions
*
-@verbatim
+@verbatim
===============================================================================
##### State and Errors functions #####
- ===============================================================================
+ ===============================================================================
[..]
This subsection provides functions allowing to
(+) Check the DMA state
@@ -776,12 +781,12 @@
@endverbatim
* @{
- */
+ */
/**
* @brief Returns the DMA state.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
+ * the configuration information for the specified DMA Channel.
* @retval HAL state
*/
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
@@ -815,7 +820,7 @@
/**
* @brief Set the DMA Transfer parameters.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
+ * the configuration information for the specified DMA Channel.
* @param SrcAddress The source memory Buffer address
* @param DstAddress The destination memory Buffer address
* @param DataLength The length of data to be transferred from source to destination
@@ -823,18 +828,18 @@
*/
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
- /* Clear all flags */
+ /* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex);
-
+
/* Configure DMA Channel data length */
hdma->Instance->CNDTR = DataLength;
-
+
/* Peripheral to Memory */
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
- {
+ {
/* Configure DMA Channel destination address */
hdma->Instance->CPAR = DstAddress;
-
+
/* Configure DMA Channel source address */
hdma->Instance->CMAR = SrcAddress;
}
@@ -843,7 +848,7 @@
{
/* Configure DMA Channel source address */
hdma->Instance->CPAR = SrcAddress;
-
+
/* Configure DMA Channel destination address */
hdma->Instance->CMAR = DstAddress;
}
@@ -852,7 +857,7 @@
/**
* @brief Set the DMA base address and channel index depending on DMA instance
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Stream.
+ * the configuration information for the specified DMA Stream.
* @retval None
*/
static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
@@ -865,7 +870,7 @@
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
hdma->DmaBaseAddress = DMA1;
}
- else
+ else
{
/* DMA2 */
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;
@@ -891,7 +896,7 @@
/**
* @}
*/
-
+
/**
* @}
*/
diff --git a/Src/stm32f3xx_hal_exti.c b/Src/stm32f3xx_hal_exti.c
index bf792a5..3c5399d 100644
--- a/Src/stm32f3xx_hal_exti.c
+++ b/Src/stm32f3xx_hal_exti.c
@@ -64,7 +64,7 @@
(++) Provide exiting handle as parameter.
(++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
- (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
+ (#) Clear Exti configuration of a dedicated line using HAL_EXTI_ClearConfigLine().
(++) Provide exiting handle as parameter.
(#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
@@ -75,7 +75,7 @@
(#) Get interrupt pending bit using HAL_EXTI_GetPending().
- (#) Clear interrupt pending bit using HAL_EXTI_GetPending().
+ (#) Clear interrupt pending bit using HAL_EXTI_ClearPending().
(#) Generate software interrupt using HAL_EXTI_GenerateSWI().
diff --git a/Src/stm32f3xx_hal_hrtim.c b/Src/stm32f3xx_hal_hrtim.c
index 03b613d..f11baa9 100644
--- a/Src/stm32f3xx_hal_hrtim.c
+++ b/Src/stm32f3xx_hal_hrtim.c
@@ -84,7 +84,6 @@
any restriction. HRTIM waveform modes are managed through the set of
functions named HAL_HRTIM_Waveform<Function>
-==============================================================================
##### How to use this driver #####
==============================================================================
[..]
@@ -8384,7 +8383,7 @@
case HRTIM_OUTPUT_TD1:
case HRTIM_OUTPUT_TE1:
{
- /* Retrieves actual OC mode and set interrupt accordingly */
+ /* Retreives actual OC mode and set interrupt accordingly */
hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R;
hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R;
@@ -8419,7 +8418,7 @@
case HRTIM_OUTPUT_TD2:
case HRTIM_OUTPUT_TE2:
{
- /* Retrieves actual OC mode and set interrupt accordingly */
+ /* Retreives actual OC mode and set interrupt accordingly */
hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R;
hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R;
@@ -8490,7 +8489,7 @@
case HRTIM_OUTPUT_TD1:
case HRTIM_OUTPUT_TE1:
{
- /* Retrieves actual OC mode and set dma_request accordingly */
+ /* Retreives actual OC mode and set dma_request accordingly */
hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R;
hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R;
@@ -8525,7 +8524,7 @@
case HRTIM_OUTPUT_TD2:
case HRTIM_OUTPUT_TE2:
{
- /* Retrieves actual OC mode and set dma_request accordingly */
+ /* Retreives actual OC mode and set dma_request accordingly */
hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R;
hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R;
diff --git a/Src/stm32f3xx_hal_i2c.c b/Src/stm32f3xx_hal_i2c.c
index 45e5ba9..7fdfa73 100644
--- a/Src/stm32f3xx_hal_i2c.c
+++ b/Src/stm32f3xx_hal_i2c.c
@@ -90,7 +90,7 @@
add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
add their own code by customization of function pointer HAL_I2C_ErrorCallback()
- (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+ (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
(+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
(+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
@@ -156,7 +156,7 @@
HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA()
(+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
- (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+ (++) Abort a master or memory IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
(+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
(++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT()
@@ -214,7 +214,7 @@
add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
add their own code by customization of function pointer HAL_I2C_ErrorCallback()
- (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+ (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
(+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
(+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
@@ -608,7 +608,12 @@
/* Configure I2Cx: Addressing Master mode */
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
{
- hi2c->Instance->CR2 = (I2C_CR2_ADD10);
+ SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
+ }
+ else
+ {
+ /* Clear the I2C ADD10 bit */
+ CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
}
/* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
@@ -1374,6 +1379,8 @@
uint32_t Timeout)
{
uint32_t tickstart;
+ uint16_t tmpXferCount;
+ HAL_StatusTypeDef error;
if (hi2c->State == HAL_I2C_STATE_READY)
{
@@ -1400,14 +1407,6 @@
/* Enable Address Acknowledge */
hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
- /* Wait until ADDR flag is set */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
- {
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_ERROR;
- }
-
/* Preload TX data if no stretch enable */
if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
{
@@ -1421,6 +1420,18 @@
hi2c->XferCount--;
}
+ /* Wait until ADDR flag is set */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+
+ return HAL_ERROR;
+ }
+
/* Clear ADDR flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
@@ -1432,6 +1443,10 @@
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+
return HAL_ERROR;
}
@@ -1444,6 +1459,10 @@
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+
return HAL_ERROR;
}
@@ -1467,31 +1486,48 @@
}
/* Wait until AF flag is set */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
+ error = I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart);
+
+ if (error != HAL_OK)
{
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_ERROR;
+ /* Check that I2C transfer finished */
+ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
+ /* Mean XferCount == 0 */
+
+ tmpXferCount = hi2c->XferCount;
+ if ((hi2c->ErrorCode == HAL_I2C_ERROR_AF) && (tmpXferCount == 0U))
+ {
+ /* Reset ErrorCode to NONE */
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ }
+ else
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_ERROR;
+ }
}
-
- /* Flush TX register */
- I2C_Flush_TXDR(hi2c);
-
- /* Clear AF flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
- /* Wait until STOP flag is set */
- if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ else
{
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
- return HAL_ERROR;
+ /* Clear AF flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Wait until STOP flag is set */
+ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ return HAL_ERROR;
+ }
+
+ /* Clear STOP flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
}
- /* Clear STOP flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
/* Wait until BUSY flag is reset */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
{
@@ -1998,8 +2034,8 @@
hi2c->hdmatx->XferAbortCallback = NULL;
/* Enable the DMA channel */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
- hi2c->XferSize);
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr,
+ (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
}
else
{
@@ -2020,7 +2056,8 @@
{
/* Send Slave Address */
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), xfermode, I2C_GENERATE_START_WRITE);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U),
+ xfermode, I2C_GENERATE_START_WRITE);
/* Update XferCount value */
hi2c->XferCount -= hi2c->XferSize;
@@ -3316,22 +3353,6 @@
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
}
- /* Check if the maximum allowed number of trials has been reached */
- if (I2C_Trials == Trials)
- {
- /* Generate Stop */
- hi2c->Instance->CR2 |= I2C_CR2_STOP;
-
- /* Wait until STOPF flag is reset */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
- }
-
/* Increment Trials */
I2C_Trials++;
} while (I2C_Trials < Trials);
@@ -3402,7 +3423,8 @@
xfermode = hi2c->XferOptions;
}
- if ((hi2c->XferSize > 0U) && ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME)))
+ if ((hi2c->XferSize > 0U) && ((XferOptions == I2C_FIRST_FRAME) || \
+ (XferOptions == I2C_FIRST_AND_LAST_FRAME)))
{
/* Preload TX register */
/* Write data to TXDR */
@@ -3516,7 +3538,8 @@
xfermode = hi2c->XferOptions;
}
- if ((hi2c->XferSize > 0U) && ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME)))
+ if ((hi2c->XferSize > 0U) && ((XferOptions == I2C_FIRST_FRAME) || \
+ (XferOptions == I2C_FIRST_AND_LAST_FRAME)))
{
/* Preload TX register */
/* Write data to TXDR */
@@ -3565,8 +3588,8 @@
hi2c->hdmatx->XferAbortCallback = NULL;
/* Enable the DMA channel */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
- hi2c->XferSize);
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr,
+ (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
}
else
{
@@ -4541,7 +4564,7 @@
}
/**
- * @brief Abort a master I2C IT or DMA process communication with Interrupt.
+ * @brief Abort a master or memory I2C IT or DMA process communication with Interrupt.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
@@ -4550,7 +4573,9 @@
*/
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
{
- if (hi2c->Mode == HAL_I2C_MODE_MASTER)
+ HAL_I2C_ModeTypeDef tmp_mode = hi2c->Mode;
+
+ if ((tmp_mode == HAL_I2C_MODE_MASTER) || (tmp_mode == HAL_I2C_MODE_MEM))
{
/* Process Locked */
__HAL_LOCK(hi2c);
@@ -6305,8 +6330,7 @@
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Disable Interrupts and Store Previous state */
- if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
- (tmpstate == HAL_I2C_STATE_LISTEN))
+ if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
{
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
@@ -6316,6 +6340,11 @@
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
}
+ else if (tmpstate == HAL_I2C_STATE_LISTEN)
+ {
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
+ hi2c->PreviousState = I2C_STATE_NONE;
+ }
else
{
/* Do nothing */
@@ -6969,6 +6998,12 @@
{
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
{
+ /* Check if an error is detected */
+ if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
diff --git a/Src/stm32f3xx_hal_i2s.c b/Src/stm32f3xx_hal_i2s.c
index 945678f..e38450b 100644
--- a/Src/stm32f3xx_hal_i2s.c
+++ b/Src/stm32f3xx_hal_i2s.c
@@ -874,15 +874,14 @@
return HAL_ERROR;
}
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
if (hi2s->State != HAL_I2S_STATE_READY)
{
- __HAL_UNLOCK(hi2s);
return HAL_BUSY;
}
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
/* Set state and reset error code */
hi2s->State = HAL_I2S_STATE_BUSY_TX;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
@@ -993,15 +992,14 @@
return HAL_ERROR;
}
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
if (hi2s->State != HAL_I2S_STATE_READY)
{
- __HAL_UNLOCK(hi2s);
return HAL_BUSY;
}
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
/* Set state and reset error code */
hi2s->State = HAL_I2S_STATE_BUSY_RX;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
@@ -1091,15 +1089,14 @@
return HAL_ERROR;
}
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
if (hi2s->State != HAL_I2S_STATE_READY)
{
- __HAL_UNLOCK(hi2s);
return HAL_BUSY;
}
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
/* Set state and reset error code */
hi2s->State = HAL_I2S_STATE_BUSY_TX;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
@@ -1118,6 +1115,8 @@
hi2s->TxXferCount = Size;
}
+ __HAL_UNLOCK(hi2s);
+
/* Enable TXE and ERR interrupt */
__HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
@@ -1128,7 +1127,6 @@
__HAL_I2S_ENABLE(hi2s);
}
- __HAL_UNLOCK(hi2s);
return HAL_OK;
}
@@ -1157,15 +1155,14 @@
return HAL_ERROR;
}
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
if (hi2s->State != HAL_I2S_STATE_READY)
{
- __HAL_UNLOCK(hi2s);
return HAL_BUSY;
}
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
/* Set state and reset error code */
hi2s->State = HAL_I2S_STATE_BUSY_RX;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
@@ -1184,6 +1181,8 @@
hi2s->RxXferCount = Size;
}
+ __HAL_UNLOCK(hi2s);
+
/* Enable RXNE and ERR interrupt */
__HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
@@ -1194,7 +1193,6 @@
__HAL_I2S_ENABLE(hi2s);
}
- __HAL_UNLOCK(hi2s);
return HAL_OK;
}
@@ -1221,15 +1219,14 @@
return HAL_ERROR;
}
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
if (hi2s->State != HAL_I2S_STATE_READY)
{
- __HAL_UNLOCK(hi2s);
return HAL_BUSY;
}
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
/* Set state and reset error code */
hi2s->State = HAL_I2S_STATE_BUSY_TX;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
@@ -1271,12 +1268,7 @@
return HAL_ERROR;
}
- /* Check if the I2S is already enabled */
- if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
- {
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
+ __HAL_UNLOCK(hi2s);
/* Check if the I2S Tx request is already enabled */
if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_TXDMAEN))
@@ -1285,7 +1277,13 @@
SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
}
- __HAL_UNLOCK(hi2s);
+ /* Check if the I2S is already enabled */
+ if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
return HAL_OK;
}
@@ -1312,15 +1310,14 @@
return HAL_ERROR;
}
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
if (hi2s->State != HAL_I2S_STATE_READY)
{
- __HAL_UNLOCK(hi2s);
return HAL_BUSY;
}
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
/* Set state and reset error code */
hi2s->State = HAL_I2S_STATE_BUSY_RX;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
@@ -1368,12 +1365,7 @@
return HAL_ERROR;
}
- /* Check if the I2S is already enabled */
- if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
- {
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
+ __HAL_UNLOCK(hi2s);
/* Check if the I2S Rx request is already enabled */
if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_RXDMAEN))
@@ -1382,7 +1374,13 @@
SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
}
- __HAL_UNLOCK(hi2s);
+ /* Check if the I2S is already enabled */
+ if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
return HAL_OK;
}
diff --git a/Src/stm32f3xx_hal_i2s_ex.c b/Src/stm32f3xx_hal_i2s_ex.c
index 7989c79..39f3767 100644
--- a/Src/stm32f3xx_hal_i2s_ex.c
+++ b/Src/stm32f3xx_hal_i2s_ex.c
@@ -210,17 +210,15 @@
uint32_t Timeout)
{
uint32_t tmp1 = 0U;
- HAL_StatusTypeDef errorcode = HAL_OK;
if (hi2s->State != HAL_I2S_STATE_READY)
{
- errorcode = HAL_BUSY;
- goto error;
+ return HAL_BUSY;
}
if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
/* Process Locked */
@@ -281,8 +279,11 @@
{
/* Set the error code */
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
- errorcode = HAL_ERROR;
- goto error;
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Process UnLock */
+ __HAL_UNLOCK(hi2s);
+ return HAL_ERROR;
}
/* Write Data on DR register */
hi2s->Instance->DR = (*pTxData++);
@@ -305,8 +306,11 @@
{
/* Set the error code */
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
- errorcode = HAL_ERROR;
- goto error;
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Process UnLock */
+ __HAL_UNLOCK(hi2s);
+ return HAL_ERROR;
}
/* Read Data from DR register */
(*pRxData++) = I2SxEXT(hi2s->Instance)->DR;
@@ -354,8 +358,11 @@
{
/* Set the error code */
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
- errorcode = HAL_ERROR;
- goto error;
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Process UnLock */
+ __HAL_UNLOCK(hi2s);
+ return HAL_ERROR;
}
/* Write Data on DR register */
I2SxEXT(hi2s->Instance)->DR = (*pTxData++);
@@ -378,8 +385,11 @@
{
/* Set the error code */
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
- errorcode = HAL_ERROR;
- goto error;
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Process UnLock */
+ __HAL_UNLOCK(hi2s);
+ return HAL_ERROR;
}
/* Read Data from DR register */
(*pRxData++) = hi2s->Instance->DR;
@@ -398,15 +408,17 @@
}
}
- if (hi2s->ErrorCode != HAL_I2S_ERROR_NONE)
- {
- errorcode = HAL_ERROR;
- }
-
-error :
hi2s->State = HAL_I2S_STATE_READY;
__HAL_UNLOCK(hi2s);
- return errorcode;
+
+ if (hi2s->ErrorCode != HAL_I2S_ERROR_NONE)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_OK;
+ }
}
/**
@@ -430,12 +442,10 @@
uint16_t Size)
{
uint32_t tmp1 = 0U;
- HAL_StatusTypeDef errorcode = HAL_OK;
if (hi2s->State != HAL_I2S_STATE_READY)
{
- errorcode = HAL_BUSY;
- goto error;
+ return HAL_BUSY;
}
if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
@@ -510,15 +520,14 @@
}
}
+ __HAL_UNLOCK(hi2s);
/* Enable I2Sext peripheral */
__HAL_I2SEXT_ENABLE(hi2s);
/* Enable I2S peripheral */
__HAL_I2S_ENABLE(hi2s);
-error :
- __HAL_UNLOCK(hi2s);
- return errorcode;
+ return HAL_OK;
}
/**
@@ -543,12 +552,10 @@
{
uint32_t *tmp = NULL;
uint32_t tmp1 = 0U;
- HAL_StatusTypeDef errorcode = HAL_OK;
if (hi2s->State != HAL_I2S_STATE_READY)
{
- errorcode = HAL_BUSY;
- goto error;
+ return HAL_BUSY;
}
if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
@@ -620,16 +627,6 @@
/* Enable Tx DMA Request */
SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
-
- /* Check if the I2S is already enabled */
- if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
- {
- /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
- __HAL_I2SEXT_ENABLE(hi2s);
-
- /* Enable I2S peripheral after the I2Sext */
- __HAL_I2S_ENABLE(hi2s);
- }
}
else
{
@@ -653,20 +650,19 @@
/* Enable Rx DMA Request */
SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
-
- /* Check if the I2S is already enabled */
- if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
- {
- /* Enable I2Sext(transmitter) before enabling I2Sx peripheral */
- __HAL_I2SEXT_ENABLE(hi2s);
- /* Enable I2S peripheral before the I2Sext */
- __HAL_I2S_ENABLE(hi2s);
- }
}
-error :
__HAL_UNLOCK(hi2s);
- return errorcode;
+ /* Check if the I2S is already enabled */
+ if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2Sext(transmitter) before enabling I2Sx peripheral */
+ __HAL_I2SEXT_ENABLE(hi2s);
+ /* Enable I2S peripheral before the I2Sext */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ return HAL_OK;
}
/**
diff --git a/Src/stm32f3xx_hal_irda.c b/Src/stm32f3xx_hal_irda.c
index e8e8714..0cb62fe 100644
--- a/Src/stm32f3xx_hal_irda.c
+++ b/Src/stm32f3xx_hal_irda.c
@@ -142,7 +142,7 @@
[..]
Use function HAL_IRDA_UnRegisterCallback() to reset a callback to the default
- weak (surcharged) function.
+ weak function.
HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
@@ -159,10 +159,10 @@
[..]
By default, after the HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET
- all callbacks are set to the corresponding weak (surcharged) functions:
+ all callbacks are set to the corresponding weak functions:
examples HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxHalfCpltCallback().
Exception done for MspInit and MspDeInit functions that are respectively
- reset to the legacy weak (surcharged) functions in the HAL_IRDA_Init()
+ reset to the legacy weak functions in the HAL_IRDA_Init()
and HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_IRDA_Init() and HAL_IRDA_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
@@ -179,7 +179,7 @@
[..]
When The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available
- and weak (surcharged) callbacks are used.
+ and weak callbacks are used.
@endverbatim
******************************************************************************
@@ -470,7 +470,7 @@
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User IRDA Callback
- * To be used instead of the weak predefined callback
+ * To be used to override the weak predefined callback
* @note The HAL_IRDA_RegisterCallback() may be called before HAL_IRDA_Init() in HAL_IRDA_STATE_RESET
* to register callbacks for HAL_IRDA_MSPINIT_CB_ID and HAL_IRDA_MSPDEINIT_CB_ID
* @param hirda irda handle
diff --git a/Src/stm32f3xx_hal_nand.c b/Src/stm32f3xx_hal_nand.c
index 442609f..f40f74f 100644
--- a/Src/stm32f3xx_hal_nand.c
+++ b/Src/stm32f3xx_hal_nand.c
@@ -77,15 +77,15 @@
and a pointer to the user callback function.
Use function HAL_NAND_UnRegisterCallback() to reset a callback to the default
- weak (surcharged) function. It allows to reset following callbacks:
+ weak (overridden) function. It allows to reset following callbacks:
(+) MspInitCallback : NAND MspInit.
(+) MspDeInitCallback : NAND MspDeInit.
This function) takes as parameters the HAL peripheral handle and the Callback ID.
By default, after the HAL_NAND_Init and if the state is HAL_NAND_STATE_RESET
- all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+ all callbacks are reset to the corresponding legacy weak (overridden) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the HAL_NAND_Init
+ reset to the legacy weak (overridden) functions in the HAL_NAND_Init
and HAL_NAND_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_NAND_Init and HAL_NAND_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
@@ -100,7 +100,7 @@
When The compilation define USE_HAL_NAND_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
- and weak (surcharged) callbacks are used.
+ and weak (overridden) callbacks are used.
@endverbatim
******************************************************************************
@@ -1976,7 +1976,7 @@
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User NAND Callback
- * To be used instead of the weak (surcharged) predefined callback
+ * To be used to override the weak predefined callback
* @param hnand : NAND handle
* @param CallbackId : ID of the callback to be registered
* This parameter can be one of the following values:
@@ -1996,9 +1996,6 @@
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(hnand);
-
if (hnand->State == HAL_NAND_STATE_READY)
{
switch (CallbackId)
@@ -2040,14 +2037,12 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hnand);
return status;
}
/**
* @brief Unregister a User NAND Callback
- * NAND Callback is redirected to the weak (surcharged) predefined callback
+ * NAND Callback is redirected to the weak predefined callback
* @param hnand : NAND handle
* @param CallbackId : ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -2060,9 +2055,6 @@
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
- __HAL_LOCK(hnand);
-
if (hnand->State == HAL_NAND_STATE_READY)
{
switch (CallbackId)
@@ -2104,8 +2096,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hnand);
return status;
}
#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
diff --git a/Src/stm32f3xx_hal_nor.c b/Src/stm32f3xx_hal_nor.c
index 4ffc324..87af606 100644
--- a/Src/stm32f3xx_hal_nor.c
+++ b/Src/stm32f3xx_hal_nor.c
@@ -74,15 +74,15 @@
and a pointer to the user callback function.
Use function HAL_NOR_UnRegisterCallback() to reset a callback to the default
- weak (surcharged) function. It allows to reset following callbacks:
+ weak (overridden) function. It allows to reset following callbacks:
(+) MspInitCallback : NOR MspInit.
(+) MspDeInitCallback : NOR MspDeInit.
This function) takes as parameters the HAL peripheral handle and the Callback ID.
By default, after the HAL_NOR_Init and if the state is HAL_NOR_STATE_RESET
- all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+ all callbacks are reset to the corresponding legacy weak (overridden) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the HAL_NOR_Init
+ reset to the legacy weak (overridden) functions in the HAL_NOR_Init
and HAL_NOR_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_NOR_Init and HAL_NOR_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
@@ -97,7 +97,7 @@
When The compilation define USE_HAL_NOR_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
- and weak (surcharged) callbacks are used.
+ and weak (overridden) callbacks are used.
@endverbatim
******************************************************************************
@@ -406,7 +406,7 @@
* @param Timeout Maximum timeout value
* @retval None
*/
-__weak void HAL_NOR_MspWait(const NOR_HandleTypeDef *hnor, uint32_t Timeout)
+__weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hnor);
@@ -1309,7 +1309,7 @@
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User NOR Callback
- * To be used instead of the weak (surcharged) predefined callback
+ * To be used to override the weak predefined callback
* @param hnor : NOR handle
* @param CallbackId : ID of the callback to be registered
* This parameter can be one of the following values:
@@ -1329,9 +1329,6 @@
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(hnor);
-
state = hnor->State;
if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
{
@@ -1355,14 +1352,12 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hnor);
return status;
}
/**
* @brief Unregister a User NOR Callback
- * NOR Callback is redirected to the weak (surcharged) predefined callback
+ * NOR Callback is redirected to the weak predefined callback
* @param hnor : NOR handle
* @param CallbackId : ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -1375,9 +1370,6 @@
HAL_StatusTypeDef status = HAL_OK;
HAL_NOR_StateTypeDef state;
- /* Process locked */
- __HAL_LOCK(hnor);
-
state = hnor->State;
if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
{
@@ -1401,8 +1393,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hnor);
return status;
}
#endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
@@ -1533,7 +1523,7 @@
* @retval NOR_Status The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
* or HAL_NOR_STATUS_TIMEOUT
*/
-HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(const NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
+HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
{
HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
uint16_t tmpsr1;
diff --git a/Src/stm32f3xx_hal_pcd.c b/Src/stm32f3xx_hal_pcd.c
index 0824d96..427a38f 100644
--- a/Src/stm32f3xx_hal_pcd.c
+++ b/Src/stm32f3xx_hal_pcd.c
@@ -1311,7 +1311,7 @@
* @param ep_addr endpoint address
* @retval Data Size
*/
-uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr)
{
return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count;
}
@@ -1451,9 +1451,18 @@
*/
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
- UNUSED(ep_addr);
+ __HAL_LOCK(hpcd);
+
+ if ((ep_addr & 0x80U) == 0x80U)
+ {
+ (void)USB_FlushTxFifo(hpcd->Instance, (uint32_t)ep_addr & EP_ADDR_MSK);
+ }
+ else
+ {
+ (void)USB_FlushRxFifo(hpcd->Instance);
+ }
+
+ __HAL_UNLOCK(hpcd);
return HAL_OK;
}
@@ -1502,7 +1511,7 @@
* @param hpcd PCD handle
* @retval HAL state
*/
-PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
+PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd)
{
return hpcd->State;
}
diff --git a/Src/stm32f3xx_hal_pwr.c b/Src/stm32f3xx_hal_pwr.c
index 77d5c2e..5a57c62 100644
--- a/Src/stm32f3xx_hal_pwr.c
+++ b/Src/stm32f3xx_hal_pwr.c
@@ -283,6 +283,9 @@
/* Check the parameters */
assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(Regulator);
+
/* Clear SLEEPDEEP bit of Cortex System Control Register */
SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
diff --git a/Src/stm32f3xx_hal_rcc.c b/Src/stm32f3xx_hal_rcc.c
index 0bb890e..c2731ea 100644
--- a/Src/stm32f3xx_hal_rcc.c
+++ b/Src/stm32f3xx_hal_rcc.c
@@ -980,8 +980,8 @@
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
{
- pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> POSITION_VAL(RCC_CFGR_PLLMUL)];
- prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> POSITION_VAL(RCC_CFGR2_PREDIV)];
+ pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_Pos];
+ prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> RCC_CFGR2_PREDIV_Pos];
#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI)
{
@@ -1100,7 +1100,7 @@
RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
}
- RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
+ RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
/* Get the LSE configuration -----------------------------------------------*/
if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
diff --git a/Src/stm32f3xx_hal_rcc_ex.c b/Src/stm32f3xx_hal_rcc_ex.c
index 8966adb..93b7c15 100644
--- a/Src/stm32f3xx_hal_rcc_ex.c
+++ b/Src/stm32f3xx_hal_rcc_ex.c
@@ -1247,12 +1247,12 @@
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
{
/* Frequency is the PLL frequency divided by ADC prescaler (1U/2U/4U/6U/8U/10U/12U/16U/32U/64U/128U/256U) */
- frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> POSITION_VAL(RCC_CFGR2_ADC1PRES)) & 0xFU];
+ frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> RCC_CFGR2_ADC1PRES_Pos) & 0xFU];
}
}
#else /* RCC_CFGR_ADCPRE */
/* ADC1 is set to PLCK2 frequency divided by 2U/4U/6U/8U */
- frequency = HAL_RCC_GetPCLK2Freq() / (((srcclk >> POSITION_VAL(RCC_CFGR_ADCPRE)) + 1U) * 2U);
+ frequency = HAL_RCC_GetPCLK2Freq() / (((srcclk >> RCC_CFGR_ADCPRE_Pos) + 1U) * 2U);
#endif /* RCC_CFGR2_ADC1PRES */
break;
}
@@ -1274,7 +1274,7 @@
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
{
/* Frequency is the PLL frequency divided by ADC prescaler (1U/2U/4U/6/8U/10U/12U/16U/32U/64U/128U/256U) */
- frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> POSITION_VAL(RCC_CFGR2_ADCPRE12)) & 0xF];
+ frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> RCC_CFGR2_ADCPRE12_Pos) & 0xF];
}
}
break;
@@ -1297,7 +1297,7 @@
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
{
/* Frequency is the PLL frequency divided by ADC prescaler (1U/2U/4U/6U/8U/10U/12U/16U/32U/64U/128U/256U) */
- frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> POSITION_VAL(RCC_CFGR2_ADCPRE34)) & 0xF];
+ frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> RCC_CFGR2_ADCPRE34_Pos) & 0xF];
}
}
break;
@@ -1480,7 +1480,7 @@
/* Get the current SDADC source */
srcclk = __HAL_RCC_GET_SDADC_SOURCE();
/* Frequency is the system frequency divided by SDADC prescaler (2U/4U/6U/8U/10U/12U/14U/16U/20U/24U/28U/32U/36U/40U/44U/48U) */
- frequency = SystemCoreClock / sdadc_prescaler_table[(srcclk >> POSITION_VAL(RCC_CFGR_SDPRE)) & 0xF];
+ frequency = SystemCoreClock / sdadc_prescaler_table[(srcclk >> RCC_CFGR_SDPRE_Pos) & 0xF];
break;
}
#endif /* RCC_CFGR_SDPRE */
diff --git a/Src/stm32f3xx_hal_rtc.c b/Src/stm32f3xx_hal_rtc.c
index 3a2a41c..c63ed71 100644
--- a/Src/stm32f3xx_hal_rtc.c
+++ b/Src/stm32f3xx_hal_rtc.c
@@ -6,8 +6,8 @@
* This file provides firmware functions to manage the following
* functionalities of the Real-Time Clock (RTC) peripheral:
* + Initialization and de-initialization functions
- * + RTC Calendar (Time and Date) configuration functions
- * + RTC Alarms (Alarm A and Alarm B) configuration functions
+ * + Calendar (Time and Date) configuration functions
+ * + Alarms (Alarm A and Alarm B) configuration functions
* + Peripheral Control functions
* + Peripheral State functions
*
@@ -63,7 +63,7 @@
##### Backup Domain Access #####
==================================================================
- [..] After reset, the backup domain (RTC registers, RTC backup data registers
+ [..] After reset, the backup domain (RTC registers and RTC backup data registers)
is protected against possible unwanted write accesses.
[..] To enable access to the RTC Domain and RTC registers, proceed as follows:
(+) Enable the Power Controller (PWR) APB1 interface clock using the
@@ -121,6 +121,12 @@
*** Callback registration ***
=============================================
[..]
+ When the compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all
+ callbacks are set to the corresponding weak functions.
+ This is the recommended configuration in order to optimize memory/code
+ consumption footprint/performances.
+ [..]
The compilation define USE_HAL_RTC_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Function HAL_RTC_RegisterCallback() to register an interrupt callback.
@@ -132,9 +138,11 @@
(+) WakeUpTimerEventCallback : RTC WakeUpTimer Event callback.
(+) Tamper1EventCallback : RTC Tamper 1 Event callback.
(+) Tamper2EventCallback : RTC Tamper 2 Event callback.
- (+) Tamper3EventCallback : RTC Tamper 3 Event callback.
+ (+) Tamper3EventCallback : RTC Tamper 3 Event callback. (*)
(+) MspInitCallback : RTC MspInit callback.
(+) MspDeInitCallback : RTC MspDeInit callback.
+
+ (*) value not applicable to all devices.
[..]
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
@@ -150,31 +158,29 @@
(+) WakeUpTimerEventCallback : RTC WakeUpTimer Event callback.
(+) Tamper1EventCallback : RTC Tamper 1 Event callback.
(+) Tamper2EventCallback : RTC Tamper 2 Event callback.
- (+) Tamper3EventCallback : RTC Tamper 3 Event callback.
+ (+) Tamper3EventCallback : RTC Tamper 3 Event callback. (*)
(+) MspInitCallback : RTC MspInit callback.
(+) MspDeInitCallback : RTC MspDeInit callback.
+
+ (*) value not applicable to all devices.
[..]
By default, after the HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET,
all callbacks are set to the corresponding weak functions:
- examples AlarmAEventCallback(), WakeUpTimerEventCallback().
+ examples AlarmAEventCallback(), TimeStampEventCallback().
Exception done for MspInit() and MspDeInit() callbacks that are reset to the
- legacy weak function in the HAL_RTC_Init()/HAL_RTC_DeInit() only
- when these callbacks are null (not registered beforehand).
+ legacy weak function in the HAL_RTC_Init()/HAL_RTC_DeInit() only when these
+ callbacks are null (not registered beforehand).
If not, MspInit() or MspDeInit() are not null, HAL_RTC_Init()/HAL_RTC_DeInit()
keep and use the user MspInit()/MspDeInit() callbacks (registered beforehand).
[..]
Callbacks can be registered/unregistered in HAL_RTC_STATE_READY state only.
- Exception done MspInit()/MspDeInit() that can be registered/unregistered
+ Exception done for MspInit() and MspDeInit() that can be registered/unregistered
in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state.
Thus registered (user) MspInit()/MspDeInit() callbacks can be used during the
Init/DeInit.
- In that case first register the MspInit()/MspDeInit() user callbacks
- using HAL_RTC_RegisterCallback() before calling HAL_RTC_DeInit()
- or HAL_RTC_Init() functions.
- [..]
- When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or
- not defined, the callback registration feature is not available and all
- callbacks are set to the corresponding weak functions.
+ In that case first register the MspInit()/MspDeInit() user callbacks using
+ HAL_RTC_RegisterCallback() before calling HAL_RTC_DeInit() or HAL_RTC_Init()
+ functions.
@endverbatim
******************************************************************************
@@ -437,12 +443,13 @@
* @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID
* @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID Timestamp Event Callback ID
* @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID Wakeup Timer Event Callback ID
- * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID
- * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID
- * @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID
- * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID
- * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID
- * @note HAL_RTC_TAMPER3_EVENT_CB_ID is not applicable to all devices.
+ * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Event Callback ID
+ * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Event Callback ID
+ * @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Event Callback ID (*)
+ * @arg @ref HAL_RTC_MSPINIT_CB_ID MSP Init callback ID
+ * @arg @ref HAL_RTC_MSPDEINIT_CB_ID MSP DeInit callback ID
+ *
+ * (*) value not applicable to all devices.
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
@@ -547,12 +554,13 @@
* @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID
* @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID Timestamp Event Callback ID
* @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID Wakeup Timer Event Callback ID
- * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID
- * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID
- * @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID
- * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID
- * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID
- * @note HAL_RTC_TAMPER3_EVENT_CB_ID is not applicable to all devices.
+ * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Event Callback ID
+ * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Event Callback ID
+ * @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Event Callback ID (*)
+ * @arg @ref HAL_RTC_MSPINIT_CB_ID MSP Init callback ID
+ * @arg @ref HAL_RTC_MSPDEINIT_CB_ID MSP DeInit callback ID
+ *
+ * (*) value not applicable to all devices.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID)
@@ -1059,7 +1067,7 @@
tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
- ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_TR_PM_Pos) | \
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \
((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
((uint32_t)sAlarm->AlarmMask));
@@ -1092,7 +1100,7 @@
tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \
((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \
((uint32_t) sAlarm->AlarmTime.Seconds) | \
- ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_TR_PM_Pos) | \
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \
((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \
((uint32_t) sAlarm->AlarmDateWeekDaySel) | \
((uint32_t) sAlarm->AlarmMask));
@@ -1105,16 +1113,15 @@
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- /* Configure the Alarm register */
if (sAlarm->Alarm == RTC_ALARM_A)
{
- /* Disable the Alarm A */
+ /* Disable Alarm A */
__HAL_RTC_ALARMA_DISABLE(hrtc);
/* In case interrupt mode is used, the interrupt source must be disabled */
__HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
- /* Clear the Alarm flag */
+ /* Clear Alarm A flag */
__HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
/* Get tick */
@@ -1137,21 +1144,22 @@
}
}
+ /* Configure Alarm A register */
hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
- /* Configure the Alarm A Subseconds register */
+ /* Configure Alarm A Subseconds register */
hrtc->Instance->ALRMASSR = subsecondtmpreg;
- /* Configure the Alarm state: Enable Alarm */
+ /* Enable Alarm A */
__HAL_RTC_ALARMA_ENABLE(hrtc);
}
else
{
- /* Disable the Alarm B */
+ /* Disable Alarm B */
__HAL_RTC_ALARMB_DISABLE(hrtc);
/* In case interrupt mode is used, the interrupt source must be disabled */
__HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB);
- /* Clear the Alarm flag */
+ /* Clear Alarm B flag */
__HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
/* Get tick */
@@ -1174,10 +1182,11 @@
}
}
+ /* Configure Alarm B register */
hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
- /* Configure the Alarm B Subseconds register */
+ /* Configure Alarm B Subseconds register */
hrtc->Instance->ALRMBSSR = subsecondtmpreg;
- /* Configure the Alarm state: Enable Alarm */
+ /* Enable Alarm B */
__HAL_RTC_ALARMB_ENABLE(hrtc);
}
@@ -1256,7 +1265,7 @@
tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
- ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_TR_PM_Pos) | \
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \
((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
((uint32_t)sAlarm->AlarmMask));
@@ -1289,7 +1298,7 @@
tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \
((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \
((uint32_t) sAlarm->AlarmTime.Seconds) | \
- ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_TR_PM_Pos) | \
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \
((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \
((uint32_t) sAlarm->AlarmDateWeekDaySel) | \
((uint32_t) sAlarm->AlarmMask));
@@ -1302,13 +1311,12 @@
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- /* Configure the Alarm register */
if (sAlarm->Alarm == RTC_ALARM_A)
{
- /* Disable the Alarm A */
+ /* Disable Alarm A */
__HAL_RTC_ALARMA_DISABLE(hrtc);
- /* Clear the Alarm flag */
+ /* Clear Alarm A flag */
__HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
/* Wait till RTC ALRAWF flag is set and if timeout is reached exit */
@@ -1329,20 +1337,21 @@
}
} while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U);
+ /* Configure Alarm A register */
hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
- /* Configure the Alarm A Subseconds register */
+ /* Configure Alarm A Subseconds register */
hrtc->Instance->ALRMASSR = subsecondtmpreg;
- /* Configure the Alarm state: Enable Alarm */
+ /* Enable Alarm A */
__HAL_RTC_ALARMA_ENABLE(hrtc);
- /* Configure the Alarm interrupt */
+ /* Enable Alarm A interrupt */
__HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRA);
}
else
{
- /* Disable the Alarm B */
+ /* Disable Alarm B */
__HAL_RTC_ALARMB_DISABLE(hrtc);
- /* Clear the Alarm flag */
+ /* Clear Alarm B flag */
__HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
/* Reload the counter */
@@ -1366,16 +1375,17 @@
}
} while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U);
+ /* Configure Alarm B register */
hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
- /* Configure the Alarm B Subseconds register */
+ /* Configure Alarm B Subseconds register */
hrtc->Instance->ALRMBSSR = subsecondtmpreg;
- /* Configure the Alarm state: Enable Alarm */
+ /* Enable Alarm B */
__HAL_RTC_ALARMB_ENABLE(hrtc);
- /* Configure the Alarm interrupt */
+ /* Enable Alarm B interrupt */
__HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRB);
}
- /* RTC Alarm Interrupt Configuration: EXTI configuration */
+ /* Enable and configure the EXTI line associated to the RTC Alarm interrupt */
__HAL_RTC_ALARM_EXTI_ENABLE_IT();
__HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();
@@ -1427,7 +1437,7 @@
/* Get tick */
tickstart = HAL_GetTick();
- /* Wait till RTC ALRxWF flag is set and if timeout is reached exit */
+ /* Wait till RTC ALRAWF flag is set and if timeout is reached exit */
while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U)
{
if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
@@ -1455,7 +1465,7 @@
/* Get tick */
tickstart = HAL_GetTick();
- /* Wait till RTC ALRxWF flag is set and if timeout is reached exit */
+ /* Wait till RTC ALRBWF flag is set and if timeout is reached exit */
while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U)
{
if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
@@ -1552,7 +1562,7 @@
*/
void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc)
{
- /* Clear the EXTI's line Flag for RTC Alarm */
+ /* Clear the EXTI flag associated to the RTC Alarm interrupt */
__HAL_RTC_ALARM_EXTI_CLEAR_FLAG();
/* Get the Alarm A interrupt source enable status */
diff --git a/Src/stm32f3xx_hal_rtc_ex.c b/Src/stm32f3xx_hal_rtc_ex.c
index 44c5f91..c192ead 100644
--- a/Src/stm32f3xx_hal_rtc_ex.c
+++ b/Src/stm32f3xx_hal_rtc_ex.c
@@ -54,7 +54,7 @@
*** Tamper configuration ***
============================
[..]
- (+) To Enable the RTC Tamper and configure the Tamper filter count, trigger
+ (+) To enable the RTC Tamper and configure the Tamper filter count, trigger
Edge or Level according to the Tamper filter value (if equal to 0 Edge
else Level), sampling frequency, precharge or discharge and Pull-UP use
the HAL_RTCEx_SetTamper() function.
@@ -84,9 +84,9 @@
This cycle is maintained by a 20-bit counter clocked by RTCCLK.
(+) The smooth calibration register (RTC_CALR) specifies the number of RTCCLK
clock cycles to be masked during the 32-second cycle.
- (+) The RTC Smooth Digital Calibration value and the corresponding calibration
- cycle period (32s, 16s, or 8s) can be calibrated using the
- HAL_RTCEx_SetSmoothCalib() function.
+ (+) To configure the RTC Smooth Digital Calibration value and the corresponding
+ calibration cycle period (32s,16s and 8s) use the HAL_RTCEx_SetSmoothCalib()
+ function.
@endverbatim
******************************************************************************
@@ -265,7 +265,7 @@
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
- /* RTC Timestamp Interrupt Configuration: EXTI configuration */
+ /* Enable and configure the EXTI line associated to the RTC Timestamp and Tamper interrupts */
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();
@@ -296,7 +296,7 @@
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- /* In case of interrupt mode is used, the interrupt source must disabled */
+ /* In case interrupt mode is used, the interrupt source must disabled */
__HAL_RTC_TIMESTAMP_DISABLE_IT(hrtc, RTC_IT_TS);
/* Get the RTC_CR register and clear the bits to be configured */
@@ -513,7 +513,7 @@
/* Copy desired configuration into configuration register */
hrtc->Instance->TAFCR = tmpreg;
- /* RTC Tamper Interrupt Configuration: EXTI configuration */
+ /* Enable and configure the EXTI line associated to the RTC Timestamp and Tamper interrupts */
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();
@@ -534,8 +534,9 @@
* This parameter can be any combination of the following values:
* @arg RTC_TAMPER_1: Tamper 1
* @arg RTC_TAMPER_2: Tamper 2
- * @arg RTC_TAMPER_3: Tamper 3
- * @note RTC_TAMPER_3 is not applicable to all devices.
+ * @arg RTC_TAMPER_3: Tamper 3 (*)
+ *
+ * (*) value not applicable to all devices.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper)
@@ -566,7 +567,7 @@
*/
void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
{
- /* Clear the EXTI's Flag for RTC Timestamp and Tamper */
+ /* Clear the EXTI flag associated to the RTC Timestamp and Tamper interrupts */
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG();
/* Get the Timestamp interrupt source enable status */
@@ -1060,7 +1061,7 @@
/* Configure the Wakeup Timer counter */
hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
- /* RTC wakeup timer Interrupt Configuration: EXTI configuration */
+ /* Enable and configure the EXTI line associated to the RTC Wakeup Timer interrupt */
__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
@@ -1102,7 +1103,7 @@
/* Disable the Wakeup Timer */
__HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
- /* In case of interrupt mode is used, the interrupt source must disabled */
+ /* In case interrupt mode is used, the interrupt source must disabled */
__HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc, RTC_IT_WUT);
/* Get tick */
@@ -1161,7 +1162,7 @@
*/
void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
{
- /* Clear the EXTI's line Flag for RTC WakeUpTimer */
+ /* Clear the EXTI flag associated to the RTC Wakeup Timer interrupt */
__HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG();
/* Get the pending status of the Wakeup timer Interrupt */
@@ -1281,7 +1282,7 @@
/* Check the parameters */
assert_param(IS_RTC_BKP(BackupRegister));
- tmp = (uint32_t) & (hrtc->Instance->BKP0R);
+ tmp = (uint32_t) &(hrtc->Instance->BKP0R);
tmp += (BackupRegister * 4U);
/* Write the specified register */
@@ -1307,7 +1308,7 @@
/* Check the parameters */
assert_param(IS_RTC_BKP(BackupRegister));
- tmp = (uint32_t) & (hrtc->Instance->BKP0R);
+ tmp = (uint32_t) &(hrtc->Instance->BKP0R);
tmp += (BackupRegister * 4U);
/* Read the specified register */
diff --git a/Src/stm32f3xx_hal_sdadc.c b/Src/stm32f3xx_hal_sdadc.c
index 24b912f..d40d3c1 100644
--- a/Src/stm32f3xx_hal_sdadc.c
+++ b/Src/stm32f3xx_hal_sdadc.c
@@ -2,7 +2,7 @@
******************************************************************************
* @file stm32f3xx_hal_sdadc.c
* @author MCD Application Team
- * @brief This file provides firmware functions to manage the following
+ * @brief This file provides firmware functions to manage the following
* functionalities of the Sigma-Delta Analog to Digital Converter
* (SDADC) peripherals:
* + Initialization and Configuration
@@ -25,11 +25,11 @@
@verbatim
==============================================================================
##### SDADC specific features #####
- ==============================================================================
- [..]
+ ==============================================================================
+ [..]
(#) 16-bit sigma delta architecture.
(#) Self calibration.
- (#) Interrupt generation at the end of calibration, regular/injected conversion
+ (#) Interrupt generation at the end of calibration, regular/injected conversion
and in case of overrun events.
(#) Single and continuous conversion modes.
(#) External trigger option with configurable polarity for injected conversion.
@@ -71,7 +71,7 @@
*** Regular channel conversion ***
============================================
- [..]
+ [..]
(#) Select trigger for regular conversion using
HAL_SDADC_SelectRegularTrigger.
(#) Select regular channel and enable/disable continuous mode using
@@ -80,19 +80,19 @@
or HAL_SDADC_Start_DMA.
(#) In polling mode, use HAL_SDADC_PollForConversion to detect the end of
regular conversion.
- (#) In interrupt mode, HAL_SDADC_ConvCpltCallback will be called at the
+ (#) In interrupt mode, HAL_SDADC_ConvCpltCallback will be called at the
end of regular conversion.
(#) Get value of regular conversion using HAL_SDADC_GetValue.
- (#) In DMA mode, HAL_SDADC_ConvHalfCpltCallback and
- HAL_SDADC_ConvCpltCallback will be called respectively at the half
+ (#) In DMA mode, HAL_SDADC_ConvHalfCpltCallback and
+ HAL_SDADC_ConvCpltCallback will be called respectively at the half
transfer and at the transfer complete.
(#) Stop regular conversion using HAL_SDADC_Stop, HAL_SDADC_Stop_IT
or HAL_SDADC_Stop_DMA.
*** Injected channels conversion ***
============================================
- [..]
- (#) Enable/disable delay on injected conversion using
+ [..]
+ (#) Enable/disable delay on injected conversion using
HAL_SDADC_SelectInjectedDelay.
(#) If external trigger is used for injected conversion, configure this
trigger using HAL_SDADC_SelectInjectedExtTrigger.
@@ -106,12 +106,12 @@
end of injected conversion.
(#) In interrupt mode, HAL_SDADC_InjectedConvCpltCallback will be called
at the end of injected conversion.
- (#) Get value of injected conversion and corresponding channel using
+ (#) Get value of injected conversion and corresponding channel using
HAL_SDADC_InjectedGetValue.
- (#) In DMA mode, HAL_SDADC_InjectedConvHalfCpltCallback and
+ (#) In DMA mode, HAL_SDADC_InjectedConvHalfCpltCallback and
HAL_SDADC_InjectedConvCpltCallback will be called respectively at the
half transfer and at the transfer complete.
- (#) Stop injected conversion using HAL_SDADC_InjectedStop,
+ (#) Stop injected conversion using HAL_SDADC_InjectedStop,
HAL_SDADC_InjectedStop_IT or HAL_SDADC_InjectedStop_DMA.
*** Multi mode regular channels conversions ***
@@ -124,15 +124,15 @@
(#) Select regular channel for SDADC1 and SDADC2 (or SDADC3) using
HAL_SDADC_ConfigChannel.
(#) Start regular conversion for SDADC2 (or SDADC3) with HAL_SDADC_Start.
- (#) Start regular conversion for SDADC1 using HAL_SDADC_Start,
+ (#) Start regular conversion for SDADC1 using HAL_SDADC_Start,
HAL_SDADC_Start_IT or HAL_SDADC_MultiModeStart_DMA.
(#) In polling mode, use HAL_SDADC_PollForConversion to detect the end of
regular conversion for SDADC1.
- (#) In interrupt mode, HAL_SDADC_ConvCpltCallback will be called at the
+ (#) In interrupt mode, HAL_SDADC_ConvCpltCallback will be called at the
end of regular conversion for SDADC1.
(#) Get value of regular conversions using HAL_SDADC_MultiModeGetValue.
- (#) In DMA mode, HAL_SDADC_ConvHalfCpltCallback and
- HAL_SDADC_ConvCpltCallback will be called respectively at the half
+ (#) In DMA mode, HAL_SDADC_ConvHalfCpltCallback and
+ HAL_SDADC_ConvCpltCallback will be called respectively at the half
transfer and at the transfer complete for SDADC1.
(#) Stop regular conversion using HAL_SDADC_Stop, HAL_SDADC_Stop_IT
or HAL_SDADC_MultiModeStop_DMA for SDADC1.
@@ -143,29 +143,29 @@
[..]
(#) Select type of multimode (SDADC1/SDADC2 or SDADC1/SDADC3) using
HAL_SDADC_InjectedMultiModeConfigChannel.
- (#) Select software or external trigger for SDADC1 and synchronized
+ (#) Select software or external trigger for SDADC1 and synchronized
trigger for SDADC2 (or SDADC3) using HAL_SDADC_SelectInjectedTrigger.
(#) Select injected channels for SDADC1 and SDADC2 (or SDADC3) using
HAL_SDADC_InjectedConfigChannel.
- (#) Start injected conversion for SDADC2 (or SDADC3) with
+ (#) Start injected conversion for SDADC2 (or SDADC3) with
HAL_SDADC_InjectedStart.
(#) Start injected conversion for SDADC1 using HAL_SDADC_InjectedStart,
HAL_SDADC_InjectedStart_IT or HAL_SDADC_InjectedMultiModeStart_DMA.
- (#) In polling mode, use HAL_SDADC_InjectedPollForConversion to detect
+ (#) In polling mode, use HAL_SDADC_InjectedPollForConversion to detect
the end of injected conversion for SDADC1.
(#) In interrupt mode, HAL_SDADC_InjectedConvCpltCallback will be called
at the end of injected conversion for SDADC1.
- (#) Get value of injected conversions using
+ (#) Get value of injected conversions using
HAL_SDADC_InjectedMultiModeGetValue.
- (#) In DMA mode, HAL_SDADC_InjectedConvHalfCpltCallback and
+ (#) In DMA mode, HAL_SDADC_InjectedConvHalfCpltCallback and
HAL_SDADC_InjectedConvCpltCallback will be called respectively at the
half transfer and at the transfer complete for SDADC1.
- (#) Stop injected conversion using HAL_SDADC_InjectedStop,
+ (#) Stop injected conversion using HAL_SDADC_InjectedStop,
HAL_SDADC_InjectedStop_IT or HAL_SDADC_InjecteddMultiModeStop_DMA
for SDADC1.
(#) Stop injected conversion using HAL_SDADC_InjectedStop for SDADC2
(or SDADC3).
-
+
*** Callback registration ***
=============================================
[..]
@@ -232,9 +232,9 @@
When the compilation flag USE_HAL_SDADC_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
-
+
@endverbatim
- */
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal.h"
@@ -248,7 +248,7 @@
/** @defgroup SDADC SDADC
* @brief SDADC HAL driver modules
* @{
- */
+ */
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
@@ -294,16 +294,16 @@
*/
/** @defgroup SDADC_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and de-initialization functions
+ * @brief Initialization and de-initialization functions
*
-@verbatim
+@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..] This section provides functions allowing to:
- (+) Initialize the SDADC.
- (+) De-initialize the SDADC.
-
+ (+) Initialize the SDADC.
+ (+) De-initialize the SDADC.
+
@endverbatim
* @{
*/
@@ -318,19 +318,21 @@
*/
HAL_StatusTypeDef HAL_SDADC_Init(SDADC_HandleTypeDef* hsdadc)
{
+ uint32_t tickstart;
+
/* Check SDADC handle */
if(hsdadc == NULL)
{
return HAL_ERROR;
}
-
+
/* Check parameters */
assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
assert_param(IS_SDADC_LOWPOWER_MODE(hsdadc->Init.IdleLowPowerMode));
assert_param(IS_SDADC_FAST_CONV_MODE(hsdadc->Init.FastConversionMode));
assert_param(IS_SDADC_SLOW_CLOCK_MODE(hsdadc->Init.SlowClockMode));
assert_param(IS_SDADC_VREF(hsdadc->Init.ReferenceVoltage));
-
+
/* Initialize SDADC variables with default values */
hsdadc->RegularContMode = SDADC_CONTINUOUS_CONV_OFF;
hsdadc->InjectedContMode = SDADC_CONTINUOUS_CONV_OFF;
@@ -342,7 +344,7 @@
hsdadc->RegularMultimode = SDADC_MULTIMODE_SDADC1_SDADC2;
hsdadc->InjectedMultimode = SDADC_MULTIMODE_SDADC1_SDADC2;
hsdadc->ErrorCode = SDADC_ERROR_NONE;
-
+
#if (USE_HAL_SDADC_REGISTER_CALLBACKS == 1)
if(hsdadc->State == HAL_SDADC_STATE_RESET)
{
@@ -354,19 +356,19 @@
hsdadc->CalibrationCpltCallback = HAL_SDADC_CalibrationCpltCallback;
hsdadc->ErrorCallback = HAL_SDADC_ErrorCallback;
}
-
+
if (hsdadc->MspInitCallback == NULL)
{
hsdadc->MspInitCallback = HAL_SDADC_MspInit; /* Legacy weak MspInit */
}
-
+
/* Init the low level hardware */
hsdadc->MspInitCallback(hsdadc);
#else
/* Init the low level hardware */
HAL_SDADC_MspInit(hsdadc);
#endif /* USE_HAL_SDADC_REGISTER_CALLBACKS */
-
+
/* Set idle low power and slow clock modes */
hsdadc->Instance->CR1 &= ~(SDADC_CR1_SBI|SDADC_CR1_PDI|SDADC_CR1_SLOWCK);
hsdadc->Instance->CR1 |= (hsdadc->Init.IdleLowPowerMode | \
@@ -384,26 +386,31 @@
/* present in SDADC1 register. */
SDADC1->CR1 &= ~(SDADC_CR1_REFV);
SDADC1->CR1 |= hsdadc->Init.ReferenceVoltage;
-
+
/* Wait at least 2ms before setting ADON */
HAL_Delay(2U);
}
-
+
/* Enable SDADC */
hsdadc->Instance->CR2 |= SDADC_CR2_ADON;
/* Wait end of stabilization */
+ tickstart = HAL_GetTick();
while((hsdadc->Instance->ISR & SDADC_ISR_STABIP) != 0UL)
{
+ if((HAL_GetTick()-tickstart) > SDADC_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
}
-
+
/* Set SDADC to ready state */
hsdadc->State = HAL_SDADC_STATE_READY;
-
+
/* Return HAL status */
return HAL_OK;
}
-
+
/**
* @brief De-initializes the SDADC.
* @param hsdadc SDADC handle.
@@ -438,7 +445,7 @@
{
hsdadc->MspDeInitCallback = HAL_SDADC_MspDeInit; /* Legacy weak MspDeInit */
}
-
+
/* DeInit the low level hardware */
hsdadc->MspDeInitCallback(hsdadc);
#else
@@ -452,7 +459,7 @@
/* Return function status */
return HAL_OK;
}
-
+
/**
* @brief Initializes the SDADC MSP.
* @param hsdadc SDADC handle
@@ -465,7 +472,7 @@
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SDADC_MspInit could be implemented in the user file.
- */
+ */
}
/**
@@ -480,7 +487,7 @@
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SDADC_MspDeInit could be implemented in the user file.
- */
+ */
}
#if (USE_HAL_SDADC_REGISTER_CALLBACKS == 1)
/**
@@ -504,7 +511,7 @@
HAL_StatusTypeDef HAL_SDADC_RegisterCallback(SDADC_HandleTypeDef *hsdadc, HAL_SDADC_CallbackIDTypeDef CallbackID, pSDADC_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
-
+
if (pCallback == NULL)
{
/* Update the error code */
@@ -512,7 +519,7 @@
return HAL_ERROR;
}
-
+
if (HAL_SDADC_STATE_READY == hsdadc->State)
{
switch (CallbackID)
@@ -520,35 +527,35 @@
case HAL_SDADC_CONVERSION_HALF_CB_ID :
hsdadc->ConvHalfCpltCallback = pCallback;
break;
-
+
case HAL_SDADC_CONVERSION_COMPLETE_CB_ID :
hsdadc->ConvCpltCallback = pCallback;
break;
-
+
case HAL_SDADC_INJ_CONVERSION_HALF_CB_ID :
hsdadc->InjectedConvHalfCpltCallback = pCallback;
break;
-
+
case HAL_SDADC_INJ_CONVERSION_COMPLETE_CB_ID :
hsdadc->InjectedConvCpltCallback = pCallback;
break;
-
+
case HAL_SDADC_CALIBRATION_COMPLETE_CB_ID :
hsdadc->CalibrationCpltCallback = pCallback;
break;
-
+
case HAL_SDADC_ERROR_CB_ID :
hsdadc->ErrorCallback = pCallback;
break;
-
+
case HAL_SDADC_MSPINIT_CB_ID :
hsdadc->MspInitCallback = pCallback;
break;
-
+
case HAL_SDADC_MSPDEINIT_CB_ID :
hsdadc->MspDeInitCallback = pCallback;
break;
-
+
default :
/* Update the error code */
hsdadc->ErrorCode |= SDADC_ERROR_INVALID_CALLBACK;
@@ -565,15 +572,15 @@
case HAL_SDADC_MSPINIT_CB_ID :
hsdadc->MspInitCallback = pCallback;
break;
-
+
case HAL_SDADC_MSPDEINIT_CB_ID :
hsdadc->MspDeInitCallback = pCallback;
break;
-
+
default :
/* Update the error code */
hsdadc->ErrorCode |= SDADC_ERROR_INVALID_CALLBACK;
-
+
/* Return error status */
status = HAL_ERROR;
break;
@@ -583,11 +590,11 @@
{
/* Update the error code */
hsdadc->ErrorCode |= SDADC_ERROR_INVALID_CALLBACK;
-
+
/* Return error status */
status = HAL_ERROR;
}
-
+
return status;
}
@@ -611,7 +618,7 @@
HAL_StatusTypeDef HAL_SDADC_UnRegisterCallback(SDADC_HandleTypeDef *hsdadc, HAL_SDADC_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
-
+
if (HAL_SDADC_STATE_READY == hsdadc->State)
{
switch (CallbackID)
@@ -619,39 +626,39 @@
case HAL_SDADC_CONVERSION_HALF_CB_ID :
hsdadc->ConvHalfCpltCallback = HAL_SDADC_ConvHalfCpltCallback;
break;
-
+
case HAL_SDADC_CONVERSION_COMPLETE_CB_ID :
hsdadc->ConvCpltCallback = HAL_SDADC_ConvCpltCallback;
break;
-
+
case HAL_SDADC_INJ_CONVERSION_HALF_CB_ID :
hsdadc->InjectedConvHalfCpltCallback = HAL_SDADC_InjectedConvHalfCpltCallback;
break;
-
+
case HAL_SDADC_INJ_CONVERSION_COMPLETE_CB_ID :
hsdadc->InjectedConvCpltCallback = HAL_SDADC_InjectedConvCpltCallback;
break;
-
+
case HAL_SDADC_CALIBRATION_COMPLETE_CB_ID :
hsdadc->CalibrationCpltCallback = HAL_SDADC_CalibrationCpltCallback;
break;
-
+
case HAL_SDADC_ERROR_CB_ID :
hsdadc->ErrorCallback = HAL_SDADC_ErrorCallback;
break;
-
+
case HAL_SDADC_MSPINIT_CB_ID :
hsdadc->MspInitCallback = HAL_SDADC_MspInit;
break;
-
+
case HAL_SDADC_MSPDEINIT_CB_ID :
hsdadc->MspDeInitCallback = HAL_SDADC_MspDeInit;
break;
-
+
default :
/* Update the error code */
hsdadc->ErrorCode |= SDADC_ERROR_INVALID_CALLBACK;
-
+
/* Return error status */
status = HAL_ERROR;
break;
@@ -664,15 +671,15 @@
case HAL_SDADC_MSPINIT_CB_ID :
hsdadc->MspInitCallback = HAL_SDADC_MspInit; /* Legacy weak MspInit */
break;
-
+
case HAL_SDADC_MSPDEINIT_CB_ID :
hsdadc->MspDeInitCallback = HAL_SDADC_MspDeInit; /* Legacy weak MspDeInit */
break;
-
+
default :
/* Update the error code */
hsdadc->ErrorCode |= SDADC_ERROR_INVALID_CALLBACK;
-
+
/* Return error status */
status = HAL_ERROR;
break;
@@ -682,11 +689,11 @@
{
/* Update the error code */
hsdadc->ErrorCode |= SDADC_ERROR_INVALID_CALLBACK;
-
+
/* Return error status */
status = HAL_ERROR;
}
-
+
return status;
}
@@ -699,10 +706,10 @@
/** @defgroup SDADC_Exported_Functions_Group2 peripheral control functions
* @brief Peripheral control functions
*
-@verbatim
+@verbatim
===============================================================================
##### Peripheral control functions #####
- ===============================================================================
+ ===============================================================================
[..] This section provides functions allowing to:
(+) Program one of the three different configurations for channels.
(+) Associate channel to one of configurations.
@@ -728,7 +735,7 @@
* @param ConfParamStruct Parameters to apply for this configuration.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SDADC_PrepareChannelConfig(SDADC_HandleTypeDef *hsdadc,
+HAL_StatusTypeDef HAL_SDADC_PrepareChannelConfig(SDADC_HandleTypeDef *hsdadc,
uint32_t ConfIndex,
SDADC_ConfParamTypeDef* ConfParamStruct)
{
@@ -829,7 +836,7 @@
else
{
hsdadc->Instance->CONFCHR2 = (uint32_t) (ConfIndex);
- }
+ }
/* Exit init mode */
SDADC_ExitInitMode(hsdadc);
}
@@ -858,7 +865,7 @@
assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
assert_param(IS_SDADC_REGULAR_CHANNEL(Channel));
assert_param(IS_SDADC_CONTINUOUS_MODE(ContinuousMode));
-
+
/* Check SDADC state */
if((hsdadc->State != HAL_SDADC_STATE_RESET) && (hsdadc->State != HAL_SDADC_STATE_ERROR))
{
@@ -866,11 +873,11 @@
hsdadc->Instance->CR2 &= (uint32_t) ~(SDADC_CR2_RCH | SDADC_CR2_RCONT);
if(ContinuousMode == SDADC_CONTINUOUS_CONV_ON)
{
- hsdadc->Instance->CR2 |= (uint32_t) ((Channel & SDADC_MSB_MASK) | SDADC_CR2_RCONT);
+ hsdadc->Instance->CR2 |= (uint32_t) ((Channel & SDADC_MSB_MASK) | SDADC_CR2_RCONT);
}
else
{
- hsdadc->Instance->CR2 |= (uint32_t) ((Channel & SDADC_MSB_MASK));
+ hsdadc->Instance->CR2 |= (uint32_t) ((Channel & SDADC_MSB_MASK));
}
/* Store continuous mode information */
hsdadc->RegularContMode = ContinuousMode;
@@ -903,7 +910,7 @@
assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
assert_param(IS_SDADC_INJECTED_CHANNEL(Channel));
assert_param(IS_SDADC_CONTINUOUS_MODE(ContinuousMode));
-
+
/* Check SDADC state */
if((hsdadc->State != HAL_SDADC_STATE_RESET) && (hsdadc->State != HAL_SDADC_STATE_ERROR))
{
@@ -912,7 +919,7 @@
/* Set or clear JCONT bit in SDADC_CR2 */
if(ContinuousMode == SDADC_CONTINUOUS_CONV_ON)
{
- hsdadc->Instance->CR2 |= SDADC_CR2_JCONT;
+ hsdadc->Instance->CR2 |= SDADC_CR2_JCONT;
}
else
{
@@ -964,7 +971,7 @@
}
else
{
- status = HAL_ERROR;
+ status = HAL_ERROR;
}
/* Return function status */
return status;
@@ -1004,7 +1011,7 @@
}
else
{
- status = HAL_ERROR;
+ status = HAL_ERROR;
}
/* Return function status */
return status;
@@ -1142,7 +1149,7 @@
}
else
{
- status = HAL_ERROR;
+ status = HAL_ERROR;
}
/* Return function status */
return status;
@@ -1181,7 +1188,7 @@
}
else
{
- status = HAL_ERROR;
+ status = HAL_ERROR;
}
/* Return function status */
return status;
@@ -1192,12 +1199,12 @@
*/
/** @defgroup SDADC_Exported_Functions_Group3 Input and Output operation functions
- * @brief IO operation Control functions
+ * @brief IO operation Control functions
*
-@verbatim
+@verbatim
===============================================================================
##### IO operation functions #####
- ===============================================================================
+ ===============================================================================
[..] This section provides functions allowing to:
(+) Start calibration.
(+) Poll for the end of calibration.
@@ -1296,7 +1303,7 @@
else
{
/* Get timeout */
- tickstart = HAL_GetTick();
+ tickstart = HAL_GetTick();
/* Wait EOCALF bit in SDADC_ISR register */
while((hsdadc->Instance->ISR & SDADC_ISR_EOCALF) != SDADC_ISR_EOCALF)
@@ -1430,7 +1437,7 @@
else
{
/* Get timeout */
- tickstart = HAL_GetTick();
+ tickstart = HAL_GetTick();
/* Wait REOCF bit in SDADC_ISR register */
while((hsdadc->Instance->ISR & SDADC_ISR_REOCF) != SDADC_ISR_REOCF)
@@ -1613,7 +1620,7 @@
{
hsdadc->hdma->XferHalfCpltCallback = SDADC_DMARegularHalfConvCplt;
}
-
+
/* Set RDMAEN bit in SDADC_CR1 register */
hsdadc->Instance->CR1 |= SDADC_CR1_RDMAEN;
@@ -1749,7 +1756,7 @@
else
{
/* Get timeout */
- tickstart = HAL_GetTick();
+ tickstart = HAL_GetTick();
/* Wait JEOCF bit in SDADC_ISR register */
while((hsdadc->Instance->ISR & SDADC_ISR_JEOCF) != SDADC_ISR_JEOCF)
@@ -1942,7 +1949,7 @@
{
hsdadc->hdma->XferHalfCpltCallback = SDADC_DMAInjectedHalfConvCplt;
}
-
+
/* Set JDMAEN bit in SDADC_CR1 register */
hsdadc->Instance->CR1 |= SDADC_CR1_JDMAEN;
@@ -2028,7 +2035,7 @@
value = hsdadc->Instance->JDATAR;
*Channel = ((value & SDADC_JDATAR_JDATACH) >> SDADC_JDATAR_CH_OFFSET);
value &= SDADC_JDATAR_JDATA;
-
+
/* Return injected conversion value */
return value;
}
@@ -2176,7 +2183,7 @@
uint32_t HAL_SDADC_MultiModeGetValue(SDADC_HandleTypeDef* hsdadc)
{
uint32_t value;
-
+
/* Check parameters and check instance is SDADC1 */
assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
assert_param(hsdadc->Instance == SDADC1);
@@ -2332,7 +2339,7 @@
uint32_t HAL_SDADC_InjectedMultiModeGetValue(SDADC_HandleTypeDef* hsdadc)
{
uint32_t value;
-
+
/* Check parameters and check instance is SDADC1 */
assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
assert_param(hsdadc->Instance == SDADC1);
@@ -2354,7 +2361,7 @@
{
uint32_t tmp_isr = hsdadc->Instance->ISR;
uint32_t tmp_cr1 = hsdadc->Instance->CR1;
-
+
/* Check if end of regular conversion */
if(((tmp_cr1 & SDADC_CR1_REOCIE) == SDADC_CR1_REOCIE) &&
((tmp_isr & SDADC_ISR_REOCF) == SDADC_ISR_REOCF))
@@ -2468,12 +2475,12 @@
{
/* No additional IRQ source */
}
-
+
return;
}
/**
- * @brief Calibration complete callback.
+ * @brief Calibration complete callback.
* @param hsdadc SDADC handle.
* @retval None
*/
@@ -2488,7 +2495,7 @@
}
/**
- * @brief Half regular conversion complete callback.
+ * @brief Half regular conversion complete callback.
* @param hsdadc SDADC handle.
* @retval None
*/
@@ -2503,7 +2510,7 @@
}
/**
- * @brief Regular conversion complete callback.
+ * @brief Regular conversion complete callback.
* @note In interrupt mode, user has to read conversion value in this function
using HAL_SDADC_GetValue or HAL_SDADC_MultiModeGetValue.
* @param hsdadc SDADC handle.
@@ -2520,7 +2527,7 @@
}
/**
- * @brief Half injected conversion complete callback.
+ * @brief Half injected conversion complete callback.
* @param hsdadc SDADC handle.
* @retval None
*/
@@ -2535,7 +2542,7 @@
}
/**
- * @brief Injected conversion complete callback.
+ * @brief Injected conversion complete callback.
* @note In interrupt mode, user has to read conversion value in this function
using HAL_SDADC_InjectedGetValue or HAL_SDADC_InjectedMultiModeGetValue.
* @param hsdadc SDADC handle.
@@ -2552,7 +2559,7 @@
}
/**
- * @brief Error callback.
+ * @brief Error callback.
* @param hsdadc SDADC handle.
* @retval None
*/
@@ -2567,11 +2574,11 @@
}
/**
- * @brief DMA half transfer complete callback for regular conversion.
+ * @brief DMA half transfer complete callback for regular conversion.
* @param hdma DMA handle.
* @retval None
*/
-static void SDADC_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma)
+static void SDADC_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma)
{
/* Get SDADC handle */
SDADC_HandleTypeDef* hsdadc = (SDADC_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
@@ -2585,11 +2592,11 @@
}
/**
- * @brief DMA transfer complete callback for regular conversion.
+ * @brief DMA transfer complete callback for regular conversion.
* @param hdma DMA handle.
* @retval None
*/
-static void SDADC_DMARegularConvCplt(DMA_HandleTypeDef *hdma)
+static void SDADC_DMARegularConvCplt(DMA_HandleTypeDef *hdma)
{
/* Get SDADC handle */
SDADC_HandleTypeDef* hsdadc = (SDADC_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
@@ -2603,11 +2610,11 @@
}
/**
- * @brief DMA half transfer complete callback for injected conversion.
+ * @brief DMA half transfer complete callback for injected conversion.
* @param hdma DMA handle.
* @retval None
*/
-static void SDADC_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma)
+static void SDADC_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma)
{
/* Get SDADC handle */
SDADC_HandleTypeDef* hsdadc = (SDADC_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
@@ -2621,11 +2628,11 @@
}
/**
- * @brief DMA transfer complete callback for injected conversion.
+ * @brief DMA transfer complete callback for injected conversion.
* @param hdma DMA handle.
* @retval None
*/
-static void SDADC_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma)
+static void SDADC_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma)
{
/* Get SDADC handle */
SDADC_HandleTypeDef* hsdadc = (SDADC_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
@@ -2639,11 +2646,11 @@
}
/**
- * @brief DMA error callback.
+ * @brief DMA error callback.
* @param hdma DMA handle.
* @retval None
*/
-static void SDADC_DMAError(DMA_HandleTypeDef *hdma)
+static void SDADC_DMAError(DMA_HandleTypeDef *hdma)
{
/* Get SDADC handle */
SDADC_HandleTypeDef* hsdadc = (SDADC_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
@@ -2664,20 +2671,20 @@
*/
/** @defgroup SDADC_Exported_Functions_Group4 Peripheral State functions
- * @brief SDADC Peripheral State functions
+ * @brief SDADC Peripheral State functions
*
-@verbatim
+@verbatim
===============================================================================
##### ADC Peripheral State functions #####
- ===============================================================================
+ ===============================================================================
[..] This subsection provides functions allowing to
(+) Get the SDADC state
(+) Get the SDADC Error
-
+
@endverbatim
* @{
*/
-
+
/**
* @brief This function allows to get the current SDADC state.
* @param hsdadc SDADC handle.
@@ -2697,7 +2704,7 @@
{
return hsdadc->ErrorCode;
}
-
+
/**
* @}
*/
@@ -2714,7 +2721,7 @@
static HAL_StatusTypeDef SDADC_EnterInitMode(SDADC_HandleTypeDef* hsdadc)
{
uint32_t tickstart;
-
+
/* Set INIT bit on SDADC_CR1 register */
hsdadc->Instance->CR1 |= SDADC_CR1_INIT;
@@ -2723,11 +2730,11 @@
while((hsdadc->Instance->ISR & SDADC_ISR_INITRDY) == (uint32_t)RESET)
{
if((HAL_GetTick()-tickstart) > SDADC_TIMEOUT)
- {
+ {
return HAL_TIMEOUT;
- }
+ }
}
-
+
/* Return HAL status */
return HAL_OK;
}
@@ -2752,7 +2759,7 @@
{
uint32_t nbChannels = 0UL;
uint32_t tmp,i;
-
+
/* Get the number of channels from bitfield */
tmp = (uint32_t) (Channels & SDADC_LSB_MASK);
for(i = 0UL ; i < 9UL ; i++)
@@ -2818,7 +2825,7 @@
{
uint32_t tickstart;
__IO uint32_t dummy_read_for_register_reset;
-
+
/* Check continuous mode */
if(hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_ON)
{
@@ -2830,7 +2837,7 @@
hsdadc->Instance->CR2 &= ~(SDADC_CR2_RCONT);
}
/* Wait for the end of regular conversion */
- tickstart = HAL_GetTick();
+ tickstart = HAL_GetTick();
while((hsdadc->Instance->ISR & SDADC_ISR_RCIP) != 0UL)
{
if((HAL_GetTick()-tickstart) > SDADC_TIMEOUT)
@@ -2942,7 +2949,7 @@
{
uint32_t tickstart;
__IO uint32_t dummy_read_for_register_reset;
-
+
/* Check continuous mode */
if(hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_ON)
{
@@ -2954,7 +2961,7 @@
hsdadc->Instance->CR2 &= ~(SDADC_CR2_JCONT);
}
/* Wait for the end of injected conversion */
- tickstart = HAL_GetTick();
+ tickstart = HAL_GetTick();
while((hsdadc->Instance->ISR & SDADC_ISR_JCIP) != 0UL)
{
if((HAL_GetTick()-tickstart) > SDADC_TIMEOUT)
@@ -3022,10 +3029,10 @@
/**
* @}
- */
+ */
#endif /* SDADC1 || SDADC2 || SDADC3 */
#endif /* HAL_SDADC_MODULE_ENABLED */
/**
* @}
- */
+ */
diff --git a/Src/stm32f3xx_hal_smartcard.c b/Src/stm32f3xx_hal_smartcard.c
index a2baef9..cad7b79 100644
--- a/Src/stm32f3xx_hal_smartcard.c
+++ b/Src/stm32f3xx_hal_smartcard.c
@@ -134,7 +134,7 @@
[..]
Use function HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default
- weak (surcharged) function.
+ weak function.
HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
@@ -149,10 +149,10 @@
[..]
By default, after the HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET
- all callbacks are set to the corresponding weak (surcharged) functions:
+ all callbacks are set to the corresponding weak functions:
examples HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback().
Exception done for MspInit and MspDeInit functions that are respectively
- reset to the legacy weak (surcharged) functions in the HAL_SMARTCARD_Init()
+ reset to the legacy weak functions in the HAL_SMARTCARD_Init()
and HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_SMARTCARD_Init() and HAL_SMARTCARD_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
@@ -169,7 +169,7 @@
[..]
When The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available
- and weak (surcharged) callbacks are used.
+ and weak callbacks are used.
@endverbatim
@@ -460,7 +460,7 @@
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User SMARTCARD Callback
- * To be used instead of the weak predefined callback
+ * To be used to override the weak predefined callback
* @note The HAL_SMARTCARD_RegisterCallback() may be called before HAL_SMARTCARD_Init()
* in HAL_SMARTCARD_STATE_RESET to register callbacks for HAL_SMARTCARD_MSPINIT_CB_ID
* and HAL_SMARTCARD_MSPDEINIT_CB_ID
@@ -2282,7 +2282,7 @@
assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
tmpreg |= (uint32_t) hsmartcard->Init.TimeOutValue;
}
- MODIFY_REG(hsmartcard->Instance->RTOR, (USART_RTOR_RTO | USART_RTOR_BLEN), tmpreg);
+ WRITE_REG(hsmartcard->Instance->RTOR, tmpreg);
/*-------------------------- USART BRR Configuration -----------------------*/
SMARTCARD_GETCLOCKSOURCE(hsmartcard, clocksource);
diff --git a/Src/stm32f3xx_hal_smbus.c b/Src/stm32f3xx_hal_smbus.c
index 4b3cdce..06df190 100644
--- a/Src/stm32f3xx_hal_smbus.c
+++ b/Src/stm32f3xx_hal_smbus.c
@@ -926,7 +926,7 @@
uint8_t *pData, uint16_t Size, uint32_t XferOptions)
{
uint32_t tmp;
- uint32_t sizetoxfer = 0U;
+ uint32_t sizetoxfer;
/* Check the parameters */
assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
@@ -960,20 +960,27 @@
}
sizetoxfer = hsmbus->XferSize;
- if ((hsmbus->XferSize > 0U) && ((XferOptions == SMBUS_FIRST_FRAME) ||
- (XferOptions == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) ||
- (XferOptions == SMBUS_FIRST_FRAME_WITH_PEC) ||
- (XferOptions == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC)))
+ if ((sizetoxfer > 0U) && ((XferOptions == SMBUS_FIRST_FRAME) ||
+ (XferOptions == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) ||
+ (XferOptions == SMBUS_FIRST_FRAME_WITH_PEC) ||
+ (XferOptions == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC)))
{
- /* Preload TX register */
- /* Write data to TXDR */
- hsmbus->Instance->TXDR = *hsmbus->pBuffPtr;
+ if (hsmbus->pBuffPtr != NULL)
+ {
+ /* Preload TX register */
+ /* Write data to TXDR */
+ hsmbus->Instance->TXDR = *hsmbus->pBuffPtr;
- /* Increment Buffer pointer */
- hsmbus->pBuffPtr++;
+ /* Increment Buffer pointer */
+ hsmbus->pBuffPtr++;
- hsmbus->XferCount--;
- hsmbus->XferSize--;
+ hsmbus->XferCount--;
+ hsmbus->XferSize--;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
}
/* Send Slave Address */
@@ -1014,8 +1021,15 @@
/* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
{
- hsmbus->XferSize--;
- hsmbus->XferCount--;
+ if (hsmbus->XferSize > 0U)
+ {
+ hsmbus->XferSize--;
+ hsmbus->XferCount--;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
}
}
@@ -2605,8 +2619,11 @@
__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR);
}
- /* Flush TX register */
- SMBUS_Flush_TXDR(hsmbus);
+ if (hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE)
+ {
+ /* Flush TX register */
+ SMBUS_Flush_TXDR(hsmbus);
+ }
/* Store current volatile hsmbus->ErrorCode, misra rule */
tmperror = hsmbus->ErrorCode;
diff --git a/Src/stm32f3xx_hal_spi.c b/Src/stm32f3xx_hal_spi.c
index c6a287e..55a9e12 100644
--- a/Src/stm32f3xx_hal_spi.c
+++ b/Src/stm32f3xx_hal_spi.c
@@ -1359,6 +1359,20 @@
hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
+
+#if (USE_SPI_CRC != 0U)
+ /* Enable CRC Transmission */
+ if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+ {
+ /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
+ if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
+ }
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+#endif /* USE_SPI_CRC */
+
}
while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
{
@@ -1418,6 +1432,19 @@
*(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
hspi->pTxBuffPtr++;
hspi->TxXferCount--;
+
+#if (USE_SPI_CRC != 0U)
+ /* Enable CRC Transmission */
+ if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+ {
+ /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
+ if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
+ }
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+#endif /* USE_SPI_CRC */
}
}
while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
diff --git a/Src/stm32f3xx_hal_spi_ex.c b/Src/stm32f3xx_hal_spi_ex.c
index 4ce240e..37d4be0 100644
--- a/Src/stm32f3xx_hal_spi_ex.c
+++ b/Src/stm32f3xx_hal_spi_ex.c
@@ -76,7 +76,7 @@
* the configuration information for the specified SPI module.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi)
+HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi)
{
__IO uint32_t tmpreg;
uint8_t count = 0U;
diff --git a/Src/stm32f3xx_hal_sram.c b/Src/stm32f3xx_hal_sram.c
index 5dab15c..0853ed3 100644
--- a/Src/stm32f3xx_hal_sram.c
+++ b/Src/stm32f3xx_hal_sram.c
@@ -83,15 +83,15 @@
and a pointer to the user callback function.
Use function HAL_SRAM_UnRegisterCallback() to reset a callback to the default
- weak (surcharged) function. It allows to reset following callbacks:
+ weak (overridden) function. It allows to reset following callbacks:
(+) MspInitCallback : SRAM MspInit.
(+) MspDeInitCallback : SRAM MspDeInit.
This function) takes as parameters the HAL peripheral handle and the Callback ID.
By default, after the HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET
- all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+ all callbacks are reset to the corresponding legacy weak (overridden) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the HAL_SRAM_Init
+ reset to the legacy weak (overridden) functions in the HAL_SRAM_Init
and HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_SRAM_Init and HAL_SRAM_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
@@ -106,7 +106,7 @@
When The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
- and weak (surcharged) callbacks are used.
+ and weak (overridden) callbacks are used.
@endverbatim
******************************************************************************
@@ -737,7 +737,7 @@
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User SRAM Callback
- * To be used instead of the weak (surcharged) predefined callback
+ * To be used to override the weak predefined callback
* @param hsram : SRAM handle
* @param CallbackId : ID of the callback to be registered
* This parameter can be one of the following values:
@@ -757,9 +757,6 @@
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(hsram);
-
state = hsram->State;
if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED))
{
@@ -783,14 +780,12 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hsram);
return status;
}
/**
* @brief Unregister a User SRAM Callback
- * SRAM Callback is redirected to the weak (surcharged) predefined callback
+ * SRAM Callback is redirected to the weak predefined callback
* @param hsram : SRAM handle
* @param CallbackId : ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -805,9 +800,6 @@
HAL_StatusTypeDef status = HAL_OK;
HAL_SRAM_StateTypeDef state;
- /* Process locked */
- __HAL_LOCK(hsram);
-
state = hsram->State;
if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
{
@@ -853,14 +845,12 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hsram);
return status;
}
/**
* @brief Register a User SRAM Callback for DMA transfers
- * To be used instead of the weak (surcharged) predefined callback
+ * To be used to override the weak predefined callback
* @param hsram : SRAM handle
* @param CallbackId : ID of the callback to be registered
* This parameter can be one of the following values:
diff --git a/Src/stm32f3xx_hal_tim.c b/Src/stm32f3xx_hal_tim.c
index adb378b..41218d5 100644
--- a/Src/stm32f3xx_hal_tim.c
+++ b/Src/stm32f3xx_hal_tim.c
@@ -894,7 +894,7 @@
uint32_t tmpsmcr;
/* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
/* Check the TIM channel state */
if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
@@ -986,7 +986,7 @@
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
switch (Channel)
{
@@ -1065,7 +1065,7 @@
uint32_t tmpsmcr;
/* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
/* Set the TIM channel state */
if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
@@ -1227,7 +1227,7 @@
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
switch (Channel)
{
@@ -1565,7 +1565,7 @@
uint32_t tmpsmcr;
/* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
/* Check the TIM channel state */
if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
@@ -1657,7 +1657,7 @@
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
switch (Channel)
{
@@ -1736,7 +1736,7 @@
uint32_t tmpsmcr;
/* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
/* Set the TIM channel state */
if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
@@ -1897,7 +1897,7 @@
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
switch (Channel)
{
@@ -2141,7 +2141,7 @@
HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
/* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
/* Check the TIM channel state */
if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
@@ -2189,7 +2189,7 @@
HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
/* Disable the Input Capture channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
@@ -2225,7 +2225,7 @@
HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
/* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
/* Check the TIM channel state */
if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
@@ -2313,7 +2313,7 @@
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
switch (Channel)
{
@@ -2389,7 +2389,7 @@
HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
/* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
/* Set the TIM channel state */
@@ -2544,7 +2544,7 @@
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
/* Disable the Input Capture channel */
@@ -3850,7 +3850,7 @@
if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
{
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
/* Input capture event */
@@ -3882,7 +3882,7 @@
{
if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
@@ -3912,7 +3912,7 @@
{
if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
@@ -3942,7 +3942,7 @@
{
if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
@@ -3972,7 +3972,7 @@
{
if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PeriodElapsedCallback(htim);
#else
@@ -3985,7 +3985,7 @@
{
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->BreakCallback(htim);
#else
@@ -4013,7 +4013,7 @@
{
if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TriggerCallback(htim);
#else
@@ -4026,7 +4026,7 @@
{
if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
{
- __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->CommutationCallback(htim);
#else
@@ -4586,7 +4586,8 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
- uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength)
+ uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
+ uint32_t BurstLength)
{
HAL_StatusTypeDef status;
@@ -7007,6 +7008,13 @@
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
+
+ /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
+ if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
+ {
+ /* Clear the update flag */
+ CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
+ }
}
/**
@@ -7021,11 +7029,12 @@
uint32_t tmpccer;
uint32_t tmpcr2;
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
@@ -7096,11 +7105,12 @@
uint32_t tmpccer;
uint32_t tmpcr2;
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
@@ -7129,7 +7139,6 @@
tmpccer |= (OC_Config->OCNPolarity << 4U);
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC2NE;
-
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
@@ -7174,11 +7183,12 @@
uint32_t tmpccer;
uint32_t tmpcr2;
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+
/* Disable the Channel 3: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
@@ -7250,11 +7260,12 @@
uint32_t tmpccer;
uint32_t tmpcr2;
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
@@ -7314,11 +7325,12 @@
uint32_t tmpccer;
uint32_t tmpcr2;
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC5E;
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
/* Get the TIMx CCMR1 register value */
@@ -7369,11 +7381,12 @@
uint32_t tmpccer;
uint32_t tmpcr2;
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC6E;
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
/* Get the TIMx CCMR1 register value */
@@ -7558,9 +7571,9 @@
uint32_t tmpccer;
/* Disable the Channel 1: Reset the CC1E Bit */
+ tmpccer = TIMx->CCER;
TIMx->CCER &= ~TIM_CCER_CC1E;
tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
/* Select the Input */
if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
@@ -7648,9 +7661,9 @@
uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */
+ tmpccer = TIMx->CCER;
TIMx->CCER &= ~TIM_CCER_CC2E;
tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
/* Select the Input */
tmpccmr1 &= ~TIM_CCMR1_CC2S;
@@ -7687,9 +7700,9 @@
uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */
+ tmpccer = TIMx->CCER;
TIMx->CCER &= ~TIM_CCER_CC2E;
tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC2F;
@@ -7731,9 +7744,9 @@
uint32_t tmpccer;
/* Disable the Channel 3: Reset the CC3E Bit */
+ tmpccer = TIMx->CCER;
TIMx->CCER &= ~TIM_CCER_CC3E;
tmpccmr2 = TIMx->CCMR2;
- tmpccer = TIMx->CCER;
/* Select the Input */
tmpccmr2 &= ~TIM_CCMR2_CC3S;
@@ -7779,9 +7792,9 @@
uint32_t tmpccer;
/* Disable the Channel 4: Reset the CC4E Bit */
+ tmpccer = TIMx->CCER;
TIMx->CCER &= ~TIM_CCER_CC4E;
tmpccmr2 = TIMx->CCMR2;
- tmpccer = TIMx->CCER;
/* Select the Input */
tmpccmr2 &= ~TIM_CCMR2_CC4S;
diff --git a/Src/stm32f3xx_hal_tim_ex.c b/Src/stm32f3xx_hal_tim_ex.c
index 8394b57..2784849 100644
--- a/Src/stm32f3xx_hal_tim_ex.c
+++ b/Src/stm32f3xx_hal_tim_ex.c
@@ -837,7 +837,7 @@
/* Disable the TIM Break interrupt (only if no more channel is active) */
tmpccer = htim->Instance->CCER;
- if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
+ if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
{
__HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
}
@@ -1083,17 +1083,6 @@
(+) Stop the Complementary PWM and disable interrupts.
(+) Start the Complementary PWM and enable DMA transfers.
(+) Stop the Complementary PWM and disable DMA transfers.
- (+) Start the Complementary Input Capture measurement.
- (+) Stop the Complementary Input Capture.
- (+) Start the Complementary Input Capture and enable interrupts.
- (+) Stop the Complementary Input Capture and disable interrupts.
- (+) Start the Complementary Input Capture and enable DMA transfers.
- (+) Stop the Complementary Input Capture and disable DMA transfers.
- (+) Start the Complementary One Pulse generation.
- (+) Stop the Complementary One Pulse.
- (+) Start the Complementary One Pulse and enable interrupts.
- (+) Stop the Complementary One Pulse and disable interrupts.
-
@endverbatim
* @{
*/
@@ -1319,7 +1308,7 @@
/* Disable the TIM Break interrupt (only if no more channel is active) */
tmpccer = htim->Instance->CCER;
- if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
+ if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
{
__HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
}
@@ -2260,7 +2249,7 @@
*/
/**
- * @brief Hall commutation changed callback in non-blocking mode
+ * @brief Commutation callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
@@ -2274,7 +2263,7 @@
*/
}
/**
- * @brief Hall commutation changed half complete callback in non-blocking mode
+ * @brief Commutation half complete callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
@@ -2289,7 +2278,7 @@
}
/**
- * @brief Hall Break detection callback in non-blocking mode
+ * @brief Break detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
@@ -2305,7 +2294,7 @@
#if defined(TIM_BDTR_BK2E)
/**
- * @brief Hall Break2 detection callback in non blocking mode
+ * @brief Break2 detection callback in non blocking mode
* @param htim: TIM handle
* @retval None
*/
@@ -2457,15 +2446,6 @@
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
}
}
- else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-
- if (hdma->Init.Mode == DMA_NORMAL)
- {
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
- }
- }
else
{
/* nothing to do */
@@ -2534,13 +2514,13 @@
{
uint32_t tmp;
- tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
+ tmp = TIM_CCER_CC1NE << (Channel & 0xFU); /* 0xFU = 15 bits max shift */
/* Reset the CCxNE Bit */
TIMx->CCER &= ~tmp;
/* Set or reset the CCxNE Bit */
- TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
+ TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0xFU)); /* 0xFU = 15 bits max shift */
}
/**
* @}
diff --git a/Src/stm32f3xx_hal_timebase_rtc_alarm_template.c b/Src/stm32f3xx_hal_timebase_rtc_alarm_template.c
index 3537aaa..02b24d0 100644
--- a/Src/stm32f3xx_hal_timebase_rtc_alarm_template.c
+++ b/Src/stm32f3xx_hal_timebase_rtc_alarm_template.c
@@ -103,19 +103,19 @@
HAL_StatusTypeDef status;
#ifdef RTC_CLOCK_SOURCE_LSE
- /* Configue LSE as RTC clock soucre */
+ /* Configure LSE as RTC clock source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
#elif defined (RTC_CLOCK_SOURCE_LSI)
- /* Configue LSI as RTC clock soucre */
+ /* Configure LSI as RTC clock source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
RCC_OscInitStruct.LSIState = RCC_LSI_ON;
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
#elif defined (RTC_CLOCK_SOURCE_HSE)
- /* Configue HSE as RTC clock soucre */
+ /* Configure HSE as RTC clock source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
diff --git a/Src/stm32f3xx_hal_timebase_rtc_wakeup_template.c b/Src/stm32f3xx_hal_timebase_rtc_wakeup_template.c
index ccdbc3f..315c4c4 100644
--- a/Src/stm32f3xx_hal_timebase_rtc_wakeup_template.c
+++ b/Src/stm32f3xx_hal_timebase_rtc_wakeup_template.c
@@ -110,19 +110,19 @@
HAL_StatusTypeDef status;
#ifdef RTC_CLOCK_SOURCE_LSE
- /* Configue LSE as RTC clock soucre */
+ /* Configure LSE as RTC clock source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
#elif defined (RTC_CLOCK_SOURCE_LSI)
- /* Configue LSI as RTC clock soucre */
+ /* Configure LSI as RTC clock source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
RCC_OscInitStruct.LSIState = RCC_LSI_ON;
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
#elif defined (RTC_CLOCK_SOURCE_HSE)
- /* Configue HSE as RTC clock soucre */
+ /* Configure HSE as RTC clock source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
diff --git a/Src/stm32f3xx_hal_uart.c b/Src/stm32f3xx_hal_uart.c
index 04649a6..a6b101f 100644
--- a/Src/stm32f3xx_hal_uart.c
+++ b/Src/stm32f3xx_hal_uart.c
@@ -105,7 +105,7 @@
[..]
Use function HAL_UART_UnRegisterCallback() to reset a callback to the default
- weak (surcharged) function.
+ weak function.
HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
@@ -127,10 +127,10 @@
[..]
By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET
- all callbacks are set to the corresponding weak (surcharged) functions:
+ all callbacks are set to the corresponding weak functions:
examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback().
Exception done for MspInit and MspDeInit functions that are respectively
- reset to the legacy weak (surcharged) functions in the HAL_UART_Init()
+ reset to the legacy weak functions in the HAL_UART_Init()
and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
@@ -147,7 +147,7 @@
[..]
When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available
- and weak (surcharged) callbacks are used.
+ and weak callbacks are used.
@endverbatim
@@ -191,8 +191,8 @@
/** @addtogroup UART_Private_Functions
* @{
*/
-static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
@@ -686,7 +686,7 @@
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User UART Callback
- * To be used instead of the weak predefined callback
+ * To be used to override the weak predefined callback
* @note The HAL_UART_RegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(),
* HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to register
* callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID
@@ -3166,20 +3166,20 @@
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
{
- /* Clear Overrun Error flag*/
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
+ /* Clear Overrun Error flag*/
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
- /* Blocking error : transfer is aborted
- Set the UART state ready to be able to start again the process,
- Disable Rx Interrupts if ongoing */
- UART_EndRxTransfer(huart);
+ /* Blocking error : transfer is aborted
+ Set the UART state ready to be able to start again the process,
+ Disable Rx Interrupts if ongoing */
+ UART_EndRxTransfer(huart);
- huart->ErrorCode = HAL_UART_ERROR_ORE;
+ huart->ErrorCode = HAL_UART_ERROR_ORE;
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
- return HAL_ERROR;
+ return HAL_ERROR;
}
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
{
diff --git a/Src/stm32f3xx_hal_uart_ex.c b/Src/stm32f3xx_hal_uart_ex.c
index a0e45cd..c63133c 100644
--- a/Src/stm32f3xx_hal_uart_ex.c
+++ b/Src/stm32f3xx_hal_uart_ex.c
@@ -599,7 +599,7 @@
*/
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
- HAL_StatusTypeDef status;
+ HAL_StatusTypeDef status = HAL_OK;
/* Check that a Rx process is not already ongoing */
if (huart->RxState == HAL_UART_STATE_READY)
@@ -613,24 +613,20 @@
huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
huart->RxEventType = HAL_UART_RXEVENT_TC;
- status = UART_Start_Receive_IT(huart, pData, Size);
+ (void)UART_Start_Receive_IT(huart, pData, Size);
- /* Check Rx process has been successfully started */
- if (status == HAL_OK)
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
{
- if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
- {
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
- ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
- }
- else
- {
- /* In case of errors already pending when reception is started,
- Interrupts may have already been raised and lead to reception abortion.
- (Overrun error for instance).
- In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
- status = HAL_ERROR;
- }
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ }
+ else
+ {
+ /* In case of errors already pending when reception is started,
+ Interrupts may have already been raised and lead to reception abortion.
+ (Overrun error for instance).
+ In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
+ status = HAL_ERROR;
}
return status;
@@ -726,7 +722,7 @@
* @param huart UART handle.
* @retval Rx Event Type (return vale will be a value of @ref UART_RxEvent_Type_Values)
*/
-HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart)
+HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart)
{
/* Return Rx Event type value, as stored in UART handle */
return (huart->RxEventType);
diff --git a/Src/stm32f3xx_hal_usart.c b/Src/stm32f3xx_hal_usart.c
index f762db4..330afef 100644
--- a/Src/stm32f3xx_hal_usart.c
+++ b/Src/stm32f3xx_hal_usart.c
@@ -89,7 +89,7 @@
[..]
Use function HAL_USART_UnRegisterCallback() to reset a callback to the default
- weak (surcharged) function.
+ weak function.
HAL_USART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
@@ -105,10 +105,10 @@
[..]
By default, after the HAL_USART_Init() and when the state is HAL_USART_STATE_RESET
- all callbacks are set to the corresponding weak (surcharged) functions:
+ all callbacks are set to the corresponding weak functions:
examples HAL_USART_TxCpltCallback(), HAL_USART_RxHalfCpltCallback().
Exception done for MspInit and MspDeInit functions that are respectively
- reset to the legacy weak (surcharged) functions in the HAL_USART_Init()
+ reset to the legacy weak functions in the HAL_USART_Init()
and HAL_USART_DeInit() only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_USART_Init() and HAL_USART_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
@@ -125,7 +125,7 @@
[..]
When The compilation define USE_HAL_USART_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available
- and weak (surcharged) callbacks are used.
+ and weak callbacks are used.
@endverbatim
@@ -140,7 +140,7 @@
*/
/** @defgroup USART USART
- * @brief HAL USART Synchronous module driver
+ * @brief HAL USART Synchronous SPI module driver
* @{
*/
@@ -212,8 +212,8 @@
===============================================================================
[..]
This subsection provides a set of functions allowing to initialize the USART
- in asynchronous and in synchronous modes.
- (+) For the asynchronous mode only these parameters can be configured:
+ in synchronous SPI master mode.
+ (+) For the synchronous SPI mode only these parameters can be configured:
(++) Baud Rate
(++) Word Length
(++) Stop Bit
@@ -225,7 +225,7 @@
(++) Receiver/transmitter modes
[..]
- The HAL_USART_Init() function follows the USART synchronous configuration
+ The HAL_USART_Init() function follows the USART synchronous SPI configuration
procedure (details for the procedure are available in reference manual).
@endverbatim
@@ -314,7 +314,7 @@
return HAL_ERROR;
}
- /* In Synchronous mode, the following bits must be kept cleared:
+ /* In Synchronous SPI mode, the following bits must be kept cleared:
- LINEN bit in the USART_CR2 register
- HDSEL, SCEN and IREN bits in the USART_CR3 register.
*/
@@ -404,7 +404,7 @@
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User USART Callback
- * To be used instead of the weak predefined callback
+ * To be used to override the weak predefined callback
* @note The HAL_USART_RegisterCallback() may be called before HAL_USART_Init() in HAL_USART_STATE_RESET
* to register callbacks for HAL_USART_MSPINIT_CB_ID and HAL_USART_MSPDEINIT_CB_ID
* @param husart usart handle
@@ -637,10 +637,10 @@
===============================================================================
##### IO operation functions #####
===============================================================================
- [..] This subsection provides a set of functions allowing to manage the USART synchronous
+ [..] This subsection provides a set of functions allowing to manage the USART synchronous SPI
data transfers.
- [..] The USART supports master mode only: it cannot receive or send data related to an input
+ [..] The USART Synchronous SPI supports master mode only: it cannot receive or send data related to an input
clock (SCLK is always an output).
[..]
@@ -2730,7 +2730,7 @@
/* Clear and configure the USART Clock, CPOL, CPHA, LBCL and STOP bits:
* set CPOL bit according to husart->Init.CLKPolarity value
* set CPHA bit according to husart->Init.CLKPhase value
- * set LBCL bit according to husart->Init.CLKLastBit value (used in SPI master mode only)
+ * set LBCL bit according to husart->Init.CLKLastBit value (used in USART Synchronous SPI master mode only)
* set STOP[13:12] bits according to husart->Init.StopBits value */
tmpreg = (uint32_t)(USART_CLOCK_ENABLE);
tmpreg |= (uint32_t)husart->Init.CLKLastBit;
diff --git a/Src/stm32f3xx_hal_wwdg.c b/Src/stm32f3xx_hal_wwdg.c
index 288739f..6a20f79 100644
--- a/Src/stm32f3xx_hal_wwdg.c
+++ b/Src/stm32f3xx_hal_wwdg.c
@@ -122,7 +122,6 @@
(+) __HAL_WWDG_ENABLE_IT: Enable the WWDG early wakeup interrupt
@endverbatim
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -418,3 +417,4 @@
/**
* @}
*/
+
diff --git a/Src/stm32f3xx_ll_adc.c b/Src/stm32f3xx_ll_adc.c
index 6d714e3..e4a6e12 100644
--- a/Src/stm32f3xx_ll_adc.c
+++ b/Src/stm32f3xx_ll_adc.c
@@ -794,7 +794,8 @@
while (( LL_ADC_REG_IsStopConversionOngoing(ADCx)
| LL_ADC_INJ_IsStopConversionOngoing(ADCx)) == 1U)
{
- if(timeout_cpu_cycles-- == 0U)
+ timeout_cpu_cycles--;
+ if(timeout_cpu_cycles == 0U)
{
/* Time-out error */
status = ERROR;
@@ -813,7 +814,8 @@
timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
while (LL_ADC_IsDisableOngoing(ADCx) == 1U)
{
- if(timeout_cpu_cycles-- == 0U)
+ timeout_cpu_cycles--;
+ if(timeout_cpu_cycles == 0U)
{
/* Time-out error */
status = ERROR;
diff --git a/Src/stm32f3xx_ll_fmc.c b/Src/stm32f3xx_ll_fmc.c
index 092481a..93a7ddb 100644
--- a/Src/stm32f3xx_ll_fmc.c
+++ b/Src/stm32f3xx_ll_fmc.c
@@ -59,7 +59,8 @@
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
-#if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED)
+#if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) \
+ || defined(HAL_SRAM_MODULE_ENABLED)
/** @defgroup FMC_LL FMC Low Layer
* @brief FMC driver modules
@@ -339,13 +340,14 @@
assert_param(IS_FMC_NORSRAM_BANK(Bank));
/* Set FMC_NORSRAM device timing parameters */
- MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime |
- ((Timing->AddressHoldTime) << FMC_BTRx_ADDHLD_Pos) |
- ((Timing->DataSetupTime) << FMC_BTRx_DATAST_Pos) |
- ((Timing->BusTurnAroundDuration) << FMC_BTRx_BUSTURN_Pos) |
- (((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos) |
- (((Timing->DataLatency) - 2U) << FMC_BTRx_DATLAT_Pos) |
- (Timing->AccessMode)));
+ Device->BTCR[Bank + 1U] =
+ (Timing->AddressSetupTime << FMC_BTRx_ADDSET_Pos) |
+ (Timing->AddressHoldTime << FMC_BTRx_ADDHLD_Pos) |
+ (Timing->DataSetupTime << FMC_BTRx_DATAST_Pos) |
+ (Timing->BusTurnAroundDuration << FMC_BTRx_BUSTURN_Pos) |
+ ((Timing->CLKDivision - 1U) << FMC_BTRx_CLKDIV_Pos) |
+ ((Timing->DataLatency - 2U) << FMC_BTRx_DATLAT_Pos) |
+ Timing->AccessMode;
/* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
diff --git a/Src/stm32f3xx_ll_tim.c b/Src/stm32f3xx_ll_tim.c
index 7a844d6..653ed07 100644
--- a/Src/stm32f3xx_ll_tim.c
+++ b/Src/stm32f3xx_ll_tim.c
@@ -495,10 +495,12 @@
case LL_TIM_CHANNEL_CH5:
result = OC5Config(TIMx, TIM_OC_InitStruct);
break;
+#endif /* TIM_CCER_CC5E */
+#if defined(TIM_CCER_CC6E)
case LL_TIM_CHANNEL_CH6:
result = OC6Config(TIMx, TIM_OC_InitStruct);
break;
-#endif /* TIM_CCER_CC5E */
+#endif /* TIM_CCER_CC6E */
default:
break;
}
@@ -813,6 +815,9 @@
assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
+#if defined(TIM_BDTR_BKF)
+ assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
+#endif /* TIM_BDTR_BKF */
/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
the OSSI State, the dead time value and the Automatic Output Enable Bit */
@@ -825,9 +830,7 @@
MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
- MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
#if defined(TIM_BDTR_BKF)
- assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
#endif /* TIM_BDTR_BKF */
#if defined(TIM_BDTR_BK2E)
@@ -881,8 +884,6 @@
assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
/* Disable the Channel 1: Reset the CC1E Bit */
CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
@@ -910,8 +911,10 @@
if (IS_TIM_BREAK_INSTANCE(TIMx))
{
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
/* Set the complementary output Polarity */
MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
@@ -960,8 +963,6 @@
assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
/* Disable the Channel 2: Reset the CC2E Bit */
CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
@@ -989,8 +990,10 @@
if (IS_TIM_BREAK_INSTANCE(TIMx))
{
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
/* Set the complementary output Polarity */
MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
@@ -1042,8 +1045,6 @@
assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
/* Disable the Channel 3: Reset the CC3E Bit */
CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
@@ -1071,8 +1072,10 @@
if (IS_TIM_BREAK_INSTANCE(TIMx))
{
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
/* Set the complementary output Polarity */
MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
@@ -1124,8 +1127,6 @@
assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
/* Disable the Channel 4: Reset the CC4E Bit */
CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
@@ -1153,7 +1154,6 @@
if (IS_TIM_BREAK_INSTANCE(TIMx))
{
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
#if defined(STM32F373xC) || defined(STM32F378xx)
@@ -1240,7 +1240,9 @@
return SUCCESS;
}
+#endif /* TIM_CCER_CC5E */
+#if defined(TIM_CCER_CC6E)
/**
* @brief Configure the TIMx output channel 6.
* @param TIMx Timer Instance
@@ -1301,7 +1303,7 @@
return SUCCESS;
}
-#endif /* TIM_CCER_CC5E */
+#endif /* TIM_CCER_CC6E */
/**
* @brief Configure the TIMx input channel 1.
@@ -1427,7 +1429,7 @@
(TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
(TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
- /* Select the Polarity and set the CC2E Bit */
+ /* Select the Polarity and set the CC4E Bit */
MODIFY_REG(TIMx->CCER,
(TIM_CCER_CC4P | TIM_CCER_CC4NP),
((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
diff --git a/Src/stm32f3xx_ll_usb.c b/Src/stm32f3xx_ll_usb.c
index 930aece..b31bd60 100644
--- a/Src/stm32f3xx_ll_usb.c
+++ b/Src/stm32f3xx_ll_usb.c
@@ -172,6 +172,47 @@
return HAL_OK;
}
+/**
+ * @brief USB_FlushTxFifo : Flush a Tx FIFO
+ * @param USBx : Selected device
+ * @param num : FIFO number
+ * This parameter can be a value from 1 to 15
+ 15 means Flush all Tx FIFOs
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef const *USBx, uint32_t num)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+ UNUSED(num);
+
+ /* NOTE : - This function is not required by USB Device FS peripheral, it is used
+ only by USB OTG FS peripheral.
+ - This function is added to ensure compatibility across platforms.
+ */
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_FlushRxFifo : Flush Rx FIFO
+ * @param USBx : Selected device
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef const *USBx)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+
+ /* NOTE : - This function is not required by USB Device FS peripheral, it is used
+ only by USB OTG FS peripheral.
+ - This function is added to ensure compatibility across platforms.
+ */
+
+ return HAL_OK;
+}
+
+
#if defined (HAL_PCD_MODULE_ENABLED)
/**
* @brief Activate and configure an endpoint
@@ -761,7 +802,7 @@
* @param USBx Selected device
* @retval USB Global Interrupt status
*/
-uint32_t USB_ReadInterrupts(USB_TypeDef *USBx)
+uint32_t USB_ReadInterrupts(USB_TypeDef const *USBx)
{
uint32_t tmpreg;
@@ -801,7 +842,7 @@
* @param wNBytes no. of bytes to be copied.
* @retval None
*/
-void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
+void USB_WritePMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
{
uint32_t n = ((uint32_t)wNBytes + 1U) >> 1;
uint32_t BaseAddr = (uint32_t)USBx;
@@ -836,7 +877,7 @@
* @param wNBytes no. of bytes to be copied.
* @retval None
*/
-void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
+void USB_ReadPMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
{
uint32_t n = (uint32_t)wNBytes >> 1;
uint32_t BaseAddr = (uint32_t)USBx;
diff --git a/Src/stm32f3xx_ll_utils.c b/Src/stm32f3xx_ll_utils.c
index 11ee50c..964b518 100644
--- a/Src/stm32f3xx_ll_utils.c
+++ b/Src/stm32f3xx_ll_utils.c
@@ -266,24 +266,21 @@
}
}
- if (status != ERROR)
- {
- LL_FLASH_SetLatency(latency);
+ LL_FLASH_SetLatency(latency);
- /* Check that the new number of wait states is taken into account to access the Flash
- memory by reading the FLASH_ACR register */
- timeout = 2;
- do
- {
+ /* Check that the new number of wait states is taken into account to access the Flash
+ memory by reading the FLASH_ACR register */
+ timeout = 2;
+ do
+ {
/* Wait for Flash latency to be updated */
getlatency = LL_FLASH_GetLatency();
timeout--;
- } while ((getlatency != latency) && (timeout > 0));
+ } while ((getlatency != latency) && (timeout > 0));
- if(getlatency != latency)
- {
- status = ERROR;
- }
+ if(getlatency != latency)
+ {
+ status = ERROR;
}
}
