| /** |
| ****************************************************************************** |
| * @file stm32f4xx_hal_rcc_ex.h |
| * @author MCD Application Team |
| * @brief Header file of RCC HAL Extension module. |
| ****************************************************************************** |
| * @attention |
| * |
| * Copyright (c) 2017 STMicroelectronics. |
| * All rights reserved. |
| * |
| * This software is licensed under terms that can be found in the LICENSE file in |
| * the root directory of this software component. |
| * If no LICENSE file comes with this software, it is provided AS-IS. |
| ****************************************************************************** |
| */ |
| |
| /* Define to prevent recursive inclusion -------------------------------------*/ |
| #ifndef __STM32F4xx_HAL_RCC_EX_H |
| #define __STM32F4xx_HAL_RCC_EX_H |
| |
| #ifdef __cplusplus |
| extern "C" { |
| #endif |
| |
| /* Includes ------------------------------------------------------------------*/ |
| #include "stm32f4xx_hal_def.h" |
| |
| /** @addtogroup STM32F4xx_HAL_Driver |
| * @{ |
| */ |
| |
| /** @addtogroup RCCEx |
| * @{ |
| */ |
| |
| /* Exported types ------------------------------------------------------------*/ |
| /** @defgroup RCCEx_Exported_Types RCCEx Exported Types |
| * @{ |
| */ |
| |
| /** |
| * @brief RCC PLL configuration structure definition |
| */ |
| typedef struct |
| { |
| uint32_t PLLState; /*!< The new state of the PLL. |
| This parameter can be a value of @ref RCC_PLL_Config */ |
| |
| uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. |
| This parameter must be a value of @ref RCC_PLL_Clock_Source */ |
| |
| uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. |
| This parameter must be a number between Min_Data = 0 and Max_Data = 63 */ |
| |
| uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. |
| This parameter must be a number between Min_Data = 50 and Max_Data = 432 |
| except for STM32F411xE devices where the Min_Data = 192 */ |
| |
| uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK). |
| This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ |
| |
| uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks. |
| This parameter must be a number between Min_Data = 2 and Max_Data = 15 */ |
| #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F469xx) ||\ |
| defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ |
| defined(STM32F413xx) || defined(STM32F423xx) |
| uint32_t PLLR; /*!< PLLR: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks. |
| This parameter is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx |
| and STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices. |
| This parameter must be a number between Min_Data = 2 and Max_Data = 7 */ |
| #endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ |
| }RCC_PLLInitTypeDef; |
| |
| #if defined(STM32F446xx) |
| /** |
| * @brief PLLI2S Clock structure definition |
| */ |
| typedef struct |
| { |
| uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock. |
| This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ |
| |
| uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. |
| This parameter must be a number between Min_Data = 50 and Max_Data = 432 */ |
| |
| uint32_t PLLI2SP; /*!< Specifies division factor for SPDIFRX Clock. |
| This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider */ |
| |
| uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock. |
| This parameter must be a number between Min_Data = 2 and Max_Data = 15. |
| This parameter will be used only when PLLI2S is selected as Clock Source SAI */ |
| |
| uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. |
| This parameter must be a number between Min_Data = 2 and Max_Data = 7. |
| This parameter will be used only when PLLI2S is selected as Clock Source I2S */ |
| }RCC_PLLI2SInitTypeDef; |
| |
| /** |
| * @brief PLLSAI Clock structure definition |
| */ |
| typedef struct |
| { |
| uint32_t PLLSAIM; /*!< Specifies division factor for PLL VCO input clock. |
| This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ |
| |
| uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. |
| This parameter must be a number between Min_Data = 50 and Max_Data = 432 */ |
| |
| uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS, SDIO and RNG clocks. |
| This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */ |
| |
| uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI clock. |
| This parameter must be a number between Min_Data = 2 and Max_Data = 15. |
| This parameter will be used only when PLLSAI is selected as Clock Source SAI */ |
| }RCC_PLLSAIInitTypeDef; |
| |
| /** |
| * @brief RCC extended clocks structure definition |
| */ |
| typedef struct |
| { |
| uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
| This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
| |
| RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. |
| This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ |
| |
| RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters. |
| This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */ |
| |
| uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. |
| This parameter must be a number between Min_Data = 1 and Max_Data = 32 |
| This parameter will be used only when PLLI2S is selected as Clock Source SAI */ |
| |
| uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. |
| This parameter must be a number between Min_Data = 1 and Max_Data = 32 |
| This parameter will be used only when PLLSAI is selected as Clock Source SAI */ |
| |
| uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Source Selection. |
| This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ |
| |
| uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Source Selection. |
| This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */ |
| |
| uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection. |
| This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */ |
| |
| uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection. |
| This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */ |
| |
| uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection. |
| This parameter can be a value of @ref RCC_RTC_Clock_Source */ |
| |
| uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection. |
| This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */ |
| |
| uint32_t CecClockSelection; /*!< Specifies CEC Clock Source Selection. |
| This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ |
| |
| uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection. |
| This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */ |
| |
| uint32_t SpdifClockSelection; /*!< Specifies SPDIFRX Clock Source Selection. |
| This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */ |
| |
| uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks. |
| This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */ |
| |
| uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection. |
| This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ |
| }RCC_PeriphCLKInitTypeDef; |
| #endif /* STM32F446xx */ |
| |
| #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) |
| /** |
| * @brief RCC extended clocks structure definition |
| */ |
| typedef struct |
| { |
| uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
| This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
| |
| uint32_t I2SClockSelection; /*!< Specifies RTC Clock Source Selection. |
| This parameter can be a value of @ref RCCEx_I2S_APB_Clock_Source */ |
| |
| uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection. |
| This parameter can be a value of @ref RCC_RTC_Clock_Source */ |
| |
| uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 Clock Source Selection. |
| This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ |
| |
| uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection. |
| This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */ |
| |
| uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection. |
| This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ |
| }RCC_PeriphCLKInitTypeDef; |
| #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ |
| |
| #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) |
| /** |
| * @brief PLLI2S Clock structure definition |
| */ |
| typedef struct |
| { |
| uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock. |
| This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ |
| |
| uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. |
| This parameter must be a number between Min_Data = 50 and Max_Data = 432 */ |
| |
| uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock. |
| This parameter must be a number between Min_Data = 2 and Max_Data = 15. |
| This parameter will be used only when PLLI2S is selected as Clock Source SAI */ |
| |
| uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. |
| This parameter must be a number between Min_Data = 2 and Max_Data = 7. |
| This parameter will be used only when PLLI2S is selected as Clock Source I2S */ |
| }RCC_PLLI2SInitTypeDef; |
| |
| /** |
| * @brief RCC extended clocks structure definition |
| */ |
| typedef struct |
| { |
| uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
| This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
| |
| RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. |
| This parameter will be used only when PLLI2S is selected as Clock Source I2S */ |
| |
| #if defined(STM32F413xx) || defined(STM32F423xx) |
| uint32_t PLLDivR; /*!< Specifies the PLL division factor for SAI1 clock. |
| This parameter must be a number between Min_Data = 1 and Max_Data = 32 |
| This parameter will be used only when PLL is selected as Clock Source SAI */ |
| |
| uint32_t PLLI2SDivR; /*!< Specifies the PLLI2S division factor for SAI1 clock. |
| This parameter must be a number between Min_Data = 1 and Max_Data = 32 |
| This parameter will be used only when PLLI2S is selected as Clock Source SAI */ |
| #endif /* STM32F413xx || STM32F423xx */ |
| |
| uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection. |
| This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */ |
| |
| uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection. |
| This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */ |
| |
| uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection. |
| This parameter can be a value of @ref RCC_RTC_Clock_Source */ |
| |
| uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection. |
| This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */ |
| |
| uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection. |
| This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */ |
| |
| uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks. |
| This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */ |
| |
| uint32_t Dfsdm1ClockSelection; /*!< Specifies DFSDM1 Clock Selection. |
| This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */ |
| |
| uint32_t Dfsdm1AudioClockSelection;/*!< Specifies DFSDM1 Audio Clock Selection. |
| This parameter can be a value of @ref RCCEx_DFSDM1_Audio_Clock_Source */ |
| |
| #if defined(STM32F413xx) || defined(STM32F423xx) |
| uint32_t Dfsdm2ClockSelection; /*!< Specifies DFSDM2 Clock Selection. |
| This parameter can be a value of @ref RCCEx_DFSDM2_Kernel_Clock_Source */ |
| |
| uint32_t Dfsdm2AudioClockSelection;/*!< Specifies DFSDM2 Audio Clock Selection. |
| This parameter can be a value of @ref RCCEx_DFSDM2_Audio_Clock_Source */ |
| |
| uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 Clock Source Selection. |
| This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ |
| |
| uint32_t SaiAClockSelection; /*!< Specifies SAI1_A Clock Prescalers Selection |
| This parameter can be a value of @ref RCCEx_SAI1_BlockA_Clock_Source */ |
| |
| uint32_t SaiBClockSelection; /*!< Specifies SAI1_B Clock Prescalers Selection |
| This parameter can be a value of @ref RCCEx_SAI1_BlockB_Clock_Source */ |
| #endif /* STM32F413xx || STM32F423xx */ |
| |
| uint32_t PLLI2SSelection; /*!< Specifies PLL I2S Clock Source Selection. |
| This parameter can be a value of @ref RCCEx_PLL_I2S_Clock_Source */ |
| |
| uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection. |
| This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ |
| }RCC_PeriphCLKInitTypeDef; |
| #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ |
| |
| #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) |
| |
| /** |
| * @brief PLLI2S Clock structure definition |
| */ |
| typedef struct |
| { |
| uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. |
| This parameter must be a number between Min_Data = 50 and Max_Data = 432. |
| This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ |
| |
| uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. |
| This parameter must be a number between Min_Data = 2 and Max_Data = 7. |
| This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ |
| |
| uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock. |
| This parameter must be a number between Min_Data = 2 and Max_Data = 15. |
| This parameter will be used only when PLLI2S is selected as Clock Source SAI */ |
| }RCC_PLLI2SInitTypeDef; |
| |
| /** |
| * @brief PLLSAI Clock structure definition |
| */ |
| typedef struct |
| { |
| uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. |
| This parameter must be a number between Min_Data = 50 and Max_Data = 432. |
| This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ |
| #if defined(STM32F469xx) || defined(STM32F479xx) |
| uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS and SDIO clocks. |
| This parameter is only available in STM32F469xx/STM32F479xx devices. |
| This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */ |
| #endif /* STM32F469xx || STM32F479xx */ |
| |
| uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock. |
| This parameter must be a number between Min_Data = 2 and Max_Data = 15. |
| This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ |
| |
| uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock |
| This parameter must be a number between Min_Data = 2 and Max_Data = 7. |
| This parameter will be used only when PLLSAI is selected as Clock Source LTDC */ |
| |
| }RCC_PLLSAIInitTypeDef; |
| |
| /** |
| * @brief RCC extended clocks structure definition |
| */ |
| typedef struct |
| { |
| uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
| This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
| |
| RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. |
| This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ |
| |
| RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters. |
| This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */ |
| |
| uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. |
| This parameter must be a number between Min_Data = 1 and Max_Data = 32 |
| This parameter will be used only when PLLI2S is selected as Clock Source SAI */ |
| |
| uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. |
| This parameter must be a number between Min_Data = 1 and Max_Data = 32 |
| This parameter will be used only when PLLSAI is selected as Clock Source SAI */ |
| |
| uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock. |
| This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */ |
| |
| uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection. |
| This parameter can be a value of @ref RCC_RTC_Clock_Source */ |
| |
| uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection. |
| This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ |
| #if defined(STM32F469xx) || defined(STM32F479xx) |
| uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks. |
| This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */ |
| |
| uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection. |
| This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */ |
| #endif /* STM32F469xx || STM32F479xx */ |
| }RCC_PeriphCLKInitTypeDef; |
| |
| #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ |
| |
| #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ |
| defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) |
| /** |
| * @brief PLLI2S Clock structure definition |
| */ |
| typedef struct |
| { |
| #if defined(STM32F411xE) |
| uint32_t PLLI2SM; /*!< PLLM: Division factor for PLLI2S VCO input clock. |
| This parameter must be a number between Min_Data = 2 and Max_Data = 62 */ |
| #endif /* STM32F411xE */ |
| |
| uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. |
| This parameter must be a number between Min_Data = 50 and Max_Data = 432 |
| Except for STM32F411xE devices where the Min_Data = 192. |
| This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ |
| |
| uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. |
| This parameter must be a number between Min_Data = 2 and Max_Data = 7. |
| This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ |
| |
| }RCC_PLLI2SInitTypeDef; |
| |
| /** |
| * @brief RCC extended clocks structure definition |
| */ |
| typedef struct |
| { |
| uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
| This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
| |
| RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. |
| This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ |
| |
| uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection. |
| This parameter can be a value of @ref RCC_RTC_Clock_Source */ |
| #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) |
| uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection. |
| This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ |
| #endif /* STM32F401xC || STM32F401xE || STM32F411xE */ |
| }RCC_PeriphCLKInitTypeDef; |
| #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */ |
| /** |
| * @} |
| */ |
| |
| /* Exported constants --------------------------------------------------------*/ |
| /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants |
| * @{ |
| */ |
| |
| /** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection |
| * @{ |
| */ |
| /* Peripheral Clock source for STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx */ |
| #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ |
| defined(STM32F413xx) || defined(STM32F423xx) |
| #define RCC_PERIPHCLK_I2S_APB1 0x00000001U |
| #define RCC_PERIPHCLK_I2S_APB2 0x00000002U |
| #define RCC_PERIPHCLK_TIM 0x00000004U |
| #define RCC_PERIPHCLK_RTC 0x00000008U |
| #define RCC_PERIPHCLK_FMPI2C1 0x00000010U |
| #define RCC_PERIPHCLK_CLK48 0x00000020U |
| #define RCC_PERIPHCLK_SDIO 0x00000040U |
| #define RCC_PERIPHCLK_PLLI2S 0x00000080U |
| #define RCC_PERIPHCLK_DFSDM1 0x00000100U |
| #define RCC_PERIPHCLK_DFSDM1_AUDIO 0x00000200U |
| #endif /* STM32F412Zx || STM32F412Vx) || STM32F412Rx || STM32F412Cx */ |
| #if defined(STM32F413xx) || defined(STM32F423xx) |
| #define RCC_PERIPHCLK_DFSDM2 0x00000400U |
| #define RCC_PERIPHCLK_DFSDM2_AUDIO 0x00000800U |
| #define RCC_PERIPHCLK_LPTIM1 0x00001000U |
| #define RCC_PERIPHCLK_SAIA 0x00002000U |
| #define RCC_PERIPHCLK_SAIB 0x00004000U |
| #endif /* STM32F413xx || STM32F423xx */ |
| /*----------------------------------------------------------------------------*/ |
| |
| /*------------------- Peripheral Clock source for STM32F410xx ----------------*/ |
| #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) |
| #define RCC_PERIPHCLK_I2S 0x00000001U |
| #define RCC_PERIPHCLK_TIM 0x00000002U |
| #define RCC_PERIPHCLK_RTC 0x00000004U |
| #define RCC_PERIPHCLK_FMPI2C1 0x00000008U |
| #define RCC_PERIPHCLK_LPTIM1 0x00000010U |
| #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ |
| /*----------------------------------------------------------------------------*/ |
| |
| /*------------------- Peripheral Clock source for STM32F446xx ----------------*/ |
| #if defined(STM32F446xx) |
| #define RCC_PERIPHCLK_I2S_APB1 0x00000001U |
| #define RCC_PERIPHCLK_I2S_APB2 0x00000002U |
| #define RCC_PERIPHCLK_SAI1 0x00000004U |
| #define RCC_PERIPHCLK_SAI2 0x00000008U |
| #define RCC_PERIPHCLK_TIM 0x00000010U |
| #define RCC_PERIPHCLK_RTC 0x00000020U |
| #define RCC_PERIPHCLK_CEC 0x00000040U |
| #define RCC_PERIPHCLK_FMPI2C1 0x00000080U |
| #define RCC_PERIPHCLK_CLK48 0x00000100U |
| #define RCC_PERIPHCLK_SDIO 0x00000200U |
| #define RCC_PERIPHCLK_SPDIFRX 0x00000400U |
| #define RCC_PERIPHCLK_PLLI2S 0x00000800U |
| #endif /* STM32F446xx */ |
| /*-----------------------------------------------------------------------------*/ |
| |
| /*----------- Peripheral Clock source for STM32F469xx/STM32F479xx -------------*/ |
| #if defined(STM32F469xx) || defined(STM32F479xx) |
| #define RCC_PERIPHCLK_I2S 0x00000001U |
| #define RCC_PERIPHCLK_SAI_PLLI2S 0x00000002U |
| #define RCC_PERIPHCLK_SAI_PLLSAI 0x00000004U |
| #define RCC_PERIPHCLK_LTDC 0x00000008U |
| #define RCC_PERIPHCLK_TIM 0x00000010U |
| #define RCC_PERIPHCLK_RTC 0x00000020U |
| #define RCC_PERIPHCLK_PLLI2S 0x00000040U |
| #define RCC_PERIPHCLK_CLK48 0x00000080U |
| #define RCC_PERIPHCLK_SDIO 0x00000100U |
| #endif /* STM32F469xx || STM32F479xx */ |
| /*----------------------------------------------------------------------------*/ |
| |
| /*-------- Peripheral Clock source for STM32F42xxx/STM32F43xxx ---------------*/ |
| #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) |
| #define RCC_PERIPHCLK_I2S 0x00000001U |
| #define RCC_PERIPHCLK_SAI_PLLI2S 0x00000002U |
| #define RCC_PERIPHCLK_SAI_PLLSAI 0x00000004U |
| #define RCC_PERIPHCLK_LTDC 0x00000008U |
| #define RCC_PERIPHCLK_TIM 0x00000010U |
| #define RCC_PERIPHCLK_RTC 0x00000020U |
| #define RCC_PERIPHCLK_PLLI2S 0x00000040U |
| #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ |
| /*----------------------------------------------------------------------------*/ |
| |
| /*-------- Peripheral Clock source for STM32F40xxx/STM32F41xxx ---------------*/ |
| #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\ |
| defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) |
| #define RCC_PERIPHCLK_I2S 0x00000001U |
| #define RCC_PERIPHCLK_RTC 0x00000002U |
| #define RCC_PERIPHCLK_PLLI2S 0x00000004U |
| #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */ |
| #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) |
| #define RCC_PERIPHCLK_TIM 0x00000008U |
| #endif /* STM32F401xC || STM32F401xE || STM32F411xE */ |
| /*----------------------------------------------------------------------------*/ |
| /** |
| * @} |
| */ |
| #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ |
| defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ |
| defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) || \ |
| defined(STM32F479xx) |
| /** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source |
| * @{ |
| */ |
| #define RCC_I2SCLKSOURCE_PLLI2S 0x00000000U |
| #define RCC_I2SCLKSOURCE_EXT 0x00000001U |
| /** |
| * @} |
| */ |
| #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || |
| STM32F401xC || STM32F401xE || STM32F411xE || STM32F469xx || STM32F479xx */ |
| |
| /** @defgroup RCCEx_PLLSAI_DIVR RCC PLLSAI DIVR |
| * @{ |
| */ |
| #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\ |
| defined(STM32F469xx) || defined(STM32F479xx) |
| #define RCC_PLLSAIDIVR_2 0x00000000U |
| #define RCC_PLLSAIDIVR_4 0x00010000U |
| #define RCC_PLLSAIDIVR_8 0x00020000U |
| #define RCC_PLLSAIDIVR_16 0x00030000U |
| #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCCEx_PLLI2SP_Clock_Divider RCC PLLI2SP Clock Divider |
| * @{ |
| */ |
| #if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ |
| defined(STM32F412Rx) || defined(STM32F412Cx) |
| #define RCC_PLLI2SP_DIV2 0x00000002U |
| #define RCC_PLLI2SP_DIV4 0x00000004U |
| #define RCC_PLLI2SP_DIV6 0x00000006U |
| #define RCC_PLLI2SP_DIV8 0x00000008U |
| #endif /* STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCCEx_PLLSAIP_Clock_Divider RCC PLLSAIP Clock Divider |
| * @{ |
| */ |
| #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) |
| #define RCC_PLLSAIP_DIV2 0x00000002U |
| #define RCC_PLLSAIP_DIV4 0x00000004U |
| #define RCC_PLLSAIP_DIV6 0x00000006U |
| #define RCC_PLLSAIP_DIV8 0x00000008U |
| #endif /* STM32F446xx || STM32F469xx || STM32F479xx */ |
| /** |
| * @} |
| */ |
| |
| #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) |
| /** @defgroup RCCEx_SAI_BlockA_Clock_Source RCC SAI BlockA Clock Source |
| * @{ |
| */ |
| #define RCC_SAIACLKSOURCE_PLLSAI 0x00000000U |
| #define RCC_SAIACLKSOURCE_PLLI2S 0x00100000U |
| #define RCC_SAIACLKSOURCE_EXT 0x00200000U |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCCEx_SAI_BlockB_Clock_Source RCC SAI BlockB Clock Source |
| * @{ |
| */ |
| #define RCC_SAIBCLKSOURCE_PLLSAI 0x00000000U |
| #define RCC_SAIBCLKSOURCE_PLLI2S 0x00400000U |
| #define RCC_SAIBCLKSOURCE_EXT 0x00800000U |
| /** |
| * @} |
| */ |
| #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ |
| |
| #if defined(STM32F469xx) || defined(STM32F479xx) |
| /** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source |
| * @{ |
| */ |
| #define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U |
| #define RCC_CLK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR_CK48MSEL) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source |
| * @{ |
| */ |
| #define RCC_SDIOCLKSOURCE_CLK48 0x00000000U |
| #define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_SDIOSEL) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCCEx_DSI_Clock_Source RCC DSI Clock Source |
| * @{ |
| */ |
| #define RCC_DSICLKSOURCE_DSIPHY 0x00000000U |
| #define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_DSISEL) |
| /** |
| * @} |
| */ |
| #endif /* STM32F469xx || STM32F479xx */ |
| |
| #if defined(STM32F446xx) |
| /** @defgroup RCCEx_SAI1_Clock_Source RCC SAI1 Clock Source |
| * @{ |
| */ |
| #define RCC_SAI1CLKSOURCE_PLLSAI 0x00000000U |
| #define RCC_SAI1CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI1SRC_0) |
| #define RCC_SAI1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1SRC_1) |
| #define RCC_SAI1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1SRC) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCCEx_SAI2_Clock_Source RCC SAI2 Clock Source |
| * @{ |
| */ |
| #define RCC_SAI2CLKSOURCE_PLLSAI 0x00000000U |
| #define RCC_SAI2CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI2SRC_0) |
| #define RCC_SAI2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI2SRC_1) |
| #define RCC_SAI2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI2SRC) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source |
| * @{ |
| */ |
| #define RCC_I2SAPB1CLKSOURCE_PLLI2S 0x00000000U |
| #define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0) |
| #define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1) |
| #define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source |
| * @{ |
| */ |
| #define RCC_I2SAPB2CLKSOURCE_PLLI2S 0x00000000U |
| #define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0) |
| #define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1) |
| #define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source |
| * @{ |
| */ |
| #define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U |
| #define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0) |
| #define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCCEx_CEC_Clock_Source RCC CEC Clock Source |
| * @{ |
| */ |
| #define RCC_CECCLKSOURCE_HSI 0x00000000U |
| #define RCC_CECCLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_CECSEL) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source |
| * @{ |
| */ |
| #define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U |
| #define RCC_CLK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR2_CK48MSEL) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source |
| * @{ |
| */ |
| #define RCC_SDIOCLKSOURCE_CLK48 0x00000000U |
| #define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCCEx_SPDIFRX_Clock_Source RCC SPDIFRX Clock Source |
| * @{ |
| */ |
| #define RCC_SPDIFRXCLKSOURCE_PLLR 0x00000000U |
| #define RCC_SPDIFRXCLKSOURCE_PLLI2SP ((uint32_t)RCC_DCKCFGR2_SPDIFRXSEL) |
| /** |
| * @} |
| */ |
| |
| #endif /* STM32F446xx */ |
| |
| #if defined(STM32F413xx) || defined(STM32F423xx) |
| /** @defgroup RCCEx_SAI1_BlockA_Clock_Source RCC SAI BlockA Clock Source |
| * @{ |
| */ |
| #define RCC_SAIACLKSOURCE_PLLI2SR 0x00000000U |
| #define RCC_SAIACLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0) |
| #define RCC_SAIACLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1ASRC_1) |
| #define RCC_SAIACLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0 | RCC_DCKCFGR_SAI1ASRC_1) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCCEx_SAI1_BlockB_Clock_Source RCC SAI BlockB Clock Source |
| * @{ |
| */ |
| #define RCC_SAIBCLKSOURCE_PLLI2SR 0x00000000U |
| #define RCC_SAIBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0) |
| #define RCC_SAIBCLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1BSRC_1) |
| #define RCC_SAIBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0 | RCC_DCKCFGR_SAI1BSRC_1) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source |
| * @{ |
| */ |
| #define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U |
| #define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0) |
| #define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1) |
| #define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1) |
| /** |
| * @} |
| */ |
| |
| |
| /** @defgroup RCCEx_DFSDM2_Audio_Clock_Source RCC DFSDM2 Audio Clock Source |
| * @{ |
| */ |
| #define RCC_DFSDM2AUDIOCLKSOURCE_I2S1 0x00000000U |
| #define RCC_DFSDM2AUDIOCLKSOURCE_I2S2 ((uint32_t)RCC_DCKCFGR_CKDFSDM2ASEL) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCCEx_DFSDM2_Kernel_Clock_Source RCC DFSDM2 Kernel Clock Source |
| * @{ |
| */ |
| #define RCC_DFSDM2CLKSOURCE_PCLK2 0x00000000U |
| #define RCC_DFSDM2CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL) |
| /** |
| * @} |
| */ |
| |
| #endif /* STM32F413xx || STM32F423xx */ |
| |
| #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) |
| /** @defgroup RCCEx_PLL_I2S_Clock_Source PLL I2S Clock Source |
| * @{ |
| */ |
| #define RCC_PLLI2SCLKSOURCE_PLLSRC 0x00000000U |
| #define RCC_PLLI2SCLKSOURCE_EXT ((uint32_t)RCC_PLLI2SCFGR_PLLI2SSRC) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCCEx_DFSDM1_Audio_Clock_Source RCC DFSDM1 Audio Clock Source |
| * @{ |
| */ |
| #define RCC_DFSDM1AUDIOCLKSOURCE_I2S1 0x00000000U |
| #define RCC_DFSDM1AUDIOCLKSOURCE_I2S2 ((uint32_t)RCC_DCKCFGR_CKDFSDM1ASEL) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source RCC DFSDM1 Kernel Clock Source |
| * @{ |
| */ |
| #define RCC_DFSDM1CLKSOURCE_PCLK2 0x00000000U |
| #define RCC_DFSDM1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source |
| * @{ |
| */ |
| #define RCC_I2SAPB1CLKSOURCE_PLLI2S 0x00000000U |
| #define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0) |
| #define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1) |
| #define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source |
| * @{ |
| */ |
| #define RCC_I2SAPB2CLKSOURCE_PLLI2S 0x00000000U |
| #define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0) |
| #define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1) |
| #define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source |
| * @{ |
| */ |
| #define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U |
| #define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0) |
| #define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source |
| * @{ |
| */ |
| #define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U |
| #define RCC_CLK48CLKSOURCE_PLLI2SQ ((uint32_t)RCC_DCKCFGR2_CK48MSEL) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source |
| * @{ |
| */ |
| #define RCC_SDIOCLKSOURCE_CLK48 0x00000000U |
| #define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL) |
| /** |
| * @} |
| */ |
| #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ |
| |
| #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) |
| |
| /** @defgroup RCCEx_I2S_APB_Clock_Source RCC I2S APB Clock Source |
| * @{ |
| */ |
| #define RCC_I2SAPBCLKSOURCE_PLLR 0x00000000U |
| #define RCC_I2SAPBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2SSRC_0) |
| #define RCC_I2SAPBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2SSRC_1) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source |
| * @{ |
| */ |
| #define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U |
| #define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0) |
| #define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source |
| * @{ |
| */ |
| #define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U |
| #define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0) |
| #define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1) |
| #define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1) |
| /** |
| * @} |
| */ |
| #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ |
| |
| #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ |
| defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ |
| defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ |
| defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ |
| defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) |
| /** @defgroup RCCEx_TIM_PRescaler_Selection RCC TIM PRescaler Selection |
| * @{ |
| */ |
| #define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00) |
| #define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01) |
| /** |
| * @} |
| */ |
| #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\ |
| STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ |
| STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ |
| |
| #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\ |
| defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ |
| defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\ |
| defined(STM32F423xx) |
| /** @defgroup RCCEx_LSE_Dual_Mode_Selection RCC LSE Dual Mode Selection |
| * @{ |
| */ |
| #define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00) |
| #define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01) |
| /** |
| * @} |
| */ |
| #endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||\ |
| STM32F412Rx || STM32F412Cx */ |
| |
| #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ |
| defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ |
| defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ |
| defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ |
| defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) |
| /** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source |
| * @{ |
| */ |
| #define RCC_MCO2SOURCE_SYSCLK 0x00000000U |
| #define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0 |
| #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1 |
| #define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2 |
| /** |
| * @} |
| */ |
| #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || |
| STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || |
| STM32F412Rx || STM32F413xx | STM32F423xx */ |
| |
| #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) |
| /** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source |
| * @{ |
| */ |
| #define RCC_MCO2SOURCE_SYSCLK 0x00000000U |
| #define RCC_MCO2SOURCE_I2SCLK RCC_CFGR_MCO2_0 |
| #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1 |
| #define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2 |
| /** |
| * @} |
| */ |
| #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ |
| |
| /** |
| * @} |
| */ |
| |
| /* Exported macro ------------------------------------------------------------*/ |
| /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros |
| * @{ |
| */ |
| /*------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx --------*/ |
| #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) |
| /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable |
| * @brief Enables or disables the AHB1 peripheral clock. |
| * @note After reset, the peripheral clock (used for registers read/write access) |
| * is disabled and the application software has to enable this clock before |
| * using it. |
| * @{ |
| */ |
| #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_CRC_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_GPIOK_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) |
| #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) |
| #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) |
| #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) |
| #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN)) |
| #define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN)) |
| #define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN)) |
| #define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN)) |
| #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN)) |
| #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN)) |
| #define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN)) |
| #define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN)) |
| #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN)) |
| #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN)) |
| #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) |
| #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) |
| #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) |
| |
| /** |
| * @brief Enable ETHERNET clock. |
| */ |
| #define __HAL_RCC_ETH_CLK_ENABLE() do { \ |
| __HAL_RCC_ETHMAC_CLK_ENABLE(); \ |
| __HAL_RCC_ETHMACTX_CLK_ENABLE(); \ |
| __HAL_RCC_ETHMACRX_CLK_ENABLE(); \ |
| } while(0U) |
| /** |
| * @brief Disable ETHERNET clock. |
| */ |
| #define __HAL_RCC_ETH_CLK_DISABLE() do { \ |
| __HAL_RCC_ETHMACTX_CLK_DISABLE(); \ |
| __HAL_RCC_ETHMACRX_CLK_DISABLE(); \ |
| __HAL_RCC_ETHMAC_CLK_DISABLE(); \ |
| } while(0U) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status |
| * @brief Get the enable or disable status of the AHB1 peripheral clock. |
| * @note After reset, the peripheral clock (used for registers read/write access) |
| * is disabled and the application software has to enable this clock before |
| * using it. |
| * @{ |
| */ |
| #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) |
| #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) |
| #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) |
| #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) |
| #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET) |
| #define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET) |
| #define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET) |
| #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET) |
| #define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET) |
| #define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET) |
| #define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET) |
| #define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET) |
| #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET) |
| #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET) |
| #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET) |
| #define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET) |
| #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) |
| #define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \ |
| __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \ |
| __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()) |
| |
| #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) |
| #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) |
| #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) |
| #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) |
| #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET) |
| #define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET) |
| #define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET) |
| #define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET) |
| #define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET) |
| #define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET) |
| #define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET) |
| #define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET) |
| #define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET) |
| #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET) |
| #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET) |
| #define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) |
| #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) |
| #define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \ |
| __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \ |
| __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable |
| * @brief Enable or disable the AHB2 peripheral clock. |
| * @note After reset, the peripheral clock (used for registers read/write access) |
| * is disabled and the application software has to enable this clock before |
| * using it. |
| * @{ |
| */ |
| #define __HAL_RCC_DCMI_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) |
| |
| #if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) |
| #define __HAL_RCC_CRYP_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_HASH_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| |
| #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN)) |
| #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN)) |
| #endif /* STM32F437xx || STM32F439xx || STM32F479xx */ |
| |
| #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ |
| __HAL_RCC_SYSCFG_CLK_ENABLE();\ |
| }while(0U) |
| |
| #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) |
| |
| #define __HAL_RCC_RNG_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status |
| * @brief Get the enable or disable status of the AHB1 peripheral clock. |
| * @note After reset, the peripheral clock (used for registers read/write access) |
| * is disabled and the application software has to enable this clock before |
| * using it. |
| * @{ |
| */ |
| #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET) |
| #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) |
| |
| #if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) |
| #define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET) |
| #define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET) |
| |
| #define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET) |
| #define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET) |
| #endif /* STM32F437xx || STM32F439xx || STM32F479xx */ |
| |
| #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) |
| #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) |
| |
| #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) |
| #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable |
| * @brief Enables or disables the AHB3 peripheral clock. |
| * @note After reset, the peripheral clock (used for registers read/write access) |
| * is disabled and the application software has to enable this clock before |
| * using it. |
| * @{ |
| */ |
| #define __HAL_RCC_FMC_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN)) |
| #if defined(STM32F469xx) || defined(STM32F479xx) |
| #define __HAL_RCC_QSPI_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN)) |
| #endif /* STM32F469xx || STM32F479xx */ |
| /** |
| * @} |
| */ |
| |
| |
| /** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status |
| * @brief Get the enable or disable status of the AHB3 peripheral clock. |
| * @note After reset, the peripheral clock (used for registers read/write access) |
| * is disabled and the application software has to enable this clock before |
| * using it. |
| * @{ |
| */ |
| #define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET) |
| #define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET) |
| #if defined(STM32F469xx) || defined(STM32F479xx) |
| #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET) |
| #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET) |
| #endif /* STM32F469xx || STM32F479xx */ |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable |
| * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. |
| * @note After reset, the peripheral clock (used for registers read/write access) |
| * is disabled and the application software has to enable this clock before |
| * using it. |
| * @{ |
| */ |
| #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_TIM12_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_TIM13_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_USART3_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_UART4_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_UART5_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_CAN1_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_CAN2_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_DAC_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_UART7_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_UART8_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) |
| #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) |
| #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) |
| #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) |
| #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) |
| #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) |
| #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) |
| #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) |
| #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) |
| #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) |
| #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) |
| #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) |
| #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) |
| #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) |
| #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) |
| #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) |
| #define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN)) |
| #define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN)) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status |
| * @brief Get the enable or disable status of the APB1 peripheral clock. |
| * @note After reset, the peripheral clock (used for registers read/write access) |
| * is disabled and the application software has to enable this clock before |
| * using it. |
| * @{ |
| */ |
| #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) |
| #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) |
| #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) |
| #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) |
| #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) |
| #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) |
| #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) |
| #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) |
| #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) |
| #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) |
| #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) |
| #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) |
| #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) |
| #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) |
| #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) |
| #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) |
| #define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET) |
| #define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET) |
| |
| #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) |
| #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) |
| #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) |
| #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) |
| #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) |
| #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) |
| #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) |
| #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) |
| #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) |
| #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) |
| #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) |
| #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) |
| #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) |
| #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) |
| #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) |
| #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) |
| #define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET) |
| #define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable |
| * @brief Enable or disable the High Speed APB (APB2) peripheral clock. |
| * @note After reset, the peripheral clock (used for registers read/write access) |
| * is disabled and the application software has to enable this clock before |
| * using it. |
| * @{ |
| */ |
| #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_ADC2_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_ADC3_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_SPI5_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_SPI6_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_SAI1_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_SDIO_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_SPI4_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_TIM10_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) |
| #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) |
| #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) |
| #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) |
| #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) |
| #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) |
| #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) |
| #define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN)) |
| #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) |
| |
| #if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) |
| #define __HAL_RCC_LTDC_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| |
| #define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN)) |
| #endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ |
| |
| #if defined(STM32F469xx) || defined(STM32F479xx) |
| #define __HAL_RCC_DSI_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| |
| #define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN)) |
| #endif /* STM32F469xx || STM32F479xx */ |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status |
| * @brief Get the enable or disable status of the APB2 peripheral clock. |
| * @note After reset, the peripheral clock (used for registers read/write access) |
| * is disabled and the application software has to enable this clock before |
| * using it. |
| * @{ |
| */ |
| #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) |
| #define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) |
| #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) |
| #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) |
| #define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET) |
| #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) |
| #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) |
| #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) |
| #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))!= RESET) |
| |
| #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) |
| #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) |
| #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))== RESET) |
| #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) |
| #define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) |
| #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) |
| #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET) |
| #define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET) |
| #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET) |
| |
| #if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) |
| #define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET) |
| #define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET) |
| #endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ |
| |
| #if defined(STM32F469xx) || defined(STM32F479xx) |
| #define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET) |
| #define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET) |
| #endif /* STM32F469xx || STM32F479xx */ |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset |
| * @brief Force or release AHB1 peripheral reset. |
| * @{ |
| */ |
| #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) |
| #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) |
| #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) |
| #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) |
| #define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST)) |
| #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST)) |
| #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST)) |
| #define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST)) |
| #define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST)) |
| #define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST)) |
| #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) |
| |
| #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) |
| #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) |
| #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) |
| #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) |
| #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST)) |
| #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST)) |
| #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST)) |
| #define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST)) |
| #define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST)) |
| #define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST)) |
| #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset |
| * @brief Force or release AHB2 peripheral reset. |
| * @{ |
| */ |
| #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) |
| #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) |
| #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) |
| #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) |
| |
| #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) |
| #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) |
| #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) |
| #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) |
| |
| #if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) |
| #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST)) |
| #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST)) |
| |
| #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST)) |
| #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST)) |
| #endif /* STM32F437xx || STM32F439xx || STM32F479xx */ |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset |
| * @brief Force or release AHB3 peripheral reset. |
| * @{ |
| */ |
| #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) |
| #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) |
| #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) |
| #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST)) |
| |
| #if defined(STM32F469xx) || defined(STM32F479xx) |
| #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) |
| #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST)) |
| #endif /* STM32F469xx || STM32F479xx */ |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset |
| * @brief Force or release APB1 peripheral reset. |
| * @{ |
| */ |
| #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) |
| #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) |
| #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) |
| #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) |
| #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) |
| #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) |
| #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) |
| #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) |
| #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) |
| #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) |
| #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) |
| #define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST)) |
| #define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST)) |
| #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) |
| #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) |
| #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) |
| #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) |
| #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) |
| |
| #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) |
| #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) |
| #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) |
| #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) |
| #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) |
| #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) |
| #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) |
| #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) |
| #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) |
| #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) |
| #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) |
| #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) |
| #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) |
| #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) |
| #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) |
| #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) |
| #define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST)) |
| #define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST)) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset |
| * @brief Force or release APB2 peripheral reset. |
| * @{ |
| */ |
| #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) |
| #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) |
| #define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST)) |
| #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) |
| #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) |
| #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) |
| #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) |
| |
| #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) |
| #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) |
| #define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) |
| #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) |
| #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) |
| #define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST)) |
| #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) |
| |
| #if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) |
| #define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST)) |
| #define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST)) |
| #endif /* STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */ |
| |
| #if defined(STM32F469xx) || defined(STM32F479xx) |
| #define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DSIRST)) |
| #define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST)) |
| #endif /* STM32F469xx || STM32F479xx */ |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable |
| * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. |
| * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| * power consumption. |
| * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
| * @note By default, all peripheral clocks are enabled during SLEEP mode. |
| * @{ |
| */ |
| #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) |
| #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) |
| #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) |
| #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) |
| #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN)) |
| #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) |
| #define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN)) |
| #define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN)) |
| #define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN)) |
| #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN)) |
| #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN)) |
| #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN)) |
| #define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN)) |
| #define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN)) |
| #define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM3LPEN)) |
| #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN)) |
| #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) |
| #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) |
| #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) |
| #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN)) |
| |
| #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) |
| #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) |
| #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) |
| #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) |
| #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN)) |
| #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) |
| #define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN)) |
| #define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN)) |
| #define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN)) |
| #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN)) |
| #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN)) |
| #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN)) |
| #define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN)) |
| #define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN)) |
| #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN)) |
| #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) |
| #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) |
| #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) |
| #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN)) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable |
| * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. |
| * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| * power consumption. |
| * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. |
| * @note By default, all peripheral clocks are enabled during SLEEP mode. |
| * @{ |
| */ |
| #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) |
| #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) |
| |
| #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) |
| #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) |
| |
| #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) |
| #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) |
| |
| #if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) |
| #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) |
| #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) |
| |
| #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN)) |
| #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN)) |
| #endif /* STM32F437xx || STM32F439xx || STM32F479xx */ |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable |
| * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. |
| * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| * power consumption. |
| * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
| * @note By default, all peripheral clocks are enabled during SLEEP mode. |
| * @{ |
| */ |
| #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) |
| #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN)) |
| |
| #if defined(STM32F469xx) || defined(STM32F479xx) |
| #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) |
| #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN)) |
| #endif /* STM32F469xx || STM32F479xx */ |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable |
| * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. |
| * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| * power consumption. |
| * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
| * @note By default, all peripheral clocks are enabled during SLEEP mode. |
| * @{ |
| */ |
| #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) |
| #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) |
| #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) |
| #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) |
| #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) |
| #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) |
| #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) |
| #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) |
| #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) |
| #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) |
| #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) |
| #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN)) |
| #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN)) |
| #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) |
| #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) |
| #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) |
| #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) |
| #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) |
| |
| #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) |
| #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) |
| #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) |
| #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) |
| #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) |
| #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) |
| #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) |
| #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) |
| #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) |
| #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) |
| #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) |
| #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) |
| #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) |
| #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) |
| #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) |
| #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) |
| #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN)) |
| #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN)) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable |
| * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. |
| * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| * power consumption. |
| * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
| * @note By default, all peripheral clocks are enabled during SLEEP mode. |
| * @{ |
| */ |
| #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) |
| #define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN)) |
| #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN)) |
| #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) |
| #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN)) |
| #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) |
| #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) |
| #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) |
| #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) |
| |
| #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) |
| #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) |
| #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) |
| #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) |
| #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN)) |
| #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN)) |
| #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) |
| #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN)) |
| #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) |
| |
| #if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) |
| #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN)) |
| |
| #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN)) |
| #endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ |
| |
| #if defined(STM32F469xx) || defined(STM32F479xx) |
| #define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DSILPEN)) |
| #define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN)) |
| #endif /* STM32F469xx || STM32F479xx */ |
| /** |
| * @} |
| */ |
| #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */ |
| /*----------------------------------------------------------------------------*/ |
| |
| /*----------------------------------- STM32F40xxx/STM32F41xxx-----------------*/ |
| #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) |
| /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable |
| * @brief Enables or disables the AHB1 peripheral clock. |
| * @note After reset, the peripheral clock (used for registers read/write access) |
| * is disabled and the application software has to enable this clock before |
| * using it. |
| * @{ |
| */ |
| #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_CRC_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) |
| #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) |
| #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) |
| #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) |
| #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN)) |
| #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN)) |
| #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN)) |
| #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) |
| #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) |
| #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) |
| #if defined(STM32F407xx)|| defined(STM32F417xx) |
| /** |
| * @brief Enable ETHERNET clock. |
| */ |
| #define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_ETH_CLK_ENABLE() do { \ |
| __HAL_RCC_ETHMAC_CLK_ENABLE(); \ |
| __HAL_RCC_ETHMACTX_CLK_ENABLE(); \ |
| __HAL_RCC_ETHMACRX_CLK_ENABLE(); \ |
| } while(0U) |
| |
| /** |
| * @brief Disable ETHERNET clock. |
| */ |
| #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN)) |
| #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN)) |
| #define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN)) |
| #define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN)) |
| #define __HAL_RCC_ETH_CLK_DISABLE() do { \ |
| __HAL_RCC_ETHMACTX_CLK_DISABLE(); \ |
| __HAL_RCC_ETHMACRX_CLK_DISABLE(); \ |
| __HAL_RCC_ETHMAC_CLK_DISABLE(); \ |
| } while(0U) |
| #endif /* STM32F407xx || STM32F417xx */ |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status |
| * @brief Get the enable or disable status of the AHB1 peripheral clock. |
| * @note After reset, the peripheral clock (used for registers read/write access) |
| * is disabled and the application software has to enable this clock before |
| * using it. |
| * @{ |
| */ |
| #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET) |
| #define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET) |
| #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) |
| #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) |
| #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) |
| #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET) |
| #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) |
| #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) |
| #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET) |
| #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET) |
| |
| #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) |
| #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) |
| #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) |
| #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) |
| #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET) |
| #define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET) |
| #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN))== RESET) |
| #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET) |
| #define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) |
| #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) |
| #if defined(STM32F407xx)|| defined(STM32F417xx) |
| /** |
| * @brief Enable ETHERNET clock. |
| */ |
| #define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET) |
| #define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET) |
| #define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET) |
| #define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET) |
| #define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \ |
| __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \ |
| __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()) |
| /** |
| * @brief Disable ETHERNET clock. |
| */ |
| #define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET) |
| #define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET) |
| #define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET) |
| #define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET) |
| #define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \ |
| __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \ |
| __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()) |
| #endif /* STM32F407xx || STM32F417xx */ |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable |
| * @brief Enable or disable the AHB2 peripheral clock. |
| * @note After reset, the peripheral clock (used for registers read/write access) |
| * is disabled and the application software has to enable this clock before |
| * using it. |
| * @{ |
| */ |
| #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ |
| __HAL_RCC_SYSCFG_CLK_ENABLE();\ |
| }while(0U) |
| |
| #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) |
| |
| #define __HAL_RCC_RNG_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) |
| |
| #if defined(STM32F407xx)|| defined(STM32F417xx) |
| #define __HAL_RCC_DCMI_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) |
| #endif /* STM32F407xx || STM32F417xx */ |
| |
| #if defined(STM32F415xx) || defined(STM32F417xx) |
| #define __HAL_RCC_CRYP_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_HASH_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN)) |
| #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN)) |
| #endif /* STM32F415xx || STM32F417xx */ |
| /** |
| * @} |
| */ |
| |
| |
| /** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status |
| * @brief Get the enable or disable status of the AHB2 peripheral clock. |
| * @note After reset, the peripheral clock (used for registers read/write access) |
| * is disabled and the application software has to enable this clock before |
| * using it. |
| * @{ |
| */ |
| #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) |
| #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) |
| |
| #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) |
| #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) |
| |
| #if defined(STM32F407xx)|| defined(STM32F417xx) |
| #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET) |
| #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) |
| #endif /* STM32F407xx || STM32F417xx */ |
| |
| #if defined(STM32F415xx) || defined(STM32F417xx) |
| #define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET) |
| #define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET) |
| |
| #define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET) |
| #define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET) |
| #endif /* STM32F415xx || STM32F417xx */ |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable |
| * @brief Enables or disables the AHB3 peripheral clock. |
| * @note After reset, the peripheral clock (used for registers read/write access) |
| * is disabled and the application software has to enable this clock before |
| * using it. |
| * @{ |
| */ |
| #define __HAL_RCC_FSMC_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN)) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status |
| * @brief Get the enable or disable status of the AHB3 peripheral clock. |
| * @note After reset, the peripheral clock (used for registers read/write access) |
| * is disabled and the application software has to enable this clock before |
| * using it. |
| * @{ |
| */ |
| #define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET) |
| #define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable |
| * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. |
| * @note After reset, the peripheral clock (used for registers read/write access) |
| * is disabled and the application software has to enable this clock before |
| * using it. |
| * @{ |
| */ |
| #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_TIM12_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_TIM13_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_USART3_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_UART4_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_UART5_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_CAN1_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_CAN2_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_DAC_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg = 0x00U; \ |
| SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ |
| UNUSED(tmpreg); \ |
| } while(0U) |
| #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) |
| #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) |
| #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) |
| #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) |
| #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) |
| #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) |
| #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) |
| #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) |
| #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) |
| #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) |
| #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) |
| #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) |
| #define __HAL_RCC_UART5_CLK_DISABLE()<
|