commit 87d69f6ca0d208113cab203c45fda636bceda89a
author Eya <aya.selmi1@st.com> Mon Sep 26 17:38:57 2022 +0100
committer Eya <aya.selmi1@st.com> Tue Sep 27 16:06:11 2022 +0100
tree 4d63b36ec754916bb2ff68c6afb8f2723e6e4101
parent d5ec9669992d4bba4c226bbd7fec2d5e0c73f9c2

[HAL][I2C] Update I2C_MemoryTransmit_TXE_BTF process to disable TXE and BTF interrupts if nothing to do and clear TXE Flag at the end of transfer

Src/stm32f4xx_hal_i2c.c

diff --git a/Src/stm32f4xx_hal_i2c.c b/Src/stm32f4xx_hal_i2c.c
index c2a8eb7..a28ad6a 100644
--- a/Src/stm32f4xx_hal_i2c.c
+++ b/Src/stm32f4xx_hal_i2c.c
@@ -383,6 +383,9 @@
 
 /* Private function to Convert Specific options */
 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
+
+/* Private function to flush DR register */
+static void I2C_Flush_DR(I2C_HandleTypeDef *hi2c);
 /**
   * @}
   */
@@ -941,6 +944,20 @@
 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
 
 /**
+  * @brief  I2C data register flush process.
+  * @param  hi2c I2C handle.
+  * @retval None
+  */
+static void I2C_Flush_DR(I2C_HandleTypeDef *hi2c)
+{
+  /* Write a dummy data in DR to clear TXE flag */
+  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) != RESET)
+  {
+    hi2c->Instance->DR = 0x00U;
+  }
+}
+
+/**
   * @}
   */
 
@@ -5504,7 +5521,8 @@
   }
   else
   {
-    /* Do nothing */
+    /* Clear TXE and BTF flag */
+    I2C_Flush_DR(hi2c);
   }
 }
 
@@ -6367,6 +6385,9 @@
     /* Disable Acknowledge */
     CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
 
+    /*Clear TXE flag*/
+    I2C_Flush_DR(hi2c);
+
 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
     hi2c->SlaveTxCpltCallback(hi2c);
 #else