Release v1.8.1
diff --git a/Inc/Legacy/stm32_hal_legacy.h b/Inc/Legacy/stm32_hal_legacy.h
index 1cfd19b..934f1f9 100644
--- a/Inc/Legacy/stm32_hal_legacy.h
+++ b/Inc/Legacy/stm32_hal_legacy.h
@@ -37,14 +37,16 @@
#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
-#if defined(STM32U5)
+#if defined(STM32U5) || defined(STM32H7) || defined(STM32MP1)
#define CRYP_DATATYPE_32B CRYP_NO_SWAP
#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP
#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP
#define CRYP_DATATYPE_1B CRYP_BIT_SWAP
+#if defined(STM32U5)
#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF
#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF
#endif /* STM32U5 */
+#endif /* STM32U5 || STM32H7 || STM32MP1 */
/**
* @}
*/
@@ -110,6 +112,7 @@
#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES
#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5
#endif /* STM32U5 */
+
/**
* @}
*/
@@ -231,8 +234,11 @@
/** @defgroup CRC_Aliases CRC API aliases
* @{
*/
+#if defined(STM32C0)
+#else
#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */
#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
+#endif
/**
* @}
*/
@@ -499,7 +505,7 @@
#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
-#if defined(STM32G0)
+#if defined(STM32G0) || defined(STM32C0)
#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE
#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH
#else
@@ -568,7 +574,6 @@
#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
#endif /* STM32G4 */
-
/**
* @}
*/
@@ -668,6 +673,10 @@
#if defined(STM32U5)
#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ
#endif /* STM32U5 */
+#if defined(STM32U5)
+#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP
+#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1
+#endif /* STM32U5 */
/**
* @}
*/
@@ -1080,8 +1089,8 @@
#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
-#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
-#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
@@ -1092,15 +1101,22 @@
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
+#if defined(STM32F7)
+#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK
+#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK
+#endif /* STM32F7 */
+
#if defined(STM32H7)
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
+#endif /* STM32H7 */
+#if defined(STM32F7) || defined(STM32H7)
#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
-#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL
-#endif /* STM32H7 */
+#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP
+#endif /* STM32F7 || STM32H7 */
/**
* @}
@@ -3407,7 +3423,7 @@
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
-#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
+#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) || defined(STM32C0)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
@@ -3520,8 +3536,8 @@
#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
#if defined(STM32U5)
-#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL
-#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL
+#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL
+#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL
#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE
#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE
#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE
@@ -3537,15 +3553,20 @@
#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2
#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1
#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK
-#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
-#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
-#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
-#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
-#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
-#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
-#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE
-#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE
-#endif
+#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
+#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
+#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
+#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
+#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
+#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
+#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE
+#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE
+#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE
+#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE
+#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE
+#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG
+#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE
+#endif /* STM32U5 */
/**
* @}
@@ -3563,7 +3584,9 @@
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{
*/
-#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5)
+#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx)|| \
+ defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
+ defined (STM32C0)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
@@ -3616,7 +3639,6 @@
#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
-
/**
* @}
*/
@@ -3628,7 +3650,7 @@
#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
-#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32L1)
+#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1)
#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE
#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE
#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE
@@ -3965,6 +3987,16 @@
* @}
*/
+/** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#if defined (STM32F7)
+#define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE
+#endif /* STM32F7 */
+/**
+ * @}
+ */
+
/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
* @{
*/
diff --git a/Inc/stm32f4xx_hal_conf_template.h b/Inc/stm32f4xx_hal_conf_template.h
index d32595f..c0c4484 100644
--- a/Inc/stm32f4xx_hal_conf_template.h
+++ b/Inc/stm32f4xx_hal_conf_template.h
@@ -209,8 +209,8 @@
#define MAC_ADDR5 0U
/* Definition of the Ethernet driver buffers size and count */
-#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
-#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
+#define ETH_RX_BUF_SIZE 1528U /* ETH Max buffer size for receive */
+#define ETH_TX_BUF_SIZE 1528U /* ETH Max buffer size for transmit */
#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
diff --git a/Inc/stm32f4xx_hal_eth.h b/Inc/stm32f4xx_hal_eth.h
index 7b8797e..ba5a09b 100644
--- a/Inc/stm32f4xx_hal_eth.h
+++ b/Inc/stm32f4xx_hal_eth.h
@@ -401,7 +401,7 @@
typedef enum
{
HAL_ETH_MII_MODE = 0x00U, /*!< Media Independent Interface */
- HAL_ETH_RMII_MODE = ((uint32_t)SYSCFG_PMC_MII_RMII_SEL) /*!< Reduced Media Independent Interface */
+ HAL_ETH_RMII_MODE = SYSCFG_PMC_MII_RMII_SEL /*!< Reduced Media Independent Interface */
} ETH_MediaInterfaceTypeDef;
/**
*
@@ -691,51 +691,51 @@
/**
* @brief Bit definition of TDES0 register: DMA Tx descriptor status register
*/
-#define ETH_DMATXDESC_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */
-#define ETH_DMATXDESC_IC ((uint32_t)0x40000000U) /*!< Interrupt on Completion */
-#define ETH_DMATXDESC_LS ((uint32_t)0x20000000U) /*!< Last Segment */
-#define ETH_DMATXDESC_FS ((uint32_t)0x10000000U) /*!< First Segment */
-#define ETH_DMATXDESC_DC ((uint32_t)0x08000000U) /*!< Disable CRC */
-#define ETH_DMATXDESC_DP ((uint32_t)0x04000000U) /*!< Disable Padding */
-#define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000U) /*!< Transmit Time Stamp Enable */
-#define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000U) /*!< Checksum Insertion Control: 4 cases */
-#define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000U) /*!< Do Nothing: Checksum Engine is bypassed */
-#define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000U) /*!< IPV4 header Checksum Insertion */
-#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000U) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
-#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000U) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
-#define ETH_DMATXDESC_TER ((uint32_t)0x00200000U) /*!< Transmit End of Ring */
-#define ETH_DMATXDESC_TCH ((uint32_t)0x00100000U) /*!< Second Address Chained */
-#define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000U) /*!< Tx Time Stamp Status */
-#define ETH_DMATXDESC_IHE ((uint32_t)0x00010000U) /*!< IP Header Error */
-#define ETH_DMATXDESC_ES ((uint32_t)0x00008000U) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
-#define ETH_DMATXDESC_JT ((uint32_t)0x00004000U) /*!< Jabber Timeout */
-#define ETH_DMATXDESC_FF ((uint32_t)0x00002000U) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
-#define ETH_DMATXDESC_PCE ((uint32_t)0x00001000U) /*!< Payload Checksum Error */
-#define ETH_DMATXDESC_LCA ((uint32_t)0x00000800U) /*!< Loss of Carrier: carrier lost during transmission */
-#define ETH_DMATXDESC_NC ((uint32_t)0x00000400U) /*!< No Carrier: no carrier signal from the transceiver */
-#define ETH_DMATXDESC_LCO ((uint32_t)0x00000200U) /*!< Late Collision: transmission aborted due to collision */
-#define ETH_DMATXDESC_EC ((uint32_t)0x00000100U) /*!< Excessive Collision: transmission aborted after 16 collisions */
-#define ETH_DMATXDESC_VF ((uint32_t)0x00000080U) /*!< VLAN Frame */
-#define ETH_DMATXDESC_CC ((uint32_t)0x00000078U) /*!< Collision Count */
-#define ETH_DMATXDESC_ED ((uint32_t)0x00000004U) /*!< Excessive Deferral */
-#define ETH_DMATXDESC_UF ((uint32_t)0x00000002U) /*!< Underflow Error: late data arrival from the memory */
-#define ETH_DMATXDESC_DB ((uint32_t)0x00000001U) /*!< Deferred Bit */
+#define ETH_DMATXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */
+#define ETH_DMATXDESC_IC 0x40000000U /*!< Interrupt on Completion */
+#define ETH_DMATXDESC_LS 0x20000000U /*!< Last Segment */
+#define ETH_DMATXDESC_FS 0x10000000U /*!< First Segment */
+#define ETH_DMATXDESC_DC 0x08000000U /*!< Disable CRC */
+#define ETH_DMATXDESC_DP 0x04000000U /*!< Disable Padding */
+#define ETH_DMATXDESC_TTSE 0x02000000U /*!< Transmit Time Stamp Enable */
+#define ETH_DMATXDESC_CIC 0x00C00000U /*!< Checksum Insertion Control: 4 cases */
+#define ETH_DMATXDESC_CIC_BYPASS 0x00000000U /*!< Do Nothing: Checksum Engine is bypassed */
+#define ETH_DMATXDESC_CIC_IPV4HEADER 0x00400000U /*!< IPV4 header Checksum Insertion */
+#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT 0x00800000U /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
+#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL 0x00C00000U /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
+#define ETH_DMATXDESC_TER 0x00200000U /*!< Transmit End of Ring */
+#define ETH_DMATXDESC_TCH 0x00100000U /*!< Second Address Chained */
+#define ETH_DMATXDESC_TTSS 0x00020000U /*!< Tx Time Stamp Status */
+#define ETH_DMATXDESC_IHE 0x00010000U /*!< IP Header Error */
+#define ETH_DMATXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
+#define ETH_DMATXDESC_JT 0x00004000U /*!< Jabber Timeout */
+#define ETH_DMATXDESC_FF 0x00002000U /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
+#define ETH_DMATXDESC_PCE 0x00001000U /*!< Payload Checksum Error */
+#define ETH_DMATXDESC_LCA 0x00000800U /*!< Loss of Carrier: carrier lost during transmission */
+#define ETH_DMATXDESC_NC 0x00000400U /*!< No Carrier: no carrier signal from the transceiver */
+#define ETH_DMATXDESC_LCO 0x00000200U /*!< Late Collision: transmission aborted due to collision */
+#define ETH_DMATXDESC_EC 0x00000100U /*!< Excessive Collision: transmission aborted after 16 collisions */
+#define ETH_DMATXDESC_VF 0x00000080U /*!< VLAN Frame */
+#define ETH_DMATXDESC_CC 0x00000078U /*!< Collision Count */
+#define ETH_DMATXDESC_ED 0x00000004U /*!< Excessive Deferral */
+#define ETH_DMATXDESC_UF 0x00000002U /*!< Underflow Error: late data arrival from the memory */
+#define ETH_DMATXDESC_DB 0x00000001U /*!< Deferred Bit */
/**
* @brief Bit definition of TDES1 register
*/
-#define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000U) /*!< Transmit Buffer2 Size */
-#define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFFU) /*!< Transmit Buffer1 Size */
+#define ETH_DMATXDESC_TBS2 0x1FFF0000U /*!< Transmit Buffer2 Size */
+#define ETH_DMATXDESC_TBS1 0x00001FFFU /*!< Transmit Buffer1 Size */
/**
* @brief Bit definition of TDES2 register
*/
-#define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer1 Address Pointer */
+#define ETH_DMATXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */
/**
* @brief Bit definition of TDES3 register
*/
-#define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer2 Address Pointer */
+#define ETH_DMATXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */
/*---------------------------------------------------------------------------------------------
TDES6 | Transmit Time Stamp Low [31:0] |
@@ -744,10 +744,10 @@
----------------------------------------------------------------------------------------------*/
/* Bit definition of TDES6 register */
-#define ETH_DMAPTPTXDESC_TTSL ((uint32_t)0xFFFFFFFFU) /* Transmit Time Stamp Low */
+#define ETH_DMAPTPTXDESC_TTSL 0xFFFFFFFFU /* Transmit Time Stamp Low */
/* Bit definition of TDES7 register */
-#define ETH_DMAPTPTXDESC_TTSH ((uint32_t)0xFFFFFFFFU) /* Transmit Time Stamp High */
+#define ETH_DMAPTPTXDESC_TTSH 0xFFFFFFFFU /* Transmit Time Stamp High */
/**
* @}
@@ -774,44 +774,44 @@
/**
* @brief Bit definition of RDES0 register: DMA Rx descriptor status register
*/
-#define ETH_DMARXDESC_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */
-#define ETH_DMARXDESC_AFM ((uint32_t)0x40000000U) /*!< DA Filter Fail for the rx frame */
-#define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000U) /*!< Receive descriptor frame length */
-#define ETH_DMARXDESC_ES ((uint32_t)0x00008000U) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
-#define ETH_DMARXDESC_DE ((uint32_t)0x00004000U) /*!< Descriptor error: no more descriptors for receive frame */
-#define ETH_DMARXDESC_SAF ((uint32_t)0x00002000U) /*!< SA Filter Fail for the received frame */
-#define ETH_DMARXDESC_LE ((uint32_t)0x00001000U) /*!< Frame size not matching with length field */
-#define ETH_DMARXDESC_OE ((uint32_t)0x00000800U) /*!< Overflow Error: Frame was damaged due to buffer overflow */
-#define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400U) /*!< VLAN Tag: received frame is a VLAN frame */
-#define ETH_DMARXDESC_FS ((uint32_t)0x00000200U) /*!< First descriptor of the frame */
-#define ETH_DMARXDESC_LS ((uint32_t)0x00000100U) /*!< Last descriptor of the frame */
-#define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080U) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */
-#define ETH_DMARXDESC_LC ((uint32_t)0x00000040U) /*!< Late collision occurred during reception */
-#define ETH_DMARXDESC_FT ((uint32_t)0x00000020U) /*!< Frame type - Ethernet, otherwise 802.3 */
-#define ETH_DMARXDESC_RWT ((uint32_t)0x00000010U) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */
-#define ETH_DMARXDESC_RE ((uint32_t)0x00000008U) /*!< Receive error: error reported by MII interface */
-#define ETH_DMARXDESC_DBE ((uint32_t)0x00000004U) /*!< Dribble bit error: frame contains non int multiple of 8 bits */
-#define ETH_DMARXDESC_CE ((uint32_t)0x00000002U) /*!< CRC error */
-#define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001U) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
+#define ETH_DMARXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */
+#define ETH_DMARXDESC_AFM 0x40000000U /*!< DA Filter Fail for the rx frame */
+#define ETH_DMARXDESC_FL 0x3FFF0000U /*!< Receive descriptor frame length */
+#define ETH_DMARXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
+#define ETH_DMARXDESC_DE 0x00004000U /*!< Descriptor error: no more descriptors for receive frame */
+#define ETH_DMARXDESC_SAF 0x00002000U /*!< SA Filter Fail for the received frame */
+#define ETH_DMARXDESC_LE 0x00001000U /*!< Frame size not matching with length field */
+#define ETH_DMARXDESC_OE 0x00000800U /*!< Overflow Error: Frame was damaged due to buffer overflow */
+#define ETH_DMARXDESC_VLAN 0x00000400U /*!< VLAN Tag: received frame is a VLAN frame */
+#define ETH_DMARXDESC_FS 0x00000200U /*!< First descriptor of the frame */
+#define ETH_DMARXDESC_LS 0x00000100U /*!< Last descriptor of the frame */
+#define ETH_DMARXDESC_IPV4HCE 0x00000080U /*!< IPC Checksum Error: Rx Ipv4 header checksum error */
+#define ETH_DMARXDESC_LC 0x00000040U /*!< Late collision occurred during reception */
+#define ETH_DMARXDESC_FT 0x00000020U /*!< Frame type - Ethernet, otherwise 802.3 */
+#define ETH_DMARXDESC_RWT 0x00000010U /*!< Receive Watchdog Timeout: watchdog timer expired during reception */
+#define ETH_DMARXDESC_RE 0x00000008U /*!< Receive error: error reported by MII interface */
+#define ETH_DMARXDESC_DBE 0x00000004U /*!< Dribble bit error: frame contains non int multiple of 8 bits */
+#define ETH_DMARXDESC_CE 0x00000002U /*!< CRC error */
+#define ETH_DMARXDESC_MAMPCE 0x00000001U /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
/**
* @brief Bit definition of RDES1 register
*/
-#define ETH_DMARXDESC_DIC ((uint32_t)0x80000000U) /*!< Disable Interrupt on Completion */
-#define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000U) /*!< Receive Buffer2 Size */
-#define ETH_DMARXDESC_RER ((uint32_t)0x00008000U) /*!< Receive End of Ring */
-#define ETH_DMARXDESC_RCH ((uint32_t)0x00004000U) /*!< Second Address Chained */
-#define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFFU) /*!< Receive Buffer1 Size */
+#define ETH_DMARXDESC_DIC 0x80000000U /*!< Disable Interrupt on Completion */
+#define ETH_DMARXDESC_RBS2 0x1FFF0000U /*!< Receive Buffer2 Size */
+#define ETH_DMARXDESC_RER 0x00008000U /*!< Receive End of Ring */
+#define ETH_DMARXDESC_RCH 0x00004000U /*!< Second Address Chained */
+#define ETH_DMARXDESC_RBS1 0x00001FFFU /*!< Receive Buffer1 Size */
/**
* @brief Bit definition of RDES2 register
*/
-#define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer1 Address Pointer */
+#define ETH_DMARXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */
/**
* @brief Bit definition of RDES3 register
*/
-#define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer2 Address Pointer */
+#define ETH_DMARXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */
/*---------------------------------------------------------------------------------------------------------------------
RDES4 | Reserved[31:15] | Extended Status [14:0] |
@@ -824,47 +824,47 @@
--------------------------------------------------------------------------------------------------------------------*/
/* Bit definition of RDES4 register */
-#define ETH_DMAPTPRXDESC_PTPV ((uint32_t)0x00002000U) /* PTP Version */
-#define ETH_DMAPTPRXDESC_PTPFT ((uint32_t)0x00001000U) /* PTP Frame Type */
-#define ETH_DMAPTPRXDESC_PTPMT ((uint32_t)0x00000F00U) /* PTP Message Type */
-#define ETH_DMAPTPRXDESC_PTPMT_SYNC ((uint32_t)0x00000100U) /* SYNC message
- (all clock types) */
-#define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP ((uint32_t)0x00000200U) /* FollowUp message
- (all clock types) */
-#define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ ((uint32_t)0x00000300U) /* DelayReq message
- (all clock types) */
-#define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP ((uint32_t)0x00000400U) /* DelayResp message
- (all clock types) */
-#define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE ((uint32_t)0x00000500U) /* PdelayReq message
- (peer-to-peer transparent clock)
- or Announce message (Ordinary
- or Boundary clock) */
-#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG ((uint32_t)0x00000600U) /* PdelayResp message
- (peer-to-peer transparent clock)
- or Management message (Ordinary
- or Boundary clock) */
-#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700U) /* PdelayRespFollowUp message
- (peer-to-peer transparent clock)
- or Signaling message (Ordinary
- or Boundary clock) */
-#define ETH_DMAPTPRXDESC_IPV6PR ((uint32_t)0x00000080U) /* IPv6 Packet Received */
-#define ETH_DMAPTPRXDESC_IPV4PR ((uint32_t)0x00000040U) /* IPv4 Packet Received */
-#define ETH_DMAPTPRXDESC_IPCB ((uint32_t)0x00000020U) /* IP Checksum Bypassed */
-#define ETH_DMAPTPRXDESC_IPPE ((uint32_t)0x00000010U) /* IP Payload Error */
-#define ETH_DMAPTPRXDESC_IPHE ((uint32_t)0x00000008U) /* IP Header Error */
-#define ETH_DMAPTPRXDESC_IPPT ((uint32_t)0x00000007U) /* IP Payload Type */
-#define ETH_DMAPTPRXDESC_IPPT_UDP ((uint32_t)0x00000001U) /* UDP payload encapsulated in
- the IP datagram */
-#define ETH_DMAPTPRXDESC_IPPT_TCP ((uint32_t)0x00000002U) /* TCP payload encapsulated in
- the IP datagram */
-#define ETH_DMAPTPRXDESC_IPPT_ICMP ((uint32_t)0x00000003U) /* ICMP payload encapsulated in
+#define ETH_DMAPTPRXDESC_PTPV 0x00002000U /* PTP Version */
+#define ETH_DMAPTPRXDESC_PTPFT 0x00001000U /* PTP Frame Type */
+#define ETH_DMAPTPRXDESC_PTPMT 0x00000F00U /* PTP Message Type */
+#define ETH_DMAPTPRXDESC_PTPMT_SYNC 0x00000100U /* SYNC message
+ (all clock types) */
+#define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP 0x00000200U /* FollowUp message
+ (all clock types) */
+#define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ 0x00000300U /* DelayReq message
+ (all clock types) */
+#define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP 0x00000400U /* DelayResp message
+ (all clock types) */
+#define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE 0x00000500U /* PdelayReq message
+ (peer-to-peer transparent clock)
+ or Announce message (Ordinary
+ or Boundary clock) */
+#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG 0x00000600U /* PdelayResp message
+ (peer-to-peer transparent clock)
+ or Management message (Ordinary
+ or Boundary clock) */
+#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL 0x00000700U /* PdelayRespFollowUp message
+ (peer-to-peer transparent clock)
+ or Signaling message (Ordinary
+ or Boundary clock) */
+#define ETH_DMAPTPRXDESC_IPV6PR 0x00000080U /* IPv6 Packet Received */
+#define ETH_DMAPTPRXDESC_IPV4PR 0x00000040U /* IPv4 Packet Received */
+#define ETH_DMAPTPRXDESC_IPCB 0x00000020U /* IP Checksum Bypassed */
+#define ETH_DMAPTPRXDESC_IPPE 0x00000010U /* IP Payload Error */
+#define ETH_DMAPTPRXDESC_IPHE 0x00000008U /* IP Header Error */
+#define ETH_DMAPTPRXDESC_IPPT 0x00000007U /* IP Payload Type */
+#define ETH_DMAPTPRXDESC_IPPT_UDP 0x00000001U /* UDP payload encapsulated in
+ the IP datagram */
+#define ETH_DMAPTPRXDESC_IPPT_TCP 0x00000002U /* TCP payload encapsulated in
+ the IP datagram */
+#define ETH_DMAPTPRXDESC_IPPT_ICMP 0x00000003U /* ICMP payload encapsulated in
the IP datagram */
/* Bit definition of RDES6 register */
-#define ETH_DMAPTPRXDESC_RTSL ((uint32_t)0xFFFFFFFFU) /* Receive Time Stamp Low */
+#define ETH_DMAPTPRXDESC_RTSL 0xFFFFFFFFU /* Receive Time Stamp Low */
/* Bit definition of RDES7 register */
-#define ETH_DMAPTPRXDESC_RTSH ((uint32_t)0xFFFFFFFFU) /* Receive Time Stamp High */
+#define ETH_DMAPTPRXDESC_RTSH 0xFFFFFFFFU /* Receive Time Stamp High */
/**
* @}
@@ -873,13 +873,13 @@
/** @defgroup ETH_Frame_settings ETH frame settings
* @{
*/
-#define ETH_MAX_PACKET_SIZE ((uint32_t)1528U) /*!< ETH_HEADER + 2*VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC */
-#define ETH_HEADER ((uint32_t)14U) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
-#define ETH_CRC ((uint32_t)4U) /*!< Ethernet CRC */
-#define ETH_VLAN_TAG ((uint32_t)4U) /*!< optional 802.1q VLAN Tag */
-#define ETH_MIN_PAYLOAD ((uint32_t)46U) /*!< Minimum Ethernet payload size */
-#define ETH_MAX_PAYLOAD ((uint32_t)1500U) /*!< Maximum Ethernet payload size */
-#define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000U) /*!< Jumbo frame payload size */
+#define ETH_MAX_PACKET_SIZE 1528U /*!< ETH_HEADER + 2*VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC */
+#define ETH_HEADER 14U /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
+#define ETH_CRC 4U /*!< Ethernet CRC */
+#define ETH_VLAN_TAG 4U /*!< optional 802.1q VLAN Tag */
+#define ETH_MIN_PAYLOAD 46U /*!< Minimum Ethernet payload size */
+#define ETH_MAX_PAYLOAD 1500U /*!< Maximum Ethernet payload size */
+#define ETH_JUMBO_FRAME_PAYLOAD 9000U /*!< Jumbo frame payload size */
/**
* @}
*/
@@ -887,14 +887,14 @@
/** @defgroup ETH_Error_Code ETH Error Code
* @{
*/
-#define HAL_ETH_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
-#define HAL_ETH_ERROR_PARAM ((uint32_t)0x00000001U) /*!< Busy error */
-#define HAL_ETH_ERROR_BUSY ((uint32_t)0x00000002U) /*!< Parameter error */
-#define HAL_ETH_ERROR_TIMEOUT ((uint32_t)0x00000004U) /*!< Timeout error */
-#define HAL_ETH_ERROR_DMA ((uint32_t)0x00000008U) /*!< DMA transfer error */
-#define HAL_ETH_ERROR_MAC ((uint32_t)0x00000010U) /*!< MAC transfer error */
+#define HAL_ETH_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_ETH_ERROR_PARAM 0x00000001U /*!< Busy error */
+#define HAL_ETH_ERROR_BUSY 0x00000002U /*!< Parameter error */
+#define HAL_ETH_ERROR_TIMEOUT 0x00000004U /*!< Timeout error */
+#define HAL_ETH_ERROR_DMA 0x00000008U /*!< DMA transfer error */
+#define HAL_ETH_ERROR_MAC 0x00000010U /*!< MAC transfer error */
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
-#define HAL_ETH_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid Callback error */
+#define HAL_ETH_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid Callback error */
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
/**
* @}
@@ -903,12 +903,12 @@
/** @defgroup ETH_Tx_Packet_Attributes ETH Tx Packet Attributes
* @{
*/
-#define ETH_TX_PACKETS_FEATURES_CSUM ((uint32_t)0x00000001U)
-#define ETH_TX_PACKETS_FEATURES_SAIC ((uint32_t)0x00000002U)
-#define ETH_TX_PACKETS_FEATURES_VLANTAG ((uint32_t)0x00000004U)
-#define ETH_TX_PACKETS_FEATURES_INNERVLANTAG ((uint32_t)0x00000008U)
-#define ETH_TX_PACKETS_FEATURES_TSO ((uint32_t)0x00000010U)
-#define ETH_TX_PACKETS_FEATURES_CRCPAD ((uint32_t)0x00000020U)
+#define ETH_TX_PACKETS_FEATURES_CSUM 0x00000001U
+#define ETH_TX_PACKETS_FEATURES_SAIC 0x00000002U
+#define ETH_TX_PACKETS_FEATURES_VLANTAG 0x00000004U
+#define ETH_TX_PACKETS_FEATURES_INNERVLANTAG 0x00000008U
+#define ETH_TX_PACKETS_FEATURES_TSO 0x00000010U
+#define ETH_TX_PACKETS_FEATURES_CRCPAD 0x00000020U
/**
* @}
*/
@@ -927,7 +927,7 @@
* @{
*/
#define ETH_CRC_PAD_DISABLE (uint32_t)(ETH_DMATXDESC_DP | ETH_DMATXDESC_DC)
-#define ETH_CRC_PAD_INSERT ((uint32_t)0x00000000U)
+#define ETH_CRC_PAD_INSERT 0x00000000U
#define ETH_CRC_INSERT ETH_DMATXDESC_DP
/**
* @}
@@ -994,7 +994,7 @@
* @{
*/
#define ETH_DMAARBITRATION_RX ETH_DMAMR_DA
-#define ETH_DMAARBITRATION_RX1_TX1 ((uint32_t)0x00000000U)
+#define ETH_DMAARBITRATION_RX1_TX1 0x00000000U
#define ETH_DMAARBITRATION_RX2_TX1 ETH_DMAMR_PR_2_1
#define ETH_DMAARBITRATION_RX3_TX1 ETH_DMAMR_PR_3_1
#define ETH_DMAARBITRATION_RX4_TX1 ETH_DMAMR_PR_4_1
@@ -1003,7 +1003,7 @@
#define ETH_DMAARBITRATION_RX7_TX1 ETH_DMAMR_PR_7_1
#define ETH_DMAARBITRATION_RX8_TX1 ETH_DMAMR_PR_8_1
#define ETH_DMAARBITRATION_TX (ETH_DMAMR_TXPR | ETH_DMAMR_DA)
-#define ETH_DMAARBITRATION_TX1_RX1 ((uint32_t)0x00000000U)
+#define ETH_DMAARBITRATION_TX1_RX1 0x00000000U
#define ETH_DMAARBITRATION_TX2_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_2_1)
#define ETH_DMAARBITRATION_TX3_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_3_1)
#define ETH_DMAARBITRATION_TX4_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_4_1)
@@ -1020,7 +1020,7 @@
*/
#define ETH_BURSTLENGTH_FIXED ETH_DMABMR_FB
#define ETH_BURSTLENGTH_MIXED ETH_DMABMR_MB
-#define ETH_BURSTLENGTH_UNSPECIFIED ((uint32_t)0x00000000U)
+#define ETH_BURSTLENGTH_UNSPECIFIED 0x00000000U
/**
* @}
*/
@@ -1086,12 +1086,12 @@
/** @defgroup ETH_DMA_Status_Flags ETH DMA Status Flags
* @{
*/
-#define ETH_DMA_RX_NO_ERROR_FLAG ((uint32_t)0x00000000U)
+#define ETH_DMA_RX_NO_ERROR_FLAG 0x00000000U
#define ETH_DMA_RX_DESC_READ_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1 | ETH_DMACSR_REB_BIT_0)
#define ETH_DMA_RX_DESC_WRITE_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1)
#define ETH_DMA_RX_BUFFER_READ_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_0)
#define ETH_DMA_RX_BUFFER_WRITE_ERROR_FLAG ETH_DMACSR_REB_BIT_2
-#define ETH_DMA_TX_NO_ERROR_FLAG ((uint32_t)0x00000000U)
+#define ETH_DMA_TX_NO_ERROR_FLAG 0x00000000U
#define ETH_DMA_TX_DESC_READ_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1 | ETH_DMACSR_TEB_BIT_0)
#define ETH_DMA_TX_DESC_WRITE_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1)
#define ETH_DMA_TX_BUFFER_READ_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_0)
@@ -1188,7 +1188,7 @@
/** @defgroup ETH_Speed ETH Speed
* @{
*/
-#define ETH_SPEED_10M ((uint32_t)0x00000000U)
+#define ETH_SPEED_10M 0x00000000U
#define ETH_SPEED_100M 0x00004000U
/**
* @}
@@ -1198,7 +1198,7 @@
* @{
*/
#define ETH_FULLDUPLEX_MODE ETH_MACCR_DM
-#define ETH_HALFDUPLEX_MODE ((uint32_t)0x00000000U)
+#define ETH_HALFDUPLEX_MODE 0x00000000U
/**
* @}
*/
@@ -1227,7 +1227,7 @@
/** @defgroup ETH_Source_Addr_Control ETH Source Addr Control
* @{
*/
-#define ETH_SOURCEADDRESS_DISABLE ((uint32_t)0x00000000U)
+#define ETH_SOURCEADDRESS_DISABLE 0x00000000U
#define ETH_SOURCEADDRESS_INSERT_ADDR0 ETH_MACCR_SARC_INSADDR0
#define ETH_SOURCEADDRESS_INSERT_ADDR1 ETH_MACCR_SARC_INSADDR1
#define ETH_SOURCEADDRESS_REPLACE_ADDR0 ETH_MACCR_SARC_REPADDR0
@@ -1259,10 +1259,10 @@
/** @defgroup ETH_MAC_addresses ETH MAC addresses
* @{
*/
-#define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000U)
-#define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008U)
-#define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010U)
-#define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018U)
+#define ETH_MAC_ADDRESS0 0x00000000U
+#define ETH_MAC_ADDRESS1 0x00000008U
+#define ETH_MAC_ADDRESS2 0x00000010U
+#define ETH_MAC_ADDRESS3 0x00000018U
/**
* @}
*/
@@ -1301,11 +1301,11 @@
/** @defgroup HAL_ETH_StateTypeDef ETH States
* @{
*/
-#define HAL_ETH_STATE_RESET ((uint32_t)0x00000000U) /*!< Peripheral not yet Initialized or disabled */
-#define HAL_ETH_STATE_READY ((uint32_t)0x00000010U) /*!< Peripheral Communication started */
-#define HAL_ETH_STATE_BUSY ((uint32_t)0x00000023U) /*!< an internal process is ongoing */
-#define HAL_ETH_STATE_STARTED ((uint32_t)0x00000023U) /*!< an internal process is started */
-#define HAL_ETH_STATE_ERROR ((uint32_t)0x000000E0U) /*!< Error State */
+#define HAL_ETH_STATE_RESET 0x00000000U /*!< Peripheral not yet Initialized or disabled */
+#define HAL_ETH_STATE_READY 0x00000010U /*!< Peripheral Communication started */
+#define HAL_ETH_STATE_BUSY 0x00000023U /*!< an internal process is ongoing */
+#define HAL_ETH_STATE_STARTED 0x00000023U /*!< an internal process is started */
+#define HAL_ETH_STATE_ERROR 0x000000E0U /*!< Error State */
/**
* @}
*/
@@ -1341,7 +1341,7 @@
* @{
*/
#define ETH_MEDIA_INTERFACE_MII 0x00000000U
-#define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)
+#define ETH_MEDIA_INTERFACE_RMII (SYSCFG_PMC_MII_RMII_SEL)
/**
* @}
*/
@@ -1802,8 +1802,8 @@
/** @defgroup ETH_PTP_Config_Status ETH PTP Config Status
* @{
*/
-#define HAL_ETH_PTP_NOT_CONFIGURATED ((uint32_t)0x00000000U) /*!< ETH PTP Configuration not done */
-#define HAL_ETH_PTP_CONFIGURATED ((uint32_t)0x00000001U) /*!< ETH PTP Configuration done */
+#define HAL_ETH_PTP_NOT_CONFIGURATED 0x00000000U /*!< ETH PTP Configuration not done */
+#define HAL_ETH_PTP_CONFIGURATED 0x00000001U /*!< ETH PTP Configuration done */
/**
* @}
*/
@@ -1925,7 +1925,7 @@
( __INTERRUPT__)) == ( __INTERRUPT__))
/*!< External interrupt line 19 Connected to the ETH wakeup EXTI Line */
-#define ETH_WAKEUP_EXTI_LINE ((uint32_t)0x00080000U)
+#define ETH_WAKEUP_EXTI_LINE 0x00080000U
/**
* @brief Enable the ETH WAKEUP Exti Line.
diff --git a/Inc/stm32f4xx_hal_rtc.h b/Inc/stm32f4xx_hal_rtc.h
index 6254ad6..24affc5 100644
--- a/Inc/stm32f4xx_hal_rtc.h
+++ b/Inc/stm32f4xx_hal_rtc.h
@@ -491,13 +491,6 @@
/**
- * @brief Check whether the RTC Calendar is initialized.
- * @param __HANDLE__ specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_IS_CALENDAR_INITIALIZED(__HANDLE__) (((((__HANDLE__)->Instance->ISR) & (RTC_FLAG_INITS)) == RTC_FLAG_INITS) ? 1U : 0U)
-
-/**
* @brief Enable the RTC ALARMA peripheral.
* @param __HANDLE__ specifies the RTC handle.
* @retval None
diff --git a/Inc/stm32f4xx_ll_adc.h b/Inc/stm32f4xx_ll_adc.h
index 4368c2f..49fee97 100644
--- a/Inc/stm32f4xx_ll_adc.h
+++ b/Inc/stm32f4xx_ll_adc.h
@@ -1879,9 +1879,6 @@
#else
__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
{
- /* Prevent unused argument compilation warning */
- (void)Register;
-
/* Retrieve address of register DR */
return (uint32_t)&(ADCx->DR);
}
@@ -4018,7 +4015,7 @@
*/
__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
{
- return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
+ return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
}
/**
@@ -4033,7 +4030,7 @@
*/
__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
{
- return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
+ return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
}
#if defined(ADC_MULTIMODE_SUPPORT)
diff --git a/README.md b/README.md
index c345d9b..5900a11 100644
--- a/README.md
+++ b/README.md
@@ -27,21 +27,7 @@
## Compatibility information
-In this table, you can find the successive versions of this HAL-LL Driver component, in line with the corresponding versions of the full MCU package:
-
-It is **crucial** that you use a consistent set of versions for the CMSIS Core - CMSIS Device - HAL, as mentioned in this table.
-
-HAL Driver F4 | CMSIS Device F4 | CMSIS Core | Was delivered in the full MCU package
-------------- | --------------- | ---------- | -------------------------------------
-Tag v1.7.6 | Tag v2.6.3 | Tag v5.4.0_cm4 | Tag v1.24.1 (and following, if any, till HAL tag)
-Tag v1.7.7 | Tag v2.6.4 | Tag v5.4.0_cm4 | Tag v1.24.2 (and following, if any, till HAL tag)
-Tag v1.7.8 | Tag v2.6.5 | Tag v5.4.0_cm4 | Tag v1.25.0 (and following, if any, till HAL tag)
-Tag v1.7.9 | Tag v2.6.5 | Tag v5.4.0_cm4 | Tag v1.25.1 (and following, if any, till HAL tag)
-Tag v1.7.10| Tag v2.6.5 | Tag v5.4.0_cm4 | Tag v1.25.2 (and following, if any, till HAL tag)
-Tag v1.7.11| Tag v2.6.6 | Tag v5.4.0_cm4 | Tag v1.26.0 (and following, if any, till HAL tag)
-Tag v1.7.12| Tag v2.6.6 | Tag v5.4.0_cm4 | Tag v1.26.1 (and following, if any, till HAL tag)
-Tag v1.7.13| Tag v2.6.7 | Tag v5.4.0_cm4 | Tag v1.26.2 (and following, if any, till HAL tag)
-Tag v1.8.0 | Tag v2.6.8 | Tag v5.4.0_cm4 | Tag v1.27.0 (and following, if any, till HAL tag)
+It is **crucial** that you use a consistent set of versions for the CMSIS Core - CMSIS Device - HAL, as mentioned in [this](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/STM32CubeF4/blob/master/Release_Notes.html) release note.
The full **STM32CubeF4** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeF4).
diff --git a/Release_Notes.html b/Release_Notes.html
index 08f03c7..215114f 100644
--- a/Release_Notes.html
+++ b/Release_Notes.html
@@ -6,7 +6,8 @@
<meta http-equiv="content-type" content="text/html;
- charset=windows-1252"><title>Release Notes for STM32F4xx HAL Drivers</title></head><body lang="EN-US" link="blue" vlink="blue">
+ charset=windows-1252"><title>Release Notes for STM32F4xx HAL Drivers</title></head>
+<body lang="EN-US" link="blue" vlink="blue">
<div class="WordSection1">
<div>
<p class="MsoNormal" style=""><span style="font-family: "Arial",sans-serif;"><o:p> </o:p></span></p>
@@ -46,11 +47,30 @@
<tbody>
<tr style="">
<td style="padding: 0in; width: 843.25pt;" valign="top" width="1124">
- <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"><font color="#ffffff"><a name="History"></a><span style="font-size: 12pt;">Update
+ <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><font color="#ffffff"><a name="History"></a><span style="font-size: 12pt;">Update
- History</span><span style=""><o:p></o:p></span></font></h2><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.8.0
+ History</span><span style=""><o:p></o:p></span></font></h2><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.8.1
+ / 24-June-2022</span></font></h3>
+ <blockquote>
+ <p><b><u><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;">Main
+
+
+
+
+ Changes<br>
+ </span></u></b></p>
+ </blockquote>
+ <ul style="orphans: 2; text-align: start; widows: 2; word-spacing: 0px;" type="disc"><li><font face="Verdana" size="-1">General updates to fix HAL ETH defects and implementation enhancements.</font></li><li><p><font face="Verdana" size="-1"><strong>HAL</strong>
+ updates</font></p>
+ <font face="Verdana" size="-1"> </font>
+
+ <ul><font face="Verdana" size="-1">
+ </font><li><font face="Verdana" size="-1"><strong>HAL ETH </strong>update</font></li><ul><li style="font-family: -apple-system,BlinkMacSystemFont,"Segoe UI",Roboto,Ubuntu,"Helvetica Neue",Helvetica,sans-serif; line-height: 1.4;">Remove useless assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr)) from static function ETH_MACAddressConfig().</li><li style="font-family: -apple-system,BlinkMacSystemFont,"Segoe UI",Roboto,Ubuntu,"Helvetica Neue",Helvetica,sans-serif; line-height: 1.4;">Replace hard coded Rx buffer size (1000U) by macro ETH_RX_BUF_SIZE.</li><li style="font-family: -apple-system,BlinkMacSystemFont,"Segoe UI",Roboto,Ubuntu,"Helvetica Neue",Helvetica,sans-serif; line-height: 1.4;">Correct
+bit positions when getting MAC and DMA configurations and replace
+UnicastSlowProtocolPacketDetect by UnicastPausePacketDetect in the
+MAC default configuration structure.</li><li style="font-family: -apple-system,BlinkMacSystemFont,"Segoe UI",Roboto,Ubuntu,"Helvetica Neue",Helvetica,sans-serif; line-height: 1.4;">Ensure a delay of 4 TX_CLK/RX_CLK cycles between two successive write operations to the same register.</li><li style="font-family: -apple-system,BlinkMacSystemFont,"Segoe UI",Roboto,Ubuntu,"Helvetica Neue",Helvetica,sans-serif; line-height: 1.4;">Disable DMA transmission in both HAL_ETH_Stop_IT() and HAL_ETH_Stop() APIs.<br><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;"></span></font></li></ul></ul></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.8.0
/ 11-February-2022</span></font></h3>
<blockquote>
<p><b><u><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;">Main
@@ -260,7 +280,7 @@
</ul>
</li>
</ul>
- <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.7.13
+ <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.7.13
/ 16-July-2021</span></font></h3>
<blockquote>
<p><b><u><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;">Main
@@ -467,7 +487,7 @@
in USB PCD control
endpoint receive ISR.</font><br><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;"></span></font></li></ul>
</li></ul>
- </li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.7.12
+ </li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.7.12
/ 26-March-2021</span><span style=""><o:p></o:p></span></font></h3>
<p class="MsoNormal" style="margin: 4.5pt 0in 4.5pt 118.5pt; text-indent: -97.5pt;"><b><u><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;">Main
@@ -491,7 +511,7 @@
</ul>
</ul>
</ul>
- <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.7.11
+ <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.7.11
/ 12-February-2021</span><span style=""><o:p></o:p></span></font></h3>
<p class="MsoNormal" style="margin: 4.5pt 0in 4.5pt 118.5pt; text-indent: -97.5pt;"><b><u><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;">Main
@@ -1016,7 +1036,7 @@
</ul>
</ul>
</ul>
- <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">V1.7.10
+ <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">V1.7.10
@@ -1050,7 +1070,7 @@
</ul>
</ul>
</ul>
- <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.7.9
+ <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.7.9
@@ -1172,7 +1192,7 @@
mode.<o:p></o:p></span></li>
</ul>
</ul>
- <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.7.8
+ <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.7.8
@@ -1280,7 +1300,7 @@
</ul>
</ul>
</ul>
- <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.7.7
+ <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.7.7
@@ -2435,7 +2455,7 @@
with reference manual</span><span style=""><o:p></o:p></span></li>
</ul>
</ul>
- <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.7.6
+ <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.7.6
@@ -2563,7 +2583,7 @@
interrupt handlers<o:p></o:p></span></li>
</ul>
</ul>
- <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.7.5
+ <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.7.5
@@ -3277,7 +3297,7 @@
instance defined in CMSIS <span class="grame"><span style="font-family: "Verdana",sans-serif;">device</span></span></span><span style=""><o:p></o:p></span></li>
</ul>
</ul>
- <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.7.4
+ <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.7.4
@@ -3339,7 +3359,7 @@
audio issue</span><span style=""><o:p></o:p></span></li>
</ul>
</ul>
- <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.7.3
+ <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.7.3
@@ -3610,7 +3630,7 @@
/ <span class="spelle"><span style="font-family: "Verdana",sans-serif;">FSMC_PCCARD_Init</span></span>()</span><span style=""><o:p></o:p></span></li>
</ul>
</ul>
- <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.7.2
+ <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.7.2
@@ -3995,7 +4015,7 @@
<span class="grame"><span style="font-family: "Verdana",sans-serif;">used</span></span></span><span style=""><o:p></o:p></span></li>
</ul>
</ul>
- <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.7.1
+ <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.7.1
@@ -4079,7 +4099,7 @@
</ul>
</ul>
</ul>
- <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.7.0
+ <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.7.0
@@ -4578,7 +4598,7 @@
functions</span><span style=""><o:p></o:p></span></li>
</ul>
</ul>
- <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.6.0
+ <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.6.0
@@ -4814,7 +4834,7 @@
<span class="grame"><span style="font-family: "Verdana",sans-serif;">callbacks</span></span></span></span><span style=""><o:p></o:p></span></li>
</ul>
</ul>
- <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.5.2
+ <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.5.2
@@ -4913,7 +4933,7 @@
optimization </span><o:p></o:p></span></span></li>
</ul>
</ul>
- <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.5.1
+ <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.5.1
@@ -5005,7 +5025,7 @@
concurrent <span class="grame">way</span></span></span><o:p></o:p></span></li>
</ul>
</ul>
- <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.5.0
+ <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.5.0
@@ -6211,7 +6231,7 @@
the changes: <span class="spelle"><span style="font-family: "Verdana",sans-serif;">WWDG_</span></span><span class="grame"><span style="font-family: "Verdana",sans-serif;">Example</span></span></span><span style=""><o:p></o:p></span></li>
</ul>
</ul>
- <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.4.4
+ <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.4.4
@@ -6957,7 +6977,7 @@
<p class="MsoNormal" style=""><span style="font-size: 10pt;"><br style="">
<!--[if !supportLineBreakNewLine]--><br style="">
<!--[endif]--><o:p></o:p></span></p>
- <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.4.4
+ <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.4.4
/ 11-December-2015</span><span style=""><o:p></o:p></span></font></h3>
<p class="MsoNormal" style=""><b><u><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;">Main Changes</span></u></b><span style="font-size: 10pt;"><o:p></o:p></span></p>
<ul style="margin-top: 0in;" type="square">
@@ -6995,7 +7015,7 @@
Software reset management</span><span style=""><o:p></o:p></span></li>
</ul>
</ul>
- <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.4.2
+ <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.4.2
@@ -7227,7 +7247,7 @@
parameters</span><span style=""><o:p></o:p></span></li>
</ul>
</ul>
- <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.4.1
+ <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.4.1
@@ -7317,7 +7337,7 @@
calculated <span class="grame"><span style="font-family: "Verdana",sans-serif;">correctly</span></span></span><span style=""><o:p></o:p></span></li>
</ul>
</ul>
- <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.4.0
+ <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.4.0
@@ -7547,7 +7567,7 @@
devices</span><span style=""><o:p></o:p></span></li>
</ul>
</ul>
- <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.3.2
+ <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.3.2
@@ -7875,7 +7895,7 @@
Host channel re-<span class="grame"><span style="font-family: "Verdana",sans-serif;">activation</span></span></span><span style=""><o:p></o:p></span></li>
</ul>
</ul>
- <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.3.1
+ <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.3.1
@@ -7945,7 +7965,7 @@
software trigger <span class="grame"><span style="font-family: "Verdana",sans-serif;">configuration</span></span></span><span style=""><o:p></o:p></span></li>
</ul>
</ul>
- <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.3.0
+ <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.3.0
@@ -8846,7 +8866,7 @@
Sensing B activation</span><span style=""><o:p></o:p></span></li>
</ul>
</ul>
- <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.2.0
+ <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.2.0
@@ -10476,7 +10496,7 @@
</ul>
</ul>
</ul>
- <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.1.0
+ <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.1.0
@@ -11393,7 +11413,7 @@
Wake</span><span style=""><o:p></o:p></span></li>
</ul>
</ul>
- <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.0.0
+ <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt;"><font color="#ffffff"><span style="font-size: 10pt; font-family: "Arial",sans-serif;">V1.0.0
@@ -11418,7 +11438,7 @@
</tr>
<tr style="">
<td style="padding: 0in; width: 843.25pt;" valign="top" width="1124">
- <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"><span style="font-size: 12pt;"><o:p> </o:p></span></h2>
+ <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><span style="font-size: 12pt;"><o:p> </o:p></span></h2>
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diff --git a/Src/stm32f4xx_hal.c b/Src/stm32f4xx_hal.c
index cb652b8..9ba2ba7 100644
--- a/Src/stm32f4xx_hal.c
+++ b/Src/stm32f4xx_hal.c
@@ -50,11 +50,11 @@
* @{
*/
/**
- * @brief STM32F4xx HAL Driver version number V1.8.0
+ * @brief STM32F4xx HAL Driver version number V1.8.1
*/
#define __STM32F4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32F4xx_HAL_VERSION_SUB1 (0x08U) /*!< [23:16] sub1 version */
-#define __STM32F4xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
+#define __STM32F4xx_HAL_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
#define __STM32F4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F4xx_HAL_VERSION ((__STM32F4xx_HAL_VERSION_MAIN << 24U)\
|(__STM32F4xx_HAL_VERSION_SUB1 << 16U)\
diff --git a/Src/stm32f4xx_hal_eth.c b/Src/stm32f4xx_hal_eth.c
index 37d551b..50d95b8 100644
--- a/Src/stm32f4xx_hal_eth.c
+++ b/Src/stm32f4xx_hal_eth.c
@@ -194,44 +194,44 @@
/** @addtogroup ETH_Private_Constants ETH Private Constants
* @{
*/
-#define ETH_MACCR_MASK ((uint32_t)0xFFFB7F7CU)
-#define ETH_MACECR_MASK ((uint32_t)0x3F077FFFU)
-#define ETH_MACFFR_MASK ((uint32_t)0x800007FFU)
-#define ETH_MACWTR_MASK ((uint32_t)0x0000010FU)
-#define ETH_MACTFCR_MASK ((uint32_t)0xFFFF00F2U)
-#define ETH_MACRFCR_MASK ((uint32_t)0x00000003U)
-#define ETH_MTLTQOMR_MASK ((uint32_t)0x00000072U)
-#define ETH_MTLRQOMR_MASK ((uint32_t)0x0000007BU)
-
-#define ETH_DMAMR_MASK ((uint32_t)0x00007802U)
-#define ETH_DMASBMR_MASK ((uint32_t)0x0000D001U)
-#define ETH_DMACCR_MASK ((uint32_t)0x00013FFFU)
-#define ETH_DMACTCR_MASK ((uint32_t)0x003F1010U)
-#define ETH_DMACRCR_MASK ((uint32_t)0x803F0000U)
-#define ETH_MACPMTCSR_MASK (ETH_MACPMTCSR_PD | ETH_MACPMTCSR_WFE | \
- ETH_MACPMTCSR_MPE | ETH_MACPMTCSR_GU)
+#define ETH_MACCR_MASK 0xFFFB7F7CU
+#define ETH_MACECR_MASK 0x3F077FFFU
+#define ETH_MACFFR_MASK 0x800007FFU
+#define ETH_MACWTR_MASK 0x0000010FU
+#define ETH_MACTFCR_MASK 0xFFFF00F2U
+#define ETH_MACRFCR_MASK 0x00000003U
+#define ETH_MTLTQOMR_MASK 0x00000072U
+#define ETH_MTLRQOMR_MASK 0x0000007BU
+
+#define ETH_DMAMR_MASK 0x00007802U
+#define ETH_DMASBMR_MASK 0x0000D001U
+#define ETH_DMACCR_MASK 0x00013FFFU
+#define ETH_DMACTCR_MASK 0x003F1010U
+#define ETH_DMACRCR_MASK 0x803F0000U
+#define ETH_MACPMTCSR_MASK (ETH_MACPMTCSR_PD | ETH_MACPMTCSR_WFE | \
+ ETH_MACPMTCSR_MPE | ETH_MACPMTCSR_GU)
/* Timeout values */
-#define ETH_SWRESET_TIMEOUT ((uint32_t)500U)
-#define ETH_MDIO_BUS_TIMEOUT ((uint32_t)1000U)
+#define ETH_SWRESET_TIMEOUT 500U
+#define ETH_MDIO_BUS_TIMEOUT 1000U
#define ETH_DMARXDESC_ERRORS_MASK ((uint32_t)(ETH_DMARXDESC_DBE | ETH_DMARXDESC_RE | \
ETH_DMARXDESC_OE | ETH_DMARXDESC_RWT |\
ETH_DMARXDESC_LC | ETH_DMARXDESC_CE |\
ETH_DMARXDESC_DE | ETH_DMARXDESC_IPV4HCE))
-#define ETH_MAC_US_TICK ((uint32_t)1000000U)
+#define ETH_MAC_US_TICK 1000000U
-#define ETH_MACTSCR_MASK ((uint32_t)0x0087FF2FU)
+#define ETH_MACTSCR_MASK 0x0087FF2FU
-#define ETH_PTPTSHR_VALUE ((uint32_t)0xFFFFFFFFU)
-#define ETH_PTPTSLR_VALUE ((uint32_t)0xBB9ACA00U)
+#define ETH_PTPTSHR_VALUE 0xFFFFFFFFU
+#define ETH_PTPTSLR_VALUE 0xBB9ACA00U
/* Ethernet MACMIIAR register Mask */
-#define ETH_MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3U)
+#define ETH_MACMIIAR_CR_MASK 0xFFFFFFE3U
/* Delay to wait when writing to some Ethernet registers */
-#define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001U)
+#define ETH_REG_WRITE_DELAY 0x00000001U
/* ETHERNET MACCR register Mask */
#define ETH_MACCR_CLEAR_MASK 0xFF20810FU
@@ -243,8 +243,8 @@
#define ETH_DMAOMR_CLEAR_MASK 0xF8DE3F23U
/* ETHERNET MAC address offsets */
-#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + 0x40U) /* ETHERNET MAC address high offset */
-#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + 0x44U) /* ETHERNET MAC address low offset */
+#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + 0x40U) /* ETHERNET MAC address high offset */
+#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + 0x44U) /* ETHERNET MAC address low offset */
/* ETHERNET DMA Rx descriptors Frame length Shift */
#define ETH_DMARXDESC_FRAMELENGTHSHIFT 16U
@@ -1229,11 +1229,6 @@
if (allocStatus != 0U)
{
- /* Ensure rest of descriptor is written to RAM before the OWN bit */
- __DMB();
-
- WRITE_REG(dmarxdesc->DESC0, ETH_DMARXDESC_OWN);
-
if (heth->RxDescList.ItMode == 0U)
{
WRITE_REG(dmarxdesc->DESC1, ETH_DMARXDESC_DIC | ETH_RX_BUF_SIZE | ETH_DMARXDESC_RCH);
@@ -1243,6 +1238,14 @@
WRITE_REG(dmarxdesc->DESC1, ETH_RX_BUF_SIZE | ETH_DMARXDESC_RCH);
}
+ /* Before transferring the ownership to DMA, make sure that the RX descriptors bits writing
+ is fully performed.
+ The __DMB() instruction is added to avoid any potential compiler optimization that
+ may lead to abnormal behavior. */
+ __DMB();
+
+ SET_BIT(dmarxdesc->DESC0, ETH_DMARXDESC_OWN);
+
/* Increment current rx descriptor index */
INCR_RX_DESC_INDEX(descidx, 1U);
/* Get current descriptor address */
diff --git a/Src/stm32f4xx_hal_rtc.c b/Src/stm32f4xx_hal_rtc.c
index f4d5dbc..2d2be66 100644
--- a/Src/stm32f4xx_hal_rtc.c
+++ b/Src/stm32f4xx_hal_rtc.c
@@ -306,50 +306,38 @@
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_BUSY;
- /* Check whether the calendar needs to be initialized */
- if (__HAL_RTC_IS_CALENDAR_INITIALIZED(hrtc) == 0U)
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Enter Initialization mode */
+ status = RTC_EnterInitMode(hrtc);
+
+ if (status == HAL_OK)
{
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+ /* Clear RTC_CR FMT, OSEL and POL Bits */
+ hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL));
+ /* Set RTC_CR register */
+ hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
- /* Enter Initialization mode */
- status = RTC_EnterInitMode(hrtc);
+ /* Configure the RTC PRER */
+ hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv);
+ hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos);
- if (status == HAL_OK)
- {
- /* Clear RTC_CR FMT, OSEL and POL Bits */
- hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL));
- /* Set RTC_CR register */
- hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
-
- /* Configure the RTC PRER */
- hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv);
- hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos);
-
- /* Exit Initialization mode */
- status = RTC_ExitInitMode(hrtc);
- }
-
- if (status == HAL_OK)
- {
- hrtc->Instance->TAFCR &= (uint32_t)~RTC_OUTPUT_TYPE_PUSHPULL;
- hrtc->Instance->TAFCR |= (uint32_t)(hrtc->Init.OutPutType);
- }
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
- }
- else
- {
- /* The calendar is already initialized */
- status = HAL_OK;
+ /* Exit Initialization mode */
+ status = RTC_ExitInitMode(hrtc);
}
if (status == HAL_OK)
{
+ hrtc->Instance->TAFCR &= (uint32_t)~RTC_OUTPUT_TYPE_PUSHPULL;
+ hrtc->Instance->TAFCR |= (uint32_t)(hrtc->Init.OutPutType);
+
hrtc->State = HAL_RTC_STATE_READY;
}
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
return status;
}
