commit 957b10c803f2f41fbe87c7929dfcde348067d41a
author Eya <aya.selmi1@st.com> Mon Sep 26 17:46:22 2022 +0100
committer Eya <aya.selmi1@st.com> Tue Sep 27 16:06:15 2022 +0100
tree eec9071f73c20468c963f57dd1e88ec8e0267906
parent 7a104e387d043e7385893c3f1d9ffc5262f39b43

[HAL][SMBUS] Update to fix issue of mismatched data received by master in case of data size to be transmitted by the slave is greater than the data size to be received by the master and add flush on TX register

Src/stm32f4xx_hal_smbus.c

diff --git a/Src/stm32f4xx_hal_smbus.c b/Src/stm32f4xx_hal_smbus.c
index 25c72fd..58622e4 100644
--- a/Src/stm32f4xx_hal_smbus.c
+++ b/Src/stm32f4xx_hal_smbus.c
@@ -213,6 +213,7 @@
 
 static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
 static void SMBUS_ITError(SMBUS_HandleTypeDef *hsmbus);
+static void SMBUS_Flush_DR(SMBUS_HandleTypeDef *hsmbus);
 
 /* Private functions for SMBUS transfer IRQ handler */
 static HAL_StatusTypeDef SMBUS_MasterTransmit_TXE(SMBUS_HandleTypeDef *hsmbus);
@@ -846,6 +847,18 @@
 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
 
 /**
+  * @brief  SMBUS data register flush process.
+  * @param  hsmbus SMBUS handle.
+  * @retval None
+  */
+static void SMBUS_Flush_DR(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* Write a dummy data in DR to clear it */
+  hsmbus->Instance->DR = 0x00U;
+
+}
+
+/**
   * @}
   */
 
@@ -1680,6 +1693,13 @@
 
       /* Clear AF flag */
       __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
+
+      /* Disable EVT, BUF and ERR interrupt */
+      __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_EVT | SMBUS_IT_BUF | SMBUS_IT_ERR);
+
+      /* Flush data register */
+      SMBUS_Flush_DR(hsmbus);
+
     }
   }