commit de395d01c05000c70893d215cfdb5ae7ca5659c9
author houssine BOUGUERBA <houssine.bougerba-ext@st.com> Tue Jun 06 11:18:20 2023 +0100
committer houssine BOUGUERBA <houssine.bougerba-ext@st.com> Tue Jun 06 11:34:02 2023 +0100
tree 17449e5c33c84675dc9ddc9b0c65a716307c1491
parent 8b8d8ba2ea9fc9ef110b48b51b03f4cc404f9954

[HAL][SPI] Update IT API to enable interrupts after process unlock

Src/stm32f4xx_hal_spi.c

diff --git a/Src/stm32f4xx_hal_spi.c b/Src/stm32f4xx_hal_spi.c
index 50f5cfe..416b1ec 100644
--- a/Src/stm32f4xx_hal_spi.c
+++ b/Src/stm32f4xx_hal_spi.c
@@ -1380,8 +1380,6 @@
   /* Check Direction parameter */
   assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
 
-  /* Process Locked */
-  __HAL_LOCK(hspi);
 
   if ((pData == NULL) || (Size == 0U))
   {
@@ -1395,6 +1393,9 @@
     goto error;
   }
 
+  /* Process Locked */
+  __HAL_LOCK(hspi);
+
   /* Set the transaction information */
   hspi->State       = HAL_SPI_STATE_BUSY_TX;
   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
@@ -1434,10 +1435,6 @@
   }
 #endif /* USE_SPI_CRC */
 
-  /* Enable TXE and ERR interrupt */
-  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
-
-
   /* Check if the SPI is already enabled */
   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
   {
@@ -1445,8 +1442,12 @@
     __HAL_SPI_ENABLE(hspi);
   }
 
-error :
+  /* Process Unlocked */
   __HAL_UNLOCK(hspi);
+  /* Enable TXE and ERR interrupt */
+  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
+
+error :
   return errorcode;
 }
 
@@ -1476,8 +1477,6 @@
     return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
   }
 
-  /* Process Locked */
-  __HAL_LOCK(hspi);
 
   if ((pData == NULL) || (Size == 0U))
   {
@@ -1485,6 +1484,9 @@
     goto error;
   }
 
+  /* Process Locked */
+  __HAL_LOCK(hspi);
+
   /* Set the transaction information */
   hspi->State       = HAL_SPI_STATE_BUSY_RX;
   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
@@ -1524,9 +1526,6 @@
   }
 #endif /* USE_SPI_CRC */
 
-  /* Enable TXE and ERR interrupt */
-  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
   /* Note : The SPI must be enabled after unlocking current process
             to avoid the risk of SPI interrupt handle execution before current
             process unlock */
@@ -1538,9 +1537,12 @@
     __HAL_SPI_ENABLE(hspi);
   }
 
-error :
   /* Process Unlocked */
   __HAL_UNLOCK(hspi);
+  /* Enable RXNE and ERR interrupt */
+  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+error :
   return errorcode;
 }
 
@@ -1562,9 +1564,6 @@
   /* Check Direction parameter */
   assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
 
-  /* Process locked */
-  __HAL_LOCK(hspi);
-
   /* Init temporary variables */
   tmp_state           = hspi->State;
   tmp_mode            = hspi->Init.Mode;
@@ -1582,6 +1581,9 @@
     goto error;
   }
 
+  /* Process locked */
+  __HAL_LOCK(hspi);
+
   /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
   if (hspi->State != HAL_SPI_STATE_BUSY_RX)
   {
@@ -1617,8 +1619,6 @@
   }
 #endif /* USE_SPI_CRC */
 
-  /* Enable TXE, RXNE and ERR interrupt */
-  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
 
   /* Check if the SPI is already enabled */
   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
@@ -1627,9 +1627,12 @@
     __HAL_SPI_ENABLE(hspi);
   }
 
-error :
   /* Process Unlocked */
   __HAL_UNLOCK(hspi);
+  /* Enable TXE, RXNE and ERR interrupt */
+  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
+
+error :
   return errorcode;
 }
 
@@ -1754,13 +1757,13 @@
 
   /* Check rx dma handle */
   assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
-  
+
   if (hspi->State != HAL_SPI_STATE_READY)
   {
     errorcode = HAL_BUSY;
     goto error;
   }
-  
+
   if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
   {
     hspi->State = HAL_SPI_STATE_BUSY_RX;