| /** |
| ****************************************************************************** |
| * @file stm32f7xx_hal_rcc.h |
| * @author MCD Application Team |
| * @brief Header file of RCC HAL module. |
| ****************************************************************************** |
| * @attention |
| * |
| * Copyright (c) 2017 STMicroelectronics. |
| * All rights reserved. |
| * |
| * This software is licensed under terms that can be found in the LICENSE file in |
| * the root directory of this software component. |
| * If no LICENSE file comes with this software, it is provided AS-IS. |
| ****************************************************************************** |
| */ |
| |
| /* Define to prevent recursive inclusion -------------------------------------*/ |
| #ifndef __STM32F7xx_HAL_RCC_H |
| #define __STM32F7xx_HAL_RCC_H |
| |
| #ifdef __cplusplus |
| extern "C" { |
| #endif |
| |
| /* Includes ------------------------------------------------------------------*/ |
| #include "stm32f7xx_hal_def.h" |
| |
| /* Include RCC HAL Extended module */ |
| /* (include on top of file since RCC structures are defined in extended file) */ |
| #include "stm32f7xx_hal_rcc_ex.h" |
| |
| /** @addtogroup STM32F7xx_HAL_Driver |
| * @{ |
| */ |
| |
| /** @addtogroup RCC |
| * @{ |
| */ |
| |
| /* Exported types ------------------------------------------------------------*/ |
| |
| /** @defgroup RCC_Exported_Types RCC Exported Types |
| * @{ |
| */ |
| |
| /** |
| * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition |
| */ |
| typedef struct |
| { |
| uint32_t OscillatorType; /*!< The oscillators to be configured. |
| This parameter can be a value of @ref RCC_Oscillator_Type */ |
| |
| uint32_t HSEState; /*!< The new state of the HSE. |
| This parameter can be a value of @ref RCC_HSE_Config */ |
| |
| uint32_t LSEState; /*!< The new state of the LSE. |
| This parameter can be a value of @ref RCC_LSE_Config */ |
| |
| uint32_t HSIState; /*!< The new state of the HSI. |
| This parameter can be a value of @ref RCC_HSI_Config */ |
| |
| uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). |
| This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ |
| |
| uint32_t LSIState; /*!< The new state of the LSI. |
| This parameter can be a value of @ref RCC_LSI_Config */ |
| |
| RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ |
| |
| }RCC_OscInitTypeDef; |
| |
| /** |
| * @brief RCC System, AHB and APB buses clock configuration structure definition |
| */ |
| typedef struct |
| { |
| uint32_t ClockType; /*!< The clock to be configured. |
| This parameter can be a value of @ref RCC_System_Clock_Type */ |
| |
| uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. |
| This parameter can be a value of @ref RCC_System_Clock_Source */ |
| |
| uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). |
| This parameter can be a value of @ref RCC_AHB_Clock_Source */ |
| |
| uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). |
| This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ |
| |
| uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). |
| This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ |
| |
| }RCC_ClkInitTypeDef; |
| |
| /** |
| * @} |
| */ |
| |
| /* Exported constants --------------------------------------------------------*/ |
| /** @defgroup RCC_Exported_Constants RCC Exported Constants |
| * @{ |
| */ |
| |
| /** @defgroup RCC_Oscillator_Type Oscillator Type |
| * @{ |
| */ |
| #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000U) |
| #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001U) |
| #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002U) |
| #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004U) |
| #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008U) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_HSE_Config RCC HSE Config |
| * @{ |
| */ |
| #define RCC_HSE_OFF ((uint32_t)0x00000000U) |
| #define RCC_HSE_ON RCC_CR_HSEON |
| #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_LSE_Config RCC LSE Config |
| * @{ |
| */ |
| #define RCC_LSE_OFF ((uint32_t)0x00000000U) |
| #define RCC_LSE_ON RCC_BDCR_LSEON |
| #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_HSI_Config RCC HSI Config |
| * @{ |
| */ |
| #define RCC_HSI_OFF ((uint32_t)0x00000000U) |
| #define RCC_HSI_ON RCC_CR_HSION |
| |
| #define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10U) /* Default HSI calibration trimming value */ |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_LSI_Config RCC LSI Config |
| * @{ |
| */ |
| #define RCC_LSI_OFF ((uint32_t)0x00000000U) |
| #define RCC_LSI_ON RCC_CSR_LSION |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_PLL_Config RCC PLL Config |
| * @{ |
| */ |
| #define RCC_PLL_NONE ((uint32_t)0x00000000U) |
| #define RCC_PLL_OFF ((uint32_t)0x00000001U) |
| #define RCC_PLL_ON ((uint32_t)0x00000002U) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider |
| * @{ |
| */ |
| #define RCC_PLLP_DIV2 ((uint32_t)0x00000002U) |
| #define RCC_PLLP_DIV4 ((uint32_t)0x00000004U) |
| #define RCC_PLLP_DIV6 ((uint32_t)0x00000006U) |
| #define RCC_PLLP_DIV8 ((uint32_t)0x00000008U) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_PLL_Clock_Source PLL Clock Source |
| * @{ |
| */ |
| #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI |
| #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_System_Clock_Type RCC System Clock Type |
| * @{ |
| */ |
| #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001U) |
| #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002U) |
| #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004U) |
| #define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008U) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_System_Clock_Source RCC System Clock Source |
| * @{ |
| */ |
| #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI |
| #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE |
| #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL |
| /** |
| * @} |
| */ |
| |
| |
| /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status |
| * @{ |
| */ |
| #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ |
| #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ |
| #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source |
| * @{ |
| */ |
| #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 |
| #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 |
| #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 |
| #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 |
| #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 |
| #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 |
| #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 |
| #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 |
| #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1/APB2 Clock Source |
| * @{ |
| */ |
| #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 |
| #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 |
| #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 |
| #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 |
| #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source |
| * @{ |
| */ |
| #define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000U) |
| #define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100U) |
| #define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200U) |
| #define RCC_RTCCLKSOURCE_HSE_DIVX ((uint32_t)0x00000300U) |
| #define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300U) |
| #define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300U) |
| #define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300U) |
| #define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300U) |
| #define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300U) |
| #define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300U) |
| #define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300U) |
| #define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300U) |
| #define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300U) |
| #define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300U) |
| #define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300U) |
| #define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300U) |
| #define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300U) |
| #define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300U) |
| #define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300U) |
| #define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300U) |
| #define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300U) |
| #define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300U) |
| #define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300U) |
| #define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300U) |
| #define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300U) |
| #define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300U) |
| #define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300U) |
| #define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300U) |
| #define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300U) |
| #define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300U) |
| #define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300U) |
| #define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300U) |
| #define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300U) |
| #define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300U) |
| /** |
| * @} |
| */ |
| |
| |
| |
| /** @defgroup RCC_MCO_Index RCC MCO Index |
| * @{ |
| */ |
| #define RCC_MCO1 ((uint32_t)0x00000000U) |
| #define RCC_MCO2 ((uint32_t)0x00000001U) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source |
| * @{ |
| */ |
| #define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000U) |
| #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0 |
| #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1 |
| #define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1 |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_MCO2_Clock_Source RCC MCO2 Clock Source |
| * @{ |
| */ |
| #define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000U) |
| #define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0 |
| #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1 |
| #define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2 |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_MCOx_Clock_Prescaler RCC MCO1 Clock Prescaler |
| * @{ |
| */ |
| #define RCC_MCODIV_1 ((uint32_t)0x00000000U) |
| #define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2 |
| #define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2) |
| #define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2) |
| #define RCC_MCODIV_5 RCC_CFGR_MCO1PRE |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_Interrupt RCC Interrupt |
| * @{ |
| */ |
| #define RCC_IT_LSIRDY ((uint8_t)0x01U) |
| #define RCC_IT_LSERDY ((uint8_t)0x02U) |
| #define RCC_IT_HSIRDY ((uint8_t)0x04U) |
| #define RCC_IT_HSERDY ((uint8_t)0x08U) |
| #define RCC_IT_PLLRDY ((uint8_t)0x10U) |
| #define RCC_IT_PLLI2SRDY ((uint8_t)0x20U) |
| #define RCC_IT_PLLSAIRDY ((uint8_t)0x40U) |
| #define RCC_IT_CSS ((uint8_t)0x80U) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_Flag RCC Flags |
| * Elements values convention: 0XXYYYYYb |
| * - YYYYY : Flag position in the register |
| * - 0XX : Register index |
| * - 01: CR register |
| * - 10: BDCR register |
| * - 11: CSR register |
| * @{ |
| */ |
| /* Flags in the CR register */ |
| #define RCC_FLAG_HSIRDY ((uint8_t)0x21U) |
| #define RCC_FLAG_HSERDY ((uint8_t)0x31U) |
| #define RCC_FLAG_PLLRDY ((uint8_t)0x39U) |
| #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3BU) |
| #define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3CU) |
| |
| /* Flags in the BDCR register */ |
| #define RCC_FLAG_LSERDY ((uint8_t)0x41U) |
| |
| /* Flags in the CSR register */ |
| #define RCC_FLAG_LSIRDY ((uint8_t)0x61U) |
| #define RCC_FLAG_BORRST ((uint8_t)0x79U) |
| #define RCC_FLAG_PINRST ((uint8_t)0x7AU) |
| #define RCC_FLAG_PORRST ((uint8_t)0x7BU) |
| #define RCC_FLAG_SFTRST ((uint8_t)0x7CU) |
| #define RCC_FLAG_IWDGRST ((uint8_t)0x7DU) |
| #define RCC_FLAG_WWDGRST ((uint8_t)0x7EU) |
| #define RCC_FLAG_LPWRRST ((uint8_t)0x7FU) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_LSEDrive_Configuration RCC LSE Drive configurations |
| * @{ |
| */ |
| #define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U) |
| #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 |
| #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 |
| #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV |
| /** |
| * @} |
| */ |
| |
| /** |
| * @} |
| */ |
| |
| /* Exported macro ------------------------------------------------------------*/ |
| /** @defgroup RCC_Exported_Macros RCC Exported Macros |
| * @{ |
| */ |
| |
| /** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable |
| * @brief Enable or disable the AHB1 peripheral clock. |
| * @note After reset, the peripheral clock (used for registers read/write access) |
| * is disabled and the application software has to enable this clock before |
| * using it. |
| * @{ |
| */ |
| #define __HAL_RCC_CRC_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg; \ |
| SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ |
| UNUSED(tmpreg); \ |
| } while(0) |
| |
| #define __HAL_RCC_DMA1_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg; \ |
| SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ |
| UNUSED(tmpreg); \ |
| } while(0) |
| |
| #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) |
| #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN)) |
| |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable |
| * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. |
| * @note After reset, the peripheral clock (used for registers read/write access) |
| * is disabled and the application software has to enable this clock before |
| * using it. |
| * @{ |
| */ |
| #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg; \ |
| SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ |
| UNUSED(tmpreg); \ |
| } while(0) |
| |
| #define __HAL_RCC_PWR_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg; \ |
| SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ |
| UNUSED(tmpreg); \ |
| } while(0) |
| |
| #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) |
| #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable |
| * @brief Enable or disable the High Speed APB (APB2) peripheral clock. |
| * @note After reset, the peripheral clock (used for registers read/write access) |
| * is disabled and the application software has to enable this clock before |
| * using it. |
| * @{ |
| */ |
| #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ |
| __IO uint32_t tmpreg; \ |
| SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ |
| /* Delay after an RCC peripheral clock enabling */ \ |
| tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ |
| UNUSED(tmpreg); \ |
| } while(0) |
| |
| #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)) |
| |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status |
| * @brief Get the enable or disable status of the AHB1 peripheral clock. |
| * @note After reset, the peripheral clock (used for registers read/write access) |
| * is disabled and the application software has to enable this clock before |
| * using it. |
| * @{ |
| */ |
| #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) |
| #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) != RESET) |
| |
| #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) |
| #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) == RESET) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status |
| * @brief Get the enable or disable status of the APB1 peripheral clock. |
| * @note After reset, the peripheral clock (used for registers read/write access) |
| * is disabled and the application software has to enable this clock before |
| * using it. |
| * @{ |
| */ |
| #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET) |
| #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET) |
| |
| #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET) |
| #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status |
| * @brief EGet the enable or disable status of the APB2 peripheral clock. |
| * @note After reset, the peripheral clock (used for registers read/write access) |
| * is disabled and the application software has to enable this clock before |
| * using it. |
| * @{ |
| */ |
| #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET) |
| #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_Peripheral_Clock_Force_Release RCC Peripheral Clock Force Release |
| * @brief Force or release AHB peripheral reset. |
| * @{ |
| */ |
| #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU) |
| #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) |
| #define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST)) |
| |
| #define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U) |
| #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) |
| #define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST)) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset |
| * @brief Force or release APB1 peripheral reset. |
| * @{ |
| */ |
| #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) |
| #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) |
| #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) |
| |
| #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U) |
| #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) |
| #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset |
| * @brief Force or release APB2 peripheral reset. |
| * @{ |
| */ |
| #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) |
| #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST)) |
| |
| #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U) |
| #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST)) |
| |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_Peripheral_Clock_Sleep_Enable_Disable RCC Peripheral Clock Sleep Enable Disable |
| * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| * power consumption. |
| * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
| * @note By default, all peripheral clocks are enabled during SLEEP mode. |
| * @{ |
| */ |
| #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) |
| #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN)) |
| |
| #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) |
| #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN)) |
| |
| /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. |
| * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| * power consumption. |
| * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
| * @note By default, all peripheral clocks are enabled during SLEEP mode. |
| */ |
| #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN)) |
| #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN)) |
| |
| #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN)) |
| #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN)) |
| |
| /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. |
| * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| * power consumption. |
| * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
| * @note By default, all peripheral clocks are enabled during SLEEP mode. |
| */ |
| #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN)) |
| #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN)) |
| |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enable Disable Status |
| * @brief Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode. |
| * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| * power consumption. |
| * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
| * @note By default, all peripheral clocks are enabled during SLEEP mode. |
| * @{ |
| */ |
| #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) != RESET) |
| #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) != RESET) |
| |
| #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) == RESET) |
| #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) == RESET) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enable Disable Status |
| * @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode. |
| * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| * power consumption. |
| * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
| * @note By default, all peripheral clocks are enabled during SLEEP mode. |
| * @{ |
| */ |
| #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) != RESET) |
| #define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) != RESET) |
| |
| #define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) == RESET) |
| #define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) == RESET) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enable Disable Status |
| * @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode. |
| * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| * power consumption. |
| * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
| * @note By default, all peripheral clocks are enabled during SLEEP mode. |
| * @{ |
| */ |
| #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) != RESET) |
| #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) == RESET) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_HSI_Configuration HSI Configuration |
| * @{ |
| */ |
| |
| /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). |
| * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. |
| * It is used (enabled by hardware) as system clock source after startup |
| * from Reset, wakeup from STOP and STANDBY mode, or in case of failure |
| * of the HSE used directly or indirectly as system clock (if the Clock |
| * Security System CSS is enabled). |
| * @note HSI can not be stopped if it is used as system clock source. In this case, |
| * you have to select another source of the system clock then stop the HSI. |
| * @note After enabling the HSI, the application software should wait on HSIRDY |
| * flag to be set indicating that HSI clock is stable and can be used as |
| * system clock source. |
| * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator |
| * clock cycles. |
| */ |
| #define __HAL_RCC_HSI_ENABLE() (RCC->CR |= (RCC_CR_HSION)) |
| #define __HAL_RCC_HSI_DISABLE() (RCC->CR &= ~(RCC_CR_HSION)) |
| |
| /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. |
| * @note The calibration is used to compensate for the variations in voltage |
| * and temperature that influence the frequency of the internal HSI RC. |
| * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value. |
| * (default is RCC_HSICALIBRATION_DEFAULT). |
| */ |
| #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) (MODIFY_REG(RCC->CR,\ |
| RCC_CR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_CR_HSITRIM_Pos)) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_LSI_Configuration LSI Configuration |
| * @{ |
| */ |
| |
| /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). |
| * @note After enabling the LSI, the application software should wait on |
| * LSIRDY flag to be set indicating that LSI clock is stable and can |
| * be used to clock the IWDG and/or the RTC. |
| * @note LSI can not be disabled if the IWDG is running. |
| * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator |
| * clock cycles. |
| */ |
| #define __HAL_RCC_LSI_ENABLE() (RCC->CSR |= (RCC_CSR_LSION)) |
| #define __HAL_RCC_LSI_DISABLE() (RCC->CSR &= ~(RCC_CSR_LSION)) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_HSE_Configuration HSE Configuration |
| * @{ |
| */ |
| /** |
| * @brief Macro to configure the External High Speed oscillator (HSE). |
| * @note Transitions HSE Bypass to HSE On and HSE On to HSE Bypass are not |
| * supported by this macro. User should request a transition to HSE Off |
| * first and then HSE On or HSE Bypass. |
| * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application |
| * software should wait on HSERDY flag to be set indicating that HSE clock |
| * is stable and can be used to clock the PLL and/or system clock. |
| * @note HSE state can not be changed if it is used directly or through the |
| * PLL as system clock. In this case, you have to select another source |
| * of the system clock then change the HSE state (ex. disable it). |
| * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. |
| * @note This function reset the CSSON bit, so if the clock security system(CSS) |
| * was previously enabled you have to enable it again after calling this |
| * function. |
| * @param __STATE__ specifies the new state of the HSE. |
| * This parameter can be one of the following values: |
| * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after |
| * 6 HSE oscillator clock cycles. |
| * @arg RCC_HSE_ON: turn ON the HSE oscillator. |
| * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock. |
| */ |
| #define __HAL_RCC_HSE_CONFIG(__STATE__) \ |
| do { \ |
| if ((__STATE__) == RCC_HSE_ON) \ |
| { \ |
| SET_BIT(RCC->CR, RCC_CR_HSEON); \ |
| } \ |
| else if ((__STATE__) == RCC_HSE_OFF) \ |
| { \ |
| CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ |
| CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ |
| } \ |
| else if ((__STATE__) == RCC_HSE_BYPASS) \ |
| { \ |
| SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ |
| SET_BIT(RCC->CR, RCC_CR_HSEON); \ |
| } \ |
| else \ |
| { \ |
| CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ |
| CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ |
| } \ |
| } while(0) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_LSE_Configuration LSE Configuration |
| * @{ |
| */ |
| |
| /** |
| * @brief Macro to configure the External Low Speed oscillator (LSE). |
| * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. |
| * User should request a transition to LSE Off first and then LSE On or LSE Bypass. |
| * @note As the LSE is in the Backup domain and write access is denied to |
| * this domain after reset, you have to enable write access using |
| * HAL_PWR_EnableBkUpAccess() function before to configure the LSE |
| * (to be done once after reset). |
| * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application |
| * software should wait on LSERDY flag to be set indicating that LSE clock |
| * is stable and can be used to clock the RTC. |
| * @param __STATE__ specifies the new state of the LSE. |
| * This parameter can be one of the following values: |
| * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after |
| * 6 LSE oscillator clock cycles. |
| * @arg RCC_LSE_ON: turn ON the LSE oscillator. |
| * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock. |
| */ |
| #define __HAL_RCC_LSE_CONFIG(__STATE__) \ |
| do { \ |
| if((__STATE__) == RCC_LSE_ON) \ |
| { \ |
| SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ |
| } \ |
| else if((__STATE__) == RCC_LSE_OFF) \ |
| { \ |
| CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ |
| CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ |
| } \ |
| else if((__STATE__) == RCC_LSE_BYPASS) \ |
| { \ |
| SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ |
| SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ |
| } \ |
| else \ |
| { \ |
| CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ |
| CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ |
| } \ |
| } while(0) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration |
| * @{ |
| */ |
| |
| /** @brief Macros to enable or disable the RTC clock. |
| * @note These macros must be used only after the RTC clock source was selected. |
| */ |
| #define __HAL_RCC_RTC_ENABLE() (RCC->BDCR |= (RCC_BDCR_RTCEN)) |
| #define __HAL_RCC_RTC_DISABLE() (RCC->BDCR &= ~(RCC_BDCR_RTCEN)) |
| |
| /** @brief Macros to configure the RTC clock (RTCCLK). |
| * @note As the RTC clock configuration bits are in the Backup domain and write |
| * access is denied to this domain after reset, you have to enable write |
| * access using the Power Backup Access macro before to configure |
| * the RTC clock source (to be done once after reset). |
| * @note Once the RTC clock is configured it can't be changed unless the |
| * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by |
| * a Power On Reset (POR). |
| * @param __RTCCLKSource__ specifies the RTC clock source. |
| * This parameter can be one of the following values: |
| @arg @ref RCC_RTCCLKSOURCE_NO_CLK: No clock selected as RTC clock. |
| * @arg @ref RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock. |
| * @arg @ref RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock. |
| * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected |
| * as RTC clock, where x:[2,31] |
| * @note If the LSE or LSI is used as RTC clock source, the RTC continues to |
| * work in STOP and STANDBY modes, and can be used as wakeup source. |
| * However, when the HSE clock is used as RTC clock source, the RTC |
| * cannot be used in STOP and STANDBY modes. |
| * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as |
| * RTC clock source). |
| */ |
| #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \ |
| MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) |
| |
| #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \ |
| RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFF); \ |
| } while (0) |
| |
| /** @brief Macro to get the RTC clock source. |
| * @retval The clock source can be one of the following values: |
| * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock |
| * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock |
| * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock |
| * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER() |
| */ |
| #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) |
| |
| /** |
| * @brief Get the RTC and HSE clock divider (RTCPRE). |
| * @retval Returned value can be one of the following values: |
| * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected |
| * as RTC clock, where x:[2,31] |
| */ |
| #define __HAL_RCC_GET_RTC_HSE_PRESCALER() (READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) | RCC_BDCR_RTCSEL) |
| |
| /** @brief Macros to force or release the Backup domain reset. |
| * @note This function resets the RTC peripheral (including the backup registers) |
| * and the RTC clock source selection in RCC_CSR register. |
| * @note The BKPSRAM is not affected by this reset. |
| */ |
| #define __HAL_RCC_BACKUPRESET_FORCE() (RCC->BDCR |= (RCC_BDCR_BDRST)) |
| #define __HAL_RCC_BACKUPRESET_RELEASE() (RCC->BDCR &= ~(RCC_BDCR_BDRST)) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_PLL_Configuration PLL Configuration |
| * @{ |
| */ |
| |
| /** @brief Macros to enable or disable the main PLL. |
| * @note After enabling the main PLL, the application software should wait on |
| * PLLRDY flag to be set indicating that PLL clock is stable and can |
| * be used as system clock source. |
| * @note The main PLL can not be disabled if it is used as system clock source |
| * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. |
| */ |
| #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON) |
| #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON) |
| |
| /** @brief Macro to configure the PLL clock source. |
| * @note This function must be used only when the main PLL is disabled. |
| * @param __PLLSOURCE__ specifies the PLL entry clock source. |
| * This parameter can be one of the following values: |
| * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry |
| * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry |
| * |
| */ |
| #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) |
| |
| /** @brief Macro to configure the PLL multiplication factor. |
| * @note This function must be used only when the main PLL is disabled. |
| * @param __PLLM__ specifies the division factor for PLL VCO input clock |
| * This parameter must be a number between Min_Data = 2 and Max_Data = 63. |
| * @note You have to set the PLLM parameter correctly to ensure that the VCO input |
| * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency |
| * of 2 MHz to limit PLL jitter. |
| * |
| */ |
| #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__)) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_PLL_I2S_Configuration PLL I2S Configuration |
| * @{ |
| */ |
| |
| /** @brief Macro to configure the I2S clock source (I2SCLK). |
| * @note This function must be called before enabling the I2S APB clock. |
| * @param __SOURCE__ specifies the I2S clock source. |
| * This parameter can be one of the following values: |
| * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source. |
| * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin |
| * used as I2S clock source. |
| */ |
| #define __HAL_RCC_I2S_CONFIG(__SOURCE__) do {RCC->CFGR &= ~(RCC_CFGR_I2SSRC); \ |
| RCC->CFGR |= (__SOURCE__); \ |
| }while(0) |
| |
| /** @brief Macros to enable or disable the PLLI2S. |
| * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes. |
| */ |
| #define __HAL_RCC_PLLI2S_ENABLE() (RCC->CR |= (RCC_CR_PLLI2SON)) |
| #define __HAL_RCC_PLLI2S_DISABLE() (RCC->CR &= ~(RCC_CR_PLLI2SON)) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_Get_Clock_source Get Clock source |
| * @{ |
| */ |
| /** |
| * @brief Macro to configure the system clock source. |
| * @param __RCC_SYSCLKSOURCE__ specifies the system clock source. |
| * This parameter can be one of the following values: |
| * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. |
| * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. |
| * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source. |
| */ |
| #define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__)) |
| |
| /** @brief Macro to get the clock source used as system clock. |
| * @retval The clock source used as system clock. The returned value can be one |
| * of the following: |
| * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock. |
| * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock. |
| * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock. |
| */ |
| #define __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR & RCC_CFGR_SWS) |
| |
| /** |
| * @brief Macro to configures the External Low Speed oscillator (LSE) drive capability. |
| * @note As the LSE is in the Backup domain and write access is denied to |
| * this domain after reset, you have to enable write access using |
| * HAL_PWR_EnableBkUpAccess() function before to configure the LSE |
| * (to be done once after reset). |
| * @param __RCC_LSEDRIVE__ specifies the new state of the LSE drive capability. |
| * This parameter can be one of the following values: |
| * @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability. |
| * @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability. |
| * @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability. |
| * @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability. |
| * @retval None |
| */ |
| #define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) \ |
| (MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) )) |
| |
| /** @brief Macro to get the oscillator used as PLL clock source. |
| * @retval The oscillator used as PLL clock source. The returned value can be one |
| * of the following: |
| * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. |
| * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. |
| */ |
| #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC)) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config |
| * @{ |
| */ |
| |
| /** @brief Macro to configure the MCO1 clock. |
| * @param __MCOCLKSOURCE__ specifies the MCO clock source. |
| * This parameter can be one of the following values: |
| * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source |
| * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source |
| * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source |
| * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source |
| * @param __MCODIV__ specifies the MCO clock prescaler. |
| * This parameter can be one of the following values: |
| * @arg RCC_MCODIV_1: no division applied to MCOx clock |
| * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock |
| * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock |
| * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock |
| * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock |
| */ |
| |
| #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ |
| MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) |
| |
| /** @brief Macro to configure the MCO2 clock. |
| * @param __MCOCLKSOURCE__ specifies the MCO clock source. |
| * This parameter can be one of the following values: |
| * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source |
| * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source |
| * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source |
| * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source |
| * @param __MCODIV__ specifies the MCO clock prescaler. |
| * This parameter can be one of the following values: |
| * @arg RCC_MCODIV_1: no division applied to MCOx clock |
| * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock |
| * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock |
| * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock |
| * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock |
| */ |
| |
| #define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ |
| MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3))); |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management |
| * @brief macros to manage the specified RCC Flags and interrupts. |
| * @{ |
| */ |
| |
| /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable |
| * the selected interrupts). |
| * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. |
| * This parameter can be any combination of the following values: |
| * @arg RCC_IT_LSIRDY: LSI ready interrupt. |
| * @arg RCC_IT_LSERDY: LSE ready interrupt. |
| * @arg RCC_IT_HSIRDY: HSI ready interrupt. |
| * @arg RCC_IT_HSERDY: HSE ready interrupt. |
| * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. |
| * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. |
| */ |
| #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) |
| |
| /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable |
| * the selected interrupts). |
| * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. |
| * This parameter can be any combination of the following values: |
| * @arg RCC_IT_LSIRDY: LSI ready interrupt. |
| * @arg RCC_IT_LSERDY: LSE ready interrupt. |
| * @arg RCC_IT_HSIRDY: HSI ready interrupt. |
| * @arg RCC_IT_HSERDY: HSE ready interrupt. |
| * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. |
| * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. |
| */ |
| #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__))) |
| |
| /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] |
| * bits to clear the selected interrupt pending bits. |
| * @param __INTERRUPT__ specifies the interrupt pending bit to clear. |
| * This parameter can be any combination of the following values: |
| * @arg RCC_IT_LSIRDY: LSI ready interrupt. |
| * @arg RCC_IT_LSERDY: LSE ready interrupt. |
| * @arg RCC_IT_HSIRDY: HSI ready interrupt. |
| * @arg RCC_IT_HSERDY: HSE ready interrupt. |
| * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. |
| * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. |
| * @arg RCC_IT_CSS: Clock Security System interrupt |
| */ |
| #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) |
| |
| /** @brief Check the RCC's interrupt has occurred or not. |
| * @param __INTERRUPT__ specifies the RCC interrupt source to check. |
| * This parameter can be one of the following values: |
| * @arg RCC_IT_LSIRDY: LSI ready interrupt. |
| * @arg RCC_IT_LSERDY: LSE ready interrupt. |
| * @arg RCC_IT_HSIRDY: HSI ready interrupt. |
| * @arg RCC_IT_HSERDY: HSE ready interrupt. |
| * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. |
| * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. |
| * @arg RCC_IT_CSS: Clock Security System interrupt |
| * @retval The new state of __INTERRUPT__ (TRUE or FALSE). |
| */ |
| #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) |
| |
| /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, |
| * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. |
| */ |
| #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) |
| |
| /** @brief Check RCC flag is set or not. |
| * @param __FLAG__ specifies the flag to check. |
| * This parameter can be one of the following values: |
| * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready. |
| * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready. |
| * @arg RCC_FLAG_PLLRDY: Main PLL clock ready. |
| * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready. |
| * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready. |
| * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready. |
| * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset. |
| * @arg RCC_FLAG_PINRST: Pin reset. |
| * @arg RCC_FLAG_PORRST: POR/PDR reset. |
| * @arg RCC_FLAG_SFTRST: Software reset. |
| * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset. |
| * @arg RCC_FLAG_WWDGRST: Window Watchdog reset. |
| * @arg RCC_FLAG_LPWRRST: Low Power reset. |
| * @retval The new state of __FLAG__ (TRUE or FALSE). |
| */ |
| #define RCC_FLAG_MASK ((uint8_t)0x1F) |
| #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0) |
| |
| /** |
| * @} |
| */ |
| |
| /** |
| * @} |
| */ |
| |
| /* Include RCC HAL Extension module */ |
| #include "stm32f7xx_hal_rcc_ex.h" |
| |
| /* Exported functions --------------------------------------------------------*/ |
| /** @addtogroup RCC_Exported_Functions |
| * @{ |
| */ |
| |
| /** @addtogroup RCC_Exported_Functions_Group1 |
| * @{ |
| */ |
| /* Initialization and de-initialization functions ******************************/ |
| HAL_StatusTypeDef HAL_RCC_DeInit(void); |
| HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); |
| HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); |
| /** |
| * @} |
| */ |
| |
| /** @addtogroup RCC_Exported_Functions_Group2 |
| * @{ |
| */ |
| /* Peripheral Control functions ************************************************/ |
| void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); |
| void HAL_RCC_EnableCSS(void); |
| void HAL_RCC_DisableCSS(void); |
| uint32_t HAL_RCC_GetSysClockFreq(void); |
| uint32_t HAL_RCC_GetHCLKFreq(void); |
| uint32_t HAL_RCC_GetPCLK1Freq(void); |
| uint32_t HAL_RCC_GetPCLK2Freq(void); |
| void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); |
| void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); |
| |
| /* CSS NMI IRQ handler */ |
| void HAL_RCC_NMI_IRQHandler(void); |
| |
| /* User Callbacks in non blocking mode (IT mode) */ |
| void HAL_RCC_CSSCallback(void); |
| /** |
| * @} |
| */ |
| |
| /** |
| * @} |
| */ |
| |
| /* Private types -------------------------------------------------------------*/ |
| /* Private variables ---------------------------------------------------------*/ |
| /* Private constants ---------------------------------------------------------*/ |
| /** @defgroup RCC_Private_Constants RCC Private Constants |
| * @{ |
| */ |
| #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT |
| #define HSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */ |
| #define LSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */ |
| #define PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */ |
| #define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */ |
| #define PLLI2S_TIMEOUT_VALUE 100U /* Timeout value fixed to 100 ms */ |
| #define PLLSAI_TIMEOUT_VALUE 100U /* Timeout value fixed to 100 ms */ |
| |
| /** @defgroup RCC_BitAddress_Alias RCC BitAddress Alias |
| * @brief RCC registers bit address alias |
| * @{ |
| */ |
| /* CIR register byte 2 (Bits[15:8]) base address */ |
| #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01)) |
| |
| /* CIR register byte 3 (Bits[23:16]) base address */ |
| #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02)) |
| |
| #define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100) |
| #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT |
| /** |
| * @} |
| */ |
| /** |
| * @} |
| */ |
| |
| /* Private macros ------------------------------------------------------------*/ |
| /** @addtogroup RCC_Private_Macros RCC Private Macros |
| * @{ |
| */ |
| |
| /** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters |
| * @{ |
| */ |
| #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15) |
| |
| #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ |
| ((HSE) == RCC_HSE_BYPASS)) |
| |
| #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ |
| ((LSE) == RCC_LSE_BYPASS)) |
| |
| #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON)) |
| |
| #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON)) |
| |
| #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON)) |
| |
| #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \ |
| ((SOURCE) == RCC_PLLSOURCE_HSE)) |
| |
| #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ |
| ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ |
| ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK)) |
| #define IS_RCC_PLLM_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 63)) |
| |
| #define IS_RCC_PLLN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) |
| |
| #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == RCC_PLLP_DIV2) || ((VALUE) == RCC_PLLP_DIV4) || \ |
| ((VALUE) == RCC_PLLP_DIV6) || ((VALUE) == RCC_PLLP_DIV8)) |
| #define IS_RCC_PLLQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) |
| |
| #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \ |
| ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \ |
| ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \ |
| ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \ |
| ((HCLK) == RCC_SYSCLK_DIV512)) |
| |
| #define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15)) |
| |
| #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \ |
| ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \ |
| ((PCLK) == RCC_HCLK_DIV16)) |
| |
| #define IS_RCC_MCO(MCOX) (((MCOX) == RCC_MCO1) || ((MCOX) == RCC_MCO2)) |
| |
| |
| #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ |
| ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK)) |
| |
| #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \ |
| ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK)) |
| |
| #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \ |
| ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \ |
| ((DIV) == RCC_MCODIV_5)) |
| #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) |
| |
| #define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE) || ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \ |
| ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3) || \ |
| ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5) || \ |
| ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7) || \ |
| ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9) || \ |
| ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || \ |
| ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || \ |
| ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || \ |
| ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || \ |
| ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || \ |
| ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || \ |
| ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || \ |
| ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || \ |
| ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || \ |
| ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || \ |
| ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31)) |
| |
| |
| #define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDRIVE_LOW) || \ |
| ((DRIVE) == RCC_LSEDRIVE_MEDIUMLOW) || \ |
| ((DRIVE) == RCC_LSEDRIVE_MEDIUMHIGH) || \ |
| ((DRIVE) == RCC_LSEDRIVE_HIGH)) |
| /** |
| * @} |
| */ |
| |
| /** |
| * @} |
| */ |
| |
| /** |
| * @} |
| */ |
| |
| /** |
| * @} |
| */ |
| |
| #ifdef __cplusplus |
| } |
| #endif |
| |
| #endif /* __STM32F7xx_HAL_RCC_H */ |
| |
